Pull iommu updates from Joerg Roedel: "Core: - Support for RISC-V IO-page-table format in generic iommupt code ARM-SMMU Updates: - Introduction of an "invalidation array" for SMMUv3, which enables future scalability work and optimisations for devices with a large number of SMMUv3 instances - Update the conditions under which the SMMUv3 driver works around hardware errata for invalidation on MMU-700 implementations - Fix broken command filtering for the host view of NVIDIA's "cmdqv" SMMUv3 extension - MMU-500 device-tree binding additions for Qualcomm Eliza & Hawi SoCs Intel VT-d: - Support for dirty tracking on domains attached to PASID - Removal of unnecessary read*()/write*() wrappers - Improvements to the invalidation paths AMD Vi: - Race-condition fixed in debugfs code - Make log buffer allocation NUMA aware RISC-V: - IO-TLB flushing improvements - Minor fixes" * tag 'iommu-updates-v7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux: (48 commits) iommu/vt-d: Restore IOMMU_CAP_CACHE_COHERENCY dt-bindings: arm-smmu: qcom: Add compatible for Hawi SoC iommu/amd: Invalidate IRT cache for DMA aliases iommu/riscv: Remove overflows on the invalidation path iommu/amd: Fix clone_alias() to use the original device's devid iommu/vt-d: Remove the remaining pages along the invalidation path iommu/vt-d: Pass size_order to qi_desc_piotlb() not npages iommu/vt-d: Split piotlb invalidation into range and all iommu/vt-d: Remove dmar_writel() and dmar_writeq() iommu/vt-d: Remove dmar_readl() and dmar_readq() iommufd/selftest: Test dirty tracking on PASID iommu/vt-d: Support dirty tracking on PASID iommu/vt-d: Rename device_set_dirty_tracking() and pass dmar_domain pointer iommu/vt-d: Block PASID attachment to nested domain with dirty tracking iommu/dma: Always allow DMA-FQ when iommupt provides the iommu_domain iommu/riscv: Fix signedness bug iommu/amd: Fix illegal cap/mmio access in IOMMU debugfs iommu/amd: Fix illegal device-id access in IOMMU debugfs iommu/tegra241-cmdqv: Update uAPI to clarify HYP_OWN requirement iommu/tegra241-cmdqv: Set supports_cmd op in tegra241_vcmdq_hw_init() ...
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| @@ -695,11 +695,15 @@ enum iommu_hw_info_type { · 694 unmodified lines | |||
| 695 | * @IOMMU_HW_CAP_PCI_PASID_PRIV: Privileged Mode Supported, user ignores it | 695 | * @IOMMU_HW_CAP_PCI_PASID_PRIV: Privileged Mode Supported, user ignores it |
| 696 | * when the struct | 696 | * when the struct |
| 697 | * iommu_hw_info::out_max_pasid_log2 is zero. | 697 | * iommu_hw_info::out_max_pasid_log2 is zero. |
| 698 | * @IOMMU_HW_CAP_PCI_ATS_NOT_SUPPORTED: ATS is not supported or cannot be used | ||
| 699 | * on this device (absence implies ATS | ||
| 700 | * may be enabled) | ||
| 698 | */ | 701 | */ |
| 699 | enum iommufd_hw_capabilities { | 702 | enum iommufd_hw_capabilities { |
| 700 | IOMMU_HW_CAP_DIRTY_TRACKING = 1 << 0, | 703 | IOMMU_HW_CAP_DIRTY_TRACKING = 1 << 0, |
| 701 | IOMMU_HW_CAP_PCI_PASID_EXEC = 1 << 1, | 704 | IOMMU_HW_CAP_PCI_PASID_EXEC = 1 << 1, |
| 702 | IOMMU_HW_CAP_PCI_PASID_PRIV = 1 << 2, | 705 | IOMMU_HW_CAP_PCI_PASID_PRIV = 1 << 2, |
| 706 | IOMMU_HW_CAP_PCI_ATS_NOT_SUPPORTED = 1 << 3, | ||
| 703 | }; | 707 | }; |
| 704 | 708 | ||
| 705 | /** | 709 | /** |
| @@ -1052,6 +1056,11 @@ struct iommu_fault_alloc { · 346 unmodified lines | |||
| 1052 | enum iommu_viommu_type { | 1056 | enum iommu_viommu_type { |
| 1053 | IOMMU_VIOMMU_TYPE_DEFAULT = 0, | 1057 | IOMMU_VIOMMU_TYPE_DEFAULT = 0, |
| 1054 | IOMMU_VIOMMU_TYPE_ARM_SMMUV3 = 1, | 1058 | IOMMU_VIOMMU_TYPE_ARM_SMMUV3 = 1, |
| 1059 | /* | ||
| 1060 | * TEGRA241_CMDQV requirements (otherwise, VCMDQs will not work) | ||
| 1061 | * - Kernel will allocate a VINTF (HYP_OWN=0) to back this VIOMMU. So, | ||
| 1062 | * VMM must wire the HYP_OWN bit to 0 in guest VINTF_CONFIG register | ||
| 1063 | */ | ||
| 1055 | IOMMU_VIOMMU_TYPE_TEGRA241_CMDQV = 2, | 1064 | IOMMU_VIOMMU_TYPE_TEGRA241_CMDQV = 2, |
| 1056 | }; | 1065 | }; |
| 1057 | 1066 | ||