Pull irq fixes from Thomas Gleixner: "A set of interrupt chip driver fixes: - Ensure the atomicity of affinity updates in the GIC driver - Don't try to sleep in atomic context when waiting for the GICv4.1 to respond. Use polling instead. - Typo fixes in Kconfig and warnings" * tag 'irq-urgent-2020-07-05' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: irqchip/gic: Atomically update affinity irqchip/riscv-intc: Fix a typo in a pr_warn() irqchip/gic-v4.1: Use readx_poll_timeout_atomic() to fix sleep in atomic irqchip/loongson-pci-msi: Fix a typo in Kconfig
Unified · Split
| @@ -563,7 +563,7 @@ config LOONGSON_PCH_PIC · 562 unmodified lines | ||
| 563 | 563 | Support for the Loongson PCH PIC Controller. |
| 564 | 564 | |
| 565 | 565 | config LOONGSON_PCH_MSI |
| 566 | − bool "Loongson PCH PIC Controller" | |
| 566 | + bool "Loongson PCH MSI Controller" | |
| 567 | 567 | depends on MACH_LOONGSON64 || COMPILE_TEST |
| 568 | 568 | depends on PCI |
| 569 | 569 | default MACH_LOONGSON64 |
| @@ -3797,10 +3797,10 @@ static void its_wait_vpt_parse_complete(void) · 3796 unmodified lines | ||
| 3797 | 3797 | if (!gic_rdists->has_vpend_valid_dirty) |
| 3798 | 3798 | return; |
| 3799 | 3799 | |
| 3800 | − WARN_ON_ONCE(readq_relaxed_poll_timeout(vlpi_base + GICR_VPENDBASER, | |
| 3801 | − val, | |
| 3802 | − !(val & GICR_VPENDBASER_Dirty), | |
| 3803 | − 10, 500)); | |
| 3800 | + WARN_ON_ONCE(readq_relaxed_poll_timeout_atomic(vlpi_base + GICR_VPENDBASER, | |
| 3801 | + val, | |
| 3802 | + !(val & GICR_VPENDBASER_Dirty), | |
| 3803 | + 10, 500)); | |
| 3804 | 3804 | } |
| 3805 | 3805 | |
| 3806 | 3806 | static void its_vpe_schedule(struct its_vpe *vpe) |
| @@ -329,10 +329,8 @@ static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) · 328 unmodified lines | ||
| 329 | 329 | static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, |
| 330 | 330 | bool force) |
| 331 | 331 | { |
| 332 | − void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3); | |
| 333 | − unsigned int cpu, shift = (gic_irq(d) % 4) * 8; | |
| 334 | − u32 val, mask, bit; | |
| 335 | − unsigned long flags; | |
| 332 | + void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + gic_irq(d); | |
| 333 | + unsigned int cpu; | |
| 336 | 334 | |
| 337 | 335 | if (!force) |
| 338 | 336 | cpu = cpumask_any_and(mask_val, cpu_online_mask); |
| @@ -342,13 +340,7 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, · 3 unmodified lines | ||
| 342 | 340 | if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids) |
| 343 | 341 | return -EINVAL; |
| 344 | 342 | |
| 345 | − gic_lock_irqsave(flags); | |
| 346 | − mask = 0xff << shift; | |
| 347 | − bit = gic_cpu_map[cpu] << shift; | |
| 348 | − val = readl_relaxed(reg) & ~mask; | |
| 349 | − writel_relaxed(val | bit, reg); | |
| 350 | − gic_unlock_irqrestore(flags); | |
| 351 | − | |
| 343 | + writeb_relaxed(gic_cpu_map[cpu], reg); | |
| 352 | 344 | irq_data_update_effective_affinity(d, cpumask_of(cpu)); |
| 353 | 345 | |
| 354 | 346 | return IRQ_SET_MASK_OK_DONE; |
| @@ -99,7 +99,7 @@ static int __init riscv_intc_init(struct device_node *node, · 98 unmodified lines | ||
| 99 | 99 | |
| 100 | 100 | hartid = riscv_of_parent_hartid(node); |
| 101 | 101 | if (hartid < 0) { |
| 102 | − pr_warn("unable to fine hart id for %pOF\n", node); | |
| 102 | + pr_warn("unable to find hart id for %pOF\n", node); | |
| 103 | 103 | return 0; |
| 104 | 104 | } |
| 105 | 105 | |