Saeed Mahameed says: ==================== mlx5 fixes 2020-05-28 This series introduces some fixes to mlx5 driver. v1->v2: - Fix bad sha1, Jakub. - Added one more patch by Pablo. net/mlx5e: replace EINVAL in mlx5e_flower_parse_meta() Nothing major, the only patch worth mentioning is the suspend/resume crash fix by adding the missing pci device handlers, the fix is very straight forward and as Dexuan already expressed, the patch is important for Azure users to avoid crash on VM hibernation, patch is marked for -stable v4.6 below. Conflict note: ('net/mlx5e: Fix MLX5_TC_CT dependencies') has a trivial one line conflict with current net-next, which can be resolved by simply using the line from net-next. Please pull and let me know if there is any problem. For -stable v4.6 ('net/mlx5: Fix crash upon suspend/resume') For -stable v5.6 ('net/mlx5e: replace EINVAL in mlx5e_flower_parse_meta()') ====================
Unified · Split
| @@ -80,7 +80,7 @@ config MLX5_ESWITCH · 79 unmodified lines | |||
| 80 | 80 | ||
| 81 | config MLX5_TC_CT | 81 | config MLX5_TC_CT |
| 82 | bool "MLX5 TC connection tracking offload support" | 82 | bool "MLX5 TC connection tracking offload support" |
| 83 | depends on MLX5_CORE_EN && NET_SWITCHDEV && NF_FLOW_TABLE && NET_ACT_CT && NET_TC_SKB_EXT | 83 | depends on MLX5_ESWITCH && NF_FLOW_TABLE && NET_ACT_CT && NET_TC_SKB_EXT |
| 84 | default y | 84 | default y |
| 85 | help | 85 | help |
| 86 | Say Y here if you want to support offloading connection tracking rules | 86 | Say Y here if you want to support offloading connection tracking rules |
| @@ -1068,10 +1068,12 @@ void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv); · 1067 unmodified lines | |||
| 1068 | 1068 | ||
| 1069 | void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len, | 1069 | void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len, |
| 1070 | int num_channels); | 1070 | int num_channels); |
| 1071 | void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, | 1071 | |
| 1072 | u8 cq_period_mode); | 1072 | void mlx5e_reset_tx_moderation(struct mlx5e_params *params, u8 cq_period_mode); |
| 1073 | void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, | 1073 | void mlx5e_reset_rx_moderation(struct mlx5e_params *params, u8 cq_period_mode); |
| 1074 | u8 cq_period_mode); | 1074 | void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode); |
| 1075 | void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode); | ||
| 1076 | |||
| 1075 | void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params); | 1077 | void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params); |
| 1076 | void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev, | 1078 | void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev, |
| 1077 | struct mlx5e_params *params); | 1079 | struct mlx5e_params *params); |
| @@ -369,17 +369,19 @@ enum mlx5e_fec_supported_link_mode { · 368 unmodified lines | |||
| 369 | *_policy = MLX5_GET(pplm_reg, _buf, fec_override_admin_##link); \ | 369 | *_policy = MLX5_GET(pplm_reg, _buf, fec_override_admin_##link); \ |
| 370 | } while (0) | 370 | } while (0) |
| 371 | 371 | ||
| 372 | #define MLX5E_FEC_OVERRIDE_ADMIN_50G_POLICY(buf, policy, write, link) \ | 372 | #define MLX5E_FEC_OVERRIDE_ADMIN_50G_POLICY(buf, policy, write, link) \ |
| 373 | do { \ | 373 | do { \ |
| 374 | u16 *__policy = &(policy); \ | 374 | unsigned long policy_long; \ |
| 375 | bool _write = (write); \ | 375 | u16 *__policy = &(policy); \ |
| 376 | \ | 376 | bool _write = (write); \ |
| 377 | if (_write && *__policy) \ | 377 | \ |
| 378 | *__policy = find_first_bit((u_long *)__policy, \ | 378 | policy_long = *__policy; \ |
| 379 | sizeof(u16) * BITS_PER_BYTE);\ | 379 | if (_write && *__policy) \ |
| 380 | MLX5E_FEC_OVERRIDE_ADMIN_POLICY(buf, *__policy, _write, link); \ | 380 | *__policy = find_first_bit(&policy_long, \ |
| 381 | if (!_write && *__policy) \ | 381 | sizeof(policy_long) * BITS_PER_BYTE);\ |
| 382 | *__policy = 1 << *__policy; \ | 382 | MLX5E_FEC_OVERRIDE_ADMIN_POLICY(buf, *__policy, _write, link); \ |
| 383 | if (!_write && *__policy) \ | ||
| 384 | *__policy = 1 << *__policy; \ | ||
| 383 | } while (0) | 385 | } while (0) |
| 384 | 386 | ||
| 385 | /* get/set FEC admin field for a given speed */ | 387 | /* get/set FEC admin field for a given speed */ |
| @@ -527,8 +527,8 @@ int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv, · 526 unmodified lines | |||
| 527 | struct dim_cq_moder *rx_moder, *tx_moder; | 527 | struct dim_cq_moder *rx_moder, *tx_moder; |
| 528 | struct mlx5_core_dev *mdev = priv->mdev; | 528 | struct mlx5_core_dev *mdev = priv->mdev; |
| 529 | struct mlx5e_channels new_channels = {}; | 529 | struct mlx5e_channels new_channels = {}; |
| 530 | bool reset_rx, reset_tx; | ||
| 530 | int err = 0; | 531 | int err = 0; |
| 531 | bool reset; | ||
| 532 | 532 | ||
| 533 | if (!MLX5_CAP_GEN(mdev, cq_moderation)) | 533 | if (!MLX5_CAP_GEN(mdev, cq_moderation)) |
| 534 | return -EOPNOTSUPP; | 534 | return -EOPNOTSUPP; |
| @@ -566,15 +566,28 @@ int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv, · 31 unmodified lines | |||
| 566 | } | 566 | } |
| 567 | /* we are opened */ | 567 | /* we are opened */ |
| 568 | 568 | ||
| 569 | reset = (!!coal->use_adaptive_rx_coalesce != priv->channels.params.rx_dim_enabled) || | 569 | reset_rx = !!coal->use_adaptive_rx_coalesce != priv->channels.params.rx_dim_enabled; |
| 570 | (!!coal->use_adaptive_tx_coalesce != priv->channels.params.tx_dim_enabled); | 570 | reset_tx = !!coal->use_adaptive_tx_coalesce != priv->channels.params.tx_dim_enabled; |
| 571 | 571 | ||
| 572 | if (!reset) { | 572 | if (!reset_rx && !reset_tx) { |
| 573 | mlx5e_set_priv_channels_coalesce(priv, coal); | 573 | mlx5e_set_priv_channels_coalesce(priv, coal); |
| 574 | priv->channels.params = new_channels.params; | 574 | priv->channels.params = new_channels.params; |
| 575 | goto out; | 575 | goto out; |
| 576 | } | 576 | } |
| 577 | 577 | ||
| 578 | if (reset_rx) { | ||
| 579 | u8 mode = MLX5E_GET_PFLAG(&new_channels.params, | ||
| 580 | MLX5E_PFLAG_RX_CQE_BASED_MODER); | ||
| 581 | |||
| 582 | mlx5e_reset_rx_moderation(&new_channels.params, mode); | ||
| 583 | } | ||
| 584 | if (reset_tx) { | ||
| 585 | u8 mode = MLX5E_GET_PFLAG(&new_channels.params, | ||
| 586 | MLX5E_PFLAG_TX_CQE_BASED_MODER); | ||
| 587 | |||
| 588 | mlx5e_reset_tx_moderation(&new_channels.params, mode); | ||
| 589 | } | ||
| 590 | |||
| 578 | err = mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL); | 591 | err = mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL); |
| 579 | 592 | ||
| 580 | out: | 593 | out: |
| @@ -665,11 +678,12 @@ static const u32 pplm_fec_2_ethtool_linkmodes[] = { · 84 unmodified lines | |||
| 665 | static int get_fec_supported_advertised(struct mlx5_core_dev *dev, | 678 | static int get_fec_supported_advertised(struct mlx5_core_dev *dev, |
| 666 | struct ethtool_link_ksettings *link_ksettings) | 679 | struct ethtool_link_ksettings *link_ksettings) |
| 667 | { | 680 | { |
| 668 | u_long active_fec = 0; | 681 | unsigned long active_fec_long; |
| 682 | u32 active_fec; | ||
| 669 | u32 bitn; | 683 | u32 bitn; |
| 670 | int err; | 684 | int err; |
| 671 | 685 | ||
| 672 | err = mlx5e_get_fec_mode(dev, (u32 *)&active_fec, NULL); | 686 | err = mlx5e_get_fec_mode(dev, &active_fec, NULL); |
| 673 | if (err) | 687 | if (err) |
| 674 | return (err == -EOPNOTSUPP) ? 0 : err; | 688 | return (err == -EOPNOTSUPP) ? 0 : err; |
| 675 | 689 | ||
| @@ -682,10 +696,11 @@ static int get_fec_supported_advertised(struct mlx5_core_dev *dev, · 6 unmodified lines | |||
| 682 | MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_LLRS_272_257_1, | 696 | MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_LLRS_272_257_1, |
| 683 | ETHTOOL_LINK_MODE_FEC_LLRS_BIT); | 697 | ETHTOOL_LINK_MODE_FEC_LLRS_BIT); |
| 684 | 698 | ||
| 699 | active_fec_long = active_fec; | ||
| 685 | /* active fec is a bit set, find out which bit is set and | 700 | /* active fec is a bit set, find out which bit is set and |
| 686 | * advertise the corresponding ethtool bit | 701 | * advertise the corresponding ethtool bit |
| 687 | */ | 702 | */ |
| 688 | bitn = find_first_bit(&active_fec, sizeof(u32) * BITS_PER_BYTE); | 703 | bitn = find_first_bit(&active_fec_long, sizeof(active_fec_long) * BITS_PER_BYTE); |
| 689 | if (bitn < ARRAY_SIZE(pplm_fec_2_ethtool_linkmodes)) | 704 | if (bitn < ARRAY_SIZE(pplm_fec_2_ethtool_linkmodes)) |
| 690 | __set_bit(pplm_fec_2_ethtool_linkmodes[bitn], | 705 | __set_bit(pplm_fec_2_ethtool_linkmodes[bitn], |
| 691 | link_ksettings->link_modes.advertising); | 706 | link_ksettings->link_modes.advertising); |
| @@ -1517,8 +1532,8 @@ static int mlx5e_get_fecparam(struct net_device *netdev, · 825 unmodified lines | |||
| 1517 | { | 1532 | { |
| 1518 | struct mlx5e_priv *priv = netdev_priv(netdev); | 1533 | struct mlx5e_priv *priv = netdev_priv(netdev); |
| 1519 | struct mlx5_core_dev *mdev = priv->mdev; | 1534 | struct mlx5_core_dev *mdev = priv->mdev; |
| 1520 | u16 fec_configured = 0; | 1535 | u16 fec_configured; |
| 1521 | u32 fec_active = 0; | 1536 | u32 fec_active; |
| 1522 | int err; | 1537 | int err; |
| 1523 | 1538 | ||
| 1524 | err = mlx5e_get_fec_mode(mdev, &fec_active, &fec_configured); | 1539 | err = mlx5e_get_fec_mode(mdev, &fec_active, &fec_configured); |
| @@ -1526,14 +1541,14 @@ static int mlx5e_get_fecparam(struct net_device *netdev, · 1 unmodified line | |||
| 1526 | if (err) | 1541 | if (err) |
| 1527 | return err; | 1542 | return err; |
| 1528 | 1543 | ||
| 1529 | fecparam->active_fec = pplm2ethtool_fec((u_long)fec_active, | 1544 | fecparam->active_fec = pplm2ethtool_fec((unsigned long)fec_active, |
| 1530 | sizeof(u32) * BITS_PER_BYTE); | 1545 | sizeof(unsigned long) * BITS_PER_BYTE); |
| 1531 | 1546 | ||
| 1532 | if (!fecparam->active_fec) | 1547 | if (!fecparam->active_fec) |
| 1533 | return -EOPNOTSUPP; | 1548 | return -EOPNOTSUPP; |
| 1534 | 1549 | ||
| 1535 | fecparam->fec = pplm2ethtool_fec((u_long)fec_configured, | 1550 | fecparam->fec = pplm2ethtool_fec((unsigned long)fec_configured, |
| 1536 | sizeof(u16) * BITS_PER_BYTE); | 1551 | sizeof(unsigned long) * BITS_PER_BYTE); |
| 1537 | 1552 | ||
| 1538 | return 0; | 1553 | return 0; |
| 1539 | } | 1554 | } |
| @@ -4716,7 +4716,7 @@ static u8 mlx5_to_net_dim_cq_period_mode(u8 cq_period_mode) · 4715 unmodified lines | |||
| 4716 | DIM_CQ_PERIOD_MODE_START_FROM_EQE; | 4716 | DIM_CQ_PERIOD_MODE_START_FROM_EQE; |
| 4717 | } | 4717 | } |
| 4718 | 4718 | ||
| 4719 | void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode) | 4719 | void mlx5e_reset_tx_moderation(struct mlx5e_params *params, u8 cq_period_mode) |
| 4720 | { | 4720 | { |
| 4721 | if (params->tx_dim_enabled) { | 4721 | if (params->tx_dim_enabled) { |
| 4722 | u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode); | 4722 | u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode); |
| @@ -4725,13 +4725,9 @@ void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode) · 2 unmodified lines | |||
| 4725 | } else { | 4725 | } else { |
| 4726 | params->tx_cq_moderation = mlx5e_get_def_tx_moderation(cq_period_mode); | 4726 | params->tx_cq_moderation = mlx5e_get_def_tx_moderation(cq_period_mode); |
| 4727 | } | 4727 | } |
| 4728 | |||
| 4729 | MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER, | ||
| 4730 | params->tx_cq_moderation.cq_period_mode == | ||
| 4731 | MLX5_CQ_PERIOD_MODE_START_FROM_CQE); | ||
| 4732 | } | 4728 | } |
| 4733 | 4729 | ||
| 4734 | void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode) | 4730 | void mlx5e_reset_rx_moderation(struct mlx5e_params *params, u8 cq_period_mode) |
| 4735 | { | 4731 | { |
| 4736 | if (params->rx_dim_enabled) { | 4732 | if (params->rx_dim_enabled) { |
| 4737 | u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode); | 4733 | u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode); |
| @@ -4740,7 +4736,19 @@ void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode) · 2 unmodified lines | |||
| 4740 | } else { | 4736 | } else { |
| 4741 | params->rx_cq_moderation = mlx5e_get_def_rx_moderation(cq_period_mode); | 4737 | params->rx_cq_moderation = mlx5e_get_def_rx_moderation(cq_period_mode); |
| 4742 | } | 4738 | } |
| 4739 | } | ||
| 4740 | |||
| 4741 | void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode) | ||
| 4742 | { | ||
| 4743 | mlx5e_reset_tx_moderation(params, cq_period_mode); | ||
| 4744 | MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER, | ||
| 4745 | params->tx_cq_moderation.cq_period_mode == | ||
| 4746 | MLX5_CQ_PERIOD_MODE_START_FROM_CQE); | ||
| 4747 | } | ||
| 4743 | 4748 | ||
| 4749 | void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode) | ||
| 4750 | { | ||
| 4751 | mlx5e_reset_rx_moderation(params, cq_period_mode); | ||
| 4744 | MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER, | 4752 | MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER, |
| 4745 | params->rx_cq_moderation.cq_period_mode == | 4753 | params->rx_cq_moderation.cq_period_mode == |
| 4746 | MLX5_CQ_PERIOD_MODE_START_FROM_CQE); | 4754 | MLX5_CQ_PERIOD_MODE_START_FROM_CQE); |
| @@ -2068,7 +2068,7 @@ static int mlx5e_flower_parse_meta(struct net_device *filter_dev, · 2067 unmodified lines | |||
| 2068 | flow_rule_match_meta(rule, &match); | 2068 | flow_rule_match_meta(rule, &match); |
| 2069 | if (match.mask->ingress_ifindex != 0xFFFFFFFF) { | 2069 | if (match.mask->ingress_ifindex != 0xFFFFFFFF) { |
| 2070 | NL_SET_ERR_MSG_MOD(extack, "Unsupported ingress ifindex mask"); | 2070 | NL_SET_ERR_MSG_MOD(extack, "Unsupported ingress ifindex mask"); |
| 2071 | return -EINVAL; | 2071 | return -EOPNOTSUPP; |
| 2072 | } | 2072 | } |
| 2073 | 2073 | ||
| 2074 | ingress_dev = __dev_get_by_index(dev_net(filter_dev), | 2074 | ingress_dev = __dev_get_by_index(dev_net(filter_dev), |
| @@ -2076,13 +2076,13 @@ static int mlx5e_flower_parse_meta(struct net_device *filter_dev, · 1 unmodified line | |||
| 2076 | if (!ingress_dev) { | 2076 | if (!ingress_dev) { |
| 2077 | NL_SET_ERR_MSG_MOD(extack, | 2077 | NL_SET_ERR_MSG_MOD(extack, |
| 2078 | "Can't find the ingress port to match on"); | 2078 | "Can't find the ingress port to match on"); |
| 2079 | return -EINVAL; | 2079 | return -ENOENT; |
| 2080 | } | 2080 | } |
| 2081 | 2081 | ||
| 2082 | if (ingress_dev != filter_dev) { | 2082 | if (ingress_dev != filter_dev) { |
| 2083 | NL_SET_ERR_MSG_MOD(extack, | 2083 | NL_SET_ERR_MSG_MOD(extack, |
| 2084 | "Can't match on the ingress filter port"); | 2084 | "Can't match on the ingress filter port"); |
| 2085 | return -EINVAL; | 2085 | return -EOPNOTSUPP; |
| 2086 | } | 2086 | } |
| 2087 | 2087 | ||
| 2088 | return 0; | 2088 | return 0; |
| @@ -3849,10 +3849,6 @@ static int parse_tc_fdb_actions(struct mlx5e_priv *priv, · 1760 unmodified lines | |||
| 3849 | if (!mlx5e_is_valid_eswitch_fwd_dev(priv, out_dev)) { | 3849 | if (!mlx5e_is_valid_eswitch_fwd_dev(priv, out_dev)) { |
| 3850 | NL_SET_ERR_MSG_MOD(extack, | 3850 | NL_SET_ERR_MSG_MOD(extack, |
| 3851 | "devices are not on same switch HW, can't offload forwarding"); | 3851 | "devices are not on same switch HW, can't offload forwarding"); |
| 3852 | netdev_warn(priv->netdev, | ||
| 3853 | "devices %s %s not on same switch HW, can't offload forwarding\n", | ||
| 3854 | priv->netdev->name, | ||
| 3855 | out_dev->name); | ||
| 3856 | return -EOPNOTSUPP; | 3852 | return -EOPNOTSUPP; |
| 3857 | } | 3853 | } |
| 3858 | 3854 | ||
| @@ -4614,7 +4610,7 @@ void mlx5e_tc_stats_matchall(struct mlx5e_priv *priv, · 755 unmodified lines | |||
| 4614 | dpkts = cur_stats.rx_packets - rpriv->prev_vf_vport_stats.rx_packets; | 4610 | dpkts = cur_stats.rx_packets - rpriv->prev_vf_vport_stats.rx_packets; |
| 4615 | dbytes = cur_stats.rx_bytes - rpriv->prev_vf_vport_stats.rx_bytes; | 4611 | dbytes = cur_stats.rx_bytes - rpriv->prev_vf_vport_stats.rx_bytes; |
| 4616 | rpriv->prev_vf_vport_stats = cur_stats; | 4612 | rpriv->prev_vf_vport_stats = cur_stats; |
| 4617 | flow_stats_update(&ma->stats, dpkts, dbytes, jiffies, | 4613 | flow_stats_update(&ma->stats, dbytes, dpkts, jiffies, |
| 4618 | FLOW_ACTION_HW_STATS_DELAYED); | 4614 | FLOW_ACTION_HW_STATS_DELAYED); |
| 4619 | } | 4615 | } |
| 4620 | 4616 | ||
| @@ -1549,6 +1549,22 @@ static void shutdown(struct pci_dev *pdev) · 1548 unmodified lines | |||
| 1549 | mlx5_pci_disable_device(dev); | 1549 | mlx5_pci_disable_device(dev); |
| 1550 | } | 1550 | } |
| 1551 | 1551 | ||
| 1552 | static int mlx5_suspend(struct pci_dev *pdev, pm_message_t state) | ||
| 1553 | { | ||
| 1554 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | ||
| 1555 | |||
| 1556 | mlx5_unload_one(dev, false); | ||
| 1557 | |||
| 1558 | return 0; | ||
| 1559 | } | ||
| 1560 | |||
| 1561 | static int mlx5_resume(struct pci_dev *pdev) | ||
| 1562 | { | ||
| 1563 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | ||
| 1564 | |||
| 1565 | return mlx5_load_one(dev, false); | ||
| 1566 | } | ||
| 1567 | |||
| 1552 | static const struct pci_device_id mlx5_core_pci_table[] = { | 1568 | static const struct pci_device_id mlx5_core_pci_table[] = { |
| 1553 | { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) }, | 1569 | { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) }, |
| 1554 | { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */ | 1570 | { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */ |
| @@ -1592,6 +1608,8 @@ static struct pci_driver mlx5_core_driver = { · 37 unmodified lines | |||
| 1592 | .id_table = mlx5_core_pci_table, | 1608 | .id_table = mlx5_core_pci_table, |
| 1593 | .probe = init_one, | 1609 | .probe = init_one, |
| 1594 | .remove = remove_one, | 1610 | .remove = remove_one, |
| 1611 | .suspend = mlx5_suspend, | ||
| 1612 | .resume = mlx5_resume, | ||
| 1595 | .shutdown = shutdown, | 1613 | .shutdown = shutdown, |
| 1596 | .err_handler = &mlx5_err_handler, | 1614 | .err_handler = &mlx5_err_handler, |
| 1597 | .sriov_configure = mlx5_core_sriov_configure, | 1615 | .sriov_configure = mlx5_core_sriov_configure, |