We currently hardcode these in mesa, but querying them from the kernel makes more sense since there may be board specific limitations that the kernel driver is better suited to determining. Userpace patches that use this interface: https://gitlab.freedesktop.org/leoliu/drm/-/commits/info_video_caps https://gitlab.freedesktop.org/leoliu/mesa/-/commits/info_video_caps v2: reorder the codecs to better align with mesa v3: add max_pixels_per_frame to handle the portrait case, squash in memory leak fix v4: drop extra break
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| @@ -782,6 +782,12 @@ struct drm_amdgpu_cs_chunk_data { · 781 unmodified lines | |||
| 782 | #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F | 782 | #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F |
| 783 | /* query ras mask of enabled features*/ | 783 | /* query ras mask of enabled features*/ |
| 784 | #define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20 | 784 | #define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20 |
| 785 | /* query video encode/decode caps */ | ||
| 786 | #define AMDGPU_INFO_VIDEO_CAPS 0x21 | ||
| 787 | /* Subquery id: Decode */ | ||
| 788 | #define AMDGPU_INFO_VIDEO_CAPS_DECODE 0 | ||
| 789 | /* Subquery id: Encode */ | ||
| 790 | #define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1 | ||
| 785 | 791 | ||
| 786 | /* RAS MASK: UMC (VRAM) */ | 792 | /* RAS MASK: UMC (VRAM) */ |
| 787 | #define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0) | 793 | #define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0) |
| @@ -878,6 +884,10 @@ struct drm_amdgpu_info { · 90 unmodified lines | |||
| 878 | struct { | 884 | struct { |
| 879 | __u32 type; | 885 | __u32 type; |
| 880 | } sensor_info; | 886 | } sensor_info; |
| 887 | |||
| 888 | struct { | ||
| 889 | __u32 type; | ||
| 890 | } video_cap; | ||
| 881 | }; | 891 | }; |
| 882 | }; | 892 | }; |
| 883 | 893 | ||
| @@ -1074,6 +1084,30 @@ struct drm_amdgpu_info_vce_clock_table { · 190 unmodified lines | |||
| 1074 | __u32 pad; | 1084 | __u32 pad; |
| 1075 | }; | 1085 | }; |
| 1076 | 1086 | ||
| 1087 | /* query video encode/decode caps */ | ||
| 1088 | #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2 0 | ||
| 1089 | #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4 1 | ||
| 1090 | #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1 2 | ||
| 1091 | #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC 3 | ||
| 1092 | #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC 4 | ||
| 1093 | #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG 5 | ||
| 1094 | #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9 6 | ||
| 1095 | #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1 7 | ||
| 1096 | #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT 8 | ||
| 1097 | |||
| 1098 | struct drm_amdgpu_info_video_codec_info { | ||
| 1099 | __u32 valid; | ||
| 1100 | __u32 max_width; | ||
| 1101 | __u32 max_height; | ||
| 1102 | __u32 max_pixels_per_frame; | ||
| 1103 | __u32 max_level; | ||
| 1104 | __u32 pad; | ||
| 1105 | }; | ||
| 1106 | |||
| 1107 | struct drm_amdgpu_info_video_caps { | ||
| 1108 | struct drm_amdgpu_info_video_codec_info codec_info[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT]; | ||
| 1109 | }; | ||
| 1110 | |||
| 1077 | /* | 1111 | /* |
| 1078 | * Supported GPU families | 1112 | * Supported GPU families |
| 1079 | */ | 1113 | */ |