Merge tag 'arc-5.13-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc

Pull ARC fixes from Vineet Gupta: - PAE fixes - syscall num check off-by-one bug - misc fixes * tag 'arc-5.13-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: ARC: mm: Use max_high_pfn as a HIGHMEM zone border ARC: mm: PAE: use 40-bit physical page mask ARC: entry: fix off-by-one error in syscall number validation ARC: kgdb: add 'fallthrough' to prevent a warning arc: Fix typos/spellos

Linus Torvalds committed 5 years ago

Commit f36edc52 parents 8f4ae0f 1d5e46412 files · +41 −25Browse files

Unified · Split

12 files

arch/arc/Makefile +1 −1
arch/arc/include/asm/cmpxchg.h +2 −2
arch/arc/include/asm/page.h +12 −0
arch/arc/include/asm/pgtable.h +3 −9
arch/arc/include/uapi/asm/page.h +0 −1
arch/arc/kernel/entry.S +2 −2
arch/arc/kernel/kgdb.c +1 −0
arch/arc/kernel/process.c +4 −4
arch/arc/kernel/signal.c +2 −2
arch/arc/mm/init.c +10 −1
arch/arc/mm/ioremap.c +3 −2
arch/arc/mm/tlb.c +1 −1

arch/arc/Makefile+1−1

@@ -31,7 +31,7 @@ endif · 30 unmodified lines
31	31
32	32
33	33	ifdef CONFIG_ARC_CURR_IN_REG
34		−# For a global register defintion, make sure it gets passed to every file
	34	+# For a global register definition, make sure it gets passed to every file
35	35	# We had a customer reported bug where some code built in kernel was NOT using
36	36	# any kernel headers, and missing the r25 global register
37	37	# Can't do unconditionally because of recursive include issues

arch/arc/include/asm/cmpxchg.h+2−2

@@ -116,7 +116,7 @@ static inline unsigned long __xchg(unsigned long val, volatile void *ptr, · 115 unmodified lines
116	116	*
117	117	* Technically the lock is also needed for UP (boils down to irq save/restore)
118	118	* but we can cheat a bit since cmpxchg() atomic_ops_lock() would cause irqs to
119		− * be disabled thus can't possibly be interrpted/preempted/clobbered by xchg()
	119	+ * be disabled thus can't possibly be interrupted/preempted/clobbered by xchg()
120	120	* Other way around, xchg is one instruction anyways, so can't be interrupted
121	121	* as such
122	122	*/
@@ -143,7 +143,7 @@ static inline unsigned long __xchg(unsigned long val, volatile void *ptr, · 20 unmodified lines
143	143	/*
144	144	* "atomic" variant of xchg()
145	145	* REQ: It needs to follow the same serialization rules as other atomic_xxx()
146		− * Since xchg() doesn't always do that, it would seem that following defintion
	146	+ * Since xchg() doesn't always do that, it would seem that following definition
147	147	* is incorrect. But here's the rationale:
148	148	* SMP : Even xchg() takes the atomic_ops_lock, so OK.
149	149	* LLSC: atomic_ops_lock are not relevant at all (even if SMP, since LLSC

arch/arc/include/asm/page.h+12−0

@@ -7,6 +7,18 @@ · 6 unmodified lines
7	7
8	8	#include <uapi/asm/page.h>
9	9
	10	+#ifdef CONFIG_ARC_HAS_PAE40
	11	+
	12	+#define MAX_POSSIBLE_PHYSMEM_BITS 40
	13	+#define PAGE_MASK_PHYS (0xff00000000ull \| PAGE_MASK)
	14	+
	15	+#else /* CONFIG_ARC_HAS_PAE40 */
	16	+
	17	+#define MAX_POSSIBLE_PHYSMEM_BITS 32
	18	+#define PAGE_MASK_PHYS PAGE_MASK
	19	+
	20	+#endif /* CONFIG_ARC_HAS_PAE40 */
	21	+
10	22	#ifndef __ASSEMBLY__
11	23
12	24	#define clear_page(paddr) memset((paddr), 0, PAGE_SIZE)

arch/arc/include/asm/pgtable.h+3−9

@@ -107,8 +107,8 @@ · 106 unmodified lines
107	107	#define ___DEF (_PAGE_PRESENT \| _PAGE_CACHEABLE)
108	108
109	109	/* Set of bits not changed in pte_modify */
110		−#define _PAGE_CHG_MASK (PAGE_MASK \| _PAGE_ACCESSED \| _PAGE_DIRTY \| _PAGE_SPECIAL)
111		−
	110	+#define _PAGE_CHG_MASK (PAGE_MASK_PHYS \| _PAGE_ACCESSED \| _PAGE_DIRTY \| \
	111	+ _PAGE_SPECIAL)
112	112	/* More Abbrevaited helpers */
113	113	#define PAGE_U_NONE __pgprot(___DEF)
114	114	#define PAGE_U_R __pgprot(___DEF \| _PAGE_READ)
@@ -132,13 +132,7 @@ · 17 unmodified lines
132	132	#define PTE_BITS_IN_PD0 (_PAGE_GLOBAL \| _PAGE_PRESENT \| _PAGE_HW_SZ)
133	133	#define PTE_BITS_RWX (_PAGE_EXECUTE \| _PAGE_WRITE \| _PAGE_READ)
134	134
135		−#ifdef CONFIG_ARC_HAS_PAE40
136		−#define PTE_BITS_NON_RWX_IN_PD1 (0xff00000000 \| PAGE_MASK \| _PAGE_CACHEABLE)
137		−#define MAX_POSSIBLE_PHYSMEM_BITS 40
138		−#else
139		−#define PTE_BITS_NON_RWX_IN_PD1 (PAGE_MASK \| _PAGE_CACHEABLE)
140		−#define MAX_POSSIBLE_PHYSMEM_BITS 32
141		−#endif
	135	+#define PTE_BITS_NON_RWX_IN_PD1 (PAGE_MASK_PHYS \| _PAGE_CACHEABLE)
142	136
143	137	/**************************************************************************
144	138	* Mapping of vm_flags (Generic VM) to PTE flags (arch specific)

arch/arc/include/uapi/asm/page.h+0−1

@@ -33,5 +33,4 @@ · 32 unmodified lines
33	33
34	34	#define PAGE_MASK (~(PAGE_SIZE-1))
35	35
36		−
37	36	#endif /* _UAPI__ASM_ARC_PAGE_H */

arch/arc/kernel/entry.S+2−2

@@ -177,7 +177,7 @@ tracesys: · 176 unmodified lines
177	177
178	178	; Do the Sys Call as we normally would.
179	179	; Validate the Sys Call number
180		− cmp r8, NR_syscalls
	180	+ cmp r8, NR_syscalls - 1
181	181	mov.hi r0, -ENOSYS
182	182	bhi tracesys_exit
183	183
@@ -255,7 +255,7 @@ ENTRY(EV_Trap) · 71 unmodified lines
255	255	;============ Normal syscall case
256	256
257	257	; syscall num shd not exceed the total system calls avail
258		− cmp r8, NR_syscalls
	258	+ cmp r8, NR_syscalls - 1
259	259	mov.hi r0, -ENOSYS
260	260	bhi .Lret_from_system_call
261	261

arch/arc/kernel/kgdb.c+1−0

@@ -140,6 +140,7 @@ int kgdb_arch_handle_exception(int e_vector, int signo, int err_code, · 139 unmodified lines
140	140	ptr = &remcomInBuffer[1];
141	141	if (kgdb_hex2long(&ptr, &addr))
142	142	regs->ret = addr;
	143	+ fallthrough;
143	144
144	145	case 'D':
145	146	case 'k':

arch/arc/kernel/process.c+4−4

@@ -50,14 +50,14 @@ SYSCALL_DEFINE3(arc_usr_cmpxchg, int *, uaddr, int, expected, int, new) · 49 unmodified lines
50	50	int ret;
51	51
52	52	/*
53		− * This is only for old cores lacking LLOCK/SCOND, which by defintion
	53	+ * This is only for old cores lacking LLOCK/SCOND, which by definition
54	54	* can't possibly be SMP. Thus doesn't need to be SMP safe.
55	55	* And this also helps reduce the overhead for serializing in
56	56	* the UP case
57	57	*/
58	58	WARN_ON_ONCE(IS_ENABLED(CONFIG_SMP));
59	59
60		− /* Z indicates to userspace if operation succeded */
	60	+ /* Z indicates to userspace if operation succeeded */
61	61	regs->status32 &= ~STATUS_Z_MASK;
62	62
63	63	ret = access_ok(uaddr, sizeof(*uaddr));
@@ -107,7 +107,7 @@ fail: · 43 unmodified lines
107	107
108	108	void arch_cpu_idle(void)
109	109	{
110		− /* Re-enable interrupts <= default irq priority before commiting SLEEP */
	110	+ /* Re-enable interrupts <= default irq priority before committing SLEEP */
111	111	const unsigned int arg = 0x10 \| ARCV2_IRQ_DEF_PRIO;
112	112
113	113	__asm__ __volatile__(
@@ -120,7 +120,7 @@ void arch_cpu_idle(void) · 6 unmodified lines
120	120
121	121	void arch_cpu_idle(void)
122	122	{
123		− /* sleep, but enable both set E1/E2 (levels of interrutps) before committing */
	123	+ /* sleep, but enable both set E1/E2 (levels of interrupts) before committing */
124	124	__asm__ __volatile__("sleep 0x3 \n");
125	125	}
126	126

arch/arc/kernel/signal.c+2−2

@@ -259,7 +259,7 @@ setup_rt_frame(struct ksignal ksig, sigset_t set, struct pt_regs *regs) · 258 unmodified lines
259	259	regs->r2 = (unsigned long)&sf->uc;
260	260
261	261	/*
262		− * small optim to avoid unconditonally calling do_sigaltstack
	262	+ * small optim to avoid unconditionally calling do_sigaltstack
263	263	* in sigreturn path, now that we only have rt_sigreturn
264	264	*/
265	265	magic = MAGIC_SIGALTSTK;
@@ -391,7 +391,7 @@ void do_signal(struct pt_regs *regs) · 125 unmodified lines
391	391	void do_notify_resume(struct pt_regs *regs)
392	392	{
393	393	/*
394		− * ASM glue gaurantees that this is only called when returning to
	394	+ * ASM glue guarantees that this is only called when returning to
395	395	* user mode
396	396	*/
397	397	if (test_thread_flag(TIF_NOTIFY_RESUME))

arch/arc/mm/init.c+10−1

@@ -157,7 +157,16 @@ void __init setup_arch_memory(void) · 156 unmodified lines
157	157	min_high_pfn = PFN_DOWN(high_mem_start);
158	158	max_high_pfn = PFN_DOWN(high_mem_start + high_mem_sz);
159	159
160		− max_zone_pfn[ZONE_HIGHMEM] = min_low_pfn;
	160	+ /*
	161	+ * max_high_pfn should be ok here for both HIGHMEM and HIGHMEM+PAE.
	162	+ * For HIGHMEM without PAE max_high_pfn should be less than
	163	+ * min_low_pfn to guarantee that these two regions don't overlap.
	164	+ * For PAE case highmem is greater than lowmem, so it is natural
	165	+ * to use max_high_pfn.
	166	+ *
	167	+ * In both cases, holes should be handled by pfn_valid().
	168	+ */
	169	+ max_zone_pfn[ZONE_HIGHMEM] = max_high_pfn;
161	170
162	171	high_memory = (void *)(min_high_pfn << PAGE_SHIFT);
163	172

arch/arc/mm/ioremap.c+3−2

@@ -53,9 +53,10 @@ EXPORT_SYMBOL(ioremap); · 52 unmodified lines
53	53	void __iomem *ioremap_prot(phys_addr_t paddr, unsigned long size,
54	54	unsigned long flags)
55	55	{
	56	+ unsigned int off;
56	57	unsigned long vaddr;
57	58	struct vm_struct *area;
58		− phys_addr_t off, end;
	59	+ phys_addr_t end;
59	60	pgprot_t prot = __pgprot(flags);
60	61
61	62	/* Don't allow wraparound, zero size */
@@ -72,7 +73,7 @@ void __iomem *ioremap_prot(phys_addr_t paddr, unsigned long size, · 10 unmodified lines
72	73
73	74	/* Mappings have to be page-aligned */
74	75	off = paddr & ~PAGE_MASK;
75		− paddr &= PAGE_MASK;
	76	+ paddr &= PAGE_MASK_PHYS;
76	77	size = PAGE_ALIGN(end + 1) - paddr;
77	78
78	79	/*

arch/arc/mm/tlb.c+1−1

@@ -576,7 +576,7 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddr_unaligned, · 575 unmodified lines
576	576	pte_t *ptep)
577	577	{
578	578	unsigned long vaddr = vaddr_unaligned & PAGE_MASK;
579		− phys_addr_t paddr = pte_val(*ptep) & PAGE_MASK;
	579	+ phys_addr_t paddr = pte_val(*ptep) & PAGE_MASK_PHYS;
580	580	struct page page = pfn_to_page(pte_pfn(ptep));
581	581
582	582	create_tlb(vma, vaddr, ptep);