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Merge tag 'arc-5.18-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc

Pull ARC fixes from Vineet Gupta: - Assorted fixes * tag 'arc-5.18-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: ARC: remove redundant READ_ONCE() in cmpxchg loop ARC: atomic: cleanup atomic-llsc definitions arc: drop definitions of pgd_index() and pgd_offset{, _k}() entirely ARC: dts: align SPI NOR node name with dtschema ARC: Remove a redundant memset() ARC: fix typos in comments ARC: entry: fix syscall_trace_exit argument

Linus Torvalds committed 4 years ago

Commit f3935922 parents 6fc2586 c6ed4d89 files · +24 −27Browse files

Unified · Split

9 files
  1. arch/arc/boot/dts/hsdk.dts +1 −1
  2. arch/arc/include/asm/atomic-llsc.h +16 −16
  3. arch/arc/include/asm/pgtable-levels.h +0 −3
  4. arch/arc/kernel/disasm.c +1 −2
  5. arch/arc/kernel/entry.S +1 −0
  6. arch/arc/kernel/signal.c +1 −1
  7. arch/arc/kernel/smp.c +2 −2
  8. arch/arc/kernel/unaligned.c +1 −1
  9. arch/arc/mm/cache.c +1 −1
arch/arc/boot/dts/hsdk.dts+1−1
@@ -275,7 +275,7 @@ · 274 unmodified lines
275 cs-gpios = <&creg_gpio 0 GPIO_ACTIVE_LOW>,275 cs-gpios = <&creg_gpio 0 GPIO_ACTIVE_LOW>,
276 <&creg_gpio 1 GPIO_ACTIVE_LOW>;276 <&creg_gpio 1 GPIO_ACTIVE_LOW>;
277 277
278 spi-flash@0 {278 flash@0 {
279 compatible = "sst26wf016b", "jedec,spi-nor";279 compatible = "sst26wf016b", "jedec,spi-nor";
280 reg = <0>;280 reg = <0>;
281 #address-cells = <1>;281 #address-cells = <1>;
arch/arc/include/asm/atomic-llsc.h+16−16
@@ -5,7 +5,7 @@ · 4 unmodified lines
5 5
6#define arch_atomic_set(v, i) WRITE_ONCE(((v)->counter), (i))6#define arch_atomic_set(v, i) WRITE_ONCE(((v)->counter), (i))
7 7
8#define ATOMIC_OP(op, c_op, asm_op) \8#define ATOMIC_OP(op, asm_op) \
9static inline void arch_atomic_##op(int i, atomic_t *v) \9static inline void arch_atomic_##op(int i, atomic_t *v) \
10{ \10{ \
11 unsigned int val; \11 unsigned int val; \
@@ -21,7 +21,7 @@ static inline void arch_atomic_##op(int i, atomic_t *v) \ · 9 unmodified lines
21 : "cc"); \21 : "cc"); \
22} \22} \
23 23
24#define ATOMIC_OP_RETURN(op, c_op, asm_op) \24#define ATOMIC_OP_RETURN(op, asm_op) \
25static inline int arch_atomic_##op##_return_relaxed(int i, atomic_t *v) \25static inline int arch_atomic_##op##_return_relaxed(int i, atomic_t *v) \
26{ \26{ \
27 unsigned int val; \27 unsigned int val; \
@@ -42,7 +42,7 @@ static inline int arch_atomic_##op##_return_relaxed(int i, atomic_t *v) \ · 14 unmodified lines
42#define arch_atomic_add_return_relaxed arch_atomic_add_return_relaxed42#define arch_atomic_add_return_relaxed arch_atomic_add_return_relaxed
43#define arch_atomic_sub_return_relaxed arch_atomic_sub_return_relaxed43#define arch_atomic_sub_return_relaxed arch_atomic_sub_return_relaxed
44 44
45#define ATOMIC_FETCH_OP(op, c_op, asm_op) \45#define ATOMIC_FETCH_OP(op, asm_op) \
46static inline int arch_atomic_fetch_##op##_relaxed(int i, atomic_t *v) \46static inline int arch_atomic_fetch_##op##_relaxed(int i, atomic_t *v) \
47{ \47{ \
48 unsigned int val, orig; \48 unsigned int val, orig; \
@@ -69,23 +69,23 @@ static inline int arch_atomic_fetch_##op##_relaxed(int i, atomic_t *v) \ · 20 unmodified lines
69#define arch_atomic_fetch_or_relaxed arch_atomic_fetch_or_relaxed69#define arch_atomic_fetch_or_relaxed arch_atomic_fetch_or_relaxed
70#define arch_atomic_fetch_xor_relaxed arch_atomic_fetch_xor_relaxed70#define arch_atomic_fetch_xor_relaxed arch_atomic_fetch_xor_relaxed
71 71
72#define ATOMIC_OPS(op, c_op, asm_op) \72#define ATOMIC_OPS(op, asm_op) \
73 ATOMIC_OP(op, c_op, asm_op) \73 ATOMIC_OP(op, asm_op) \
74 ATOMIC_OP_RETURN(op, c_op, asm_op) \74 ATOMIC_OP_RETURN(op, asm_op) \
75 ATOMIC_FETCH_OP(op, c_op, asm_op)75 ATOMIC_FETCH_OP(op, asm_op)
76 76
77ATOMIC_OPS(add, +=, add)77ATOMIC_OPS(add, add)
78ATOMIC_OPS(sub, -=, sub)78ATOMIC_OPS(sub, sub)
79 79
80#undef ATOMIC_OPS80#undef ATOMIC_OPS
81#define ATOMIC_OPS(op, c_op, asm_op) \81#define ATOMIC_OPS(op, asm_op) \
82 ATOMIC_OP(op, c_op, asm_op) \82 ATOMIC_OP(op, asm_op) \
83 ATOMIC_FETCH_OP(op, c_op, asm_op)83 ATOMIC_FETCH_OP(op, asm_op)
84 84
85ATOMIC_OPS(and, &=, and)85ATOMIC_OPS(and, and)
86ATOMIC_OPS(andnot, &= ~, bic)86ATOMIC_OPS(andnot, bic)
87ATOMIC_OPS(or, |=, or)87ATOMIC_OPS(or, or)
88ATOMIC_OPS(xor, ^=, xor)88ATOMIC_OPS(xor, xor)
89 89
90#define arch_atomic_andnot arch_atomic_andnot90#define arch_atomic_andnot arch_atomic_andnot
91 91
arch/arc/include/asm/pgtable-levels.h+0−3
@@ -98,9 +98,6 @@ · 97 unmodified lines
98/*98/*
99 * 1st level paging: pgd99 * 1st level paging: pgd
100 */100 */
101#define pgd_index(addr) ((addr) >> PGDIR_SHIFT)
102#define pgd_offset(mm, addr) (((mm)->pgd) + pgd_index(addr))
103#define pgd_offset_k(addr) pgd_offset(&init_mm, addr)
104#define pgd_ERROR(e) \101#define pgd_ERROR(e) \
105 pr_crit("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))102 pr_crit("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
106 103
arch/arc/kernel/disasm.c+1−2
@@ -366,7 +366,7 @@ void __kprobes disasm_instr(unsigned long addr, struct disasm_state *state, · 365 unmodified lines
366 case op_SP: /* LD_S|LDB_S b,[sp,u7], ST_S|STB_S b,[sp,u7] */366 case op_SP: /* LD_S|LDB_S b,[sp,u7], ST_S|STB_S b,[sp,u7] */
367 /* note: we are ignoring possibility of:367 /* note: we are ignoring possibility of:
368 * ADD_S, SUB_S, PUSH_S, POP_S as these should not368 * ADD_S, SUB_S, PUSH_S, POP_S as these should not
369 * cause unaliged exception anyway */369 * cause unaligned exception anyway */
370 state->write = BITS(state->words[0], 6, 6);370 state->write = BITS(state->words[0], 6, 6);
371 state->zz = BITS(state->words[0], 5, 5);371 state->zz = BITS(state->words[0], 5, 5);
372 if (state->zz)372 if (state->zz)
@@ -503,7 +503,6 @@ int __kprobes disasm_next_pc(unsigned long pc, struct pt_regs *regs, · 130 unmodified lines
503{503{
504 struct disasm_state instr;504 struct disasm_state instr;
505 505
506 memset(&instr, 0, sizeof(struct disasm_state));
507 disasm_instr(pc, &instr, 0, regs, cregs);506 disasm_instr(pc, &instr, 0, regs, cregs);
508 507
509 *next_pc = pc + instr.instr_len;508 *next_pc = pc + instr.instr_len;
arch/arc/kernel/entry.S+1−0
@@ -196,6 +196,7 @@ tracesys_exit: · 195 unmodified lines
196 st r0, [sp, PT_r0] ; sys call return value in pt_regs196 st r0, [sp, PT_r0] ; sys call return value in pt_regs
197 197
198 ;POST Sys Call Ptrace Hook198 ;POST Sys Call Ptrace Hook
199 mov r0, sp ; pt_regs needed
199 bl @syscall_trace_exit200 bl @syscall_trace_exit
200 b ret_from_exception ; NOT ret_from_system_call at is saves r0 which201 b ret_from_exception ; NOT ret_from_system_call at is saves r0 which
201 ; we'd done before calling post hook above202 ; we'd done before calling post hook above
arch/arc/kernel/signal.c+1−1
@@ -319,7 +319,7 @@ setup_rt_frame(struct ksignal *ksig, sigset_t *set, struct pt_regs *regs) · 318 unmodified lines
319 regs->ret = (unsigned long)ksig->ka.sa.sa_handler;319 regs->ret = (unsigned long)ksig->ka.sa.sa_handler;
320 320
321 /*321 /*
322 * handler returns using sigreturn stub provided already by userpsace322 * handler returns using sigreturn stub provided already by userspace
323 * If not, nuke the process right away323 * If not, nuke the process right away
324 */324 */
325 if(!(ksig->ka.sa.sa_flags & SA_RESTORER))325 if(!(ksig->ka.sa.sa_flags & SA_RESTORER))
arch/arc/kernel/smp.c+2−2
@@ -35,7 +35,7 @@ EXPORT_SYMBOL_GPL(smp_atomic_ops_lock); · 34 unmodified lines
35 35
36struct plat_smp_ops __weak plat_smp_ops;36struct plat_smp_ops __weak plat_smp_ops;
37 37
38/* XXX: per cpu ? Only needed once in early seconday boot */38/* XXX: per cpu ? Only needed once in early secondary boot */
39struct task_struct *secondary_idle_tsk;39struct task_struct *secondary_idle_tsk;
40 40
41/* Called from start_kernel */41/* Called from start_kernel */
@@ -274,7 +274,7 @@ static void ipi_send_msg_one(int cpu, enum ipi_msg_type msg) · 232 unmodified lines
274 * and read back old value274 * and read back old value
275 */275 */
276 do {276 do {
277 new = old = READ_ONCE(*ipi_data_ptr);277 new = old = *ipi_data_ptr;
278 new |= 1U << msg;278 new |= 1U << msg;
279 } while (cmpxchg(ipi_data_ptr, old, new) != old);279 } while (cmpxchg(ipi_data_ptr, old, new) != old);
280 280
arch/arc/kernel/unaligned.c+1−1
@@ -237,7 +237,7 @@ int misaligned_fixup(unsigned long address, struct pt_regs *regs, · 236 unmodified lines
237 if (state.fault)237 if (state.fault)
238 goto fault;238 goto fault;
239 239
240 /* clear any remanants of delay slot */240 /* clear any remnants of delay slot */
241 if (delay_mode(regs)) {241 if (delay_mode(regs)) {
242 regs->ret = regs->bta & ~1U;242 regs->ret = regs->bta & ~1U;
243 regs->status32 &= ~STATUS_DE_MASK;243 regs->status32 &= ~STATUS_DE_MASK;
arch/arc/mm/cache.c+1−1
@@ -401,7 +401,7 @@ static inline void __before_dc_op(const int op) · 400 unmodified lines
401{401{
402 if (op == OP_FLUSH_N_INV) {402 if (op == OP_FLUSH_N_INV) {
403 /* Dcache provides 2 cmd: FLUSH or INV403 /* Dcache provides 2 cmd: FLUSH or INV
404 * INV inturn has sub-modes: DISCARD or FLUSH-BEFORE404 * INV in turn has sub-modes: DISCARD or FLUSH-BEFORE
405 * flush-n-inv is achieved by INV cmd but with IM=1405 * flush-n-inv is achieved by INV cmd but with IM=1
406 * So toggle INV sub-mode depending on op request and default406 * So toggle INV sub-mode depending on op request and default
407 */407 */

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