History

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd: "There are a few changes to the core framework this time around, in addition to the normal collection of driver updates to support new SoCs, fix incorrect data, and convert various drivers to clk_hw based APIs. In the core, we allow clk_ops::init() to return an error code now so that we can fail clk registration if the callback does something like fail to allocate memory. We also add a new "terminate" clk_op so that things done in clk_ops::init() can be undone, e.g. free memory. We also spit out a warning now when critical clks fail to enable and we support changing clk rates and enable/disable state through debugfs when developers compile the kernel themselves. On the driver front, we get support for what seems like a lot of Qualcomm and NXP SoCs given that those vendors dominate the diffstat. There are a couple new drivers for Xilinx and Amlogic SoCs too. The updates are all small things like fixing the way glitch free muxes switch parents, avoiding div-by-zero problems, or fixing data like parent names. See the updates section below for more details. Finally, the "basic" clk types have been converted to support specifying parents with clk_hw pointers. This work includes an overhaul of the fixed-rate clk type to be more modern by using clk_hw APIs. Core: - Let clk_ops::init() return an error code - Add a clk_ops::terminate() callback to undo clk_ops::init() - Warn about critical clks that fail to enable or prepare - Support dangerous debugfs actions on clks with dead code New Drivers: - Support for Xilinx Versal platform clks - Display clk controller on qcom sc7180 - Video clk controller on qcom sc7180 - Graphics clk controller on qcom sc7180 - CPU PLLs for qcom msm8916 - Move qcom msm8974 gfx3d clk to RPM control - Display port clk support on qcom sdm845 SoCs - Global clk controller on qcom ipq6018 - Add a driver for BCLK of Freescale SAI cores - Add cam, vpe and sgx clock support for TI dra7 - Add aess clock support for TI omap5 - Enable clks for CPUfreq on Allwinner A64 SoCs - Add Amlogic meson8b DDR clock controller - Add input clocks to Amlogic meson8b controllers - Add SPIBSC (SPI FLASH) clock on Renesas RZ/A2 - i.MX8MP clk driver support Updates: - Convert gpio, fixed-factor, mux, gate, divider basic clks to hw based APIs - Detect more PRMCU variants in ux500 driver - Adjust the composite clk type to new way of describing clk parents - Fixes for clk controllers on qcom msm8998 SoCs - Fix gmac main clock for TI dra7 - Move TI dra7-atl clock header to correct location - Fix hidden node name dependency on TI clkctrl clocks - Fix Amlogic meson8b mali clock update using the glitch free mux - Fix Amlogic pll driver division by zero at init - Prepare for split of Renesas R-Car H3 ES1.x and ES2.0+ config symbols - Switch more i.MX clk drivers to clk_hw based APIs - Disable non-functional divider between pll4_audio_div and pll4_post_div on imx6q - Fix watchdog2 clock name typo in imx7ulp clock driver - Set CLK_GET_RATE_NOCACHE flag for DRAM related clocks on i.MX8M SoCs - Suppress bind attrs for i.MX8M clock driver - Add a big comment in imx8qxp-lpcg driver to tell why devm_platform_ioremap_resource() shouldn't be used for the driver - A correction on i.MX8MN usb1_ctrl parent clock setting" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (140 commits) dt/bindings: clk: fsl,plldig: Drop 'bindings' from schema id clk: ls1028a: Fix warning on clamp() usage clk: qoriq: add ls1088a hwaccel clocks support clk: ls1028a: Add clock driver for Display output interface dt/bindings: clk: Add YAML schemas for LS1028A Display Clock bindings clk: fsl-sai: new driver dt-bindings: clock: document the fsl-sai driver clk: composite: add _register_composite_pdata() variants clk: qcom: rpmh: Sort OF match table dt-bindings: fix warnings in validation of qcom,gcc.yaml dt-binding: fix compilation error of the example in qcom,gcc.yaml clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flag clk: zynqmp: Fix divider calculation clk: zynqmp: Add support for get max divider clk: zynqmp: Warn user if clock user are more than allowed clk: zynqmp: Extend driver for versal dt-bindings: clock: Add bindings for versal clock driver clk: ti: clkctrl: Fix hidden dependency to node name clk: ti: add clkctrl data dra7 sgx clk: ti: omap5: Add missing AESS clock ...

Linus Torvalds committed 6 years ago

Commit f4a63652 parents fe70da5 fc6a15c146 files · +15018 −1806Browse files

Showing the changes to include/linux (3 of 146 files). Show all

Unified · Split

3 files
  1. include/linux/clk-provider.h +359 −85
  2. include/linux/clk.h +3 −0
  3. include/linux/firmware/xlnx-zynqmp.h +2 −0
include/linux/clk-provider.h+359−85
@@ -190,8 +190,14 @@ struct clk_duty { · 189 unmodified lines
190 *190 *
191 * @init: Perform platform-specific initialization magic.191 * @init: Perform platform-specific initialization magic.
192 * This is not not used by any of the basic clock types.192 * This is not not used by any of the basic clock types.
193 * Please consider other ways of solving initialization problems193 * This callback exist for HW which needs to perform some
194 * before using this callback, as its use is discouraged.194 * initialisation magic for CCF to get an accurate view of the
195 * clock. It may also be used dynamic resource allocation is
196 * required. It shall not used to deal with clock parameters,
197 * such as rate or parents.
198 * Returns 0 on success, -EERROR otherwise.
199 *
200 * @terminate: Free any resource allocated by init.
195 *201 *
196 * @debug_init: Set up type-specific debugfs entries for this clock. This202 * @debug_init: Set up type-specific debugfs entries for this clock. This
197 * is called once, after the debugfs directory entry for this203 * is called once, after the debugfs directory entry for this
@@ -243,7 +249,8 @@ struct clk_ops { · 45 unmodified lines
243 struct clk_duty *duty);249 struct clk_duty *duty);
244 int (*set_duty_cycle)(struct clk_hw *hw,250 int (*set_duty_cycle)(struct clk_hw *hw,
245 struct clk_duty *duty);251 struct clk_duty *duty);
246 void (*init)(struct clk_hw *hw);252 int (*init)(struct clk_hw *hw);
253 void (*terminate)(struct clk_hw *hw);
247 void (*debug_init)(struct clk_hw *hw, struct dentry *dentry);254 void (*debug_init)(struct clk_hw *hw, struct dentry *dentry);
248};255};
249 256
@@ -321,29 +328,119 @@ struct clk_hw { · 71 unmodified lines
321 * struct clk_fixed_rate - fixed-rate clock328 * struct clk_fixed_rate - fixed-rate clock
322 * @hw: handle between common and hardware-specific interfaces329 * @hw: handle between common and hardware-specific interfaces
323 * @fixed_rate: constant frequency of clock330 * @fixed_rate: constant frequency of clock
331 * @fixed_accuracy: constant accuracy of clock in ppb (parts per billion)
332 * @flags: hardware specific flags
333 *
334 * Flags:
335 * * CLK_FIXED_RATE_PARENT_ACCURACY - Use the accuracy of the parent clk
336 * instead of what's set in @fixed_accuracy.
324 */337 */
325struct clk_fixed_rate {338struct clk_fixed_rate {
326 struct clk_hw hw;339 struct clk_hw hw;
327 unsigned long fixed_rate;340 unsigned long fixed_rate;
328 unsigned long fixed_accuracy;341 unsigned long fixed_accuracy;
342 unsigned long flags;
329};343};
330 344
331#define to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate, hw)345#define CLK_FIXED_RATE_PARENT_ACCURACY BIT(0)
332 346
333extern const struct clk_ops clk_fixed_rate_ops;347extern const struct clk_ops clk_fixed_rate_ops;
348struct clk_hw *__clk_hw_register_fixed_rate(struct device *dev,
349 struct device_node *np, const char *name,
350 const char *parent_name, const struct clk_hw *parent_hw,
351 const struct clk_parent_data *parent_data, unsigned long flags,
352 unsigned long fixed_rate, unsigned long fixed_accuracy,
353 unsigned long clk_fixed_flags);
334struct clk *clk_register_fixed_rate(struct device *dev, const char *name,354struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
335 const char *parent_name, unsigned long flags,355 const char *parent_name, unsigned long flags,
336 unsigned long fixed_rate);356 unsigned long fixed_rate);
337struct clk_hw *clk_hw_register_fixed_rate(struct device *dev, const char *name,357/**
338 const char *parent_name, unsigned long flags,358 * clk_hw_register_fixed_rate - register fixed-rate clock with the clock
339 unsigned long fixed_rate);359 * framework
340struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev,360 * @dev: device that is registering this clock
341 const char *name, const char *parent_name, unsigned long flags,361 * @name: name of this clock
342 unsigned long fixed_rate, unsigned long fixed_accuracy);362 * @parent_name: name of clock's parent
363 * @flags: framework-specific flags
364 * @fixed_rate: non-adjustable clock rate
365 */
366#define clk_hw_register_fixed_rate(dev, name, parent_name, flags, fixed_rate) \
367 __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), NULL, \
368 NULL, (flags), (fixed_rate), 0, 0)
369/**
370 * clk_hw_register_fixed_rate_parent_hw - register fixed-rate clock with
371 * the clock framework
372 * @dev: device that is registering this clock
373 * @name: name of this clock
374 * @parent_hw: pointer to parent clk
375 * @flags: framework-specific flags
376 * @fixed_rate: non-adjustable clock rate
377 */
378#define clk_hw_register_fixed_rate_parent_hw(dev, name, parent_hw, flags, \
379 fixed_rate) \
380 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw), \
381 NULL, (flags), (fixed_rate), 0, 0)
382/**
383 * clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with
384 * the clock framework
385 * @dev: device that is registering this clock
386 * @name: name of this clock
387 * @parent_data: parent clk data
388 * @flags: framework-specific flags
389 * @fixed_rate: non-adjustable clock rate
390 */
391#define clk_hw_register_fixed_rate_parent_data(dev, name, parent_hw, flags, \
392 fixed_rate) \
393 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
394 (parent_data), (flags), (fixed_rate), 0, \
395 0)
396/**
397 * clk_hw_register_fixed_rate_with_accuracy - register fixed-rate clock with
398 * the clock framework
399 * @dev: device that is registering this clock
400 * @name: name of this clock
401 * @parent_name: name of clock's parent
402 * @flags: framework-specific flags
403 * @fixed_rate: non-adjustable clock rate
404 * @fixed_accuracy: non-adjustable clock accuracy
405 */
406#define clk_hw_register_fixed_rate_with_accuracy(dev, name, parent_name, \
407 flags, fixed_rate, \
408 fixed_accuracy) \
409 __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), \
410 NULL, NULL, (flags), (fixed_rate), \
411 (fixed_accuracy), 0)
412/**
413 * clk_hw_register_fixed_rate_with_accuracy_parent_hw - register fixed-rate
414 * clock with the clock framework
415 * @dev: device that is registering this clock
416 * @name: name of this clock
417 * @parent_hw: pointer to parent clk
418 * @flags: framework-specific flags
419 * @fixed_rate: non-adjustable clock rate
420 * @fixed_accuracy: non-adjustable clock accuracy
421 */
422#define clk_hw_register_fixed_rate_with_accuracy_parent_hw(dev, name, \
423 parent_hw, flags, fixed_rate, fixed_accuracy) \
424 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw) \
425 NULL, NULL, (flags), (fixed_rate), \
426 (fixed_accuracy), 0)
427/**
428 * clk_hw_register_fixed_rate_with_accuracy_parent_data - register fixed-rate
429 * clock with the clock framework
430 * @dev: device that is registering this clock
431 * @name: name of this clock
432 * @parent_name: name of clock's parent
433 * @flags: framework-specific flags
434 * @fixed_rate: non-adjustable clock rate
435 * @fixed_accuracy: non-adjustable clock accuracy
436 */
437#define clk_hw_register_fixed_rate_with_accuracy_parent_data(dev, name, \
438 parent_data, flags, fixed_rate, fixed_accuracy) \
439 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
440 (parent_data), NULL, (flags), \
441 (fixed_rate), (fixed_accuracy), 0)
442
343void clk_unregister_fixed_rate(struct clk *clk);443void clk_unregister_fixed_rate(struct clk *clk);
344struct clk_hw *clk_hw_register_fixed_rate_with_accuracy(struct device *dev,
345 const char *name, const char *parent_name, unsigned long flags,
346 unsigned long fixed_rate, unsigned long fixed_accuracy);
347void clk_hw_unregister_fixed_rate(struct clk_hw *hw);444void clk_hw_unregister_fixed_rate(struct clk_hw *hw);
348 445
349void of_fixed_clk_setup(struct device_node *np);446void of_fixed_clk_setup(struct device_node *np);
@@ -386,14 +483,67 @@ struct clk_gate { · 36 unmodified lines
386#define CLK_GATE_BIG_ENDIAN BIT(2)483#define CLK_GATE_BIG_ENDIAN BIT(2)
387 484
388extern const struct clk_ops clk_gate_ops;485extern const struct clk_ops clk_gate_ops;
389struct clk *clk_register_gate(struct device *dev, const char *name,486struct clk_hw *__clk_hw_register_gate(struct device *dev,
390 const char *parent_name, unsigned long flags,487 struct device_node *np, const char *name,
488 const char *parent_name, const struct clk_hw *parent_hw,
489 const struct clk_parent_data *parent_data,
490 unsigned long flags,
391 void __iomem *reg, u8 bit_idx,491 void __iomem *reg, u8 bit_idx,
392 u8 clk_gate_flags, spinlock_t *lock);492 u8 clk_gate_flags, spinlock_t *lock);
393struct clk_hw *clk_hw_register_gate(struct device *dev, const char *name,493struct clk *clk_register_gate(struct device *dev, const char *name,
394 const char *parent_name, unsigned long flags,494 const char *parent_name, unsigned long flags,
395 void __iomem *reg, u8 bit_idx,495 void __iomem *reg, u8 bit_idx,
396 u8 clk_gate_flags, spinlock_t *lock);496 u8 clk_gate_flags, spinlock_t *lock);
497/**
498 * clk_hw_register_gate - register a gate clock with the clock framework
499 * @dev: device that is registering this clock
500 * @name: name of this clock
501 * @parent_name: name of this clock's parent
502 * @flags: framework-specific flags for this clock
503 * @reg: register address to control gating of this clock
504 * @bit_idx: which bit in the register controls gating of this clock
505 * @clk_gate_flags: gate-specific flags for this clock
506 * @lock: shared register lock for this clock
507 */
508#define clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx, \
509 clk_gate_flags, lock) \
510 __clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \
511 NULL, (flags), (reg), (bit_idx), \
512 (clk_gate_flags), (lock))
513/**
514 * clk_hw_register_gate_parent_hw - register a gate clock with the clock
515 * framework
516 * @dev: device that is registering this clock
517 * @name: name of this clock
518 * @parent_hw: pointer to parent clk
519 * @flags: framework-specific flags for this clock
520 * @reg: register address to control gating of this clock
521 * @bit_idx: which bit in the register controls gating of this clock
522 * @clk_gate_flags: gate-specific flags for this clock
523 * @lock: shared register lock for this clock
524 */
525#define clk_hw_register_gate_parent_hw(dev, name, parent_name, flags, reg, \
526 bit_idx, clk_gate_flags, lock) \
527 __clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \
528 NULL, (flags), (reg), (bit_idx), \
529 (clk_gate_flags), (lock))
530/**
531 * clk_hw_register_gate_parent_data - register a gate clock with the clock
532 * framework
533 * @dev: device that is registering this clock
534 * @name: name of this clock
535 * @parent_data: parent clk data
536 * @flags: framework-specific flags for this clock
537 * @reg: register address to control gating of this clock
538 * @bit_idx: which bit in the register controls gating of this clock
539 * @clk_gate_flags: gate-specific flags for this clock
540 * @lock: shared register lock for this clock
541 */
542#define clk_hw_register_gate_parent_data(dev, name, parent_name, flags, reg, \
543 bit_idx, clk_gate_flags, lock) \
544 __clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \
545 NULL, (flags), (reg), (bit_idx), \
546 (clk_gate_flags), (lock))
397void clk_unregister_gate(struct clk *clk);547void clk_unregister_gate(struct clk *clk);
398void clk_hw_unregister_gate(struct clk_hw *hw);548void clk_hw_unregister_gate(struct clk_hw *hw);
399int clk_gate_is_enabled(struct clk_hw *hw);549int clk_gate_is_enabled(struct clk_hw *hw);
@@ -483,24 +633,153 @@ int divider_get_val(unsigned long rate, unsigned long parent_rate, · 83 unmodified lines
483 const struct clk_div_table *table, u8 width,633 const struct clk_div_table *table, u8 width,
484 unsigned long flags);634 unsigned long flags);
485 635
486struct clk *clk_register_divider(struct device *dev, const char *name,636struct clk_hw *__clk_hw_register_divider(struct device *dev,
487 const char *parent_name, unsigned long flags,637 struct device_node *np, const char *name,
488 void __iomem *reg, u8 shift, u8 width,638 const char *parent_name, const struct clk_hw *parent_hw,
489 u8 clk_divider_flags, spinlock_t *lock);639 const struct clk_parent_data *parent_data, unsigned long flags,
490struct clk_hw *clk_hw_register_divider(struct device *dev, const char *name,640 void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,
491 const char *parent_name, unsigned long flags,641 const struct clk_div_table *table, spinlock_t *lock);
492 void __iomem *reg, u8 shift, u8 width,
493 u8 clk_divider_flags, spinlock_t *lock);
494struct clk *clk_register_divider_table(struct device *dev, const char *name,642struct clk *clk_register_divider_table(struct device *dev, const char *name,
495 const char *parent_name, unsigned long flags,643 const char *parent_name, unsigned long flags,
496 void __iomem *reg, u8 shift, u8 width,644 void __iomem *reg, u8 shift, u8 width,
497 u8 clk_divider_flags, const struct clk_div_table *table,645 u8 clk_divider_flags, const struct clk_div_table *table,
498 spinlock_t *lock);646 spinlock_t *lock);
499struct clk_hw *clk_hw_register_divider_table(struct device *dev,647/**
500 const char *name, const char *parent_name, unsigned long flags,648 * clk_register_divider - register a divider clock with the clock framework
501 void __iomem *reg, u8 shift, u8 width,649 * @dev: device registering this clock
502 u8 clk_divider_flags, const struct clk_div_table *table,650 * @name: name of this clock
503 spinlock_t *lock);651 * @parent_name: name of clock's parent
652 * @flags: framework-specific flags
653 * @reg: register address to adjust divider
654 * @shift: number of bits to shift the bitfield
655 * @width: width of the bitfield
656 * @clk_divider_flags: divider-specific flags for this clock
657 * @lock: shared register lock for this clock
658 */
659#define clk_register_divider(dev, name, parent_name, flags, reg, shift, width, \
660 clk_divider_flags, lock) \
661 clk_register_divider_table((dev), (name), (parent_name), (flags), \
662 (reg), (shift), (width), \
663 (clk_divider_flags), NULL, (lock))
664/**
665 * clk_hw_register_divider - register a divider clock with the clock framework
666 * @dev: device registering this clock
667 * @name: name of this clock
668 * @parent_name: name of clock's parent
669 * @flags: framework-specific flags
670 * @reg: register address to adjust divider
671 * @shift: number of bits to shift the bitfield
672 * @width: width of the bitfield
673 * @clk_divider_flags: divider-specific flags for this clock
674 * @lock: shared register lock for this clock
675 */
676#define clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, \
677 width, clk_divider_flags, lock) \
678 __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \
679 NULL, (flags), (reg), (shift), (width), \
680 (clk_divider_flags), NULL, (lock))
681/**
682 * clk_hw_register_divider_parent_hw - register a divider clock with the clock
683 * framework
684 * @dev: device registering this clock
685 * @name: name of this clock
686 * @parent_hw: pointer to parent clk
687 * @flags: framework-specific flags
688 * @reg: register address to adjust divider
689 * @shift: number of bits to shift the bitfield
690 * @width: width of the bitfield
691 * @clk_divider_flags: divider-specific flags for this clock
692 * @lock: shared register lock for this clock
693 */
694#define clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags, reg, \
695 shift, width, clk_divider_flags, \
696 lock) \
697 __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \
698 NULL, (flags), (reg), (shift), (width), \
699 (clk_divider_flags), NULL, (lock))
700/**
701 * clk_hw_register_divider_parent_data - register a divider clock with the clock
702 * framework
703 * @dev: device registering this clock
704 * @name: name of this clock
705 * @parent_data: parent clk data
706 * @flags: framework-specific flags
707 * @reg: register address to adjust divider
708 * @shift: number of bits to shift the bitfield
709 * @width: width of the bitfield
710 * @clk_divider_flags: divider-specific flags for this clock
711 * @lock: shared register lock for this clock
712 */
713#define clk_hw_register_divider_parent_data(dev, name, parent_data, flags, \
714 reg, shift, width, \
715 clk_divider_flags, lock) \
716 __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \
717 (parent_data), (flags), (reg), (shift), \
718 (width), (clk_divider_flags), NULL, (lock))
719/**
720 * clk_hw_register_divider_table - register a table based divider clock with
721 * the clock framework
722 * @dev: device registering this clock
723 * @name: name of this clock
724 * @parent_name: name of clock's parent
725 * @flags: framework-specific flags
726 * @reg: register address to adjust divider
727 * @shift: number of bits to shift the bitfield
728 * @width: width of the bitfield
729 * @clk_divider_flags: divider-specific flags for this clock
730 * @table: array of divider/value pairs ending with a div set to 0
731 * @lock: shared register lock for this clock
732 */
733#define clk_hw_register_divider_table(dev, name, parent_name, flags, reg, \
734 shift, width, clk_divider_flags, table, \
735 lock) \
736 __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \
737 NULL, (flags), (reg), (shift), (width), \
738 (clk_divider_flags), (table), (lock))
739/**
740 * clk_hw_register_divider_table_parent_hw - register a table based divider
741 * clock with the clock framework
742 * @dev: device registering this clock
743 * @name: name of this clock
744 * @parent_hw: pointer to parent clk
745 * @flags: framework-specific flags
746 * @reg: register address to adjust divider
747 * @shift: number of bits to shift the bitfield
748 * @width: width of the bitfield
749 * @clk_divider_flags: divider-specific flags for this clock
750 * @table: array of divider/value pairs ending with a div set to 0
751 * @lock: shared register lock for this clock
752 */
753#define clk_hw_register_divider_table_parent_hw(dev, name, parent_hw, flags, \
754 reg, shift, width, \
755 clk_divider_flags, table, \
756 lock) \
757 __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \
758 NULL, (flags), (reg), (shift), (width), \
759 (clk_divider_flags), (table), (lock))
760/**
761 * clk_hw_register_divider_table_parent_data - register a table based divider
762 * clock with the clock framework
763 * @dev: device registering this clock
764 * @name: name of this clock
765 * @parent_data: parent clk data
766 * @flags: framework-specific flags
767 * @reg: register address to adjust divider
768 * @shift: number of bits to shift the bitfield
769 * @width: width of the bitfield
770 * @clk_divider_flags: divider-specific flags for this clock
771 * @table: array of divider/value pairs ending with a div set to 0
772 * @lock: shared register lock for this clock
773 */
774#define clk_hw_register_divider_table_parent_data(dev, name, parent_data, \
775 flags, reg, shift, width, \
776 clk_divider_flags, table, \
777 lock) \
778 __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \
779 (parent_data), (flags), (reg), (shift), \
780 (width), (clk_divider_flags), (table), \
781 (lock))
782
504void clk_unregister_divider(struct clk *clk);783void clk_unregister_divider(struct clk *clk);
505void clk_hw_unregister_divider(struct clk_hw *hw);784void clk_hw_unregister_divider(struct clk_hw *hw);
506 785
@@ -555,28 +834,48 @@ struct clk_mux { · 48 unmodified lines
555extern const struct clk_ops clk_mux_ops;834extern const struct clk_ops clk_mux_ops;
556extern const struct clk_ops clk_mux_ro_ops;835extern const struct clk_ops clk_mux_ro_ops;
557 836
558struct clk *clk_register_mux(struct device *dev, const char *name,837struct clk_hw *__clk_hw_register_mux(struct device *dev, struct device_node *np,
559 const char * const *parent_names, u8 num_parents,838 const char *name, u8 num_parents,
560 unsigned long flags,839 const char * const *parent_names,
561 void __iomem *reg, u8 shift, u8 width,840 const struct clk_hw **parent_hws,
562 u8 clk_mux_flags, spinlock_t *lock);841 const struct clk_parent_data *parent_data,
563struct clk_hw *clk_hw_register_mux(struct device *dev, const char *name,842 unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
564 const char * const *parent_names, u8 num_parents,
565 unsigned long flags,
566 void __iomem *reg, u8 shift, u8 width,
567 u8 clk_mux_flags, spinlock_t *lock);
568
569struct clk *clk_register_mux_table(struct device *dev, const char *name,
570 const char * const *parent_names, u8 num_parents,
571 unsigned long flags,
572 void __iomem *reg, u8 shift, u32 mask,
573 u8 clk_mux_flags, u32 *table, spinlock_t *lock);843 u8 clk_mux_flags, u32 *table, spinlock_t *lock);
574struct clk_hw *clk_hw_register_mux_table(struct device *dev, const char *name,844struct clk *clk_register_mux_table(struct device *dev, const char *name,
575 const char * const *parent_names, u8 num_parents,845 const char * const *parent_names, u8 num_parents,
576 unsigned long flags,846 unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
577 void __iomem *reg, u8 shift, u32 mask,
578 u8 clk_mux_flags, u32 *table, spinlock_t *lock);847 u8 clk_mux_flags, u32 *table, spinlock_t *lock);
579 848
849#define clk_register_mux(dev, name, parent_names, num_parents, flags, reg, \
850 shift, width, clk_mux_flags, lock) \
851 clk_register_mux_table((dev), (name), (parent_names), (num_parents), \
852 (flags), (reg), (shift), BIT((width)) - 1, \
853 (clk_mux_flags), NULL, (lock))
854#define clk_hw_register_mux_table(dev, name, parent_names, num_parents, \
855 flags, reg, shift, mask, clk_mux_flags, \
856 table, lock) \
857 __clk_hw_register_mux((dev), NULL, (name), (num_parents), \
858 (parent_names), NULL, NULL, (flags), (reg), \
859 (shift), (mask), (clk_mux_flags), (table), \
860 (lock))
861#define clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \
862 shift, width, clk_mux_flags, lock) \
863 __clk_hw_register_mux((dev), NULL, (name), (num_parents), \
864 (parent_names), NULL, NULL, (flags), (reg), \
865 (shift), BIT((width)) - 1, (clk_mux_flags), \
866 NULL, (lock))
867#define clk_hw_register_mux_hws(dev, name, parent_hws, num_parents, flags, \
868 reg, shift, width, clk_mux_flags, lock) \
869 __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \
870 (parent_hws), NULL, (flags), (reg), (shift), \
871 BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
872#define clk_hw_register_mux_parent_data(dev, name, parent_data, num_parents, \
873 flags, reg, shift, width, \
874 clk_mux_flags, lock) \
875 __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \
876 (parent_data), (flags), (reg), (shift), \
877 BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
878
580int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags,879int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags,
581 unsigned int val);880 unsigned int val);
582unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index);881unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index);
@@ -743,6 +1042,12 @@ struct clk *clk_register_composite(struct device *dev, const char *name, · 160 unmodified lines
743 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,1042 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
744 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,1043 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
745 unsigned long flags);1044 unsigned long flags);
1045struct clk *clk_register_composite_pdata(struct device *dev, const char *name,
1046 const struct clk_parent_data *parent_data, int num_parents,
1047 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1048 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1049 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1050 unsigned long flags);
746void clk_unregister_composite(struct clk *clk);1051void clk_unregister_composite(struct clk *clk);
747struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,1052struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
748 const char * const *parent_names, int num_parents,1053 const char * const *parent_names, int num_parents,
@@ -750,45 +1055,14 @@ struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name, · 1 unmodified line
750 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,1055 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
751 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,1056 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
752 unsigned long flags);1057 unsigned long flags);
753void clk_hw_unregister_composite(struct clk_hw *hw);1058struct clk_hw *clk_hw_register_composite_pdata(struct device *dev,
754 1059 const char *name,
755/**1060 const struct clk_parent_data *parent_data, int num_parents,
756 * struct clk_gpio - gpio gated clock1061 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
757 *1062 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
758 * @hw: handle between common and hardware-specific interfaces1063 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
759 * @gpiod: gpio descriptor
760 *
761 * Clock with a gpio control for enabling and disabling the parent clock
762 * or switching between two parents by asserting or deasserting the gpio.
763 *
764 * Implements .enable, .disable and .is_enabled or
765 * .get_parent, .set_parent and .determine_rate depending on which clk_ops
766 * is used.
767 */
768struct clk_gpio {
769 struct clk_hw hw;
770 struct gpio_desc *gpiod;
771};
772
773#define to_clk_gpio(_hw) container_of(_hw, struct clk_gpio, hw)
774
775extern const struct clk_ops clk_gpio_gate_ops;
776struct clk *clk_register_gpio_gate(struct device *dev, const char *name,
777 const char *parent_name, struct gpio_desc *gpiod,
778 unsigned long flags);
779struct clk_hw *clk_hw_register_gpio_gate(struct device *dev, const char *name,
780 const char *parent_name, struct gpio_desc *gpiod,
781 unsigned long flags);
782void clk_hw_unregister_gpio_gate(struct clk_hw *hw);
783
784extern const struct clk_ops clk_gpio_mux_ops;
785struct clk *clk_register_gpio_mux(struct device *dev, const char *name,
786 const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod,
787 unsigned long flags);
788struct clk_hw *clk_hw_register_gpio_mux(struct device *dev, const char *name,
789 const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod,
790 unsigned long flags);1064 unsigned long flags);
791void clk_hw_unregister_gpio_mux(struct clk_hw *hw);1065void clk_hw_unregister_composite(struct clk_hw *hw);
792 1066
793struct clk *clk_register(struct device *dev, struct clk_hw *hw);1067struct clk *clk_register(struct device *dev, struct clk_hw *hw);
794struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw);1068struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw);
include/linux/clk.h+3−0
@@ -627,6 +627,9 @@ long clk_round_rate(struct clk *clk, unsigned long rate); · 626 unmodified lines
627 * @clk: clock source627 * @clk: clock source
628 * @rate: desired clock rate in Hz628 * @rate: desired clock rate in Hz
629 *629 *
630 * Updating the rate starts at the top-most affected clock and then
631 * walks the tree down to the bottom-most clock that needs updating.
632 *
630 * Returns success (0) or negative errno.633 * Returns success (0) or negative errno.
631 */634 */
632int clk_set_rate(struct clk *clk, unsigned long rate);635int clk_set_rate(struct clk *clk, unsigned long rate);
include/linux/firmware/xlnx-zynqmp.h+2−0
@@ -89,6 +89,7 @@ enum pm_ret_status { · 88 unmodified lines
89 XST_PM_INVALID_NODE,89 XST_PM_INVALID_NODE,
90 XST_PM_DOUBLE_REQ,90 XST_PM_DOUBLE_REQ,
91 XST_PM_ABORT_SUSPEND,91 XST_PM_ABORT_SUSPEND,
92 XST_PM_MULT_USER = 2008,
92};93};
93 94
94enum pm_ioctl_id {95enum pm_ioctl_id {
@@ -107,6 +108,7 @@ enum pm_query_id { · 12 unmodified lines
107 PM_QID_CLOCK_GET_PARENTS,108 PM_QID_CLOCK_GET_PARENTS,
108 PM_QID_CLOCK_GET_ATTRIBUTES,109 PM_QID_CLOCK_GET_ATTRIBUTES,
109 PM_QID_CLOCK_GET_NUM_CLOCKS = 12,110 PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
111 PM_QID_CLOCK_GET_MAX_DIVISOR,
110};112};
111 113
112enum zynqmp_pm_reset_action {114enum zynqmp_pm_reset_action {