History

Merge branch 'drm-next-5.1' of git://people.freedesktop.org/~agd5f/linux into drm-next

Updates for 5.1: - GDS fixes - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES interface - GPUVM fixes - PCIE DPM switching fixes for vega20 - Vega10 uclk DPM regression fix - DC Freesync fixes - DC ABM fixes - Various DC cleanups

Dave Airlie committed 7 years ago

Commit f4bc54b2 parents 5ea3998 046122151 files · +1161 −486Browse files

Unified · Split

51 files
  1. drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +12 −1
  2. drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +46 −12
  3. drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +3 −1
  4. drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h +2 −0
  5. drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +0 −7
  6. drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +12 −4
  7. drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +3 −3
  8. drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +16 −17
  9. drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c +1 −1
  10. drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +18 −1
  11. drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +19 −2
  12. drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +38 −2
  13. drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +93 −105
  14. drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +5 −0
  15. drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c +1 −1
  16. drivers/gpu/drm/amd/display/dc/core/dc.c +171 −18
  17. drivers/gpu/drm/amd/display/dc/core/dc_link.c +39 −27
  18. drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +4 −35
  19. drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c +4 −0
  20. drivers/gpu/drm/amd/display/dc/core/dc_resource.c +54 −2
  21. drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c +7 −11
  22. drivers/gpu/drm/amd/display/dc/dc.h +6 −2
  23. drivers/gpu/drm/amd/display/dc/dc_link.h +2 −0
  24. drivers/gpu/drm/amd/display/dc/dc_stream.h +17 −8
  25. drivers/gpu/drm/amd/display/dc/dc_types.h +1 −0
  26. drivers/gpu/drm/amd/display/dc/dce/dce_abm.c +2 −2
  27. drivers/gpu/drm/amd/display/dc/dce/dce_aux.c +1 −1
  28. drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +26 −2
  29. drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +32 −20
  30. drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c +11 −8
  31. drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h +1 −1
  32. drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c +21 −2
  33. drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +99 −95
  34. drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c +10 −0
  35. drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h +2 −0
  36. drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c +180 −17
  37. drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h +5 −3
  38. drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c +12 −0
  39. drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c +28 −0
  40. drivers/gpu/drm/amd/display/dc/gpio/gpio_service.h +10 −0
  41. drivers/gpu/drm/amd/display/dc/inc/clock_source.h +4 −0
  42. drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h +1 −0
  43. drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +10 −3
  44. drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +2 −0
  45. drivers/gpu/drm/amd/display/dc/inc/vm_helper.h +4 −3
  46. drivers/gpu/drm/amd/display/include/gpio_interface.h +8 −0
  47. drivers/gpu/drm/amd/display/modules/color/color_gamma.c +52 −37
  48. drivers/gpu/drm/amd/display/modules/power/power_helpers.c +26 −12
  49. drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +7 −0
  50. drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c +27 −20
  51. include/uapi/drm/amdgpu_drm.h +6 −0
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c+12−1
@@ -214,6 +214,7 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, union drm_amdgpu_cs · 213 unmodified lines
214214 case AMDGPU_CHUNK_ID_DEPENDENCIES:
215215 case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
216216 case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
217+ case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES:
217218 break;
218219
219220 default:
@@ -1090,6 +1091,15 @@ static int amdgpu_cs_process_fence_dep(struct amdgpu_cs_parser *p, · 870 unmodified lines
10901091
10911092 fence = amdgpu_ctx_get_fence(ctx, entity,
10921093 deps[i].handle);
1094+
1095+ if (chunk->chunk_id == AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES) {
1096+ struct drm_sched_fence *s_fence = to_drm_sched_fence(fence);
1097+ struct dma_fence *old = fence;
1098+
1099+ fence = dma_fence_get(&s_fence->scheduled);
1100+ dma_fence_put(old);
1101+ }
1102+
10931103 if (IS_ERR(fence)) {
10941104 r = PTR_ERR(fence);
10951105 amdgpu_ctx_put(ctx);
@@ -1177,7 +1187,8 @@ static int amdgpu_cs_dependencies(struct amdgpu_device *adev, · 81 unmodified lines
11771187
11781188 chunk = &p->chunks[i];
11791189
1180− if (chunk->chunk_id == AMDGPU_CHUNK_ID_DEPENDENCIES) {
1190+ if (chunk->chunk_id == AMDGPU_CHUNK_ID_DEPENDENCIES ||
1191+ chunk->chunk_id == AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES) {
11811192 r = amdgpu_cs_process_fence_dep(p, chunk);
11821193 if (r)
11831194 return r;
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c+46−12
@@ -3618,6 +3618,38 @@ retry: /* Rest of adevs pre asic reset from XGMI hive. */ · 3617 unmodified lines
36183618 return r;
36193619 }
36203620
3621+static void amdgpu_device_get_min_pci_speed_width(struct amdgpu_device *adev,
3622+ enum pci_bus_speed *speed,
3623+ enum pcie_link_width *width)
3624+{
3625+ struct pci_dev *pdev = adev->pdev;
3626+ enum pci_bus_speed cur_speed;
3627+ enum pcie_link_width cur_width;
3628+
3629+ *speed = PCI_SPEED_UNKNOWN;
3630+ *width = PCIE_LNK_WIDTH_UNKNOWN;
3631+
3632+ while (pdev) {
3633+ cur_speed = pcie_get_speed_cap(pdev);
3634+ cur_width = pcie_get_width_cap(pdev);
3635+
3636+ if (cur_speed != PCI_SPEED_UNKNOWN) {
3637+ if (*speed == PCI_SPEED_UNKNOWN)
3638+ *speed = cur_speed;
3639+ else if (cur_speed < *speed)
3640+ *speed = cur_speed;
3641+ }
3642+
3643+ if (cur_width != PCIE_LNK_WIDTH_UNKNOWN) {
3644+ if (*width == PCIE_LNK_WIDTH_UNKNOWN)
3645+ *width = cur_width;
3646+ else if (cur_width < *width)
3647+ *width = cur_width;
3648+ }
3649+ pdev = pci_upstream_bridge(pdev);
3650+ }
3651+}
3652+
36213653 /**
36223654 * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot
36233655 *
@@ -3630,8 +3662,8 @@ retry: /* Rest of adevs pre asic reset from XGMI hive. */ · 6 unmodified lines
36303662 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
36313663 {
36323664 struct pci_dev *pdev;
3633− enum pci_bus_speed speed_cap;
3634− enum pcie_link_width link_width;
3665+ enum pci_bus_speed speed_cap, platform_speed_cap;
3666+ enum pcie_link_width platform_link_width;
36353667
36363668 if (amdgpu_pcie_gen_cap)
36373669 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
@@ -3648,6 +3680,12 @@ static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev) · 10 unmodified lines
36483680 return;
36493681 }
36503682
3683+ if (adev->pm.pcie_gen_mask && adev->pm.pcie_mlw_mask)
3684+ return;
3685+
3686+ amdgpu_device_get_min_pci_speed_width(adev, &platform_speed_cap,
3687+ &platform_link_width);
3688+
36513689 if (adev->pm.pcie_gen_mask == 0) {
36523690 /* asic caps */
36533691 pdev = adev->pdev;
@@ -3673,22 +3711,20 @@ static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev) · 19 unmodified lines
36733711 adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1;
36743712 }
36753713 /* platform caps */
3676− pdev = adev->ddev->pdev->bus->self;
3677− speed_cap = pcie_get_speed_cap(pdev);
3678− if (speed_cap == PCI_SPEED_UNKNOWN) {
3714+ if (platform_speed_cap == PCI_SPEED_UNKNOWN) {
36793715 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
36803716 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
36813717 } else {
3682− if (speed_cap == PCIE_SPEED_16_0GT)
3718+ if (platform_speed_cap == PCIE_SPEED_16_0GT)
36833719 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
36843720 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
36853721 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
36863722 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4);
3687− else if (speed_cap == PCIE_SPEED_8_0GT)
3723+ else if (platform_speed_cap == PCIE_SPEED_8_0GT)
36883724 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
36893725 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
36903726 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3);
3691− else if (speed_cap == PCIE_SPEED_5_0GT)
3727+ else if (platform_speed_cap == PCIE_SPEED_5_0GT)
36923728 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
36933729 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
36943730 else
@@ -3697,12 +3733,10 @@ static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev) · 2 unmodified lines
36973733 }
36983734 }
36993735 if (adev->pm.pcie_mlw_mask == 0) {
3700− pdev = adev->ddev->pdev->bus->self;
3701− link_width = pcie_get_width_cap(pdev);
3702− if (link_width == PCIE_LNK_WIDTH_UNKNOWN) {
3736+ if (platform_link_width == PCIE_LNK_WIDTH_UNKNOWN) {
37033737 adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK;
37043738 } else {
3705− switch (link_width) {
3739+ switch (platform_link_width) {
37063740 case PCIE_LNK_X32:
37073741 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
37083742 CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c+3−1
@@ -71,9 +71,11 @@ · 70 unmodified lines
7171 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk).
7272 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE.
7373 * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation.
74+ * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES
75+ * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
7476 */
7577 #define KMS_DRIVER_MAJOR 3
76−#define KMS_DRIVER_MINOR 27
78+#define KMS_DRIVER_MINOR 29
7779 #define KMS_DRIVER_PATCHLEVEL 0
7880
7981 int amdgpu_vram_limit = 0;
drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h+2−0
@@ -37,6 +37,8 @@ struct amdgpu_gds { · 36 unmodified lines
3737 struct amdgpu_gds_asic_info mem;
3838 struct amdgpu_gds_asic_info gws;
3939 struct amdgpu_gds_asic_info oa;
40+ uint32_t gds_compute_max_wave_id;
41+
4042 /* At present, GDS, GWS and OA resources for gfx (graphics)
4143 * is always pre-allocated and available for graphics operation.
4244 * Such resource is shared between all gfx clients.
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c+0−7
@@ -54,10 +54,6 @@ int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, · 53 unmodified lines
5454
5555 memset(&bp, 0, sizeof(bp));
5656 *obj = NULL;
57− /* At least align on page size */
58− if (alignment < PAGE_SIZE) {
59− alignment = PAGE_SIZE;
60− }
6157
6258 bp.size = size;
6359 bp.byte_align = alignment;
@@ -244,9 +240,6 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, · 180 unmodified lines
244240 return -EINVAL;
245241 }
246242 flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
247− /* GDS allocations must be DW aligned */
248− if (args->in.domains & AMDGPU_GEM_DOMAIN_GDS)
249− size = ALIGN(size, 4);
250243 }
251244
252245 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c+12−4
@@ -426,12 +426,20 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev, · 425 unmodified lines
426426 size_t acc_size;
427427 int r;
428428
429− page_align = roundup(bp->byte_align, PAGE_SIZE) >> PAGE_SHIFT;
430− if (bp->domain & (AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS |
431− AMDGPU_GEM_DOMAIN_OA))
429+ /* Note that GDS/GWS/OA allocates 1 page per byte/resource. */
430+ if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
431+ /* GWS and OA don't need any alignment. */
432+ page_align = bp->byte_align;
432433 size <<= PAGE_SHIFT;
433− else
434+ } else if (bp->domain & AMDGPU_GEM_DOMAIN_GDS) {
435+ /* Both size and alignment must be a multiple of 4. */
436+ page_align = ALIGN(bp->byte_align, 4);
437+ size = ALIGN(size, 4) << PAGE_SHIFT;
438+ } else {
439+ /* Memory should be aligned at least to a page size. */
440+ page_align = ALIGN(bp->byte_align, PAGE_SIZE) >> PAGE_SHIFT;
434441 size = ALIGN(size, PAGE_SIZE);
442+ }
435443
436444 if (!amdgpu_bo_validate_size(adev, size, bp->domain))
437445 return -ENOMEM;
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c+3−3
@@ -1756,7 +1756,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) · 1755 unmodified lines
17561756 }
17571757
17581758 r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size,
1759− PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS,
1759+ 4, AMDGPU_GEM_DOMAIN_GDS,
17601760 &adev->gds.gds_gfx_bo, NULL, NULL);
17611761 if (r)
17621762 return r;
@@ -1769,7 +1769,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) · 6 unmodified lines
17691769 }
17701770
17711771 r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size,
1772− PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS,
1772+ 1, AMDGPU_GEM_DOMAIN_GWS,
17731773 &adev->gds.gws_gfx_bo, NULL, NULL);
17741774 if (r)
17751775 return r;
@@ -1782,7 +1782,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) · 6 unmodified lines
17821782 }
17831783
17841784 r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size,
1785− PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA,
1785+ 1, AMDGPU_GEM_DOMAIN_OA,
17861786 &adev->gds.oa_gfx_bo, NULL, NULL);
17871787 if (r)
17881788 return r;
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c+16−17
@@ -107,14 +107,6 @@ struct amdgpu_pte_update_params { · 106 unmodified lines
107107 * DMA addresses to use for mapping, used during VM update by CPU
108108 */
109109 dma_addr_t *pages_addr;
110−
111− /**
112− * @kptr:
113− *
114− * Kernel pointer of PD/PT BO that needs to be updated,
115− * used during VM update by CPU
116− */
117− void *kptr;
118110 };
119111
120112 /**
@@ -1789,13 +1781,20 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, · 1668 unmodified lines
17891781 if (pages_addr)
17901782 params.src = ~0;
17911783
1792− /* Wait for PT BOs to be free. PTs share the same resv. object
1784+ /* Wait for PT BOs to be idle. PTs share the same resv. object
17931785 * as the root PD BO
17941786 */
17951787 r = amdgpu_vm_wait_pd(adev, vm, owner);
17961788 if (unlikely(r))
17971789 return r;
17981790
1791+ /* Wait for any BO move to be completed */
1792+ if (exclusive) {
1793+ r = dma_fence_wait(exclusive, true);
1794+ if (unlikely(r))
1795+ return r;
1796+ }
1797+
17991798 params.func = amdgpu_vm_cpu_set_ptes;
18001799 params.pages_addr = pages_addr;
18011800 return amdgpu_vm_update_ptes(&params, start, last + 1,
@@ -1809,13 +1808,12 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, · 7 unmodified lines
18091808 /*
18101809 * reserve space for two commands every (1 << BLOCK_SIZE)
18111810 * entries or 2k dwords (whatever is smaller)
1812− *
1813− * The second command is for the shadow pagetables.
18141811 */
1812+ ncmds = ((nptes >> min(adev->vm_manager.block_size, 11u)) + 1);
1813+
1814+ /* The second command is for the shadow pagetables. */
18151815 if (vm->root.base.bo->shadow)
1816− ncmds = ((nptes >> min(adev->vm_manager.block_size, 11u)) + 1) * 2;
1817− else
1818− ncmds = ((nptes >> min(adev->vm_manager.block_size, 11u)) + 1);
1816+ ncmds *= 2;
18191817
18201818 /* padding, etc. */
18211819 ndw = 64;
@@ -1834,10 +1832,11 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, · 12 unmodified lines
18341832 ndw += ncmds * 10;
18351833
18361834 /* extra commands for begin/end fragments */
1835+ ncmds = 2 * adev->vm_manager.fragment_size;
18371836 if (vm->root.base.bo->shadow)
1838− ndw += 2 * 10 * adev->vm_manager.fragment_size * 2;
1839− else
1840− ndw += 2 * 10 * adev->vm_manager.fragment_size;
1837+ ncmds *= 2;
1838+
1839+ ndw += 10 * ncmds;
18411840
18421841 params.func = amdgpu_vm_do_set_ptes;
18431842 }
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c+1−1
@@ -125,7 +125,7 @@ int amdgpu_xgmi_add_device(struct amdgpu_device *adev) · 124 unmodified lines
125125 if (!hive) {
126126 ret = -EINVAL;
127127 dev_err(adev->dev,
128− "XGMI: node 0x%llx, can not matech hive 0x%llx in the hive list.\n",
128+ "XGMI: node 0x%llx, can not match hive 0x%llx in the hive list.\n",
129129 adev->gmc.xgmi.node_id, adev->gmc.xgmi.hive_id);
130130 goto exit;
131131 }
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c+18−1
@@ -2264,6 +2264,22 @@ static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring, · 2263 unmodified lines
22642264 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
22652265 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
22662266
2267+ /* Currently, there is a high possibility to get wave ID mismatch
2268+ * between ME and GDS, leading to a hw deadlock, because ME generates
2269+ * different wave IDs than the GDS expects. This situation happens
2270+ * randomly when at least 5 compute pipes use GDS ordered append.
2271+ * The wave IDs generated by ME are also wrong after suspend/resume.
2272+ * Those are probably bugs somewhere else in the kernel driver.
2273+ *
2274+ * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
2275+ * GDS to 0 for this ring (me/pipe).
2276+ */
2277+ if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
2278+ amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2279+ amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID - PACKET3_SET_CONFIG_REG_START);
2280+ amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
2281+ }
2282+
22672283 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
22682284 amdgpu_ring_write(ring,
22692285 #ifdef __BIG_ENDIAN
@@ -5000,7 +5016,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = { · 2730 unmodified lines
50005016 7 + /* gfx_v7_0_ring_emit_pipeline_sync */
50015017 CIK_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v7_0_ring_emit_vm_flush */
50025018 7 + 7 + 7, /* gfx_v7_0_ring_emit_fence_compute x3 for user fence, vm fence */
5003− .emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_compute */
5019+ .emit_ib_size = 7, /* gfx_v7_0_ring_emit_ib_compute */
50045020 .emit_ib = gfx_v7_0_ring_emit_ib_compute,
50055021 .emit_fence = gfx_v7_0_ring_emit_fence_compute,
50065022 .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync,
@@ -5057,6 +5073,7 @@ static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev) · 50 unmodified lines
50575073 adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);
50585074 adev->gds.gws.total_size = 64;
50595075 adev->gds.oa.total_size = 16;
5076+ adev->gds.gds_compute_max_wave_id = RREG32(mmGDS_COMPUTE_MAX_WAVE_ID);
50605077
50615078 if (adev->gds.mem.total_size == 64 * 1024) {
50625079 adev->gds.mem.gfx_partition_size = 4096;
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c+19−2
@@ -6084,6 +6084,22 @@ static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring, · 6083 unmodified lines
60846084 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
60856085 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
60866086
6087+ /* Currently, there is a high possibility to get wave ID mismatch
6088+ * between ME and GDS, leading to a hw deadlock, because ME generates
6089+ * different wave IDs than the GDS expects. This situation happens
6090+ * randomly when at least 5 compute pipes use GDS ordered append.
6091+ * The wave IDs generated by ME are also wrong after suspend/resume.
6092+ * Those are probably bugs somewhere else in the kernel driver.
6093+ *
6094+ * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
6095+ * GDS to 0 for this ring (me/pipe).
6096+ */
6097+ if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
6098+ amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
6099+ amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID - PACKET3_SET_CONFIG_REG_START);
6100+ amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
6101+ }
6102+
60876103 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
60886104 amdgpu_ring_write(ring,
60896105 #ifdef __BIG_ENDIAN
@@ -6890,7 +6906,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = { · 800 unmodified lines
68906906 7 + /* gfx_v8_0_ring_emit_pipeline_sync */
68916907 VI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v8_0_ring_emit_vm_flush */
68926908 7 + 7 + 7, /* gfx_v8_0_ring_emit_fence_compute x3 for user fence, vm fence */
6893− .emit_ib_size = 4, /* gfx_v8_0_ring_emit_ib_compute */
6909+ .emit_ib_size = 7, /* gfx_v8_0_ring_emit_ib_compute */
68946910 .emit_ib = gfx_v8_0_ring_emit_ib_compute,
68956911 .emit_fence = gfx_v8_0_ring_emit_fence_compute,
68966912 .emit_pipeline_sync = gfx_v8_0_ring_emit_pipeline_sync,
@@ -6920,7 +6936,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_kiq = { · 23 unmodified lines
69206936 7 + /* gfx_v8_0_ring_emit_pipeline_sync */
69216937 17 + /* gfx_v8_0_ring_emit_vm_flush */
69226938 7 + 7 + 7, /* gfx_v8_0_ring_emit_fence_kiq x3 for user fence, vm fence */
6923− .emit_ib_size = 4, /* gfx_v8_0_ring_emit_ib_compute */
6939+ .emit_ib_size = 7, /* gfx_v8_0_ring_emit_ib_compute */
69246940 .emit_fence = gfx_v8_0_ring_emit_fence_kiq,
69256941 .test_ring = gfx_v8_0_ring_test_ring,
69266942 .insert_nop = amdgpu_ring_insert_nop,
@@ -6996,6 +7012,7 @@ static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev) · 69 unmodified lines
69967012 adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);
69977013 adev->gds.gws.total_size = 64;
69987014 adev->gds.oa.total_size = 16;
7015+ adev->gds.gds_compute_max_wave_id = RREG32(mmGDS_COMPUTE_MAX_WAVE_ID);
69997016
70007017 if (adev->gds.mem.total_size == 64 * 1024) {
70017018 adev->gds.mem.gfx_partition_size = 4096;
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c+38−2
@@ -4010,6 +4010,22 @@ static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring, · 4009 unmodified lines
40104010 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
40114011 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
40124012
4013+ /* Currently, there is a high possibility to get wave ID mismatch
4014+ * between ME and GDS, leading to a hw deadlock, because ME generates
4015+ * different wave IDs than the GDS expects. This situation happens
4016+ * randomly when at least 5 compute pipes use GDS ordered append.
4017+ * The wave IDs generated by ME are also wrong after suspend/resume.
4018+ * Those are probably bugs somewhere else in the kernel driver.
4019+ *
4020+ * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
4021+ * GDS to 0 for this ring (me/pipe).
4022+ */
4023+ if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
4024+ amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
4025+ amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
4026+ amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
4027+ }
4028+
40134029 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
40144030 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
40154031 amdgpu_ring_write(ring,
@@ -4729,7 +4745,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = { · 713 unmodified lines
47294745 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
47304746 2 + /* gfx_v9_0_ring_emit_vm_flush */
47314747 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
4732− .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
4748+ .emit_ib_size = 7, /* gfx_v9_0_ring_emit_ib_compute */
47334749 .emit_ib = gfx_v9_0_ring_emit_ib_compute,
47344750 .emit_fence = gfx_v9_0_ring_emit_fence,
47354751 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
@@ -4764,7 +4780,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = { · 28 unmodified lines
47644780 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
47654781 2 + /* gfx_v9_0_ring_emit_vm_flush */
47664782 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */
4767− .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
4783+ .emit_ib_size = 7, /* gfx_v9_0_ring_emit_ib_compute */
47684784 .emit_fence = gfx_v9_0_ring_emit_fence_kiq,
47694785 .test_ring = gfx_v9_0_ring_test_ring,
47704786 .insert_nop = amdgpu_ring_insert_nop,
@@ -4846,6 +4862,26 @@ static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev) · 75 unmodified lines
48464862 break;
48474863 }
48484864
4865+ switch (adev->asic_type) {
4866+ case CHIP_VEGA10:
4867+ case CHIP_VEGA20:
4868+ adev->gds.gds_compute_max_wave_id = 0x7ff;
4869+ break;
4870+ case CHIP_VEGA12:
4871+ adev->gds.gds_compute_max_wave_id = 0x27f;
4872+ break;
4873+ case CHIP_RAVEN:
4874+ if (adev->rev_id >= 0x8)
4875+ adev->gds.gds_compute_max_wave_id = 0x77; /* raven2 */
4876+ else
4877+ adev->gds.gds_compute_max_wave_id = 0x15f; /* raven1 */
4878+ break;
4879+ default:
4880+ /* this really depends on the chip */
4881+ adev->gds.gds_compute_max_wave_id = 0x7ff;
4882+ break;
4883+ }
4884+
48494885 adev->gds.gws.total_size = 64;
48504886 adev->gds.oa.total_size = 16;
48514887
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c+93−105
@@ -2297,12 +2297,15 @@ static bool fill_plane_dcc_attributes(struct amdgpu_device *adev, · 2296 unmodified lines
22972297 uint64_t info)
22982298 {
22992299 struct dc *dc = adev->dm.dc;
2300− struct dc_dcc_surface_param input = {0};
2301− struct dc_surface_dcc_cap output = {0};
2300+ struct dc_dcc_surface_param input;
2301+ struct dc_surface_dcc_cap output;
23022302 uint32_t offset = AMDGPU_TILING_GET(info, DCC_OFFSET_256B);
23032303 uint32_t i64b = AMDGPU_TILING_GET(info, DCC_INDEPENDENT_64B) != 0;
23042304 uint64_t dcc_address;
23052305
2306+ memset(&input, 0, sizeof(input));
2307+ memset(&output, 0, sizeof(output));
2308+
23062309 if (!offset)
23072310 return false;
23082311
@@ -2956,11 +2959,9 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, · 647 unmodified lines
29562959 drm_connector = &aconnector->base;
29572960
29582961 if (!aconnector->dc_sink) {
2959− if (!aconnector->mst_port) {
2960− sink = create_fake_sink(aconnector);
2961− if (!sink)
2962− return stream;
2963− }
2962+ sink = create_fake_sink(aconnector);
2963+ if (!sink)
2964+ return stream;
29642965 } else {
29652966 sink = aconnector->dc_sink;
29662967 }
@@ -3027,9 +3028,6 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, · 60 unmodified lines
30273028
30283029 update_stream_signal(stream, sink);
30293030
3030− if (dm_state && dm_state->freesync_capable)
3031− stream->ignore_msa_timing_param = true;
3032−
30333031 finish:
30343032 if (sink && sink->sink_signal == SIGNAL_TYPE_VIRTUAL && aconnector->base.force != DRM_FORCE_ON)
30353033 dc_sink_release(sink);
@@ -4610,12 +4608,6 @@ static void update_freesync_state_on_stream( · 1574 unmodified lines
46104608 new_crtc_state->base.crtc->base.id,
46114609 (int)new_crtc_state->base.vrr_enabled,
46124610 (int)vrr_params.state);
4613−
4614− if (new_crtc_state->freesync_timing_changed)
4615− DRM_DEBUG_KMS("VRR timing update: crtc=%u min=%u max=%u\n",
4616− new_crtc_state->base.crtc->base.id,
4617− vrr_params.adjust.v_total_min,
4618− vrr_params.adjust.v_total_max);
46194611 }
46204612
46214613 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
@@ -4639,7 +4631,6 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, · 17 unmodified lines
46394631 unsigned long flags;
46404632 struct amdgpu_bo *abo;
46414633 uint64_t tiling_flags, dcc_address;
4642− struct dc_stream_status *stream_status;
46434634 uint32_t target, target_vblank;
46444635
46454636 struct {
@@ -4670,7 +4661,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, · 24 unmodified lines
46704661 struct drm_framebuffer *fb = new_plane_state->fb;
46714662 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
46724663 bool pflip_needed;
4673− struct dc_plane_state *surface, *dc_plane;
4664+ struct dc_plane_state *dc_plane;
46744665 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
46754666
46764667 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
@@ -4733,39 +4724,22 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, · 56 unmodified lines
47334724 timestamp_ns = ktime_get_ns();
47344725 flip->flip_addrs[flip_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
47354726 flip->surface_updates[flip_count].flip_addr = &flip->flip_addrs[flip_count];
4727+ flip->surface_updates[flip_count].surface = dc_plane;
47364728
4737− stream_status = dc_stream_get_status(acrtc_state->stream);
4738− if (!stream_status) {
4739− DRM_ERROR("No stream status for CRTC: id=%d\n",
4740− acrtc_attach->crtc_id);
4741− continue;
4742− }
4743−
4744− surface = stream_status->plane_states[0];
4745− flip->surface_updates[flip_count].surface = surface;
47464729 if (!flip->surface_updates[flip_count].surface) {
47474730 DRM_ERROR("No surface for CRTC: id=%d\n",
47484731 acrtc_attach->crtc_id);
47494732 continue;
47504733 }
47514734
4752− if (acrtc_state->stream)
4735+ if (plane == pcrtc->primary)
47534736 update_freesync_state_on_stream(
47544737 dm,
47554738 acrtc_state,
47564739 acrtc_state->stream,
4757− surface,
4740+ dc_plane,
47584741 flip->flip_addrs[flip_count].flip_timestamp_in_us);
47594742
4760− /* Update surface timing information. */
4761− surface->time.time_elapsed_in_us[surface->time.index] =
4762− flip->flip_addrs[flip_count].flip_timestamp_in_us -
4763− surface->time.prev_update_time_in_us;
4764− surface->time.prev_update_time_in_us = flip->flip_addrs[flip_count].flip_timestamp_in_us;
4765− surface->time.index++;
4766− if (surface->time.index >= DC_PLANE_UPDATE_TIMES_MAX)
4767− surface->time.index = 0;
4768−
47694743 DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x\n",
47704744 __func__,
47714745 flip->flip_addrs[flip_count].address.grph.addr.high_part,
@@ -4902,7 +4876,8 @@ cleanup: · 130 unmodified lines
49024876 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
49034877 struct dc_stream_state *stream_state)
49044878 {
4905− stream_state->mode_changed = crtc_state->mode_changed;
4879+ stream_state->mode_changed =
4880+ crtc_state->mode_changed || crtc_state->active_changed;
49064881 }
49074882
49084883 static int amdgpu_dm_atomic_commit(struct drm_device *dev,
@@ -5094,10 +5069,13 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) · 185 unmodified lines
50945069 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
50955070 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
50965071 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
5097− struct dc_surface_update dummy_updates[MAX_SURFACES] = { 0 };
5098− struct dc_stream_update stream_update = { 0 };
5072+ struct dc_surface_update dummy_updates[MAX_SURFACES];
5073+ struct dc_stream_update stream_update;
50995074 struct dc_stream_status *status = NULL;
51005075
5076+ memset(&dummy_updates, 0, sizeof(dummy_updates));
5077+ memset(&stream_update, 0, sizeof(stream_update));
5078+
51015079 if (acrtc) {
51025080 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
51035081 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
@@ -5174,9 +5152,11 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) · 70 unmodified lines
51745152
51755153 manage_dm_interrupts(adev, acrtc, true);
51765154
5155+#ifdef CONFIG_DEBUG_FS
51775156 /* The stream has changed so CRC capture needs to re-enabled. */
51785157 if (dm_new_crtc_state->crc_enabled)
51795158 amdgpu_dm_crtc_set_crc_source(crtc, "auto");
5159+#endif
51805160 }
51815161
51825162 /* update planes when needed per crtc*/
@@ -5372,10 +5352,13 @@ static void get_freesync_config_for_crtc( · 189 unmodified lines
53725352 struct mod_freesync_config config = {0};
53735353 struct amdgpu_dm_connector *aconnector =
53745354 to_amdgpu_dm_connector(new_con_state->base.connector);
5355+ struct drm_display_mode *mode = &new_crtc_state->base.mode;
53755356
5376− new_crtc_state->vrr_supported = new_con_state->freesync_capable;
5357+ new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
5358+ aconnector->min_vfreq <= drm_mode_vrefresh(mode);
53775359
5378− if (new_con_state->freesync_capable) {
5360+ if (new_crtc_state->vrr_supported) {
5361+ new_crtc_state->stream->ignore_msa_timing_param = true;
53795362 config.state = new_crtc_state->base.vrr_enabled ?
53805363 VRR_STATE_ACTIVE_VARIABLE :
53815364 VRR_STATE_INACTIVE;
@@ -5783,7 +5766,6 @@ dm_determine_update_type_for_commit(struct dc *dc, · 401 unmodified lines
57835766
57845767 struct dc_surface_update *updates;
57855768 struct dc_plane_state *surface;
5786− struct dc_stream_update stream_update;
57875769 enum surface_update_type update_type = UPDATE_TYPE_FAST;
57885770
57895771 updates = kcalloc(MAX_SURFACES, sizeof(*updates), GFP_KERNEL);
@@ -5797,79 +5779,85 @@ dm_determine_update_type_for_commit(struct dc *dc, · 7 unmodified lines
57975779 }
57985780
57995781 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
5782+ struct dc_stream_update stream_update = { 0 };
5783+
58005784 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
58015785 old_dm_crtc_state = to_dm_crtc_state(old_crtc_state);
58025786 num_plane = 0;
58035787
5804− if (new_dm_crtc_state->stream) {
5805−
5806− for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, j) {
5807− new_plane_crtc = new_plane_state->crtc;
5808− old_plane_crtc = old_plane_state->crtc;
5809− new_dm_plane_state = to_dm_plane_state(new_plane_state);
5810− old_dm_plane_state = to_dm_plane_state(old_plane_state);
5811−
5812− if (plane->type == DRM_PLANE_TYPE_CURSOR)
5813− continue;
5814−
5815− if (!state->allow_modeset)
5816− continue;
5817−
5818− if (crtc == new_plane_crtc) {
5819− updates[num_plane].surface = &surface[num_plane];
5820−
5821− if (new_crtc_state->mode_changed) {
5822− updates[num_plane].surface->src_rect =
5823− new_dm_plane_state->dc_state->src_rect;
5824− updates[num_plane].surface->dst_rect =
5825− new_dm_plane_state->dc_state->dst_rect;
5826− updates[num_plane].surface->rotation =
5827− new_dm_plane_state->dc_state->rotation;
5828− updates[num_plane].surface->in_transfer_func =
5829− new_dm_plane_state->dc_state->in_transfer_func;
5830− stream_update.dst = new_dm_crtc_state->stream->dst;
5831− stream_update.src = new_dm_crtc_state->stream->src;
5832− }
5833−
5834− if (new_crtc_state->color_mgmt_changed) {
5835− updates[num_plane].gamma =
5836− new_dm_plane_state->dc_state->gamma_correction;
5837− updates[num_plane].in_transfer_func =
5838− new_dm_plane_state->dc_state->in_transfer_func;
5839− stream_update.gamut_remap =
5840− &new_dm_crtc_state->stream->gamut_remap_matrix;
5841− stream_update.out_transfer_func =
5842− new_dm_crtc_state->stream->out_transfer_func;
5843− }
5844−
5845− num_plane++;
5846− }
5788+ if (!new_dm_crtc_state->stream) {
5789+ if (!new_dm_crtc_state->stream && old_dm_crtc_state->stream) {
5790+ update_type = UPDATE_TYPE_FULL;
5791+ goto cleanup;
58475792 }
58485793
5849− if (num_plane > 0) {
5850− ret = dm_atomic_get_state(state, &dm_state);
5851− if (ret)
5852− goto cleanup;
5794+ continue;
5795+ }
58535796
5854− old_dm_state = dm_atomic_get_old_state(state);
5855− if (!old_dm_state) {
5856− ret = -EINVAL;
5857− goto cleanup;
5858− }
5797+ for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, j) {
5798+ new_plane_crtc = new_plane_state->crtc;
5799+ old_plane_crtc = old_plane_state->crtc;
5800+ new_dm_plane_state = to_dm_plane_state(new_plane_state);
5801+ old_dm_plane_state = to_dm_plane_state(old_plane_state);
58595802
5860− status = dc_stream_get_status_from_state(old_dm_state->context,
5861− new_dm_crtc_state->stream);
5803+ if (plane->type == DRM_PLANE_TYPE_CURSOR)
5804+ continue;
58625805
5863− update_type = dc_check_update_surfaces_for_stream(dc, updates, num_plane,
5864− &stream_update, status);
5806+ if (!state->allow_modeset)
5807+ continue;
58655808
5866− if (update_type > UPDATE_TYPE_MED) {
5867− update_type = UPDATE_TYPE_FULL;
5868− goto cleanup;
5869− }
5809+ if (crtc != new_plane_crtc)
5810+ continue;
5811+
5812+ updates[num_plane].surface = &surface[num_plane];
5813+
5814+ if (new_crtc_state->mode_changed) {
5815+ updates[num_plane].surface->src_rect =
5816+ new_dm_plane_state->dc_state->src_rect;
5817+ updates[num_plane].surface->dst_rect =
5818+ new_dm_plane_state->dc_state->dst_rect;
5819+ updates[num_plane].surface->rotation =
5820+ new_dm_plane_state->dc_state->rotation;
5821+ updates[num_plane].surface->in_transfer_func =
5822+ new_dm_plane_state->dc_state->in_transfer_func;
5823+ stream_update.dst = new_dm_crtc_state->stream->dst;
5824+ stream_update.src = new_dm_crtc_state->stream->src;
5825+ }
5826+
5827+ if (new_crtc_state->color_mgmt_changed) {
5828+ updates[num_plane].gamma =
5829+ new_dm_plane_state->dc_state->gamma_correction;
5830+ updates[num_plane].in_transfer_func =
5831+ new_dm_plane_state->dc_state->in_transfer_func;
5832+ stream_update.gamut_remap =
5833+ &new_dm_crtc_state->stream->gamut_remap_matrix;
5834+ stream_update.out_transfer_func =
5835+ new_dm_crtc_state->stream->out_transfer_func;
58705836 }
58715837
5872− } else if (!new_dm_crtc_state->stream && old_dm_crtc_state->stream) {
5838+ num_plane++;
5839+ }
5840+
5841+ if (num_plane == 0)
5842+ continue;
5843+
5844+ ret = dm_atomic_get_state(state, &dm_state);
5845+ if (ret)
5846+ goto cleanup;
5847+
5848+ old_dm_state = dm_atomic_get_old_state(state);
5849+ if (!old_dm_state) {
5850+ ret = -EINVAL;
5851+ goto cleanup;
5852+ }
5853+
5854+ status = dc_stream_get_status_from_state(old_dm_state->context,
5855+ new_dm_crtc_state->stream);
5856+
5857+ update_type = dc_check_update_surfaces_for_stream(dc, updates, num_plane,
5858+ &stream_update, status);
5859+
5860+ if (update_type > UPDATE_TYPE_MED) {
58735861 update_type = UPDATE_TYPE_FULL;
58745862 goto cleanup;
58755863 }
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c+5−0
@@ -174,6 +174,11 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) · 173 unmodified lines
174174 aconnector->edid = edid;
175175 }
176176
177+ if (aconnector->dc_sink && aconnector->dc_sink->sink_signal == SIGNAL_TYPE_VIRTUAL) {
178+ dc_sink_release(aconnector->dc_sink);
179+ aconnector->dc_sink = NULL;
180+ }
181+
177182 if (!aconnector->dc_sink) {
178183 struct dc_sink *dc_sink;
179184 struct dc_sink_init_data init_params = {
drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c+1−1
@@ -63,7 +63,7 @@ void scaler_settings_calculation(struct dcn_bw_internal_vars *v) · 62 unmodified lines
6363 if (v->interlace_output[k] == 1.0) {
6464 v->v_ratio[k] = 2.0 * v->v_ratio[k];
6565 }
66− if ((v->underscan_output[k] == 1.0)) {
66+ if (v->underscan_output[k] == 1.0) {
6767 v->h_ratio[k] = v->h_ratio[k] * v->under_scan_factor;
6868 v->v_ratio[k] = v->v_ratio[k] * v->under_scan_factor;
6969 }
drivers/gpu/drm/amd/display/dc/core/dc.c+171−18
@@ -621,7 +621,6 @@ static bool construct(struct dc *dc, · 620 unmodified lines
621621 #endif
622622
623623 enum dce_version dc_version = DCE_VERSION_UNKNOWN;
624−
625624 dc_dceip = kzalloc(sizeof(*dc_dceip), GFP_KERNEL);
626625 if (!dc_dceip) {
627626 dm_error("%s: failed to create dceip\n", __func__);
@@ -869,8 +868,9 @@ static void program_timing_sync( · 241 unmodified lines
869868 struct dc *dc,
870869 struct dc_state *ctx)
871870 {
872− int i, j;
871+ int i, j, k;
873872 int group_index = 0;
873+ int num_group = 0;
874874 int pipe_count = dc->res_pool->pipe_count;
875875 struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL };
876876
@@ -907,11 +907,11 @@ static void program_timing_sync( · 30 unmodified lines
907907 }
908908 }
909909
910− /* set first unblanked pipe as master */
910+ /* set first pipe with plane as master */
911911 for (j = 0; j < group_size; j++) {
912912 struct pipe_ctx *temp;
913913
914− if (pipe_set[j]->stream_res.tg->funcs->is_blanked && !pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg)) {
914+ if (pipe_set[j]->plane_state) {
915915 if (j == 0)
916916 break;
917917
@@ -922,9 +922,21 @@ static void program_timing_sync( · 4 unmodified lines
922922 }
923923 }
924924
925− /* remove any other unblanked pipes as they have already been synced */
925+
926+ for (k = 0; k < group_size; k++) {
927+ struct dc_stream_status *status = dc_stream_get_status_from_state(ctx, pipe_set[k]->stream);
928+
929+ status->timing_sync_info.group_id = num_group;
930+ status->timing_sync_info.group_size = group_size;
931+ if (k == 0)
932+ status->timing_sync_info.master = true;
933+ else
934+ status->timing_sync_info.master = false;
935+
936+ }
937+ /* remove any other pipes with plane as they have already been synced */
926938 for (j = j + 1; j < group_size; j++) {
927− if (pipe_set[j]->stream_res.tg->funcs->is_blanked && !pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg)) {
939+ if (pipe_set[j]->plane_state) {
928940 group_size--;
929941 pipe_set[j] = pipe_set[group_size];
930942 j--;
@@ -936,6 +948,7 @@ static void program_timing_sync( · 5 unmodified lines
936948 dc, group_index, group_size, pipe_set);
937949 group_index++;
938950 }
951+ num_group++;
939952 }
940953 }
941954
@@ -956,6 +969,52 @@ static bool context_changed( · 14 unmodified lines
956969 return false;
957970 }
958971
972+bool dc_validate_seamless_boot_timing(struct dc *dc,
973+ const struct dc_sink *sink,
974+ struct dc_crtc_timing *crtc_timing)
975+{
976+ struct timing_generator *tg;
977+ struct dc_link *link = sink->link;
978+ unsigned int inst;
979+
980+ /* Check for enabled DIG to identify enabled display */
981+ if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
982+ return false;
983+
984+ /* Check for which front end is used by this encoder.
985+ * Note the inst is 1 indexed, where 0 is undefined.
986+ * Note that DIG_FE can source from different OTG but our
987+ * current implementation always map 1-to-1, so this code makes
988+ * the same assumption and doesn't check OTG source.
989+ */
990+ inst = link->link_enc->funcs->get_dig_frontend(link->link_enc) - 1;
991+
992+ /* Instance should be within the range of the pool */
993+ if (inst >= dc->res_pool->pipe_count)
994+ return false;
995+
996+ tg = dc->res_pool->timing_generators[inst];
997+
998+ if (!tg->funcs->is_matching_timing)
999+ return false;
1000+
1001+ if (!tg->funcs->is_matching_timing(tg, crtc_timing))
1002+ return false;
1003+
1004+ if (dc_is_dp_signal(link->connector_signal)) {
1005+ unsigned int pix_clk_100hz;
1006+
1007+ dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(
1008+ dc->res_pool->dp_clock_source,
1009+ inst, &pix_clk_100hz);
1010+
1011+ if (crtc_timing->pix_clk_100hz != pix_clk_100hz)
1012+ return false;
1013+ }
1014+
1015+ return true;
1016+}
1017+
9591018 bool dc_enable_stereo(
9601019 struct dc *dc,
9611020 struct dc_state *context,
@@ -1037,6 +1096,9 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c · 75 unmodified lines
10371096 const struct dc_link *link = context->streams[i]->link;
10381097 struct dc_stream_status *status;
10391098
1099+ if (context->streams[i]->apply_seamless_boot_optimization)
1100+ context->streams[i]->apply_seamless_boot_optimization = false;
1101+
10401102 if (!context->streams[i]->mode_changed)
10411103 continue;
10421104
@@ -1112,6 +1174,9 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc) · 69 unmodified lines
11121174 int i;
11131175 struct dc_state *context = dc->current_state;
11141176
1177+ if (dc->optimized_required == false)
1178+ return true;
1179+
11151180 post_surface_trace(dc);
11161181
11171182 for (i = 0; i < dc->res_pool->pipe_count; i++)
@@ -1440,6 +1505,101 @@ static struct dc_stream_status *stream_get_status( · 322 unmodified lines
14401505
14411506 static const enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL;
14421507
1508+static void copy_surface_update_to_plane(
1509+ struct dc_plane_state *surface,
1510+ struct dc_surface_update *srf_update)
1511+{
1512+ if (srf_update->flip_addr) {
1513+ surface->address = srf_update->flip_addr->address;
1514+ surface->flip_immediate =
1515+ srf_update->flip_addr->flip_immediate;
1516+ surface->time.time_elapsed_in_us[surface->time.index] =
1517+ srf_update->flip_addr->flip_timestamp_in_us -
1518+ surface->time.prev_update_time_in_us;
1519+ surface->time.prev_update_time_in_us =
1520+ srf_update->flip_addr->flip_timestamp_in_us;
1521+ surface->time.index++;
1522+ if (surface->time.index >= DC_PLANE_UPDATE_TIMES_MAX)
1523+ surface->time.index = 0;
1524+ }
1525+
1526+ if (srf_update->scaling_info) {
1527+ surface->scaling_quality =
1528+ srf_update->scaling_info->scaling_quality;
1529+ surface->dst_rect =
1530+ srf_update->scaling_info->dst_rect;
1531+ surface->src_rect =
1532+ srf_update->scaling_info->src_rect;
1533+ surface->clip_rect =
1534+ srf_update->scaling_info->clip_rect;
1535+ }
1536+
1537+ if (srf_update->plane_info) {
1538+ surface->color_space =
1539+ srf_update->plane_info->color_space;
1540+ surface->format =
1541+ srf_update->plane_info->format;
1542+ surface->plane_size =
1543+ srf_update->plane_info->plane_size;
1544+ surface->rotation =
1545+ srf_update->plane_info->rotation;
1546+ surface->horizontal_mirror =
1547+ srf_update->plane_info->horizontal_mirror;
1548+ surface->stereo_format =
1549+ srf_update->plane_info->stereo_format;
1550+ surface->tiling_info =
1551+ srf_update->plane_info->tiling_info;
1552+ surface->visible =
1553+ srf_update->plane_info->visible;
1554+ surface->per_pixel_alpha =
1555+ srf_update->plane_info->per_pixel_alpha;
1556+ surface->global_alpha =
1557+ srf_update->plane_info->global_alpha;
1558+ surface->global_alpha_value =
1559+ srf_update->plane_info->global_alpha_value;
1560+ surface->dcc =
1561+ srf_update->plane_info->dcc;
1562+ surface->sdr_white_level =
1563+ srf_update->plane_info->sdr_white_level;
1564+ }
1565+
1566+ if (srf_update->gamma &&
1567+ (surface->gamma_correction !=
1568+ srf_update->gamma)) {
1569+ memcpy(&surface->gamma_correction->entries,
1570+ &srf_update->gamma->entries,
1571+ sizeof(struct dc_gamma_entries));
1572+ surface->gamma_correction->is_identity =
1573+ srf_update->gamma->is_identity;
1574+ surface->gamma_correction->num_entries =
1575+ srf_update->gamma->num_entries;
1576+ surface->gamma_correction->type =
1577+ srf_update->gamma->type;
1578+ }
1579+
1580+ if (srf_update->in_transfer_func &&
1581+ (surface->in_transfer_func !=
1582+ srf_update->in_transfer_func)) {
1583+ surface->in_transfer_func->sdr_ref_white_level =
1584+ srf_update->in_transfer_func->sdr_ref_white_level;
1585+ surface->in_transfer_func->tf =
1586+ srf_update->in_transfer_func->tf;
1587+ surface->in_transfer_func->type =
1588+ srf_update->in_transfer_func->type;
1589+ memcpy(&surface->in_transfer_func->tf_pts,
1590+ &srf_update->in_transfer_func->tf_pts,
1591+ sizeof(struct dc_transfer_func_distributed_points));
1592+ }
1593+
1594+ if (srf_update->input_csc_color_matrix)
1595+ surface->input_csc_color_matrix =
1596+ *srf_update->input_csc_color_matrix;
1597+
1598+ if (srf_update->coeff_reduction_factor)
1599+ surface->coeff_reduction_factor =
1600+ *srf_update->coeff_reduction_factor;
1601+}
1602+
14431603 static void commit_planes_do_stream_update(struct dc *dc,
14441604 struct dc_stream_state *stream,
14451605 struct dc_stream_update *stream_update,
@@ -1463,13 +1623,13 @@ static void commit_planes_do_stream_update(struct dc *dc, · 17 unmodified lines
14631623 stream_update->adjust->v_total_min,
14641624 stream_update->adjust->v_total_max);
14651625
1466− if (stream_update->vline0_config && pipe_ctx->stream_res.tg->funcs->program_vline_interrupt)
1626+ if (stream_update->periodic_vsync_config && pipe_ctx->stream_res.tg->funcs->program_vline_interrupt)
14671627 pipe_ctx->stream_res.tg->funcs->program_vline_interrupt(
1468− pipe_ctx->stream_res.tg, VLINE0, stream->vline0_config);
1628+ pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, VLINE0, &stream->periodic_vsync_config);
14691629
1470− if (stream_update->vline1_config && pipe_ctx->stream_res.tg->funcs->program_vline_interrupt)
1630+ if (stream_update->enhanced_sync_config && pipe_ctx->stream_res.tg->funcs->program_vline_interrupt)
14711631 pipe_ctx->stream_res.tg->funcs->program_vline_interrupt(
1472− pipe_ctx->stream_res.tg, VLINE1, stream->vline1_config);
1632+ pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, VLINE1, &stream->enhanced_sync_config);
14731633
14741634 if ((stream_update->hdr_static_metadata && !stream->use_dynamic_meta) ||
14751635 stream_update->vrr_infopacket ||
@@ -1645,14 +1805,7 @@ void dc_commit_updates_for_stream(struct dc *dc, · 169 unmodified lines
16451805 for (i = 0; i < surface_count; i++) {
16461806 struct dc_plane_state *surface = srf_updates[i].surface;
16471807
1648− /* TODO: On flip we don't build the state, so it still has the
1649− * old address. Which is why we are updating the address here
1650− */
1651− if (srf_updates[i].flip_addr) {
1652− surface->address = srf_updates[i].flip_addr->address;
1653− surface->flip_immediate = srf_updates[i].flip_addr->flip_immediate;
1654−
1655− }
1808+ copy_surface_update_to_plane(surface, &srf_updates[i]);
16561809
16571810 if (update_type >= UPDATE_TYPE_MED) {
16581811 for (j = 0; j < dc->res_pool->pipe_count; j++) {
drivers/gpu/drm/amd/display/dc/core/dc_link.c+39−27
@@ -76,6 +76,12 @@ static void destruct(struct dc_link *link) · 75 unmodified lines
7676 {
7777 int i;
7878
79+ if (link->hpd_gpio != NULL) {
80+ dal_gpio_close(link->hpd_gpio);
81+ dal_gpio_destroy_irq(&link->hpd_gpio);
82+ link->hpd_gpio = NULL;
83+ }
84+
7985 if (link->ddc)
8086 dal_ddc_service_destroy(&link->ddc);
8187
@@ -931,18 +937,11 @@ bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason) · 849 unmodified lines
931937
932938 bool dc_link_get_hpd_state(struct dc_link *dc_link)
933939 {
934− struct gpio *hpd_pin;
935940 uint32_t state;
936941
937− hpd_pin = get_hpd_gpio(dc_link->ctx->dc_bios,
938− dc_link->link_id, dc_link->ctx->gpio_service);
939− if (hpd_pin == NULL)
940− ASSERT(false);
941−
942− dal_gpio_open(hpd_pin, GPIO_MODE_INTERRUPT);
943− dal_gpio_get_value(hpd_pin, &state);
944− dal_gpio_close(hpd_pin);
945− dal_gpio_destroy_irq(&hpd_pin);
942+ dal_gpio_lock_pin(dc_link->hpd_gpio);
943+ dal_gpio_get_value(dc_link->hpd_gpio, &state);
944+ dal_gpio_unlock_pin(dc_link->hpd_gpio);
946945
947946 return state;
948947 }
@@ -1098,7 +1097,6 @@ static bool construct( · 149 unmodified lines
10981097 const struct link_init_data *init_params)
10991098 {
11001099 uint8_t i;
1101− struct gpio *hpd_gpio = NULL;
11021100 struct ddc_service_init_data ddc_service_init_data = { { 0 } };
11031101 struct dc_context *dc_ctx = init_params->ctx;
11041102 struct encoder_init_data enc_init_data = { 0 };
@@ -1128,10 +1126,12 @@ static bool construct( · 23 unmodified lines
11281126 if (link->dc->res_pool->funcs->link_init)
11291127 link->dc->res_pool->funcs->link_init(link);
11301128
1131− hpd_gpio = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
1132−
1133− if (hpd_gpio != NULL)
1134− link->irq_source_hpd = dal_irq_get_source(hpd_gpio);
1129+ link->hpd_gpio = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
1130+ if (link->hpd_gpio != NULL) {
1131+ dal_gpio_open(link->hpd_gpio, GPIO_MODE_INTERRUPT);
1132+ dal_gpio_unlock_pin(link->hpd_gpio);
1133+ link->irq_source_hpd = dal_irq_get_source(link->hpd_gpio);
1134+ }
11351135
11361136 switch (link->link_id.id) {
11371137 case CONNECTOR_ID_HDMI_TYPE_A:
@@ -1149,18 +1149,18 @@ static bool construct( · 11 unmodified lines
11491149 case CONNECTOR_ID_DISPLAY_PORT:
11501150 link->connector_signal = SIGNAL_TYPE_DISPLAY_PORT;
11511151
1152− if (hpd_gpio != NULL)
1152+ if (link->hpd_gpio != NULL)
11531153 link->irq_source_hpd_rx =
1154− dal_irq_get_rx_source(hpd_gpio);
1154+ dal_irq_get_rx_source(link->hpd_gpio);
11551155
11561156 break;
11571157 case CONNECTOR_ID_EDP:
11581158 link->connector_signal = SIGNAL_TYPE_EDP;
11591159
1160− if (hpd_gpio != NULL) {
1160+ if (link->hpd_gpio != NULL) {
11611161 link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
11621162 link->irq_source_hpd_rx =
1163− dal_irq_get_rx_source(hpd_gpio);
1163+ dal_irq_get_rx_source(link->hpd_gpio);
11641164 }
11651165 break;
11661166 case CONNECTOR_ID_LVDS:
@@ -1171,10 +1171,7 @@ static bool construct( · 4 unmodified lines
11711171 goto create_fail;
11721172 }
11731173
1174− if (hpd_gpio != NULL) {
1175− dal_gpio_destroy_irq(&hpd_gpio);
1176− hpd_gpio = NULL;
1177− }
1174+
11781175
11791176 /* TODO: #DAL3 Implement id to str function.*/
11801177 LINK_INFO("Connector[%d] description:"
@@ -1277,8 +1274,9 @@ link_enc_create_fail: · 96 unmodified lines
12771274 ddc_create_fail:
12781275 create_fail:
12791276
1280− if (hpd_gpio != NULL) {
1281− dal_gpio_destroy_irq(&hpd_gpio);
1277+ if (link->hpd_gpio != NULL) {
1278+ dal_gpio_destroy_irq(&link->hpd_gpio);
1279+ link->hpd_gpio = NULL;
12821280 }
12831281
12841282 return false;
@@ -2582,13 +2580,23 @@ void core_link_enable_stream( · 1297 unmodified lines
25822580 &stream->timing);
25832581
25842582 if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
2583+ bool apply_edp_fast_boot_optimization =
2584+ pipe_ctx->stream->apply_edp_fast_boot_optimization;
2585+
2586+ pipe_ctx->stream->apply_edp_fast_boot_optimization = false;
2587+
25852588 resource_build_info_frame(pipe_ctx);
25862589 core_dc->hwss.update_info_frame(pipe_ctx);
25872590
2591+ /* Do not touch link on seamless boot optimization. */
2592+ if (pipe_ctx->stream->apply_seamless_boot_optimization) {
2593+ pipe_ctx->stream->dpms_off = false;
2594+ return;
2595+ }
2596+
25882597 /* eDP lit up by bios already, no need to enable again. */
25892598 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
2590− pipe_ctx->stream->apply_edp_fast_boot_optimization) {
2591− pipe_ctx->stream->apply_edp_fast_boot_optimization = false;
2599+ apply_edp_fast_boot_optimization) {
25922600 pipe_ctx->stream->dpms_off = false;
25932601 return;
25942602 }
@@ -2615,6 +2623,8 @@ void core_link_enable_stream( · 20 unmodified lines
26152623 }
26162624 }
26172625
2626+ stream->link->link_status.link_active = true;
2627+
26182628 core_dc->hwss.enable_audio_stream(pipe_ctx);
26192629
26202630 /* turn off otg test pattern if enable */
@@ -2649,6 +2659,8 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx, int option) · 28 unmodified lines
26492659 core_dc->hwss.disable_stream(pipe_ctx, option);
26502660
26512661 disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);
2662+
2663+ pipe_ctx->stream->link->link_status.link_active = false;
26522664 }
26532665
26542666 void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c+4−35
@@ -47,7 +47,9 @@ static void wait_for_training_aux_rd_interval( · 46 unmodified lines
4747 struct dc_link *link,
4848 uint32_t default_wait_in_micro_secs)
4949 {
50− union training_aux_rd_interval training_rd_interval = {0};
50+ union training_aux_rd_interval training_rd_interval;
51+
52+ memset(&training_rd_interval, 0, sizeof(training_rd_interval));
5153
5254 /* overwrite the delay if rev > 1.1*/
5355 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
@@ -2538,7 +2540,6 @@ void detect_edp_sink_caps(struct dc_link *link) · 2484 unmodified lines
25382540 uint32_t entry;
25392541 uint32_t link_rate_in_khz;
25402542 enum dc_link_rate link_rate = LINK_RATE_UNKNOWN;
2541− uint8_t link_rate_set = 0;
25422543
25432544 retrieve_link_cap(link);
25442545
@@ -2558,39 +2559,7 @@ void detect_edp_sink_caps(struct dc_link *link) · 13 unmodified lines
25582559 link_rate = linkRateInKHzToLinkRateMultiplier(link_rate_in_khz);
25592560 if (link->reported_link_cap.link_rate < link_rate) {
25602561 link->reported_link_cap.link_rate = link_rate;
2561−
2562− switch (link_rate) {
2563− case LINK_RATE_LOW:
2564− link_rate_set = 1;
2565− break;
2566− case LINK_RATE_RATE_2:
2567− link_rate_set = 2;
2568− break;
2569− case LINK_RATE_RATE_3:
2570− link_rate_set = 3;
2571− break;
2572− case LINK_RATE_HIGH:
2573− link_rate_set = 4;
2574− break;
2575− case LINK_RATE_RBR2:
2576− link_rate_set = 5;
2577− break;
2578− case LINK_RATE_RATE_6:
2579− link_rate_set = 6;
2580− break;
2581− case LINK_RATE_HIGH2:
2582− link_rate_set = 7;
2583− break;
2584− case LINK_RATE_HIGH3:
2585− link_rate_set = 8;
2586− break;
2587− default:
2588− link_rate_set = 0;
2589− break;
2590− }
2591−
2592− if (link->dpcd_caps.link_rate_set < link_rate_set)
2593− link->dpcd_caps.link_rate_set = link_rate_set;
2562+ link->dpcd_caps.link_rate_set = entry;
25942563 }
25952564 }
25962565 }
drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c+4−0
@@ -119,6 +119,10 @@ bool edp_receiver_ready_T9(struct dc_link *link) · 118 unmodified lines
119119 break;
120120 udelay(100); //MAx T9
121121 } while (++tries < 50);
122+
123+ if (link->local_sink->edid_caps.panel_patch.extra_delay_backlight_off > 0)
124+ udelay(link->local_sink->edid_caps.panel_patch.extra_delay_backlight_off * 1000);
125+
122126 return result;
123127 }
124128 bool edp_receiver_ready_T7(struct dc_link *link)
drivers/gpu/drm/amd/display/dc/core/dc_resource.c+54−2
@@ -1800,6 +1800,51 @@ static void calculate_phy_pix_clks(struct dc_stream_state *stream) · 1799 unmodified lines
18001800 stream->phy_pix_clk *= 2;
18011801 }
18021802
1803+static int acquire_resource_from_hw_enabled_state(
1804+ struct resource_context *res_ctx,
1805+ const struct resource_pool *pool,
1806+ struct dc_stream_state *stream)
1807+{
1808+ struct dc_link *link = stream->link;
1809+ unsigned int inst;
1810+
1811+ /* Check for enabled DIG to identify enabled display */
1812+ if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
1813+ return -1;
1814+
1815+ /* Check for which front end is used by this encoder.
1816+ * Note the inst is 1 indexed, where 0 is undefined.
1817+ * Note that DIG_FE can source from different OTG but our
1818+ * current implementation always map 1-to-1, so this code makes
1819+ * the same assumption and doesn't check OTG source.
1820+ */
1821+ inst = link->link_enc->funcs->get_dig_frontend(link->link_enc) - 1;
1822+
1823+ /* Instance should be within the range of the pool */
1824+ if (inst >= pool->pipe_count)
1825+ return -1;
1826+
1827+ if (!res_ctx->pipe_ctx[inst].stream) {
1828+ struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[inst];
1829+
1830+ pipe_ctx->stream_res.tg = pool->timing_generators[inst];
1831+ pipe_ctx->plane_res.mi = pool->mis[inst];
1832+ pipe_ctx->plane_res.hubp = pool->hubps[inst];
1833+ pipe_ctx->plane_res.ipp = pool->ipps[inst];
1834+ pipe_ctx->plane_res.xfm = pool->transforms[inst];
1835+ pipe_ctx->plane_res.dpp = pool->dpps[inst];
1836+ pipe_ctx->stream_res.opp = pool->opps[inst];
1837+ if (pool->dpps[inst])
1838+ pipe_ctx->plane_res.mpcc_inst = pool->dpps[inst]->inst;
1839+ pipe_ctx->pipe_idx = inst;
1840+
1841+ pipe_ctx->stream = stream;
1842+ return inst;
1843+ }
1844+
1845+ return -1;
1846+}
1847+
18031848 enum dc_status resource_map_pool_resources(
18041849 const struct dc *dc,
18051850 struct dc_state *context,
@@ -1824,8 +1869,15 @@ enum dc_status resource_map_pool_resources( · 18 unmodified lines
18241869
18251870 calculate_phy_pix_clks(stream);
18261871
1827− /* acquire new resources */
1828− pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream);
1872+ if (stream->apply_seamless_boot_optimization)
1873+ pipe_idx = acquire_resource_from_hw_enabled_state(
1874+ &context->res_ctx,
1875+ pool,
1876+ stream);
1877+
1878+ if (pipe_idx < 0)
1879+ /* acquire new resources */
1880+ pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream);
18291881
18301882 #ifdef CONFIG_DRM_AMD_DC_DCN1_0
18311883 if (pipe_idx < 0)
drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c+7−11
@@ -112,16 +112,12 @@ uint8_t get_vmid_for_ptb(struct vm_helper *vm_helper, int64_t ptb, uint8_t hubp_ · 111 unmodified lines
112112 return vmid;
113113 }
114114
115−struct vm_helper init_vm_helper(unsigned int num_vmid, unsigned int num_hubp)
115+void init_vm_helper(struct vm_helper *vm_helper, unsigned int num_vmid, unsigned int num_hubp)
116116 {
117− static uint64_t ptb_assigned_to_vmid[MAX_VMID];
118− static struct vmid_usage hubp_vmid_usage[MAX_HUBP];
119−
120− return (struct vm_helper){
121− .num_vmid = num_vmid,
122− .num_hubp = num_hubp,
123− .num_vmids_available = num_vmid - 1,
124− .ptb_assigned_to_vmid = ptb_assigned_to_vmid,
125− .hubp_vmid_usage = hubp_vmid_usage
126− };
117+ vm_helper->num_vmid = num_vmid;
118+ vm_helper->num_hubp = num_hubp;
119+ vm_helper->num_vmids_available = num_vmid - 1;
120+
121+ memset(vm_helper->hubp_vmid_usage, 0, sizeof(vm_helper->hubp_vmid_usage[0]) * MAX_HUBP);
122+ memset(vm_helper->ptb_assigned_to_vmid, 0, sizeof(vm_helper->ptb_assigned_to_vmid[0]) * MAX_VMID);
127123 }
drivers/gpu/drm/amd/display/dc/dc.h+6−2
@@ -39,7 +39,7 @@ · 38 unmodified lines
3939 #include "inc/hw/dmcu.h"
4040 #include "dml/display_mode_lib.h"
4141
42−#define DC_VER "3.2.15"
42+#define DC_VER "3.2.17"
4343
4444 #define MAX_SURFACES 3
4545 #define MAX_STREAMS 6
@@ -255,6 +255,7 @@ struct dc_debug_options { · 209 unmodified lines
255255 bool scl_reset_length10;
256256 bool hdmi20_disable;
257257 bool skip_detection_link_training;
258+ unsigned int force_odm_combine; //bit vector based on otg inst
258259 unsigned int force_fclk_khz;
259260 };
260261
@@ -264,7 +265,6 @@ struct dc_debug_data { · 3 unmodified lines
264265 uint32_t auxErrorCount;
265266 };
266267
267−
268268 struct dc_state;
269269 struct resource_pool;
270270 struct dce_hwseq;
@@ -594,6 +594,10 @@ struct dc_validation_set { · 323 unmodified lines
594594 uint8_t plane_count;
595595 };
596596
597+bool dc_validate_seamless_boot_timing(struct dc *dc,
598+ const struct dc_sink *sink,
599+ struct dc_crtc_timing *crtc_timing);
600+
597601 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);
598602
599603 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info);
drivers/gpu/drm/amd/display/dc/dc_link.h+2−0
@@ -30,6 +30,7 @@ · 29 unmodified lines
3030 #include "grph_object_defs.h"
3131
3232 struct dc_link_status {
33+ bool link_active;
3334 struct dpcd_caps *dpcd_caps;
3435 };
3536
@@ -125,6 +126,7 @@ struct dc_link { · 89 unmodified lines
125126 struct dc_link_status link_status;
126127
127128 struct link_trace link_trace;
129+ struct gpio *hpd_gpio;
128130 };
129131
130132 const struct dc_link_status *dc_link_get_status(const struct dc_link *dc_link);
drivers/gpu/drm/amd/display/dc/dc_stream.h+17−8
@@ -32,11 +32,17 @@ · 31 unmodified lines
3232 /*******************************************************************************
3333 * Stream Interfaces
3434 ******************************************************************************/
35+struct timing_sync_info {
36+ int group_id;
37+ int group_size;
38+ bool master;
39+};
3540
3641 struct dc_stream_status {
3742 int primary_otg_inst;
3843 int stream_enc_inst;
3944 int plane_count;
45+ struct timing_sync_info timing_sync_info;
4046 struct dc_plane_state *plane_states[MAX_SURFACE_NUM];
4147 };
4248
@@ -45,11 +51,12 @@ struct freesync_context { · 2 unmodified lines
4551 bool dummy;
4652 };
4753
48−struct vline_config {
49− unsigned int start_line;
50− unsigned int end_line;
54+union vline_config {
55+ unsigned int line_number;
56+ unsigned long long delta_in_ns;
5157 };
5258
59+
5360 struct dc_stream_state {
5461 // sink is deprecated, new code should not reference
5562 // this pointer
@@ -99,8 +106,8 @@ struct dc_stream_state { · 43 unmodified lines
99106 /* DMCU info */
100107 unsigned int abm_level;
101108
102− struct vline_config vline0_config;
103− struct vline_config vline1_config;
109+ union vline_config periodic_vsync_config;
110+ union vline_config enhanced_sync_config;
104111
105112 /* from core_stream struct */
106113 struct dc_context *ctx;
@@ -112,7 +119,6 @@ struct dc_stream_state { · 5 unmodified lines
112119 int phy_pix_clk;
113120 enum signal_type signal;
114121 bool dpms_off;
115− bool apply_edp_fast_boot_optimization;
116122
117123 void *dm_stream_context;
118124
@@ -139,6 +145,9 @@ struct dc_stream_state { · 20 unmodified lines
139145 uint8_t otg_offset;
140146 } out;
141147
148+ bool apply_edp_fast_boot_optimization;
149+ bool apply_seamless_boot_optimization;
150+
142151 uint32_t stream_id;
143152 };
144153
@@ -149,8 +158,8 @@ struct dc_stream_update { · 4 unmodified lines
149158 struct dc_info_packet *hdr_static_metadata;
150159 unsigned int *abm_level;
151160
152− struct vline_config *vline0_config;
153− struct vline_config *vline1_config;
161+ union vline_config *periodic_vsync_config;
162+ union vline_config *enhanced_sync_config;
154163
155164 struct dc_crtc_timing_adjust *adjust;
156165 struct dc_info_packet *vrr_infopacket;
drivers/gpu/drm/amd/display/dc/dc_types.h+1−0
@@ -201,6 +201,7 @@ union display_content_support { · 200 unmodified lines
201201 struct dc_panel_patch {
202202 unsigned int dppowerup_delay;
203203 unsigned int extra_t12_ms;
204+ unsigned int extra_delay_backlight_off;
204205 };
205206
206207 struct dc_edid_caps {
drivers/gpu/drm/amd/display/dc/dce/dce_abm.c+2−2
@@ -314,8 +314,8 @@ static bool dce_abm_immediate_disable(struct abm *abm) · 313 unmodified lines
314314
315315 /* setDMCUParam_ABMLevel */
316316 REG_UPDATE_2(MASTER_COMM_CMD_REG,
317− MASTER_COMM_CMD_REG_BYTE0, MCP_ABM_LEVEL_SET,
318− MASTER_COMM_CMD_REG_BYTE2, MCP_DISABLE_ABM_IMMEDIATELY);
317+ MASTER_COMM_CMD_REG_BYTE0, MCP_ABM_PIPE_SET,
318+ MASTER_COMM_CMD_REG_BYTE1, MCP_DISABLE_ABM_IMMEDIATELY);
319319
320320 /* notifyDMCUMsg */
321321 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c+1−1
@@ -516,7 +516,7 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc, · 515 unmodified lines
516516 }
517517 }
518518
519− msleep(1);
519+ udelay(1000);
520520 }
521521 return false;
522522 }
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c+26−2
@@ -977,6 +977,28 @@ static bool dce110_clock_source_power_down( · 976 unmodified lines
977977 return bp_result == BP_RESULT_OK;
978978 }
979979
980+static bool get_pixel_clk_frequency_100hz(
981+ struct clock_source *clock_source,
982+ unsigned int inst,
983+ unsigned int *pixel_clk_khz)
984+{
985+ struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
986+ unsigned int clock_hz = 0;
987+
988+ if (clock_source->id == CLOCK_SOURCE_ID_DP_DTO) {
989+ clock_hz = REG_READ(PHASE[inst]);
990+
991+ /* NOTE: There is agreement with VBIOS here that MODULO is
992+ * programmed equal to DPREFCLK, in which case PHASE will be
993+ * equivalent to pixel clock.
994+ */
995+ *pixel_clk_khz = clock_hz / 100;
996+ return true;
997+ }
998+
999+ return false;
1000+}
1001+
9801002 /*****************************************/
9811003 /* Constructor */
9821004 /*****************************************/
@@ -984,12 +1006,14 @@ static bool dce110_clock_source_power_down( · 1 unmodified line
9841006 static const struct clock_source_funcs dce112_clk_src_funcs = {
9851007 .cs_power_down = dce110_clock_source_power_down,
9861008 .program_pix_clk = dce112_program_pix_clk,
987− .get_pix_clk_dividers = dce112_get_pix_clk_dividers
1009+ .get_pix_clk_dividers = dce112_get_pix_clk_dividers,
1010+ .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz
9881011 };
9891012 static const struct clock_source_funcs dce110_clk_src_funcs = {
9901013 .cs_power_down = dce110_clock_source_power_down,
9911014 .program_pix_clk = dce110_program_pix_clk,
992− .get_pix_clk_dividers = dce110_get_pix_clk_dividers
1015+ .get_pix_clk_dividers = dce110_get_pix_clk_dividers,
1016+ .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz
9931017 };
9941018
9951019
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c+32−20
@@ -1032,8 +1032,7 @@ void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, · 1031 unmodified lines
10321032 struct dc_link *link = stream->link;
10331033
10341034 /* only 3 items below are used by unblank */
1035− params.pixel_clk_khz =
1036− pipe_ctx->stream->timing.pix_clk_100hz / 10;
1035+ params.pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10;
10371036 params.link_settings.link_rate = link_settings->link_rate;
10381037
10391038 if (dc_is_dp_signal(pipe_ctx->stream->signal))
@@ -1043,6 +1042,7 @@ void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, · 3 unmodified lines
10431042 link->dc->hwss.edp_backlight_control(link, true);
10441043 }
10451044 }
1045+
10461046 void dce110_blank_stream(struct pipe_ctx *pipe_ctx)
10471047 {
10481048 struct dc_stream_state *stream = pipe_ctx->stream;
@@ -1250,8 +1250,6 @@ static enum dc_status dce110_enable_stream_timing( · 201 unmodified lines
12501250 struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx.
12511251 pipe_ctx[pipe_ctx->pipe_idx];
12521252 struct tg_color black_color = {0};
1253− struct drr_params params = {0};
1254− unsigned int event_triggers = 0;
12551253
12561254 if (!pipe_ctx_old->stream) {
12571255
@@ -1280,20 +1278,6 @@ static enum dc_status dce110_enable_stream_timing( · 22 unmodified lines
12801278 pipe_ctx->stream_res.tg,
12811279 &stream->timing,
12821280 true);
1283−
1284− params.vertical_total_min = stream->adjust.v_total_min;
1285− params.vertical_total_max = stream->adjust.v_total_max;
1286− if (pipe_ctx->stream_res.tg->funcs->set_drr)
1287− pipe_ctx->stream_res.tg->funcs->set_drr(
1288− pipe_ctx->stream_res.tg, &params);
1289−
1290− // DRR should set trigger event to monitor surface update event
1291− if (stream->adjust.v_total_min != 0 &&
1292− stream->adjust.v_total_max != 0)
1293− event_triggers = 0x80;
1294− if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)
1295− pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
1296− pipe_ctx->stream_res.tg, event_triggers);
12971281 }
12981282
12991283 if (!pipe_ctx_old->stream) {
@@ -1313,6 +1297,8 @@ static enum dc_status apply_single_controller_ctx_to_hw( · 13 unmodified lines
13131297 struct dc *dc)
13141298 {
13151299 struct dc_stream_state *stream = pipe_ctx->stream;
1300+ struct drr_params params = {0};
1301+ unsigned int event_triggers = 0;
13161302
13171303 if (pipe_ctx->stream_res.audio != NULL) {
13181304 struct audio_output audio_output;
@@ -1339,7 +1325,27 @@ static enum dc_status apply_single_controller_ctx_to_hw( · 20 unmodified lines
13391325 }
13401326
13411327 /* */
1342− dc->hwss.enable_stream_timing(pipe_ctx, context, dc);
1328+ /* Do not touch stream timing on seamless boot optimization. */
1329+ if (!pipe_ctx->stream->apply_seamless_boot_optimization)
1330+ dc->hwss.enable_stream_timing(pipe_ctx, context, dc);
1331+
1332+ if (pipe_ctx->stream_res.tg->funcs->program_vupdate_interrupt)
1333+ pipe_ctx->stream_res.tg->funcs->program_vupdate_interrupt(
1334+ pipe_ctx->stream_res.tg,
1335+ &stream->timing);
1336+
1337+ params.vertical_total_min = stream->adjust.v_total_min;
1338+ params.vertical_total_max = stream->adjust.v_total_max;
1339+ if (pipe_ctx->stream_res.tg->funcs->set_drr)
1340+ pipe_ctx->stream_res.tg->funcs->set_drr(
1341+ pipe_ctx->stream_res.tg, &params);
1342+
1343+ // DRR should set trigger event to monitor surface update event
1344+ if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0)
1345+ event_triggers = 0x80;
1346+ if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)
1347+ pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
1348+ pipe_ctx->stream_res.tg, event_triggers);
13431349
13441350 if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL)
13451351 pipe_ctx->stream_res.stream_enc->funcs->dig_connect_to_otg(
@@ -2269,6 +2275,11 @@ static void dce110_enable_per_frame_crtc_position_reset( · 923 unmodified lines
22692275
22702276 }
22712277
2278+static void init_pipes(struct dc *dc, struct dc_state *context)
2279+{
2280+ // Do nothing
2281+}
2282+
22722283 static void init_hw(struct dc *dc)
22732284 {
22742285 int i;
@@ -2535,7 +2546,7 @@ static void dce110_apply_ctx_for_surface( · 260 unmodified lines
25352546 }
25362547
25372548 if (dc->fbc_compressor)
2538− enable_fbc(dc, dc->current_state);
2549+ enable_fbc(dc, context);
25392550 }
25402551
25412552 static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx)
@@ -2636,6 +2647,7 @@ static const struct hw_sequencer_funcs dce110_funcs = { · 94 unmodified lines
26362647 .program_gamut_remap = program_gamut_remap,
26372648 .program_output_csc = program_output_csc,
26382649 .init_hw = init_hw,
2650+ .init_pipes = init_pipes,
26392651 .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
26402652 .apply_ctx_for_surface = dce110_apply_ctx_for_surface,
26412653 .update_plane_addr = update_plane_addr,
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c+11−8
@@ -88,11 +88,18 @@ void hubbub1_wm_read_state(struct hubbub *hubbub, · 87 unmodified lines
8888 s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D);
8989 }
9090
91−void hubbub1_disable_allow_self_refresh(struct hubbub *hubbub)
91+void hubbub1_allow_self_refresh_control(struct hubbub *hubbub, bool allow)
9292 {
9393 struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);
94− REG_UPDATE(DCHUBBUB_ARB_DRAM_STATE_CNTL,
95− DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, 0);
94+
95+ /*
96+ * DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE = 1 means do not allow stutter
97+ * DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE = 0 means allow stutter
98+ */
99+
100+ REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL,
101+ DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, 0,
102+ DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, !allow);
96103 }
97104
98105 bool hububu1_is_allow_self_refresh_enabled(struct hubbub *hubbub)
@@ -262,8 +269,6 @@ void hubbub1_program_watermarks( · 163 unmodified lines
262269 bool safe_to_lower)
263270 {
264271 struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);
265−
266− uint32_t force_en = hubbub1->base.ctx->dc->debug.disable_stutter ? 1 : 0;
267272 /*
268273 * Need to clamp to max of the register values (i.e. no wrap)
269274 * for dcn1, all wm registers are 21-bit wide
@@ -537,9 +542,7 @@ void hubbub1_program_watermarks( · 267 unmodified lines
537542 REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND,
538543 DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 68);
539544
540− REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL,
541− DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, 0,
542− DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, force_en);
545+ hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);
543546
544547 #if 0
545548 REG_UPDATE_2(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h+1−1
@@ -204,7 +204,7 @@ void hubbub1_program_watermarks( · 203 unmodified lines
204204 unsigned int refclk_mhz,
205205 bool safe_to_lower);
206206
207−void hubbub1_disable_allow_self_refresh(struct hubbub *hubbub);
207+void hubbub1_allow_self_refresh_control(struct hubbub *hubbub, bool allow);
208208
209209 bool hububu1_is_allow_self_refresh_enabled(struct hubbub *hubub);
210210
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c+21−2
@@ -1150,9 +1150,28 @@ void hubp1_cursor_set_position( · 1149 unmodified lines
11501150 REG_UPDATE(CURSOR_CONTROL,
11511151 CURSOR_ENABLE, cur_en);
11521152
1153− REG_SET_2(CURSOR_POSITION, 0,
1154− CURSOR_X_POSITION, pos->x,
1153+ //account for cases where we see negative offset relative to overlay plane
1154+ if (src_x_offset < 0 && src_y_offset < 0) {
1155+ REG_SET_2(CURSOR_POSITION, 0,
1156+ CURSOR_X_POSITION, 0,
1157+ CURSOR_Y_POSITION, 0);
1158+ x_hotspot -= src_x_offset;
1159+ y_hotspot -= src_y_offset;
1160+ } else if (src_x_offset < 0) {
1161+ REG_SET_2(CURSOR_POSITION, 0,
1162+ CURSOR_X_POSITION, 0,
11551163 CURSOR_Y_POSITION, pos->y);
1164+ x_hotspot -= src_x_offset;
1165+ } else if (src_y_offset < 0) {
1166+ REG_SET_2(CURSOR_POSITION, 0,
1167+ CURSOR_X_POSITION, pos->x,
1168+ CURSOR_Y_POSITION, 0);
1169+ y_hotspot -= src_y_offset;
1170+ } else {
1171+ REG_SET_2(CURSOR_POSITION, 0,
1172+ CURSOR_X_POSITION, pos->x,
1173+ CURSOR_Y_POSITION, pos->y);
1174+ }
11561175
11571176 REG_SET_2(CURSOR_HOT_SPOT, 0,
11581177 CURSOR_HOT_SPOT_X, x_hotspot,
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c+99−95
@@ -636,8 +636,6 @@ static enum dc_status dcn10_enable_stream_timing( · 635 unmodified lines
636636 struct dc_stream_state *stream = pipe_ctx->stream;
637637 enum dc_color_space color_space;
638638 struct tg_color black_color = {0};
639− struct drr_params params = {0};
640− unsigned int event_triggers = 0;
641639
642640 /* by upper caller loop, pipe0 is parent pipe and be called first.
643641 * back end is set up by for pipe0. Other children pipe share back end
@@ -705,19 +703,6 @@ static enum dc_status dcn10_enable_stream_timing( · 61 unmodified lines
705703 return DC_ERROR_UNEXPECTED;
706704 }
707705
708− params.vertical_total_min = stream->adjust.v_total_min;
709− params.vertical_total_max = stream->adjust.v_total_max;
710− if (pipe_ctx->stream_res.tg->funcs->set_drr)
711− pipe_ctx->stream_res.tg->funcs->set_drr(
712− pipe_ctx->stream_res.tg, &params);
713−
714− // DRR should set trigger event to monitor surface update event
715− if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0)
716− event_triggers = 0x80;
717− if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)
718− pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
719− pipe_ctx->stream_res.tg, event_triggers);
720−
721706 /* TODO program crtc source select for non-virtual signal*/
722707 /* TODO program FMT */
723708 /* TODO setup link_enc */
@@ -971,92 +956,34 @@ static void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx) · 247 unmodified lines
971956 pipe_ctx->pipe_idx);
972957 }
973958
974−static void dcn10_init_hw(struct dc *dc)
959+static void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
975960 {
976961 int i;
977− struct abm *abm = dc->res_pool->abm;
978− struct dmcu *dmcu = dc->res_pool->dmcu;
979− struct dce_hwseq *hws = dc->hwseq;
980− struct dc_bios *dcb = dc->ctx->dc_bios;
981− struct dc_state *context = dc->current_state;
982−
983− if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
984− REG_WRITE(REFCLK_CNTL, 0);
985− REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
986− REG_WRITE(DIO_MEM_PWR_CTRL, 0);
987−
988− if (!dc->debug.disable_clock_gate) {
989− /* enable all DCN clock gating */
990− REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
991−
992− REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
993−
994− REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
995− }
996−
997− enable_power_gating_plane(dc->hwseq, true);
998− } else {
999−
1000− if (!dcb->funcs->is_accelerated_mode(dcb)) {
1001− bool allow_self_fresh_force_enable =
1002− hububu1_is_allow_self_refresh_enabled(dc->res_pool->hubbub);
1003−
1004− bios_golden_init(dc);
1005−
1006− /* WA for making DF sleep when idle after resume from S0i3.
1007− * DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE is set to 1 by
1008− * command table, if DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE = 0
1009− * before calling command table and it changed to 1 after,
1010− * it should be set back to 0.
1011− */
1012− if (allow_self_fresh_force_enable == false &&
1013− hububu1_is_allow_self_refresh_enabled(dc->res_pool->hubbub))
1014− hubbub1_disable_allow_self_refresh(dc->res_pool->hubbub);
1015−
1016− disable_vga(dc->hwseq);
1017− }
1018−
1019− for (i = 0; i < dc->link_count; i++) {
1020− /* Power up AND update implementation according to the
1021− * required signal (which may be different from the
1022− * default signal on connector).
1023− */
1024− struct dc_link *link = dc->links[i];
1025−
1026− if (link->link_enc->connector.id == CONNECTOR_ID_EDP)
1027− dc->hwss.edp_power_control(link, true);
1028−
1029− link->link_enc->funcs->hw_init(link->link_enc);
1030− }
1031− }
1032962
1033963 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1034964 struct timing_generator *tg = dc->res_pool->timing_generators[i];
1035965
1036966 if (tg->funcs->is_tg_enabled(tg))
1037967 tg->funcs->lock(tg);
1038− }
1039−
1040− /* Blank controller using driver code instead of
1041− * command table.
1042− */
1043− for (i = 0; i < dc->res_pool->pipe_count; i++) {
1044− struct timing_generator *tg = dc->res_pool->timing_generators[i];
1045968
969+ /* Blank controller using driver code instead of
970+ * command table.
971+ */
1046972 if (tg->funcs->is_tg_enabled(tg)) {
1047973 tg->funcs->set_blank(tg, true);
1048974 hwss_wait_for_blank_complete(tg);
1049975 }
1050976 }
1051977
1052− /* Reset all MPCC muxes */
1053978 dc->res_pool->mpc->funcs->mpc_init(dc->res_pool->mpc);
1054979
1055− for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
980+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
1056981 struct timing_generator *tg = dc->res_pool->timing_generators[i];
1057− struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1058982 struct hubp *hubp = dc->res_pool->hubps[i];
1059983 struct dpp *dpp = dc->res_pool->dpps[i];
984+ struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
985+
986+ dpp->funcs->dpp_reset(dpp);
1060987
1061988 pipe_ctx->stream_res.tg = tg;
1062989 pipe_ctx->pipe_idx = i;
@@ -1074,18 +1001,9 @@ static void dcn10_init_hw(struct dc *dc) · 11 unmodified lines
10741001 pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
10751002
10761003 hwss1_plane_atomic_disconnect(dc, pipe_ctx);
1077− }
1078−
1079− for (i = 0; i < dc->res_pool->pipe_count; i++) {
1080− struct timing_generator *tg = dc->res_pool->timing_generators[i];
10811004
10821005 if (tg->funcs->is_tg_enabled(tg))
10831006 tg->funcs->unlock(tg);
1084− }
1085−
1086− for (i = 0; i < dc->res_pool->pipe_count; i++) {
1087− struct timing_generator *tg = dc->res_pool->timing_generators[i];
1088− struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
10891007
10901008 dcn10_disable_plane(dc, pipe_ctx);
10911009
@@ -1094,10 +1012,73 @@ static void dcn10_init_hw(struct dc *dc) · 2 unmodified lines
10941012
10951013 tg->funcs->tg_init(tg);
10961014 }
1015+}
1016+
1017+static void dcn10_init_hw(struct dc *dc)
1018+{
1019+ int i;
1020+ struct abm *abm = dc->res_pool->abm;
1021+ struct dmcu *dmcu = dc->res_pool->dmcu;
1022+ struct dce_hwseq *hws = dc->hwseq;
1023+ struct dc_bios *dcb = dc->ctx->dc_bios;
1024+
1025+ if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
1026+ REG_WRITE(REFCLK_CNTL, 0);
1027+ REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
1028+ REG_WRITE(DIO_MEM_PWR_CTRL, 0);
1029+
1030+ if (!dc->debug.disable_clock_gate) {
1031+ /* enable all DCN clock gating */
1032+ REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
1033+
1034+ REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
1035+
1036+ REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
1037+ }
1038+
1039+ enable_power_gating_plane(dc->hwseq, true);
10971040
1098− /* end of FPGA. Below if real ASIC */
1099− if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
1041+ /* end of FPGA. Below if real ASIC */
11001042 return;
1043+ }
1044+
1045+ if (!dcb->funcs->is_accelerated_mode(dcb)) {
1046+ bool allow_self_fresh_force_enable =
1047+ hububu1_is_allow_self_refresh_enabled(
1048+ dc->res_pool->hubbub);
1049+
1050+ bios_golden_init(dc);
1051+
1052+ /* WA for making DF sleep when idle after resume from S0i3.
1053+ * DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE is set to 1 by
1054+ * command table, if DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE = 0
1055+ * before calling command table and it changed to 1 after,
1056+ * it should be set back to 0.
1057+ */
1058+ if (allow_self_fresh_force_enable == false &&
1059+ hububu1_is_allow_self_refresh_enabled(dc->res_pool->hubbub))
1060+ hubbub1_allow_self_refresh_control(dc->res_pool->hubbub, true);
1061+
1062+ disable_vga(dc->hwseq);
1063+ }
1064+
1065+ for (i = 0; i < dc->link_count; i++) {
1066+ /* Power up AND update implementation according to the
1067+ * required signal (which may be different from the
1068+ * default signal on connector).
1069+ */
1070+ struct dc_link *link = dc->links[i];
1071+
1072+ if (link->link_enc->connector.id == CONNECTOR_ID_EDP)
1073+ dc->hwss.edp_power_control(link, true);
1074+
1075+ link->link_enc->funcs->hw_init(link->link_enc);
1076+
1077+ /* Check for enabled DIG to identify enabled display */
1078+ if (link->link_enc->funcs->is_dig_enabled &&
1079+ link->link_enc->funcs->is_dig_enabled(link->link_enc))
1080+ link->link_status.link_active = true;
1081+ }
11011082
11021083 for (i = 0; i < dc->res_pool->audio_count; i++) {
11031084 struct audio *audio = dc->res_pool->audios[i];
@@ -1128,6 +1109,9 @@ static void dcn10_init_hw(struct dc *dc) · 24 unmodified lines
11281109 enable_power_gating_plane(dc->hwseq, true);
11291110
11301111 memset(&dc->res_pool->clk_mgr->clks, 0, sizeof(dc->res_pool->clk_mgr->clks));
1112+
1113+ if (dc->hwss.init_pipes)
1114+ dc->hwss.init_pipes(dc, dc->current_state);
11311115 }
11321116
11331117 static void reset_hw_ctx_wrap(
@@ -2334,9 +2318,10 @@ static void dcn10_apply_ctx_for_surface( · 1200 unmodified lines
23342318 }
23352319 }
23362320
2337− if (!pipe_ctx->plane_state &&
2338− old_pipe_ctx->plane_state &&
2339− old_pipe_ctx->stream_res.tg == tg) {
2321+ if ((!pipe_ctx->plane_state ||
2322+ pipe_ctx->stream_res.tg != old_pipe_ctx->stream_res.tg) &&
2323+ old_pipe_ctx->plane_state &&
2324+ old_pipe_ctx->stream_res.tg == tg) {
23402325
23412326 dc->hwss.plane_atomic_disconnect(dc, old_pipe_ctx);
23422327 removed_pipe[i] = true;
@@ -2383,6 +2368,22 @@ static void dcn10_apply_ctx_for_surface( · 40 unmodified lines
23832368 hubbub1_wm_change_req_wa(dc->res_pool->hubbub);
23842369 }
23852370
2371+static void dcn10_stereo_hw_frame_pack_wa(struct dc *dc, struct dc_state *context)
2372+{
2373+ uint8_t i;
2374+
2375+ for (i = 0; i < context->stream_count; i++) {
2376+ if (context->streams[i]->timing.timing_3d_format
2377+ == TIMING_3D_FORMAT_HW_FRAME_PACKING) {
2378+ /*
2379+ * Disable stutter
2380+ */
2381+ hubbub1_allow_self_refresh_control(dc->res_pool->hubbub, false);
2382+ break;
2383+ }
2384+ }
2385+}
2386+
23862387 static void dcn10_prepare_bandwidth(
23872388 struct dc *dc,
23882389 struct dc_state *context)
@@ -2404,6 +2405,7 @@ static void dcn10_prepare_bandwidth( · 15 unmodified lines
24042405 &context->bw.dcn.watermarks,
24052406 dc->res_pool->ref_clock_inKhz / 1000,
24062407 true);
2408+ dcn10_stereo_hw_frame_pack_wa(dc, context);
24072409
24082410 if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE)
24092411 dcn_bw_notify_pplib_of_wm_ranges(dc);
@@ -2433,6 +2435,7 @@ static void dcn10_optimize_bandwidth( · 23 unmodified lines
24332435 &context->bw.dcn.watermarks,
24342436 dc->res_pool->ref_clock_inKhz / 1000,
24352437 true);
2438+ dcn10_stereo_hw_frame_pack_wa(dc, context);
24362439
24372440 if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE)
24382441 dcn_bw_notify_pplib_of_wm_ranges(dc);
@@ -2709,6 +2712,7 @@ static void dcn10_set_cursor_sdr_white_level(struct pipe_ctx *pipe_ctx) · 270 unmodified lines
27092712 static const struct hw_sequencer_funcs dcn10_funcs = {
27102713 .program_gamut_remap = program_gamut_remap,
27112714 .init_hw = dcn10_init_hw,
2715+ .init_pipes = dcn10_init_pipes,
27122716 .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
27132717 .apply_ctx_for_surface = dcn10_apply_ctx_for_surface,
27142718 .update_plane_addr = dcn10_update_plane_addr,
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c+10−0
@@ -85,6 +85,7 @@ static const struct link_encoder_funcs dcn10_lnk_enc_funcs = { · 84 unmodified lines
8585 .enable_hpd = dcn10_link_encoder_enable_hpd,
8686 .disable_hpd = dcn10_link_encoder_disable_hpd,
8787 .is_dig_enabled = dcn10_is_dig_enabled,
88+ .get_dig_frontend = dcn10_get_dig_frontend,
8889 .destroy = dcn10_link_encoder_destroy
8990 };
9091
@@ -495,6 +496,15 @@ bool dcn10_is_dig_enabled(struct link_encoder *enc) · 404 unmodified lines
495496 return value;
496497 }
497498
499+unsigned int dcn10_get_dig_frontend(struct link_encoder *enc)
500+{
501+ struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
502+ uint32_t value;
503+
504+ REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &value);
505+ return value;
506+}
507+
498508 static void link_encoder_disable(struct dcn10_link_encoder *enc10)
499509 {
500510 /* reset training pattern */
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h+2−0
@@ -336,6 +336,8 @@ void dcn10_psr_program_secondary_packet(struct link_encoder *enc, · 335 unmodified lines
336336
337337 bool dcn10_is_dig_enabled(struct link_encoder *enc);
338338
339+unsigned int dcn10_get_dig_frontend(struct link_encoder *enc);
340+
339341 void dcn10_aux_initialize(struct dcn10_link_encoder *enc10);
340342
341343 #endif /* __DC_LINK_ENCODER__DCN10_H__ */
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c+180−17
@@ -92,28 +92,136 @@ static void optc1_disable_stereo(struct timing_generator *optc) · 91 unmodified lines
9292 OTG_3D_STRUCTURE_STEREO_SEL_OVR, 0);
9393 }
9494
95+static uint32_t get_start_vline(struct timing_generator *optc, const struct dc_crtc_timing *dc_crtc_timing)
96+{
97+ struct dc_crtc_timing patched_crtc_timing;
98+ int vesa_sync_start;
99+ int asic_blank_end;
100+ int interlace_factor;
101+ int vertical_line_start;
102+
103+ patched_crtc_timing = *dc_crtc_timing;
104+ optc1_apply_front_porch_workaround(optc, &patched_crtc_timing);
105+
106+ vesa_sync_start = patched_crtc_timing.h_addressable +
107+ patched_crtc_timing.h_border_right +
108+ patched_crtc_timing.h_front_porch;
109+
110+ asic_blank_end = patched_crtc_timing.h_total -
111+ vesa_sync_start -
112+ patched_crtc_timing.h_border_left;
113+
114+ interlace_factor = patched_crtc_timing.flags.INTERLACE ? 2 : 1;
115+
116+ vesa_sync_start = patched_crtc_timing.v_addressable +
117+ patched_crtc_timing.v_border_bottom +
118+ patched_crtc_timing.v_front_porch;
119+
120+ asic_blank_end = (patched_crtc_timing.v_total -
121+ vesa_sync_start -
122+ patched_crtc_timing.v_border_top)
123+ * interlace_factor;
124+
125+ vertical_line_start = asic_blank_end - optc->dlg_otg_param.vstartup_start + 1;
126+ if (vertical_line_start < 0) {
127+ ASSERT(0);
128+ vertical_line_start = 0;
129+ }
130+
131+ return vertical_line_start;
132+}
133+
134+static void calc_vline_position(
135+ struct timing_generator *optc,
136+ const struct dc_crtc_timing *dc_crtc_timing,
137+ unsigned long long vsync_delta,
138+ uint32_t *start_line,
139+ uint32_t *end_line)
140+{
141+ unsigned long long req_delta_tens_of_usec = div64_u64((vsync_delta + 9999), 10000);
142+ unsigned long long pix_clk_hundreds_khz = div64_u64((dc_crtc_timing->pix_clk_100hz + 999), 1000);
143+ uint32_t req_delta_lines = (uint32_t) div64_u64(
144+ (req_delta_tens_of_usec * pix_clk_hundreds_khz + dc_crtc_timing->h_total - 1),
145+ dc_crtc_timing->h_total);
146+
147+ uint32_t vsync_line = get_start_vline(optc, dc_crtc_timing);
148+
149+ if (req_delta_lines != 0)
150+ req_delta_lines--;
151+
152+ if (req_delta_lines > vsync_line)
153+ *start_line = dc_crtc_timing->v_total - (req_delta_lines - vsync_line) - 1;
154+ else
155+ *start_line = vsync_line - req_delta_lines;
156+
157+ *end_line = *start_line + 2;
158+
159+ if (*end_line >= dc_crtc_timing->v_total)
160+ *end_line = 2;
161+}
162+
95163 void optc1_program_vline_interrupt(
96164 struct timing_generator *optc,
165+ const struct dc_crtc_timing *dc_crtc_timing,
97166 enum vline_select vline,
98− struct vline_config vline_config)
167+ const union vline_config *vline_config)
99168 {
100169 struct optc *optc1 = DCN10TG_FROM_TG(optc);
170+ uint32_t start_line = 0;
171+ uint32_t end_line = 0;
101172
102173 switch (vline) {
103174 case VLINE0:
175+ calc_vline_position(optc, dc_crtc_timing, vline_config->delta_in_ns, &start_line, &end_line);
104176 REG_SET_2(OTG_VERTICAL_INTERRUPT0_POSITION, 0,
105− OTG_VERTICAL_INTERRUPT0_LINE_START, vline_config.start_line,
106− OTG_VERTICAL_INTERRUPT0_LINE_END, vline_config.end_line);
177+ OTG_VERTICAL_INTERRUPT0_LINE_START, start_line,
178+ OTG_VERTICAL_INTERRUPT0_LINE_END, end_line);
107179 break;
108180 case VLINE1:
109181 REG_SET(OTG_VERTICAL_INTERRUPT1_POSITION, 0,
110− OTG_VERTICAL_INTERRUPT1_LINE_START, vline_config.start_line);
182+ OTG_VERTICAL_INTERRUPT1_LINE_START, vline_config->line_number);
111183 break;
112184 default:
113185 break;
114186 }
115187 }
116188
189+void optc1_program_vupdate_interrupt(
190+ struct timing_generator *optc,
191+ const struct dc_crtc_timing *dc_crtc_timing)
192+{
193+ struct optc *optc1 = DCN10TG_FROM_TG(optc);
194+ int32_t vertical_line_start;
195+ uint32_t asic_blank_end;
196+ uint32_t vesa_sync_start;
197+ struct dc_crtc_timing patched_crtc_timing;
198+
199+ patched_crtc_timing = *dc_crtc_timing;
200+ optc1_apply_front_porch_workaround(optc, &patched_crtc_timing);
201+
202+ /* asic_h_blank_end = HsyncWidth + HbackPorch =
203+ * vesa. usHorizontalTotal - vesa. usHorizontalSyncStart -
204+ * vesa.h_left_border
205+ */
206+ vesa_sync_start = patched_crtc_timing.h_addressable +
207+ patched_crtc_timing.h_border_right +
208+ patched_crtc_timing.h_front_porch;
209+
210+ asic_blank_end = patched_crtc_timing.h_total -
211+ vesa_sync_start -
212+ patched_crtc_timing.h_border_left;
213+
214+ /* Use OTG_VERTICAL_INTERRUPT2 replace VUPDATE interrupt,
215+ * program the reg for interrupt postition.
216+ */
217+ vertical_line_start = asic_blank_end - optc->dlg_otg_param.vstartup_start + 1;
218+ if (vertical_line_start < 0)
219+ vertical_line_start = 0;
220+
221+ REG_SET(OTG_VERTICAL_INTERRUPT2_POSITION, 0,
222+ OTG_VERTICAL_INTERRUPT2_LINE_START, vertical_line_start);
223+}
224+
117225 /**
118226 * program_timing_generator used by mode timing set
119227 * Program CRTC Timing Registers - OTG_H_*, OTG_V_*, Pixel repetition.
@@ -216,22 +324,14 @@ void optc1_program_timing( · 96 unmodified lines
216324 patched_crtc_timing.v_addressable +
217325 patched_crtc_timing.v_border_bottom);
218326
219− REG_UPDATE_2(OTG_V_BLANK_START_END,
220− OTG_V_BLANK_START, asic_blank_start,
221− OTG_V_BLANK_END, asic_blank_end);
222−
223− /* Use OTG_VERTICAL_INTERRUPT2 replace VUPDATE interrupt,
224− * program the reg for interrupt postition.
225− */
226327 vertical_line_start = asic_blank_end - optc->dlg_otg_param.vstartup_start + 1;
227328 v_fp2 = 0;
228329 if (vertical_line_start < 0)
229330 v_fp2 = -vertical_line_start;
230− if (vertical_line_start < 0)
231− vertical_line_start = 0;
232331
233− REG_SET(OTG_VERTICAL_INTERRUPT2_POSITION, 0,
234− OTG_VERTICAL_INTERRUPT2_LINE_START, vertical_line_start);
332+ REG_UPDATE_2(OTG_V_BLANK_START_END,
333+ OTG_V_BLANK_START, asic_blank_start,
334+ OTG_V_BLANK_END, asic_blank_end);
235335
236336 /* v_sync polarity */
237337 v_sync_polarity = patched_crtc_timing.flags.VSYNC_POSITIVE_POLARITY ?
@@ -290,7 +390,7 @@ void optc1_program_timing( · 52 unmodified lines
290390
291391 h_div_2 = optc1_is_two_pixels_per_containter(&patched_crtc_timing);
292392 REG_UPDATE(OTG_H_TIMING_CNTL,
293− OTG_H_TIMING_DIV_BY2, h_div_2);
393+ OTG_H_TIMING_DIV_BY2, h_div_2 || optc1->comb_opp_id != 0xf);
294394
295395 }
296396
@@ -1136,6 +1236,64 @@ bool optc1_is_stereo_left_eye(struct timing_generator *optc) · 839 unmodified lines
11361236 return ret;
11371237 }
11381238
1239+bool optc1_is_matching_timing(struct timing_generator *tg,
1240+ const struct dc_crtc_timing *otg_timing)
1241+{
1242+ struct dc_crtc_timing hw_crtc_timing = {0};
1243+ struct dcn_otg_state s = {0};
1244+
1245+ if (tg == NULL || otg_timing == NULL)
1246+ return false;
1247+
1248+ optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s);
1249+
1250+ hw_crtc_timing.h_total = s.h_total + 1;
1251+ hw_crtc_timing.h_addressable = s.h_total - ((s.h_total - s.h_blank_start) + s.h_blank_end);
1252+ hw_crtc_timing.h_front_porch = s.h_total + 1 - s.h_blank_start;
1253+ hw_crtc_timing.h_sync_width = s.h_sync_a_end - s.h_sync_a_start;
1254+
1255+ hw_crtc_timing.v_total = s.v_total + 1;
1256+ hw_crtc_timing.v_addressable = s.v_total - ((s.v_total - s.v_blank_start) + s.v_blank_end);
1257+ hw_crtc_timing.v_front_porch = s.v_total + 1 - s.v_blank_start;
1258+ hw_crtc_timing.v_sync_width = s.v_sync_a_end - s.v_sync_a_start;
1259+
1260+ if (otg_timing->h_total != hw_crtc_timing.h_total)
1261+ return false;
1262+
1263+ if (otg_timing->h_border_left != hw_crtc_timing.h_border_left)
1264+ return false;
1265+
1266+ if (otg_timing->h_addressable != hw_crtc_timing.h_addressable)
1267+ return false;
1268+
1269+ if (otg_timing->h_border_right != hw_crtc_timing.h_border_right)
1270+ return false;
1271+
1272+ if (otg_timing->h_front_porch != hw_crtc_timing.h_front_porch)
1273+ return false;
1274+
1275+ if (otg_timing->h_sync_width != hw_crtc_timing.h_sync_width)
1276+ return false;
1277+
1278+ if (otg_timing->v_total != hw_crtc_timing.v_total)
1279+ return false;
1280+
1281+ if (otg_timing->v_border_top != hw_crtc_timing.v_border_top)
1282+ return false;
1283+
1284+ if (otg_timing->v_addressable != hw_crtc_timing.v_addressable)
1285+ return false;
1286+
1287+ if (otg_timing->v_border_bottom != hw_crtc_timing.v_border_bottom)
1288+ return false;
1289+
1290+ if (otg_timing->v_sync_width != hw_crtc_timing.v_sync_width)
1291+ return false;
1292+
1293+ return true;
1294+}
1295+
1296+
11391297 void optc1_read_otg_state(struct optc *optc1,
11401298 struct dcn_otg_state *s)
11411299 {
@@ -1323,6 +1481,7 @@ static const struct timing_generator_funcs dcn10_tg_funcs = { · 181 unmodified lines
13231481 .validate_timing = optc1_validate_timing,
13241482 .program_timing = optc1_program_timing,
13251483 .program_vline_interrupt = optc1_program_vline_interrupt,
1484+ .program_vupdate_interrupt = optc1_program_vupdate_interrupt,
13261485 .program_global_sync = optc1_program_global_sync,
13271486 .enable_crtc = optc1_enable_crtc,
13281487 .disable_crtc = optc1_disable_crtc,
@@ -1332,6 +1491,7 @@ static const struct timing_generator_funcs dcn10_tg_funcs = { · 3 unmodified lines
13321491 .get_frame_count = optc1_get_vblank_counter,
13331492 .get_scanoutpos = optc1_get_crtc_scanoutpos,
13341493 .get_otg_active_size = optc1_get_otg_active_size,
1494+ .is_matching_timing = optc1_is_matching_timing,
13351495 .set_early_control = optc1_set_early_control,
13361496 /* used by enable_timing_synchronization. Not need for FPGA */
13371497 .wait_for_state = optc1_wait_for_state,
@@ -1371,10 +1531,13 @@ void dcn10_timing_generator_init(struct optc *optc1) · 33 unmodified lines
13711531 optc1->min_v_blank_interlace = 5;
13721532 optc1->min_h_sync_width = 8;
13731533 optc1->min_v_sync_width = 1;
1534+ optc1->comb_opp_id = 0xf;
13741535 }
13751536
13761537 bool optc1_is_two_pixels_per_containter(const struct dc_crtc_timing *timing)
13771538 {
1378− return timing->pixel_encoding == PIXEL_ENCODING_YCBCR420;
1539+ bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420;
1540+
1541+ return two_pix;
13791542 }
13801543
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h+5−3
@@ -435,7 +435,7 @@ struct optc { · 434 unmodified lines
435435 const struct dcn_optc_shift *tg_shift;
436436 const struct dcn_optc_mask *tg_mask;
437437
438− enum controller_id controller_id;
438+ int comb_opp_id;
439439
440440 uint32_t max_h_total;
441441 uint32_t max_v_total;
@@ -483,9 +483,11 @@ void optc1_program_timing( · 41 unmodified lines
483483 const struct dc_crtc_timing *dc_crtc_timing,
484484 bool use_vbios);
485485
486−void optc1_program_vline_interrupt(struct timing_generator *optc,
486+void optc1_program_vline_interrupt(
487+ struct timing_generator *optc,
488+ const struct dc_crtc_timing *dc_crtc_timing,
487489 enum vline_select vline,
488− struct vline_config vline_config);
490+ const union vline_config *vline_config);
489491
490492 void optc1_program_global_sync(
491493 struct timing_generator *optc);
drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c+12−0
@@ -101,6 +101,18 @@ enum gpio_mode dal_gpio_get_mode( · 100 unmodified lines
101101 return gpio->mode;
102102 }
103103
104+enum gpio_result dal_gpio_lock_pin(
105+ struct gpio *gpio)
106+{
107+ return dal_gpio_service_lock(gpio->service, gpio->id, gpio->en);
108+}
109+
110+enum gpio_result dal_gpio_unlock_pin(
111+ struct gpio *gpio)
112+{
113+ return dal_gpio_service_unlock(gpio->service, gpio->id, gpio->en);
114+}
115+
104116 enum gpio_result dal_gpio_change_mode(
105117 struct gpio *gpio,
106118 enum gpio_mode mode)
drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c+28−0
@@ -192,6 +192,34 @@ static void set_pin_free( · 191 unmodified lines
192192 service->busyness[id][en] = false;
193193 }
194194
195+enum gpio_result dal_gpio_service_lock(
196+ struct gpio_service *service,
197+ enum gpio_id id,
198+ uint32_t en)
199+{
200+ if (!service->busyness[id]) {
201+ ASSERT_CRITICAL(false);
202+ return GPIO_RESULT_OPEN_FAILED;
203+ }
204+
205+ set_pin_busy(service, id, en);
206+ return GPIO_RESULT_OK;
207+}
208+
209+enum gpio_result dal_gpio_service_unlock(
210+ struct gpio_service *service,
211+ enum gpio_id id,
212+ uint32_t en)
213+{
214+ if (!service->busyness[id]) {
215+ ASSERT_CRITICAL(false);
216+ return GPIO_RESULT_OPEN_FAILED;
217+ }
218+
219+ set_pin_free(service, id, en);
220+ return GPIO_RESULT_OK;
221+}
222+
195223 enum gpio_result dal_gpio_service_open(
196224 struct gpio_service *service,
197225 enum gpio_id id,
drivers/gpu/drm/amd/display/dc/gpio/gpio_service.h+10−0
@@ -52,4 +52,14 @@ void dal_gpio_service_close( · 51 unmodified lines
5252 struct gpio_service *service,
5353 struct hw_gpio_pin **ptr);
5454
55+enum gpio_result dal_gpio_service_lock(
56+ struct gpio_service *service,
57+ enum gpio_id id,
58+ uint32_t en);
59+
60+enum gpio_result dal_gpio_service_unlock(
61+ struct gpio_service *service,
62+ enum gpio_id id,
63+ uint32_t en);
64+
5565 #endif
drivers/gpu/drm/amd/display/dc/inc/clock_source.h+4−0
@@ -166,6 +166,10 @@ struct clock_source_funcs { · 165 unmodified lines
166166 struct clock_source *,
167167 struct pixel_clk_params *,
168168 struct pll_settings *);
169+ bool (*get_pixel_clk_frequency_100hz)(
170+ struct clock_source *clock_source,
171+ unsigned int inst,
172+ unsigned int *pixel_clk_khz);
169173 };
170174
171175 struct clock_source {
drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h+1−0
@@ -153,6 +153,7 @@ struct link_encoder_funcs { · 152 unmodified lines
153153 void (*enable_hpd)(struct link_encoder *enc);
154154 void (*disable_hpd)(struct link_encoder *enc);
155155 bool (*is_dig_enabled)(struct link_encoder *enc);
156+ unsigned int (*get_dig_frontend)(struct link_encoder *enc);
156157 void (*destroy)(struct link_encoder **enc);
157158 };
158159
drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h+10−3
@@ -134,7 +134,7 @@ struct dc_crtc_timing; · 133 unmodified lines
134134
135135 struct drr_params;
136136
137−struct vline_config;
137+union vline_config;
138138
139139
140140 enum vline_select {
@@ -149,9 +149,14 @@ struct timing_generator_funcs { · 8 unmodified lines
149149 void (*program_timing)(struct timing_generator *tg,
150150 const struct dc_crtc_timing *timing,
151151 bool use_vbios);
152− void (*program_vline_interrupt)(struct timing_generator *optc,
152+ void (*program_vline_interrupt)(
153+ struct timing_generator *optc,
154+ const struct dc_crtc_timing *dc_crtc_timing,
153155 enum vline_select vline,
154− struct vline_config vline_config);
156+ const union vline_config *vline_config);
157+
158+ void (*program_vupdate_interrupt)(struct timing_generator *optc,
159+ const struct dc_crtc_timing *dc_crtc_timing);
155160 bool (*enable_crtc)(struct timing_generator *tg);
156161 bool (*disable_crtc)(struct timing_generator *tg);
157162 bool (*is_counter_moving)(struct timing_generator *tg);
@@ -168,6 +173,8 @@ struct timing_generator_funcs { · 10 unmodified lines
168173 bool (*get_otg_active_size)(struct timing_generator *optc,
169174 uint32_t *otg_active_width,
170175 uint32_t *otg_active_height);
176+ bool (*is_matching_timing)(struct timing_generator *tg,
177+ const struct dc_crtc_timing *otg_timing);
171178 void (*set_early_control)(struct timing_generator *tg,
172179 uint32_t early_cntl);
173180 void (*wait_for_state)(struct timing_generator *tg,
drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h+2−0
@@ -70,6 +70,8 @@ struct hw_sequencer_funcs { · 69 unmodified lines
7070
7171 void (*init_hw)(struct dc *dc);
7272
73+ void (*init_pipes)(struct dc *dc, struct dc_state *context);
74+
7375 enum dc_status (*apply_ctx_to_hw)(
7476 struct dc *dc, struct dc_state *context);
7577
drivers/gpu/drm/amd/display/dc/inc/vm_helper.h+4−3
@@ -39,8 +39,8 @@ struct vm_helper { · 38 unmodified lines
3939 unsigned int num_vmid;
4040 unsigned int num_hubp;
4141 unsigned int num_vmids_available;
42− uint64_t *ptb_assigned_to_vmid;
43− struct vmid_usage *hubp_vmid_usage;
42+ uint64_t ptb_assigned_to_vmid[MAX_VMID];
43+ struct vmid_usage hubp_vmid_usage[MAX_HUBP];
4444 };
4545
4646 uint8_t get_vmid_for_ptb(
@@ -48,7 +48,8 @@ uint8_t get_vmid_for_ptb( · 1 unmodified line
4848 int64_t ptb,
4949 uint8_t pipe_idx);
5050
51−struct vm_helper init_vm_helper(
51+void init_vm_helper(
52+ struct vm_helper *vm_helper,
5253 unsigned int num_vmid,
5354 unsigned int num_hubp);
5455
drivers/gpu/drm/amd/display/include/gpio_interface.h+8−0
@@ -59,6 +59,14 @@ enum gpio_result dal_gpio_change_mode( · 58 unmodified lines
5959 struct gpio *gpio,
6060 enum gpio_mode mode);
6161
62+/* Lock Pin */
63+enum gpio_result dal_gpio_lock_pin(
64+ struct gpio *gpio);
65+
66+/* Unlock Pin */
67+enum gpio_result dal_gpio_unlock_pin(
68+ struct gpio *gpio);
69+
6270 /* Get the GPIO id */
6371 enum gpio_id dal_gpio_get_id(
6472 const struct gpio *gpio);
drivers/gpu/drm/amd/display/modules/color/color_gamma.c+52−37
@@ -1765,68 +1765,85 @@ bool mod_color_calculate_degamma_params(struct dc_transfer_func *input_tf, · 1764 unmodified lines
17651765 {
17661766 struct dc_transfer_func_distributed_points *tf_pts = &input_tf->tf_pts;
17671767 struct dividers dividers;
1768−
17691768 struct pwl_float_data *rgb_user = NULL;
17701769 struct pwl_float_data_ex *curve = NULL;
17711770 struct gamma_pixel *axis_x = NULL;
17721771 struct pixel_gamma_point *coeff = NULL;
17731772 enum dc_transfer_func_predefined tf = TRANSFER_FUNCTION_SRGB;
1773+ uint32_t i;
17741774 bool ret = false;
17751775
17761776 if (input_tf->type == TF_TYPE_BYPASS)
17771777 return false;
17781778
1779− /* we can use hardcoded curve for plain SRGB TF */
1779+ /* we can use hardcoded curve for plain SRGB TF
1780+ * If linear, it's bypass if on user ramp
1781+ */
17801782 if (input_tf->type == TF_TYPE_PREDEFINED &&
1781− input_tf->tf == TRANSFER_FUNCTION_SRGB &&
1782− !mapUserRamp)
1783+ (input_tf->tf == TRANSFER_FUNCTION_SRGB ||
1784+ input_tf->tf == TRANSFER_FUNCTION_LINEAR) &&
1785+ !mapUserRamp)
17831786 return true;
17841787
17851788 input_tf->type = TF_TYPE_DISTRIBUTED_POINTS;
17861789
1787− rgb_user = kvcalloc(ramp->num_entries + _EXTRA_POINTS,
1788− sizeof(*rgb_user),
1789− GFP_KERNEL);
1790− if (!rgb_user)
1791− goto rgb_user_alloc_fail;
1790+ if (mapUserRamp && ramp && ramp->type == GAMMA_RGB_256) {
1791+ rgb_user = kvcalloc(ramp->num_entries + _EXTRA_POINTS,
1792+ sizeof(*rgb_user),
1793+ GFP_KERNEL);
1794+ if (!rgb_user)
1795+ goto rgb_user_alloc_fail;
1796+
1797+ axis_x = kvcalloc(ramp->num_entries + _EXTRA_POINTS, sizeof(*axis_x),
1798+ GFP_KERNEL);
1799+ if (!axis_x)
1800+ goto axis_x_alloc_fail;
1801+
1802+ dividers.divider1 = dc_fixpt_from_fraction(3, 2);
1803+ dividers.divider2 = dc_fixpt_from_int(2);
1804+ dividers.divider3 = dc_fixpt_from_fraction(5, 2);
1805+
1806+ build_evenly_distributed_points(
1807+ axis_x,
1808+ ramp->num_entries,
1809+ dividers);
1810+
1811+ scale_gamma(rgb_user, ramp, dividers);
1812+ }
1813+
17921814 curve = kvcalloc(MAX_HW_POINTS + _EXTRA_POINTS, sizeof(*curve),
1793− GFP_KERNEL);
1815+ GFP_KERNEL);
17941816 if (!curve)
17951817 goto curve_alloc_fail;
1796− axis_x = kvcalloc(ramp->num_entries + _EXTRA_POINTS, sizeof(*axis_x),
1797− GFP_KERNEL);
1798− if (!axis_x)
1799− goto axis_x_alloc_fail;
1818+
18001819 coeff = kvcalloc(MAX_HW_POINTS + _EXTRA_POINTS, sizeof(*coeff),
1801− GFP_KERNEL);
1820+ GFP_KERNEL);
18021821 if (!coeff)
18031822 goto coeff_alloc_fail;
18041823
1805− dividers.divider1 = dc_fixpt_from_fraction(3, 2);
1806− dividers.divider2 = dc_fixpt_from_int(2);
1807− dividers.divider3 = dc_fixpt_from_fraction(5, 2);
1808−
18091824 tf = input_tf->tf;
18101825
1811− build_evenly_distributed_points(
1812− axis_x,
1813− ramp->num_entries,
1814− dividers);
1815−
1816− if (ramp->type == GAMMA_RGB_256 && mapUserRamp)
1817− scale_gamma(rgb_user, ramp, dividers);
1818− else if (ramp->type == GAMMA_RGB_FLOAT_1024)
1819− scale_gamma_dx(rgb_user, ramp, dividers);
1820−
18211826 if (tf == TRANSFER_FUNCTION_PQ)
18221827 build_de_pq(curve,
18231828 MAX_HW_POINTS,
18241829 coordinates_x);
1825− else
1830+ else if (tf == TRANSFER_FUNCTION_SRGB ||
1831+ tf == TRANSFER_FUNCTION_BT709)
18261832 build_degamma(curve,
18271833 MAX_HW_POINTS,
18281834 coordinates_x,
1829− tf == TRANSFER_FUNCTION_SRGB ? true:false);
1835+ tf == TRANSFER_FUNCTION_SRGB ? true : false);
1836+ else if (tf == TRANSFER_FUNCTION_LINEAR) {
1837+ // just copy coordinates_x into curve
1838+ i = 0;
1839+ while (i != MAX_HW_POINTS + 1) {
1840+ curve[i].r = coordinates_x[i].x;
1841+ curve[i].g = curve[i].r;
1842+ curve[i].b = curve[i].r;
1843+ i++;
1844+ }
1845+ } else
1846+ goto invalid_tf_fail;
18301847
18311848 tf_pts->end_exponent = 0;
18321849 tf_pts->x_point_at_y1_red = 1;
@@ -1836,23 +1853,21 @@ bool mod_color_calculate_degamma_params(struct dc_transfer_func *input_tf, · 3 unmodified lines
18361853 map_regamma_hw_to_x_user(ramp, coeff, rgb_user,
18371854 coordinates_x, axis_x, curve,
18381855 MAX_HW_POINTS, tf_pts,
1839− mapUserRamp && ramp->type != GAMMA_CUSTOM);
1840− if (ramp->type == GAMMA_CUSTOM)
1841− apply_lut_1d(ramp, MAX_HW_POINTS, tf_pts);
1856+ mapUserRamp && ramp && ramp->type == GAMMA_RGB_256);
18421857
18431858 ret = true;
18441859
1860+invalid_tf_fail:
18451861 kvfree(coeff);
18461862 coeff_alloc_fail:
1847− kvfree(axis_x);
1848−axis_x_alloc_fail:
18491863 kvfree(curve);
18501864 curve_alloc_fail:
1865+ kvfree(axis_x);
1866+axis_x_alloc_fail:
18511867 kvfree(rgb_user);
18521868 rgb_user_alloc_fail:
18531869
18541870 return ret;
1855−
18561871 }
18571872
18581873
drivers/gpu/drm/amd/display/modules/power/power_helpers.c+26−12
@@ -47,10 +47,10 @@ static const unsigned char min_reduction_table_v_2_2[13] = { · 46 unmodified lines
4747
4848 /* Possible ABM 2.2 Max Reduction configs from least aggressive to most aggressive
4949 * 0 1 2 3 4 5 6 7 8 9 10 11 12
50− * 96.1 89.8 85.1 80.3 69.4 64.7 54.9 45.1 30.2 25.1 19.6 12.5 12.5 %
50+ * 96.1 89.8 74.9 69.4 64.7 52.2 48.6 39.6 30.2 25.1 19.6 12.5 12.5 %
5151 */
5252 static const unsigned char max_reduction_table_v_2_2[13] = {
53−0xf5, 0xe5, 0xd9, 0xcd, 0xb1, 0xa5, 0x8c, 0x73, 0x4d, 0x40, 0x32, 0x20, 0x20};
53+0xf5, 0xe5, 0xbf, 0xb1, 0xa5, 0x85, 0x7c, 0x65, 0x4d, 0x40, 0x32, 0x20, 0x20};
5454
5555 /* Predefined ABM configuration sets. We may have different configuration sets
5656 * in order to satisfy different power/quality requirements.
@@ -67,9 +67,14 @@ static const unsigned char abm_config[abm_defines_max_config][abm_defines_max_le · 10 unmodified lines
6767 #define NUM_AGGR_LEVEL 4
6868 #define NUM_POWER_FN_SEGS 8
6969 #define NUM_BL_CURVE_SEGS 16
70−#define IRAM_RESERVE_AREA_START 0xF0 // reserve 0xF0~0xFF are write by DMCU only
7170 #define IRAM_SIZE 256
7271
72+#define IRAM_RESERVE_AREA_START_V2 0xF0 // reserve 0xF0~0xF6 are write by DMCU only
73+#define IRAM_RESERVE_AREA_END_V2 0xF6 // reserve 0xF0~0xF6 are write by DMCU only
74+
75+#define IRAM_RESERVE_AREA_START_V2_2 0xF0 // reserve 0xF0~0xFF are write by DMCU only
76+#define IRAM_RESERVE_AREA_END_V2_2 0xFF // reserve 0xF0~0xFF are write by DMCU only
77+
7378 #pragma pack(push, 1)
7479 /* NOTE: iRAM is 256B in size */
7580 struct iram_table_v_2 {
@@ -148,8 +153,10 @@ struct iram_table_v_2_2 { · 72 unmodified lines
148153 uint16_t dmcu_version; /* 0xf4 */
149154 uint8_t dmcu_state; /* 0xf6 */
150155
151− uint16_t blRampReduction; /* 0xf7 */
152− uint16_t blRampStart; /* 0xf9 */
156+ uint8_t dummy1; /* 0xf7 */
157+ uint8_t dummy2; /* 0xf8 */
158+ uint8_t dummy3; /* 0xf9 */
159+ uint8_t dummy4; /* 0xfa */
153160 uint8_t dummy5; /* 0xfb */
154161 uint8_t dummy6; /* 0xfc */
155162 uint8_t dummy7; /* 0xfd */
@@ -420,11 +427,6 @@ void fill_iram_v_2_2(struct iram_table_v_2_2 *ram_table, struct dmcu_iram_parame · 264 unmodified lines
420427 ram_table->deviation_gain[2] = 0xb3;
421428 ram_table->deviation_gain[3] = 0xb3;
422429
423− ram_table->blRampReduction =
424− cpu_to_be16(params.backlight_ramping_reduction);
425− ram_table->blRampStart =
426− cpu_to_be16(params.backlight_ramping_start);
427−
428430 ram_table->min_reduction[0][0] = min_reduction_table_v_2_2[abm_config[set][0]];
429431 ram_table->min_reduction[1][0] = min_reduction_table_v_2_2[abm_config[set][0]];
430432 ram_table->min_reduction[2][0] = min_reduction_table_v_2_2[abm_config[set][0]];
@@ -561,6 +563,7 @@ bool dmcu_load_iram(struct dmcu *dmcu, · 130 unmodified lines
561563 struct dmcu_iram_parameters params)
562564 {
563565 unsigned char ram_table[IRAM_SIZE];
566+ bool result = false;
564567
565568 if (dmcu == NULL)
566569 return false;
@@ -572,10 +575,21 @@ bool dmcu_load_iram(struct dmcu *dmcu, · 5 unmodified lines
572575
573576 if (dmcu->dmcu_version.abm_version == 0x22) {
574577 fill_iram_v_2_2((struct iram_table_v_2_2 *)ram_table, params);
578+
579+ result = dmcu->funcs->load_iram(
580+ dmcu, 0, (char *)(&ram_table), IRAM_RESERVE_AREA_START_V2_2);
575581 } else {
576582 fill_iram_v_2((struct iram_table_v_2 *)ram_table, params);
583+
584+ result = dmcu->funcs->load_iram(
585+ dmcu, 0, (char *)(&ram_table), IRAM_RESERVE_AREA_START_V2);
586+
587+ if (result)
588+ result = dmcu->funcs->load_iram(
589+ dmcu, IRAM_RESERVE_AREA_END_V2 + 1,
590+ (char *)(&ram_table) + IRAM_RESERVE_AREA_END_V2 + 1,
591+ sizeof(ram_table) - IRAM_RESERVE_AREA_END_V2 - 1);
577592 }
578593
579− return dmcu->funcs->load_iram(
580− dmcu, 0, (char *)(&ram_table), IRAM_RESERVE_AREA_START);
594+ return result;
581595 }
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c+7−0
@@ -3579,6 +3579,10 @@ static int vega10_generate_dpm_level_enable_mask( · 3578 unmodified lines
35793579 vega10_find_lowest_dpm_level(&(data->dpm_table.mem_table));
35803580 data->smc_state_table.mem_max_level =
35813581 vega10_find_highest_dpm_level(&(data->dpm_table.mem_table));
3582+ data->smc_state_table.soc_boot_level =
3583+ vega10_find_lowest_dpm_level(&(data->dpm_table.soc_table));
3584+ data->smc_state_table.soc_max_level =
3585+ vega10_find_highest_dpm_level(&(data->dpm_table.soc_table));
35823586
35833587 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
35843588 "Attempt to upload DPM Bootup Levels Failed!",
@@ -3593,6 +3597,9 @@ static int vega10_generate_dpm_level_enable_mask( · 8 unmodified lines
35933597 for(i = data->smc_state_table.mem_boot_level; i < data->smc_state_table.mem_max_level; i++)
35943598 data->dpm_table.mem_table.dpm_levels[i].enabled = true;
35953599
3600+ for (i = data->smc_state_table.soc_boot_level; i < data->smc_state_table.soc_max_level; i++)
3601+ data->dpm_table.soc_table.dpm_levels[i].enabled = true;
3602+
35963603 return 0;
35973604 }
35983605
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c+27−20
@@ -771,40 +771,47 @@ static int vega20_init_smc_table(struct pp_hwmgr *hwmgr) · 770 unmodified lines
771771 return 0;
772772 }
773773
774+/*
775+ * Override PCIe link speed and link width for DPM Level 1. PPTable entries
776+ * reflect the ASIC capabilities and not the system capabilities. For e.g.
777+ * Vega20 board in a PCI Gen3 system. In this case, when SMU's tries to switch
778+ * to DPM1, it fails as system doesn't support Gen4.
779+ */
774780 static int vega20_override_pcie_parameters(struct pp_hwmgr *hwmgr)
775781 {
776782 struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
777− uint32_t pcie_speed = 0, pcie_width = 0, pcie_arg;
783+ uint32_t pcie_gen = 0, pcie_width = 0, smu_pcie_arg;
778784 int ret;
779785
780786 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
781− pcie_speed = 16;
787+ pcie_gen = 3;
782788 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
783− pcie_speed = 8;
789+ pcie_gen = 2;
784790 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
785− pcie_speed = 5;
791+ pcie_gen = 1;
786792 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
787− pcie_speed = 2;
793+ pcie_gen = 0;
788794
789− if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X32)
790− pcie_width = 32;
791− else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
792− pcie_width = 16;
795+ if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
796+ pcie_width = 6;
793797 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
794− pcie_width = 12;
798+ pcie_width = 5;
795799 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
796− pcie_width = 8;
797− else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
798800 pcie_width = 4;
801+ else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
802+ pcie_width = 3;
799803 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
800804 pcie_width = 2;
801805 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
802806 pcie_width = 1;
803807
804− pcie_arg = pcie_width | (pcie_speed << 8);
805−
808+ /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
809+ * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
810+ * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32
811+ */
812+ smu_pcie_arg = (1 << 16) | (pcie_gen << 8) | pcie_width;
806813 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
807− PPSMC_MSG_OverridePcieParameters, pcie_arg);
814+ PPSMC_MSG_OverridePcieParameters, smu_pcie_arg);
808815 PP_ASSERT_WITH_CODE(!ret,
809816 "[OverridePcieParameters] Attempt to override pcie params failed!",
810817 return ret);
@@ -1611,11 +1618,6 @@ static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr) · 800 unmodified lines
16111618 "[EnableDPMTasks] Failed to initialize SMC table!",
16121619 return result);
16131620
1614− result = vega20_override_pcie_parameters(hwmgr);
1615− PP_ASSERT_WITH_CODE(!result,
1616− "[EnableDPMTasks] Failed to override pcie parameters!",
1617− return result);
1618−
16191621 result = vega20_run_btc(hwmgr);
16201622 PP_ASSERT_WITH_CODE(!result,
16211623 "[EnableDPMTasks] Failed to run btc!",
@@ -1631,6 +1633,11 @@ static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr) · 9 unmodified lines
16311633 "[EnableDPMTasks] Failed to enable all smu features!",
16321634 return result);
16331635
1636+ result = vega20_override_pcie_parameters(hwmgr);
1637+ PP_ASSERT_WITH_CODE(!result,
1638+ "[EnableDPMTasks] Failed to override pcie parameters!",
1639+ return result);
1640+
16341641 result = vega20_notify_smc_display_change(hwmgr);
16351642 PP_ASSERT_WITH_CODE(!result,
16361643 "[EnableDPMTasks] Failed to notify smc display change!",
include/uapi/drm/amdgpu_drm.h+6−0
@@ -523,6 +523,7 @@ struct drm_amdgpu_gem_va { · 522 unmodified lines
523523 #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04
524524 #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05
525525 #define AMDGPU_CHUNK_ID_BO_HANDLES 0x06
526+#define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07
526527
527528 struct drm_amdgpu_cs_chunk {
528529 __u32 chunk_id;
@@ -565,6 +566,11 @@ union drm_amdgpu_cs { · 36 unmodified lines
565566 * caches (L2/vL1/sL1/I$). */
566567 #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3)
567568
569+/* Set GDS_COMPUTE_MAX_WAVE_ID = DEFAULT before PACKET3_INDIRECT_BUFFER.
570+ * This will reset wave ID counters for the IB.
571+ */
572+#define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4)
573+
568574 struct drm_amdgpu_cs_chunk_ib {
569575 __u32 _pad;
570576 /** AMDGPU_IB_FLAG_* */

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