History

drm/amdgpu: use 6.1.0 register offset for HDP CLK_CNTL

Use 6.1.0 register offset and remove unused variable. v2: clean up logic (Alex)

Lang Yu committed 3 years ago

Commit f56c1941 parent dd054841 file · +16 −4Browse files

Unified · Split

drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c+16−4
@@ -28,6 +28,9 @@ · 27 unmodified lines
28#include "hdp/hdp_6_0_0_sh_mask.h"28#include "hdp/hdp_6_0_0_sh_mask.h"
29#include <uapi/linux/kfd_ioctl.h>29#include <uapi/linux/kfd_ioctl.h>
30 30
31#define regHDP_CLK_CNTL_V6_1 0xd5
32#define regHDP_CLK_CNTL_V6_1_BASE_IDX 0
33
31static void hdp_v6_0_flush_hdp(struct amdgpu_device *adev,34static void hdp_v6_0_flush_hdp(struct amdgpu_device *adev,
32 struct amdgpu_ring *ring)35 struct amdgpu_ring *ring)
33{36{
@@ -40,7 +43,7 @@ static void hdp_v6_0_flush_hdp(struct amdgpu_device *adev, · 6 unmodified lines
40static void hdp_v6_0_update_clock_gating(struct amdgpu_device *adev,43static void hdp_v6_0_update_clock_gating(struct amdgpu_device *adev,
41 bool enable)44 bool enable)
42{45{
43 uint32_t hdp_clk_cntl, hdp_clk_cntl1;46 uint32_t hdp_clk_cntl;
44 uint32_t hdp_mem_pwr_cntl;47 uint32_t hdp_mem_pwr_cntl;
45 48
46 if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS |49 if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS |
@@ -48,14 +51,20 @@ static void hdp_v6_0_update_clock_gating(struct amdgpu_device *adev, · 1 unmodified line
48 AMD_CG_SUPPORT_HDP_SD)))51 AMD_CG_SUPPORT_HDP_SD)))
49 return;52 return;
50 53
51 hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0,regHDP_CLK_CNTL);54 if (adev->ip_versions[HDP_HWIP][0] == IP_VERSION(6, 1, 0))
55 hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL_V6_1);
56 else
57 hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL);
52 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL);58 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL);
53 59
54 /* Before doing clock/power mode switch,60 /* Before doing clock/power mode switch,
55 * forced on IPH & RC clock */61 * forced on IPH & RC clock */
56 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,62 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
57 RC_MEM_CLK_SOFT_OVERRIDE, 1);63 RC_MEM_CLK_SOFT_OVERRIDE, 1);
58 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl);64 if (adev->ip_versions[HDP_HWIP][0] == IP_VERSION(6, 1, 0))
65 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL_V6_1, hdp_clk_cntl);
66 else
67 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl);
59 68
60 /* disable clock and power gating before any changing */69 /* disable clock and power gating before any changing */
61 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,70 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
@@ -117,7 +126,10 @@ static void hdp_v6_0_update_clock_gating(struct amdgpu_device *adev, · 55 unmodified lines
117 /* disable IPH & RC clock override after clock/power mode changing */126 /* disable IPH & RC clock override after clock/power mode changing */
118 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,127 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
119 RC_MEM_CLK_SOFT_OVERRIDE, 0);128 RC_MEM_CLK_SOFT_OVERRIDE, 0);
120 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl);129 if (adev->ip_versions[HDP_HWIP][0] == IP_VERSION(6, 1, 0))
130 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL_V6_1, hdp_clk_cntl);
131 else
132 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl);
121}133}
122 134
123static void hdp_v6_0_get_clockgating_state(struct amdgpu_device *adev,135static void hdp_v6_0_get_clockgating_state(struct amdgpu_device *adev,