Implement a perf core library that can support all the essential perf features in future. It can also accommodate any type of PMU implementation in future. Currently, both SBI based perf driver and legacy driver implemented uses the library. Most of the common perf functionalities are kept in this core library wile PMU specific driver can implement PMU specific features. For example, the SBI specific functionality will be implemented in the SBI specific driver.
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| 1 | +/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | +/* | |
| 3 | + * Copyright (C) 2018 SiFive | |
| 4 | + * Copyright (C) 2018 Andes Technology Corporation | |
| 5 | + * Copyright (C) 2021 Western Digital Corporation or its affiliates. | |
| 6 | + * | |
| 7 | + */ | |
| 8 | + | |
| 9 | +#ifndef _ASM_RISCV_PERF_EVENT_H | |
| 10 | +#define _ASM_RISCV_PERF_EVENT_H | |
| 11 | + | |
| 12 | +#include <linux/perf_event.h> | |
| 13 | +#include <linux/ptrace.h> | |
| 14 | +#include <linux/interrupt.h> | |
| 15 | + | |
| 16 | +#ifdef CONFIG_RISCV_PMU | |
| 17 | + | |
| 18 | +/* | |
| 19 | + * The RISCV_MAX_COUNTERS parameter should be specified. | |
| 20 | + */ | |
| 21 | + | |
| 22 | +#define RISCV_MAX_COUNTERS 64 | |
| 23 | +#define RISCV_OP_UNSUPP (-EOPNOTSUPP) | |
| 24 | +#define RISCV_PMU_PDEV_NAME "riscv-pmu" | |
| 25 | + | |
| 26 | +#define RISCV_PMU_STOP_FLAG_RESET 1 | |
| 27 | + | |
| 28 | +struct cpu_hw_events { | |
| 29 | + /* currently enabled events */ | |
| 30 | + int n_events; | |
| 31 | + /* currently enabled events */ | |
| 32 | + struct perf_event *events[RISCV_MAX_COUNTERS]; | |
| 33 | + /* currently enabled counters */ | |
| 34 | + DECLARE_BITMAP(used_event_ctrs, RISCV_MAX_COUNTERS); | |
| 35 | +}; | |
| 36 | + | |
| 37 | +struct riscv_pmu { | |
| 38 | + struct pmu pmu; | |
| 39 | + char *name; | |
| 40 | + | |
| 41 | + irqreturn_t (*handle_irq)(int irq_num, void *dev); | |
| 42 | + | |
| 43 | + int num_counters; | |
| 44 | + u64 (*ctr_read)(struct perf_event *event); | |
| 45 | + int (*ctr_get_idx)(struct perf_event *event); | |
| 46 | + int (*ctr_get_width)(int idx); | |
| 47 | + void (*ctr_clear_idx)(struct perf_event *event); | |
| 48 | + void (*ctr_start)(struct perf_event *event, u64 init_val); | |
| 49 | + void (*ctr_stop)(struct perf_event *event, unsigned long flag); | |
| 50 | + int (*event_map)(struct perf_event *event, u64 *config); | |
| 51 | + | |
| 52 | + struct cpu_hw_events __percpu *hw_events; | |
| 53 | + struct hlist_node node; | |
| 54 | +}; | |
| 55 | + | |
| 56 | +#define to_riscv_pmu(p) (container_of(p, struct riscv_pmu, pmu)) | |
| 57 | +unsigned long riscv_pmu_ctr_read_csr(unsigned long csr); | |
| 58 | +int riscv_pmu_event_set_period(struct perf_event *event); | |
| 59 | +uint64_t riscv_pmu_ctr_get_width_mask(struct perf_event *event); | |
| 60 | +u64 riscv_pmu_event_update(struct perf_event *event); | |
| 61 | +struct riscv_pmu *riscv_pmu_alloc(void); | |
| 62 | + | |
| 63 | +#endif /* CONFIG_RISCV_PMU */ | |
| 64 | + | |
| 65 | +#endif /* _ASM_RISCV_PERF_EVENT_H */ | |