Add support for PCIe TLP Processing Hints (TPH) support (see PCIe r6.2, sec 6.17). Add TPH register definitions in pci_regs.h, including the TPH Requester capability register, TPH Requester control register, TPH Completer capability, and the ST fields of MSI-X entry. Introduce pcie_enable_tph() and pcie_disable_tph(), enabling drivers to toggle TPH support and configure specific ST mode as needed. Also add a new kernel parameter, "pci=notph", allowing users to disable TPH support across the entire system.
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| @@ -340,7 +340,8 @@ · 339 unmodified lines | |||
| 340 | #define PCI_MSIX_ENTRY_UPPER_ADDR 0x4 /* Message Upper Address */ | 340 | #define PCI_MSIX_ENTRY_UPPER_ADDR 0x4 /* Message Upper Address */ |
| 341 | #define PCI_MSIX_ENTRY_DATA 0x8 /* Message Data */ | 341 | #define PCI_MSIX_ENTRY_DATA 0x8 /* Message Data */ |
| 342 | #define PCI_MSIX_ENTRY_VECTOR_CTRL 0xc /* Vector Control */ | 342 | #define PCI_MSIX_ENTRY_VECTOR_CTRL 0xc /* Vector Control */ |
| 343 | #define PCI_MSIX_ENTRY_CTRL_MASKBIT 0x00000001 | 343 | #define PCI_MSIX_ENTRY_CTRL_MASKBIT 0x00000001 /* Mask Bit */ |
| 344 | #define PCI_MSIX_ENTRY_CTRL_ST 0xffff0000 /* Steering Tag */ | ||
| 344 | 345 | ||
| 345 | /* CompactPCI Hotswap Register */ | 346 | /* CompactPCI Hotswap Register */ |
| 346 | 347 | ||
| @@ -659,6 +660,7 @@ · 312 unmodified lines | |||
| 659 | #define PCI_EXP_DEVCAP2_ATOMIC_COMP64 0x00000100 /* 64b AtomicOp completion */ | 660 | #define PCI_EXP_DEVCAP2_ATOMIC_COMP64 0x00000100 /* 64b AtomicOp completion */ |
| 660 | #define PCI_EXP_DEVCAP2_ATOMIC_COMP128 0x00000200 /* 128b AtomicOp completion */ | 661 | #define PCI_EXP_DEVCAP2_ATOMIC_COMP128 0x00000200 /* 128b AtomicOp completion */ |
| 661 | #define PCI_EXP_DEVCAP2_LTR 0x00000800 /* Latency tolerance reporting */ | 662 | #define PCI_EXP_DEVCAP2_LTR 0x00000800 /* Latency tolerance reporting */ |
| 663 | #define PCI_EXP_DEVCAP2_TPH_COMP_MASK 0x00003000 /* TPH completer support */ | ||
| 662 | #define PCI_EXP_DEVCAP2_OBFF_MASK 0x000c0000 /* OBFF support mechanism */ | 664 | #define PCI_EXP_DEVCAP2_OBFF_MASK 0x000c0000 /* OBFF support mechanism */ |
| 663 | #define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000 /* New message signaling */ | 665 | #define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000 /* New message signaling */ |
| 664 | #define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000 /* Re-use WAKE# for OBFF */ | 666 | #define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000 /* Re-use WAKE# for OBFF */ |
| @@ -1023,15 +1025,34 @@ · 358 unmodified lines | |||
| 1023 | #define PCI_DPA_CAP_SUBSTATE_MASK 0x1F /* # substates - 1 */ | 1025 | #define PCI_DPA_CAP_SUBSTATE_MASK 0x1F /* # substates - 1 */ |
| 1024 | #define PCI_DPA_BASE_SIZEOF 16 /* size with 0 substates */ | 1026 | #define PCI_DPA_BASE_SIZEOF 16 /* size with 0 substates */ |
| 1025 | 1027 | ||
| 1028 | /* TPH Completer Support */ | ||
| 1029 | #define PCI_EXP_DEVCAP2_TPH_COMP_NONE 0x0 /* None */ | ||
| 1030 | #define PCI_EXP_DEVCAP2_TPH_COMP_TPH_ONLY 0x1 /* TPH only */ | ||
| 1031 | #define PCI_EXP_DEVCAP2_TPH_COMP_EXT_TPH 0x3 /* TPH and Extended TPH */ | ||
| 1032 | |||
| 1026 | /* TPH Requester */ | 1033 | /* TPH Requester */ |
| 1027 | #define PCI_TPH_CAP 4 /* capability register */ | 1034 | #define PCI_TPH_CAP 4 /* capability register */ |
| 1028 | #define PCI_TPH_CAP_LOC_MASK 0x600 /* location mask */ | 1035 | #define PCI_TPH_CAP_ST_NS 0x00000001 /* No ST Mode Supported */ |
| 1029 | #define PCI_TPH_LOC_NONE 0x000 /* no location */ | 1036 | #define PCI_TPH_CAP_ST_IV 0x00000002 /* Interrupt Vector Mode Supported */ |
| 1030 | #define PCI_TPH_LOC_CAP 0x200 /* in capability */ | 1037 | #define PCI_TPH_CAP_ST_DS 0x00000004 /* Device Specific Mode Supported */ |
| 1031 | #define PCI_TPH_LOC_MSIX 0x400 /* in MSI-X */ | 1038 | #define PCI_TPH_CAP_EXT_TPH 0x00000100 /* Ext TPH Requester Supported */ |
| 1032 | #define PCI_TPH_CAP_ST_MASK 0x07FF0000 /* ST table mask */ | 1039 | #define PCI_TPH_CAP_LOC_MASK 0x00000600 /* ST Table Location */ |
| 1033 | #define PCI_TPH_CAP_ST_SHIFT 16 /* ST table shift */ | 1040 | #define PCI_TPH_LOC_NONE 0x00000000 /* Not present */ |
| 1034 | #define PCI_TPH_BASE_SIZEOF 0xc /* size with no ST table */ | 1041 | #define PCI_TPH_LOC_CAP 0x00000200 /* In capability */ |
| 1042 | #define PCI_TPH_LOC_MSIX 0x00000400 /* In MSI-X */ | ||
| 1043 | #define PCI_TPH_CAP_ST_MASK 0x07FF0000 /* ST Table Size */ | ||
| 1044 | #define PCI_TPH_CAP_ST_SHIFT 16 /* ST Table Size shift */ | ||
| 1045 | #define PCI_TPH_BASE_SIZEOF 0xc /* Size with no ST table */ | ||
| 1046 | |||
| 1047 | #define PCI_TPH_CTRL 8 /* control register */ | ||
| 1048 | #define PCI_TPH_CTRL_MODE_SEL_MASK 0x00000007 /* ST Mode Select */ | ||
| 1049 | #define PCI_TPH_ST_NS_MODE 0x0 /* No ST Mode */ | ||
| 1050 | #define PCI_TPH_ST_IV_MODE 0x1 /* Interrupt Vector Mode */ | ||
| 1051 | #define PCI_TPH_ST_DS_MODE 0x2 /* Device Specific Mode */ | ||
| 1052 | #define PCI_TPH_CTRL_REQ_EN_MASK 0x00000300 /* TPH Requester Enable */ | ||
| 1053 | #define PCI_TPH_REQ_DISABLE 0x0 /* No TPH requests allowed */ | ||
| 1054 | #define PCI_TPH_REQ_TPH_ONLY 0x1 /* TPH only requests allowed */ | ||
| 1055 | #define PCI_TPH_REQ_EXT_TPH 0x3 /* Extended TPH requests allowed */ | ||
| 1035 | 1056 | ||
| 1036 | /* Downstream Port Containment */ | 1057 | /* Downstream Port Containment */ |
| 1037 | #define PCI_EXP_DPC_CAP 0x04 /* DPC Capability */ | 1058 | #define PCI_EXP_DPC_CAP 0x04 /* DPC Capability */ |