Fix whitespace, capitalization, and spelling errors. No functional change. I know "busses" is not an error, but "buses" was more common, so I used it consistently.
Showing the changes to include/uapi/linux (1 of 65 files). Show all
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| @@ -13,10 +13,10 @@ · 12 unmodified lines | |||
| 13 | * PCI to PCI Bridge Specification | 13 | * PCI to PCI Bridge Specification |
| 14 | * PCI System Design Guide | 14 | * PCI System Design Guide |
| 15 | * | 15 | * |
| 16 | * For hypertransport information, please consult the following manuals | 16 | * For HyperTransport information, please consult the following manuals |
| 17 | * from http://www.hypertransport.org | 17 | * from http://www.hypertransport.org |
| 18 | * | 18 | * |
| 19 | * The Hypertransport I/O Link Specification | 19 | * The HyperTransport I/O Link Specification |
| 20 | */ | 20 | */ |
| 21 | 21 | ||
| 22 | #ifndef LINUX_PCI_REGS_H | 22 | #ifndef LINUX_PCI_REGS_H |
| @@ -37,7 +37,7 @@ · 14 unmodified lines | |||
| 37 | #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */ | 37 | #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */ |
| 38 | #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */ | 38 | #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */ |
| 39 | #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */ | 39 | #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */ |
| 40 | #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */ | 40 | #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */ |
| 41 | #define PCI_COMMAND_SERR 0x100 /* Enable SERR */ | 41 | #define PCI_COMMAND_SERR 0x100 /* Enable SERR */ |
| 42 | #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ | 42 | #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ |
| 43 | #define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */ | 43 | #define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */ |
| @@ -45,7 +45,7 @@ · 1 unmodified line | |||
| 45 | #define PCI_STATUS 0x06 /* 16 bits */ | 45 | #define PCI_STATUS 0x06 /* 16 bits */ |
| 46 | #define PCI_STATUS_INTERRUPT 0x08 /* Interrupt status */ | 46 | #define PCI_STATUS_INTERRUPT 0x08 /* Interrupt status */ |
| 47 | #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */ | 47 | #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */ |
| 48 | #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */ | 48 | #define PCI_STATUS_66MHZ 0x20 /* Support 66 MHz PCI 2.1 bus */ |
| 49 | #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */ | 49 | #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */ |
| 50 | #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */ | 50 | #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */ |
| 51 | #define PCI_STATUS_PARITY 0x100 /* Detected parity error */ | 51 | #define PCI_STATUS_PARITY 0x100 /* Detected parity error */ |
| @@ -205,14 +205,14 @@ · 153 unmodified lines | |||
| 205 | #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ | 205 | #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ |
| 206 | #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */ | 206 | #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */ |
| 207 | #define PCI_CAP_ID_HT 0x08 /* HyperTransport */ | 207 | #define PCI_CAP_ID_HT 0x08 /* HyperTransport */ |
| 208 | #define PCI_CAP_ID_VNDR 0x09 /* Vendor specific */ | 208 | #define PCI_CAP_ID_VNDR 0x09 /* Vendor-Specific */ |
| 209 | #define PCI_CAP_ID_DBG 0x0A /* Debug port */ | 209 | #define PCI_CAP_ID_DBG 0x0A /* Debug port */ |
| 210 | #define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */ | 210 | #define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */ |
| 211 | #define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */ | 211 | #define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */ |
| 212 | #define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */ | 212 | #define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */ |
| 213 | #define PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */ | 213 | #define PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */ |
| 214 | #define PCI_CAP_ID_SECDEV 0x0F /* Secure Device */ | 214 | #define PCI_CAP_ID_SECDEV 0x0F /* Secure Device */ |
| 215 | #define PCI_CAP_ID_EXP 0x10 /* PCI Express */ | 215 | #define PCI_CAP_ID_EXP 0x10 /* PCI Express */ |
| 216 | #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */ | 216 | #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */ |
| 217 | #define PCI_CAP_ID_SATA 0x12 /* SATA Data/Index Conf. */ | 217 | #define PCI_CAP_ID_SATA 0x12 /* SATA Data/Index Conf. */ |
| 218 | #define PCI_CAP_ID_AF 0x13 /* PCI Advanced Features */ | 218 | #define PCI_CAP_ID_AF 0x13 /* PCI Advanced Features */ |
| @@ -268,8 +268,8 @@ · 49 unmodified lines | |||
| 268 | #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */ | 268 | #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */ |
| 269 | #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */ | 269 | #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */ |
| 270 | #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */ | 270 | #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */ |
| 271 | #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */ | 271 | #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */ |
| 272 | #define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */ | 272 | #define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */ |
| 273 | #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */ | 273 | #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */ |
| 274 | #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate */ | 274 | #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate */ |
| 275 | #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate */ | 275 | #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate */ |
| @@ -321,7 +321,7 @@ · 45 unmodified lines | |||
| 321 | #define PCI_MSIX_PBA_OFFSET 0xfffffff8 /* Offset into specified BAR */ | 321 | #define PCI_MSIX_PBA_OFFSET 0xfffffff8 /* Offset into specified BAR */ |
| 322 | #define PCI_CAP_MSIX_SIZEOF 12 /* size of MSIX registers */ | 322 | #define PCI_CAP_MSIX_SIZEOF 12 /* size of MSIX registers */ |
| 323 | 323 | ||
| 324 | /* MSI-X entry's format */ | 324 | /* MSI-X Table entry format */ |
| 325 | #define PCI_MSIX_ENTRY_SIZE 16 | 325 | #define PCI_MSIX_ENTRY_SIZE 16 |
| 326 | #define PCI_MSIX_ENTRY_LOWER_ADDR 0 | 326 | #define PCI_MSIX_ENTRY_LOWER_ADDR 0 |
| 327 | #define PCI_MSIX_ENTRY_UPPER_ADDR 4 | 327 | #define PCI_MSIX_ENTRY_UPPER_ADDR 4 |
| @@ -372,7 +372,7 @@ · 44 unmodified lines | |||
| 372 | #define PCI_X_CMD_SPLIT_16 0x0060 /* Max 16 */ | 372 | #define PCI_X_CMD_SPLIT_16 0x0060 /* Max 16 */ |
| 373 | #define PCI_X_CMD_SPLIT_32 0x0070 /* Max 32 */ | 373 | #define PCI_X_CMD_SPLIT_32 0x0070 /* Max 32 */ |
| 374 | #define PCI_X_CMD_MAX_SPLIT 0x0070 /* Max Outstanding Split Transactions */ | 374 | #define PCI_X_CMD_MAX_SPLIT 0x0070 /* Max Outstanding Split Transactions */ |
| 375 | #define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */ | 375 | #define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */ |
| 376 | #define PCI_X_STATUS 4 /* PCI-X capabilities */ | 376 | #define PCI_X_STATUS 4 /* PCI-X capabilities */ |
| 377 | #define PCI_X_STATUS_DEVFN 0x000000ff /* A copy of devfn */ | 377 | #define PCI_X_STATUS_DEVFN 0x000000ff /* A copy of devfn */ |
| 378 | #define PCI_X_STATUS_BUS 0x0000ff00 /* A copy of bus nr */ | 378 | #define PCI_X_STATUS_BUS 0x0000ff00 /* A copy of bus nr */ |
| @@ -407,8 +407,8 @@ · 28 unmodified lines | |||
| 407 | 407 | ||
| 408 | /* PCI Bridge Subsystem ID registers */ | 408 | /* PCI Bridge Subsystem ID registers */ |
| 409 | 409 | ||
| 410 | #define PCI_SSVID_VENDOR_ID 4 /* PCI-Bridge subsystem vendor id register */ | 410 | #define PCI_SSVID_VENDOR_ID 4 /* PCI Bridge subsystem vendor ID */ |
| 411 | #define PCI_SSVID_DEVICE_ID 6 /* PCI-Bridge subsystem device id register */ | 411 | #define PCI_SSVID_DEVICE_ID 6 /* PCI Bridge subsystem device ID */ |
| 412 | 412 | ||
| 413 | /* PCI Express capability registers */ | 413 | /* PCI Express capability registers */ |
| 414 | 414 | ||
| @@ -484,12 +484,12 @@ · 69 unmodified lines | |||
| 484 | #define PCI_EXP_LNKCTL_CLKREQ_EN 0x0100 /* Enable clkreq */ | 484 | #define PCI_EXP_LNKCTL_CLKREQ_EN 0x0100 /* Enable clkreq */ |
| 485 | #define PCI_EXP_LNKCTL_HAWD 0x0200 /* Hardware Autonomous Width Disable */ | 485 | #define PCI_EXP_LNKCTL_HAWD 0x0200 /* Hardware Autonomous Width Disable */ |
| 486 | #define PCI_EXP_LNKCTL_LBMIE 0x0400 /* Link Bandwidth Management Interrupt Enable */ | 486 | #define PCI_EXP_LNKCTL_LBMIE 0x0400 /* Link Bandwidth Management Interrupt Enable */ |
| 487 | #define PCI_EXP_LNKCTL_LABIE 0x0800 /* Lnk Autonomous Bandwidth Interrupt Enable */ | 487 | #define PCI_EXP_LNKCTL_LABIE 0x0800 /* Link Autonomous Bandwidth Interrupt Enable */ |
| 488 | #define PCI_EXP_LNKSTA 18 /* Link Status */ | 488 | #define PCI_EXP_LNKSTA 18 /* Link Status */ |
| 489 | #define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */ | 489 | #define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */ |
| 490 | #define PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */ | 490 | #define PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */ |
| 491 | #define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */ | 491 | #define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */ |
| 492 | #define PCI_EXP_LNKSTA_NLW 0x03f0 /* Nogotiated Link Width */ | 492 | #define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */ |
| 493 | #define PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */ | 493 | #define PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */ |
| 494 | #define PCI_EXP_LNKSTA_LT 0x0800 /* Link Training */ | 494 | #define PCI_EXP_LNKSTA_LT 0x0800 /* Link Training */ |
| 495 | #define PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */ | 495 | #define PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */ |
| @@ -593,7 +593,7 @@ · 97 unmodified lines | |||
| 593 | #define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function VC Capability */ | 593 | #define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function VC Capability */ |
| 594 | #define PCI_EXT_CAP_ID_VC9 0x09 /* same as _VC */ | 594 | #define PCI_EXT_CAP_ID_VC9 0x09 /* same as _VC */ |
| 595 | #define PCI_EXT_CAP_ID_RCRB 0x0A /* Root Complex RB? */ | 595 | #define PCI_EXT_CAP_ID_RCRB 0x0A /* Root Complex RB? */ |
| 596 | #define PCI_EXT_CAP_ID_VNDR 0x0B /* Vendor Specific */ | 596 | #define PCI_EXT_CAP_ID_VNDR 0x0B /* Vendor-Specific */ |
| 597 | #define PCI_EXT_CAP_ID_CAC 0x0C /* Config Access - obsolete */ | 597 | #define PCI_EXT_CAP_ID_CAC 0x0C /* Config Access - obsolete */ |
| 598 | #define PCI_EXT_CAP_ID_ACS 0x0D /* Access Control Services */ | 598 | #define PCI_EXT_CAP_ID_ACS 0x0D /* Access Control Services */ |
| 599 | #define PCI_EXT_CAP_ID_ARI 0x0E /* Alternate Routing ID */ | 599 | #define PCI_EXT_CAP_ID_ARI 0x0E /* Alternate Routing ID */ |
| @@ -602,12 +602,12 @@ · 2 unmodified lines | |||
| 602 | #define PCI_EXT_CAP_ID_MRIOV 0x11 /* Multi Root I/O Virtualization */ | 602 | #define PCI_EXT_CAP_ID_MRIOV 0x11 /* Multi Root I/O Virtualization */ |
| 603 | #define PCI_EXT_CAP_ID_MCAST 0x12 /* Multicast */ | 603 | #define PCI_EXT_CAP_ID_MCAST 0x12 /* Multicast */ |
| 604 | #define PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */ | 604 | #define PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */ |
| 605 | #define PCI_EXT_CAP_ID_AMD_XXX 0x14 /* reserved for AMD */ | 605 | #define PCI_EXT_CAP_ID_AMD_XXX 0x14 /* Reserved for AMD */ |
| 606 | #define PCI_EXT_CAP_ID_REBAR 0x15 /* resizable BAR */ | 606 | #define PCI_EXT_CAP_ID_REBAR 0x15 /* Resizable BAR */ |
| 607 | #define PCI_EXT_CAP_ID_DPA 0x16 /* dynamic power alloc */ | 607 | #define PCI_EXT_CAP_ID_DPA 0x16 /* Dynamic Power Allocation */ |
| 608 | #define PCI_EXT_CAP_ID_TPH 0x17 /* TPH request */ | 608 | #define PCI_EXT_CAP_ID_TPH 0x17 /* TPH Requester */ |
| 609 | #define PCI_EXT_CAP_ID_LTR 0x18 /* latency tolerance reporting */ | 609 | #define PCI_EXT_CAP_ID_LTR 0x18 /* Latency Tolerance Reporting */ |
| 610 | #define PCI_EXT_CAP_ID_SECPCI 0x19 /* Secondary PCIe */ | 610 | #define PCI_EXT_CAP_ID_SECPCI 0x19 /* Secondary PCIe Capability */ |
| 611 | #define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */ | 611 | #define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */ |
| 612 | #define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */ | 612 | #define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */ |
| 613 | #define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PASID | 613 | #define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PASID |
| @@ -667,9 +667,9 @@ · 53 unmodified lines | |||
| 667 | #define PCI_ERR_ROOT_COR_RCV 0x00000001 /* ERR_COR Received */ | 667 | #define PCI_ERR_ROOT_COR_RCV 0x00000001 /* ERR_COR Received */ |
| 668 | /* Multi ERR_COR Received */ | 668 | /* Multi ERR_COR Received */ |
| 669 | #define PCI_ERR_ROOT_MULTI_COR_RCV 0x00000002 | 669 | #define PCI_ERR_ROOT_MULTI_COR_RCV 0x00000002 |
| 670 | /* ERR_FATAL/NONFATAL Recevied */ | 670 | /* ERR_FATAL/NONFATAL Received */ |
| 671 | #define PCI_ERR_ROOT_UNCOR_RCV 0x00000004 | 671 | #define PCI_ERR_ROOT_UNCOR_RCV 0x00000004 |
| 672 | /* Multi ERR_FATAL/NONFATAL Recevied */ | 672 | /* Multi ERR_FATAL/NONFATAL Received */ |
| 673 | #define PCI_ERR_ROOT_MULTI_UNCOR_RCV 0x00000008 | 673 | #define PCI_ERR_ROOT_MULTI_UNCOR_RCV 0x00000008 |
| 674 | #define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 /* First Fatal */ | 674 | #define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 /* First Fatal */ |
| 675 | #define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 /* Non-Fatal Received */ | 675 | #define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 /* Non-Fatal Received */ |
| @@ -678,7 +678,7 @@ · 2 unmodified lines | |||
| 678 | 678 | ||
| 679 | /* Virtual Channel */ | 679 | /* Virtual Channel */ |
| 680 | #define PCI_VC_PORT_REG1 4 | 680 | #define PCI_VC_PORT_REG1 4 |
| 681 | #define PCI_VC_REG1_EVCC 0x7 /* extended vc count */ | 681 | #define PCI_VC_REG1_EVCC 0x7 /* extended VC count */ |
| 682 | #define PCI_VC_PORT_REG2 8 | 682 | #define PCI_VC_PORT_REG2 8 |
| 683 | #define PCI_VC_REG2_32_PHASE 0x2 | 683 | #define PCI_VC_REG2_32_PHASE 0x2 |
| 684 | #define PCI_VC_REG2_64_PHASE 0x4 | 684 | #define PCI_VC_REG2_64_PHASE 0x4 |
| @@ -711,7 +711,7 @@ · 26 unmodified lines | |||
| 711 | #define PCI_VNDR_HEADER_LEN(x) (((x) >> 20) & 0xfff) | 711 | #define PCI_VNDR_HEADER_LEN(x) (((x) >> 20) & 0xfff) |
| 712 | 712 | ||
| 713 | /* | 713 | /* |
| 714 | * Hypertransport sub capability types | 714 | * HyperTransport sub capability types |
| 715 | * | 715 | * |
| 716 | * Unfortunately there are both 3 bit and 5 bit capability types defined | 716 | * Unfortunately there are both 3 bit and 5 bit capability types defined |
| 717 | * in the HT spec, catering for that is a little messy. You probably don't | 717 | * in the HT spec, catering for that is a little messy. You probably don't |
| @@ -739,8 +739,8 @@ · 21 unmodified lines | |||
| 739 | #define HT_CAPTYPE_DIRECT_ROUTE 0xB0 /* Direct routing configuration */ | 739 | #define HT_CAPTYPE_DIRECT_ROUTE 0xB0 /* Direct routing configuration */ |
| 740 | #define HT_CAPTYPE_VCSET 0xB8 /* Virtual Channel configuration */ | 740 | #define HT_CAPTYPE_VCSET 0xB8 /* Virtual Channel configuration */ |
| 741 | #define HT_CAPTYPE_ERROR_RETRY 0xC0 /* Retry on error configuration */ | 741 | #define HT_CAPTYPE_ERROR_RETRY 0xC0 /* Retry on error configuration */ |
| 742 | #define HT_CAPTYPE_GEN3 0xD0 /* Generation 3 hypertransport configuration */ | 742 | #define HT_CAPTYPE_GEN3 0xD0 /* Generation 3 HyperTransport configuration */ |
| 743 | #define HT_CAPTYPE_PM 0xE0 /* Hypertransport powermanagement configuration */ | 743 | #define HT_CAPTYPE_PM 0xE0 /* HyperTransport power management configuration */ |
| 744 | #define HT_CAP_SIZEOF_LONG 28 /* slave & primary */ | 744 | #define HT_CAP_SIZEOF_LONG 28 /* slave & primary */ |
| 745 | #define HT_CAP_SIZEOF_SHORT 24 /* host & secondary */ | 745 | #define HT_CAP_SIZEOF_SHORT 24 /* host & secondary */ |
| 746 | 746 | ||
| @@ -777,14 +777,14 @@ · 30 unmodified lines | |||
| 777 | #define PCI_PRI_ALLOC_REQ 0x0c /* PRI max reqs allowed */ | 777 | #define PCI_PRI_ALLOC_REQ 0x0c /* PRI max reqs allowed */ |
| 778 | #define PCI_EXT_CAP_PRI_SIZEOF 16 | 778 | #define PCI_EXT_CAP_PRI_SIZEOF 16 |
| 779 | 779 | ||
| 780 | /* PASID capability */ | 780 | /* Process Address Space ID */ |
| 781 | #define PCI_PASID_CAP 0x04 /* PASID feature register */ | 781 | #define PCI_PASID_CAP 0x04 /* PASID feature register */ |
| 782 | #define PCI_PASID_CAP_EXEC 0x02 /* Exec permissions Supported */ | 782 | #define PCI_PASID_CAP_EXEC 0x02 /* Exec permissions Supported */ |
| 783 | #define PCI_PASID_CAP_PRIV 0x04 /* Priviledge Mode Supported */ | 783 | #define PCI_PASID_CAP_PRIV 0x04 /* Privilege Mode Supported */ |
| 784 | #define PCI_PASID_CTRL 0x06 /* PASID control register */ | 784 | #define PCI_PASID_CTRL 0x06 /* PASID control register */ |
| 785 | #define PCI_PASID_CTRL_ENABLE 0x01 /* Enable bit */ | 785 | #define PCI_PASID_CTRL_ENABLE 0x01 /* Enable bit */ |
| 786 | #define PCI_PASID_CTRL_EXEC 0x02 /* Exec permissions Enable */ | 786 | #define PCI_PASID_CTRL_EXEC 0x02 /* Exec permissions Enable */ |
| 787 | #define PCI_PASID_CTRL_PRIV 0x04 /* Priviledge Mode Enable */ | 787 | #define PCI_PASID_CTRL_PRIV 0x04 /* Privilege Mode Enable */ |
| 788 | #define PCI_EXT_CAP_PASID_SIZEOF 8 | 788 | #define PCI_EXT_CAP_PASID_SIZEOF 8 |
| 789 | 789 | ||
| 790 | /* Single Root I/O Virtualization */ | 790 | /* Single Root I/O Virtualization */ |
| @@ -839,22 +839,22 @@ · 48 unmodified lines | |||
| 839 | #define PCI_ACS_CTRL 0x06 /* ACS Control Register */ | 839 | #define PCI_ACS_CTRL 0x06 /* ACS Control Register */ |
| 840 | #define PCI_ACS_EGRESS_CTL_V 0x08 /* ACS Egress Control Vector */ | 840 | #define PCI_ACS_EGRESS_CTL_V 0x08 /* ACS Egress Control Vector */ |
| 841 | 841 | ||
| 842 | #define PCI_VSEC_HDR 4 /* extended cap - vendor specific */ | 842 | #define PCI_VSEC_HDR 4 /* extended cap - vendor-specific */ |
| 843 | #define PCI_VSEC_HDR_LEN_SHIFT 20 /* shift for length field */ | 843 | #define PCI_VSEC_HDR_LEN_SHIFT 20 /* shift for length field */ |
| 844 | 844 | ||
| 845 | /* sata capability */ | 845 | /* SATA capability */ |
| 846 | #define PCI_SATA_REGS 4 /* SATA REGs specifier */ | 846 | #define PCI_SATA_REGS 4 /* SATA REGs specifier */ |
| 847 | #define PCI_SATA_REGS_MASK 0xF /* location - BAR#/inline */ | 847 | #define PCI_SATA_REGS_MASK 0xF /* location - BAR#/inline */ |
| 848 | #define PCI_SATA_REGS_INLINE 0xF /* REGS in config space */ | 848 | #define PCI_SATA_REGS_INLINE 0xF /* REGS in config space */ |
| 849 | #define PCI_SATA_SIZEOF_SHORT 8 | 849 | #define PCI_SATA_SIZEOF_SHORT 8 |
| 850 | #define PCI_SATA_SIZEOF_LONG 16 | 850 | #define PCI_SATA_SIZEOF_LONG 16 |
| 851 | 851 | ||
| 852 | /* resizable BARs */ | 852 | /* Resizable BARs */ |
| 853 | #define PCI_REBAR_CTRL 8 /* control register */ | 853 | #define PCI_REBAR_CTRL 8 /* control register */ |
| 854 | #define PCI_REBAR_CTRL_NBAR_MASK (7 << 5) /* mask for # bars */ | 854 | #define PCI_REBAR_CTRL_NBAR_MASK (7 << 5) /* mask for # bars */ |
| 855 | #define PCI_REBAR_CTRL_NBAR_SHIFT 5 /* shift for # bars */ | 855 | #define PCI_REBAR_CTRL_NBAR_SHIFT 5 /* shift for # bars */ |
| 856 | 856 | ||
| 857 | /* dynamic power allocation */ | 857 | /* Dynamic Power Allocation */ |
| 858 | #define PCI_DPA_CAP 4 /* capability register */ | 858 | #define PCI_DPA_CAP 4 /* capability register */ |
| 859 | #define PCI_DPA_CAP_SUBSTATE_MASK 0x1F /* # substates - 1 */ | 859 | #define PCI_DPA_CAP_SUBSTATE_MASK 0x1F /* # substates - 1 */ |
| 860 | #define PCI_DPA_BASE_SIZEOF 16 /* size with 0 substates */ | 860 | #define PCI_DPA_BASE_SIZEOF 16 /* size with 0 substates */ |