History

drm/radeon: add GET_PARAM/INFO support for Z pipes

Needed for occlusion queries on rv530 chips.

Alex Deucher committed 17 years ago

Commit f779b3e1 parent 17782d910 files · +39 −4Browse files

Unified · Split

10 files
  1. drivers/gpu/drm/radeon/r300.c +3 −1
  2. drivers/gpu/drm/radeon/r420.c +12 −1
  3. drivers/gpu/drm/radeon/r520.c +0 −1
  4. drivers/gpu/drm/radeon/radeon.h +1 −0
  5. drivers/gpu/drm/radeon/radeon_cp.c +9 −0
  6. drivers/gpu/drm/radeon/radeon_drv.h +4 −1
  7. drivers/gpu/drm/radeon/radeon_kms.c +3 −0
  8. drivers/gpu/drm/radeon/radeon_reg.h +2 −0
  9. drivers/gpu/drm/radeon/radeon_state.c +3 −0
  10. include/drm/radeon_drm.h +2 −0
drivers/gpu/drm/radeon/r300.c+3−1
@@ -448,6 +448,7 @@ void r300_gpu_init(struct radeon_device *rdev) · 447 unmodified lines
448 /* rv350,rv370,rv380 */448 /* rv350,rv370,rv380 */
449 rdev->num_gb_pipes = 1;449 rdev->num_gb_pipes = 1;
450 }450 }
451 rdev->num_z_pipes = 1;
451 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);452 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
452 switch (rdev->num_gb_pipes) {453 switch (rdev->num_gb_pipes) {
453 case 2:454 case 2:
@@ -486,7 +487,8 @@ void r300_gpu_init(struct radeon_device *rdev) · 32 unmodified lines
486 printk(KERN_WARNING "Failed to wait MC idle while "487 printk(KERN_WARNING "Failed to wait MC idle while "
487 "programming pipes. Bad things might happen.\n");488 "programming pipes. Bad things might happen.\n");
488 }489 }
489 DRM_INFO("radeon: %d pipes initialized.\n", rdev->num_gb_pipes);490 DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n",
491 rdev->num_gb_pipes, rdev->num_z_pipes);
490}492}
491 493
492int r300_ga_reset(struct radeon_device *rdev)494int r300_ga_reset(struct radeon_device *rdev)
drivers/gpu/drm/radeon/r420.c+12−1
@@ -165,7 +165,18 @@ void r420_pipes_init(struct radeon_device *rdev) · 164 unmodified lines
165 printk(KERN_WARNING "Failed to wait GUI idle while "165 printk(KERN_WARNING "Failed to wait GUI idle while "
166 "programming pipes. Bad things might happen.\n");166 "programming pipes. Bad things might happen.\n");
167 }167 }
168 DRM_INFO("radeon: %d pipes initialized.\n", rdev->num_gb_pipes);168
169 if (rdev->family == CHIP_RV530) {
170 tmp = RREG32(RV530_GB_PIPE_SELECT2);
171 if ((tmp & 3) == 3)
172 rdev->num_z_pipes = 2;
173 else
174 rdev->num_z_pipes = 1;
175 } else
176 rdev->num_z_pipes = 1;
177
178 DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n",
179 rdev->num_gb_pipes, rdev->num_z_pipes);
169}180}
170 181
171void r420_gpu_init(struct radeon_device *rdev)182void r420_gpu_init(struct radeon_device *rdev)
drivers/gpu/drm/radeon/r520.c+0−1
@@ -177,7 +177,6 @@ void r520_gpu_init(struct radeon_device *rdev) · 176 unmodified lines
177 */177 */
178 /* workaround for RV530 */178 /* workaround for RV530 */
179 if (rdev->family == CHIP_RV530) {179 if (rdev->family == CHIP_RV530) {
180 WREG32(0x4124, 1);
181 WREG32(0x4128, 0xFF);180 WREG32(0x4128, 0xFF);
182 }181 }
183 r420_pipes_init(rdev);182 r420_pipes_init(rdev);
drivers/gpu/drm/radeon/radeon.h+1−0
@@ -655,6 +655,7 @@ struct radeon_device { · 654 unmodified lines
655 int usec_timeout;655 int usec_timeout;
656 enum radeon_pll_errata pll_errata;656 enum radeon_pll_errata pll_errata;
657 int num_gb_pipes;657 int num_gb_pipes;
658 int num_z_pipes;
658 int disp_priority;659 int disp_priority;
659 /* BIOS */660 /* BIOS */
660 uint8_t *bios;661 uint8_t *bios;
drivers/gpu/drm/radeon/radeon_cp.c+9−0
@@ -406,6 +406,15 @@ static void radeon_init_pipes(drm_radeon_private_t *dev_priv) · 405 unmodified lines
406{406{
407 uint32_t gb_tile_config, gb_pipe_sel = 0;407 uint32_t gb_tile_config, gb_pipe_sel = 0;
408 408
409 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) {
410 uint32_t z_pipe_sel = RADEON_READ(RV530_GB_PIPE_SELECT2);
411 if ((z_pipe_sel & 3) == 3)
412 dev_priv->num_z_pipes = 2;
413 else
414 dev_priv->num_z_pipes = 1;
415 } else
416 dev_priv->num_z_pipes = 1;
417
409 /* RS4xx/RS6xx/R4xx/R5xx */418 /* RS4xx/RS6xx/R4xx/R5xx */
410 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {419 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
411 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);420 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
drivers/gpu/drm/radeon/radeon_drv.h+4−1
@@ -100,9 +100,10 @@ · 99 unmodified lines
100 * 1.28- Add support for VBL on CRTC2100 * 1.28- Add support for VBL on CRTC2
101 * 1.29- R500 3D cmd buffer support101 * 1.29- R500 3D cmd buffer support
102 * 1.30- Add support for occlusion queries102 * 1.30- Add support for occlusion queries
103 * 1.31- Add support for num Z pipes from GET_PARAM
103 */104 */
104#define DRIVER_MAJOR 1105#define DRIVER_MAJOR 1
105#define DRIVER_MINOR 30106#define DRIVER_MINOR 31
106#define DRIVER_PATCHLEVEL 0107#define DRIVER_PATCHLEVEL 0
107 108
108/*109/*
@@ -329,6 +330,7 @@ typedef struct drm_radeon_private { · 220 unmodified lines
329 resource_size_t fb_aper_offset;330 resource_size_t fb_aper_offset;
330 331
331 int num_gb_pipes;332 int num_gb_pipes;
333 int num_z_pipes;
332 int track_flush;334 int track_flush;
333 drm_local_map_t *mmio;335 drm_local_map_t *mmio;
334 336
@@ -689,6 +691,7 @@ extern void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pciga · 354 unmodified lines
689 691
690/* pipe config regs */692/* pipe config regs */
691#define R400_GB_PIPE_SELECT 0x402c693#define R400_GB_PIPE_SELECT 0x402c
694#define RV530_GB_PIPE_SELECT2 0x4124
692#define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */695#define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */
693#define R300_GB_TILE_CONFIG 0x4018696#define R300_GB_TILE_CONFIG 0x4018
694# define R300_ENABLE_TILING (1 << 0)697# define R300_ENABLE_TILING (1 << 0)
drivers/gpu/drm/radeon/radeon_kms.c+3−0
@@ -95,6 +95,9 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) · 94 unmodified lines
95 case RADEON_INFO_NUM_GB_PIPES:95 case RADEON_INFO_NUM_GB_PIPES:
96 value = rdev->num_gb_pipes;96 value = rdev->num_gb_pipes;
97 break;97 break;
98 case RADEON_INFO_NUM_Z_PIPES:
99 value = rdev->num_z_pipes;
100 break;
98 default:101 default:
99 DRM_DEBUG("Invalid request %d\n", info->request);102 DRM_DEBUG("Invalid request %d\n", info->request);
100 return -EINVAL;103 return -EINVAL;
drivers/gpu/drm/radeon/radeon_reg.h+2−0
@@ -3574,4 +3574,6 @@ · 3573 unmodified lines
3574#define RADEON_SCRATCH_REG4 0x15f03574#define RADEON_SCRATCH_REG4 0x15f0
3575#define RADEON_SCRATCH_REG5 0x15f43575#define RADEON_SCRATCH_REG5 0x15f4
3576 3576
3577#define RV530_GB_PIPE_SELECT2 0x4124
3578
3577#endif3579#endif
drivers/gpu/drm/radeon/radeon_state.c+3−0
@@ -3081,6 +3081,9 @@ static int radeon_cp_getparam(struct drm_device *dev, void *data, struct drm_fil · 3080 unmodified lines
3081 case RADEON_PARAM_NUM_GB_PIPES:3081 case RADEON_PARAM_NUM_GB_PIPES:
3082 value = dev_priv->num_gb_pipes;3082 value = dev_priv->num_gb_pipes;
3083 break;3083 break;
3084 case RADEON_PARAM_NUM_Z_PIPES:
3085 value = dev_priv->num_z_pipes;
3086 break;
3084 default:3087 default:
3085 DRM_DEBUG("Invalid parameter %d\n", param->param);3088 DRM_DEBUG("Invalid parameter %d\n", param->param);
3086 return -EINVAL;3089 return -EINVAL;
include/drm/radeon_drm.h+2−0
@@ -709,6 +709,7 @@ typedef struct drm_radeon_indirect { · 708 unmodified lines
709#define RADEON_PARAM_FB_LOCATION 14 /* FB location */709#define RADEON_PARAM_FB_LOCATION 14 /* FB location */
710#define RADEON_PARAM_NUM_GB_PIPES 15 /* num GB pipes */710#define RADEON_PARAM_NUM_GB_PIPES 15 /* num GB pipes */
711#define RADEON_PARAM_DEVICE_ID 16711#define RADEON_PARAM_DEVICE_ID 16
712#define RADEON_PARAM_NUM_Z_PIPES 17 /* num Z pipes */
712 713
713typedef struct drm_radeon_getparam {714typedef struct drm_radeon_getparam {
714 int param;715 int param;
@@ -897,6 +898,7 @@ struct drm_radeon_cs { · 182 unmodified lines
897 898
898#define RADEON_INFO_DEVICE_ID 0x00899#define RADEON_INFO_DEVICE_ID 0x00
899#define RADEON_INFO_NUM_GB_PIPES 0x01900#define RADEON_INFO_NUM_GB_PIPES 0x01
901#define RADEON_INFO_NUM_Z_PIPES 0x02
900 902
901struct drm_radeon_info {903struct drm_radeon_info {
902 uint32_t request;904 uint32_t request;