The IOC4 is a multi-function chip seen on SGI SN2 and some SGI MIPS systems. This removes the base driver, which while not having an SN2 Kconfig dependency was only for sub-drivers that had one.
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| 1 | /* | ||
| 2 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 3 | * License. See the file "COPYING" in the main directory of this archive | ||
| 4 | * for more details. | ||
| 5 | * | ||
| 6 | * Copyright (c) 2005 Silicon Graphics, Inc. All Rights Reserved. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #ifndef _LINUX_IOC4_H | ||
| 10 | #define _LINUX_IOC4_H | ||
| 11 | |||
| 12 | #include <linux/interrupt.h> | ||
| 13 | |||
| 14 | /*************** | ||
| 15 | * Definitions * | ||
| 16 | ***************/ | ||
| 17 | |||
| 18 | /* Miscellaneous values inherent to hardware */ | ||
| 19 | |||
| 20 | #define IOC4_EXTINT_COUNT_DIVISOR 520 /* PCI clocks per COUNT tick */ | ||
| 21 | |||
| 22 | /*********************************** | ||
| 23 | * Structures needed by subdrivers * | ||
| 24 | ***********************************/ | ||
| 25 | |||
| 26 | /* This structure fully describes the IOC4 miscellaneous registers which | ||
| 27 | * appear at bar[0]+0x00000 through bar[0]+0x0005c. The corresponding | ||
| 28 | * PCI resource is managed by the main IOC4 driver because it contains | ||
| 29 | * registers of interest to many different IOC4 subdrivers. | ||
| 30 | */ | ||
| 31 | struct ioc4_misc_regs { | ||
| 32 | /* Miscellaneous IOC4 registers */ | ||
| 33 | union ioc4_pci_err_addr_l { | ||
| 34 | uint32_t raw; | ||
| 35 | struct { | ||
| 36 | uint32_t valid:1; /* Address captured */ | ||
| 37 | uint32_t master_id:4; /* Unit causing error | ||
| 38 | * 0/1: Serial port 0 TX/RX | ||
| 39 | * 2/3: Serial port 1 TX/RX | ||
| 40 | * 4/5: Serial port 2 TX/RX | ||
| 41 | * 6/7: Serial port 3 TX/RX | ||
| 42 | * 8: ATA/ATAPI | ||
| 43 | * 9-15: Undefined | ||
| 44 | */ | ||
| 45 | uint32_t mul_err:1; /* Multiple errors occurred */ | ||
| 46 | uint32_t addr:26; /* Bits 31-6 of error addr */ | ||
| 47 | } fields; | ||
| 48 | } pci_err_addr_l; | ||
| 49 | uint32_t pci_err_addr_h; /* Bits 63-32 of error addr */ | ||
| 50 | union ioc4_sio_int { | ||
| 51 | uint32_t raw; | ||
| 52 | struct { | ||
| 53 | uint8_t tx_mt:1; /* TX ring buffer empty */ | ||
| 54 | uint8_t rx_full:1; /* RX ring buffer full */ | ||
| 55 | uint8_t rx_high:1; /* RX high-water exceeded */ | ||
| 56 | uint8_t rx_timer:1; /* RX timer has triggered */ | ||
| 57 | uint8_t delta_dcd:1; /* DELTA_DCD seen */ | ||
| 58 | uint8_t delta_cts:1; /* DELTA_CTS seen */ | ||
| 59 | uint8_t intr_pass:1; /* Interrupt pass-through */ | ||
| 60 | uint8_t tx_explicit:1; /* TX, MCW, or delay complete */ | ||
| 61 | } fields[4]; | ||
| 62 | } sio_ir; /* Serial interrupt state */ | ||
| 63 | union ioc4_other_int { | ||
| 64 | uint32_t raw; | ||
| 65 | struct { | ||
| 66 | uint32_t ata_int:1; /* ATA port passthru */ | ||
| 67 | uint32_t ata_memerr:1; /* ATA halted by mem error */ | ||
| 68 | uint32_t memerr:4; /* Serial halted by mem err */ | ||
| 69 | uint32_t kbd_int:1; /* kbd/mouse intr asserted */ | ||
| 70 | uint32_t reserved:16; /* zero */ | ||
| 71 | uint32_t rt_int:1; /* INT_OUT section latch */ | ||
| 72 | uint32_t gen_int:8; /* Intr. from generic pins */ | ||
| 73 | } fields; | ||
| 74 | } other_ir; /* Other interrupt state */ | ||
| 75 | union ioc4_sio_int sio_ies; /* Serial interrupt enable set */ | ||
| 76 | union ioc4_other_int other_ies; /* Other interrupt enable set */ | ||
| 77 | union ioc4_sio_int sio_iec; /* Serial interrupt enable clear */ | ||
| 78 | union ioc4_other_int other_iec; /* Other interrupt enable clear */ | ||
| 79 | union ioc4_sio_cr { | ||
| 80 | uint32_t raw; | ||
| 81 | struct { | ||
| 82 | uint32_t cmd_pulse:4; /* Bytebus strobe width */ | ||
| 83 | uint32_t arb_diag:3; /* PCI bus requester */ | ||
| 84 | uint32_t sio_diag_idle:1; /* Active ser req? */ | ||
| 85 | uint32_t ata_diag_idle:1; /* Active ATA req? */ | ||
| 86 | uint32_t ata_diag_active:1; /* ATA req is winner */ | ||
| 87 | uint32_t reserved:22; /* zero */ | ||
| 88 | } fields; | ||
| 89 | } sio_cr; | ||
| 90 | uint32_t unused1; | ||
| 91 | union ioc4_int_out { | ||
| 92 | uint32_t raw; | ||
| 93 | struct { | ||
| 94 | uint32_t count:16; /* Period control */ | ||
| 95 | uint32_t mode:3; /* Output signal shape */ | ||
| 96 | uint32_t reserved:11; /* zero */ | ||
| 97 | uint32_t diag:1; /* Timebase control */ | ||
| 98 | uint32_t int_out:1; /* Current value */ | ||
| 99 | } fields; | ||
| 100 | } int_out; /* External interrupt output control */ | ||
| 101 | uint32_t unused2; | ||
| 102 | union ioc4_gpcr { | ||
| 103 | uint32_t raw; | ||
| 104 | struct { | ||
| 105 | uint32_t dir:8; /* Pin direction */ | ||
| 106 | uint32_t edge:8; /* Edge/level mode */ | ||
| 107 | uint32_t reserved1:4; /* zero */ | ||
| 108 | uint32_t int_out_en:1; /* INT_OUT enable */ | ||
| 109 | uint32_t reserved2:11; /* zero */ | ||
| 110 | } fields; | ||
| 111 | } gpcr_s; /* Generic PIO control set */ | ||
| 112 | union ioc4_gpcr gpcr_c; /* Generic PIO control clear */ | ||
| 113 | union ioc4_gpdr { | ||
| 114 | uint32_t raw; | ||
| 115 | struct { | ||
| 116 | uint32_t gen_pin:8; /* State of pins */ | ||
| 117 | uint32_t reserved:24; | ||
| 118 | } fields; | ||
| 119 | } gpdr; /* Generic PIO data */ | ||
| 120 | uint32_t unused3; | ||
| 121 | union ioc4_gppr { | ||
| 122 | uint32_t raw; | ||
| 123 | struct { | ||
| 124 | uint32_t gen_pin:1; /* Single pin state */ | ||
| 125 | uint32_t reserved:31; | ||
| 126 | } fields; | ||
| 127 | } gppr[8]; /* Generic PIO pins */ | ||
| 128 | }; | ||
| 129 | |||
| 130 | /* Masks for GPCR DIR pins */ | ||
| 131 | #define IOC4_GPCR_DIR_0 0x01 /* External interrupt output */ | ||
| 132 | #define IOC4_GPCR_DIR_1 0x02 /* External interrupt input */ | ||
| 133 | #define IOC4_GPCR_DIR_2 0x04 | ||
| 134 | #define IOC4_GPCR_DIR_3 0x08 /* Keyboard/mouse presence */ | ||
| 135 | #define IOC4_GPCR_DIR_4 0x10 /* Ser. port 0 xcvr select (0=232, 1=422) */ | ||
| 136 | #define IOC4_GPCR_DIR_5 0x20 /* Ser. port 1 xcvr select (0=232, 1=422) */ | ||
| 137 | #define IOC4_GPCR_DIR_6 0x40 /* Ser. port 2 xcvr select (0=232, 1=422) */ | ||
| 138 | #define IOC4_GPCR_DIR_7 0x80 /* Ser. port 3 xcvr select (0=232, 1=422) */ | ||
| 139 | |||
| 140 | /* Masks for GPCR EDGE pins */ | ||
| 141 | #define IOC4_GPCR_EDGE_0 0x01 | ||
| 142 | #define IOC4_GPCR_EDGE_1 0x02 /* External interrupt input */ | ||
| 143 | #define IOC4_GPCR_EDGE_2 0x04 | ||
| 144 | #define IOC4_GPCR_EDGE_3 0x08 | ||
| 145 | #define IOC4_GPCR_EDGE_4 0x10 | ||
| 146 | #define IOC4_GPCR_EDGE_5 0x20 | ||
| 147 | #define IOC4_GPCR_EDGE_6 0x40 | ||
| 148 | #define IOC4_GPCR_EDGE_7 0x80 | ||
| 149 | |||
| 150 | #define IOC4_VARIANT_IO9 0x0900 | ||
| 151 | #define IOC4_VARIANT_PCI_RT 0x0901 | ||
| 152 | #define IOC4_VARIANT_IO10 0x1000 | ||
| 153 | |||
| 154 | /* One of these per IOC4 */ | ||
| 155 | struct ioc4_driver_data { | ||
| 156 | struct list_head idd_list; | ||
| 157 | unsigned long idd_bar0; | ||
| 158 | struct pci_dev *idd_pdev; | ||
| 159 | const struct pci_device_id *idd_pci_id; | ||
| 160 | struct ioc4_misc_regs __iomem *idd_misc_regs; | ||
| 161 | unsigned long count_period; | ||
| 162 | void *idd_serial_data; | ||
| 163 | unsigned int idd_variant; | ||
| 164 | }; | ||
| 165 | |||
| 166 | /* One per submodule */ | ||
| 167 | struct ioc4_submodule { | ||
| 168 | struct list_head is_list; | ||
| 169 | char *is_name; | ||
| 170 | struct module *is_owner; | ||
| 171 | int (*is_probe) (struct ioc4_driver_data *); | ||
| 172 | int (*is_remove) (struct ioc4_driver_data *); | ||
| 173 | }; | ||
| 174 | |||
| 175 | #define IOC4_NUM_CARDS 8 /* max cards per partition */ | ||
| 176 | |||
| 177 | /********************************** | ||
| 178 | * Functions needed by submodules * | ||
| 179 | **********************************/ | ||
| 180 | |||
| 181 | extern int ioc4_register_submodule(struct ioc4_submodule *); | ||
| 182 | extern void ioc4_unregister_submodule(struct ioc4_submodule *); | ||
| 183 | |||
| 184 | #endif /* _LINUX_IOC4_H */ | ||
| @@ -1070,7 +1070,6 @@ · 1069 unmodified lines | |||
| 1070 | #define PCI_VENDOR_ID_SGI 0x10a9 | 1070 | #define PCI_VENDOR_ID_SGI 0x10a9 |
| 1071 | #define PCI_DEVICE_ID_SGI_IOC3 0x0003 | 1071 | #define PCI_DEVICE_ID_SGI_IOC3 0x0003 |
| 1072 | #define PCI_DEVICE_ID_SGI_LITHIUM 0x1002 | 1072 | #define PCI_DEVICE_ID_SGI_LITHIUM 0x1002 |
| 1073 | #define PCI_DEVICE_ID_SGI_IOC4 0x100a | ||
| 1074 | 1073 | ||
| 1075 | #define PCI_VENDOR_ID_WINBOND 0x10ad | 1074 | #define PCI_VENDOR_ID_WINBOND 0x10ad |
| 1076 | #define PCI_DEVICE_ID_WINBOND_82C105 0x0105 | 1075 | #define PCI_DEVICE_ID_WINBOND_82C105 0x0105 |