It was always expected to have a use for this some day, so we left a placeholder. Now we do. (And I expect another use in the not too distant future when we start allowing userspace to allocate GPU iova.)
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| @@ -67,16 +67,20 @@ struct drm_msm_timespec { · 66 unmodified lines | ||
| 67 | 67 | __s64 tv_nsec; /* nanoseconds */ |
| 68 | 68 | }; |
| 69 | 69 | |
| 70 | −#define MSM_PARAM_GPU_ID 0x01 | |
| 71 | −#define MSM_PARAM_GMEM_SIZE 0x02 | |
| 72 | −#define MSM_PARAM_CHIP_ID 0x03 | |
| 73 | −#define MSM_PARAM_MAX_FREQ 0x04 | |
| 74 | −#define MSM_PARAM_TIMESTAMP 0x05 | |
| 75 | −#define MSM_PARAM_GMEM_BASE 0x06 | |
| 76 | −#define MSM_PARAM_PRIORITIES 0x07 /* The # of priority levels */ | |
| 77 | −#define MSM_PARAM_PP_PGTABLE 0x08 /* => 1 for per-process pagetables, else 0 */ | |
| 78 | −#define MSM_PARAM_FAULTS 0x09 | |
| 79 | −#define MSM_PARAM_SUSPENDS 0x0a | |
| 70 | +/* Below "RO" indicates a read-only param, "WO" indicates write-only, and | |
| 71 | + * "RW" indicates a param that can be both read (GET_PARAM) and written | |
| 72 | + * (SET_PARAM) | |
| 73 | + */ | |
| 74 | +#define MSM_PARAM_GPU_ID 0x01 /* RO */ | |
| 75 | +#define MSM_PARAM_GMEM_SIZE 0x02 /* RO */ | |
| 76 | +#define MSM_PARAM_CHIP_ID 0x03 /* RO */ | |
| 77 | +#define MSM_PARAM_MAX_FREQ 0x04 /* RO */ | |
| 78 | +#define MSM_PARAM_TIMESTAMP 0x05 /* RO */ | |
| 79 | +#define MSM_PARAM_GMEM_BASE 0x06 /* RO */ | |
| 80 | +#define MSM_PARAM_PRIORITIES 0x07 /* RO: The # of priority levels */ | |
| 81 | +#define MSM_PARAM_PP_PGTABLE 0x08 /* RO: Deprecated, always returns zero */ | |
| 82 | +#define MSM_PARAM_FAULTS 0x09 /* RO */ | |
| 83 | +#define MSM_PARAM_SUSPENDS 0x0a /* RO */ | |
| 80 | 84 | |
| 81 | 85 | /* For backwards compat. The original support for preemption was based on |
| 82 | 86 | * a single ring per priority level so # of priority levels equals the # |
| @@ -333,9 +337,7 @@ struct drm_msm_submitqueue_query { · 250 unmodified lines | ||
| 333 | 337 | }; |
| 334 | 338 | |
| 335 | 339 | #define DRM_MSM_GET_PARAM 0x00 |
| 336 | −/* placeholder: | |
| 337 | 340 | #define DRM_MSM_SET_PARAM 0x01 |
| 338 | − */ | |
| 339 | 341 | #define DRM_MSM_GEM_NEW 0x02 |
| 340 | 342 | #define DRM_MSM_GEM_INFO 0x03 |
| 341 | 343 | #define DRM_MSM_GEM_CPU_PREP 0x04 |
| @@ -351,6 +353,7 @@ struct drm_msm_submitqueue_query { · 9 unmodified lines | ||
| 351 | 353 | #define DRM_MSM_SUBMITQUEUE_QUERY 0x0C |
| 352 | 354 | |
| 353 | 355 | #define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param) |
| 356 | +#define DRM_IOCTL_MSM_SET_PARAM DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SET_PARAM, struct drm_msm_param) | |
| 354 | 357 | #define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new) |
| 355 | 358 | #define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info) |
| 356 | 359 | #define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep) |