drm/msm: Add per-instance submit queues

Currently the behavior of a command stream is provided by the user application during submission and the application is expected to internally maintain the settings for each 'context' or 'rendering queue' and specify the correct ones. This works okay for simple cases but as applications become more complex we will want to set context specific flags and do various permission checks to allow certain contexts to enable additional privileges. Add kernel-side submit queues to be analogous to 'contexts' or 'rendering queues' on the application side. Each file descriptor instance will maintain its own list of queues. Queues cannot be shared between file descriptors. For backwards compatibility context id '0' is defined as a default context specifying no priority and no special flags. This is intended to be the usual configuration for 99% of applications so that a garden variety application can function correctly without creating a queue. Only those applications requiring the specific benefit of different queues need create one.

Jordan Crouse committed 9 years ago

Commit f7de1541 parent 0033e1b8 files · +250 −16Browse files

Unified · Split

8 files

drivers/gpu/drm/msm/Makefile +2 −1
drivers/gpu/drm/msm/msm_drv.c +48 −8
drivers/gpu/drm/msm/msm_drv.h +15 −5
drivers/gpu/drm/msm/msm_gem.h +1 −0
drivers/gpu/drm/msm/msm_gem_submit.c +12 −2
drivers/gpu/drm/msm/msm_gpu.h +15 −0
drivers/gpu/drm/msm/msm_submitqueue.c +135 −0
include/uapi/drm/msm_drm.h +22 −0

drivers/gpu/drm/msm/Makefile+2−1

@@ -57,7 +57,8 @@ msm-y := \ · 56 unmodified lines
57	msm_iommu.o \	57	msm_iommu.o \
58	msm_perf.o \	58	msm_perf.o \
59	msm_rd.o \	59	msm_rd.o \
60	msm_ringbuffer.o	60	msm_ringbuffer.o \
		61	msm_submitqueue.o
61		62
62	msm-$(CONFIG_DRM_FBDEV_EMULATION) += msm_fbdev.o	63	msm-$(CONFIG_DRM_FBDEV_EMULATION) += msm_fbdev.o
63	msm-$(CONFIG_COMMON_CLK) += mdp/mdp4/mdp4_lvds_pll.o	64	msm-$(CONFIG_COMMON_CLK) += mdp/mdp4/mdp4_lvds_pll.o

drivers/gpu/drm/msm/msm_drv.c+48−8

  * - 1.0.0 - initial interface
  * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers
  * - 1.2.0 - adds explicit fence support for submit ioctl
+ * - 1.3.0 - adds GMEM_BASE + NR_RINGS params, SUBMITQUEUE_NEW +
+ *           SUBMITQUEUE_CLOSE ioctls, and MSM_INFO_IOVA flag for
+ *           MSM_GEM_INFO ioctl.
  */
 #define MSM_VERSION_MAJOR	1
-#define MSM_VERSION_MINOR	2
+#define MSM_VERSION_MINOR	3
 #define MSM_VERSION_PATCHLEVEL	0
 static void msm_fb_output_poll_changed(struct drm_device *dev)
 	mutex_unlock(&init_lock);
 }
-static int msm_open(struct drm_device *dev, struct drm_file *file)
+static int context_init(struct drm_file *file)
 {
 	struct msm_file_private *ctx;
-	/* For now, load gpu on open.. to avoid the requirement of having
-	 * firmware in the initrd.
-	 */
-	load_gpu(dev);
 	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
 	if (!ctx)
 		return -ENOMEM;
+	msm_submitqueue_init(ctx);
 	file->driver_priv = ctx;
 	return 0;
 }
+static int msm_open(struct drm_device *dev, struct drm_file *file)
+{
+	/* For now, load gpu on open.. to avoid the requirement of having
+	 * firmware in the initrd.
+	 */
+	load_gpu(dev);
+	return context_init(file);
+}
+static void context_close(struct msm_file_private *ctx)
+{
+	msm_submitqueue_close(ctx);
+	kfree(ctx);
+}
 static void msm_postclose(struct drm_device *dev, struct drm_file *file)
 {
 	struct msm_drm_private *priv = dev->dev_private;
 		priv->lastctx = NULL;
 	mutex_unlock(&dev->struct_mutex);
-	kfree(ctx);
+	context_close(ctx);
 }
 static void msm_lastclose(struct drm_device *dev)
 	return ret;
 }
+static int msm_ioctl_submitqueue_new(struct drm_device *dev, void *data,
+		struct drm_file *file)
+{
+	struct drm_msm_submitqueue *args = data;
+	if (args->flags & ~MSM_SUBMITQUEUE_FLAGS)
+		return -EINVAL;
+	return msm_submitqueue_create(file->driver_priv, args->prio,
+		args->flags, &args->id);
+}
+static int msm_ioctl_submitqueue_close(struct drm_device *dev, void *data,
+		struct drm_file *file)
+{
+	u32 id = *(u32 *) data;
+	return msm_submitqueue_remove(file->driver_priv, id);
+}
 static const struct drm_ioctl_desc msm_ioctls[] = {
 	DRM_IOCTL_DEF_DRV(MSM_GET_PARAM,    msm_ioctl_get_param,    DRM_AUTH|DRM_RENDER_ALLOW),
 	DRM_IOCTL_DEF_DRV(MSM_GEM_NEW,      msm_ioctl_gem_new,      DRM_AUTH|DRM_RENDER_ALLOW),
 	DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT,   msm_ioctl_gem_submit,   DRM_AUTH|DRM_RENDER_ALLOW),
 	DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE,   msm_ioctl_wait_fence,   DRM_AUTH|DRM_RENDER_ALLOW),
 	DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE,  msm_ioctl_gem_madvise,  DRM_AUTH|DRM_RENDER_ALLOW),
+	DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW,   msm_ioctl_submitqueue_new,   DRM_AUTH|DRM_RENDER_ALLOW),
+	DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close, DRM_AUTH|DRM_RENDER_ALLOW),
 };
 static const struct vm_operations_struct vm_ops = {

drivers/gpu/drm/msm/msm_drv.h+15−5

 struct msm_gem_vma;
 struct msm_file_private {
-	/* currently we don't do anything useful with this.. but when
+	rwlock_t queuelock;
-	 * per-context address spaces are supported we'd keep track of
+	struct list_head submitqueues;
-	 * the context's page-tables here.
+	int queueid;
-	 */
-	int dummy;
 };
 enum msm_mdp_plane_property {
 void msm_writel(u32 data, void __iomem *addr);
 u32 msm_readl(const void __iomem *addr);
+struct msm_gpu_submitqueue;
+int msm_submitqueue_init(struct msm_file_private *ctx);
+struct msm_gpu_submitqueue *msm_submitqueue_get(struct msm_file_private *ctx,
+		u32 id);
+int msm_submitqueue_create(struct msm_file_private *ctx, u32 prio,
+		u32 flags, u32 *id);
+int msm_submitqueue_remove(struct msm_file_private *ctx, u32 id);
+void msm_submitqueue_close(struct msm_file_private *ctx);
+void msm_submitqueue_destroy(struct kref *kref);
 #define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
 #define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)

drivers/gpu/drm/msm/msm_gem.h+1−0

@@ -142,6 +142,7 @@ struct msm_gem_submit { · 141 unmodified lines
142	struct list_head bo_list;	142	struct list_head bo_list;
143	struct ww_acquire_ctx ticket;	143	struct ww_acquire_ctx ticket;
144	struct dma_fence *fence;	144	struct dma_fence *fence;
		145	struct msm_gpu_submitqueue *queue;
145	struct pid pid; / submitting process */	146	struct pid pid; / submitting process */
146	bool valid; /* true if no cmdstream patching needed */	147	bool valid; /* true if no cmdstream patching needed */
147	unsigned int nr_cmds;	148	unsigned int nr_cmds;

drivers/gpu/drm/msm/msm_gem_submit.c+12−2

 #define BO_PINNED   0x2000
 static struct msm_gem_submit *submit_create(struct drm_device *dev,
-		struct msm_gpu *gpu, uint32_t nr_bos, uint32_t nr_cmds)
+		struct msm_gpu *gpu, struct msm_gpu_submitqueue *queue,
+		uint32_t nr_bos, uint32_t nr_cmds)
 {
 	struct msm_gem_submit *submit;
 	uint64_t sz = sizeof(*submit) + ((u64)nr_bos * sizeof(submit->bos[0])) +
 	submit->fence = NULL;
 	submit->pid = get_pid(task_pid(current));
 	submit->cmd = (void *)&submit->bos[nr_bos];
+	submit->queue = queue;
 	/* initially, until copy_from_user() and bo lookup succeeds: */
 	submit->nr_bos = 0;
 	dma_fence_put(submit->fence);
 	list_del(&submit->node);
 	put_pid(submit->pid);
+	msm_submitqueue_put(submit->queue);
 	kfree(submit);
 }
 	struct msm_gpu *gpu = priv->gpu;
 	struct dma_fence *in_fence = NULL;
 	struct sync_file *sync_file = NULL;
+	struct msm_gpu_submitqueue *queue;
 	int out_fence_fd = -1;
 	unsigned i;
 	int ret;
 	if (MSM_PIPE_FLAGS(args->flags) & ~MSM_SUBMIT_FLAGS)
 		return -EINVAL;
+	queue = msm_submitqueue_get(ctx, args->queueid);
+	if (!queue)
+		return -ENOENT;
 	if (args->flags & MSM_SUBMIT_FENCE_FD_IN) {
 		in_fence = sync_file_get_fence(args->fence_fd);
 	}
 	priv->struct_mutex_task = current;
-	submit = submit_create(dev, gpu, args->nr_bos, args->nr_cmds);
+	submit = submit_create(dev, gpu, queue, args->nr_bos, args->nr_cmds);
 	if (!submit) {
 		ret = -ENOMEM;
 		goto out_unlock;
 	submit->nr_cmds = i;
 	submit->fence = msm_fence_alloc(gpu->fctx);
 	if (IS_ERR(submit->fence)) {
 		ret = PTR_ERR(submit->fence);
 		submit->fence = NULL;

drivers/gpu/drm/msm/msm_gpu.h+15−0

@@ -150,6 +150,15 @@ struct msm_gpu_perfcntr { · 149 unmodified lines
150	const char *name;	150	const char *name;
151	};	151	};
152		152
		153	struct msm_gpu_submitqueue {
		154	int id;
		155	u32 flags;
		156	u32 prio;
		157	int faults;
		158	struct list_head node;
		159	struct kref ref;
		160	};
		161
153	static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data)	162	static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data)
154	{	163	{
155	msm_writel(data, gpu->mmio + (reg << 2));	164	msm_writel(data, gpu->mmio + (reg << 2));
@@ -223,4 +232,10 @@ struct msm_gpu adreno_load_gpu(struct drm_device dev); · 67 unmodified lines
223	void __init adreno_register(void);	232	void __init adreno_register(void);
224	void __exit adreno_unregister(void);	233	void __exit adreno_unregister(void);
225		234
		235	static inline void msm_submitqueue_put(struct msm_gpu_submitqueue *queue)
		236	{
		237	if (queue)
		238	kref_put(&queue->ref, msm_submitqueue_destroy);
		239	}
		240
226	#endif /* __MSM_GPU_H__ */	241	#endif /* __MSM_GPU_H__ */

drivers/gpu/drm/msm/msm_submitqueue.c+135−0

@@ -0,0 +1,135 @@
	1	/* Copyright (c) 2017 The Linux Foundation. All rights reserved.
	2	*
	3	* This program is free software; you can redistribute it and/or modify
	4	* it under the terms of the GNU General Public License version 2 and
	5	* only version 2 as published by the Free Software Foundation.
	6	*
	7	* This program is distributed in the hope that it will be useful,
	8	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	9	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	10	* GNU General Public License for more details.
	11	*
	12	*/
	13
	14	#include <linux/kref.h>
	15	#include "msm_gpu.h"
	16
	17	void msm_submitqueue_destroy(struct kref *kref)
	18	{
	19	struct msm_gpu_submitqueue *queue = container_of(kref,
	20	struct msm_gpu_submitqueue, ref);
	21
	22	kfree(queue);
	23	}
	24
	25	struct msm_gpu_submitqueue msm_submitqueue_get(struct msm_file_private ctx,
	26	u32 id)
	27	{
	28	struct msm_gpu_submitqueue *entry;
	29
	30	if (!ctx)
	31	return NULL;
	32
	33	read_lock(&ctx->queuelock);
	34
	35	list_for_each_entry(entry, &ctx->submitqueues, node) {
	36	if (entry->id == id) {
	37	kref_get(&entry->ref);
	38	read_unlock(&ctx->queuelock);
	39
	40	return entry;
	41	}
	42	}
	43
	44	read_unlock(&ctx->queuelock);
	45	return NULL;
	46	}
	47
	48	void msm_submitqueue_close(struct msm_file_private *ctx)
	49	{
	50	struct msm_gpu_submitqueue entry, tmp;
	51
	52	if (!ctx)
	53	return;
	54
	55	/*
	56	* No lock needed in close and there won't
	57	* be any more user ioctls coming our way
	58	*/
	59	list_for_each_entry_safe(entry, tmp, &ctx->submitqueues, node)
	60	msm_submitqueue_put(entry);
	61	}
	62
	63	int msm_submitqueue_create(struct msm_file_private *ctx, u32 prio, u32 flags,
	64	u32 *id)
	65	{
	66	struct msm_gpu_submitqueue *queue;
	67
	68	if (!ctx)
	69	return -ENODEV;
	70
	71	queue = kzalloc(sizeof(*queue), GFP_KERNEL);
	72
	73	if (!queue)
	74	return -ENOMEM;
	75
	76	kref_init(&queue->ref);
	77	queue->flags = flags;
	78	queue->prio = prio;
	79
	80	write_lock(&ctx->queuelock);
	81
	82	queue->id = ctx->queueid++;
	83
	84	if (id)
	85	*id = queue->id;
	86
	87	list_add_tail(&queue->node, &ctx->submitqueues);
	88
	89	write_unlock(&ctx->queuelock);
	90
	91	return 0;
	92	}
	93
	94	int msm_submitqueue_init(struct msm_file_private *ctx)
	95	{
	96	if (!ctx)
	97	return 0;
	98
	99	INIT_LIST_HEAD(&ctx->submitqueues);
	100
	101	rwlock_init(&ctx->queuelock);
	102
	103	return msm_submitqueue_create(ctx, 2, 0, NULL);
	104	}
	105
	106	int msm_submitqueue_remove(struct msm_file_private *ctx, u32 id)
	107	{
	108	struct msm_gpu_submitqueue *entry;
	109
	110	if (!ctx)
	111	return 0;
	112
	113	/*
	114	* id 0 is the "default" queue and can't be destroyed
	115	* by the user
	116	*/
	117	if (!id)
	118	return -ENOENT;
	119
	120	write_lock(&ctx->queuelock);
	121
	122	list_for_each_entry(entry, &ctx->submitqueues, node) {
	123	if (entry->id == id) {
	124	list_del(&entry->node);
	125	write_unlock(&ctx->queuelock);
	126
	127	msm_submitqueue_put(entry);
	128	return 0;
	129	}
	130	}
	131
	132	write_unlock(&ctx->queuelock);
	133	return -ENOENT;
	134	}
	135

include/uapi/drm/msm_drm.h+22−0

 	__u64 bos;            /* in, ptr to array of submit_bo's */
 	__u64 cmds;           /* in, ptr to array of submit_cmd's */
 	__s32 fence_fd;       /* in/out fence fd (see MSM_SUBMIT_FENCE_FD_IN/OUT) */
+	__u32 queueid;         /* in, submitqueue id */
 };
 /* The normal way to synchronize with the GPU is just to CPU_PREP on
 	__u32 retained;       /* out, whether backing store still exists */
 };
+/*
+ * Draw queues allow the user to set specific submission parameter. Command
+ * submissions specify a specific submitqueue to use.  ID 0 is reserved for
+ * backwards compatibility as a "default" submitqueue
+ */
+#define MSM_SUBMITQUEUE_FLAGS (0)
+struct drm_msm_submitqueue {
+	__u32 flags;   /* in, MSM_SUBMITQUEUE_x */
+	__u32 prio;    /* in, Priority level */
+	__u32 id;      /* out, identifier */
+};
 #define DRM_MSM_GET_PARAM              0x00
 /* placeholder:
 #define DRM_MSM_SET_PARAM              0x01
 #define DRM_MSM_GEM_SUBMIT             0x06
 #define DRM_MSM_WAIT_FENCE             0x07
 #define DRM_MSM_GEM_MADVISE            0x08
+/* placeholder:
+#define DRM_MSM_GEM_SVM_NEW            0x09
+ */
+#define DRM_MSM_SUBMITQUEUE_NEW        0x0A
+#define DRM_MSM_SUBMITQUEUE_CLOSE      0x0B
 #define DRM_IOCTL_MSM_GET_PARAM        DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param)
 #define DRM_IOCTL_MSM_GEM_NEW          DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new)
 #define DRM_IOCTL_MSM_GEM_SUBMIT       DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit)
 #define DRM_IOCTL_MSM_WAIT_FENCE       DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence)
 #define DRM_IOCTL_MSM_GEM_MADVISE      DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise)
+#define DRM_IOCTL_MSM_SUBMITQUEUE_NEW    DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_NEW, struct drm_msm_submitqueue)
+#define DRM_IOCTL_MSM_SUBMITQUEUE_CLOSE  DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_CLOSE, __u32)
 #if defined(__cplusplus)
 }

drm/msm: Add per-instance submit queues

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