History

clk: qcom: smd: Add missing RPM clocks for msm8992/4

XO and MSS_CFG were omitted when first adding the clocks for these SoCs. Add them, and while at it, move the XO clock to the top of the definition list, as ideally everyone should start using it sooner or later..

Konrad Dybcio committed 4 years ago

Commit f8043601 parent 5b2fa282 files · +12 −2Browse files

Unified · Split

2 files
  1. drivers/clk/qcom/clk-smd-rpm.c +11 −2
  2. include/linux/soc/qcom/smd-rpm.h +1 −0
drivers/clk/qcom/clk-smd-rpm.c+11−2
@@ -413,6 +413,7 @@ static const struct clk_ops clk_smd_rpm_branch_ops = { · 412 unmodified lines
413 .recalc_rate = clk_smd_rpm_recalc_rate,413 .recalc_rate = clk_smd_rpm_recalc_rate,
414};414};
415 415
416DEFINE_CLK_SMD_RPM_BRANCH(sdm660, bi_tcxo, bi_tcxo_a, QCOM_SMD_RPM_MISC_CLK, 0, 19200000);
416DEFINE_CLK_SMD_RPM(msm8916, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);417DEFINE_CLK_SMD_RPM(msm8916, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
417DEFINE_CLK_SMD_RPM(msm8916, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);418DEFINE_CLK_SMD_RPM(msm8916, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
418DEFINE_CLK_SMD_RPM(msm8916, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);419DEFINE_CLK_SMD_RPM(msm8916, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
@@ -604,7 +605,11 @@ DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, ln_bb_clk, ln_bb_a_clk, 8, 19200000); · 185 unmodified lines
604DEFINE_CLK_SMD_RPM(msm8992, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);605DEFINE_CLK_SMD_RPM(msm8992, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);
605DEFINE_CLK_SMD_RPM(msm8992, ce2_clk, ce2_a_clk, QCOM_SMD_RPM_CE_CLK, 1);606DEFINE_CLK_SMD_RPM(msm8992, ce2_clk, ce2_a_clk, QCOM_SMD_RPM_CE_CLK, 1);
606 607
608DEFINE_CLK_SMD_RPM_BRANCH(msm8992, mss_cfg_ahb_clk, mss_cfg_ahb_a_clk,
609 QCOM_SMD_RPM_MCFG_CLK, 0, 19200000);
607static struct clk_smd_rpm *msm8992_clks[] = {610static struct clk_smd_rpm *msm8992_clks[] = {
611 [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo,
612 [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a,
608 [RPM_SMD_PNOC_CLK] = &msm8916_pcnoc_clk,613 [RPM_SMD_PNOC_CLK] = &msm8916_pcnoc_clk,
609 [RPM_SMD_PNOC_A_CLK] = &msm8916_pcnoc_a_clk,614 [RPM_SMD_PNOC_A_CLK] = &msm8916_pcnoc_a_clk,
610 [RPM_SMD_OCMEMGX_CLK] = &msm8974_ocmemgx_clk,615 [RPM_SMD_OCMEMGX_CLK] = &msm8974_ocmemgx_clk,
@@ -637,6 +642,8 @@ static struct clk_smd_rpm *msm8992_clks[] = { · 26 unmodified lines
637 [RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk,642 [RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk,
638 [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_mmssnoc_ahb_clk,643 [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_mmssnoc_ahb_clk,
639 [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_mmssnoc_ahb_a_clk,644 [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_mmssnoc_ahb_a_clk,
645 [RPM_SMD_MSS_CFG_AHB_CLK] = &msm8992_mss_cfg_ahb_clk,
646 [RPM_SMD_MSS_CFG_AHB_A_CLK] = &msm8992_mss_cfg_ahb_a_clk,
640 [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,647 [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
641 [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,648 [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
642 [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,649 [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
@@ -661,6 +668,8 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8992 = { · 18 unmodified lines
661DEFINE_CLK_SMD_RPM(msm8994, ce3_clk, ce3_a_clk, QCOM_SMD_RPM_CE_CLK, 2);668DEFINE_CLK_SMD_RPM(msm8994, ce3_clk, ce3_a_clk, QCOM_SMD_RPM_CE_CLK, 2);
662 669
663static struct clk_smd_rpm *msm8994_clks[] = {670static struct clk_smd_rpm *msm8994_clks[] = {
671 [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo,
672 [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a,
664 [RPM_SMD_PNOC_CLK] = &msm8916_pcnoc_clk,673 [RPM_SMD_PNOC_CLK] = &msm8916_pcnoc_clk,
665 [RPM_SMD_PNOC_A_CLK] = &msm8916_pcnoc_a_clk,674 [RPM_SMD_PNOC_A_CLK] = &msm8916_pcnoc_a_clk,
666 [RPM_SMD_OCMEMGX_CLK] = &msm8974_ocmemgx_clk,675 [RPM_SMD_OCMEMGX_CLK] = &msm8974_ocmemgx_clk,
@@ -693,6 +702,8 @@ static struct clk_smd_rpm *msm8994_clks[] = { · 26 unmodified lines
693 [RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk,702 [RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk,
694 [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_mmssnoc_ahb_clk,703 [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_mmssnoc_ahb_clk,
695 [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_mmssnoc_ahb_a_clk,704 [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_mmssnoc_ahb_a_clk,
705 [RPM_SMD_MSS_CFG_AHB_CLK] = &msm8992_mss_cfg_ahb_clk,
706 [RPM_SMD_MSS_CFG_AHB_A_CLK] = &msm8992_mss_cfg_ahb_a_clk,
696 [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,707 [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
697 [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,708 [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
698 [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,709 [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
@@ -857,8 +868,6 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8998 = { · 158 unmodified lines
857 .num_clks = ARRAY_SIZE(msm8998_clks),868 .num_clks = ARRAY_SIZE(msm8998_clks),
858};869};
859 870
860DEFINE_CLK_SMD_RPM_BRANCH(sdm660, bi_tcxo, bi_tcxo_a, QCOM_SMD_RPM_MISC_CLK, 0,
861 19200000);
862DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk3, ln_bb_clk3_a, 3, 19200000);871DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk3, ln_bb_clk3_a, 3, 19200000);
863DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk3_pin, ln_bb_clk3_pin_a, 3, 19200000);872DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk3_pin, ln_bb_clk3_pin_a, 3, 19200000);
864 873
include/linux/soc/qcom/smd-rpm.h+1−0
@@ -40,6 +40,7 @@ struct qcom_smd_rpm; · 39 unmodified lines
40#define QCOM_SMD_RPM_AGGR_CLK 0x7267676140#define QCOM_SMD_RPM_AGGR_CLK 0x72676761
41#define QCOM_SMD_RPM_HWKM_CLK 0x6d6b776841#define QCOM_SMD_RPM_HWKM_CLK 0x6d6b7768
42#define QCOM_SMD_RPM_PKA_CLK 0x616b7042#define QCOM_SMD_RPM_PKA_CLK 0x616b70
43#define QCOM_SMD_RPM_MCFG_CLK 0x6766636d
43 44
44int qcom_rpm_smd_write(struct qcom_smd_rpm *rpm,45int qcom_rpm_smd_write(struct qcom_smd_rpm *rpm,
45 int state,46 int state,

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