Merge branch kvm-arm64/vgic-v5-ppi into kvmarm-master/next

* kvm-arm64/vgic-v5-ppi: (40 commits) : . : Add initial GICv5 support for KVM guests, only adding PPI support : for the time being. Patches courtesy of Sascha Bischoff. : : From the cover letter: : : "This is v7 of the patch series to add the virtual GICv5 [1] device : (vgic_v5). Only PPIs are supported by this initial series, and the : vgic_v5 implementation is restricted to the CPU interface, : only. Further patch series are to follow in due course, and will add : support for SPIs, LPIs, the GICv5 IRS, and the GICv5 ITS." : . KVM: arm64: selftests: Add no-vgic-v5 selftest KVM: arm64: selftests: Introduce a minimal GICv5 PPI selftest KVM: arm64: gic-v5: Communicate userspace-driveable PPIs via a UAPI Documentation: KVM: Introduce documentation for VGICv5 KVM: arm64: gic-v5: Probe for GICv5 device KVM: arm64: gic-v5: Set ICH_VCTLR_EL2.En on boot KVM: arm64: gic-v5: Introduce kvm_arm_vgic_v5_ops and register them KVM: arm64: gic-v5: Hide FEAT_GCIE from NV GICv5 guests KVM: arm64: gic: Hide GICv5 for protected guests KVM: arm64: gic-v5: Mandate architected PPI for PMU emulation on GICv5 KVM: arm64: gic-v5: Enlighten arch timer for GICv5 irqchip/gic-v5: Introduce minimal irq_set_type() for PPIs KVM: arm64: gic-v5: Initialise ID and priority bits when resetting vcpu KVM: arm64: gic-v5: Create and initialise vgic_v5 KVM: arm64: gic-v5: Support GICv5 interrupts with KVM_IRQ_LINE KVM: arm64: gic-v5: Implement direct injection of PPIs KVM: arm64: Introduce set_direct_injection irq_op KVM: arm64: gic-v5: Trap and mask guest ICC_PPI_ENABLERx_EL1 writes KVM: arm64: gic-v5: Check for pending PPIs KVM: arm64: gic-v5: Clear TWI if single task running ...

Marc Zyngier committed 7 months ago

Commit f8078d52 parents 2de32a2 ce2926147 files · +3204 −382Browse files

Unified · Split

47 files

Documentation/virt/kvm/api.rst +4 −2
Documentation/virt/kvm/devices/arm-vgic-v5.rst +50 −0
Documentation/virt/kvm/devices/index.rst +1 −0
Documentation/virt/kvm/devices/vcpu.rst +3 −2
arch/arm64/include/asm/el2_setup.h +2 −0
arch/arm64/include/asm/kvm_asm.h +2 −0
arch/arm64/include/asm/kvm_host.h +34 −0
arch/arm64/include/asm/kvm_hyp.h +10 −0
arch/arm64/include/asm/sysreg.h +7 −0
arch/arm64/include/asm/vncr_mapping.h +3 −0
arch/arm64/include/uapi/asm/kvm.h +1 −0
arch/arm64/kvm/arch_timer.c +80 −28
arch/arm64/kvm/arm.c +40 −4
arch/arm64/kvm/config.c +116 −7
arch/arm64/kvm/emulate-nested.c +68 −0
arch/arm64/kvm/hyp/include/hyp/switch.h +27 −0
arch/arm64/kvm/hyp/nvhe/Makefile +1 −1
arch/arm64/kvm/hyp/nvhe/hyp-main.c +16 −0
arch/arm64/kvm/hyp/nvhe/switch.c +15 −0
arch/arm64/kvm/hyp/nvhe/sys_regs.c +8 −0
arch/arm64/kvm/hyp/vgic-v5-sr.c +166 −0
arch/arm64/kvm/hyp/vhe/Makefile +1 −1
arch/arm64/kvm/nested.c +5 −0
arch/arm64/kvm/pmu-emul.c +15 −5
arch/arm64/kvm/sys_regs.c +158 −18
arch/arm64/kvm/vgic/vgic-init.c +150 −64
arch/arm64/kvm/vgic/vgic-kvm-device.c +106 −1
arch/arm64/kvm/vgic/vgic-mmio.c +34 −6
arch/arm64/kvm/vgic/vgic-v3.c +1 −1
arch/arm64/kvm/vgic/vgic-v5.c +494 −9
arch/arm64/kvm/vgic/vgic.c +139 −34
arch/arm64/kvm/vgic/vgic.h +40 −13
arch/arm64/tools/sysreg +480 −0
drivers/irqchip/irq-gic-v5.c +18 −0
include/kvm/arm_arch_timer.h +10 −1
include/kvm/arm_pmu.h +4 −1
include/kvm/arm_vgic.h +185 −6
include/linux/irqchip/arm-gic-v5.h +27 −0
include/linux/kvm_host.h +1 −0
include/uapi/linux/kvm.h +2 −0
tools/arch/arm64/include/uapi/asm/kvm.h +1 −0
tools/include/uapi/linux/kvm.h +2 −0
tools/testing/selftests/kvm/Makefile.kvm +2 −1
tools/testing/selftests/kvm/arm64/no-vgic-v3.c +0 −177
tools/testing/selftests/kvm/arm64/no-vgic.c +297 −0
tools/testing/selftests/kvm/arm64/vgic_v5.c +228 −0
tools/testing/selftests/kvm/include/arm64/gic_v5.h +150 −0

Documentation/virt/kvm/api.rst+4−2

@@ -907,10 +907,12 @@ The irq_type field has the following values: · 906 unmodified lines
907	907	- KVM_ARM_IRQ_TYPE_CPU:
908	908	out-of-kernel GIC: irq_id 0 is IRQ, irq_id 1 is FIQ
909	909	- KVM_ARM_IRQ_TYPE_SPI:
910		− in-kernel GIC: SPI, irq_id between 32 and 1019 (incl.)
	910	+ in-kernel GICv2/GICv3: SPI, irq_id between 32 and 1019 (incl.)
911	911	(the vcpu_index field is ignored)
	912	+ in-kernel GICv5: SPI, irq_id between 0 and 65535 (incl.)
912	913	- KVM_ARM_IRQ_TYPE_PPI:
913		− in-kernel GIC: PPI, irq_id between 16 and 31 (incl.)
	914	+ in-kernel GICv2/GICv3: PPI, irq_id between 16 and 31 (incl.)
	915	+ in-kernel GICv5: PPI, irq_id between 0 and 127 (incl.)
914	916
915	917	(The irq_id field thus corresponds nicely to the IRQ ID in the ARM GIC specs)
916	918

Documentation/virt/kvm/devices/arm-vgic-v5.rst+50−0

@@ -0,0 +1,50 @@
	1	+.. SPDX-License-Identifier: GPL-2.0
	2	+
	3	+====================================================
	4	+ARM Virtual Generic Interrupt Controller v5 (VGICv5)
	5	+====================================================
	6	+
	7	+
	8	+Device types supported:
	9	+ - KVM_DEV_TYPE_ARM_VGIC_V5 ARM Generic Interrupt Controller v5.0
	10	+
	11	+Only one VGIC instance may be instantiated through this API. The created VGIC
	12	+will act as the VM interrupt controller, requiring emulated user-space devices
	13	+to inject interrupts to the VGIC instead of directly to CPUs.
	14	+
	15	+Creating a guest GICv5 device requires a host GICv5 host. The current VGICv5
	16	+device only supports PPI interrupts. These can either be injected from emulated
	17	+in-kernel devices (such as the Arch Timer, or PMU), or via the KVM_IRQ_LINE
	18	+ioctl.
	19	+
	20	+Groups:
	21	+ KVM_DEV_ARM_VGIC_GRP_CTRL
	22	+ Attributes:
	23	+
	24	+ KVM_DEV_ARM_VGIC_CTRL_INIT
	25	+ request the initialization of the VGIC, no additional parameter in
	26	+ kvm_device_attr.addr. Must be called after all VCPUs have been created.
	27	+
	28	+ KVM_DEV_ARM_VGIC_USERPSPACE_PPIs
	29	+ request the mask of userspace-drivable PPIs. Only a subset of the PPIs can
	30	+ be directly driven from userspace with GICv5, and the returned mask
	31	+ informs userspace of which it is allowed to drive via KVM_IRQ_LINE.
	32	+
	33	+ Userspace must allocate and point to __u64[2] of data in
	34	+ kvm_device_attr.addr. When this call returns, the provided memory will be
	35	+ populated with the userspace PPI mask. The lower __u64 contains the mask
	36	+ for the lower 64 PPIS, with the remaining 64 being in the second __u64.
	37	+
	38	+ This is a read-only attribute, and cannot be set. Attempts to set it are
	39	+ rejected.
	40	+
	41	+ Errors:
	42	+
	43	+ ======= ========================================================
	44	+ -ENXIO VGIC not properly configured as required prior to calling
	45	+ this attribute
	46	+ -ENODEV no online VCPU
	47	+ -ENOMEM memory shortage when allocating vgic internal data
	48	+ -EFAULT Invalid guest ram access
	49	+ -EBUSY One or more VCPUS are running
	50	+ ======= ========================================================

Documentation/virt/kvm/devices/index.rst+1−0

@@ -10,6 +10,7 @@ Devices · 9 unmodified lines
10	10	arm-vgic-its
11	11	arm-vgic
12	12	arm-vgic-v3
	13	+ arm-vgic-v5
13	14	mpic
14	15	s390_flic
15	16	vcpu

Documentation/virt/kvm/devices/vcpu.rst+3−2

@@ -37,7 +37,8 @@ Returns: · 36 unmodified lines
37	37	A value describing the PMUv3 (Performance Monitor Unit v3) overflow interrupt
38	38	number for this vcpu. This interrupt could be a PPI or SPI, but the interrupt
39	39	type must be same for each vcpu. As a PPI, the interrupt number is the same for
40		−all vcpus, while as an SPI it must be a separate number per vcpu.
	40	+all vcpus, while as an SPI it must be a separate number per vcpu. For
	41	+GICv5-based guests, the architected PPI (23) must be used.
41	42
42	43	1.2 ATTRIBUTE: KVM_ARM_VCPU_PMU_V3_INIT
43	44	---------------------------------------
@@ -50,7 +51,7 @@ Returns: · 6 unmodified lines
50	51	-EEXIST Interrupt number already used
51	52	-ENODEV PMUv3 not supported or GIC not initialized
52	53	-ENXIO PMUv3 not supported, missing VCPU feature or interrupt
53		− number not set
	54	+ number not set (non-GICv5 guests, only)
54	55	-EBUSY PMUv3 already initialized
55	56	======= ======================================================
56	57

arch/arm64/include/asm/el2_setup.h+2−0

@@ -248,6 +248,8 @@ · 247 unmodified lines
248	248	ICH_HFGWTR_EL2_ICC_CR0_EL1 \| \
249	249	ICH_HFGWTR_EL2_ICC_APR_EL1)
250	250	msr_s SYS_ICH_HFGWTR_EL2, x0 // Disable reg write traps
	251	+ mov x0, #(ICH_VCTLR_EL2_En)
	252	+ msr_s SYS_ICH_VCTLR_EL2, x0 // Enable vHPPI selection
251	253	.Lskip_gicv5_\@:
252	254	.endm
253	255

arch/arm64/include/asm/kvm_asm.h+2−0

@@ -81,6 +81,8 @@ enum __kvm_host_smccc_func { · 80 unmodified lines
81	81	__KVM_HOST_SMCCC_FUNC___kvm_timer_set_cntvoff,
82	82	__KVM_HOST_SMCCC_FUNC___vgic_v3_save_aprs,
83	83	__KVM_HOST_SMCCC_FUNC___vgic_v3_restore_vmcr_aprs,
	84	+ __KVM_HOST_SMCCC_FUNC___vgic_v5_save_apr,
	85	+ __KVM_HOST_SMCCC_FUNC___vgic_v5_restore_vmcr_apr,
84	86	__KVM_HOST_SMCCC_FUNC___pkvm_reserve_vm,
85	87	__KVM_HOST_SMCCC_FUNC___pkvm_unreserve_vm,
86	88	__KVM_HOST_SMCCC_FUNC___pkvm_init_vm,

arch/arm64/include/asm/kvm_host.h+34−0

@@ -287,6 +287,9 @@ enum fgt_group_id { · 286 unmodified lines
287	287	HDFGRTR2_GROUP,
288	288	HDFGWTR2_GROUP = HDFGRTR2_GROUP,
289	289	HFGITR2_GROUP,
	290	+ ICH_HFGRTR_GROUP,
	291	+ ICH_HFGWTR_GROUP = ICH_HFGRTR_GROUP,
	292	+ ICH_HFGITR_GROUP,
290	293
291	294	/* Must be last */
292	295	__NR_FGT_GROUP_IDS__
@@ -620,6 +623,10 @@ enum vcpu_sysreg { · 327 unmodified lines
620	623	VNCR(ICH_HCR_EL2),
621	624	VNCR(ICH_VMCR_EL2),
622	625
	626	+ VNCR(ICH_HFGRTR_EL2),
	627	+ VNCR(ICH_HFGWTR_EL2),
	628	+ VNCR(ICH_HFGITR_EL2),
	629	+
623	630	NR_SYS_REGS /* Nothing after this line! */
624	631	};
625	632
@@ -675,6 +682,9 @@ extern struct fgt_masks hfgwtr2_masks; · 49 unmodified lines
675	682	extern struct fgt_masks hfgitr2_masks;
676	683	extern struct fgt_masks hdfgrtr2_masks;
677	684	extern struct fgt_masks hdfgwtr2_masks;
	685	+extern struct fgt_masks ich_hfgrtr_masks;
	686	+extern struct fgt_masks ich_hfgwtr_masks;
	687	+extern struct fgt_masks ich_hfgitr_masks;
678	688
679	689	extern struct fgt_masks kvm_nvhe_sym(hfgrtr_masks);
680	690	extern struct fgt_masks kvm_nvhe_sym(hfgwtr_masks);
@@ -687,6 +697,9 @@ extern struct fgt_masks kvm_nvhe_sym(hfgwtr2_masks); · 6 unmodified lines
687	697	extern struct fgt_masks kvm_nvhe_sym(hfgitr2_masks);
688	698	extern struct fgt_masks kvm_nvhe_sym(hdfgrtr2_masks);
689	699	extern struct fgt_masks kvm_nvhe_sym(hdfgwtr2_masks);
	700	+extern struct fgt_masks kvm_nvhe_sym(ich_hfgrtr_masks);
	701	+extern struct fgt_masks kvm_nvhe_sym(ich_hfgwtr_masks);
	702	+extern struct fgt_masks kvm_nvhe_sym(ich_hfgitr_masks);
690	703
691	704	struct kvm_cpu_context {
692	705	struct user_pt_regs regs; /* sp = sp_el0 */
@@ -787,6 +800,21 @@ struct kvm_host_data { · 94 unmodified lines
787	800
788	801	/* Last vgic_irq part of the AP list recorded in an LR */
789	802	struct vgic_irq *last_lr_irq;
	803	+
	804	+ /* PPI state tracking for GICv5-based guests */
	805	+ struct {
	806	+ /*
	807	+ * For tracking the PPI pending state, we need both the entry
	808	+ * state and exit state to correctly detect edges as it is
	809	+ * possible that an interrupt has been injected in software in
	810	+ * the interim.
	811	+ */
	812	+ DECLARE_BITMAP(pendr_entry, VGIC_V5_NR_PRIVATE_IRQS);
	813	+ DECLARE_BITMAP(pendr_exit, VGIC_V5_NR_PRIVATE_IRQS);
	814	+
	815	+ /* The saved state of the regs when leaving the guest */
	816	+ DECLARE_BITMAP(activer_exit, VGIC_V5_NR_PRIVATE_IRQS);
	817	+ } vgic_v5_ppi_state;
790	818	};
791	819
792	820	struct kvm_host_psci_config {
@@ -1662,6 +1690,11 @@ static __always_inline enum fgt_group_id __fgt_reg_to_group_id(enum vcpu_sysreg · 869 unmodified lines
1662	1690	case HDFGRTR2_EL2:
1663	1691	case HDFGWTR2_EL2:
1664	1692	return HDFGRTR2_GROUP;
	1693	+ case ICH_HFGRTR_EL2:
	1694	+ case ICH_HFGWTR_EL2:
	1695	+ return ICH_HFGRTR_GROUP;
	1696	+ case ICH_HFGITR_EL2:
	1697	+ return ICH_HFGITR_GROUP;
1665	1698	default:
1666	1699	BUILD_BUG_ON(1);
1667	1700	}
@@ -1676,6 +1709,7 @@ static __always_inline enum fgt_group_id __fgt_reg_to_group_id(enum vcpu_sysreg · 8 unmodified lines
1676	1709	case HDFGWTR_EL2: \
1677	1710	case HFGWTR2_EL2: \
1678	1711	case HDFGWTR2_EL2: \
	1712	+ case ICH_HFGWTR_EL2: \
1679	1713	p = &(vcpu)->arch.fgt[id].w; \
1680	1714	break; \
1681	1715	default: \

arch/arm64/include/asm/kvm_hyp.h+10−0

@@ -87,6 +87,15 @@ void __vgic_v3_save_aprs(struct vgic_v3_cpu_if *cpu_if); · 86 unmodified lines
87	87	void __vgic_v3_restore_vmcr_aprs(struct vgic_v3_cpu_if *cpu_if);
88	88	int __vgic_v3_perform_cpuif_access(struct kvm_vcpu *vcpu);
89	89
	90	+/* GICv5 */
	91	+void __vgic_v5_save_apr(struct vgic_v5_cpu_if *cpu_if);
	92	+void __vgic_v5_restore_vmcr_apr(struct vgic_v5_cpu_if *cpu_if);
	93	+/* No hypercalls for the following */
	94	+void __vgic_v5_save_ppi_state(struct vgic_v5_cpu_if *cpu_if);
	95	+void __vgic_v5_restore_ppi_state(struct vgic_v5_cpu_if *cpu_if);
	96	+void __vgic_v5_save_state(struct vgic_v5_cpu_if *cpu_if);
	97	+void __vgic_v5_restore_state(struct vgic_v5_cpu_if *cpu_if);
	98	+
90	99	#ifdef __KVM_NVHE_HYPERVISOR__
91	100	void __timer_enable_traps(struct kvm_vcpu *vcpu);
92	101	void __timer_disable_traps(struct kvm_vcpu *vcpu);
@@ -135,6 +144,7 @@ void __noreturn __host_enter(struct kvm_cpu_context *host_ctxt); · 42 unmodified lines
135	144
136	145	extern u64 kvm_nvhe_sym(id_aa64pfr0_el1_sys_val);
137	146	extern u64 kvm_nvhe_sym(id_aa64pfr1_el1_sys_val);
	147	+extern u64 kvm_nvhe_sym(id_aa64pfr2_el1_sys_val);
138	148	extern u64 kvm_nvhe_sym(id_aa64isar0_el1_sys_val);
139	149	extern u64 kvm_nvhe_sym(id_aa64isar1_el1_sys_val);
140	150	extern u64 kvm_nvhe_sym(id_aa64isar2_el1_sys_val);

arch/arm64/include/asm/sysreg.h+7−0

@@ -1052,6 +1052,7 @@ · 1051 unmodified lines
1052	1052	#define GICV5_OP_GIC_CDPRI sys_insn(1, 0, 12, 1, 2)
1053	1053	#define GICV5_OP_GIC_CDRCFG sys_insn(1, 0, 12, 1, 5)
1054	1054	#define GICV5_OP_GICR_CDIA sys_insn(1, 0, 12, 3, 0)
	1055	+#define GICV5_OP_GICR_CDNMIA sys_insn(1, 0, 12, 3, 1)
1055	1056
1056	1057	/* Definitions for GIC CDAFF */
1057	1058	#define GICV5_GIC_CDAFF_IAFFID_MASK GENMASK_ULL(47, 32)
@@ -1098,6 +1099,12 @@ · 40 unmodified lines
1098	1099	#define GICV5_GIC_CDIA_TYPE_MASK GENMASK_ULL(31, 29)
1099	1100	#define GICV5_GIC_CDIA_ID_MASK GENMASK_ULL(23, 0)
1100	1101
	1102	+/* Definitions for GICR CDNMIA */
	1103	+#define GICV5_GICR_CDNMIA_VALID_MASK BIT_ULL(32)
	1104	+#define GICV5_GICR_CDNMIA_VALID(r) FIELD_GET(GICV5_GICR_CDNMIA_VALID_MASK, r)
	1105	+#define GICV5_GICR_CDNMIA_TYPE_MASK GENMASK_ULL(31, 29)
	1106	+#define GICV5_GICR_CDNMIA_ID_MASK GENMASK_ULL(23, 0)
	1107	+
1101	1108	#define gicr_insn(insn) read_sysreg_s(GICV5_OP_GICR_##insn)
1102	1109	#define gic_insn(v, insn) write_sysreg_s(v, GICV5_OP_GIC_##insn)
1103	1110

arch/arm64/include/asm/vncr_mapping.h+3−0

@@ -108,5 +108,8 @@ · 107 unmodified lines
108	108	#define VNCR_MPAMVPM5_EL2 0x968
109	109	#define VNCR_MPAMVPM6_EL2 0x970
110	110	#define VNCR_MPAMVPM7_EL2 0x978
	111	+#define VNCR_ICH_HFGITR_EL2 0xB10
	112	+#define VNCR_ICH_HFGRTR_EL2 0xB18
	113	+#define VNCR_ICH_HFGWTR_EL2 0xB20
111	114
112	115	#endif /* __ARM64_VNCR_MAPPING_H__ */

arch/arm64/include/uapi/asm/kvm.h+1−0

@@ -428,6 +428,7 @@ enum { · 427 unmodified lines
428	428	#define KVM_DEV_ARM_ITS_RESTORE_TABLES 2
429	429	#define KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES 3
430	430	#define KVM_DEV_ARM_ITS_CTRL_RESET 4
	431	+#define KVM_DEV_ARM_VGIC_USERSPACE_PPIS 5
431	432
432	433	/* Device Control API on vcpu fd */
433	434	#define KVM_ARM_VCPU_PMU_V3_CTRL 0

arch/arm64/kvm/arch_timer.c+80−28

@@ -56,6 +56,12 @@ static struct irq_ops arch_timer_irq_ops = { · 55 unmodified lines
56	56	.get_input_level = kvm_arch_timer_get_input_level,
57	57	};
58	58
	59	+static struct irq_ops arch_timer_irq_ops_vgic_v5 = {
	60	+ .get_input_level = kvm_arch_timer_get_input_level,
	61	+ .queue_irq_unlock = vgic_v5_ppi_queue_irq_unlock,
	62	+ .set_direct_injection = vgic_v5_set_ppi_dvi,
	63	+};
	64	+
59	65	static int nr_timers(struct kvm_vcpu *vcpu)
60	66	{
61	67	if (!vcpu_has_nv(vcpu))
@@ -177,6 +183,10 @@ void get_timer_map(struct kvm_vcpu vcpu, struct timer_map map) · 115 unmodified lines
177	183	map->emul_ptimer = vcpu_ptimer(vcpu);
178	184	}
179	185
	186	+ map->direct_vtimer->direct = true;
	187	+ if (map->direct_ptimer)
	188	+ map->direct_ptimer->direct = true;
	189	+
180	190	trace_kvm_get_timer_map(vcpu->vcpu_id, map);
181	191	}
182	192
@@ -396,7 +406,11 @@ static bool kvm_timer_should_fire(struct arch_timer_context *timer_ctx) · 213 unmodified lines
396	406
397	407	int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
398	408	{
399		− return vcpu_has_wfit_active(vcpu) && wfit_delay_ns(vcpu) == 0;
	409	+ struct arch_timer_context *vtimer = vcpu_vtimer(vcpu);
	410	+ struct arch_timer_context *ptimer = vcpu_ptimer(vcpu);
	411	+
	412	+ return kvm_timer_should_fire(vtimer) \|\| kvm_timer_should_fire(ptimer) \|\|
	413	+ (vcpu_has_wfit_active(vcpu) && wfit_delay_ns(vcpu) == 0);
400	414	}
401	415
402	416	/*
@@ -447,6 +461,10 @@ static void kvm_timer_update_irq(struct kvm_vcpu *vcpu, bool new_level, · 44 unmodified lines
447	461	if (userspace_irqchip(vcpu->kvm))
448	462	return;
449	463
	464	+ /* Skip injecting on GICv5 for directly injected (DVI'd) timers */
	465	+ if (vgic_is_v5(vcpu->kvm) && timer_ctx->direct)
	466	+ return;
	467	+
450	468	kvm_vgic_inject_irq(vcpu->kvm, vcpu,
451	469	timer_irq(timer_ctx),
452	470	timer_ctx->irq.level,
@@ -674,6 +692,7 @@ static void kvm_timer_vcpu_load_gic(struct arch_timer_context *ctx) · 221 unmodified lines
674	692	phys_active = kvm_vgic_map_is_active(vcpu, timer_irq(ctx));
675	693
676	694	phys_active \|= ctx->irq.level;
	695	+ phys_active \|= vgic_is_v5(vcpu->kvm);
677	696
678	697	set_timer_irq_phys_active(ctx, phys_active);
679	698	}
@@ -740,13 +759,11 @@ static void kvm_timer_vcpu_load_nested_switch(struct kvm_vcpu *vcpu, · 60 unmodified lines
740	759
741	760	ret = kvm_vgic_map_phys_irq(vcpu,
742	761	map->direct_vtimer->host_timer_irq,
743		− timer_irq(map->direct_vtimer),
744		− &arch_timer_irq_ops);
	762	+ timer_irq(map->direct_vtimer));
745	763	WARN_ON_ONCE(ret);
746	764	ret = kvm_vgic_map_phys_irq(vcpu,
747	765	map->direct_ptimer->host_timer_irq,
748		− timer_irq(map->direct_ptimer),
749		− &arch_timer_irq_ops);
	766	+ timer_irq(map->direct_ptimer));
750	767	WARN_ON_ONCE(ret);
751	768	}
752	769	}
@@ -864,7 +881,8 @@ void kvm_timer_vcpu_load(struct kvm_vcpu *vcpu) · 111 unmodified lines
864	881	get_timer_map(vcpu, &map);
865	882
866	883	if (static_branch_likely(&has_gic_active_state)) {
867		− if (vcpu_has_nv(vcpu))
	884	+ /* We don't do NV on GICv5, yet */
	885	+ if (vcpu_has_nv(vcpu) && !vgic_is_v5(vcpu->kvm))
868	886	kvm_timer_vcpu_load_nested_switch(vcpu, &map);
869	887
870	888	kvm_timer_vcpu_load_gic(map.direct_vtimer);
@@ -934,6 +952,12 @@ void kvm_timer_vcpu_put(struct kvm_vcpu *vcpu) · 63 unmodified lines
934	952
935	953	if (kvm_vcpu_is_blocking(vcpu))
936	954	kvm_timer_blocking(vcpu);
	955	+
	956	+ if (vgic_is_v5(vcpu->kvm)) {
	957	+ set_timer_irq_phys_active(map.direct_vtimer, false);
	958	+ if (map.direct_ptimer)
	959	+ set_timer_irq_phys_active(map.direct_ptimer, false);
	960	+ }
937	961	}
938	962
939	963	void kvm_timer_sync_nested(struct kvm_vcpu *vcpu)
@@ -1097,10 +1121,19 @@ void kvm_timer_vcpu_init(struct kvm_vcpu *vcpu) · 157 unmodified lines
1097	1121	HRTIMER_MODE_ABS_HARD);
1098	1122	}
1099	1123
	1124	+/*
	1125	+ * This is always called during kvm_arch_init_vm, but will also be
	1126	+ * called from kvm_vgic_create if we have a vGICv5.
	1127	+ */
1100	1128	void kvm_timer_init_vm(struct kvm *kvm)
1101	1129	{
	1130	+ /*
	1131	+ * Set up the default PPIs - note that we adjust them based on
	1132	+ * the model of the GIC as GICv5 uses a different way to
	1133	+ * describing interrupts.
	1134	+ */
1102	1135	for (int i = 0; i < NR_KVM_TIMERS; i++)
1103		− kvm->arch.timer_data.ppi[i] = default_ppi[i];
	1136	+ kvm->arch.timer_data.ppi[i] = get_vgic_ppi(kvm, default_ppi[i]);
1104	1137	}
1105	1138
1106	1139	void kvm_timer_cpu_up(void)
@@ -1269,7 +1302,15 @@ static int timer_irq_set_irqchip_state(struct irq_data *d, · 162 unmodified lines
1269	1302
1270	1303	static void timer_irq_eoi(struct irq_data *d)
1271	1304	{
1272		− if (!irqd_is_forwarded_to_vcpu(d))
	1305	+ /*
	1306	+ * On a GICv5 host, we still need to call EOI on the parent for
	1307	+ * PPIs. The host driver already handles irqs which are forwarded to
	1308	+ * vcpus, and skips the GIC CDDI while still doing the GIC CDEOI. This
	1309	+ * is required to emulate the EOIMode=1 on GICv5 hardware. Failure to
	1310	+ * call EOI unsurprisingly results in BAD lock-ups.
	1311	+ */
	1312	+ if (!irqd_is_forwarded_to_vcpu(d) \|\|
	1313	+ kvm_vgic_global_state.type == VGIC_V5)
1273	1314	irq_chip_eoi_parent(d);
1274	1315	}
1275	1316
@@ -1333,7 +1374,8 @@ static int kvm_irq_init(struct arch_timer_kvm_info *info) · 57 unmodified lines
1333	1374	host_vtimer_irq = info->virtual_irq;
1334	1375	kvm_irq_fixup_flags(host_vtimer_irq, &host_vtimer_irq_flags);
1335	1376
1336		− if (kvm_vgic_global_state.no_hw_deactivation) {
	1377	+ if (kvm_vgic_global_state.no_hw_deactivation \|\|
	1378	+ kvm_vgic_global_state.type == VGIC_V5) {
1337	1379	struct fwnode_handle *fwnode;
1338	1380	struct irq_data *data;
1339	1381
@@ -1351,7 +1393,8 @@ static int kvm_irq_init(struct arch_timer_kvm_info *info) · 11 unmodified lines
1351	1393	return -ENOMEM;
1352	1394	}
1353	1395
1354		− arch_timer_irq_ops.flags \|= VGIC_IRQ_SW_RESAMPLE;
	1396	+ if (kvm_vgic_global_state.no_hw_deactivation)
	1397	+ arch_timer_irq_ops.flags \|= VGIC_IRQ_SW_RESAMPLE;
1355	1398	WARN_ON(irq_domain_push_irq(domain, host_vtimer_irq,
1356	1399	(void *)TIMER_VTIMER));
1357	1400	}
@@ -1502,10 +1545,13 @@ static bool timer_irqs_are_valid(struct kvm_vcpu *vcpu) · 144 unmodified lines
1502	1545	break;
1503	1546
1504	1547	/*
1505		− * We know by construction that we only have PPIs, so
1506		− * all values are less than 32.
	1548	+ * We know by construction that we only have PPIs, so all values
	1549	+ * are less than 32 for non-GICv5 VGICs. On GICv5, they are
	1550	+ * architecturally defined to be under 32 too. However, we mask
	1551	+ * off most of the bits as we might be presented with a GICv5
	1552	+ * style PPI where the type is encoded in the top-bits.
1507	1553	*/
1508		− ppis \|= BIT(irq);
	1554	+ ppis \|= BIT(irq & 0x1f);
1509	1555	}
1510	1556
1511	1557	valid = hweight32(ppis) == nr_timers(vcpu);
@@ -1543,6 +1589,7 @@ int kvm_timer_enable(struct kvm_vcpu *vcpu) · 31 unmodified lines
1543	1589	{
1544	1590	struct arch_timer_cpu *timer = vcpu_timer(vcpu);
1545	1591	struct timer_map map;
	1592	+ struct irq_ops *ops;
1546	1593	int ret;
1547	1594
1548	1595	if (timer->enabled)
@@ -1563,20 +1610,22 @@ int kvm_timer_enable(struct kvm_vcpu *vcpu) · 14 unmodified lines
1563	1610
1564	1611	get_timer_map(vcpu, &map);
1565	1612
	1613	+ ops = vgic_is_v5(vcpu->kvm) ? &arch_timer_irq_ops_vgic_v5 :
	1614	+ &arch_timer_irq_ops;
	1615	+
	1616	+ for (int i = 0; i < nr_timers(vcpu); i++)
	1617	+ kvm_vgic_set_irq_ops(vcpu, timer_irq(vcpu_get_timer(vcpu, i)), ops);
	1618	+
1566	1619	ret = kvm_vgic_map_phys_irq(vcpu,
1567	1620	map.direct_vtimer->host_timer_irq,
1568		− timer_irq(map.direct_vtimer),
1569		− &arch_timer_irq_ops);
	1621	+ timer_irq(map.direct_vtimer));
1570	1622	if (ret)
1571	1623	return ret;
1572	1624
1573		− if (map.direct_ptimer) {
	1625	+ if (map.direct_ptimer)
1574	1626	ret = kvm_vgic_map_phys_irq(vcpu,
1575	1627	map.direct_ptimer->host_timer_irq,
1576		− timer_irq(map.direct_ptimer),
1577		− &arch_timer_irq_ops);
1578		− }
1579		−
	1628	+ timer_irq(map.direct_ptimer));
1580	1629	if (ret)
1581	1630	return ret;
1582	1631
@@ -1603,15 +1652,14 @@ int kvm_arm_timer_set_attr(struct kvm_vcpu vcpu, struct kvm_device_attr attr) · 20 unmodified lines
1603	1652	if (get_user(irq, uaddr))
1604	1653	return -EFAULT;
1605	1654
1606		− if (!(irq_is_ppi(irq)))
	1655	+ if (!(irq_is_ppi(vcpu->kvm, irq)))
1607	1656	return -EINVAL;
1608	1657
1609		− mutex_lock(&vcpu->kvm->arch.config_lock);
	1658	+ guard(mutex)(&vcpu->kvm->arch.config_lock);
1610	1659
1611	1660	if (test_bit(KVM_ARCH_FLAG_TIMER_PPIS_IMMUTABLE,
1612	1661	&vcpu->kvm->arch.flags)) {
1613		− ret = -EBUSY;
1614		− goto out;
	1662	+ return -EBUSY;
1615	1663	}
1616	1664
1617	1665	switch (attr->attr) {
@@ -1628,10 +1676,16 @@ int kvm_arm_timer_set_attr(struct kvm_vcpu vcpu, struct kvm_device_attr attr) · 10 unmodified lines
1628	1676	idx = TIMER_HPTIMER;
1629	1677	break;
1630	1678	default:
1631		− ret = -ENXIO;
1632		− goto out;
	1679	+ return -ENXIO;
1633	1680	}
1634	1681
	1682	+ /*
	1683	+ * The PPIs for the Arch Timers are architecturally defined for
	1684	+ * GICv5. Reject anything that changes them from the specified value.
	1685	+ */
	1686	+ if (vgic_is_v5(vcpu->kvm) && vcpu->kvm->arch.timer_data.ppi[idx] != irq)
	1687	+ return -EINVAL;
	1688	+
1635	1689	/*
1636	1690	* We cannot validate the IRQ unicity before we run, so take it at
1637	1691	* face value. The verdict will be given on first vcpu run, for each
@@ -1639,8 +1693,6 @@ int kvm_arm_timer_set_attr(struct kvm_vcpu vcpu, struct kvm_device_attr attr) · 1 unmodified line
1639	1693	*/
1640	1694	vcpu->kvm->arch.timer_data.ppi[idx] = irq;
1641	1695
1642		−out:
1643		− mutex_unlock(&vcpu->kvm->arch.config_lock);
1644	1696	return ret;
1645	1697	}
1646	1698

arch/arm64/kvm/arm.c+40−4

@@ -47,6 +47,9 @@ · 46 unmodified lines
47	47	#include <kvm/arm_hypercalls.h>
48	48	#include <kvm/arm_pmu.h>
49	49	#include <kvm/arm_psci.h>
	50	+#include <kvm/arm_vgic.h>
	51	+
	52	+#include <linux/irqchip/arm-gic-v5.h>
50	53
51	54	#include "sys_regs.h"
52	55
@@ -615,6 +618,9 @@ static bool kvm_vcpu_should_clear_twi(struct kvm_vcpu *vcpu) · 562 unmodified lines
615	618	if (unlikely(kvm_wfi_trap_policy != KVM_WFX_NOTRAP_SINGLE_TASK))
616	619	return kvm_wfi_trap_policy == KVM_WFX_NOTRAP;
617	620
	621	+ if (vgic_is_v5(vcpu->kvm))
	622	+ return single_task_running();
	623	+
618	624	return single_task_running() &&
619	625	vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3 &&
620	626	(atomic_read(&vcpu->arch.vgic_cpu.vgic_v3.its_vpe.vlpi_count) \|\|
@@ -938,6 +944,10 @@ int kvm_arch_vcpu_run_pid_change(struct kvm_vcpu *vcpu) · 317 unmodified lines
938	944	return ret;
939	945	}
940	946
	947	+ ret = vgic_v5_finalize_ppi_state(kvm);
	948	+ if (ret)
	949	+ return ret;
	950	+
941	951	if (is_protected_kvm_enabled()) {
942	952	ret = pkvm_create_hyp_vm(kvm);
943	953	if (ret)
@@ -1443,10 +1453,11 @@ static int vcpu_interrupt_line(struct kvm_vcpu *vcpu, int number, bool level) · 499 unmodified lines
1443	1453	int kvm_vm_ioctl_irq_line(struct kvm kvm, struct kvm_irq_level irq_level,
1444	1454	bool line_status)
1445	1455	{
1446		− u32 irq = irq_level->irq;
1447	1456	unsigned int irq_type, vcpu_id, irq_num;
1448	1457	struct kvm_vcpu *vcpu = NULL;
1449	1458	bool level = irq_level->level;
	1459	+ u32 irq = irq_level->irq;
	1460	+ unsigned long *mask;
1450	1461
1451	1462	irq_type = (irq >> KVM_ARM_IRQ_TYPE_SHIFT) & KVM_ARM_IRQ_TYPE_MASK;
1452	1463	vcpu_id = (irq >> KVM_ARM_IRQ_VCPU_SHIFT) & KVM_ARM_IRQ_VCPU_MASK;
@@ -1476,16 +1487,37 @@ int kvm_vm_ioctl_irq_line(struct kvm kvm, struct kvm_irq_level irq_level, · 23 unmodified lines
1476	1487	if (!vcpu)
1477	1488	return -EINVAL;
1478	1489
1479		− if (irq_num < VGIC_NR_SGIS \|\| irq_num >= VGIC_NR_PRIVATE_IRQS)
	1490	+ if (vgic_is_v5(kvm)) {
	1491	+ if (irq_num >= VGIC_V5_NR_PRIVATE_IRQS)
	1492	+ return -EINVAL;
	1493	+
	1494	+ /*
	1495	+ * Only allow PPIs that are explicitly exposed to
	1496	+ * usespace to be driven via KVM_IRQ_LINE
	1497	+ */
	1498	+ mask = kvm->arch.vgic.gicv5_vm.userspace_ppis;
	1499	+ if (!test_bit(irq_num, mask))
	1500	+ return -EINVAL;
	1501	+
	1502	+ /* Build a GICv5-style IntID here */
	1503	+ irq_num = vgic_v5_make_ppi(irq_num);
	1504	+ } else if (irq_num < VGIC_NR_SGIS \|\|
	1505	+ irq_num >= VGIC_NR_PRIVATE_IRQS) {
1480	1506	return -EINVAL;
	1507	+ }
1481	1508
1482	1509	return kvm_vgic_inject_irq(kvm, vcpu, irq_num, level, NULL);
1483	1510	case KVM_ARM_IRQ_TYPE_SPI:
1484	1511	if (!irqchip_in_kernel(kvm))
1485	1512	return -ENXIO;
1486	1513
1487		− if (irq_num < VGIC_NR_PRIVATE_IRQS)
1488		− return -EINVAL;
	1514	+ if (vgic_is_v5(kvm)) {
	1515	+ /* Build a GICv5-style IntID here */
	1516	+ irq_num = vgic_v5_make_spi(irq_num);
	1517	+ } else {
	1518	+ if (irq_num < VGIC_NR_PRIVATE_IRQS)
	1519	+ return -EINVAL;
	1520	+ }
1489	1521
1490	1522	return kvm_vgic_inject_irq(kvm, NULL, irq_num, level, NULL);
1491	1523	}
@@ -2515,6 +2547,7 @@ static void kvm_hyp_init_symbols(void) · 1023 unmodified lines
2515	2547	{
2516	2548	kvm_nvhe_sym(id_aa64pfr0_el1_sys_val) = get_hyp_id_aa64pfr0_el1();
2517	2549	kvm_nvhe_sym(id_aa64pfr1_el1_sys_val) = read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1);
	2550	+ kvm_nvhe_sym(id_aa64pfr2_el1_sys_val) = read_sanitised_ftr_reg(SYS_ID_AA64PFR2_EL1);
2518	2551	kvm_nvhe_sym(id_aa64isar0_el1_sys_val) = read_sanitised_ftr_reg(SYS_ID_AA64ISAR0_EL1);
2519	2552	kvm_nvhe_sym(id_aa64isar1_el1_sys_val) = read_sanitised_ftr_reg(SYS_ID_AA64ISAR1_EL1);
2520	2553	kvm_nvhe_sym(id_aa64isar2_el1_sys_val) = read_sanitised_ftr_reg(SYS_ID_AA64ISAR2_EL1);
@@ -2537,6 +2570,9 @@ static void kvm_hyp_init_symbols(void) · 16 unmodified lines
2537	2570	kvm_nvhe_sym(hfgitr2_masks) = hfgitr2_masks;
2538	2571	kvm_nvhe_sym(hdfgrtr2_masks)= hdfgrtr2_masks;
2539	2572	kvm_nvhe_sym(hdfgwtr2_masks)= hdfgwtr2_masks;
	2573	+ kvm_nvhe_sym(ich_hfgrtr_masks) = ich_hfgrtr_masks;
	2574	+ kvm_nvhe_sym(ich_hfgwtr_masks) = ich_hfgwtr_masks;
	2575	+ kvm_nvhe_sym(ich_hfgitr_masks) = ich_hfgitr_masks;
2540	2576
2541	2577	/*
2542	2578	* Flush entire BSS since part of its data containing init symbols is read

arch/arm64/kvm/config.c+116−7

@@ -225,6 +225,7 @@ struct reg_feat_map_desc { · 224 unmodified lines
225	225	#define FEAT_MTPMU ID_AA64DFR0_EL1, MTPMU, IMP
226	226	#define FEAT_HCX ID_AA64MMFR1_EL1, HCX, IMP
227	227	#define FEAT_S2PIE ID_AA64MMFR3_EL1, S2PIE, IMP
	228	+#define FEAT_GCIE ID_AA64PFR2_EL1, GCIE, IMP
228	229
229	230	static bool not_feat_aa64el3(struct kvm *kvm)
230	231	{
@@ -1277,6 +1278,58 @@ static const struct reg_bits_to_feat_map vtcr_el2_feat_map[] = { · 1046 unmodified lines
1277	1278	static const DECLARE_FEAT_MAP(vtcr_el2_desc, VTCR_EL2,
1278	1279	vtcr_el2_feat_map, FEAT_AA64EL2);
1279	1280
	1281	+static const struct reg_bits_to_feat_map ich_hfgrtr_feat_map[] = {
	1282	+ NEEDS_FEAT(ICH_HFGRTR_EL2_ICC_APR_EL1 \|
	1283	+ ICH_HFGRTR_EL2_ICC_IDRn_EL1 \|
	1284	+ ICH_HFGRTR_EL2_ICC_CR0_EL1 \|
	1285	+ ICH_HFGRTR_EL2_ICC_HPPIR_EL1 \|
	1286	+ ICH_HFGRTR_EL2_ICC_PCR_EL1 \|
	1287	+ ICH_HFGRTR_EL2_ICC_ICSR_EL1 \|
	1288	+ ICH_HFGRTR_EL2_ICC_IAFFIDR_EL1 \|
	1289	+ ICH_HFGRTR_EL2_ICC_PPI_HMRn_EL1 \|
	1290	+ ICH_HFGRTR_EL2_ICC_PPI_ENABLERn_EL1 \|
	1291	+ ICH_HFGRTR_EL2_ICC_PPI_PENDRn_EL1 \|
	1292	+ ICH_HFGRTR_EL2_ICC_PPI_PRIORITYRn_EL1 \|
	1293	+ ICH_HFGRTR_EL2_ICC_PPI_ACTIVERn_EL1,
	1294	+ FEAT_GCIE),
	1295	+};
	1296	+
	1297	+static const DECLARE_FEAT_MAP_FGT(ich_hfgrtr_desc, ich_hfgrtr_masks,
	1298	+ ich_hfgrtr_feat_map, FEAT_GCIE);
	1299	+
	1300	+static const struct reg_bits_to_feat_map ich_hfgwtr_feat_map[] = {
	1301	+ NEEDS_FEAT(ICH_HFGWTR_EL2_ICC_APR_EL1 \|
	1302	+ ICH_HFGWTR_EL2_ICC_CR0_EL1 \|
	1303	+ ICH_HFGWTR_EL2_ICC_PCR_EL1 \|
	1304	+ ICH_HFGWTR_EL2_ICC_ICSR_EL1 \|
	1305	+ ICH_HFGWTR_EL2_ICC_PPI_ENABLERn_EL1 \|
	1306	+ ICH_HFGWTR_EL2_ICC_PPI_PENDRn_EL1 \|
	1307	+ ICH_HFGWTR_EL2_ICC_PPI_PRIORITYRn_EL1 \|
	1308	+ ICH_HFGWTR_EL2_ICC_PPI_ACTIVERn_EL1,
	1309	+ FEAT_GCIE),
	1310	+};
	1311	+
	1312	+static const DECLARE_FEAT_MAP_FGT(ich_hfgwtr_desc, ich_hfgwtr_masks,
	1313	+ ich_hfgwtr_feat_map, FEAT_GCIE);
	1314	+
	1315	+static const struct reg_bits_to_feat_map ich_hfgitr_feat_map[] = {
	1316	+ NEEDS_FEAT(ICH_HFGITR_EL2_GICCDEN \|
	1317	+ ICH_HFGITR_EL2_GICCDDIS \|
	1318	+ ICH_HFGITR_EL2_GICCDPRI \|
	1319	+ ICH_HFGITR_EL2_GICCDAFF \|
	1320	+ ICH_HFGITR_EL2_GICCDPEND \|
	1321	+ ICH_HFGITR_EL2_GICCDRCFG \|
	1322	+ ICH_HFGITR_EL2_GICCDHM \|
	1323	+ ICH_HFGITR_EL2_GICCDEOI \|
	1324	+ ICH_HFGITR_EL2_GICCDDI \|
	1325	+ ICH_HFGITR_EL2_GICRCDIA \|
	1326	+ ICH_HFGITR_EL2_GICRCDNMIA,
	1327	+ FEAT_GCIE),
	1328	+};
	1329	+
	1330	+static const DECLARE_FEAT_MAP_FGT(ich_hfgitr_desc, ich_hfgitr_masks,
	1331	+ ich_hfgitr_feat_map, FEAT_GCIE);
	1332	+
1280	1333	static void __init check_feat_map(const struct reg_bits_to_feat_map *map,
1281	1334	int map_size, u64 resx, const char *str)
1282	1335	{
@@ -1328,6 +1381,9 @@ void __init check_feature_map(void) · 45 unmodified lines
1328	1381	check_reg_desc(&sctlr_el2_desc);
1329	1382	check_reg_desc(&mdcr_el2_desc);
1330	1383	check_reg_desc(&vtcr_el2_desc);
	1384	+ check_reg_desc(&ich_hfgrtr_desc);
	1385	+ check_reg_desc(&ich_hfgwtr_desc);
	1386	+ check_reg_desc(&ich_hfgitr_desc);
1331	1387	}
1332	1388
1333	1389	static bool idreg_feat_match(struct kvm kvm, const struct reg_bits_to_feat_map map)
@@ -1460,6 +1516,13 @@ void compute_fgu(struct kvm *kvm, enum fgt_group_id fgt) · 126 unmodified lines
1460	1516	val \|= compute_fgu_bits(kvm, &hdfgrtr2_desc);
1461	1517	val \|= compute_fgu_bits(kvm, &hdfgwtr2_desc);
1462	1518	break;
	1519	+ case ICH_HFGRTR_GROUP:
	1520	+ val \|= compute_fgu_bits(kvm, &ich_hfgrtr_desc);
	1521	+ val \|= compute_fgu_bits(kvm, &ich_hfgwtr_desc);
	1522	+ break;
	1523	+ case ICH_HFGITR_GROUP:
	1524	+ val \|= compute_fgu_bits(kvm, &ich_hfgitr_desc);
	1525	+ break;
1463	1526	default:
1464	1527	BUG();
1465	1528	}
@@ -1531,6 +1594,15 @@ struct resx get_reg_fixed_bits(struct kvm *kvm, enum vcpu_sysreg reg) · 65 unmodified lines
1531	1594	case VTCR_EL2:
1532	1595	resx = compute_reg_resx_bits(kvm, &vtcr_el2_desc, 0, 0);
1533	1596	break;
	1597	+ case ICH_HFGRTR_EL2:
	1598	+ resx = compute_reg_resx_bits(kvm, &ich_hfgrtr_desc, 0, 0);
	1599	+ break;
	1600	+ case ICH_HFGWTR_EL2:
	1601	+ resx = compute_reg_resx_bits(kvm, &ich_hfgwtr_desc, 0, 0);
	1602	+ break;
	1603	+ case ICH_HFGITR_EL2:
	1604	+ resx = compute_reg_resx_bits(kvm, &ich_hfgitr_desc, 0, 0);
	1605	+ break;
1534	1606	default:
1535	1607	WARN_ON_ONCE(1);
1536	1608	resx = (typeof(resx)){};
@@ -1565,6 +1637,12 @@ static __always_inline struct fgt_masks *__fgt_reg_to_masks(enum vcpu_sysreg reg · 28 unmodified lines
1565	1637	return &hdfgrtr2_masks;
1566	1638	case HDFGWTR2_EL2:
1567	1639	return &hdfgwtr2_masks;
	1640	+ case ICH_HFGRTR_EL2:
	1641	+ return &ich_hfgrtr_masks;
	1642	+ case ICH_HFGWTR_EL2:
	1643	+ return &ich_hfgwtr_masks;
	1644	+ case ICH_HFGITR_EL2:
	1645	+ return &ich_hfgitr_masks;
1568	1646	default:
1569	1647	BUILD_BUG_ON(1);
1570	1648	}
@@ -1606,6 +1684,32 @@ static void __compute_hdfgwtr(struct kvm_vcpu *vcpu) · 35 unmodified lines
1606	1684	*vcpu_fgt(vcpu, HDFGWTR_EL2) \|= HDFGWTR_EL2_MDSCR_EL1;
1607	1685	}
1608	1686
	1687	+static void __compute_ich_hfgrtr(struct kvm_vcpu *vcpu)
	1688	+{
	1689	+ __compute_fgt(vcpu, ICH_HFGRTR_EL2);
	1690	+
	1691	+ /*
	1692	+ * ICC_IAFFIDR_EL1 always needs to be trapped when running a guest.
	1693	+ *
	1694	+ * We also trap accesses to ICC_IDR0_EL1 to allow us to completely hide
	1695	+ * FEAT_GCIE_LEGACY from the guest, and to (potentially) present fewer
	1696	+ * ID bits than the host supports.
	1697	+ */
	1698	+ *vcpu_fgt(vcpu, ICH_HFGRTR_EL2) &= ~(ICH_HFGRTR_EL2_ICC_IAFFIDR_EL1 \|
	1699	+ ICH_HFGRTR_EL2_ICC_IDRn_EL1);
	1700	+}
	1701	+
	1702	+static void __compute_ich_hfgwtr(struct kvm_vcpu *vcpu)
	1703	+{
	1704	+ __compute_fgt(vcpu, ICH_HFGWTR_EL2);
	1705	+
	1706	+ /*
	1707	+ * We present a different subset of PPIs the guest from what
	1708	+ * exist in real hardware. We only trap writes, not reads.
	1709	+ */
	1710	+ *vcpu_fgt(vcpu, ICH_HFGWTR_EL2) &= ~(ICH_HFGWTR_EL2_ICC_PPI_ENABLERn_EL1);
	1711	+}
	1712	+
1609	1713	void kvm_vcpu_load_fgt(struct kvm_vcpu *vcpu)
1610	1714	{
1611	1715	if (!cpus_have_final_cap(ARM64_HAS_FGT))
@@ -1618,12 +1722,17 @@ void kvm_vcpu_load_fgt(struct kvm_vcpu *vcpu) · 6 unmodified lines
1618	1722	__compute_hdfgwtr(vcpu);
1619	1723	__compute_fgt(vcpu, HAFGRTR_EL2);
1620	1724
1621		− if (!cpus_have_final_cap(ARM64_HAS_FGT2))
1622		− return;
	1725	+ if (cpus_have_final_cap(ARM64_HAS_FGT2)) {
	1726	+ __compute_fgt(vcpu, HFGRTR2_EL2);
	1727	+ __compute_fgt(vcpu, HFGWTR2_EL2);
	1728	+ __compute_fgt(vcpu, HFGITR2_EL2);
	1729	+ __compute_fgt(vcpu, HDFGRTR2_EL2);
	1730	+ __compute_fgt(vcpu, HDFGWTR2_EL2);
	1731	+ }
1623	1732
1624		− __compute_fgt(vcpu, HFGRTR2_EL2);
1625		− __compute_fgt(vcpu, HFGWTR2_EL2);
1626		− __compute_fgt(vcpu, HFGITR2_EL2);
1627		− __compute_fgt(vcpu, HDFGRTR2_EL2);
1628		− __compute_fgt(vcpu, HDFGWTR2_EL2);
	1733	+ if (cpus_have_final_cap(ARM64_HAS_GICV5_CPUIF)) {
	1734	+ __compute_ich_hfgrtr(vcpu);
	1735	+ __compute_ich_hfgwtr(vcpu);
	1736	+ __compute_fgt(vcpu, ICH_HFGITR_EL2);
	1737	+ }
1629	1738	}

arch/arm64/kvm/emulate-nested.c+68−0

@@ -2053,6 +2053,60 @@ static const struct encoding_to_trap_config encoding_to_fgt[] __initconst = { · 2052 unmodified lines
2053	2053	SR_FGT(SYS_AMEVCNTR0_EL0(2), HAFGRTR, AMEVCNTR02_EL0, 1),
2054	2054	SR_FGT(SYS_AMEVCNTR0_EL0(1), HAFGRTR, AMEVCNTR01_EL0, 1),
2055	2055	SR_FGT(SYS_AMEVCNTR0_EL0(0), HAFGRTR, AMEVCNTR00_EL0, 1),
	2056	+
	2057	+ /*
	2058	+ * ICH_HFGRTR_EL2 & ICH_HFGWTR_EL2
	2059	+ */
	2060	+ SR_FGT(SYS_ICC_APR_EL1, ICH_HFGRTR, ICC_APR_EL1, 0),
	2061	+ SR_FGT(SYS_ICC_IDR0_EL1, ICH_HFGRTR, ICC_IDRn_EL1, 0),
	2062	+ SR_FGT(SYS_ICC_CR0_EL1, ICH_HFGRTR, ICC_CR0_EL1, 0),
	2063	+ SR_FGT(SYS_ICC_HPPIR_EL1, ICH_HFGRTR, ICC_HPPIR_EL1, 0),
	2064	+ SR_FGT(SYS_ICC_PCR_EL1, ICH_HFGRTR, ICC_PCR_EL1, 0),
	2065	+ SR_FGT(SYS_ICC_ICSR_EL1, ICH_HFGRTR, ICC_ICSR_EL1, 0),
	2066	+ SR_FGT(SYS_ICC_IAFFIDR_EL1, ICH_HFGRTR, ICC_IAFFIDR_EL1, 0),
	2067	+ SR_FGT(SYS_ICC_PPI_HMR0_EL1, ICH_HFGRTR, ICC_PPI_HMRn_EL1, 0),
	2068	+ SR_FGT(SYS_ICC_PPI_HMR1_EL1, ICH_HFGRTR, ICC_PPI_HMRn_EL1, 0),
	2069	+ SR_FGT(SYS_ICC_PPI_ENABLER0_EL1, ICH_HFGRTR, ICC_PPI_ENABLERn_EL1, 0),
	2070	+ SR_FGT(SYS_ICC_PPI_ENABLER1_EL1, ICH_HFGRTR, ICC_PPI_ENABLERn_EL1, 0),
	2071	+ SR_FGT(SYS_ICC_PPI_CPENDR0_EL1, ICH_HFGRTR, ICC_PPI_PENDRn_EL1, 0),
	2072	+ SR_FGT(SYS_ICC_PPI_CPENDR1_EL1, ICH_HFGRTR, ICC_PPI_PENDRn_EL1, 0),
	2073	+ SR_FGT(SYS_ICC_PPI_SPENDR0_EL1, ICH_HFGRTR, ICC_PPI_PENDRn_EL1, 0),
	2074	+ SR_FGT(SYS_ICC_PPI_SPENDR1_EL1, ICH_HFGRTR, ICC_PPI_PENDRn_EL1, 0),
	2075	+ SR_FGT(SYS_ICC_PPI_PRIORITYR0_EL1, ICH_HFGRTR, ICC_PPI_PRIORITYRn_EL1, 0),
	2076	+ SR_FGT(SYS_ICC_PPI_PRIORITYR1_EL1, ICH_HFGRTR, ICC_PPI_PRIORITYRn_EL1, 0),
	2077	+ SR_FGT(SYS_ICC_PPI_PRIORITYR2_EL1, ICH_HFGRTR, ICC_PPI_PRIORITYRn_EL1, 0),
	2078	+ SR_FGT(SYS_ICC_PPI_PRIORITYR3_EL1, ICH_HFGRTR, ICC_PPI_PRIORITYRn_EL1, 0),
	2079	+ SR_FGT(SYS_ICC_PPI_PRIORITYR4_EL1, ICH_HFGRTR, ICC_PPI_PRIORITYRn_EL1, 0),
	2080	+ SR_FGT(SYS_ICC_PPI_PRIORITYR5_EL1, ICH_HFGRTR, ICC_PPI_PRIORITYRn_EL1, 0),
	2081	+ SR_FGT(SYS_ICC_PPI_PRIORITYR6_EL1, ICH_HFGRTR, ICC_PPI_PRIORITYRn_EL1, 0),
	2082	+ SR_FGT(SYS_ICC_PPI_PRIORITYR7_EL1, ICH_HFGRTR, ICC_PPI_PRIORITYRn_EL1, 0),
	2083	+ SR_FGT(SYS_ICC_PPI_PRIORITYR8_EL1, ICH_HFGRTR, ICC_PPI_PRIORITYRn_EL1, 0),
	2084	+ SR_FGT(SYS_ICC_PPI_PRIORITYR9_EL1, ICH_HFGRTR, ICC_PPI_PRIORITYRn_EL1, 0),
	2085	+ SR_FGT(SYS_ICC_PPI_PRIORITYR10_EL1, ICH_HFGRTR, ICC_PPI_PRIORITYRn_EL1, 0),
	2086	+ SR_FGT(SYS_ICC_PPI_PRIORITYR11_EL1, ICH_HFGRTR, ICC_PPI_PRIORITYRn_EL1, 0),
	2087	+ SR_FGT(SYS_ICC_PPI_PRIORITYR12_EL1, ICH_HFGRTR, ICC_PPI_PRIORITYRn_EL1, 0),
	2088	+ SR_FGT(SYS_ICC_PPI_PRIORITYR13_EL1, ICH_HFGRTR, ICC_PPI_PRIORITYRn_EL1, 0),
	2089	+ SR_FGT(SYS_ICC_PPI_PRIORITYR14_EL1, ICH_HFGRTR, ICC_PPI_PRIORITYRn_EL1, 0),
	2090	+ SR_FGT(SYS_ICC_PPI_PRIORITYR15_EL1, ICH_HFGRTR, ICC_PPI_PRIORITYRn_EL1, 0),
	2091	+ SR_FGT(SYS_ICC_PPI_CACTIVER0_EL1, ICH_HFGRTR, ICC_PPI_ACTIVERn_EL1, 0),
	2092	+ SR_FGT(SYS_ICC_PPI_CACTIVER1_EL1, ICH_HFGRTR, ICC_PPI_ACTIVERn_EL1, 0),
	2093	+ SR_FGT(SYS_ICC_PPI_SACTIVER0_EL1, ICH_HFGRTR, ICC_PPI_ACTIVERn_EL1, 0),
	2094	+ SR_FGT(SYS_ICC_PPI_SACTIVER1_EL1, ICH_HFGRTR, ICC_PPI_ACTIVERn_EL1, 0),
	2095	+
	2096	+ /*
	2097	+ * ICH_HFGITR_EL2
	2098	+ */
	2099	+ SR_FGT(GICV5_OP_GIC_CDEN, ICH_HFGITR, GICCDEN, 0),
	2100	+ SR_FGT(GICV5_OP_GIC_CDDIS, ICH_HFGITR, GICCDDIS, 0),
	2101	+ SR_FGT(GICV5_OP_GIC_CDPRI, ICH_HFGITR, GICCDPRI, 0),
	2102	+ SR_FGT(GICV5_OP_GIC_CDAFF, ICH_HFGITR, GICCDAFF, 0),
	2103	+ SR_FGT(GICV5_OP_GIC_CDPEND, ICH_HFGITR, GICCDPEND, 0),
	2104	+ SR_FGT(GICV5_OP_GIC_CDRCFG, ICH_HFGITR, GICCDRCFG, 0),
	2105	+ SR_FGT(GICV5_OP_GIC_CDHM, ICH_HFGITR, GICCDHM, 0),
	2106	+ SR_FGT(GICV5_OP_GIC_CDEOI, ICH_HFGITR, GICCDEOI, 0),
	2107	+ SR_FGT(GICV5_OP_GIC_CDDI, ICH_HFGITR, GICCDDI, 0),
	2108	+ SR_FGT(GICV5_OP_GICR_CDIA, ICH_HFGITR, GICRCDIA, 0),
	2109	+ SR_FGT(GICV5_OP_GICR_CDNMIA, ICH_HFGITR, GICRCDNMIA, 0),
2056	2110	};
2057	2111
2058	2112	/*
@@ -2127,6 +2181,9 @@ FGT_MASKS(hfgwtr2_masks, HFGWTR2_EL2); · 68 unmodified lines
2127	2181	FGT_MASKS(hfgitr2_masks, HFGITR2_EL2);
2128	2182	FGT_MASKS(hdfgrtr2_masks, HDFGRTR2_EL2);
2129	2183	FGT_MASKS(hdfgwtr2_masks, HDFGWTR2_EL2);
	2184	+FGT_MASKS(ich_hfgrtr_masks, ICH_HFGRTR_EL2);
	2185	+FGT_MASKS(ich_hfgwtr_masks, ICH_HFGWTR_EL2);
	2186	+FGT_MASKS(ich_hfgitr_masks, ICH_HFGITR_EL2);
2130	2187
2131	2188	static __init bool aggregate_fgt(union trap_config tc)
2132	2189	{
@@ -2162,6 +2219,14 @@ static __init bool aggregate_fgt(union trap_config tc) · 29 unmodified lines
2162	2219	rmasks = &hfgitr2_masks;
2163	2220	wmasks = NULL;
2164	2221	break;
	2222	+ case ICH_HFGRTR_GROUP:
	2223	+ rmasks = &ich_hfgrtr_masks;
	2224	+ wmasks = &ich_hfgwtr_masks;
	2225	+ break;
	2226	+ case ICH_HFGITR_GROUP:
	2227	+ rmasks = &ich_hfgitr_masks;
	2228	+ wmasks = NULL;
	2229	+ break;
2165	2230	}
2166	2231
2167	2232	rresx = rmasks->res0 \| rmasks->res1;
@@ -2232,6 +2297,9 @@ static __init int check_all_fgt_masks(int ret) · 64 unmodified lines
2232	2297	&hfgitr2_masks,
2233	2298	&hdfgrtr2_masks,
2234	2299	&hdfgwtr2_masks,
	2300	+ &ich_hfgrtr_masks,
	2301	+ &ich_hfgwtr_masks,
	2302	+ &ich_hfgitr_masks,
2235	2303	};
2236	2304	int err = 0;
2237	2305

arch/arm64/kvm/hyp/include/hyp/switch.h+27−0

@@ -233,6 +233,18 @@ static inline void __activate_traps_hfgxtr(struct kvm_vcpu *vcpu) · 232 unmodified lines
233	233	__activate_fgt(hctxt, vcpu, HDFGWTR2_EL2);
234	234	}
235	235
	236	+static inline void __activate_traps_ich_hfgxtr(struct kvm_vcpu *vcpu)
	237	+{
	238	+ struct kvm_cpu_context *hctxt = host_data_ptr(host_ctxt);
	239	+
	240	+ if (!cpus_have_final_cap(ARM64_HAS_GICV5_CPUIF))
	241	+ return;
	242	+
	243	+ __activate_fgt(hctxt, vcpu, ICH_HFGRTR_EL2);
	244	+ __activate_fgt(hctxt, vcpu, ICH_HFGWTR_EL2);
	245	+ __activate_fgt(hctxt, vcpu, ICH_HFGITR_EL2);
	246	+}
	247	+
236	248	#define __deactivate_fgt(htcxt, vcpu, reg) \
237	249	do { \
238	250	write_sysreg_s(ctxt_sys_reg(hctxt, reg), \
@@ -265,6 +277,19 @@ static inline void __deactivate_traps_hfgxtr(struct kvm_vcpu *vcpu) · 26 unmodified lines
265	277	__deactivate_fgt(hctxt, vcpu, HDFGWTR2_EL2);
266	278	}
267	279
	280	+static inline void __deactivate_traps_ich_hfgxtr(struct kvm_vcpu *vcpu)
	281	+{
	282	+ struct kvm_cpu_context *hctxt = host_data_ptr(host_ctxt);
	283	+
	284	+ if (!cpus_have_final_cap(ARM64_HAS_GICV5_CPUIF))
	285	+ return;
	286	+
	287	+ __deactivate_fgt(hctxt, vcpu, ICH_HFGRTR_EL2);
	288	+ __deactivate_fgt(hctxt, vcpu, ICH_HFGWTR_EL2);
	289	+ __deactivate_fgt(hctxt, vcpu, ICH_HFGITR_EL2);
	290	+
	291	+}
	292	+
268	293	static inline void __activate_traps_mpam(struct kvm_vcpu *vcpu)
269	294	{
270	295	u64 r = MPAM2_EL2_TRAPMPAM0EL1 \| MPAM2_EL2_TRAPMPAM1EL1;
@@ -328,6 +353,7 @@ static inline void __activate_traps_common(struct kvm_vcpu *vcpu) · 57 unmodified lines
328	353	}
329	354
330	355	__activate_traps_hfgxtr(vcpu);
	356	+ __activate_traps_ich_hfgxtr(vcpu);
331	357	__activate_traps_mpam(vcpu);
332	358	}
333	359
@@ -345,6 +371,7 @@ static inline void __deactivate_traps_common(struct kvm_vcpu *vcpu) · 11 unmodified lines
345	371	write_sysreg_s(ctxt_sys_reg(hctxt, HCRX_EL2), SYS_HCRX_EL2);
346	372
347	373	__deactivate_traps_hfgxtr(vcpu);
	374	+ __deactivate_traps_ich_hfgxtr(vcpu);
348	375	__deactivate_traps_mpam();
349	376	}
350	377

arch/arm64/kvm/hyp/nvhe/Makefile+1−1

@@ -26,7 +26,7 @@ hyp-obj-y := timer-sr.o sysreg-sr.o debug-sr.o switch.o tlb.o hyp-init.o host.o · 25 unmodified lines
26	26	hyp-main.o hyp-smp.o psci-relay.o early_alloc.o page_alloc.o \
27	27	cache.o setup.o mm.o mem_protect.o sys_regs.o pkvm.o stacktrace.o ffa.o
28	28	hyp-obj-y += ../vgic-v3-sr.o ../aarch32.o ../vgic-v2-cpuif-proxy.o ../entry.o \
29		− ../fpsimd.o ../hyp-entry.o ../exception.o ../pgtable.o
	29	+ ../fpsimd.o ../hyp-entry.o ../exception.o ../pgtable.o ../vgic-v5-sr.o
30	30	hyp-obj-y += ../../../kernel/smccc-call.o
31	31	hyp-obj-$(CONFIG_LIST_HARDENED) += list_debug.o
32	32	hyp-obj-$(CONFIG_NVHE_EL2_TRACING) += clock.o trace.o events.o

arch/arm64/kvm/hyp/nvhe/hyp-main.c+16−0

@@ -650,6 +650,20 @@ static void handle___tracing_write_event(struct kvm_cpu_context *host_ctxt) · 649 unmodified lines
650	650	trace_selftest(id);
651	651	}
652	652
	653	+static void handle___vgic_v5_save_apr(struct kvm_cpu_context *host_ctxt)
	654	+{
	655	+ DECLARE_REG(struct vgic_v5_cpu_if *, cpu_if, host_ctxt, 1);
	656	+
	657	+ __vgic_v5_save_apr(kern_hyp_va(cpu_if));
	658	+}
	659	+
	660	+static void handle___vgic_v5_restore_vmcr_apr(struct kvm_cpu_context *host_ctxt)
	661	+{
	662	+ DECLARE_REG(struct vgic_v5_cpu_if *, cpu_if, host_ctxt, 1);
	663	+
	664	+ __vgic_v5_restore_vmcr_apr(kern_hyp_va(cpu_if));
	665	+}
	666	+
653	667	typedef void (hcall_t)(struct kvm_cpu_context );
654	668
655	669	#define HANDLE_FUNC(x) [__KVM_HOST_SMCCC_FUNC_##x] = (hcall_t)handle_##x
@@ -683,6 +697,8 @@ static const hcall_t host_hcall[] = { · 27 unmodified lines
683	697	HANDLE_FUNC(__kvm_timer_set_cntvoff),
684	698	HANDLE_FUNC(__vgic_v3_save_aprs),
685	699	HANDLE_FUNC(__vgic_v3_restore_vmcr_aprs),
	700	+ HANDLE_FUNC(__vgic_v5_save_apr),
	701	+ HANDLE_FUNC(__vgic_v5_restore_vmcr_apr),
686	702	HANDLE_FUNC(__pkvm_reserve_vm),
687	703	HANDLE_FUNC(__pkvm_unreserve_vm),
688	704	HANDLE_FUNC(__pkvm_init_vm),

arch/arm64/kvm/hyp/nvhe/switch.c+15−0

@@ -44,6 +44,9 @@ struct fgt_masks hfgwtr2_masks; · 43 unmodified lines
44	44	struct fgt_masks hfgitr2_masks;
45	45	struct fgt_masks hdfgrtr2_masks;
46	46	struct fgt_masks hdfgwtr2_masks;
	47	+struct fgt_masks ich_hfgrtr_masks;
	48	+struct fgt_masks ich_hfgwtr_masks;
	49	+struct fgt_masks ich_hfgitr_masks;
47	50
48	51	extern void kvm_nvhe_prepare_backtrace(unsigned long fp, unsigned long pc);
49	52
@@ -110,6 +113,12 @@ static void __deactivate_traps(struct kvm_vcpu *vcpu) · 60 unmodified lines
110	113	/* Save VGICv3 state on non-VHE systems */
111	114	static void __hyp_vgic_save_state(struct kvm_vcpu *vcpu)
112	115	{
	116	+ if (vgic_is_v5(kern_hyp_va(vcpu->kvm))) {
	117	+ __vgic_v5_save_state(&vcpu->arch.vgic_cpu.vgic_v5);
	118	+ __vgic_v5_save_ppi_state(&vcpu->arch.vgic_cpu.vgic_v5);
	119	+ return;
	120	+ }
	121	+
113	122	if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif)) {
114	123	__vgic_v3_save_state(&vcpu->arch.vgic_cpu.vgic_v3);
115	124	__vgic_v3_deactivate_traps(&vcpu->arch.vgic_cpu.vgic_v3);
@@ -119,6 +128,12 @@ static void __hyp_vgic_save_state(struct kvm_vcpu *vcpu) · 3 unmodified lines
119	128	/* Restore VGICv3 state on non-VHE systems */
120	129	static void __hyp_vgic_restore_state(struct kvm_vcpu *vcpu)
121	130	{
	131	+ if (vgic_is_v5(kern_hyp_va(vcpu->kvm))) {
	132	+ __vgic_v5_restore_state(&vcpu->arch.vgic_cpu.vgic_v5);
	133	+ __vgic_v5_restore_ppi_state(&vcpu->arch.vgic_cpu.vgic_v5);
	134	+ return;
	135	+ }
	136	+
122	137	if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif)) {
123	138	__vgic_v3_activate_traps(&vcpu->arch.vgic_cpu.vgic_v3);
124	139	__vgic_v3_restore_state(&vcpu->arch.vgic_cpu.vgic_v3);

arch/arm64/kvm/hyp/nvhe/sys_regs.c+8−0

@@ -20,6 +20,7 @@ · 19 unmodified lines
20	20	*/
21	21	u64 id_aa64pfr0_el1_sys_val;
22	22	u64 id_aa64pfr1_el1_sys_val;
	23	+u64 id_aa64pfr2_el1_sys_val;
23	24	u64 id_aa64isar0_el1_sys_val;
24	25	u64 id_aa64isar1_el1_sys_val;
25	26	u64 id_aa64isar2_el1_sys_val;
@@ -108,6 +109,11 @@ static const struct pvm_ftr_bits pvmid_aa64pfr1[] = { · 82 unmodified lines
108	109	FEAT_END
109	110	};
110	111
	112	+static const struct pvm_ftr_bits pvmid_aa64pfr2[] = {
	113	+ MAX_FEAT(ID_AA64PFR2_EL1, GCIE, NI),
	114	+ FEAT_END
	115	+};
	116	+
111	117	static const struct pvm_ftr_bits pvmid_aa64mmfr0[] = {
112	118	MAX_FEAT_ENUM(ID_AA64MMFR0_EL1, PARANGE, 40),
113	119	MAX_FEAT_ENUM(ID_AA64MMFR0_EL1, ASIDBITS, 16),
@@ -221,6 +227,8 @@ static u64 pvm_calc_id_reg(const struct kvm_vcpu *vcpu, u32 id) · 107 unmodified lines
221	227	return get_restricted_features(vcpu, id_aa64pfr0_el1_sys_val, pvmid_aa64pfr0);
222	228	case SYS_ID_AA64PFR1_EL1:
223	229	return get_restricted_features(vcpu, id_aa64pfr1_el1_sys_val, pvmid_aa64pfr1);
	230	+ case SYS_ID_AA64PFR2_EL1:
	231	+ return get_restricted_features(vcpu, id_aa64pfr2_el1_sys_val, pvmid_aa64pfr2);
224	232	case SYS_ID_AA64ISAR0_EL1:
225	233	return id_aa64isar0_el1_sys_val;
226	234	case SYS_ID_AA64ISAR1_EL1:

arch/arm64/kvm/hyp/vgic-v5-sr.c+166−0

@@ -0,0 +1,166 @@
	1	+// SPDX-License-Identifier: GPL-2.0-only
	2	+/*
	3	+ * Copyright (C) 2025, 2026 - Arm Ltd
	4	+ */
	5	+
	6	+#include <linux/irqchip/arm-gic-v5.h>
	7	+
	8	+#include <asm/kvm_hyp.h>
	9	+
	10	+void __vgic_v5_save_apr(struct vgic_v5_cpu_if *cpu_if)
	11	+{
	12	+ cpu_if->vgic_apr = read_sysreg_s(SYS_ICH_APR_EL2);
	13	+}
	14	+
	15	+static void __vgic_v5_compat_mode_disable(void)
	16	+{
	17	+ sysreg_clear_set_s(SYS_ICH_VCTLR_EL2, ICH_VCTLR_EL2_V3, 0);
	18	+ isb();
	19	+}
	20	+
	21	+void __vgic_v5_restore_vmcr_apr(struct vgic_v5_cpu_if *cpu_if)
	22	+{
	23	+ __vgic_v5_compat_mode_disable();
	24	+
	25	+ write_sysreg_s(cpu_if->vgic_vmcr, SYS_ICH_VMCR_EL2);
	26	+ write_sysreg_s(cpu_if->vgic_apr, SYS_ICH_APR_EL2);
	27	+}
	28	+
	29	+void __vgic_v5_save_ppi_state(struct vgic_v5_cpu_if *cpu_if)
	30	+{
	31	+ /*
	32	+ * The following code assumes that the bitmap storage that we have for
	33	+ * PPIs is either 64 (architected PPIs, only) or 128 bits (architected &
	34	+ * impdef PPIs).
	35	+ */
	36	+ BUILD_BUG_ON(VGIC_V5_NR_PRIVATE_IRQS % 64);
	37	+
	38	+ bitmap_write(host_data_ptr(vgic_v5_ppi_state)->activer_exit,
	39	+ read_sysreg_s(SYS_ICH_PPI_ACTIVER0_EL2), 0, 64);
	40	+ bitmap_write(host_data_ptr(vgic_v5_ppi_state)->pendr_exit,
	41	+ read_sysreg_s(SYS_ICH_PPI_PENDR0_EL2), 0, 64);
	42	+
	43	+ cpu_if->vgic_ppi_priorityr[0] = read_sysreg_s(SYS_ICH_PPI_PRIORITYR0_EL2);
	44	+ cpu_if->vgic_ppi_priorityr[1] = read_sysreg_s(SYS_ICH_PPI_PRIORITYR1_EL2);
	45	+ cpu_if->vgic_ppi_priorityr[2] = read_sysreg_s(SYS_ICH_PPI_PRIORITYR2_EL2);
	46	+ cpu_if->vgic_ppi_priorityr[3] = read_sysreg_s(SYS_ICH_PPI_PRIORITYR3_EL2);
	47	+ cpu_if->vgic_ppi_priorityr[4] = read_sysreg_s(SYS_ICH_PPI_PRIORITYR4_EL2);
	48	+ cpu_if->vgic_ppi_priorityr[5] = read_sysreg_s(SYS_ICH_PPI_PRIORITYR5_EL2);
	49	+ cpu_if->vgic_ppi_priorityr[6] = read_sysreg_s(SYS_ICH_PPI_PRIORITYR6_EL2);
	50	+ cpu_if->vgic_ppi_priorityr[7] = read_sysreg_s(SYS_ICH_PPI_PRIORITYR7_EL2);
	51	+
	52	+ if (VGIC_V5_NR_PRIVATE_IRQS == 128) {
	53	+ bitmap_write(host_data_ptr(vgic_v5_ppi_state)->activer_exit,
	54	+ read_sysreg_s(SYS_ICH_PPI_ACTIVER1_EL2), 64, 64);
	55	+ bitmap_write(host_data_ptr(vgic_v5_ppi_state)->pendr_exit,
	56	+ read_sysreg_s(SYS_ICH_PPI_PENDR1_EL2), 64, 64);
	57	+
	58	+ cpu_if->vgic_ppi_priorityr[8] = read_sysreg_s(SYS_ICH_PPI_PRIORITYR8_EL2);
	59	+ cpu_if->vgic_ppi_priorityr[9] = read_sysreg_s(SYS_ICH_PPI_PRIORITYR9_EL2);
	60	+ cpu_if->vgic_ppi_priorityr[10] = read_sysreg_s(SYS_ICH_PPI_PRIORITYR10_EL2);
	61	+ cpu_if->vgic_ppi_priorityr[11] = read_sysreg_s(SYS_ICH_PPI_PRIORITYR11_EL2);
	62	+ cpu_if->vgic_ppi_priorityr[12] = read_sysreg_s(SYS_ICH_PPI_PRIORITYR12_EL2);
	63	+ cpu_if->vgic_ppi_priorityr[13] = read_sysreg_s(SYS_ICH_PPI_PRIORITYR13_EL2);
	64	+ cpu_if->vgic_ppi_priorityr[14] = read_sysreg_s(SYS_ICH_PPI_PRIORITYR14_EL2);
	65	+ cpu_if->vgic_ppi_priorityr[15] = read_sysreg_s(SYS_ICH_PPI_PRIORITYR15_EL2);
	66	+ }
	67	+
	68	+ /* Now that we are done, disable DVI */
	69	+ write_sysreg_s(0, SYS_ICH_PPI_DVIR0_EL2);
	70	+ write_sysreg_s(0, SYS_ICH_PPI_DVIR1_EL2);
	71	+}
	72	+
	73	+void __vgic_v5_restore_ppi_state(struct vgic_v5_cpu_if *cpu_if)
	74	+{
	75	+ DECLARE_BITMAP(pendr, VGIC_V5_NR_PRIVATE_IRQS);
	76	+
	77	+ /* We assume 64 or 128 PPIs - see above comment */
	78	+ BUILD_BUG_ON(VGIC_V5_NR_PRIVATE_IRQS % 64);
	79	+
	80	+ /* Enable DVI so that the guest's interrupt config takes over */
	81	+ write_sysreg_s(bitmap_read(cpu_if->vgic_ppi_dvir, 0, 64),
	82	+ SYS_ICH_PPI_DVIR0_EL2);
	83	+
	84	+ write_sysreg_s(bitmap_read(cpu_if->vgic_ppi_activer, 0, 64),
	85	+ SYS_ICH_PPI_ACTIVER0_EL2);
	86	+ write_sysreg_s(bitmap_read(cpu_if->vgic_ppi_enabler, 0, 64),
	87	+ SYS_ICH_PPI_ENABLER0_EL2);
	88	+
	89	+ /* Update the pending state of the NON-DVI'd PPIs, only */
	90	+ bitmap_andnot(pendr, host_data_ptr(vgic_v5_ppi_state)->pendr_entry,
	91	+ cpu_if->vgic_ppi_dvir, VGIC_V5_NR_PRIVATE_IRQS);
	92	+ write_sysreg_s(bitmap_read(pendr, 0, 64), SYS_ICH_PPI_PENDR0_EL2);
	93	+
	94	+ write_sysreg_s(cpu_if->vgic_ppi_priorityr[0],
	95	+ SYS_ICH_PPI_PRIORITYR0_EL2);
	96	+ write_sysreg_s(cpu_if->vgic_ppi_priorityr[1],
	97	+ SYS_ICH_PPI_PRIORITYR1_EL2);
	98	+ write_sysreg_s(cpu_if->vgic_ppi_priorityr[2],
	99	+ SYS_ICH_PPI_PRIORITYR2_EL2);
	100	+ write_sysreg_s(cpu_if->vgic_ppi_priorityr[3],
	101	+ SYS_ICH_PPI_PRIORITYR3_EL2);
	102	+ write_sysreg_s(cpu_if->vgic_ppi_priorityr[4],
	103	+ SYS_ICH_PPI_PRIORITYR4_EL2);
	104	+ write_sysreg_s(cpu_if->vgic_ppi_priorityr[5],
	105	+ SYS_ICH_PPI_PRIORITYR5_EL2);
	106	+ write_sysreg_s(cpu_if->vgic_ppi_priorityr[6],
	107	+ SYS_ICH_PPI_PRIORITYR6_EL2);
	108	+ write_sysreg_s(cpu_if->vgic_ppi_priorityr[7],
	109	+ SYS_ICH_PPI_PRIORITYR7_EL2);
	110	+
	111	+ if (VGIC_V5_NR_PRIVATE_IRQS == 128) {
	112	+ /* Enable DVI so that the guest's interrupt config takes over */
	113	+ write_sysreg_s(bitmap_read(cpu_if->vgic_ppi_dvir, 64, 64),
	114	+ SYS_ICH_PPI_DVIR1_EL2);
	115	+
	116	+ write_sysreg_s(bitmap_read(cpu_if->vgic_ppi_activer, 64, 64),
	117	+ SYS_ICH_PPI_ACTIVER1_EL2);
	118	+ write_sysreg_s(bitmap_read(cpu_if->vgic_ppi_enabler, 64, 64),
	119	+ SYS_ICH_PPI_ENABLER1_EL2);
	120	+ write_sysreg_s(bitmap_read(pendr, 64, 64),
	121	+ SYS_ICH_PPI_PENDR1_EL2);
	122	+
	123	+ write_sysreg_s(cpu_if->vgic_ppi_priorityr[8],
	124	+ SYS_ICH_PPI_PRIORITYR8_EL2);
	125	+ write_sysreg_s(cpu_if->vgic_ppi_priorityr[9],
	126	+ SYS_ICH_PPI_PRIORITYR9_EL2);
	127	+ write_sysreg_s(cpu_if->vgic_ppi_priorityr[10],
	128	+ SYS_ICH_PPI_PRIORITYR10_EL2);
	129	+ write_sysreg_s(cpu_if->vgic_ppi_priorityr[11],
	130	+ SYS_ICH_PPI_PRIORITYR11_EL2);
	131	+ write_sysreg_s(cpu_if->vgic_ppi_priorityr[12],
	132	+ SYS_ICH_PPI_PRIORITYR12_EL2);
	133	+ write_sysreg_s(cpu_if->vgic_ppi_priorityr[13],
	134	+ SYS_ICH_PPI_PRIORITYR13_EL2);
	135	+ write_sysreg_s(cpu_if->vgic_ppi_priorityr[14],
	136	+ SYS_ICH_PPI_PRIORITYR14_EL2);
	137	+ write_sysreg_s(cpu_if->vgic_ppi_priorityr[15],
	138	+ SYS_ICH_PPI_PRIORITYR15_EL2);
	139	+ } else {
	140	+ write_sysreg_s(0, SYS_ICH_PPI_DVIR1_EL2);
	141	+
	142	+ write_sysreg_s(0, SYS_ICH_PPI_ACTIVER1_EL2);
	143	+ write_sysreg_s(0, SYS_ICH_PPI_ENABLER1_EL2);
	144	+ write_sysreg_s(0, SYS_ICH_PPI_PENDR1_EL2);
	145	+
	146	+ write_sysreg_s(0, SYS_ICH_PPI_PRIORITYR8_EL2);
	147	+ write_sysreg_s(0, SYS_ICH_PPI_PRIORITYR9_EL2);
	148	+ write_sysreg_s(0, SYS_ICH_PPI_PRIORITYR10_EL2);
	149	+ write_sysreg_s(0, SYS_ICH_PPI_PRIORITYR11_EL2);
	150	+ write_sysreg_s(0, SYS_ICH_PPI_PRIORITYR12_EL2);
	151	+ write_sysreg_s(0, SYS_ICH_PPI_PRIORITYR13_EL2);
	152	+ write_sysreg_s(0, SYS_ICH_PPI_PRIORITYR14_EL2);
	153	+ write_sysreg_s(0, SYS_ICH_PPI_PRIORITYR15_EL2);
	154	+ }
	155	+}
	156	+
	157	+void __vgic_v5_save_state(struct vgic_v5_cpu_if *cpu_if)
	158	+{
	159	+ cpu_if->vgic_vmcr = read_sysreg_s(SYS_ICH_VMCR_EL2);
	160	+ cpu_if->vgic_icsr = read_sysreg_s(SYS_ICC_ICSR_EL1);
	161	+}
	162	+
	163	+void __vgic_v5_restore_state(struct vgic_v5_cpu_if *cpu_if)
	164	+{
	165	+ write_sysreg_s(cpu_if->vgic_icsr, SYS_ICC_ICSR_EL1);
	166	+}

arch/arm64/kvm/hyp/vhe/Makefile+1−1

@@ -10,4 +10,4 @@ CFLAGS_switch.o += -Wno-override-init · 9 unmodified lines
10	10
11	11	obj-y := timer-sr.o sysreg-sr.o debug-sr.o switch.o tlb.o
12	12	obj-y += ../vgic-v3-sr.o ../aarch32.o ../vgic-v2-cpuif-proxy.o ../entry.o \
13		− ../fpsimd.o ../hyp-entry.o ../exception.o
	13	+ ../fpsimd.o ../hyp-entry.o ../exception.o ../vgic-v5-sr.o

arch/arm64/kvm/nested.c+5−0

@@ -1558,6 +1558,11 @@ u64 limit_nv_id_reg(struct kvm *kvm, u32 reg, u64 val) · 1557 unmodified lines
1558	1558	ID_AA64PFR1_EL1_MTE);
1559	1559	break;
1560	1560
	1561	+ case SYS_ID_AA64PFR2_EL1:
	1562	+ /* GICv5 is not yet supported for NV */
	1563	+ val &= ~ID_AA64PFR2_EL1_GCIE;
	1564	+ break;
	1565	+
1561	1566	case SYS_ID_AA64MMFR0_EL1:
1562	1567	/* Hide ExS, Secure Memory */
1563	1568	val &= ~(ID_AA64MMFR0_EL1_EXS \|

arch/arm64/kvm/pmu-emul.c+15−5

@@ -939,7 +939,8 @@ int kvm_arm_pmu_v3_enable(struct kvm_vcpu *vcpu) · 938 unmodified lines
939	939	* number against the dimensions of the vgic and make sure
940	940	* it's valid.
941	941	*/
942		− if (!irq_is_ppi(irq) && !vgic_valid_spi(vcpu->kvm, irq))
	942	+ if (!irq_is_ppi(vcpu->kvm, irq) &&
	943	+ !vgic_valid_spi(vcpu->kvm, irq))
943	944	return -EINVAL;
944	945	} else if (kvm_arm_pmu_irq_initialized(vcpu)) {
945	946	return -EINVAL;
@@ -961,8 +962,13 @@ static int kvm_arm_pmu_v3_init(struct kvm_vcpu *vcpu) · 15 unmodified lines
961	962	if (!vgic_initialized(vcpu->kvm))
962	963	return -ENODEV;
963	964
964		− if (!kvm_arm_pmu_irq_initialized(vcpu))
965		− return -ENXIO;
	965	+ if (!kvm_arm_pmu_irq_initialized(vcpu)) {
	966	+ if (!vgic_is_v5(vcpu->kvm))
	967	+ return -ENXIO;
	968	+
	969	+ /* Use the architected irq number for GICv5. */
	970	+ vcpu->arch.pmu.irq_num = KVM_ARMV8_PMU_GICV5_IRQ;
	971	+ }
966	972
967	973	ret = kvm_vgic_set_owner(vcpu, vcpu->arch.pmu.irq_num,
968	974	&vcpu->arch.pmu);
@@ -987,11 +993,15 @@ static bool pmu_irq_is_valid(struct kvm *kvm, int irq) · 18 unmodified lines
987	993	unsigned long i;
988	994	struct kvm_vcpu *vcpu;
989	995
	996	+ /* On GICv5, the PMUIRQ is architecturally mandated to be PPI 23 */
	997	+ if (vgic_is_v5(kvm) && irq != KVM_ARMV8_PMU_GICV5_IRQ)
	998	+ return false;
	999	+
990	1000	kvm_for_each_vcpu(i, vcpu, kvm) {
991	1001	if (!kvm_arm_pmu_irq_initialized(vcpu))
992	1002	continue;
993	1003
994		− if (irq_is_ppi(irq)) {
	1004	+ if (irq_is_ppi(vcpu->kvm, irq)) {
995	1005	if (vcpu->arch.pmu.irq_num != irq)
996	1006	return false;
997	1007	} else {
@@ -1142,7 +1152,7 @@ int kvm_arm_pmu_v3_set_attr(struct kvm_vcpu vcpu, struct kvm_device_attr attr) · 144 unmodified lines
1142	1152	return -EFAULT;
1143	1153
1144	1154	/* The PMU overflow interrupt can be a PPI or a valid SPI. */
1145		− if (!(irq_is_ppi(irq) \|\| irq_is_spi(irq)))
	1155	+ if (!(irq_is_ppi(vcpu->kvm, irq) \|\| irq_is_spi(vcpu->kvm, irq)))
1146	1156	return -EINVAL;
1147	1157
1148	1158	if (!pmu_irq_is_valid(kvm, irq))

arch/arm64/kvm/sys_regs.c+158−18

@@ -681,6 +681,91 @@ static bool access_gic_dir(struct kvm_vcpu *vcpu, · 680 unmodified lines
681	681	return true;
682	682	}
683	683
	684	+static bool access_gicv5_idr0(struct kvm_vcpu vcpu, struct sys_reg_params p,
	685	+ const struct sys_reg_desc *r)
	686	+{
	687	+ if (p->is_write)
	688	+ return undef_access(vcpu, p, r);
	689	+
	690	+ /*
	691	+ * Expose KVM's priority- and ID-bits to the guest, but not GCIE_LEGACY.
	692	+ *
	693	+ * Note: for GICv5 the mimic the way that the num_pri_bits and
	694	+ * num_id_bits fields are used with GICv3:
	695	+ * - num_pri_bits stores the actual number of priority bits, whereas the
	696	+ * register field stores num_pri_bits - 1.
	697	+ * - num_id_bits stores the raw field value, which is 0b0000 for 16 bits
	698	+ * and 0b0001 for 24 bits.
	699	+ */
	700	+ p->regval = FIELD_PREP(ICC_IDR0_EL1_PRI_BITS, vcpu->arch.vgic_cpu.num_pri_bits - 1) \|
	701	+ FIELD_PREP(ICC_IDR0_EL1_ID_BITS, vcpu->arch.vgic_cpu.num_id_bits);
	702	+
	703	+ return true;
	704	+}
	705	+
	706	+static bool access_gicv5_iaffid(struct kvm_vcpu vcpu, struct sys_reg_params p,
	707	+ const struct sys_reg_desc *r)
	708	+{
	709	+ if (p->is_write)
	710	+ return undef_access(vcpu, p, r);
	711	+
	712	+ /*
	713	+ * For GICv5 VMs, the IAFFID value is the same as the VPE ID. The VPE ID
	714	+ * is the same as the VCPU's ID.
	715	+ */
	716	+ p->regval = FIELD_PREP(ICC_IAFFIDR_EL1_IAFFID, vcpu->vcpu_id);
	717	+
	718	+ return true;
	719	+}
	720	+
	721	+static bool access_gicv5_ppi_enabler(struct kvm_vcpu *vcpu,
	722	+ struct sys_reg_params *p,
	723	+ const struct sys_reg_desc *r)
	724	+{
	725	+ unsigned long *mask = vcpu->kvm->arch.vgic.gicv5_vm.vgic_ppi_mask;
	726	+ struct vgic_v5_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v5;
	727	+ int i;
	728	+
	729	+ /* We never expect to get here with a read! */
	730	+ if (WARN_ON_ONCE(!p->is_write))
	731	+ return undef_access(vcpu, p, r);
	732	+
	733	+ /*
	734	+ * If we're only handling architected PPIs and the guest writes to the
	735	+ * enable for the non-architected PPIs, we just return as there's
	736	+ * nothing to do at all. We don't even allocate the storage for them in
	737	+ * this case.
	738	+ */
	739	+ if (VGIC_V5_NR_PRIVATE_IRQS == 64 && p->Op2 % 2)
	740	+ return true;
	741	+
	742	+ /*
	743	+ * Merge the raw guest write into out bitmap at an offset of either 0 or
	744	+ * 64, then and it with our PPI mask.
	745	+ */
	746	+ bitmap_write(cpu_if->vgic_ppi_enabler, p->regval, 64 * (p->Op2 % 2), 64);
	747	+ bitmap_and(cpu_if->vgic_ppi_enabler, cpu_if->vgic_ppi_enabler, mask,
	748	+ VGIC_V5_NR_PRIVATE_IRQS);
	749	+
	750	+ /*
	751	+ * Sync the change in enable states to the vgic_irqs. We consider all
	752	+ * PPIs as we don't expose many to the guest.
	753	+ */
	754	+ for_each_set_bit(i, mask, VGIC_V5_NR_PRIVATE_IRQS) {
	755	+ u32 intid = vgic_v5_make_ppi(i);
	756	+ struct vgic_irq *irq;
	757	+
	758	+ irq = vgic_get_vcpu_irq(vcpu, intid);
	759	+
	760	+ scoped_guard(raw_spinlock_irqsave, &irq->irq_lock)
	761	+ irq->enabled = test_bit(i, cpu_if->vgic_ppi_enabler);
	762	+
	763	+ vgic_put_irq(vcpu->kvm, irq);
	764	+ }
	765	+
	766	+ return true;
	767	+}
	768	+
684	769	static bool trap_raz_wi(struct kvm_vcpu *vcpu,
685	770	struct sys_reg_params *p,
686	771	const struct sys_reg_desc *r)
@@ -1758,6 +1843,7 @@ static u8 pmuver_to_perfmon(u8 pmuver) · 1071 unmodified lines
1758	1843
1759	1844	static u64 sanitise_id_aa64pfr0_el1(const struct kvm_vcpu *vcpu, u64 val);
1760	1845	static u64 sanitise_id_aa64pfr1_el1(const struct kvm_vcpu *vcpu, u64 val);
	1846	+static u64 sanitise_id_aa64pfr2_el1(const struct kvm_vcpu *vcpu, u64 val);
1761	1847	static u64 sanitise_id_aa64dfr0_el1(const struct kvm_vcpu *vcpu, u64 val);
1762	1848
1763	1849	/* Read a sanitised cpufeature ID register by sys_reg_desc */
@@ -1783,10 +1869,7 @@ static u64 __kvm_read_sanitised_id_reg(const struct kvm_vcpu *vcpu, · 19 unmodified lines
1783	1869	val = sanitise_id_aa64pfr1_el1(vcpu, val);
1784	1870	break;
1785	1871	case SYS_ID_AA64PFR2_EL1:
1786		− val &= ID_AA64PFR2_EL1_FPMR \|
1787		− (kvm_has_mte(vcpu->kvm) ?
1788		− ID_AA64PFR2_EL1_MTEFAR \| ID_AA64PFR2_EL1_MTESTOREONLY :
1789		− 0);
	1872	+ val = sanitise_id_aa64pfr2_el1(vcpu, val);
1790	1873	break;
1791	1874	case SYS_ID_AA64ISAR1_EL1:
1792	1875	if (!vcpu_has_ptrauth(vcpu))
@@ -1985,7 +2068,7 @@ static u64 sanitise_id_aa64pfr0_el1(const struct kvm_vcpu *vcpu, u64 val) · 192 unmodified lines
1985	2068	val \|= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, CSV3, IMP);
1986	2069	}
1987	2070
1988		− if (vgic_is_v3(vcpu->kvm)) {
	2071	+ if (vgic_host_has_gicv3()) {
1989	2072	val &= ~ID_AA64PFR0_EL1_GIC_MASK;
1990	2073	val \|= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, GIC, IMP);
1991	2074	}
@@ -2027,6 +2110,23 @@ static u64 sanitise_id_aa64pfr1_el1(const struct kvm_vcpu *vcpu, u64 val) · 35 unmodified lines
2027	2110	return val;
2028	2111	}
2029	2112
	2113	+static u64 sanitise_id_aa64pfr2_el1(const struct kvm_vcpu *vcpu, u64 val)
	2114	+{
	2115	+ val &= ID_AA64PFR2_EL1_FPMR \|
	2116	+ ID_AA64PFR2_EL1_MTEFAR \|
	2117	+ ID_AA64PFR2_EL1_MTESTOREONLY;
	2118	+
	2119	+ if (!kvm_has_mte(vcpu->kvm)) {
	2120	+ val &= ~ID_AA64PFR2_EL1_MTEFAR;
	2121	+ val &= ~ID_AA64PFR2_EL1_MTESTOREONLY;
	2122	+ }
	2123	+
	2124	+ if (vgic_host_has_gicv5())
	2125	+ val \|= SYS_FIELD_PREP_ENUM(ID_AA64PFR2_EL1, GCIE, IMP);
	2126	+
	2127	+ return val;
	2128	+}
	2129	+
2030	2130	static u64 sanitise_id_aa64dfr0_el1(const struct kvm_vcpu *vcpu, u64 val)
2031	2131	{
2032	2132	val = ID_REG_LIMIT_FIELD_ENUM(val, ID_AA64DFR0_EL1, DebugVer, V8P8);
@@ -2177,14 +2277,6 @@ static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, · 144 unmodified lines
2177	2277	(vcpu_has_nv(vcpu) && !FIELD_GET(ID_AA64PFR0_EL1_EL2, user_val)))
2178	2278	return -EINVAL;
2179	2279
2180		− /*
2181		− * If we are running on a GICv5 host and support FEAT_GCIE_LEGACY, then
2182		− * we support GICv3. Fail attempts to do anything but set that to IMP.
2183		− */
2184		− if (vgic_is_v3_compat(vcpu->kvm) &&
2185		− FIELD_GET(ID_AA64PFR0_EL1_GIC_MASK, user_val) != ID_AA64PFR0_EL1_GIC_IMP)
2186		− return -EINVAL;
2187		−
2188	2280	return set_id_reg(vcpu, rd, user_val);
2189	2281	}
2190	2282
@@ -2224,6 +2316,12 @@ static int set_id_aa64pfr1_el1(struct kvm_vcpu *vcpu, · 33 unmodified lines
2224	2316	return set_id_reg(vcpu, rd, user_val);
2225	2317	}
2226	2318
	2319	+static int set_id_aa64pfr2_el1(struct kvm_vcpu *vcpu,
	2320	+ const struct sys_reg_desc *rd, u64 user_val)
	2321	+{
	2322	+ return set_id_reg(vcpu, rd, user_val);
	2323	+}
	2324	+
2227	2325	/*
2228	2326	* Allow userspace to de-feature a stage-2 translation granule but prevent it
2229	2327	* from claiming the impossible.
@@ -3205,10 +3303,11 @@ static const struct sys_reg_desc sys_reg_descs[] = { · 975 unmodified lines
3205	3303	ID_AA64PFR1_EL1_RES0 \|
3206	3304	ID_AA64PFR1_EL1_MPAM_frac \|
3207	3305	ID_AA64PFR1_EL1_MTE)),
3208		− ID_WRITABLE(ID_AA64PFR2_EL1,
3209		− ID_AA64PFR2_EL1_FPMR \|
3210		− ID_AA64PFR2_EL1_MTEFAR \|
3211		− ID_AA64PFR2_EL1_MTESTOREONLY),
	3306	+ ID_FILTERED(ID_AA64PFR2_EL1, id_aa64pfr2_el1,
	3307	+ ~(ID_AA64PFR2_EL1_FPMR \|
	3308	+ ID_AA64PFR2_EL1_MTEFAR \|
	3309	+ ID_AA64PFR2_EL1_MTESTOREONLY \|
	3310	+ ID_AA64PFR2_EL1_GCIE)),
3212	3311	ID_UNALLOCATED(4,3),
3213	3312	ID_WRITABLE(ID_AA64ZFR0_EL1, ~ID_AA64ZFR0_EL1_RES0),
3214	3313	ID_HIDDEN(ID_AA64SMFR0_EL1),
@@ -3391,6 +3490,10 @@ static const struct sys_reg_desc sys_reg_descs[] = { · 176 unmodified lines
3391	3490	{ SYS_DESC(SYS_ICC_AP1R1_EL1), undef_access },
3392	3491	{ SYS_DESC(SYS_ICC_AP1R2_EL1), undef_access },
3393	3492	{ SYS_DESC(SYS_ICC_AP1R3_EL1), undef_access },
	3493	+ { SYS_DESC(SYS_ICC_IDR0_EL1), access_gicv5_idr0 },
	3494	+ { SYS_DESC(SYS_ICC_IAFFIDR_EL1), access_gicv5_iaffid },
	3495	+ { SYS_DESC(SYS_ICC_PPI_ENABLER0_EL1), access_gicv5_ppi_enabler },
	3496	+ { SYS_DESC(SYS_ICC_PPI_ENABLER1_EL1), access_gicv5_ppi_enabler },
3394	3497	{ SYS_DESC(SYS_ICC_DIR_EL1), access_gic_dir },
3395	3498	{ SYS_DESC(SYS_ICC_RPR_EL1), undef_access },
3396	3499	{ SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi },
@@ -5647,6 +5750,8 @@ void kvm_calculate_traps(struct kvm_vcpu *vcpu) · 2250 unmodified lines
5647	5750	compute_fgu(kvm, HFGRTR2_GROUP);
5648	5751	compute_fgu(kvm, HFGITR2_GROUP);
5649	5752	compute_fgu(kvm, HDFGRTR2_GROUP);
	5753	+ compute_fgu(kvm, ICH_HFGRTR_GROUP);
	5754	+ compute_fgu(kvm, ICH_HFGITR_GROUP);
5650	5755
5651	5756	set_bit(KVM_ARCH_FLAG_FGU_INITIALIZED, &kvm->arch.flags);
5652	5757	out:
@@ -5667,17 +5772,52 @@ int kvm_finalize_sys_regs(struct kvm_vcpu *vcpu) · 14 unmodified lines
5667	5772
5668	5773	guard(mutex)(&kvm->arch.config_lock);
5669	5774
	5775	+ if (kvm_vm_has_ran_once(kvm))
	5776	+ return 0;
	5777	+
5670	5778	/*
5671	5779	* This hacks into the ID registers, so only perform it when the
5672	5780	* first vcpu runs, or the kvm_set_vm_id_reg() helper will scream.
5673	5781	*/
5674		− if (!irqchip_in_kernel(kvm) && !kvm_vm_has_ran_once(kvm)) {
	5782	+ if (!irqchip_in_kernel(kvm)) {
5675	5783	u64 val;
5676	5784
5677	5785	val = kvm_read_vm_id_reg(kvm, SYS_ID_AA64PFR0_EL1) & ~ID_AA64PFR0_EL1_GIC;
5678	5786	kvm_set_vm_id_reg(kvm, SYS_ID_AA64PFR0_EL1, val);
	5787	+ val = kvm_read_vm_id_reg(kvm, SYS_ID_AA64PFR2_EL1) & ~ID_AA64PFR2_EL1_GCIE;
	5788	+ kvm_set_vm_id_reg(kvm, SYS_ID_AA64PFR2_EL1, val);
5679	5789	val = kvm_read_vm_id_reg(kvm, SYS_ID_PFR1_EL1) & ~ID_PFR1_EL1_GIC;
5680	5790	kvm_set_vm_id_reg(kvm, SYS_ID_PFR1_EL1, val);
	5791	+ } else {
	5792	+ /*
	5793	+ * Certain userspace software - QEMU - samples the system
	5794	+ * register state without creating an irqchip, then blindly
	5795	+ * restores the state prior to running the final guest. This
	5796	+ * means that it restores the virtualization & emulation
	5797	+ * capabilities of the host system, rather than something that
	5798	+ * reflects the final guest state. Moreover, it checks that the
	5799	+ * state was "correctly" restored (i.e., verbatim), bailing if
	5800	+ * it isn't, so masking off invalid state isn't an option.
	5801	+ *
	5802	+ * On GICv5 hardware that supports FEAT_GCIE_LEGACY we can run
	5803	+ * both GICv3- and GICv5-based guests. Therefore, we initially
	5804	+ * present both ID_AA64PFR0.GIC and ID_AA64PFR2.GCIE as IMP to
	5805	+ * reflect that userspace can create EITHER a vGICv3 or a
	5806	+ * vGICv5. This is an architecturally invalid combination, of
	5807	+ * course. Once an in-kernel GIC is created, the sysreg state is
	5808	+ * updated to reflect the actual, valid configuration.
	5809	+ *
	5810	+ * Setting both the GIC and GCIE features to IMP unsurprisingly
	5811	+ * results in guests falling over, and hence we need to fix up
	5812	+ * this mess in KVM. Before running for the first time we yet
	5813	+ * again ensure that the GIC and GCIE fields accurately reflect
	5814	+ * the actual hardware the guest should see.
	5815	+ *
	5816	+ * This hack allows legacy QEMU-based GICv3 guests to run
	5817	+ * unmodified on compatible GICv5 hosts, and avoids the inverse
	5818	+ * problem for GICv5-based guests in the future.
	5819	+ */
	5820	+ kvm_vgic_finalize_idregs(kvm);
5681	5821	}
5682	5822
5683	5823	if (vcpu_has_nv(vcpu)) {

arch/arm64/kvm/vgic/vgic-init.c+150−64

@@ -66,12 +66,11 @@ static int vgic_allocate_private_irqs_locked(struct kvm_vcpu *vcpu, u32 type); · 65 unmodified lines
66	66	* or through the generic KVM_CREATE_DEVICE API ioctl.
67	67	* irqchip_in_kernel() tells you if this function succeeded or not.
68	68	* @kvm: kvm struct pointer
69		− * @type: KVM_DEV_TYPE_ARM_VGIC_V[23]
	69	+ * @type: KVM_DEV_TYPE_ARM_VGIC_V[235]
70	70	*/
71	71	int kvm_vgic_create(struct kvm *kvm, u32 type)
72	72	{
73	73	struct kvm_vcpu *vcpu;
74		− u64 aa64pfr0, pfr1;
75	74	unsigned long i;
76	75	int ret;
77	76
@@ -132,8 +131,11 @@ int kvm_vgic_create(struct kvm *kvm, u32 type) · 54 unmodified lines
132	131
133	132	if (type == KVM_DEV_TYPE_ARM_VGIC_V2)
134	133	kvm->max_vcpus = VGIC_V2_MAX_CPUS;
135		− else
	134	+ else if (type == KVM_DEV_TYPE_ARM_VGIC_V3)
136	135	kvm->max_vcpus = VGIC_V3_MAX_CPUS;
	136	+ else if (type == KVM_DEV_TYPE_ARM_VGIC_V5)
	137	+ kvm->max_vcpus = min(VGIC_V5_MAX_CPUS,
	138	+ kvm_vgic_global_state.max_gic_vcpus);
137	139
138	140	if (atomic_read(&kvm->online_vcpus) > kvm->max_vcpus) {
139	141	ret = -E2BIG;
@@ -145,19 +147,11 @@ int kvm_vgic_create(struct kvm *kvm, u32 type) · 5 unmodified lines
145	147	kvm->arch.vgic.implementation_rev = KVM_VGIC_IMP_REV_LATEST;
146	148	kvm->arch.vgic.vgic_dist_base = VGIC_ADDR_UNDEF;
147	149
148		− aa64pfr0 = kvm_read_vm_id_reg(kvm, SYS_ID_AA64PFR0_EL1) & ~ID_AA64PFR0_EL1_GIC;
149		− pfr1 = kvm_read_vm_id_reg(kvm, SYS_ID_PFR1_EL1) & ~ID_PFR1_EL1_GIC;
150		−
151		− if (type == KVM_DEV_TYPE_ARM_VGIC_V2) {
152		− kvm->arch.vgic.vgic_cpu_base = VGIC_ADDR_UNDEF;
153		− } else {
154		− INIT_LIST_HEAD(&kvm->arch.vgic.rd_regions);
155		− aa64pfr0 \|= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, GIC, IMP);
156		− pfr1 \|= SYS_FIELD_PREP_ENUM(ID_PFR1_EL1, GIC, GICv3);
157		− }
158		−
159		− kvm_set_vm_id_reg(kvm, SYS_ID_AA64PFR0_EL1, aa64pfr0);
160		− kvm_set_vm_id_reg(kvm, SYS_ID_PFR1_EL1, pfr1);
	150	+ /*
	151	+ * We've now created the GIC. Update the system register state
	152	+ * to accurately reflect what we've created.
	153	+ */
	154	+ kvm_vgic_finalize_idregs(kvm);
161	155
162	156	kvm_for_each_vcpu(i, vcpu, kvm) {
163	157	ret = vgic_allocate_private_irqs_locked(vcpu, type);
@@ -179,6 +173,15 @@ int kvm_vgic_create(struct kvm *kvm, u32 type) · 15 unmodified lines
179	173	if (type == KVM_DEV_TYPE_ARM_VGIC_V3)
180	174	kvm->arch.vgic.nassgicap = system_supports_direct_sgis();
181	175
	176	+ /*
	177	+ * We now know that we have a GICv5. The Arch Timer PPI interrupts may
	178	+ * have been initialised at this stage, but will have done so assuming
	179	+ * that we have an older GIC, meaning that the IntIDs won't be
	180	+ * correct. We init them again, and this time they will be correct.
	181	+ */
	182	+ if (type == KVM_DEV_TYPE_ARM_VGIC_V5)
	183	+ kvm_timer_init_vm(kvm);
	184	+
182	185	out_unlock:
183	186	mutex_unlock(&kvm->arch.config_lock);
184	187	kvm_unlock_all_vcpus(kvm);
@@ -259,9 +262,65 @@ int kvm_vgic_vcpu_nv_init(struct kvm_vcpu *vcpu) · 74 unmodified lines
259	262	return ret;
260	263	}
261	264
	265	+static void vgic_allocate_private_irq(struct kvm_vcpu *vcpu, int i, u32 type)
	266	+{
	267	+ struct vgic_irq *irq = &vcpu->arch.vgic_cpu.private_irqs[i];
	268	+
	269	+ INIT_LIST_HEAD(&irq->ap_list);
	270	+ raw_spin_lock_init(&irq->irq_lock);
	271	+ irq->vcpu = NULL;
	272	+ irq->target_vcpu = vcpu;
	273	+ refcount_set(&irq->refcount, 0);
	274	+
	275	+ irq->intid = i;
	276	+ if (vgic_irq_is_sgi(i)) {
	277	+ /* SGIs */
	278	+ irq->enabled = 1;
	279	+ irq->config = VGIC_CONFIG_EDGE;
	280	+ } else {
	281	+ /* PPIs */
	282	+ irq->config = VGIC_CONFIG_LEVEL;
	283	+ }
	284	+
	285	+ switch (type) {
	286	+ case KVM_DEV_TYPE_ARM_VGIC_V3:
	287	+ irq->group = 1;
	288	+ irq->mpidr = kvm_vcpu_get_mpidr_aff(vcpu);
	289	+ break;
	290	+ case KVM_DEV_TYPE_ARM_VGIC_V2:
	291	+ irq->group = 0;
	292	+ irq->targets = BIT(vcpu->vcpu_id);
	293	+ break;
	294	+ }
	295	+}
	296	+
	297	+static void vgic_v5_allocate_private_irq(struct kvm_vcpu *vcpu, int i, u32 type)
	298	+{
	299	+ struct vgic_irq *irq = &vcpu->arch.vgic_cpu.private_irqs[i];
	300	+ u32 intid = vgic_v5_make_ppi(i);
	301	+
	302	+ INIT_LIST_HEAD(&irq->ap_list);
	303	+ raw_spin_lock_init(&irq->irq_lock);
	304	+ irq->vcpu = NULL;
	305	+ irq->target_vcpu = vcpu;
	306	+ refcount_set(&irq->refcount, 0);
	307	+
	308	+ irq->intid = intid;
	309	+
	310	+ /* The only Edge architected PPI is the SW_PPI */
	311	+ if (i == GICV5_ARCH_PPI_SW_PPI)
	312	+ irq->config = VGIC_CONFIG_EDGE;
	313	+ else
	314	+ irq->config = VGIC_CONFIG_LEVEL;
	315	+
	316	+ /* Register the GICv5-specific PPI ops */
	317	+ vgic_v5_set_ppi_ops(vcpu, intid);
	318	+}
	319	+
262	320	static int vgic_allocate_private_irqs_locked(struct kvm_vcpu *vcpu, u32 type)
263	321	{
264	322	struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
	323	+ u32 num_private_irqs;
265	324	int i;
266	325
267	326	lockdep_assert_held(&vcpu->kvm->arch.config_lock);
@@ -269,8 +328,13 @@ static int vgic_allocate_private_irqs_locked(struct kvm_vcpu *vcpu, u32 type) · 1 unmodified line
269	328	if (vgic_cpu->private_irqs)
270	329	return 0;
271	330
	331	+ if (vgic_is_v5(vcpu->kvm))
	332	+ num_private_irqs = VGIC_V5_NR_PRIVATE_IRQS;
	333	+ else
	334	+ num_private_irqs = VGIC_NR_PRIVATE_IRQS;
	335	+
272	336	vgic_cpu->private_irqs = kzalloc_objs(struct vgic_irq,
273		− VGIC_NR_PRIVATE_IRQS,
	337	+ num_private_irqs,
274	338	GFP_KERNEL_ACCOUNT);
275	339
276	340	if (!vgic_cpu->private_irqs)
@@ -280,34 +344,11 @@ static int vgic_allocate_private_irqs_locked(struct kvm_vcpu *vcpu, u32 type) · 3 unmodified lines
280	344	* Enable and configure all SGIs to be edge-triggered and
281	345	* configure all PPIs as level-triggered.
282	346	*/
283		− for (i = 0; i < VGIC_NR_PRIVATE_IRQS; i++) {
284		− struct vgic_irq *irq = &vgic_cpu->private_irqs[i];
285		−
286		− INIT_LIST_HEAD(&irq->ap_list);
287		− raw_spin_lock_init(&irq->irq_lock);
288		− irq->intid = i;
289		− irq->vcpu = NULL;
290		− irq->target_vcpu = vcpu;
291		− refcount_set(&irq->refcount, 0);
292		− if (vgic_irq_is_sgi(i)) {
293		− /* SGIs */
294		− irq->enabled = 1;
295		− irq->config = VGIC_CONFIG_EDGE;
296		− } else {
297		− /* PPIs */
298		− irq->config = VGIC_CONFIG_LEVEL;
299		− }
300		−
301		− switch (type) {
302		− case KVM_DEV_TYPE_ARM_VGIC_V3:
303		− irq->group = 1;
304		− irq->mpidr = kvm_vcpu_get_mpidr_aff(vcpu);
305		− break;
306		− case KVM_DEV_TYPE_ARM_VGIC_V2:
307		− irq->group = 0;
308		− irq->targets = BIT(vcpu->vcpu_id);
309		− break;
310		− }
	347	+ for (i = 0; i < num_private_irqs; i++) {
	348	+ if (vgic_is_v5(vcpu->kvm))
	349	+ vgic_v5_allocate_private_irq(vcpu, i, type);
	350	+ else
	351	+ vgic_allocate_private_irq(vcpu, i, type);
311	352	}
312	353
313	354	return 0;
@@ -366,7 +407,11 @@ int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu) · 52 unmodified lines
366	407
367	408	static void kvm_vgic_vcpu_reset(struct kvm_vcpu *vcpu)
368	409	{
369		− if (kvm_vgic_global_state.type == VGIC_V2)
	410	+ const struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
	411	+
	412	+ if (dist->vgic_model == KVM_DEV_TYPE_ARM_VGIC_V5)
	413	+ vgic_v5_reset(vcpu);
	414	+ else if (kvm_vgic_global_state.type == VGIC_V2)
370	415	vgic_v2_reset(vcpu);
371	416	else
372	417	vgic_v3_reset(vcpu);
@@ -397,22 +442,28 @@ int vgic_init(struct kvm *kvm) · 24 unmodified lines
397	442	if (kvm->created_vcpus != atomic_read(&kvm->online_vcpus))
398	443	return -EBUSY;
399	444
400		− /* freeze the number of spis */
401		− if (!dist->nr_spis)
402		− dist->nr_spis = VGIC_NR_IRQS_LEGACY - VGIC_NR_PRIVATE_IRQS;
	445	+ if (!vgic_is_v5(kvm)) {
	446	+ /* freeze the number of spis */
	447	+ if (!dist->nr_spis)
	448	+ dist->nr_spis = VGIC_NR_IRQS_LEGACY - VGIC_NR_PRIVATE_IRQS;
403	449
404		− ret = kvm_vgic_dist_init(kvm, dist->nr_spis);
405		− if (ret)
406		− goto out;
	450	+ ret = kvm_vgic_dist_init(kvm, dist->nr_spis);
	451	+ if (ret)
	452	+ return ret;
407	453
408		− /*
409		− * Ensure vPEs are allocated if direct IRQ injection (e.g. vSGIs,
410		− * vLPIs) is supported.
411		− */
412		− if (vgic_supports_direct_irqs(kvm)) {
413		− ret = vgic_v4_init(kvm);
	454	+ /*
	455	+ * Ensure vPEs are allocated if direct IRQ injection (e.g. vSGIs,
	456	+ * vLPIs) is supported.
	457	+ */
	458	+ if (vgic_supports_direct_irqs(kvm)) {
	459	+ ret = vgic_v4_init(kvm);
	460	+ if (ret)
	461	+ return ret;
	462	+ }
	463	+ } else {
	464	+ ret = vgic_v5_init(kvm);
414	465	if (ret)
415		− goto out;
	466	+ return ret;
416	467	}
417	468
418	469	kvm_for_each_vcpu(idx, vcpu, kvm)
@@ -420,12 +471,12 @@ int vgic_init(struct kvm *kvm) · 1 unmodified line
420	471
421	472	ret = kvm_vgic_setup_default_irq_routing(kvm);
422	473	if (ret)
423		− goto out;
	474	+ return ret;
424	475
425	476	vgic_debug_init(kvm);
426	477	dist->initialized = true;
427		−out:
428		− return ret;
	478	+
	479	+ return 0;
429	480	}
430	481
431	482	static void kvm_vgic_dist_destroy(struct kvm *kvm)
@@ -569,6 +620,7 @@ int vgic_lazy_init(struct kvm *kvm) · 137 unmodified lines
569	620	int kvm_vgic_map_resources(struct kvm *kvm)
570	621	{
571	622	struct vgic_dist *dist = &kvm->arch.vgic;
	623	+ bool needs_dist = true;
572	624	enum vgic_type type;
573	625	gpa_t dist_base;
574	626	int ret = 0;
@@ -587,12 +639,16 @@ int kvm_vgic_map_resources(struct kvm *kvm) · 12 unmodified lines
587	639	if (dist->vgic_model == KVM_DEV_TYPE_ARM_VGIC_V2) {
588	640	ret = vgic_v2_map_resources(kvm);
589	641	type = VGIC_V2;
590		− } else {
	642	+ } else if (dist->vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) {
591	643	ret = vgic_v3_map_resources(kvm);
592	644	type = VGIC_V3;
	645	+ } else {
	646	+ ret = vgic_v5_map_resources(kvm);
	647	+ type = VGIC_V5;
	648	+ needs_dist = false;
593	649	}
594	650
595		− if (ret)
	651	+ if (ret \|\| !needs_dist)
596	652	goto out;
597	653
598	654	dist_base = dist->vgic_dist_base;
@@ -617,6 +673,36 @@ out_slots: · 18 unmodified lines
617	673	return ret;
618	674	}
619	675
	676	+void kvm_vgic_finalize_idregs(struct kvm *kvm)
	677	+{
	678	+ u32 type = kvm->arch.vgic.vgic_model;
	679	+ u64 aa64pfr0, aa64pfr2, pfr1;
	680	+
	681	+ aa64pfr0 = kvm_read_vm_id_reg(kvm, SYS_ID_AA64PFR0_EL1) & ~ID_AA64PFR0_EL1_GIC;
	682	+ aa64pfr2 = kvm_read_vm_id_reg(kvm, SYS_ID_AA64PFR2_EL1) & ~ID_AA64PFR2_EL1_GCIE;
	683	+ pfr1 = kvm_read_vm_id_reg(kvm, SYS_ID_PFR1_EL1) & ~ID_PFR1_EL1_GIC;
	684	+
	685	+ switch (type) {
	686	+ case KVM_DEV_TYPE_ARM_VGIC_V2:
	687	+ kvm->arch.vgic.vgic_cpu_base = VGIC_ADDR_UNDEF;
	688	+ break;
	689	+ case KVM_DEV_TYPE_ARM_VGIC_V3:
	690	+ INIT_LIST_HEAD(&kvm->arch.vgic.rd_regions);
	691	+ aa64pfr0 \|= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, GIC, IMP);
	692	+ pfr1 \|= SYS_FIELD_PREP_ENUM(ID_PFR1_EL1, GIC, GICv3);
	693	+ break;
	694	+ case KVM_DEV_TYPE_ARM_VGIC_V5:
	695	+ aa64pfr2 \|= SYS_FIELD_PREP_ENUM(ID_AA64PFR2_EL1, GCIE, IMP);
	696	+ break;
	697	+ default:
	698	+ WARN_ONCE(1, "Unknown VGIC type!!!\n");
	699	+ }
	700	+
	701	+ kvm_set_vm_id_reg(kvm, SYS_ID_AA64PFR0_EL1, aa64pfr0);
	702	+ kvm_set_vm_id_reg(kvm, SYS_ID_AA64PFR2_EL1, aa64pfr2);
	703	+ kvm_set_vm_id_reg(kvm, SYS_ID_PFR1_EL1, pfr1);
	704	+}
	705	+
620	706	/* GENERIC PROBE */
621	707
622	708	void kvm_vgic_cpu_up(void)

arch/arm64/kvm/vgic/vgic-kvm-device.c+106−1

@@ -336,6 +336,10 @@ int kvm_register_vgic_device(unsigned long type) · 335 unmodified lines
336	336	break;
337	337	ret = kvm_vgic_register_its_device();
338	338	break;
	339	+ case KVM_DEV_TYPE_ARM_VGIC_V5:
	340	+ ret = kvm_register_device_ops(&kvm_arm_vgic_v5_ops,
	341	+ KVM_DEV_TYPE_ARM_VGIC_V5);
	342	+ break;
339	343	}
340	344
341	345	return ret;
@@ -639,7 +643,7 @@ static int vgic_v3_set_attr(struct kvm_device *dev, · 297 unmodified lines
639	643	if (vgic_initialized(dev->kvm))
640	644	return -EBUSY;
641	645
642		− if (!irq_is_ppi(val))
	646	+ if (!irq_is_ppi(dev->kvm, val))
643	647	return -EINVAL;
644	648
645	649	dev->kvm->arch.vgic.mi_intid = val;
@@ -715,3 +719,104 @@ struct kvm_device_ops kvm_arm_vgic_v3_ops = { · 69 unmodified lines
715	719	.get_attr = vgic_v3_get_attr,
716	720	.has_attr = vgic_v3_has_attr,
717	721	};
	722	+
	723	+static int vgic_v5_get_userspace_ppis(struct kvm_device *dev,
	724	+ struct kvm_device_attr *attr)
	725	+{
	726	+ struct vgic_v5_vm *gicv5_vm = &dev->kvm->arch.vgic.gicv5_vm;
	727	+ u64 __user uaddr = (u64 __user )(long)attr->addr;
	728	+ int ret;
	729	+
	730	+ guard(mutex)(&dev->kvm->arch.config_lock);
	731	+
	732	+ /*
	733	+ * We either support 64 or 128 PPIs. In the former case, we need to
	734	+ * return 0s for the second 64 bits as we have no storage backing those.
	735	+ */
	736	+ ret = put_user(bitmap_read(gicv5_vm->userspace_ppis, 0, 64), uaddr);
	737	+ if (ret)
	738	+ return ret;
	739	+ uaddr++;
	740	+
	741	+ if (VGIC_V5_NR_PRIVATE_IRQS == 128)
	742	+ ret = put_user(bitmap_read(gicv5_vm->userspace_ppis, 64, 128), uaddr);
	743	+ else
	744	+ ret = put_user(0, uaddr);
	745	+
	746	+ return ret;
	747	+}
	748	+
	749	+static int vgic_v5_set_attr(struct kvm_device *dev,
	750	+ struct kvm_device_attr *attr)
	751	+{
	752	+ switch (attr->group) {
	753	+ case KVM_DEV_ARM_VGIC_GRP_ADDR:
	754	+ case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS:
	755	+ case KVM_DEV_ARM_VGIC_GRP_NR_IRQS:
	756	+ return -ENXIO;
	757	+ case KVM_DEV_ARM_VGIC_GRP_CTRL:
	758	+ switch (attr->attr) {
	759	+ case KVM_DEV_ARM_VGIC_CTRL_INIT:
	760	+ return vgic_set_common_attr(dev, attr);
	761	+ case KVM_DEV_ARM_VGIC_USERSPACE_PPIS:
	762	+ default:
	763	+ return -ENXIO;
	764	+ }
	765	+ default:
	766	+ return -ENXIO;
	767	+ }
	768	+
	769	+}
	770	+
	771	+static int vgic_v5_get_attr(struct kvm_device *dev,
	772	+ struct kvm_device_attr *attr)
	773	+{
	774	+ switch (attr->group) {
	775	+ case KVM_DEV_ARM_VGIC_GRP_ADDR:
	776	+ case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS:
	777	+ case KVM_DEV_ARM_VGIC_GRP_NR_IRQS:
	778	+ return -ENXIO;
	779	+ case KVM_DEV_ARM_VGIC_GRP_CTRL:
	780	+ switch (attr->attr) {
	781	+ case KVM_DEV_ARM_VGIC_CTRL_INIT:
	782	+ return vgic_get_common_attr(dev, attr);
	783	+ case KVM_DEV_ARM_VGIC_USERSPACE_PPIS:
	784	+ return vgic_v5_get_userspace_ppis(dev, attr);
	785	+ default:
	786	+ return -ENXIO;
	787	+ }
	788	+ default:
	789	+ return -ENXIO;
	790	+ }
	791	+}
	792	+
	793	+static int vgic_v5_has_attr(struct kvm_device *dev,
	794	+ struct kvm_device_attr *attr)
	795	+{
	796	+ switch (attr->group) {
	797	+ case KVM_DEV_ARM_VGIC_GRP_ADDR:
	798	+ case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS:
	799	+ case KVM_DEV_ARM_VGIC_GRP_NR_IRQS:
	800	+ return -ENXIO;
	801	+ case KVM_DEV_ARM_VGIC_GRP_CTRL:
	802	+ switch (attr->attr) {
	803	+ case KVM_DEV_ARM_VGIC_CTRL_INIT:
	804	+ return 0;
	805	+ case KVM_DEV_ARM_VGIC_USERSPACE_PPIS:
	806	+ return 0;
	807	+ default:
	808	+ return -ENXIO;
	809	+ }
	810	+ default:
	811	+ return -ENXIO;
	812	+ }
	813	+}
	814	+
	815	+struct kvm_device_ops kvm_arm_vgic_v5_ops = {
	816	+ .name = "kvm-arm-vgic-v5",
	817	+ .create = vgic_create,
	818	+ .destroy = vgic_destroy,
	819	+ .set_attr = vgic_v5_set_attr,
	820	+ .get_attr = vgic_v5_get_attr,
	821	+ .has_attr = vgic_v5_has_attr,
	822	+};

arch/arm64/kvm/vgic/vgic-mmio.c+34−6

@@ -842,18 +842,46 @@ vgic_find_mmio_region(const struct vgic_register_region *regions, · 841 unmodified lines
842	842
843	843	void vgic_set_vmcr(struct kvm_vcpu vcpu, struct vgic_vmcr vmcr)
844	844	{
845		− if (kvm_vgic_global_state.type == VGIC_V2)
846		− vgic_v2_set_vmcr(vcpu, vmcr);
847		− else
	845	+ const struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
	846	+
	847	+ switch (dist->vgic_model) {
	848	+ case KVM_DEV_TYPE_ARM_VGIC_V5:
	849	+ vgic_v5_set_vmcr(vcpu, vmcr);
	850	+ break;
	851	+ case KVM_DEV_TYPE_ARM_VGIC_V3:
848	852	vgic_v3_set_vmcr(vcpu, vmcr);
	853	+ break;
	854	+ case KVM_DEV_TYPE_ARM_VGIC_V2:
	855	+ if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif))
	856	+ vgic_v3_set_vmcr(vcpu, vmcr);
	857	+ else
	858	+ vgic_v2_set_vmcr(vcpu, vmcr);
	859	+ break;
	860	+ default:
	861	+ BUG();
	862	+ }
849	863	}
850	864
851	865	void vgic_get_vmcr(struct kvm_vcpu vcpu, struct vgic_vmcr vmcr)
852	866	{
853		− if (kvm_vgic_global_state.type == VGIC_V2)
854		− vgic_v2_get_vmcr(vcpu, vmcr);
855		− else
	867	+ const struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
	868	+
	869	+ switch (dist->vgic_model) {
	870	+ case KVM_DEV_TYPE_ARM_VGIC_V5:
	871	+ vgic_v5_get_vmcr(vcpu, vmcr);
	872	+ break;
	873	+ case KVM_DEV_TYPE_ARM_VGIC_V3:
856	874	vgic_v3_get_vmcr(vcpu, vmcr);
	875	+ break;
	876	+ case KVM_DEV_TYPE_ARM_VGIC_V2:
	877	+ if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif))
	878	+ vgic_v3_get_vmcr(vcpu, vmcr);
	879	+ else
	880	+ vgic_v2_get_vmcr(vcpu, vmcr);
	881	+ break;
	882	+ default:
	883	+ BUG();
	884	+ }
857	885	}
858	886
859	887	/*

arch/arm64/kvm/vgic/vgic-v3.c+1−1

@@ -499,7 +499,7 @@ void vcpu_set_ich_hcr(struct kvm_vcpu *vcpu) · 498 unmodified lines
499	499	{
500	500	struct vgic_v3_cpu_if *vgic_v3 = &vcpu->arch.vgic_cpu.vgic_v3;
501	501
502		− if (!vgic_is_v3(vcpu->kvm))
	502	+ if (!vgic_host_has_gicv3())
503	503	return;
504	504
505	505	/* Hide GICv3 sysreg if necessary */

arch/arm64/kvm/vgic/vgic-v5.c+494−9

@@ -1,28 +1,52 @@
1	1	// SPDX-License-Identifier: GPL-2.0-only
	2	+/*
	3	+ * Copyright (C) 2025, 2026 Arm Ltd.
	4	+ */
2	5
3	6	#include <kvm/arm_vgic.h>
	7	+
	8	+#include <linux/bitops.h>
4	9	#include <linux/irqchip/arm-vgic-info.h>
5	10
6	11	#include "vgic.h"
7	12
	13	+static struct vgic_v5_ppi_caps ppi_caps;
	14	+
	15	+/*
	16	+ * Not all PPIs are guaranteed to be implemented for GICv5. Deterermine which
	17	+ * ones are, and generate a mask.
	18	+ */
	19	+static void vgic_v5_get_implemented_ppis(void)
	20	+{
	21	+ if (!cpus_have_final_cap(ARM64_HAS_GICV5_CPUIF))
	22	+ return;
	23	+
	24	+ /*
	25	+ * If we have KVM, we have EL2, which means that we have support for the
	26	+ * EL1 and EL2 Physical & Virtual timers.
	27	+ */
	28	+ __assign_bit(GICV5_ARCH_PPI_CNTHP, ppi_caps.impl_ppi_mask, 1);
	29	+ __assign_bit(GICV5_ARCH_PPI_CNTV, ppi_caps.impl_ppi_mask, 1);
	30	+ __assign_bit(GICV5_ARCH_PPI_CNTHV, ppi_caps.impl_ppi_mask, 1);
	31	+ __assign_bit(GICV5_ARCH_PPI_CNTP, ppi_caps.impl_ppi_mask, 1);
	32	+
	33	+ /* The SW_PPI should be available */
	34	+ __assign_bit(GICV5_ARCH_PPI_SW_PPI, ppi_caps.impl_ppi_mask, 1);
	35	+
	36	+ /* The PMUIRQ is available if we have the PMU */
	37	+ __assign_bit(GICV5_ARCH_PPI_PMUIRQ, ppi_caps.impl_ppi_mask, system_supports_pmuv3());
	38	+}
	39	+
8	40	/*
9	41	* Probe for a vGICv5 compatible interrupt controller, returning 0 on success.
10		− * Currently only supports GICv3-based VMs on a GICv5 host, and hence only
11		− * registers a VGIC_V3 device.
12	42	*/
13	43	int vgic_v5_probe(const struct gic_kvm_info *info)
14	44	{
	45	+ bool v5_registered = false;
15	46	u64 ich_vtr_el2;
16	47	int ret;
17	48
18		− if (!cpus_have_final_cap(ARM64_HAS_GICV5_LEGACY))
19		− return -ENODEV;
20		−
21	49	kvm_vgic_global_state.type = VGIC_V5;
22		− kvm_vgic_global_state.has_gcie_v3_compat = true;
23		−
24		− /* We only support v3 compat mode - use vGICv3 limits */
25		− kvm_vgic_global_state.max_gic_vcpus = VGIC_V3_MAX_CPUS;
26	50
27	51	kvm_vgic_global_state.vcpu_base = 0;
28	52	kvm_vgic_global_state.vctrl_base = NULL;
@@ -30,6 +54,38 @@ int vgic_v5_probe(const struct gic_kvm_info *info) · 1 unmodified line
30	54	kvm_vgic_global_state.has_gicv4 = false;
31	55	kvm_vgic_global_state.has_gicv4_1 = false;
32	56
	57	+ /*
	58	+ * GICv5 is currently not supported in Protected mode. Skip the
	59	+ * registration of GICv5 completely to make sure no guests can create a
	60	+ * GICv5-based guest.
	61	+ */
	62	+ if (is_protected_kvm_enabled()) {
	63	+ kvm_info("GICv5-based guests are not supported with pKVM\n");
	64	+ goto skip_v5;
	65	+ }
	66	+
	67	+ kvm_vgic_global_state.max_gic_vcpus = VGIC_V5_MAX_CPUS;
	68	+
	69	+ vgic_v5_get_implemented_ppis();
	70	+
	71	+ ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V5);
	72	+ if (ret) {
	73	+ kvm_err("Cannot register GICv5 KVM device.\n");
	74	+ goto skip_v5;
	75	+ }
	76	+
	77	+ v5_registered = true;
	78	+ kvm_info("GCIE system register CPU interface\n");
	79	+
	80	+skip_v5:
	81	+ /* If we don't support the GICv3 compat mode we're done. */
	82	+ if (!cpus_have_final_cap(ARM64_HAS_GICV5_LEGACY)) {
	83	+ if (!v5_registered)
	84	+ return -ENODEV;
	85	+ return 0;
	86	+ }
	87	+
	88	+ kvm_vgic_global_state.has_gcie_v3_compat = true;
33	89	ich_vtr_el2 = kvm_call_hyp_ret(__vgic_v3_get_gic_config);
34	90	kvm_vgic_global_state.ich_vtr_el2 = (u32)ich_vtr_el2;
35	91
@@ -45,6 +101,10 @@ int vgic_v5_probe(const struct gic_kvm_info *info) · 9 unmodified lines
45	101	return ret;
46	102	}
47	103
	104	+ /* We potentially limit the max VCPUs further than we need to here */
	105	+ kvm_vgic_global_state.max_gic_vcpus = min(VGIC_V3_MAX_CPUS,
	106	+ VGIC_V5_MAX_CPUS);
	107	+
48	108	static_branch_enable(&kvm_vgic_global_state.gicv3_cpuif);
49	109	kvm_info("GCIE legacy system register CPU interface\n");
50	110
@@ -52,3 +112,428 @@ int vgic_v5_probe(const struct gic_kvm_info *info) · 1 unmodified line
52	112
53	113	return 0;
54	114	}
	115	+
	116	+void vgic_v5_reset(struct kvm_vcpu *vcpu)
	117	+{
	118	+ /*
	119	+ * We always present 16-bits of ID space to the guest, irrespective of
	120	+ * the host allowing more.
	121	+ */
	122	+ vcpu->arch.vgic_cpu.num_id_bits = ICC_IDR0_EL1_ID_BITS_16BITS;
	123	+
	124	+ /*
	125	+ * The GICv5 architeture only supports 5-bits of priority in the
	126	+ * CPUIF (but potentially fewer in the IRS).
	127	+ */
	128	+ vcpu->arch.vgic_cpu.num_pri_bits = 5;
	129	+}
	130	+
	131	+int vgic_v5_init(struct kvm *kvm)
	132	+{
	133	+ struct kvm_vcpu *vcpu;
	134	+ unsigned long idx;
	135	+
	136	+ if (vgic_initialized(kvm))
	137	+ return 0;
	138	+
	139	+ kvm_for_each_vcpu(idx, vcpu, kvm) {
	140	+ if (vcpu_has_nv(vcpu)) {
	141	+ kvm_err("Nested GICv5 VMs are currently unsupported\n");
	142	+ return -EINVAL;
	143	+ }
	144	+ }
	145	+
	146	+ /* We only allow userspace to drive the SW_PPI, if it is implemented. */
	147	+ bitmap_zero(kvm->arch.vgic.gicv5_vm.userspace_ppis,
	148	+ VGIC_V5_NR_PRIVATE_IRQS);
	149	+ __assign_bit(GICV5_ARCH_PPI_SW_PPI,
	150	+ kvm->arch.vgic.gicv5_vm.userspace_ppis,
	151	+ VGIC_V5_NR_PRIVATE_IRQS);
	152	+ bitmap_and(kvm->arch.vgic.gicv5_vm.userspace_ppis,
	153	+ kvm->arch.vgic.gicv5_vm.userspace_ppis,
	154	+ ppi_caps.impl_ppi_mask, VGIC_V5_NR_PRIVATE_IRQS);
	155	+
	156	+ return 0;
	157	+}
	158	+
	159	+int vgic_v5_map_resources(struct kvm *kvm)
	160	+{
	161	+ if (!vgic_initialized(kvm))
	162	+ return -EBUSY;
	163	+
	164	+ return 0;
	165	+}
	166	+
	167	+int vgic_v5_finalize_ppi_state(struct kvm *kvm)
	168	+{
	169	+ struct kvm_vcpu *vcpu0;
	170	+ int i;
	171	+
	172	+ if (!vgic_is_v5(kvm))
	173	+ return 0;
	174	+
	175	+ /* The PPI state for all VCPUs should be the same. Pick the first. */
	176	+ vcpu0 = kvm_get_vcpu(kvm, 0);
	177	+
	178	+ bitmap_zero(kvm->arch.vgic.gicv5_vm.vgic_ppi_mask, VGIC_V5_NR_PRIVATE_IRQS);
	179	+ bitmap_zero(kvm->arch.vgic.gicv5_vm.vgic_ppi_hmr, VGIC_V5_NR_PRIVATE_IRQS);
	180	+
	181	+ for_each_set_bit(i, ppi_caps.impl_ppi_mask, VGIC_V5_NR_PRIVATE_IRQS) {
	182	+ const u32 intid = vgic_v5_make_ppi(i);
	183	+ struct vgic_irq *irq;
	184	+
	185	+ irq = vgic_get_vcpu_irq(vcpu0, intid);
	186	+
	187	+ /* Expose PPIs with an owner or the SW_PPI, only */
	188	+ scoped_guard(raw_spinlock_irqsave, &irq->irq_lock) {
	189	+ if (irq->owner \|\| i == GICV5_ARCH_PPI_SW_PPI) {
	190	+ __assign_bit(i, kvm->arch.vgic.gicv5_vm.vgic_ppi_mask, 1);
	191	+ __assign_bit(i, kvm->arch.vgic.gicv5_vm.vgic_ppi_hmr,
	192	+ irq->config == VGIC_CONFIG_LEVEL);
	193	+ }
	194	+ }
	195	+
	196	+ vgic_put_irq(vcpu0->kvm, irq);
	197	+ }
	198	+
	199	+ return 0;
	200	+}
	201	+
	202	+static u32 vgic_v5_get_effective_priority_mask(struct kvm_vcpu *vcpu)
	203	+{
	204	+ struct vgic_v5_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v5;
	205	+ u32 highest_ap, priority_mask;
	206	+
	207	+ /*
	208	+ * If the guest's CPU has not opted to receive interrupts, then the
	209	+ * effective running priority is the highest priority. Just return 0
	210	+ * (the highest priority).
	211	+ */
	212	+ if (!FIELD_GET(FEAT_GCIE_ICH_VMCR_EL2_EN, cpu_if->vgic_vmcr))
	213	+ return 0;
	214	+
	215	+ /*
	216	+ * Counting the number of trailing zeros gives the current active
	217	+ * priority. Explicitly use the 32-bit version here as we have 32
	218	+ * priorities. 32 then means that there are no active priorities.
	219	+ */
	220	+ highest_ap = cpu_if->vgic_apr ? __builtin_ctz(cpu_if->vgic_apr) : 32;
	221	+
	222	+ /*
	223	+ * An interrupt is of sufficient priority if it is equal to or
	224	+ * greater than the priority mask. Add 1 to the priority mask
	225	+ * (i.e., lower priority) to match the APR logic before taking
	226	+ * the min. This gives us the lowest priority that is masked.
	227	+ */
	228	+ priority_mask = FIELD_GET(FEAT_GCIE_ICH_VMCR_EL2_VPMR, cpu_if->vgic_vmcr);
	229	+
	230	+ return min(highest_ap, priority_mask + 1);
	231	+}
	232	+
	233	+/*
	234	+ * For GICv5, the PPIs are mostly directly managed by the hardware. We (the
	235	+ * hypervisor) handle the pending, active, enable state save/restore, but don't
	236	+ * need the PPIs to be queued on a per-VCPU AP list. Therefore, sanity check the
	237	+ * state, unlock, and return.
	238	+ */
	239	+bool vgic_v5_ppi_queue_irq_unlock(struct kvm kvm, struct vgic_irq irq,
	240	+ unsigned long flags)
	241	+ __releases(&irq->irq_lock)
	242	+{
	243	+ struct kvm_vcpu *vcpu;
	244	+
	245	+ lockdep_assert_held(&irq->irq_lock);
	246	+
	247	+ if (WARN_ON_ONCE(!__irq_is_ppi(KVM_DEV_TYPE_ARM_VGIC_V5, irq->intid)))
	248	+ goto out_unlock_fail;
	249	+
	250	+ vcpu = irq->target_vcpu;
	251	+ if (WARN_ON_ONCE(!vcpu))
	252	+ goto out_unlock_fail;
	253	+
	254	+ raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
	255	+
	256	+ /* Directly kick the target VCPU to make sure it sees the IRQ */
	257	+ kvm_make_request(KVM_REQ_IRQ_PENDING, vcpu);
	258	+ kvm_vcpu_kick(vcpu);
	259	+
	260	+ return true;
	261	+
	262	+out_unlock_fail:
	263	+ raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
	264	+
	265	+ return false;
	266	+}
	267	+
	268	+/*
	269	+ * Sets/clears the corresponding bit in the ICH_PPI_DVIR register.
	270	+ */
	271	+void vgic_v5_set_ppi_dvi(struct kvm_vcpu vcpu, struct vgic_irq irq, bool dvi)
	272	+{
	273	+ struct vgic_v5_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v5;
	274	+ u32 ppi;
	275	+
	276	+ lockdep_assert_held(&irq->irq_lock);
	277	+
	278	+ ppi = vgic_v5_get_hwirq_id(irq->intid);
	279	+ __assign_bit(ppi, cpu_if->vgic_ppi_dvir, dvi);
	280	+}
	281	+
	282	+static struct irq_ops vgic_v5_ppi_irq_ops = {
	283	+ .queue_irq_unlock = vgic_v5_ppi_queue_irq_unlock,
	284	+ .set_direct_injection = vgic_v5_set_ppi_dvi,
	285	+};
	286	+
	287	+void vgic_v5_set_ppi_ops(struct kvm_vcpu *vcpu, u32 vintid)
	288	+{
	289	+ kvm_vgic_set_irq_ops(vcpu, vintid, &vgic_v5_ppi_irq_ops);
	290	+}
	291	+
	292	+/*
	293	+ * Sync back the PPI priorities to the vgic_irq shadow state for any interrupts
	294	+ * exposed to the guest (skipping all others).
	295	+ */
	296	+static void vgic_v5_sync_ppi_priorities(struct kvm_vcpu *vcpu)
	297	+{
	298	+ struct vgic_v5_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v5;
	299	+ u64 priorityr;
	300	+ int i;
	301	+
	302	+ /*
	303	+ * We have up to 16 PPI Priority regs, but only have a few interrupts
	304	+ * that the guest is allowed to use. Limit our sync of PPI priorities to
	305	+ * those actually exposed to the guest by first iterating over the mask
	306	+ * of exposed PPIs.
	307	+ */
	308	+ for_each_set_bit(i, vcpu->kvm->arch.vgic.gicv5_vm.vgic_ppi_mask, VGIC_V5_NR_PRIVATE_IRQS) {
	309	+ u32 intid = vgic_v5_make_ppi(i);
	310	+ struct vgic_irq *irq;
	311	+ int pri_idx, pri_reg, pri_bit;
	312	+ u8 priority;
	313	+
	314	+ /*
	315	+ * Determine which priority register and the field within it to
	316	+ * extract.
	317	+ */
	318	+ pri_reg = i / 8;
	319	+ pri_idx = i % 8;
	320	+ pri_bit = pri_idx * 8;
	321	+
	322	+ priorityr = cpu_if->vgic_ppi_priorityr[pri_reg];
	323	+ priority = field_get(GENMASK(pri_bit + 4, pri_bit), priorityr);
	324	+
	325	+ irq = vgic_get_vcpu_irq(vcpu, intid);
	326	+
	327	+ scoped_guard(raw_spinlock_irqsave, &irq->irq_lock)
	328	+ irq->priority = priority;
	329	+
	330	+ vgic_put_irq(vcpu->kvm, irq);
	331	+ }
	332	+}
	333	+
	334	+bool vgic_v5_has_pending_ppi(struct kvm_vcpu *vcpu)
	335	+{
	336	+ unsigned int priority_mask;
	337	+ int i;
	338	+
	339	+ priority_mask = vgic_v5_get_effective_priority_mask(vcpu);
	340	+
	341	+ /*
	342	+ * If the combined priority mask is 0, nothing can be signalled! In the
	343	+ * case where the guest has disabled interrupt delivery for the vcpu
	344	+ * (via ICV_CR0_EL1.EN->ICH_VMCR_EL2.EN), we calculate the priority mask
	345	+ * as 0 too (the highest possible priority).
	346	+ */
	347	+ if (!priority_mask)
	348	+ return false;
	349	+
	350	+ for_each_set_bit(i, vcpu->kvm->arch.vgic.gicv5_vm.vgic_ppi_mask, VGIC_V5_NR_PRIVATE_IRQS) {
	351	+ u32 intid = vgic_v5_make_ppi(i);
	352	+ bool has_pending = false;
	353	+ struct vgic_irq *irq;
	354	+
	355	+ irq = vgic_get_vcpu_irq(vcpu, intid);
	356	+
	357	+ scoped_guard(raw_spinlock_irqsave, &irq->irq_lock)
	358	+ has_pending = (irq->enabled && irq_is_pending(irq) &&
	359	+ irq->priority <= priority_mask);
	360	+
	361	+ vgic_put_irq(vcpu->kvm, irq);
	362	+
	363	+ if (has_pending)
	364	+ return true;
	365	+ }
	366	+
	367	+ return false;
	368	+}
	369	+
	370	+/*
	371	+ * Detect any PPIs state changes, and propagate the state with KVM's
	372	+ * shadow structures.
	373	+ */
	374	+void vgic_v5_fold_ppi_state(struct kvm_vcpu *vcpu)
	375	+{
	376	+ struct vgic_v5_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v5;
	377	+ DECLARE_BITMAP(changed_active, VGIC_V5_NR_PRIVATE_IRQS);
	378	+ DECLARE_BITMAP(changed_pending, VGIC_V5_NR_PRIVATE_IRQS);
	379	+ DECLARE_BITMAP(changed_bits, VGIC_V5_NR_PRIVATE_IRQS);
	380	+ unsigned long activer, pendr_entry, *pendr;
	381	+ int i;
	382	+
	383	+ activer = host_data_ptr(vgic_v5_ppi_state)->activer_exit;
	384	+ pendr_entry = host_data_ptr(vgic_v5_ppi_state)->pendr_entry;
	385	+ pendr = host_data_ptr(vgic_v5_ppi_state)->pendr_exit;
	386	+
	387	+ bitmap_xor(changed_active, cpu_if->vgic_ppi_activer, activer,
	388	+ VGIC_V5_NR_PRIVATE_IRQS);
	389	+ bitmap_xor(changed_pending, pendr_entry, pendr,
	390	+ VGIC_V5_NR_PRIVATE_IRQS);
	391	+ bitmap_or(changed_bits, changed_active, changed_pending,
	392	+ VGIC_V5_NR_PRIVATE_IRQS);
	393	+
	394	+ for_each_set_bit(i, changed_bits, VGIC_V5_NR_PRIVATE_IRQS) {
	395	+ u32 intid = vgic_v5_make_ppi(i);
	396	+ struct vgic_irq *irq;
	397	+
	398	+ irq = vgic_get_vcpu_irq(vcpu, intid);
	399	+
	400	+ scoped_guard(raw_spinlock_irqsave, &irq->irq_lock) {
	401	+ irq->active = test_bit(i, activer);
	402	+
	403	+ /* This is an OR to avoid losing incoming edges! */
	404	+ if (irq->config == VGIC_CONFIG_EDGE)
	405	+ irq->pending_latch \|= test_bit(i, pendr);
	406	+ }
	407	+
	408	+ vgic_put_irq(vcpu->kvm, irq);
	409	+ }
	410	+
	411	+ /*
	412	+ * Re-inject the exit state as entry state next time!
	413	+ *
	414	+ * Note that the write of the Enable state is trapped, and hence there
	415	+ * is nothing to explcitly sync back here as we already have the latest
	416	+ * copy by definition.
	417	+ */
	418	+ bitmap_copy(cpu_if->vgic_ppi_activer, activer, VGIC_V5_NR_PRIVATE_IRQS);
	419	+}
	420	+
	421	+void vgic_v5_flush_ppi_state(struct kvm_vcpu *vcpu)
	422	+{
	423	+ DECLARE_BITMAP(pendr, VGIC_V5_NR_PRIVATE_IRQS);
	424	+ int i;
	425	+
	426	+ /*
	427	+ * Time to enter the guest - we first need to build the guest's
	428	+ * ICC_PPI_PENDRx_EL1, however.
	429	+ */
	430	+ bitmap_zero(pendr, VGIC_V5_NR_PRIVATE_IRQS);
	431	+ for_each_set_bit(i, vcpu->kvm->arch.vgic.gicv5_vm.vgic_ppi_mask,
	432	+ VGIC_V5_NR_PRIVATE_IRQS) {
	433	+ u32 intid = vgic_v5_make_ppi(i);
	434	+ struct vgic_irq *irq;
	435	+
	436	+ irq = vgic_get_vcpu_irq(vcpu, intid);
	437	+
	438	+ scoped_guard(raw_spinlock_irqsave, &irq->irq_lock)
	439	+ __assign_bit(i, pendr, irq_is_pending(irq));
	440	+
	441	+ vgic_put_irq(vcpu->kvm, irq);
	442	+ }
	443	+
	444	+ /*
	445	+ * Copy the shadow state to the pending reg that will be written to the
	446	+ * ICH_PPI_PENDRx_EL2 regs. While the guest is running we track any
	447	+ * incoming changes to the pending state in the vgic_irq structures. The
	448	+ * incoming changes are merged with the outgoing changes on the return
	449	+ * path.
	450	+ */
	451	+ bitmap_copy(host_data_ptr(vgic_v5_ppi_state)->pendr_entry, pendr,
	452	+ VGIC_V5_NR_PRIVATE_IRQS);
	453	+
	454	+ /*
	455	+ * Make sure that we can correctly detect "edges" in the PPI
	456	+ * state. There's a path where we never actually enter the guest, and
	457	+ * failure to do this risks losing pending state
	458	+ */
	459	+ bitmap_copy(host_data_ptr(vgic_v5_ppi_state)->pendr_exit, pendr,
	460	+ VGIC_V5_NR_PRIVATE_IRQS);
	461	+}
	462	+
	463	+void vgic_v5_load(struct kvm_vcpu *vcpu)
	464	+{
	465	+ struct vgic_v5_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v5;
	466	+
	467	+ /*
	468	+ * On the WFI path, vgic_load is called a second time. The first is when
	469	+ * scheduling in the vcpu thread again, and the second is when leaving
	470	+ * WFI. Skip the second instance as it serves no purpose and just
	471	+ * restores the same state again.
	472	+ */
	473	+ if (cpu_if->gicv5_vpe.resident)
	474	+ return;
	475	+
	476	+ kvm_call_hyp(__vgic_v5_restore_vmcr_apr, cpu_if);
	477	+
	478	+ cpu_if->gicv5_vpe.resident = true;
	479	+}
	480	+
	481	+void vgic_v5_put(struct kvm_vcpu *vcpu)
	482	+{
	483	+ struct vgic_v5_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v5;
	484	+
	485	+ /*
	486	+ * Do nothing if we're not resident. This can happen in the WFI path
	487	+ * where we do a vgic_put in the WFI path and again later when
	488	+ * descheduling the thread. We risk losing VMCR state if we sync it
	489	+ * twice, so instead return early in this case.
	490	+ */
	491	+ if (!cpu_if->gicv5_vpe.resident)
	492	+ return;
	493	+
	494	+ kvm_call_hyp(__vgic_v5_save_apr, cpu_if);
	495	+
	496	+ cpu_if->gicv5_vpe.resident = false;
	497	+
	498	+ /* The shadow priority is only updated on entering WFI */
	499	+ if (vcpu_get_flag(vcpu, IN_WFI))
	500	+ vgic_v5_sync_ppi_priorities(vcpu);
	501	+}
	502	+
	503	+void vgic_v5_get_vmcr(struct kvm_vcpu vcpu, struct vgic_vmcr vmcrp)
	504	+{
	505	+ struct vgic_v5_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v5;
	506	+ u64 vmcr = cpu_if->vgic_vmcr;
	507	+
	508	+ vmcrp->en = FIELD_GET(FEAT_GCIE_ICH_VMCR_EL2_EN, vmcr);
	509	+ vmcrp->pmr = FIELD_GET(FEAT_GCIE_ICH_VMCR_EL2_VPMR, vmcr);
	510	+}
	511	+
	512	+void vgic_v5_set_vmcr(struct kvm_vcpu vcpu, struct vgic_vmcr vmcrp)
	513	+{
	514	+ struct vgic_v5_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v5;
	515	+ u64 vmcr;
	516	+
	517	+ vmcr = FIELD_PREP(FEAT_GCIE_ICH_VMCR_EL2_VPMR, vmcrp->pmr) \|
	518	+ FIELD_PREP(FEAT_GCIE_ICH_VMCR_EL2_EN, vmcrp->en);
	519	+
	520	+ cpu_if->vgic_vmcr = vmcr;
	521	+}
	522	+
	523	+void vgic_v5_restore_state(struct kvm_vcpu *vcpu)
	524	+{
	525	+ struct vgic_v5_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v5;
	526	+
	527	+ __vgic_v5_restore_state(cpu_if);
	528	+ __vgic_v5_restore_ppi_state(cpu_if);
	529	+ dsb(sy);
	530	+}
	531	+
	532	+void vgic_v5_save_state(struct kvm_vcpu *vcpu)
	533	+{
	534	+ struct vgic_v5_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v5;
	535	+
	536	+ __vgic_v5_save_state(cpu_if);
	537	+ __vgic_v5_save_ppi_state(cpu_if);
	538	+ dsb(sy);
	539	+}

arch/arm64/kvm/vgic/vgic.c+139−34

@@ -86,6 +86,10 @@ static struct vgic_irq vgic_get_lpi(struct kvm kvm, u32 intid) · 85 unmodified lines
86	86	*/
87	87	struct vgic_irq vgic_get_irq(struct kvm kvm, u32 intid)
88	88	{
	89	+ /* Non-private IRQs are not yet implemented for GICv5 */
	90	+ if (vgic_is_v5(kvm))
	91	+ return NULL;
	92	+
89	93	/* SPIs */
90	94	if (intid >= VGIC_NR_PRIVATE_IRQS &&
91	95	intid < (kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS)) {
@@ -94,7 +98,7 @@ struct vgic_irq vgic_get_irq(struct kvm kvm, u32 intid) · 2 unmodified lines
94	98	}
95	99
96	100	/* LPIs */
97		− if (intid >= VGIC_MIN_LPI)
	101	+ if (irq_is_lpi(kvm, intid))
98	102	return vgic_get_lpi(kvm, intid);
99	103
100	104	return NULL;
@@ -105,6 +109,18 @@ struct vgic_irq vgic_get_vcpu_irq(struct kvm_vcpu vcpu, u32 intid) · 4 unmodified lines
105	109	if (WARN_ON(!vcpu))
106	110	return NULL;
107	111
	112	+ if (vgic_is_v5(vcpu->kvm)) {
	113	+ u32 int_num, hwirq_id;
	114	+
	115	+ if (!__irq_is_ppi(KVM_DEV_TYPE_ARM_VGIC_V5, intid))
	116	+ return NULL;
	117	+
	118	+ hwirq_id = FIELD_GET(GICV5_HWIRQ_ID, intid);
	119	+ int_num = array_index_nospec(hwirq_id, VGIC_V5_NR_PRIVATE_IRQS);
	120	+
	121	+ return &vcpu->arch.vgic_cpu.private_irqs[int_num];
	122	+ }
	123	+
108	124	/* SGIs and PPIs */
109	125	if (intid < VGIC_NR_PRIVATE_IRQS) {
110	126	intid = array_index_nospec(intid, VGIC_NR_PRIVATE_IRQS);
@@ -123,7 +139,7 @@ static void vgic_release_lpi_locked(struct vgic_dist dist, struct vgic_irq irq · 12 unmodified lines
123	139
124	140	static __must_check bool __vgic_put_irq(struct kvm kvm, struct vgic_irq irq)
125	141	{
126		− if (irq->intid < VGIC_MIN_LPI)
	142	+ if (!irq_is_lpi(kvm, irq->intid))
127	143	return false;
128	144
129	145	return refcount_dec_and_test(&irq->refcount);
@@ -148,7 +164,7 @@ void vgic_put_irq(struct kvm kvm, struct vgic_irq irq) · 18 unmodified lines
148	164	* Acquire/release it early on lockdep kernels to make locking issues
149	165	* in rare release paths a bit more obvious.
150	166	*/
151		− if (IS_ENABLED(CONFIG_LOCKDEP) && irq->intid >= VGIC_MIN_LPI) {
	167	+ if (IS_ENABLED(CONFIG_LOCKDEP) && irq_is_lpi(kvm, irq->intid)) {
152	168	guard(spinlock_irqsave)(&dist->lpi_xa.xa_lock);
153	169	}
154	170
@@ -186,7 +202,7 @@ void vgic_flush_pending_lpis(struct kvm_vcpu *vcpu) · 31 unmodified lines
186	202	raw_spin_lock_irqsave(&vgic_cpu->ap_list_lock, flags);
187	203
188	204	list_for_each_entry_safe(irq, tmp, &vgic_cpu->ap_list_head, ap_list) {
189		− if (irq->intid >= VGIC_MIN_LPI) {
	205	+ if (irq_is_lpi(vcpu->kvm, irq->intid)) {
190	206	raw_spin_lock(&irq->irq_lock);
191	207	list_del(&irq->ap_list);
192	208	irq->vcpu = NULL;
@@ -404,6 +420,9 @@ bool vgic_queue_irq_unlock(struct kvm kvm, struct vgic_irq irq, · 211 unmodified lines
404	420
405	421	lockdep_assert_held(&irq->irq_lock);
406	422
	423	+ if (irq->ops && irq->ops->queue_irq_unlock)
	424	+ return irq->ops->queue_irq_unlock(kvm, irq, flags);
	425	+
407	426	retry:
408	427	vcpu = vgic_target_oracle(irq);
409	428	if (irq->vcpu \|\| !vcpu) {
@@ -521,12 +540,12 @@ int kvm_vgic_inject_irq(struct kvm kvm, struct kvm_vcpu vcpu, · 111 unmodified lines
521	540	if (ret)
522	541	return ret;
523	542
524		− if (!vcpu && intid < VGIC_NR_PRIVATE_IRQS)
	543	+ if (!vcpu && irq_is_private(kvm, intid))
525	544	return -EINVAL;
526	545
527	546	trace_vgic_update_irq_pending(vcpu ? vcpu->vcpu_idx : 0, intid, level);
528	547
529		− if (intid < VGIC_NR_PRIVATE_IRQS)
	548	+ if (irq_is_private(kvm, intid))
530	549	irq = vgic_get_vcpu_irq(vcpu, intid);
531	550	else
532	551	irq = vgic_get_irq(kvm, intid);
@@ -553,10 +572,27 @@ int kvm_vgic_inject_irq(struct kvm kvm, struct kvm_vcpu vcpu, · 20 unmodified lines
553	572	return 0;
554	573	}
555	574
	575	+void kvm_vgic_set_irq_ops(struct kvm_vcpu *vcpu, u32 vintid,
	576	+ struct irq_ops *ops)
	577	+{
	578	+ struct vgic_irq *irq = vgic_get_vcpu_irq(vcpu, vintid);
	579	+
	580	+ BUG_ON(!irq);
	581	+
	582	+ scoped_guard(raw_spinlock_irqsave, &irq->irq_lock)
	583	+ irq->ops = ops;
	584	+
	585	+ vgic_put_irq(vcpu->kvm, irq);
	586	+}
	587	+
	588	+void kvm_vgic_clear_irq_ops(struct kvm_vcpu *vcpu, u32 vintid)
	589	+{
	590	+ kvm_vgic_set_irq_ops(vcpu, vintid, NULL);
	591	+}
	592	+
556	593	/* @irq->irq_lock must be held */
557	594	static int kvm_vgic_map_irq(struct kvm_vcpu vcpu, struct vgic_irq irq,
558		− unsigned int host_irq,
559		− struct irq_ops *ops)
	595	+ unsigned int host_irq)
560	596	{
561	597	struct irq_desc *desc;
562	598	struct irq_data *data;
@@ -576,20 +612,25 @@ static int kvm_vgic_map_irq(struct kvm_vcpu vcpu, struct vgic_irq irq, · 13 unmodified lines
576	612	irq->hw = true;
577	613	irq->host_irq = host_irq;
578	614	irq->hwintid = data->hwirq;
579		− irq->ops = ops;
	615	+
	616	+ if (irq->ops && irq->ops->set_direct_injection)
	617	+ irq->ops->set_direct_injection(vcpu, irq, true);
	618	+
580	619	return 0;
581	620	}
582	621
583	622	/* @irq->irq_lock must be held */
584	623	static inline void kvm_vgic_unmap_irq(struct vgic_irq *irq)
585	624	{
	625	+ if (irq->ops && irq->ops->set_direct_injection)
	626	+ irq->ops->set_direct_injection(irq->target_vcpu, irq, false);
	627	+
586	628	irq->hw = false;
587	629	irq->hwintid = 0;
588		− irq->ops = NULL;
589	630	}
590	631
591	632	int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, unsigned int host_irq,
592		− u32 vintid, struct irq_ops *ops)
	633	+ u32 vintid)
593	634	{
594	635	struct vgic_irq *irq = vgic_get_vcpu_irq(vcpu, vintid);
595	636	unsigned long flags;
@@ -598,7 +639,7 @@ int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, unsigned int host_irq, · 2 unmodified lines
598	639	BUG_ON(!irq);
599	640
600	641	raw_spin_lock_irqsave(&irq->irq_lock, flags);
601		− ret = kvm_vgic_map_irq(vcpu, irq, host_irq, ops);
	642	+ ret = kvm_vgic_map_irq(vcpu, irq, host_irq);
602	643	raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
603	644	vgic_put_irq(vcpu->kvm, irq);
604	645
@@ -685,7 +726,7 @@ int kvm_vgic_set_owner(struct kvm_vcpu vcpu, unsigned int intid, void owner) · 80 unmodified lines
685	726	return -EAGAIN;
686	727
687	728	/* SGIs and LPIs cannot be wired up to any device */
688		− if (!irq_is_ppi(intid) && !vgic_valid_spi(vcpu->kvm, intid))
	729	+ if (!irq_is_ppi(vcpu->kvm, intid) && !vgic_valid_spi(vcpu->kvm, intid))
689	730	return -EINVAL;
690	731
691	732	irq = vgic_get_vcpu_irq(vcpu, intid);
@@ -812,8 +853,13 @@ retry: · 120 unmodified lines
812	853	vgic_release_deleted_lpis(vcpu->kvm);
813	854	}
814	855
815		−static inline void vgic_fold_lr_state(struct kvm_vcpu *vcpu)
	856	+static void vgic_fold_state(struct kvm_vcpu *vcpu)
816	857	{
	858	+ if (vgic_is_v5(vcpu->kvm)) {
	859	+ vgic_v5_fold_ppi_state(vcpu);
	860	+ return;
	861	+ }
	862	+
817	863	if (!*host_data_ptr(last_lr_irq))
818	864	return;
819	865
@@ -1002,7 +1048,10 @@ static inline bool can_access_vgic_from_kernel(void) · 182 unmodified lines
1002	1048
1003	1049	static inline void vgic_save_state(struct kvm_vcpu *vcpu)
1004	1050	{
1005		− if (!static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif))
	1051	+ /* No switch statement here. See comment in vgic_restore_state() */
	1052	+ if (vgic_is_v5(vcpu->kvm))
	1053	+ vgic_v5_save_state(vcpu);
	1054	+ else if (!static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif))
1006	1055	vgic_v2_save_state(vcpu);
1007	1056	else
1008	1057	__vgic_v3_save_state(&vcpu->arch.vgic_cpu.vgic_v3);
@@ -1011,20 +1060,24 @@ static inline void vgic_save_state(struct kvm_vcpu *vcpu) · 2 unmodified lines
1011	1060	/* Sync back the hardware VGIC state into our emulation after a guest's run. */
1012	1061	void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu)
1013	1062	{
1014		− /* If nesting, emulate the HW effect from L0 to L1 */
1015		− if (vgic_state_is_nested(vcpu)) {
1016		− vgic_v3_sync_nested(vcpu);
1017		− return;
1018		− }
	1063	+ if (vgic_is_v3(vcpu->kvm)) {
	1064	+ /* If nesting, emulate the HW effect from L0 to L1 */
	1065	+ if (vgic_state_is_nested(vcpu)) {
	1066	+ vgic_v3_sync_nested(vcpu);
	1067	+ return;
	1068	+ }
1019	1069
1020		− if (vcpu_has_nv(vcpu))
1021		− vgic_v3_nested_update_mi(vcpu);
	1070	+ if (vcpu_has_nv(vcpu))
	1071	+ vgic_v3_nested_update_mi(vcpu);
	1072	+ }
1022	1073
1023	1074	if (can_access_vgic_from_kernel())
1024	1075	vgic_save_state(vcpu);
1025	1076
1026		− vgic_fold_lr_state(vcpu);
1027		− vgic_prune_ap_list(vcpu);
	1077	+ vgic_fold_state(vcpu);
	1078	+
	1079	+ if (!vgic_is_v5(vcpu->kvm))
	1080	+ vgic_prune_ap_list(vcpu);
1028	1081	}
1029	1082
1030	1083	/* Sync interrupts that were deactivated through a DIR trap */
@@ -1040,12 +1093,34 @@ void kvm_vgic_process_async_update(struct kvm_vcpu *vcpu) · 9 unmodified lines
1040	1093
1041	1094	static inline void vgic_restore_state(struct kvm_vcpu *vcpu)
1042	1095	{
1043		− if (!static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif))
	1096	+ /*
	1097	+ * As nice as it would be to restructure this code into a switch
	1098	+ * statement as can be found elsewhere, the logic quickly gets ugly.
	1099	+ *
	1100	+ * __vgic_v3_restore_state() is doing a lot of heavy lifting here. It is
	1101	+ * required for GICv3-on-GICv3, GICv2-on-GICv3, GICv3-on-GICv5, and the
	1102	+ * no-in-kernel-irqchip case on GICv3 hardware. Hence, adding a switch
	1103	+ * here results in much more complex code.
	1104	+ */
	1105	+ if (vgic_is_v5(vcpu->kvm))
	1106	+ vgic_v5_restore_state(vcpu);
	1107	+ else if (!static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif))
1044	1108	vgic_v2_restore_state(vcpu);
1045	1109	else
1046	1110	__vgic_v3_restore_state(&vcpu->arch.vgic_cpu.vgic_v3);
1047	1111	}
1048	1112
	1113	+static void vgic_flush_state(struct kvm_vcpu *vcpu)
	1114	+{
	1115	+ if (vgic_is_v5(vcpu->kvm)) {
	1116	+ vgic_v5_flush_ppi_state(vcpu);
	1117	+ return;
	1118	+ }
	1119	+
	1120	+ scoped_guard(raw_spinlock, &vcpu->arch.vgic_cpu.ap_list_lock)
	1121	+ vgic_flush_lr_state(vcpu);
	1122	+}
	1123	+
1049	1124	/* Flush our emulation state into the GIC hardware before entering the guest. */
1050	1125	void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu)
1051	1126	{
@@ -1082,42 +1157,69 @@ void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) · 30 unmodified lines
1082	1157
1083	1158	DEBUG_SPINLOCK_BUG_ON(!irqs_disabled());
1084	1159
1085		− scoped_guard(raw_spinlock, &vcpu->arch.vgic_cpu.ap_list_lock)
1086		− vgic_flush_lr_state(vcpu);
	1160	+ vgic_flush_state(vcpu);
1087	1161
1088	1162	if (can_access_vgic_from_kernel())
1089	1163	vgic_restore_state(vcpu);
1090	1164
1091		− if (vgic_supports_direct_irqs(vcpu->kvm))
	1165	+ if (vgic_supports_direct_irqs(vcpu->kvm) && kvm_vgic_global_state.has_gicv4)
1092	1166	vgic_v4_commit(vcpu);
1093	1167	}
1094	1168
1095	1169	void kvm_vgic_load(struct kvm_vcpu *vcpu)
1096	1170	{
	1171	+ const struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
	1172	+
1097	1173	if (unlikely(!irqchip_in_kernel(vcpu->kvm) \|\| !vgic_initialized(vcpu->kvm))) {
1098	1174	if (has_vhe() && static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif))
1099	1175	__vgic_v3_activate_traps(&vcpu->arch.vgic_cpu.vgic_v3);
1100	1176	return;
1101	1177	}
1102	1178
1103		− if (!static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif))
1104		− vgic_v2_load(vcpu);
1105		− else
	1179	+ switch (dist->vgic_model) {
	1180	+ case KVM_DEV_TYPE_ARM_VGIC_V5:
	1181	+ vgic_v5_load(vcpu);
	1182	+ break;
	1183	+ case KVM_DEV_TYPE_ARM_VGIC_V3:
1106	1184	vgic_v3_load(vcpu);
	1185	+ break;
	1186	+ case KVM_DEV_TYPE_ARM_VGIC_V2:
	1187	+ if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif))
	1188	+ vgic_v3_load(vcpu);
	1189	+ else
	1190	+ vgic_v2_load(vcpu);
	1191	+ break;
	1192	+ default:
	1193	+ BUG();
	1194	+ }
1107	1195	}
1108	1196
1109	1197	void kvm_vgic_put(struct kvm_vcpu *vcpu)
1110	1198	{
	1199	+ const struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
	1200	+
1111	1201	if (unlikely(!irqchip_in_kernel(vcpu->kvm) \|\| !vgic_initialized(vcpu->kvm))) {
1112	1202	if (has_vhe() && static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif))
1113	1203	__vgic_v3_deactivate_traps(&vcpu->arch.vgic_cpu.vgic_v3);
1114	1204	return;
1115	1205	}
1116	1206
1117		− if (!static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif))
1118		− vgic_v2_put(vcpu);
1119		− else
	1207	+ switch (dist->vgic_model) {
	1208	+ case KVM_DEV_TYPE_ARM_VGIC_V5:
	1209	+ vgic_v5_put(vcpu);
	1210	+ break;
	1211	+ case KVM_DEV_TYPE_ARM_VGIC_V3:
1120	1212	vgic_v3_put(vcpu);
	1213	+ break;
	1214	+ case KVM_DEV_TYPE_ARM_VGIC_V2:
	1215	+ if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif))
	1216	+ vgic_v3_put(vcpu);
	1217	+ else
	1218	+ vgic_v2_put(vcpu);
	1219	+ break;
	1220	+ default:
	1221	+ BUG();
	1222	+ }
1121	1223	}
1122	1224
1123	1225	int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu)
@@ -1128,6 +1230,9 @@ int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu) · 4 unmodified lines
1128	1230	unsigned long flags;
1129	1231	struct vgic_vmcr vmcr;
1130	1232
	1233	+ if (vgic_is_v5(vcpu->kvm))
	1234	+ return vgic_v5_has_pending_ppi(vcpu);
	1235	+
1131	1236	if (!vcpu->kvm->arch.vgic.enabled)
1132	1237	return false;
1133	1238

arch/arm64/kvm/vgic/vgic.h+40−13

@@ -187,6 +187,7 @@ static inline u64 vgic_ich_hcr_trap_bits(void) · 186 unmodified lines
187	187	* registers regardless of the hardware backed GIC used.
188	188	*/
189	189	struct vgic_vmcr {
	190	+ u32 en; /* GICv5-specific */
190	191	u32 grpen0;
191	192	u32 grpen1;
192	193
@@ -363,6 +364,19 @@ void vgic_debug_init(struct kvm *kvm); · 170 unmodified lines
363	364	void vgic_debug_destroy(struct kvm *kvm);
364	365
365	366	int vgic_v5_probe(const struct gic_kvm_info *info);
	367	+void vgic_v5_reset(struct kvm_vcpu *vcpu);
	368	+int vgic_v5_init(struct kvm *kvm);
	369	+int vgic_v5_map_resources(struct kvm *kvm);
	370	+void vgic_v5_set_ppi_ops(struct kvm_vcpu *vcpu, u32 vintid);
	371	+bool vgic_v5_has_pending_ppi(struct kvm_vcpu *vcpu);
	372	+void vgic_v5_flush_ppi_state(struct kvm_vcpu *vcpu);
	373	+void vgic_v5_fold_ppi_state(struct kvm_vcpu *vcpu);
	374	+void vgic_v5_load(struct kvm_vcpu *vcpu);
	375	+void vgic_v5_put(struct kvm_vcpu *vcpu);
	376	+void vgic_v5_set_vmcr(struct kvm_vcpu vcpu, struct vgic_vmcr vmcr);
	377	+void vgic_v5_get_vmcr(struct kvm_vcpu vcpu, struct vgic_vmcr vmcr);
	378	+void vgic_v5_restore_state(struct kvm_vcpu *vcpu);
	379	+void vgic_v5_save_state(struct kvm_vcpu *vcpu);
366	380
367	381	static inline int vgic_v3_max_apr_idx(struct kvm_vcpu *vcpu)
368	382	{
@@ -425,15 +439,6 @@ void vgic_its_invalidate_all_caches(struct kvm *kvm); · 56 unmodified lines
425	439	int vgic_its_inv_lpi(struct kvm kvm, struct vgic_irq irq);
426	440	int vgic_its_invall(struct kvm_vcpu *vcpu);
427	441
428		−bool system_supports_direct_sgis(void);
429		−bool vgic_supports_direct_msis(struct kvm *kvm);
430		−bool vgic_supports_direct_sgis(struct kvm *kvm);
431		−
432		−static inline bool vgic_supports_direct_irqs(struct kvm *kvm)
433		−{
434		− return vgic_supports_direct_msis(kvm) \|\| vgic_supports_direct_sgis(kvm);
435		−}
436		−
437	442	int vgic_v4_init(struct kvm *kvm);
438	443	void vgic_v4_teardown(struct kvm *kvm);
439	444	void vgic_v4_configure_vsgis(struct kvm *kvm);
@@ -447,6 +452,11 @@ static inline bool kvm_has_gicv3(struct kvm *kvm) · 7 unmodified lines
447	452	return kvm_has_feat(kvm, ID_AA64PFR0_EL1, GIC, IMP);
448	453	}
449	454
	455	+static inline bool kvm_has_gicv5(struct kvm *kvm)
	456	+{
	457	+ return kvm_has_feat(kvm, ID_AA64PFR2_EL1, GCIE, IMP);
	458	+}
	459	+
450	460	void vgic_v3_flush_nested(struct kvm_vcpu *vcpu);
451	461	void vgic_v3_sync_nested(struct kvm_vcpu *vcpu);
452	462	void vgic_v3_load_nested(struct kvm_vcpu *vcpu);
@@ -454,15 +464,32 @@ void vgic_v3_put_nested(struct kvm_vcpu *vcpu); · 1 unmodified line
454	464	void vgic_v3_handle_nested_maint_irq(struct kvm_vcpu *vcpu);
455	465	void vgic_v3_nested_update_mi(struct kvm_vcpu *vcpu);
456	466
457		−static inline bool vgic_is_v3_compat(struct kvm *kvm)
	467	+static inline bool vgic_host_has_gicv3(void)
458	468	{
459		− return cpus_have_final_cap(ARM64_HAS_GICV5_CPUIF) &&
	469	+ /*
	470	+ * Either the host is a native GICv3, or it is GICv5 with
	471	+ * FEAT_GCIE_LEGACY.
	472	+ */
	473	+ return kvm_vgic_global_state.type == VGIC_V3 \|\|
460	474	kvm_vgic_global_state.has_gcie_v3_compat;
461	475	}
462	476
463		−static inline bool vgic_is_v3(struct kvm *kvm)
	477	+static inline bool vgic_host_has_gicv5(void)
	478	+{
	479	+ return kvm_vgic_global_state.type == VGIC_V5;
	480	+}
	481	+
	482	+bool system_supports_direct_sgis(void);
	483	+bool vgic_supports_direct_msis(struct kvm *kvm);
	484	+bool vgic_supports_direct_sgis(struct kvm *kvm);
	485	+
	486	+static inline bool vgic_supports_direct_irqs(struct kvm *kvm)
464	487	{
465		− return kvm_vgic_global_state.type == VGIC_V3 \|\| vgic_is_v3_compat(kvm);
	488	+ /* GICv5 always supports direct IRQs */
	489	+ if (vgic_is_v5(kvm))
	490	+ return true;
	491	+
	492	+ return vgic_supports_direct_msis(kvm) \|\| vgic_supports_direct_sgis(kvm);
466	493	}
467	494
468	495	int vgic_its_debug_init(struct kvm_device *dev);

arch/arm64/tools/sysreg+480−0

@@ -3243,6 +3243,14 @@ UnsignedEnum 3:0 ID_BITS · 3242 unmodified lines
3243	3243	EndEnum
3244	3244	EndSysreg
3245	3245
	3246	+Sysreg ICC_HPPIR_EL1 3 0 12 10 3
	3247	+Res0 63:33
	3248	+Field 32 HPPIV
	3249	+Field 31:29 TYPE
	3250	+Res0 28:24
	3251	+Field 23:0 ID
	3252	+EndSysreg
	3253	+
3246	3254	Sysreg ICC_ICSR_EL1 3 0 12 10 4
3247	3255	Res0 63:48
3248	3256	Field 47:32 IAFFID
@@ -3257,6 +3265,11 @@ Field 1 Enabled · 8 unmodified lines
3257	3265	Field 0 F
3258	3266	EndSysreg
3259	3267
	3268	+Sysreg ICC_IAFFIDR_EL1 3 0 12 10 5
	3269	+Res0 63:16
	3270	+Field 15:0 IAFFID
	3271	+EndSysreg
	3272	+
3260	3273	SysregFields ICC_PPI_ENABLERx_EL1
3261	3274	Field 63 EN63
3262	3275	Field 62 EN62
@@ -3663,6 +3676,42 @@ Res0 14:12 · 400 unmodified lines
3663	3676	Field 11:0 AFFINITY
3664	3677	EndSysreg
3665	3678
	3679	+Sysreg ICC_APR_EL1 3 1 12 0 0
	3680	+Res0 63:32
	3681	+Field 31 P31
	3682	+Field 30 P30
	3683	+Field 29 P29
	3684	+Field 28 P28
	3685	+Field 27 P27
	3686	+Field 26 P26
	3687	+Field 25 P25
	3688	+Field 24 P24
	3689	+Field 23 P23
	3690	+Field 22 P22
	3691	+Field 21 P21
	3692	+Field 20 P20
	3693	+Field 19 P19
	3694	+Field 18 P18
	3695	+Field 17 P17
	3696	+Field 16 P16
	3697	+Field 15 P15
	3698	+Field 14 P14
	3699	+Field 13 P13
	3700	+Field 12 P12
	3701	+Field 11 P11
	3702	+Field 10 P10
	3703	+Field 9 P9
	3704	+Field 8 P8
	3705	+Field 7 P7
	3706	+Field 6 P6
	3707	+Field 5 P5
	3708	+Field 4 P4
	3709	+Field 3 P3
	3710	+Field 2 P2
	3711	+Field 1 P1
	3712	+Field 0 P0
	3713	+EndSysreg
	3714	+
3666	3715	Sysreg ICC_CR0_EL1 3 1 12 0 1
3667	3716	Res0 63:39
3668	3717	Field 38 PID
@@ -4687,6 +4736,42 @@ Field 31:16 PhyPARTID29 · 1018 unmodified lines
4687	4736	Field 15:0 PhyPARTID28
4688	4737	EndSysreg
4689	4738
	4739	+Sysreg ICH_APR_EL2 3 4 12 8 4
	4740	+Res0 63:32
	4741	+Field 31 P31
	4742	+Field 30 P30
	4743	+Field 29 P29
	4744	+Field 28 P28
	4745	+Field 27 P27
	4746	+Field 26 P26
	4747	+Field 25 P25
	4748	+Field 24 P24
	4749	+Field 23 P23
	4750	+Field 22 P22
	4751	+Field 21 P21
	4752	+Field 20 P20
	4753	+Field 19 P19
	4754	+Field 18 P18
	4755	+Field 17 P17
	4756	+Field 16 P16
	4757	+Field 15 P15
	4758	+Field 14 P14
	4759	+Field 13 P13
	4760	+Field 12 P12
	4761	+Field 11 P11
	4762	+Field 10 P10
	4763	+Field 9 P9
	4764	+Field 8 P8
	4765	+Field 7 P7
	4766	+Field 6 P6
	4767	+Field 5 P5
	4768	+Field 4 P4
	4769	+Field 3 P3
	4770	+Field 2 P2
	4771	+Field 1 P1
	4772	+Field 0 P0
	4773	+EndSysreg
	4774	+
4690	4775	Sysreg ICH_HFGRTR_EL2 3 4 12 9 4
4691	4776	Res0 63:21
4692	4777	Field 20 ICC_PPI_ACTIVERn_EL1
@@ -4735,6 +4820,306 @@ Field 1 GICCDDIS · 42 unmodified lines
4735	4820	Field 0 GICCDEN
4736	4821	EndSysreg
4737	4822
	4823	+SysregFields ICH_PPI_DVIRx_EL2
	4824	+Field 63 DVI63
	4825	+Field 62 DVI62
	4826	+Field 61 DVI61
	4827	+Field 60 DVI60
	4828	+Field 59 DVI59
	4829	+Field 58 DVI58
	4830	+Field 57 DVI57
	4831	+Field 56 DVI56
	4832	+Field 55 DVI55
	4833	+Field 54 DVI54
	4834	+Field 53 DVI53
	4835	+Field 52 DVI52
	4836	+Field 51 DVI51
	4837	+Field 50 DVI50
	4838	+Field 49 DVI49
	4839	+Field 48 DVI48
	4840	+Field 47 DVI47
	4841	+Field 46 DVI46
	4842	+Field 45 DVI45
	4843	+Field 44 DVI44
	4844	+Field 43 DVI43
	4845	+Field 42 DVI42
	4846	+Field 41 DVI41
	4847	+Field 40 DVI40
	4848	+Field 39 DVI39
	4849	+Field 38 DVI38
	4850	+Field 37 DVI37
	4851	+Field 36 DVI36
	4852	+Field 35 DVI35
	4853	+Field 34 DVI34
	4854	+Field 33 DVI33
	4855	+Field 32 DVI32
	4856	+Field 31 DVI31
	4857	+Field 30 DVI30
	4858	+Field 29 DVI29
	4859	+Field 28 DVI28
	4860	+Field 27 DVI27
	4861	+Field 26 DVI26
	4862	+Field 25 DVI25
	4863	+Field 24 DVI24
	4864	+Field 23 DVI23
	4865	+Field 22 DVI22
	4866	+Field 21 DVI21
	4867	+Field 20 DVI20
	4868	+Field 19 DVI19
	4869	+Field 18 DVI18
	4870	+Field 17 DVI17
	4871	+Field 16 DVI16
	4872	+Field 15 DVI15
	4873	+Field 14 DVI14
	4874	+Field 13 DVI13
	4875	+Field 12 DVI12
	4876	+Field 11 DVI11
	4877	+Field 10 DVI10
	4878	+Field 9 DVI9
	4879	+Field 8 DVI8
	4880	+Field 7 DVI7
	4881	+Field 6 DVI6
	4882	+Field 5 DVI5
	4883	+Field 4 DVI4
	4884	+Field 3 DVI3
	4885	+Field 2 DVI2
	4886	+Field 1 DVI1
	4887	+Field 0 DVI0
	4888	+EndSysregFields
	4889	+
	4890	+Sysreg ICH_PPI_DVIR0_EL2 3 4 12 10 0
	4891	+Fields ICH_PPI_DVIx_EL2
	4892	+EndSysreg
	4893	+
	4894	+Sysreg ICH_PPI_DVIR1_EL2 3 4 12 10 1
	4895	+Fields ICH_PPI_DVIx_EL2
	4896	+EndSysreg
	4897	+
	4898	+SysregFields ICH_PPI_ENABLERx_EL2
	4899	+Field 63 EN63
	4900	+Field 62 EN62
	4901	+Field 61 EN61
	4902	+Field 60 EN60
	4903	+Field 59 EN59
	4904	+Field 58 EN58
	4905	+Field 57 EN57
	4906	+Field 56 EN56
	4907	+Field 55 EN55
	4908	+Field 54 EN54
	4909	+Field 53 EN53
	4910	+Field 52 EN52
	4911	+Field 51 EN51
	4912	+Field 50 EN50
	4913	+Field 49 EN49
	4914	+Field 48 EN48
	4915	+Field 47 EN47
	4916	+Field 46 EN46
	4917	+Field 45 EN45
	4918	+Field 44 EN44
	4919	+Field 43 EN43
	4920	+Field 42 EN42
	4921	+Field 41 EN41
	4922	+Field 40 EN40
	4923	+Field 39 EN39
	4924	+Field 38 EN38
	4925	+Field 37 EN37
	4926	+Field 36 EN36
	4927	+Field 35 EN35
	4928	+Field 34 EN34
	4929	+Field 33 EN33
	4930	+Field 32 EN32
	4931	+Field 31 EN31
	4932	+Field 30 EN30
	4933	+Field 29 EN29
	4934	+Field 28 EN28
	4935	+Field 27 EN27
	4936	+Field 26 EN26
	4937	+Field 25 EN25
	4938	+Field 24 EN24
	4939	+Field 23 EN23
	4940	+Field 22 EN22
	4941	+Field 21 EN21
	4942	+Field 20 EN20
	4943	+Field 19 EN19
	4944	+Field 18 EN18
	4945	+Field 17 EN17
	4946	+Field 16 EN16
	4947	+Field 15 EN15
	4948	+Field 14 EN14
	4949	+Field 13 EN13
	4950	+Field 12 EN12
	4951	+Field 11 EN11
	4952	+Field 10 EN10
	4953	+Field 9 EN9
	4954	+Field 8 EN8
	4955	+Field 7 EN7
	4956	+Field 6 EN6
	4957	+Field 5 EN5
	4958	+Field 4 EN4
	4959	+Field 3 EN3
	4960	+Field 2 EN2
	4961	+Field 1 EN1
	4962	+Field 0 EN0
	4963	+EndSysregFields
	4964	+
	4965	+Sysreg ICH_PPI_ENABLER0_EL2 3 4 12 10 2
	4966	+Fields ICH_PPI_ENABLERx_EL2
	4967	+EndSysreg
	4968	+
	4969	+Sysreg ICH_PPI_ENABLER1_EL2 3 4 12 10 3
	4970	+Fields ICH_PPI_ENABLERx_EL2
	4971	+EndSysreg
	4972	+
	4973	+SysregFields ICH_PPI_PENDRx_EL2
	4974	+Field 63 PEND63
	4975	+Field 62 PEND62
	4976	+Field 61 PEND61
	4977	+Field 60 PEND60
	4978	+Field 59 PEND59
	4979	+Field 58 PEND58
	4980	+Field 57 PEND57
	4981	+Field 56 PEND56
	4982	+Field 55 PEND55
	4983	+Field 54 PEND54
	4984	+Field 53 PEND53
	4985	+Field 52 PEND52
	4986	+Field 51 PEND51
	4987	+Field 50 PEND50
	4988	+Field 49 PEND49
	4989	+Field 48 PEND48
	4990	+Field 47 PEND47
	4991	+Field 46 PEND46
	4992	+Field 45 PEND45
	4993	+Field 44 PEND44
	4994	+Field 43 PEND43
	4995	+Field 42 PEND42
	4996	+Field 41 PEND41
	4997	+Field 40 PEND40
	4998	+Field 39 PEND39
	4999	+Field 38 PEND38
	5000	+Field 37 PEND37
	5001	+Field 36 PEND36
	5002	+Field 35 PEND35
	5003	+Field 34 PEND34
	5004	+Field 33 PEND33
	5005	+Field 32 PEND32
	5006	+Field 31 PEND31
	5007	+Field 30 PEND30
	5008	+Field 29 PEND29
	5009	+Field 28 PEND28
	5010	+Field 27 PEND27
	5011	+Field 26 PEND26
	5012	+Field 25 PEND25
	5013	+Field 24 PEND24
	5014	+Field 23 PEND23
	5015	+Field 22 PEND22
	5016	+Field 21 PEND21
	5017	+Field 20 PEND20
	5018	+Field 19 PEND19
	5019	+Field 18 PEND18
	5020	+Field 17 PEND17
	5021	+Field 16 PEND16
	5022	+Field 15 PEND15
	5023	+Field 14 PEND14
	5024	+Field 13 PEND13
	5025	+Field 12 PEND12
	5026	+Field 11 PEND11
	5027	+Field 10 PEND10
	5028	+Field 9 PEND9
	5029	+Field 8 PEND8
	5030	+Field 7 PEND7
	5031	+Field 6 PEND6
	5032	+Field 5 PEND5
	5033	+Field 4 PEND4
	5034	+Field 3 PEND3
	5035	+Field 2 PEND2
	5036	+Field 1 PEND1
	5037	+Field 0 PEND0
	5038	+EndSysregFields
	5039	+
	5040	+Sysreg ICH_PPI_PENDR0_EL2 3 4 12 10 4
	5041	+Fields ICH_PPI_PENDRx_EL2
	5042	+EndSysreg
	5043	+
	5044	+Sysreg ICH_PPI_PENDR1_EL2 3 4 12 10 5
	5045	+Fields ICH_PPI_PENDRx_EL2
	5046	+EndSysreg
	5047	+
	5048	+SysregFields ICH_PPI_ACTIVERx_EL2
	5049	+Field 63 ACTIVE63
	5050	+Field 62 ACTIVE62
	5051	+Field 61 ACTIVE61
	5052	+Field 60 ACTIVE60
	5053	+Field 59 ACTIVE59
	5054	+Field 58 ACTIVE58
	5055	+Field 57 ACTIVE57
	5056	+Field 56 ACTIVE56
	5057	+Field 55 ACTIVE55
	5058	+Field 54 ACTIVE54
	5059	+Field 53 ACTIVE53
	5060	+Field 52 ACTIVE52
	5061	+Field 51 ACTIVE51
	5062	+Field 50 ACTIVE50
	5063	+Field 49 ACTIVE49
	5064	+Field 48 ACTIVE48
	5065	+Field 47 ACTIVE47
	5066	+Field 46 ACTIVE46
	5067	+Field 45 ACTIVE45
	5068	+Field 44 ACTIVE44
	5069	+Field 43 ACTIVE43
	5070	+Field 42 ACTIVE42
	5071	+Field 41 ACTIVE41
	5072	+Field 40 ACTIVE40
	5073	+Field 39 ACTIVE39
	5074	+Field 38 ACTIVE38
	5075	+Field 37 ACTIVE37
	5076	+Field 36 ACTIVE36
	5077	+Field 35 ACTIVE35
	5078	+Field 34 ACTIVE34
	5079	+Field 33 ACTIVE33
	5080	+Field 32 ACTIVE32
	5081	+Field 31 ACTIVE31
	5082	+Field 30 ACTIVE30
	5083	+Field 29 ACTIVE29
	5084	+Field 28 ACTIVE28
	5085	+Field 27 ACTIVE27
	5086	+Field 26 ACTIVE26
	5087	+Field 25 ACTIVE25
	5088	+Field 24 ACTIVE24
	5089	+Field 23 ACTIVE23
	5090	+Field 22 ACTIVE22
	5091	+Field 21 ACTIVE21
	5092	+Field 20 ACTIVE20
	5093	+Field 19 ACTIVE19
	5094	+Field 18 ACTIVE18
	5095	+Field 17 ACTIVE17
	5096	+Field 16 ACTIVE16
	5097	+Field 15 ACTIVE15
	5098	+Field 14 ACTIVE14
	5099	+Field 13 ACTIVE13
	5100	+Field 12 ACTIVE12
	5101	+Field 11 ACTIVE11
	5102	+Field 10 ACTIVE10
	5103	+Field 9 ACTIVE9
	5104	+Field 8 ACTIVE8
	5105	+Field 7 ACTIVE7
	5106	+Field 6 ACTIVE6
	5107	+Field 5 ACTIVE5
	5108	+Field 4 ACTIVE4
	5109	+Field 3 ACTIVE3
	5110	+Field 2 ACTIVE2
	5111	+Field 1 ACTIVE1
	5112	+Field 0 ACTIVE0
	5113	+EndSysregFields
	5114	+
	5115	+Sysreg ICH_PPI_ACTIVER0_EL2 3 4 12 10 6
	5116	+Fields ICH_PPI_ACTIVERx_EL2
	5117	+EndSysreg
	5118	+
	5119	+Sysreg ICH_PPI_ACTIVER1_EL2 3 4 12 10 7
	5120	+Fields ICH_PPI_ACTIVERx_EL2
	5121	+EndSysreg
	5122	+
4738	5123	Sysreg ICH_HCR_EL2 3 4 12 11 0
4739	5124	Res0 63:32
4740	5125	Field 31:27 EOIcount
@@ -4789,6 +5174,18 @@ Field 1 V3 · 48 unmodified lines
4789	5174	Field 0 En
4790	5175	EndSysreg
4791	5176
	5177	+Sysreg ICH_CONTEXTR_EL2 3 4 12 11 6
	5178	+Field 63 V
	5179	+Field 62 F
	5180	+Field 61 IRICHPPIDIS
	5181	+Field 60 DB
	5182	+Field 59:55 DBPM
	5183	+Res0 54:48
	5184	+Field 47:32 VPE
	5185	+Res0 31:16
	5186	+Field 15:0 VM
	5187	+EndSysreg
	5188	+
4792	5189	Sysreg ICH_VMCR_EL2 3 4 12 11 7
4793	5190	Prefix FEAT_GCIE
4794	5191	Res0 63:32
@@ -4810,6 +5207,89 @@ Field 1 VENG1 · 15 unmodified lines
4810	5207	Field 0 VENG0
4811	5208	EndSysreg
4812	5209
	5210	+SysregFields ICH_PPI_PRIORITYRx_EL2
	5211	+Res0 63:61
	5212	+Field 60:56 Priority7
	5213	+Res0 55:53
	5214	+Field 52:48 Priority6
	5215	+Res0 47:45
	5216	+Field 44:40 Priority5
	5217	+Res0 39:37
	5218	+Field 36:32 Priority4
	5219	+Res0 31:29
	5220	+Field 28:24 Priority3
	5221	+Res0 23:21
	5222	+Field 20:16 Priority2
	5223	+Res0 15:13
	5224	+Field 12:8 Priority1
	5225	+Res0 7:5
	5226	+Field 4:0 Priority0
	5227	+EndSysregFields
	5228	+
	5229	+Sysreg ICH_PPI_PRIORITYR0_EL2 3 4 12 14 0
	5230	+Fields ICH_PPI_PRIORITYRx_EL2
	5231	+EndSysreg
	5232	+
	5233	+Sysreg ICH_PPI_PRIORITYR1_EL2 3 4 12 14 1
	5234	+Fields ICH_PPI_PRIORITYRx_EL2
	5235	+EndSysreg
	5236	+
	5237	+Sysreg ICH_PPI_PRIORITYR2_EL2 3 4 12 14 2
	5238	+Fields ICH_PPI_PRIORITYRx_EL2
	5239	+EndSysreg
	5240	+
	5241	+Sysreg ICH_PPI_PRIORITYR3_EL2 3 4 12 14 3
	5242	+Fields ICH_PPI_PRIORITYRx_EL2
	5243	+EndSysreg
	5244	+
	5245	+Sysreg ICH_PPI_PRIORITYR4_EL2 3 4 12 14 4
	5246	+Fields ICH_PPI_PRIORITYRx_EL2
	5247	+EndSysreg
	5248	+
	5249	+Sysreg ICH_PPI_PRIORITYR5_EL2 3 4 12 14 5
	5250	+Fields ICH_PPI_PRIORITYRx_EL2
	5251	+EndSysreg
	5252	+
	5253	+Sysreg ICH_PPI_PRIORITYR6_EL2 3 4 12 14 6
	5254	+Fields ICH_PPI_PRIORITYRx_EL2
	5255	+EndSysreg
	5256	+
	5257	+Sysreg ICH_PPI_PRIORITYR7_EL2 3 4 12 14 7
	5258	+Fields ICH_PPI_PRIORITYRx_EL2
	5259	+EndSysreg
	5260	+
	5261	+Sysreg ICH_PPI_PRIORITYR8_EL2 3 4 12 15 0
	5262	+Fields ICH_PPI_PRIORITYRx_EL2
	5263	+EndSysreg
	5264	+
	5265	+Sysreg ICH_PPI_PRIORITYR9_EL2 3 4 12 15 1
	5266	+Fields ICH_PPI_PRIORITYRx_EL2
	5267	+EndSysreg
	5268	+
	5269	+Sysreg ICH_PPI_PRIORITYR10_EL2 3 4 12 15 2
	5270	+Fields ICH_PPI_PRIORITYRx_EL2
	5271	+EndSysreg
	5272	+
	5273	+Sysreg ICH_PPI_PRIORITYR11_EL2 3 4 12 15 3
	5274	+Fields ICH_PPI_PRIORITYRx_EL2
	5275	+EndSysreg
	5276	+
	5277	+Sysreg ICH_PPI_PRIORITYR12_EL2 3 4 12 15 4
	5278	+Fields ICH_PPI_PRIORITYRx_EL2
	5279	+EndSysreg
	5280	+
	5281	+Sysreg ICH_PPI_PRIORITYR13_EL2 3 4 12 15 5
	5282	+Fields ICH_PPI_PRIORITYRx_EL2
	5283	+EndSysreg
	5284	+
	5285	+Sysreg ICH_PPI_PRIORITYR14_EL2 3 4 12 15 6
	5286	+Fields ICH_PPI_PRIORITYRx_EL2
	5287	+EndSysreg
	5288	+
	5289	+Sysreg ICH_PPI_PRIORITYR15_EL2 3 4 12 15 7
	5290	+Fields ICH_PPI_PRIORITYRx_EL2
	5291	+EndSysreg
	5292	+
4813	5293	Sysreg CONTEXTIDR_EL2 3 4 13 0 1
4814	5294	Fields CONTEXTIDR_ELx
4815	5295	EndSysreg

drivers/irqchip/irq-gic-v5.c+18−0

@@ -511,6 +511,23 @@ static bool gicv5_ppi_irq_is_level(irq_hw_number_t hwirq) · 510 unmodified lines
511	511	return !!(read_ppi_sysreg_s(hwirq, PPI_HM) & bit);
512	512	}
513	513
	514	+static int gicv5_ppi_irq_set_type(struct irq_data *d, unsigned int type)
	515	+{
	516	+ /*
	517	+ * GICv5's PPIs do not have a configurable trigger or handling
	518	+ * mode. Check that the attempt to set a type matches what the
	519	+ * hardware reports in the HMR, and error on a mismatch.
	520	+ */
	521	+
	522	+ if (type & IRQ_TYPE_EDGE_BOTH && gicv5_ppi_irq_is_level(d->hwirq))
	523	+ return -EINVAL;
	524	+
	525	+ if (type & IRQ_TYPE_LEVEL_MASK && !gicv5_ppi_irq_is_level(d->hwirq))
	526	+ return -EINVAL;
	527	+
	528	+ return 0;
	529	+}
	530	+
514	531	static int gicv5_ppi_irq_set_vcpu_affinity(struct irq_data d, void vcpu)
515	532	{
516	533	if (vcpu)
@@ -526,6 +543,7 @@ static const struct irq_chip gicv5_ppi_irq_chip = { · 9 unmodified lines
526	543	.irq_mask = gicv5_ppi_irq_mask,
527	544	.irq_unmask = gicv5_ppi_irq_unmask,
528	545	.irq_eoi = gicv5_ppi_irq_eoi,
	546	+ .irq_set_type = gicv5_ppi_irq_set_type,
529	547	.irq_get_irqchip_state = gicv5_ppi_irq_get_irqchip_state,
530	548	.irq_set_irqchip_state = gicv5_ppi_irq_set_irqchip_state,
531	549	.irq_set_vcpu_affinity = gicv5_ppi_irq_set_vcpu_affinity,

include/kvm/arm_arch_timer.h+10−1

@@ -10,6 +10,8 @@ · 9 unmodified lines
10	10	#include <linux/clocksource.h>
11	11	#include <linux/hrtimer.h>
12	12
	13	+#include <linux/irqchip/arm-gic-v5.h>
	14	+
13	15	enum kvm_arch_timers {
14	16	TIMER_PTIMER,
15	17	TIMER_VTIMER,
@@ -47,7 +49,7 @@ struct arch_timer_vm_data { · 31 unmodified lines
47	49	u64 poffset;
48	50
49	51	/* The PPI for each timer, global to the VM */
50		− u8 ppi[NR_KVM_TIMERS];
	52	+ u32 ppi[NR_KVM_TIMERS];
51	53	};
52	54
53	55	struct arch_timer_context {
@@ -74,6 +76,9 @@ struct arch_timer_context { · 20 unmodified lines
74	76
75	77	/* Duplicated state from arch_timer.c for convenience */
76	78	u32 host_timer_irq;
	79	+
	80	+ /* Is this a direct timer? */
	81	+ bool direct;
77	82	};
78	83
79	84	struct timer_map {
@@ -130,6 +135,10 @@ void kvm_timer_init_vhe(void); · 50 unmodified lines
130	135	#define timer_vm_data(ctx) (&(timer_context_to_vcpu(ctx)->kvm->arch.timer_data))
131	136	#define timer_irq(ctx) (timer_vm_data(ctx)->ppi[arch_timer_ctx_index(ctx)])
132	137
	138	+#define get_vgic_ppi(k, i) (((k)->arch.vgic.vgic_model != KVM_DEV_TYPE_ARM_VGIC_V5) ? \
	139	+ (i) : (FIELD_PREP(GICV5_HWIRQ_ID, i) \| \
	140	+ FIELD_PREP(GICV5_HWIRQ_TYPE, GICV5_HWIRQ_TYPE_PPI)))
	141	+
133	142	u64 kvm_arm_timer_read_sysreg(struct kvm_vcpu *vcpu,
134	143	enum kvm_arch_timers tmr,
135	144	enum kvm_arch_timer_regs treg);

include/kvm/arm_pmu.h+4−1

@@ -12,6 +12,9 @@ · 11 unmodified lines
12	12
13	13	#define KVM_ARMV8_PMU_MAX_COUNTERS 32
14	14
	15	+/* PPI #23 - architecturally specified for GICv5 */
	16	+#define KVM_ARMV8_PMU_GICV5_IRQ 0x20000017
	17	+
15	18	#if IS_ENABLED(CONFIG_HW_PERF_EVENTS) && IS_ENABLED(CONFIG_KVM)
16	19	struct kvm_pmc {
17	20	u8 idx; /* index into the pmu->pmc array */
@@ -38,7 +41,7 @@ struct arm_pmu_entry { · 20 unmodified lines
38	41	};
39	42
40	43	bool kvm_supports_guest_pmuv3(void);
41		−#define kvm_arm_pmu_irq_initialized(v) ((v)->arch.pmu.irq_num >= VGIC_NR_SGIS)
	44	+#define kvm_arm_pmu_irq_initialized(v) ((v)->arch.pmu.irq_num != 0)
42	45	u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx);
43	46	void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu, u64 select_idx, u64 val);
44	47	void kvm_pmu_set_counter_value_user(struct kvm_vcpu *vcpu, u64 select_idx, u64 val);

include/kvm/arm_vgic.h+185−6

@@ -19,7 +19,9 @@ · 18 unmodified lines
19	19	#include <linux/jump_label.h>
20	20
21	21	#include <linux/irqchip/arm-gic-v4.h>
	22	+#include <linux/irqchip/arm-gic-v5.h>
22	23
	24	+#define VGIC_V5_MAX_CPUS 512
23	25	#define VGIC_V3_MAX_CPUS 512
24	26	#define VGIC_V2_MAX_CPUS 8
25	27	#define VGIC_NR_IRQS_LEGACY 256
@@ -31,9 +33,96 @@ · 5 unmodified lines
31	33	#define VGIC_MIN_LPI 8192
32	34	#define KVM_IRQCHIP_NUM_PINS (1020 - 32)
33	35
34		−#define irq_is_ppi(irq) ((irq) >= VGIC_NR_SGIS && (irq) < VGIC_NR_PRIVATE_IRQS)
35		−#define irq_is_spi(irq) ((irq) >= VGIC_NR_PRIVATE_IRQS && \
36		− (irq) <= VGIC_MAX_SPI)
	36	+/*
	37	+ * GICv5 supports 128 PPIs, but only the first 64 are architected. We only
	38	+ * support the timers and PMU in KVM, both of which are architected. Rather than
	39	+ * handling twice the state, we instead opt to only support the architected set
	40	+ * in KVM for now. At a future stage, this can be bumped up to 128, if required.
	41	+ */
	42	+#define VGIC_V5_NR_PRIVATE_IRQS 64
	43	+
	44	+#define is_v5_type(t, i) (FIELD_GET(GICV5_HWIRQ_TYPE, (i)) == (t))
	45	+
	46	+#define __irq_is_sgi(t, i) \
	47	+ ({ \
	48	+ bool __ret; \
	49	+ \
	50	+ switch (t) { \
	51	+ case KVM_DEV_TYPE_ARM_VGIC_V5: \
	52	+ __ret = false; \
	53	+ break; \
	54	+ default: \
	55	+ __ret = (i) < VGIC_NR_SGIS; \
	56	+ } \
	57	+ \
	58	+ __ret; \
	59	+ })
	60	+
	61	+#define __irq_is_ppi(t, i) \
	62	+ ({ \
	63	+ bool __ret; \
	64	+ \
	65	+ switch (t) { \
	66	+ case KVM_DEV_TYPE_ARM_VGIC_V5: \
	67	+ __ret = is_v5_type(GICV5_HWIRQ_TYPE_PPI, (i)); \
	68	+ break; \
	69	+ default: \
	70	+ __ret = (i) >= VGIC_NR_SGIS; \
	71	+ __ret &= (i) < VGIC_NR_PRIVATE_IRQS; \
	72	+ } \
	73	+ \
	74	+ __ret; \
	75	+ })
	76	+
	77	+#define __irq_is_spi(t, i) \
	78	+ ({ \
	79	+ bool __ret; \
	80	+ \
	81	+ switch (t) { \
	82	+ case KVM_DEV_TYPE_ARM_VGIC_V5: \
	83	+ __ret = is_v5_type(GICV5_HWIRQ_TYPE_SPI, (i)); \
	84	+ break; \
	85	+ default: \
	86	+ __ret = (i) <= VGIC_MAX_SPI; \
	87	+ __ret &= (i) >= VGIC_NR_PRIVATE_IRQS; \
	88	+ } \
	89	+ \
	90	+ __ret; \
	91	+ })
	92	+
	93	+#define __irq_is_lpi(t, i) \
	94	+ ({ \
	95	+ bool __ret; \
	96	+ \
	97	+ switch (t) { \
	98	+ case KVM_DEV_TYPE_ARM_VGIC_V5: \
	99	+ __ret = is_v5_type(GICV5_HWIRQ_TYPE_LPI, (i)); \
	100	+ break; \
	101	+ default: \
	102	+ __ret = (i) >= 8192; \
	103	+ } \
	104	+ \
	105	+ __ret; \
	106	+ })
	107	+
	108	+#define irq_is_sgi(k, i) __irq_is_sgi((k)->arch.vgic.vgic_model, i)
	109	+#define irq_is_ppi(k, i) __irq_is_ppi((k)->arch.vgic.vgic_model, i)
	110	+#define irq_is_spi(k, i) __irq_is_spi((k)->arch.vgic.vgic_model, i)
	111	+#define irq_is_lpi(k, i) __irq_is_lpi((k)->arch.vgic.vgic_model, i)
	112	+
	113	+#define irq_is_private(k, i) (irq_is_ppi(k, i) \|\| irq_is_sgi(k, i))
	114	+
	115	+#define vgic_v5_get_hwirq_id(x) FIELD_GET(GICV5_HWIRQ_ID, (x))
	116	+#define vgic_v5_set_hwirq_id(x) FIELD_PREP(GICV5_HWIRQ_ID, (x))
	117	+
	118	+#define __vgic_v5_set_type(t) (FIELD_PREP(GICV5_HWIRQ_TYPE, GICV5_HWIRQ_TYPE_##t))
	119	+#define vgic_v5_make_ppi(x) (__vgic_v5_set_type(PPI) \| vgic_v5_set_hwirq_id(x))
	120	+#define vgic_v5_make_spi(x) (__vgic_v5_set_type(SPI) \| vgic_v5_set_hwirq_id(x))
	121	+#define vgic_v5_make_lpi(x) (__vgic_v5_set_type(LPI) \| vgic_v5_set_hwirq_id(x))
	122	+
	123	+#define __vgic_is_v(k, v) ((k)->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V##v)
	124	+#define vgic_is_v3(k) (__vgic_is_v(k, 3))
	125	+#define vgic_is_v5(k) (__vgic_is_v(k, 5))
37	126
38	127	enum vgic_type {
39	128	VGIC_V2, /* Good ol' GICv2 */
@@ -101,6 +190,8 @@ enum vgic_irq_config { · 61 unmodified lines
101	190	VGIC_CONFIG_LEVEL
102	191	};
103	192
	193	+struct vgic_irq;
	194	+
104	195	/*
105	196	* Per-irq ops overriding some common behavious.
106	197	*
@@ -119,6 +210,19 @@ struct irq_ops { · 12 unmodified lines
119	210	* peaking into the physical GIC.
120	211	*/
121	212	bool (*get_input_level)(int vintid);
	213	+
	214	+ /*
	215	+ * Function pointer to override the queuing of an IRQ.
	216	+ */
	217	+ bool (queue_irq_unlock)(struct kvm kvm, struct vgic_irq *irq,
	218	+ unsigned long flags) __releases(&irq->irq_lock);
	219	+
	220	+ /*
	221	+ * Callback function pointer to either enable or disable direct
	222	+ * injection for a mapped interrupt.
	223	+ */
	224	+ void (set_direct_injection)(struct kvm_vcpu vcpu,
	225	+ struct vgic_irq *irq, bool direct);
122	226	};
123	227
124	228	struct vgic_irq {
@@ -238,6 +342,26 @@ struct vgic_redist_region { · 113 unmodified lines
238	342	struct list_head list;
239	343	};
240	344
	345	+struct vgic_v5_vm {
	346	+ /*
	347	+ * We only expose a subset of PPIs to the guest. This subset is a
	348	+ * combination of the PPIs that are actually implemented and what we
	349	+ * actually choose to expose.
	350	+ */
	351	+ DECLARE_BITMAP(vgic_ppi_mask, VGIC_V5_NR_PRIVATE_IRQS);
	352	+
	353	+ /* A mask of the PPIs that are exposed for userspace to drive. */
	354	+ DECLARE_BITMAP(userspace_ppis, VGIC_V5_NR_PRIVATE_IRQS);
	355	+
	356	+ /*
	357	+ * The HMR itself is handled by the hardware, but we still need to have
	358	+ * a mask that we can use when merging in pending state (only the state
	359	+ * of Edge PPIs is merged back in from the guest an the HMR provides a
	360	+ * convenient way to do that).
	361	+ */
	362	+ DECLARE_BITMAP(vgic_ppi_hmr, VGIC_V5_NR_PRIVATE_IRQS);
	363	+};
	364	+
241	365	struct vgic_dist {
242	366	bool in_kernel;
243	367	bool ready;
@@ -310,6 +434,11 @@ struct vgic_dist { · 66 unmodified lines
310	434	* else.
311	435	*/
312	436	struct its_vm its_vm;
	437	+
	438	+ /*
	439	+ * GICv5 per-VM data.
	440	+ */
	441	+ struct vgic_v5_vm gicv5_vm;
313	442	};
314	443
315	444	struct vgic_v2_cpu_if {
@@ -340,11 +469,40 @@ struct vgic_v3_cpu_if { · 24 unmodified lines
340	469	unsigned int used_lrs;
341	470	};
342	471
	472	+struct vgic_v5_cpu_if {
	473	+ u64 vgic_apr;
	474	+ u64 vgic_vmcr;
	475	+
	476	+ /* PPI register state */
	477	+ DECLARE_BITMAP(vgic_ppi_dvir, VGIC_V5_NR_PRIVATE_IRQS);
	478	+ DECLARE_BITMAP(vgic_ppi_activer, VGIC_V5_NR_PRIVATE_IRQS);
	479	+ DECLARE_BITMAP(vgic_ppi_enabler, VGIC_V5_NR_PRIVATE_IRQS);
	480	+ /* We have one byte (of which 5 bits are used) per PPI for priority */
	481	+ u64 vgic_ppi_priorityr[VGIC_V5_NR_PRIVATE_IRQS / 8];
	482	+
	483	+ /*
	484	+ * The ICSR is re-used across host and guest, and hence it needs to be
	485	+ * saved/restored. Only one copy is required as the host should block
	486	+ * preemption between executing GIC CDRCFG and acccessing the
	487	+ * ICC_ICSR_EL1. A guest, of course, can never guarantee this, and hence
	488	+ * it is the hyp's responsibility to keep the state constistent.
	489	+ */
	490	+ u64 vgic_icsr;
	491	+
	492	+ struct gicv5_vpe gicv5_vpe;
	493	+};
	494	+
	495	+/* What PPI capabilities does a GICv5 host have */
	496	+struct vgic_v5_ppi_caps {
	497	+ DECLARE_BITMAP(impl_ppi_mask, VGIC_V5_NR_PRIVATE_IRQS);
	498	+};
	499	+
343	500	struct vgic_cpu {
344	501	/* CPU vif control registers for world switch */
345	502	union {
346	503	struct vgic_v2_cpu_if vgic_v2;
347	504	struct vgic_v3_cpu_if vgic_v3;
	505	+ struct vgic_v5_cpu_if vgic_v5;
348	506	};
349	507
350	508	struct vgic_irq *private_irqs;
@@ -392,13 +550,17 @@ int kvm_vgic_create(struct kvm *kvm, u32 type); · 41 unmodified lines
392	550	void kvm_vgic_destroy(struct kvm *kvm);
393	551	void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu);
394	552	int kvm_vgic_map_resources(struct kvm *kvm);
	553	+void kvm_vgic_finalize_idregs(struct kvm *kvm);
395	554	int kvm_vgic_hyp_init(void);
396	555	void kvm_vgic_init_cpu_hardware(void);
397	556
398	557	int kvm_vgic_inject_irq(struct kvm kvm, struct kvm_vcpu vcpu,
399	558	unsigned int intid, bool level, void *owner);
	559	+void kvm_vgic_set_irq_ops(struct kvm_vcpu *vcpu, u32 vintid,
	560	+ struct irq_ops *ops);
	561	+void kvm_vgic_clear_irq_ops(struct kvm_vcpu *vcpu, u32 vintid);
400	562	int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, unsigned int host_irq,
401		− u32 vintid, struct irq_ops *ops);
	563	+ u32 vintid);
402	564	int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, unsigned int vintid);
403	565	int kvm_vgic_get_map(struct kvm_vcpu *vcpu, unsigned int vintid);
404	566	bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int vintid);
@@ -414,8 +576,20 @@ u64 vgic_v3_get_misr(struct kvm_vcpu *vcpu); · 9 unmodified lines
414	576
415	577	#define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel))
416	578	#define vgic_initialized(k) ((k)->arch.vgic.initialized)
417		−#define vgic_valid_spi(k, i) (((i) >= VGIC_NR_PRIVATE_IRQS) && \
418		− ((i) < (k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS))
	579	+#define vgic_valid_spi(k, i) \
	580	+ ({ \
	581	+ bool __ret = irq_is_spi(k, i); \
	582	+ \
	583	+ switch ((k)->arch.vgic.vgic_model) { \
	584	+ case KVM_DEV_TYPE_ARM_VGIC_V5: \
	585	+ __ret &= FIELD_GET(GICV5_HWIRQ_ID, i) < (k)->arch.vgic.nr_spis; \
	586	+ break; \
	587	+ default: \
	588	+ __ret &= (i) < ((k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS); \
	589	+ } \
	590	+ \
	591	+ __ret; \
	592	+ })
419	593
420	594	bool kvm_vcpu_has_pending_irqs(struct kvm_vcpu *vcpu);
421	595	void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
@@ -455,6 +629,11 @@ int vgic_v4_load(struct kvm_vcpu *vcpu); · 33 unmodified lines
455	629	void vgic_v4_commit(struct kvm_vcpu *vcpu);
456	630	int vgic_v4_put(struct kvm_vcpu *vcpu);
457	631
	632	+int vgic_v5_finalize_ppi_state(struct kvm *kvm);
	633	+bool vgic_v5_ppi_queue_irq_unlock(struct kvm kvm, struct vgic_irq irq,
	634	+ unsigned long flags);
	635	+void vgic_v5_set_ppi_dvi(struct kvm_vcpu vcpu, struct vgic_irq irq, bool dvi);
	636	+
458	637	bool vgic_state_is_nested(struct kvm_vcpu *vcpu);
459	638
460	639	/* CPU HP callbacks */

include/linux/irqchip/arm-gic-v5.h+27−0

@@ -24,6 +24,28 @@ · 23 unmodified lines
24	24	#define GICV5_HWIRQ_TYPE_LPI UL(0x2)
25	25	#define GICV5_HWIRQ_TYPE_SPI UL(0x3)
26	26
	27	+/*
	28	+ * Architected PPIs
	29	+ */
	30	+#define GICV5_ARCH_PPI_S_DB_PPI 0x0
	31	+#define GICV5_ARCH_PPI_RL_DB_PPI 0x1
	32	+#define GICV5_ARCH_PPI_NS_DB_PPI 0x2
	33	+#define GICV5_ARCH_PPI_SW_PPI 0x3
	34	+#define GICV5_ARCH_PPI_HACDBSIRQ 0xf
	35	+#define GICV5_ARCH_PPI_CNTHVS 0x13
	36	+#define GICV5_ARCH_PPI_CNTHPS 0x14
	37	+#define GICV5_ARCH_PPI_PMBIRQ 0x15
	38	+#define GICV5_ARCH_PPI_COMMIRQ 0x16
	39	+#define GICV5_ARCH_PPI_PMUIRQ 0x17
	40	+#define GICV5_ARCH_PPI_CTIIRQ 0x18
	41	+#define GICV5_ARCH_PPI_GICMNT 0x19
	42	+#define GICV5_ARCH_PPI_CNTHP 0x1a
	43	+#define GICV5_ARCH_PPI_CNTV 0x1b
	44	+#define GICV5_ARCH_PPI_CNTHV 0x1c
	45	+#define GICV5_ARCH_PPI_CNTPS 0x1d
	46	+#define GICV5_ARCH_PPI_CNTP 0x1e
	47	+#define GICV5_ARCH_PPI_TRBIRQ 0x1f
	48	+
27	49	/*
28	50	* Tables attributes
29	51	*/
@@ -365,6 +387,11 @@ int gicv5_spi_irq_set_type(struct irq_data *d, unsigned int type); · 335 unmodified lines
365	387	int gicv5_irs_iste_alloc(u32 lpi);
366	388	void gicv5_irs_syncr(void);
367	389
	390	+/* Embedded in kvm.arch */
	391	+struct gicv5_vpe {
	392	+ bool resident;
	393	+};
	394	+
368	395	struct gicv5_its_devtab_cfg {
369	396	union {
370	397	struct {

include/linux/kvm_host.h+1−0

@@ -2366,6 +2366,7 @@ void kvm_unregister_device_ops(u32 type); · 2365 unmodified lines
2366	2366	extern struct kvm_device_ops kvm_mpic_ops;
2367	2367	extern struct kvm_device_ops kvm_arm_vgic_v2_ops;
2368	2368	extern struct kvm_device_ops kvm_arm_vgic_v3_ops;
	2369	+extern struct kvm_device_ops kvm_arm_vgic_v5_ops;
2369	2370
2370	2371	#ifdef CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT
2371	2372

include/uapi/linux/kvm.h+2−0

@@ -1224,6 +1224,8 @@ enum kvm_device_type { · 1223 unmodified lines
1224	1224	#define KVM_DEV_TYPE_LOONGARCH_EIOINTC KVM_DEV_TYPE_LOONGARCH_EIOINTC
1225	1225	KVM_DEV_TYPE_LOONGARCH_PCHPIC,
1226	1226	#define KVM_DEV_TYPE_LOONGARCH_PCHPIC KVM_DEV_TYPE_LOONGARCH_PCHPIC
	1227	+ KVM_DEV_TYPE_ARM_VGIC_V5,
	1228	+#define KVM_DEV_TYPE_ARM_VGIC_V5 KVM_DEV_TYPE_ARM_VGIC_V5
1227	1229
1228	1230	KVM_DEV_TYPE_MAX,
1229	1231

tools/arch/arm64/include/uapi/asm/kvm.h+1−0

@@ -428,6 +428,7 @@ enum { · 427 unmodified lines
428	428	#define KVM_DEV_ARM_ITS_RESTORE_TABLES 2
429	429	#define KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES 3
430	430	#define KVM_DEV_ARM_ITS_CTRL_RESET 4
	431	+#define KVM_DEV_ARM_VGIC_USERSPACE_PPIS 5
431	432
432	433	/* Device Control API on vcpu fd */
433	434	#define KVM_ARM_VCPU_PMU_V3_CTRL 0

tools/include/uapi/linux/kvm.h+2−0

@@ -1220,6 +1220,8 @@ enum kvm_device_type { · 1219 unmodified lines
1220	1220	#define KVM_DEV_TYPE_LOONGARCH_EIOINTC KVM_DEV_TYPE_LOONGARCH_EIOINTC
1221	1221	KVM_DEV_TYPE_LOONGARCH_PCHPIC,
1222	1222	#define KVM_DEV_TYPE_LOONGARCH_PCHPIC KVM_DEV_TYPE_LOONGARCH_PCHPIC
	1223	+ KVM_DEV_TYPE_ARM_VGIC_V5,
	1224	+#define KVM_DEV_TYPE_ARM_VGIC_V5 KVM_DEV_TYPE_ARM_VGIC_V5
1223	1225
1224	1226	KVM_DEV_TYPE_MAX,
1225	1227

tools/testing/selftests/kvm/Makefile.kvm+2−1

@@ -177,8 +177,9 @@ TEST_GEN_PROGS_arm64 += arm64/vcpu_width_config · 176 unmodified lines
177	177	TEST_GEN_PROGS_arm64 += arm64/vgic_init
178	178	TEST_GEN_PROGS_arm64 += arm64/vgic_irq
179	179	TEST_GEN_PROGS_arm64 += arm64/vgic_lpi_stress
	180	+TEST_GEN_PROGS_arm64 += arm64/vgic_v5
180	181	TEST_GEN_PROGS_arm64 += arm64/vpmu_counter_access
181		−TEST_GEN_PROGS_arm64 += arm64/no-vgic-v3
	182	+TEST_GEN_PROGS_arm64 += arm64/no-vgic
182	183	TEST_GEN_PROGS_arm64 += arm64/idreg-idst
183	184	TEST_GEN_PROGS_arm64 += arm64/kvm-uuid
184	185	TEST_GEN_PROGS_arm64 += access_tracking_perf_test

tools/testing/selftests/kvm/arm64/no-vgic-v3.c+0−177

@@ -1,177 +0,0 @@
1		−// SPDX-License-Identifier: GPL-2.0
2		−
3		−// Check that, on a GICv3 system, not configuring GICv3 correctly
4		−// results in all of the sysregs generating an UNDEF exception.
5		−
6		−#include <test_util.h>
7		−#include <kvm_util.h>
8		−#include <processor.h>
9		−
10		−static volatile bool handled;
11		−
12		−#define __check_sr_read(r) \
13		− ({ \
14		− uint64_t val; \
15		− \
16		− handled = false; \
17		− dsb(sy); \
18		− val = read_sysreg_s(SYS_ ## r); \
19		− val; \
20		− })
21		−
22		−#define __check_sr_write(r) \
23		− do { \
24		− handled = false; \
25		− dsb(sy); \
26		− write_sysreg_s(0, SYS_ ## r); \
27		− isb(); \
28		− } while(0)
29		−
30		−/* Fatal checks */
31		−#define check_sr_read(r) \
32		− do { \
33		− __check_sr_read(r); \
34		− __GUEST_ASSERT(handled, #r " no read trap"); \
35		− } while(0)
36		−
37		−#define check_sr_write(r) \
38		− do { \
39		− __check_sr_write(r); \
40		− __GUEST_ASSERT(handled, #r " no write trap"); \
41		− } while(0)
42		−
43		−#define check_sr_rw(r) \
44		− do { \
45		− check_sr_read(r); \
46		− check_sr_write(r); \
47		− } while(0)
48		−
49		−static void guest_code(void)
50		−{
51		− uint64_t val;
52		−
53		− /*
54		− * Check that we advertise that ID_AA64PFR0_EL1.GIC == 0, having
55		− * hidden the feature at runtime without any other userspace action.
56		− */
57		− __GUEST_ASSERT(FIELD_GET(ID_AA64PFR0_EL1_GIC,
58		− read_sysreg(id_aa64pfr0_el1)) == 0,
59		− "GICv3 wrongly advertised");
60		−
61		− /*
62		− * Access all GICv3 registers, and fail if we don't get an UNDEF.
63		− * Note that we happily access all the APxRn registers without
64		− * checking their existance, as all we want to see is a failure.
65		− */
66		− check_sr_rw(ICC_PMR_EL1);
67		− check_sr_read(ICC_IAR0_EL1);
68		− check_sr_write(ICC_EOIR0_EL1);
69		− check_sr_rw(ICC_HPPIR0_EL1);
70		− check_sr_rw(ICC_BPR0_EL1);
71		− check_sr_rw(ICC_AP0R0_EL1);
72		− check_sr_rw(ICC_AP0R1_EL1);
73		− check_sr_rw(ICC_AP0R2_EL1);
74		− check_sr_rw(ICC_AP0R3_EL1);
75		− check_sr_rw(ICC_AP1R0_EL1);
76		− check_sr_rw(ICC_AP1R1_EL1);
77		− check_sr_rw(ICC_AP1R2_EL1);
78		− check_sr_rw(ICC_AP1R3_EL1);
79		− check_sr_write(ICC_DIR_EL1);
80		− check_sr_read(ICC_RPR_EL1);
81		− check_sr_write(ICC_SGI1R_EL1);
82		− check_sr_write(ICC_ASGI1R_EL1);
83		− check_sr_write(ICC_SGI0R_EL1);
84		− check_sr_read(ICC_IAR1_EL1);
85		− check_sr_write(ICC_EOIR1_EL1);
86		− check_sr_rw(ICC_HPPIR1_EL1);
87		− check_sr_rw(ICC_BPR1_EL1);
88		− check_sr_rw(ICC_CTLR_EL1);
89		− check_sr_rw(ICC_IGRPEN0_EL1);
90		− check_sr_rw(ICC_IGRPEN1_EL1);
91		−
92		− /*
93		− * ICC_SRE_EL1 may not be trappable, as ICC_SRE_EL2.Enable can
94		− * be RAO/WI. Engage in non-fatal accesses, starting with a
95		− * write of 0 to try and disable SRE, and let's see if it
96		− * sticks.
97		− */
98		− __check_sr_write(ICC_SRE_EL1);
99		− if (!handled)
100		− GUEST_PRINTF("ICC_SRE_EL1 write not trapping (OK)\n");
101		−
102		− val = __check_sr_read(ICC_SRE_EL1);
103		− if (!handled) {
104		− __GUEST_ASSERT((val & BIT(0)),
105		− "ICC_SRE_EL1 not trapped but ICC_SRE_EL1.SRE not set\n");
106		− GUEST_PRINTF("ICC_SRE_EL1 read not trapping (OK)\n");
107		− }
108		−
109		− GUEST_DONE();
110		−}
111		−
112		−static void guest_undef_handler(struct ex_regs *regs)
113		−{
114		− /* Success, we've gracefully exploded! */
115		− handled = true;
116		− regs->pc += 4;
117		−}
118		−
119		−static void test_run_vcpu(struct kvm_vcpu *vcpu)
120		−{
121		− struct ucall uc;
122		−
123		− do {
124		− vcpu_run(vcpu);
125		−
126		− switch (get_ucall(vcpu, &uc)) {
127		− case UCALL_ABORT:
128		− REPORT_GUEST_ASSERT(uc);
129		− break;
130		− case UCALL_PRINTF:
131		− printf("%s", uc.buffer);
132		− break;
133		− case UCALL_DONE:
134		− break;
135		− default:
136		− TEST_FAIL("Unknown ucall %lu", uc.cmd);
137		− }
138		− } while (uc.cmd != UCALL_DONE);
139		−}
140		−
141		−static void test_guest_no_gicv3(void)
142		−{
143		− struct kvm_vcpu *vcpu;
144		− struct kvm_vm *vm;
145		−
146		− /* Create a VM without a GICv3 */
147		− vm = vm_create_with_one_vcpu(&vcpu, guest_code);
148		−
149		− vm_init_descriptor_tables(vm);
150		− vcpu_init_descriptor_tables(vcpu);
151		−
152		− vm_install_sync_handler(vm, VECTOR_SYNC_CURRENT,
153		− ESR_ELx_EC_UNKNOWN, guest_undef_handler);
154		−
155		− test_run_vcpu(vcpu);
156		−
157		− kvm_vm_free(vm);
158		−}
159		−
160		−int main(int argc, char *argv[])
161		−{
162		− struct kvm_vcpu *vcpu;
163		− struct kvm_vm *vm;
164		− uint64_t pfr0;
165		−
166		− test_disable_default_vgic();
167		−
168		− vm = vm_create_with_one_vcpu(&vcpu, NULL);
169		− pfr0 = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1));
170		− __TEST_REQUIRE(FIELD_GET(ID_AA64PFR0_EL1_GIC, pfr0),
171		− "GICv3 not supported.");
172		− kvm_vm_free(vm);
173		−
174		− test_guest_no_gicv3();
175		−
176		− return 0;
177		−}

tools/testing/selftests/kvm/arm64/no-vgic.c+297−0

@@ -0,0 +1,297 @@
	1	+// SPDX-License-Identifier: GPL-2.0
	2	+
	3	+// Check that, on a GICv3-capable system (GICv3 native, or GICv5 with
	4	+// FEAT_GCIE_LEGACY), not configuring GICv3 correctly results in all
	5	+// of the sysregs generating an UNDEF exception. Do the same for GICv5
	6	+// on a GICv5 host.
	7	+
	8	+#include <test_util.h>
	9	+#include <kvm_util.h>
	10	+#include <processor.h>
	11	+
	12	+#include <arm64/gic_v5.h>
	13	+
	14	+static volatile bool handled;
	15	+
	16	+#define __check_sr_read(r) \
	17	+ ({ \
	18	+ uint64_t val; \
	19	+ \
	20	+ handled = false; \
	21	+ dsb(sy); \
	22	+ val = read_sysreg_s(SYS_ ## r); \
	23	+ val; \
	24	+ })
	25	+
	26	+#define __check_sr_write(r) \
	27	+ do { \
	28	+ handled = false; \
	29	+ dsb(sy); \
	30	+ write_sysreg_s(0, SYS_ ## r); \
	31	+ isb(); \
	32	+ } while (0)
	33	+
	34	+#define __check_gicv5_gicr_op(r) \
	35	+ ({ \
	36	+ uint64_t val; \
	37	+ \
	38	+ handled = false; \
	39	+ dsb(sy); \
	40	+ val = read_sysreg_s(GICV5_OP_GICR_ ## r); \
	41	+ val; \
	42	+ })
	43	+
	44	+#define __check_gicv5_gic_op(r) \
	45	+ do { \
	46	+ handled = false; \
	47	+ dsb(sy); \
	48	+ write_sysreg_s(0, GICV5_OP_GIC_ ## r); \
	49	+ isb(); \
	50	+ } while (0)
	51	+
	52	+/* Fatal checks */
	53	+#define check_sr_read(r) \
	54	+ do { \
	55	+ __check_sr_read(r); \
	56	+ __GUEST_ASSERT(handled, #r " no read trap"); \
	57	+ } while (0)
	58	+
	59	+#define check_sr_write(r) \
	60	+ do { \
	61	+ __check_sr_write(r); \
	62	+ __GUEST_ASSERT(handled, #r " no write trap"); \
	63	+ } while (0)
	64	+
	65	+#define check_sr_rw(r) \
	66	+ do { \
	67	+ check_sr_read(r); \
	68	+ check_sr_write(r); \
	69	+ } while (0)
	70	+
	71	+#define check_gicv5_gicr_op(r) \
	72	+ do { \
	73	+ __check_gicv5_gicr_op(r); \
	74	+ __GUEST_ASSERT(handled, #r " no read trap"); \
	75	+ } while (0)
	76	+
	77	+#define check_gicv5_gic_op(r) \
	78	+ do { \
	79	+ __check_gicv5_gic_op(r); \
	80	+ __GUEST_ASSERT(handled, #r " no write trap"); \
	81	+ } while (0)
	82	+
	83	+static void guest_code_gicv3(void)
	84	+{
	85	+ uint64_t val;
	86	+
	87	+ /*
	88	+ * Check that we advertise that ID_AA64PFR0_EL1.GIC == 0, having
	89	+ * hidden the feature at runtime without any other userspace action.
	90	+ */
	91	+ __GUEST_ASSERT(FIELD_GET(ID_AA64PFR0_EL1_GIC,
	92	+ read_sysreg(id_aa64pfr0_el1)) == 0,
	93	+ "GICv3 wrongly advertised");
	94	+
	95	+ /*
	96	+ * Access all GICv3 registers, and fail if we don't get an UNDEF.
	97	+ * Note that we happily access all the APxRn registers without
	98	+ * checking their existence, as all we want to see is a failure.
	99	+ */
	100	+ check_sr_rw(ICC_PMR_EL1);
	101	+ check_sr_read(ICC_IAR0_EL1);
	102	+ check_sr_write(ICC_EOIR0_EL1);
	103	+ check_sr_rw(ICC_HPPIR0_EL1);
	104	+ check_sr_rw(ICC_BPR0_EL1);
	105	+ check_sr_rw(ICC_AP0R0_EL1);
	106	+ check_sr_rw(ICC_AP0R1_EL1);
	107	+ check_sr_rw(ICC_AP0R2_EL1);
	108	+ check_sr_rw(ICC_AP0R3_EL1);
	109	+ check_sr_rw(ICC_AP1R0_EL1);
	110	+ check_sr_rw(ICC_AP1R1_EL1);
	111	+ check_sr_rw(ICC_AP1R2_EL1);
	112	+ check_sr_rw(ICC_AP1R3_EL1);
	113	+ check_sr_write(ICC_DIR_EL1);
	114	+ check_sr_read(ICC_RPR_EL1);
	115	+ check_sr_write(ICC_SGI1R_EL1);
	116	+ check_sr_write(ICC_ASGI1R_EL1);
	117	+ check_sr_write(ICC_SGI0R_EL1);
	118	+ check_sr_read(ICC_IAR1_EL1);
	119	+ check_sr_write(ICC_EOIR1_EL1);
	120	+ check_sr_rw(ICC_HPPIR1_EL1);
	121	+ check_sr_rw(ICC_BPR1_EL1);
	122	+ check_sr_rw(ICC_CTLR_EL1);
	123	+ check_sr_rw(ICC_IGRPEN0_EL1);
	124	+ check_sr_rw(ICC_IGRPEN1_EL1);
	125	+
	126	+ /*
	127	+ * ICC_SRE_EL1 may not be trappable, as ICC_SRE_EL2.Enable can
	128	+ * be RAO/WI. Engage in non-fatal accesses, starting with a
	129	+ * write of 0 to try and disable SRE, and let's see if it
	130	+ * sticks.
	131	+ */
	132	+ __check_sr_write(ICC_SRE_EL1);
	133	+ if (!handled)
	134	+ GUEST_PRINTF("ICC_SRE_EL1 write not trapping (OK)\n");
	135	+
	136	+ val = __check_sr_read(ICC_SRE_EL1);
	137	+ if (!handled) {
	138	+ __GUEST_ASSERT((val & BIT(0)),
	139	+ "ICC_SRE_EL1 not trapped but ICC_SRE_EL1.SRE not set\n");
	140	+ GUEST_PRINTF("ICC_SRE_EL1 read not trapping (OK)\n");
	141	+ }
	142	+
	143	+ GUEST_DONE();
	144	+}
	145	+
	146	+static void guest_code_gicv5(void)
	147	+{
	148	+ /*
	149	+ * Check that we advertise that ID_AA64PFR2_EL1.GCIE == 0, having
	150	+ * hidden the feature at runtime without any other userspace action.
	151	+ */
	152	+ __GUEST_ASSERT(FIELD_GET(ID_AA64PFR2_EL1_GCIE,
	153	+ read_sysreg_s(SYS_ID_AA64PFR2_EL1)) == 0,
	154	+ "GICv5 wrongly advertised");
	155	+
	156	+ /*
	157	+ * Try all GICv5 instructions, and fail if we don't get an UNDEF.
	158	+ */
	159	+ check_gicv5_gic_op(CDAFF);
	160	+ check_gicv5_gic_op(CDDI);
	161	+ check_gicv5_gic_op(CDDIS);
	162	+ check_gicv5_gic_op(CDEOI);
	163	+ check_gicv5_gic_op(CDHM);
	164	+ check_gicv5_gic_op(CDPEND);
	165	+ check_gicv5_gic_op(CDPRI);
	166	+ check_gicv5_gic_op(CDRCFG);
	167	+ check_gicv5_gicr_op(CDIA);
	168	+ check_gicv5_gicr_op(CDNMIA);
	169	+
	170	+ /* Check General System Register acccesses */
	171	+ check_sr_rw(ICC_APR_EL1);
	172	+ check_sr_rw(ICC_CR0_EL1);
	173	+ check_sr_read(ICC_HPPIR_EL1);
	174	+ check_sr_read(ICC_IAFFIDR_EL1);
	175	+ check_sr_rw(ICC_ICSR_EL1);
	176	+ check_sr_read(ICC_IDR0_EL1);
	177	+ check_sr_rw(ICC_PCR_EL1);
	178	+
	179	+ /* Check PPI System Register accessess */
	180	+ check_sr_rw(ICC_PPI_CACTIVER0_EL1);
	181	+ check_sr_rw(ICC_PPI_CACTIVER1_EL1);
	182	+ check_sr_rw(ICC_PPI_SACTIVER0_EL1);
	183	+ check_sr_rw(ICC_PPI_SACTIVER1_EL1);
	184	+ check_sr_rw(ICC_PPI_CPENDR0_EL1);
	185	+ check_sr_rw(ICC_PPI_CPENDR1_EL1);
	186	+ check_sr_rw(ICC_PPI_SPENDR0_EL1);
	187	+ check_sr_rw(ICC_PPI_SPENDR1_EL1);
	188	+ check_sr_rw(ICC_PPI_ENABLER0_EL1);
	189	+ check_sr_rw(ICC_PPI_ENABLER1_EL1);
	190	+ check_sr_read(ICC_PPI_HMR0_EL1);
	191	+ check_sr_read(ICC_PPI_HMR1_EL1);
	192	+ check_sr_rw(ICC_PPI_PRIORITYR0_EL1);
	193	+ check_sr_rw(ICC_PPI_PRIORITYR1_EL1);
	194	+ check_sr_rw(ICC_PPI_PRIORITYR2_EL1);
	195	+ check_sr_rw(ICC_PPI_PRIORITYR3_EL1);
	196	+ check_sr_rw(ICC_PPI_PRIORITYR4_EL1);
	197	+ check_sr_rw(ICC_PPI_PRIORITYR5_EL1);
	198	+ check_sr_rw(ICC_PPI_PRIORITYR6_EL1);
	199	+ check_sr_rw(ICC_PPI_PRIORITYR7_EL1);
	200	+ check_sr_rw(ICC_PPI_PRIORITYR8_EL1);
	201	+ check_sr_rw(ICC_PPI_PRIORITYR9_EL1);
	202	+ check_sr_rw(ICC_PPI_PRIORITYR10_EL1);
	203	+ check_sr_rw(ICC_PPI_PRIORITYR11_EL1);
	204	+ check_sr_rw(ICC_PPI_PRIORITYR12_EL1);
	205	+ check_sr_rw(ICC_PPI_PRIORITYR13_EL1);
	206	+ check_sr_rw(ICC_PPI_PRIORITYR14_EL1);
	207	+ check_sr_rw(ICC_PPI_PRIORITYR15_EL1);
	208	+
	209	+ GUEST_DONE();
	210	+}
	211	+
	212	+static void guest_undef_handler(struct ex_regs *regs)
	213	+{
	214	+ /* Success, we've gracefully exploded! */
	215	+ handled = true;
	216	+ regs->pc += 4;
	217	+}
	218	+
	219	+static void test_run_vcpu(struct kvm_vcpu *vcpu)
	220	+{
	221	+ struct ucall uc;
	222	+
	223	+ do {
	224	+ vcpu_run(vcpu);
	225	+
	226	+ switch (get_ucall(vcpu, &uc)) {
	227	+ case UCALL_ABORT:
	228	+ REPORT_GUEST_ASSERT(uc);
	229	+ break;
	230	+ case UCALL_PRINTF:
	231	+ printf("%s", uc.buffer);
	232	+ break;
	233	+ case UCALL_DONE:
	234	+ break;
	235	+ default:
	236	+ TEST_FAIL("Unknown ucall %lu", uc.cmd);
	237	+ }
	238	+ } while (uc.cmd != UCALL_DONE);
	239	+}
	240	+
	241	+static void test_guest_no_vgic(void *guest_code)
	242	+{
	243	+ struct kvm_vcpu *vcpu;
	244	+ struct kvm_vm *vm;
	245	+
	246	+ /* Create a VM without a GIC */
	247	+ vm = vm_create_with_one_vcpu(&vcpu, guest_code);
	248	+
	249	+ vm_init_descriptor_tables(vm);
	250	+ vcpu_init_descriptor_tables(vcpu);
	251	+
	252	+ vm_install_sync_handler(vm, VECTOR_SYNC_CURRENT,
	253	+ ESR_ELx_EC_UNKNOWN, guest_undef_handler);
	254	+
	255	+ test_run_vcpu(vcpu);
	256	+
	257	+ kvm_vm_free(vm);
	258	+}
	259	+
	260	+int main(int argc, char *argv[])
	261	+{
	262	+ struct kvm_vcpu *vcpu;
	263	+ struct kvm_vm *vm;
	264	+ bool has_v3, has_v5;
	265	+ uint64_t pfr;
	266	+
	267	+ test_disable_default_vgic();
	268	+
	269	+ vm = vm_create_with_one_vcpu(&vcpu, NULL);
	270	+
	271	+ pfr = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1));
	272	+ has_v3 = !!FIELD_GET(ID_AA64PFR0_EL1_GIC, pfr);
	273	+
	274	+ pfr = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR2_EL1));
	275	+ has_v5 = !!FIELD_GET(ID_AA64PFR2_EL1_GCIE, pfr);
	276	+
	277	+ kvm_vm_free(vm);
	278	+
	279	+ __TEST_REQUIRE(has_v3 \|\| has_v5,
	280	+ "Neither GICv3 nor GICv5 supported.");
	281	+
	282	+ if (has_v3) {
	283	+ pr_info("Testing no-vgic-v3\n");
	284	+ test_guest_no_vgic(guest_code_gicv3);
	285	+ } else {
	286	+ pr_info("No GICv3 support: skipping no-vgic-v3 test\n");
	287	+ }
	288	+
	289	+ if (has_v5) {
	290	+ pr_info("Testing no-vgic-v5\n");
	291	+ test_guest_no_vgic(guest_code_gicv5);
	292	+ } else {
	293	+ pr_info("No GICv5 support: skipping no-vgic-v5 test\n");
	294	+ }
	295	+
	296	+ return 0;
	297	+}

tools/testing/selftests/kvm/arm64/vgic_v5.c+228−0

@@ -0,0 +1,228 @@
	1	+// SPDX-License-Identifier: GPL-2.0
	2	+
	3	+#include <linux/kernel.h>
	4	+#include <sys/syscall.h>
	5	+#include <asm/kvm.h>
	6	+#include <asm/kvm_para.h>
	7	+
	8	+#include <arm64/gic_v5.h>
	9	+
	10	+#include "test_util.h"
	11	+#include "kvm_util.h"
	12	+#include "processor.h"
	13	+#include "vgic.h"
	14	+
	15	+#define NR_VCPUS 1
	16	+
	17	+struct vm_gic {
	18	+ struct kvm_vm *vm;
	19	+ int gic_fd;
	20	+ uint32_t gic_dev_type;
	21	+};
	22	+
	23	+static uint64_t max_phys_size;
	24	+
	25	+#define GUEST_CMD_IRQ_CDIA 10
	26	+#define GUEST_CMD_IRQ_DIEOI 11
	27	+#define GUEST_CMD_IS_AWAKE 12
	28	+#define GUEST_CMD_IS_READY 13
	29	+
	30	+static void guest_irq_handler(struct ex_regs *regs)
	31	+{
	32	+ bool valid;
	33	+ u32 hwirq;
	34	+ u64 ia;
	35	+ static int count;
	36	+
	37	+ /*
	38	+ * We have pending interrupts. Should never actually enter WFI
	39	+ * here!
	40	+ */
	41	+ wfi();
	42	+ GUEST_SYNC(GUEST_CMD_IS_AWAKE);
	43	+
	44	+ ia = gicr_insn(CDIA);
	45	+ valid = GICV5_GICR_CDIA_VALID(ia);
	46	+
	47	+ GUEST_SYNC(GUEST_CMD_IRQ_CDIA);
	48	+
	49	+ if (!valid)
	50	+ return;
	51	+
	52	+ gsb_ack();
	53	+ isb();
	54	+
	55	+ hwirq = FIELD_GET(GICV5_GICR_CDIA_INTID, ia);
	56	+
	57	+ gic_insn(hwirq, CDDI);
	58	+ gic_insn(0, CDEOI);
	59	+
	60	+ GUEST_SYNC(GUEST_CMD_IRQ_DIEOI);
	61	+
	62	+ if (++count >= 2)
	63	+ GUEST_DONE();
	64	+
	65	+ /* Ask for the next interrupt to be injected */
	66	+ GUEST_SYNC(GUEST_CMD_IS_READY);
	67	+}
	68	+
	69	+static void guest_code(void)
	70	+{
	71	+ local_irq_disable();
	72	+
	73	+ gicv5_cpu_enable_interrupts();
	74	+ local_irq_enable();
	75	+
	76	+ /* Enable the SW_PPI (3) */
	77	+ write_sysreg_s(BIT_ULL(3), SYS_ICC_PPI_ENABLER0_EL1);
	78	+
	79	+ /* Ask for the first interrupt to be injected */
	80	+ GUEST_SYNC(GUEST_CMD_IS_READY);
	81	+
	82	+ /* Loop forever waiting for interrupts */
	83	+ while (1);
	84	+}
	85	+
	86	+
	87	+/* we don't want to assert on run execution, hence that helper */
	88	+static int run_vcpu(struct kvm_vcpu *vcpu)
	89	+{
	90	+ return __vcpu_run(vcpu) ? -errno : 0;
	91	+}
	92	+
	93	+static void vm_gic_destroy(struct vm_gic *v)
	94	+{
	95	+ close(v->gic_fd);
	96	+ kvm_vm_free(v->vm);
	97	+}
	98	+
	99	+static void test_vgic_v5_ppis(uint32_t gic_dev_type)
	100	+{
	101	+ struct kvm_vcpu *vcpus[NR_VCPUS];
	102	+ struct ucall uc;
	103	+ u64 user_ppis[2];
	104	+ struct vm_gic v;
	105	+ int ret, i;
	106	+
	107	+ v.gic_dev_type = gic_dev_type;
	108	+ v.vm = __vm_create(VM_SHAPE_DEFAULT, NR_VCPUS, 0);
	109	+
	110	+ v.gic_fd = kvm_create_device(v.vm, gic_dev_type);
	111	+
	112	+ for (i = 0; i < NR_VCPUS; i++)
	113	+ vcpus[i] = vm_vcpu_add(v.vm, i, guest_code);
	114	+
	115	+ vm_init_descriptor_tables(v.vm);
	116	+ vm_install_exception_handler(v.vm, VECTOR_IRQ_CURRENT, guest_irq_handler);
	117	+
	118	+ for (i = 0; i < NR_VCPUS; i++)
	119	+ vcpu_init_descriptor_tables(vcpus[i]);
	120	+
	121	+ kvm_device_attr_set(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
	122	+ KVM_DEV_ARM_VGIC_CTRL_INIT, NULL);
	123	+
	124	+ /* Read out the PPIs that user space is allowed to drive. */
	125	+ kvm_device_attr_get(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
	126	+ KVM_DEV_ARM_VGIC_USERSPACE_PPIS, &user_ppis);
	127	+
	128	+ /* We should always be able to drive the SW_PPI. */
	129	+ TEST_ASSERT(user_ppis[0] & BIT(GICV5_ARCH_PPI_SW_PPI),
	130	+ "SW_PPI is not drivable by userspace");
	131	+
	132	+ while (1) {
	133	+ ret = run_vcpu(vcpus[0]);
	134	+
	135	+ switch (get_ucall(vcpus[0], &uc)) {
	136	+ case UCALL_SYNC:
	137	+ /*
	138	+ * The guest is ready for the next level change. Set
	139	+ * high if ready, and lower if it has been consumed.
	140	+ */
	141	+ if (uc.args[1] == GUEST_CMD_IS_READY \|\|
	142	+ uc.args[1] == GUEST_CMD_IRQ_DIEOI) {
	143	+ u64 irq;
	144	+ bool level = uc.args[1] == GUEST_CMD_IRQ_DIEOI ? 0 : 1;
	145	+
	146	+ irq = FIELD_PREP(KVM_ARM_IRQ_NUM_MASK, 3);
	147	+ irq \|= KVM_ARM_IRQ_TYPE_PPI << KVM_ARM_IRQ_TYPE_SHIFT;
	148	+
	149	+ _kvm_irq_line(v.vm, irq, level);
	150	+ } else if (uc.args[1] == GUEST_CMD_IS_AWAKE) {
	151	+ pr_info("Guest skipping WFI due to pending IRQ\n");
	152	+ } else if (uc.args[1] == GUEST_CMD_IRQ_CDIA) {
	153	+ pr_info("Guest acknowledged IRQ\n");
	154	+ }
	155	+
	156	+ continue;
	157	+ case UCALL_ABORT:
	158	+ REPORT_GUEST_ASSERT(uc);
	159	+ break;
	160	+ case UCALL_DONE:
	161	+ goto done;
	162	+ default:
	163	+ TEST_FAIL("Unknown ucall %lu", uc.cmd);
	164	+ }
	165	+ }
	166	+
	167	+done:
	168	+ TEST_ASSERT(ret == 0, "Failed to test GICv5 PPIs");
	169	+
	170	+ vm_gic_destroy(&v);
	171	+}
	172	+
	173	+/*
	174	+ * Returns 0 if it's possible to create GIC device of a given type (V5).
	175	+ */
	176	+int test_kvm_device(uint32_t gic_dev_type)
	177	+{
	178	+ struct kvm_vcpu *vcpus[NR_VCPUS];
	179	+ struct vm_gic v;
	180	+ int ret;
	181	+
	182	+ v.vm = vm_create_with_vcpus(NR_VCPUS, guest_code, vcpus);
	183	+
	184	+ /* try to create a non existing KVM device */
	185	+ ret = __kvm_test_create_device(v.vm, 0);
	186	+ TEST_ASSERT(ret && errno == ENODEV, "unsupported device");
	187	+
	188	+ /* trial mode */
	189	+ ret = __kvm_test_create_device(v.vm, gic_dev_type);
	190	+ if (ret)
	191	+ return ret;
	192	+ v.gic_fd = kvm_create_device(v.vm, gic_dev_type);
	193	+
	194	+ ret = __kvm_create_device(v.vm, gic_dev_type);
	195	+ TEST_ASSERT(ret < 0 && errno == EEXIST, "create GIC device twice");
	196	+
	197	+ vm_gic_destroy(&v);
	198	+
	199	+ return 0;
	200	+}
	201	+
	202	+void run_tests(uint32_t gic_dev_type)
	203	+{
	204	+ pr_info("Test VGICv5 PPIs\n");
	205	+ test_vgic_v5_ppis(gic_dev_type);
	206	+}
	207	+
	208	+int main(int ac, char **av)
	209	+{
	210	+ int ret;
	211	+ int pa_bits;
	212	+
	213	+ test_disable_default_vgic();
	214	+
	215	+ pa_bits = vm_guest_mode_params[VM_MODE_DEFAULT].pa_bits;
	216	+ max_phys_size = 1ULL << pa_bits;
	217	+
	218	+ ret = test_kvm_device(KVM_DEV_TYPE_ARM_VGIC_V5);
	219	+ if (ret) {
	220	+ pr_info("No GICv5 support; Not running GIC_v5 tests.\n");
	221	+ exit(KSFT_SKIP);
	222	+ }
	223	+
	224	+ pr_info("Running VGIC_V5 tests.\n");
	225	+ run_tests(KVM_DEV_TYPE_ARM_VGIC_V5);
	226	+
	227	+ return 0;
	228	+}

tools/testing/selftests/kvm/include/arm64/gic_v5.h+150−0

@@ -0,0 +1,150 @@
	1	+/* SPDX-License-Identifier: GPL-2.0-only */
	2	+
	3	+#ifndef __SELFTESTS_GIC_V5_H
	4	+#define __SELFTESTS_GIC_V5_H
	5	+
	6	+#include <asm/barrier.h>
	7	+#include <asm/sysreg.h>
	8	+
	9	+#include <linux/bitfield.h>
	10	+
	11	+#include "processor.h"
	12	+
	13	+/*
	14	+ * Definitions for GICv5 instructions for the Current Domain
	15	+ */
	16	+#define GICV5_OP_GIC_CDAFF sys_insn(1, 0, 12, 1, 3)
	17	+#define GICV5_OP_GIC_CDDI sys_insn(1, 0, 12, 2, 0)
	18	+#define GICV5_OP_GIC_CDDIS sys_insn(1, 0, 12, 1, 0)
	19	+#define GICV5_OP_GIC_CDHM sys_insn(1, 0, 12, 2, 1)
	20	+#define GICV5_OP_GIC_CDEN sys_insn(1, 0, 12, 1, 1)
	21	+#define GICV5_OP_GIC_CDEOI sys_insn(1, 0, 12, 1, 7)
	22	+#define GICV5_OP_GIC_CDPEND sys_insn(1, 0, 12, 1, 4)
	23	+#define GICV5_OP_GIC_CDPRI sys_insn(1, 0, 12, 1, 2)
	24	+#define GICV5_OP_GIC_CDRCFG sys_insn(1, 0, 12, 1, 5)
	25	+#define GICV5_OP_GICR_CDIA sys_insn(1, 0, 12, 3, 0)
	26	+#define GICV5_OP_GICR_CDNMIA sys_insn(1, 0, 12, 3, 1)
	27	+
	28	+/* Definitions for GIC CDAFF */
	29	+#define GICV5_GIC_CDAFF_IAFFID_MASK GENMASK_ULL(47, 32)
	30	+#define GICV5_GIC_CDAFF_TYPE_MASK GENMASK_ULL(31, 29)
	31	+#define GICV5_GIC_CDAFF_IRM_MASK BIT_ULL(28)
	32	+#define GICV5_GIC_CDAFF_ID_MASK GENMASK_ULL(23, 0)
	33	+
	34	+/* Definitions for GIC CDDI */
	35	+#define GICV5_GIC_CDDI_TYPE_MASK GENMASK_ULL(31, 29)
	36	+#define GICV5_GIC_CDDI_ID_MASK GENMASK_ULL(23, 0)
	37	+
	38	+/* Definitions for GIC CDDIS */
	39	+#define GICV5_GIC_CDDIS_TYPE_MASK GENMASK_ULL(31, 29)
	40	+#define GICV5_GIC_CDDIS_TYPE(r) FIELD_GET(GICV5_GIC_CDDIS_TYPE_MASK, r)
	41	+#define GICV5_GIC_CDDIS_ID_MASK GENMASK_ULL(23, 0)
	42	+#define GICV5_GIC_CDDIS_ID(r) FIELD_GET(GICV5_GIC_CDDIS_ID_MASK, r)
	43	+
	44	+/* Definitions for GIC CDEN */
	45	+#define GICV5_GIC_CDEN_TYPE_MASK GENMASK_ULL(31, 29)
	46	+#define GICV5_GIC_CDEN_ID_MASK GENMASK_ULL(23, 0)
	47	+
	48	+/* Definitions for GIC CDHM */
	49	+#define GICV5_GIC_CDHM_HM_MASK BIT_ULL(32)
	50	+#define GICV5_GIC_CDHM_TYPE_MASK GENMASK_ULL(31, 29)
	51	+#define GICV5_GIC_CDHM_ID_MASK GENMASK_ULL(23, 0)
	52	+
	53	+/* Definitions for GIC CDPEND */
	54	+#define GICV5_GIC_CDPEND_PENDING_MASK BIT_ULL(32)
	55	+#define GICV5_GIC_CDPEND_TYPE_MASK GENMASK_ULL(31, 29)
	56	+#define GICV5_GIC_CDPEND_ID_MASK GENMASK_ULL(23, 0)
	57	+
	58	+/* Definitions for GIC CDPRI */
	59	+#define GICV5_GIC_CDPRI_PRIORITY_MASK GENMASK_ULL(39, 35)
	60	+#define GICV5_GIC_CDPRI_TYPE_MASK GENMASK_ULL(31, 29)
	61	+#define GICV5_GIC_CDPRI_ID_MASK GENMASK_ULL(23, 0)
	62	+
	63	+/* Definitions for GIC CDRCFG */
	64	+#define GICV5_GIC_CDRCFG_TYPE_MASK GENMASK_ULL(31, 29)
	65	+#define GICV5_GIC_CDRCFG_ID_MASK GENMASK_ULL(23, 0)
	66	+
	67	+/* Definitions for GICR CDIA */
	68	+#define GICV5_GICR_CDIA_VALID_MASK BIT_ULL(32)
	69	+#define GICV5_GICR_CDIA_VALID(r) FIELD_GET(GICV5_GICR_CDIA_VALID_MASK, r)
	70	+#define GICV5_GICR_CDIA_TYPE_MASK GENMASK_ULL(31, 29)
	71	+#define GICV5_GICR_CDIA_ID_MASK GENMASK_ULL(23, 0)
	72	+#define GICV5_GICR_CDIA_INTID GENMASK_ULL(31, 0)
	73	+
	74	+/* Definitions for GICR CDNMIA */
	75	+#define GICV5_GICR_CDNMIA_VALID_MASK BIT_ULL(32)
	76	+#define GICV5_GICR_CDNMIA_VALID(r) FIELD_GET(GICV5_GICR_CDNMIA_VALID_MASK, r)
	77	+#define GICV5_GICR_CDNMIA_TYPE_MASK GENMASK_ULL(31, 29)
	78	+#define GICV5_GICR_CDNMIA_ID_MASK GENMASK_ULL(23, 0)
	79	+
	80	+#define gicr_insn(insn) read_sysreg_s(GICV5_OP_GICR_##insn)
	81	+#define gic_insn(v, insn) write_sysreg_s(v, GICV5_OP_GIC_##insn)
	82	+
	83	+#define __GIC_BARRIER_INSN(op0, op1, CRn, CRm, op2, Rt) \
	84	+ __emit_inst(0xd5000000 \| \
	85	+ sys_insn((op0), (op1), (CRn), (CRm), (op2)) \| \
	86	+ ((Rt) & 0x1f))
	87	+
	88	+#define GSB_SYS_BARRIER_INSN __GIC_BARRIER_INSN(1, 0, 12, 0, 0, 31)
	89	+#define GSB_ACK_BARRIER_INSN __GIC_BARRIER_INSN(1, 0, 12, 0, 1, 31)
	90	+
	91	+#define gsb_ack() asm volatile(GSB_ACK_BARRIER_INSN : : : "memory")
	92	+#define gsb_sys() asm volatile(GSB_SYS_BARRIER_INSN : : : "memory")
	93	+
	94	+#define REPEAT_BYTE(x) ((~0ul / 0xff) * (x))
	95	+
	96	+#define GICV5_IRQ_DEFAULT_PRI 0b10000
	97	+
	98	+#define GICV5_ARCH_PPI_SW_PPI 0x3
	99	+
	100	+void gicv5_ppi_priority_init(void)
	101	+{
	102	+ write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_DEFAULT_PRI), SYS_ICC_PPI_PRIORITYR0_EL1);
	103	+ write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_DEFAULT_PRI), SYS_ICC_PPI_PRIORITYR1_EL1);
	104	+ write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_DEFAULT_PRI), SYS_ICC_PPI_PRIORITYR2_EL1);
	105	+ write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_DEFAULT_PRI), SYS_ICC_PPI_PRIORITYR3_EL1);
	106	+ write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_DEFAULT_PRI), SYS_ICC_PPI_PRIORITYR4_EL1);
	107	+ write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_DEFAULT_PRI), SYS_ICC_PPI_PRIORITYR5_EL1);
	108	+ write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_DEFAULT_PRI), SYS_ICC_PPI_PRIORITYR6_EL1);
	109	+ write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_DEFAULT_PRI), SYS_ICC_PPI_PRIORITYR7_EL1);
	110	+ write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_DEFAULT_PRI), SYS_ICC_PPI_PRIORITYR8_EL1);
	111	+ write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_DEFAULT_PRI), SYS_ICC_PPI_PRIORITYR9_EL1);
	112	+ write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_DEFAULT_PRI), SYS_ICC_PPI_PRIORITYR10_EL1);
	113	+ write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_DEFAULT_PRI), SYS_ICC_PPI_PRIORITYR11_EL1);
	114	+ write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_DEFAULT_PRI), SYS_ICC_PPI_PRIORITYR12_EL1);
	115	+ write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_DEFAULT_PRI), SYS_ICC_PPI_PRIORITYR13_EL1);
	116	+ write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_DEFAULT_PRI), SYS_ICC_PPI_PRIORITYR14_EL1);
	117	+ write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_DEFAULT_PRI), SYS_ICC_PPI_PRIORITYR15_EL1);
	118	+
	119	+ /*
	120	+ * Context syncronization required to make sure system register writes
	121	+ * effects are synchronised.
	122	+ */
	123	+ isb();
	124	+}
	125	+
	126	+void gicv5_cpu_disable_interrupts(void)
	127	+{
	128	+ u64 cr0;
	129	+
	130	+ cr0 = FIELD_PREP(ICC_CR0_EL1_EN, 0);
	131	+ write_sysreg_s(cr0, SYS_ICC_CR0_EL1);
	132	+}
	133	+
	134	+void gicv5_cpu_enable_interrupts(void)
	135	+{
	136	+ u64 cr0, pcr;
	137	+
	138	+ write_sysreg_s(0, SYS_ICC_PPI_ENABLER0_EL1);
	139	+ write_sysreg_s(0, SYS_ICC_PPI_ENABLER1_EL1);
	140	+
	141	+ gicv5_ppi_priority_init();
	142	+
	143	+ pcr = FIELD_PREP(ICC_PCR_EL1_PRIORITY, GICV5_IRQ_DEFAULT_PRI);
	144	+ write_sysreg_s(pcr, SYS_ICC_PCR_EL1);
	145	+
	146	+ cr0 = FIELD_PREP(ICC_CR0_EL1_EN, 1);
	147	+ write_sysreg_s(cr0, SYS_ICC_CR0_EL1);
	148	+}
	149	+
	150	+#endif