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Merge branches 'fixes', 'arm/smmu/updates', 'arm/smmu/bindings', 'riscv', 'intel/vt-d', 'amd/amd-vi' and 'core' into next

Will Deacon committed 7 months ago

Commit f8d5e708 parents 7aaa804 7e05485 9dcef98 5e8323c 40a13b4 b334d7f 5aac287 ebfaf2b43 files · +2166 −798Browse files

Showing the changes to include/uapi (1 of 43 files). Show all

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include/uapi/linux/iommufd.h+9−0
@@ -695,11 +695,15 @@ enum iommu_hw_info_type { · 694 unmodified lines
695 * @IOMMU_HW_CAP_PCI_PASID_PRIV: Privileged Mode Supported, user ignores it695 * @IOMMU_HW_CAP_PCI_PASID_PRIV: Privileged Mode Supported, user ignores it
696 * when the struct696 * when the struct
697 * iommu_hw_info::out_max_pasid_log2 is zero.697 * iommu_hw_info::out_max_pasid_log2 is zero.
698 * @IOMMU_HW_CAP_PCI_ATS_NOT_SUPPORTED: ATS is not supported or cannot be used
699 * on this device (absence implies ATS
700 * may be enabled)
698 */701 */
699enum iommufd_hw_capabilities {702enum iommufd_hw_capabilities {
700 IOMMU_HW_CAP_DIRTY_TRACKING = 1 << 0,703 IOMMU_HW_CAP_DIRTY_TRACKING = 1 << 0,
701 IOMMU_HW_CAP_PCI_PASID_EXEC = 1 << 1,704 IOMMU_HW_CAP_PCI_PASID_EXEC = 1 << 1,
702 IOMMU_HW_CAP_PCI_PASID_PRIV = 1 << 2,705 IOMMU_HW_CAP_PCI_PASID_PRIV = 1 << 2,
706 IOMMU_HW_CAP_PCI_ATS_NOT_SUPPORTED = 1 << 3,
703};707};
704 708
705/**709/**
@@ -1052,6 +1056,11 @@ struct iommu_fault_alloc { · 346 unmodified lines
1052enum iommu_viommu_type {1056enum iommu_viommu_type {
1053 IOMMU_VIOMMU_TYPE_DEFAULT = 0,1057 IOMMU_VIOMMU_TYPE_DEFAULT = 0,
1054 IOMMU_VIOMMU_TYPE_ARM_SMMUV3 = 1,1058 IOMMU_VIOMMU_TYPE_ARM_SMMUV3 = 1,
1059 /*
1060 * TEGRA241_CMDQV requirements (otherwise, VCMDQs will not work)
1061 * - Kernel will allocate a VINTF (HYP_OWN=0) to back this VIOMMU. So,
1062 * VMM must wire the HYP_OWN bit to 0 in guest VINTF_CONFIG register
1063 */
1055 IOMMU_VIOMMU_TYPE_TEGRA241_CMDQV = 2,1064 IOMMU_VIOMMU_TYPE_TEGRA241_CMDQV = 2,
1056};1065};
1057 1066

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