drm/msm: Support multiple ringbuffers

Add the infrastructure to support the idea of multiple ringbuffers. Assign each ringbuffer an id and use that as an index for the various ring specific operations. The biggest delta is to support legacy fences. Each fence gets its own sequence number but the legacy functions expect to use a unique integer. To handle this we return a unique identifier for each submission but map it to a specific ring/sequence under the covers. Newer users use a dma_fence pointer anyway so they don't care about the actual sequence ID or ring. The actual mechanics for multiple ringbuffers are very target specific so this code just allows for the possibility but still only defines one ringbuffer for each target family.

Jordan Crouse committed 9 years ago

Commit f97deca1 parent cd414f320 files · +1251 −210Browse files

Unified · Split

20 files

drivers/gpu/drm/msm/adreno/a3xx_gpu.c +5 −4
drivers/gpu/drm/msm/adreno/a4xx_gpu.c +5 −4
drivers/gpu/drm/msm/adreno/a5xx_gpu.c +28 −26
drivers/gpu/drm/msm/adreno/a5xx_gpu.h +1 −1
drivers/gpu/drm/msm/adreno/a5xx_power.c +3 −3
drivers/gpu/drm/msm/adreno/adreno_gpu.c +82 −54
drivers/gpu/drm/msm/adreno/adreno_gpu.h +11 −9
drivers/gpu/drm/msm/msm_drv.c +17 −6
drivers/gpu/drm/msm/msm_drv.h +5 −3
drivers/gpu/drm/msm/msm_fence.c +1 −1
drivers/gpu/drm/msm/msm_fence.h +1 −1
drivers/gpu/drm/msm/msm_gem.h +3 −1
drivers/gpu/drm/msm/msm_gem_submit.c +8 −4
drivers/gpu/drm/msm/msm_gpu.c +111 −52
drivers/gpu/drm/msm/msm_gpu.h +18 −24
drivers/gpu/drm/msm/msm_ringbuffer.c +24 −10
drivers/gpu/drm/msm/msm_ringbuffer.h +18 −2
drivers/gpu/drm/msm/msm_submitqueue.c +22 −5
include/dt-bindings/msm/msm-bus-ids.h +887 −0
include/uapi/drm/msm_drm.h +1 −0

drivers/gpu/drm/msm/adreno/a3xx_gpu.c+5−4

@@ -44,7 +44,7 @@ static bool a3xx_idle(struct msm_gpu *gpu); · 43 unmodified lines
44	44
45	45	static bool a3xx_me_init(struct msm_gpu *gpu)
46	46	{
47		− struct msm_ringbuffer *ring = gpu->rb;
	47	+ struct msm_ringbuffer *ring = gpu->rb[0];
48	48
49	49	OUT_PKT3(ring, CP_ME_INIT, 17);
50	50	OUT_RING(ring, 0x000003f7);
@@ -65,7 +65,7 @@ static bool a3xx_me_init(struct msm_gpu *gpu) · 14 unmodified lines
65	65	OUT_RING(ring, 0x00000000);
66	66	OUT_RING(ring, 0x00000000);
67	67
68		− gpu->funcs->flush(gpu);
	68	+ gpu->funcs->flush(gpu, ring);
69	69	return a3xx_idle(gpu);
70	70	}
71	71
@@ -339,7 +339,7 @@ static void a3xx_destroy(struct msm_gpu *gpu) · 267 unmodified lines
339	339	static bool a3xx_idle(struct msm_gpu *gpu)
340	340	{
341	341	/* wait for ringbuffer to drain: */
342		− if (!adreno_idle(gpu))
	342	+ if (!adreno_idle(gpu, gpu->rb[0]))
343	343	return false;
344	344
345	345	/* then wait for GPU to finish: */
@@ -446,6 +446,7 @@ static const struct adreno_gpu_funcs funcs = { · 100 unmodified lines
446	446	.recover = a3xx_recover,
447	447	.submit = adreno_submit,
448	448	.flush = adreno_flush,
	449	+ .active_ring = adreno_active_ring,
449	450	.irq = a3xx_irq,
450	451	.destroy = a3xx_destroy,
451	452	#ifdef CONFIG_DEBUG_FS
@@ -491,7 +492,7 @@ struct msm_gpu a3xx_gpu_init(struct drm_device dev) · 39 unmodified lines
491	492	adreno_gpu->registers = a3xx_registers;
492	493	adreno_gpu->reg_offsets = a3xx_register_offsets;
493	494
494		− ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs);
	495	+ ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1);
495	496	if (ret)
496	497	goto fail;
497	498

drivers/gpu/drm/msm/adreno/a4xx_gpu.c+5−4

@@ -116,7 +116,7 @@ static void a4xx_enable_hwcg(struct msm_gpu *gpu) · 115 unmodified lines
116	116
117	117	static bool a4xx_me_init(struct msm_gpu *gpu)
118	118	{
119		− struct msm_ringbuffer *ring = gpu->rb;
	119	+ struct msm_ringbuffer *ring = gpu->rb[0];
120	120
121	121	OUT_PKT3(ring, CP_ME_INIT, 17);
122	122	OUT_RING(ring, 0x000003f7);
@@ -137,7 +137,7 @@ static bool a4xx_me_init(struct msm_gpu *gpu) · 14 unmodified lines
137	137	OUT_RING(ring, 0x00000000);
138	138	OUT_RING(ring, 0x00000000);
139	139
140		− gpu->funcs->flush(gpu);
	140	+ gpu->funcs->flush(gpu, ring);
141	141	return a4xx_idle(gpu);
142	142	}
143	143
@@ -337,7 +337,7 @@ static void a4xx_destroy(struct msm_gpu *gpu) · 193 unmodified lines
337	337	static bool a4xx_idle(struct msm_gpu *gpu)
338	338	{
339	339	/* wait for ringbuffer to drain: */
340		− if (!adreno_idle(gpu))
	340	+ if (!adreno_idle(gpu, gpu->rb[0]))
341	341	return false;
342	342
343	343	/* then wait for GPU to finish: */
@@ -534,6 +534,7 @@ static const struct adreno_gpu_funcs funcs = { · 190 unmodified lines
534	534	.recover = a4xx_recover,
535	535	.submit = adreno_submit,
536	536	.flush = adreno_flush,
	537	+ .active_ring = adreno_active_ring,
537	538	.irq = a4xx_irq,
538	539	.destroy = a4xx_destroy,
539	540	#ifdef CONFIG_DEBUG_FS
@@ -573,7 +574,7 @@ struct msm_gpu a4xx_gpu_init(struct drm_device dev) · 33 unmodified lines
573	574	adreno_gpu->registers = a4xx_registers;
574	575	adreno_gpu->reg_offsets = a4xx_register_offsets;
575	576
576		− ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs);
	577	+ ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1);
577	578	if (ret)
578	579	goto fail;
579	580

drivers/gpu/drm/msm/adreno/a5xx_gpu.c+28−26

@@ -117,7 +117,7 @@ static void a5xx_submit(struct msm_gpu gpu, struct msm_gem_submit submit, · 116 unmodified lines
117	117	struct msm_file_private *ctx)
118	118	{
119	119	struct msm_drm_private *priv = gpu->dev->dev_private;
120		− struct msm_ringbuffer *ring = gpu->rb;
	120	+ struct msm_ringbuffer *ring = submit->ring;
121	121	unsigned int i, ibs = 0;
122	122
123	123	for (i = 0; i < submit->nr_cmds; i++) {
@@ -138,15 +138,15 @@ static void a5xx_submit(struct msm_gpu gpu, struct msm_gem_submit submit, · 14 unmodified lines
138	138	}
139	139
140	140	OUT_PKT4(ring, REG_A5XX_CP_SCRATCH_REG(2), 1);
141		− OUT_RING(ring, submit->fence->seqno);
	141	+ OUT_RING(ring, submit->seqno);
142	142
143	143	OUT_PKT7(ring, CP_EVENT_WRITE, 4);
144	144	OUT_RING(ring, CACHE_FLUSH_TS \| (1 << 31));
145		− OUT_RING(ring, lower_32_bits(rbmemptr(gpu, fence)));
146		− OUT_RING(ring, upper_32_bits(rbmemptr(gpu, fence)));
147		− OUT_RING(ring, submit->fence->seqno);
	145	+ OUT_RING(ring, lower_32_bits(rbmemptr(ring, fence)));
	146	+ OUT_RING(ring, upper_32_bits(rbmemptr(ring, fence)));
	147	+ OUT_RING(ring, submit->seqno);
148	148
149		− gpu->funcs->flush(gpu);
	149	+ gpu->funcs->flush(gpu, ring);
150	150	}
151	151
152	152	static const struct {
@@ -262,7 +262,7 @@ void a5xx_set_hwcg(struct msm_gpu *gpu, bool state) · 109 unmodified lines
262	262	static int a5xx_me_init(struct msm_gpu *gpu)
263	263	{
264	264	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
265		− struct msm_ringbuffer *ring = gpu->rb;
	265	+ struct msm_ringbuffer *ring = gpu->rb[0];
266	266
267	267	OUT_PKT7(ring, CP_ME_INIT, 8);
268	268
@@ -293,9 +293,8 @@ static int a5xx_me_init(struct msm_gpu *gpu) · 24 unmodified lines
293	293	OUT_RING(ring, 0x00000000);
294	294	OUT_RING(ring, 0x00000000);
295	295
296		− gpu->funcs->flush(gpu);
297		−
298		− return a5xx_idle(gpu) ? 0 : -EINVAL;
	296	+ gpu->funcs->flush(gpu, ring);
	297	+ return a5xx_idle(gpu, ring) ? 0 : -EINVAL;
299	298	}
300	299
301	300	static struct drm_gem_object a5xx_ucode_load_bo(struct msm_gpu gpu,
@@ -581,11 +580,11 @@ static int a5xx_hw_init(struct msm_gpu *gpu) · 279 unmodified lines
581	580	* ticking correctly
582	581	*/
583	582	if (adreno_is_a530(adreno_gpu)) {
584		− OUT_PKT7(gpu->rb, CP_EVENT_WRITE, 1);
585		− OUT_RING(gpu->rb, 0x0F);
	583	+ OUT_PKT7(gpu->rb[0], CP_EVENT_WRITE, 1);
	584	+ OUT_RING(gpu->rb[0], 0x0F);
586	585
587		− gpu->funcs->flush(gpu);
588		− if (!a5xx_idle(gpu))
	586	+ gpu->funcs->flush(gpu, gpu->rb[0]);
	587	+ if (!a5xx_idle(gpu, gpu->rb[0]))
589	588	return -EINVAL;
590	589	}
591	590
@@ -598,11 +597,11 @@ static int a5xx_hw_init(struct msm_gpu *gpu) · 6 unmodified lines
598	597	*/
599	598	ret = a5xx_zap_shader_init(gpu);
600	599	if (!ret) {
601		− OUT_PKT7(gpu->rb, CP_SET_SECURE_MODE, 1);
602		− OUT_RING(gpu->rb, 0x00000000);
	600	+ OUT_PKT7(gpu->rb[0], CP_SET_SECURE_MODE, 1);
	601	+ OUT_RING(gpu->rb[0], 0x00000000);
603	602
604		− gpu->funcs->flush(gpu);
605		− if (!a5xx_idle(gpu))
	603	+ gpu->funcs->flush(gpu, gpu->rb[0]);
	604	+ if (!a5xx_idle(gpu, gpu->rb[0]))
606	605	return -EINVAL;
607	606	} else {
608	607	/* Print a warning so if we die, we know why */
@@ -676,18 +675,19 @@ static inline bool _a5xx_check_idle(struct msm_gpu *gpu) · 67 unmodified lines
676	675	A5XX_RBBM_INT_0_MASK_MISC_HANG_DETECT);
677	676	}
678	677
679		−bool a5xx_idle(struct msm_gpu *gpu)
	678	+bool a5xx_idle(struct msm_gpu gpu, struct msm_ringbuffer ring)
680	679	{
681	680	/* wait for CP to drain ringbuffer: */
682		− if (!adreno_idle(gpu))
	681	+ if (!adreno_idle(gpu, ring))
683	682	return false;
684	683
685	684	if (spin_until(_a5xx_check_idle(gpu))) {
686		− DRM_ERROR("%s: %ps: timeout waiting for GPU to idle: status %8.8X irq %8.8X\n",
	685	+ DRM_ERROR("%s: %ps: timeout waiting for GPU to idle: status %8.8X irq %8.8X rptr/wptr %d/%d\n",
687	686	gpu->name, __builtin_return_address(0),
688	687	gpu_read(gpu, REG_A5XX_RBBM_STATUS),
689		− gpu_read(gpu, REG_A5XX_RBBM_INT_0_STATUS));
690		−
	688	+ gpu_read(gpu, REG_A5XX_RBBM_INT_0_STATUS),
	689	+ gpu_read(gpu, REG_A5XX_CP_RB_RPTR),
	690	+ gpu_read(gpu, REG_A5XX_CP_RB_WPTR));
691	691	return false;
692	692	}
693	693
@@ -818,9 +818,10 @@ static void a5xx_fault_detect_irq(struct msm_gpu *gpu) · 124 unmodified lines
818	818	{
819	819	struct drm_device *dev = gpu->dev;
820	820	struct msm_drm_private *priv = dev->dev_private;
	821	+ struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu);
821	822
822		− dev_err(dev->dev, "gpu fault fence %x status %8.8X rb %4.4x/%4.4x ib1 %16.16llX/%4.4x ib2 %16.16llX/%4.4x\n",
823		− gpu->memptrs->fence,
	823	+ dev_err(dev->dev, "gpu fault ring %d fence %x status %8.8X rb %4.4x/%4.4x ib1 %16.16llX/%4.4x ib2 %16.16llX/%4.4x\n",
	824	+ ring ? ring->id : -1, ring ? ring->seqno : 0,
824	825	gpu_read(gpu, REG_A5XX_RBBM_STATUS),
825	826	gpu_read(gpu, REG_A5XX_CP_RB_RPTR),
826	827	gpu_read(gpu, REG_A5XX_CP_RB_WPTR),
@@ -1010,6 +1011,7 @@ static const struct adreno_gpu_funcs funcs = { · 183 unmodified lines
1010	1011	.recover = a5xx_recover,
1011	1012	.submit = a5xx_submit,
1012	1013	.flush = adreno_flush,
	1014	+ .active_ring = adreno_active_ring,
1013	1015	.irq = a5xx_irq,
1014	1016	.destroy = a5xx_destroy,
1015	1017	#ifdef CONFIG_DEBUG_FS
@@ -1045,7 +1047,7 @@ struct msm_gpu a5xx_gpu_init(struct drm_device dev) · 29 unmodified lines
1045	1047
1046	1048	a5xx_gpu->lm_leakage = 0x4E001A;
1047	1049
1048		− ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs);
	1050	+ ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1);
1049	1051	if (ret) {
1050	1052	a5xx_destroy(&(a5xx_gpu->base.base));
1051	1053	return ERR_PTR(ret);

drivers/gpu/drm/msm/adreno/a5xx_gpu.h+1−1

@@ -55,7 +55,7 @@ static inline int spin_usecs(struct msm_gpu *gpu, uint32_t usecs, · 54 unmodified lines
55	55	return -ETIMEDOUT;
56	56	}
57	57
58		−bool a5xx_idle(struct msm_gpu *gpu);
	58	+bool a5xx_idle(struct msm_gpu gpu, struct msm_ringbuffer ring);
59	59	void a5xx_set_hwcg(struct msm_gpu *gpu, bool state);
60	60
61	61	#endif /* __A5XX_GPU_H__ */

drivers/gpu/drm/msm/adreno/a5xx_power.c+3−3

@@ -173,7 +173,7 @@ static int a5xx_gpmu_init(struct msm_gpu *gpu) · 172 unmodified lines
173	173	{
174	174	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
175	175	struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);
176		− struct msm_ringbuffer *ring = gpu->rb;
	176	+ struct msm_ringbuffer *ring = gpu->rb[0];
177	177
178	178	if (!a5xx_gpu->gpmu_dwords)
179	179	return 0;
@@ -192,9 +192,9 @@ static int a5xx_gpmu_init(struct msm_gpu *gpu) · 12 unmodified lines
192	192	OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1);
193	193	OUT_RING(ring, 1);
194	194
195		− gpu->funcs->flush(gpu);
	195	+ gpu->funcs->flush(gpu, ring);
196	196
197		− if (!a5xx_idle(gpu)) {
	197	+ if (!a5xx_idle(gpu, ring)) {
198	198	DRM_ERROR("%s: Unable to load GPMU firmware. GPMU will not be active\n",
199	199	gpu->name);
200	200	return -EINVAL;

drivers/gpu/drm/msm/adreno/adreno_gpu.c+82−54

@@ -21,7 +21,6 @@ · 20 unmodified lines
21	21	#include "msm_gem.h"
22	22	#include "msm_mmu.h"
23	23
24		−#define RB_SIZE SZ_32K
25	24	#define RB_BLKSIZE 32
26	25
27	26	int adreno_get_param(struct msm_gpu gpu, uint32_t param, uint64_t value)
@@ -163,7 +162,7 @@ static int adreno_load_fw(struct adreno_gpu *adreno_gpu) · 135 unmodified lines
163	162	int adreno_hw_init(struct msm_gpu *gpu)
164	163	{
165	164	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
166		− int ret;
	165	+ int ret, i;
167	166
168	167	DBG("%s", gpu->name);
169	168
@@ -171,34 +170,42 @@ int adreno_hw_init(struct msm_gpu *gpu) · 1 unmodified line
171	170	if (ret)
172	171	return ret;
173	172
174		− ret = msm_gem_get_iova(gpu->rb->bo, gpu->aspace, &gpu->rb_iova);
175		− if (ret) {
176		− gpu->rb_iova = 0;
177		− dev_err(gpu->dev->dev, "could not map ringbuffer: %d\n", ret);
178		− return ret;
179		− }
	173	+ for (i = 0; i < gpu->nr_rings; i++) {
	174	+ struct msm_ringbuffer *ring = gpu->rb[i];
180	175
181		− /* reset ringbuffer: */
182		− gpu->rb->cur = gpu->rb->start;
	176	+ if (!ring)
	177	+ continue;
183	178
184		− /* reset completed fence seqno: */
185		− gpu->memptrs->fence = gpu->fctx->completed_fence;
186		− gpu->memptrs->rptr = 0;
	179	+ ret = msm_gem_get_iova(ring->bo, gpu->aspace, &ring->iova);
	180	+ if (ret) {
	181	+ ring->iova = 0;
	182	+ dev_err(gpu->dev->dev,
	183	+ "could not map ringbuffer %d: %d\n", i, ret);
	184	+ return ret;
	185	+ }
	186	+
	187	+ ring->cur = ring->start;
	188	+
	189	+ /* reset completed fence seqno: */
	190	+ ring->memptrs->fence = ring->seqno;
	191	+ ring->memptrs->rptr = 0;
	192	+ }
187	193
188	194	/* Setup REG_CP_RB_CNTL: */
189	195	adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_CNTL,
190		− /* size is log2(quad-words): */
191		− AXXX_CP_RB_CNTL_BUFSZ(ilog2(gpu->rb->size / 8)) \|
192		− AXXX_CP_RB_CNTL_BLKSZ(ilog2(RB_BLKSIZE / 8)) \|
193		− (adreno_is_a430(adreno_gpu) ? AXXX_CP_RB_CNTL_NO_UPDATE : 0));
	196	+ /* size is log2(quad-words): */
	197	+ AXXX_CP_RB_CNTL_BUFSZ(ilog2(MSM_GPU_RINGBUFFER_SZ / 8)) \|
	198	+ AXXX_CP_RB_CNTL_BLKSZ(ilog2(RB_BLKSIZE / 8)) \|
	199	+ (adreno_is_a430(adreno_gpu) ? AXXX_CP_RB_CNTL_NO_UPDATE : 0));
194	200
195		− /* Setup ringbuffer address: */
	201	+ /* Setup ringbuffer address - use ringbuffer[0] for GPU init */
196	202	adreno_gpu_write64(adreno_gpu, REG_ADRENO_CP_RB_BASE,
197		− REG_ADRENO_CP_RB_BASE_HI, gpu->rb_iova);
	203	+ REG_ADRENO_CP_RB_BASE_HI, gpu->rb[0]->iova);
198	204
199	205	if (!adreno_is_a430(adreno_gpu)) {
200	206	adreno_gpu_write64(adreno_gpu, REG_ADRENO_CP_RB_RPTR_ADDR,
201		− REG_ADRENO_CP_RB_RPTR_ADDR_HI, rbmemptr(gpu, rptr));
	207	+ REG_ADRENO_CP_RB_RPTR_ADDR_HI,
	208	+ rbmemptr(gpu->rb[0], rptr));
202	209	}
203	210
204	211	return 0;
@@ -210,15 +217,19 @@ static uint32_t get_wptr(struct msm_ringbuffer *ring) · 5 unmodified lines
210	217	}
211	218
212	219	/* Use this helper to read rptr, since a430 doesn't update rptr in memory */
213		−static uint32_t get_rptr(struct adreno_gpu *adreno_gpu)
	220	+static uint32_t get_rptr(struct adreno_gpu *adreno_gpu,
	221	+ struct msm_ringbuffer *ring)
214	222	{
215		− struct msm_gpu *gpu = &adreno_gpu->base;
216		−
217	223	if (adreno_is_a430(adreno_gpu))
218		− return gpu->memptrs->rptr = adreno_gpu_read(
	224	+ return ring->memptrs->rptr = adreno_gpu_read(
219	225	adreno_gpu, REG_ADRENO_CP_RB_RPTR);
220	226	else
221		− return gpu->memptrs->rptr;
	227	+ return ring->memptrs->rptr;
	228	+}
	229	+
	230	+struct msm_ringbuffer adreno_active_ring(struct msm_gpu gpu)
	231	+{
	232	+ return gpu->rb[0];
222	233	}
223	234
224	235	void adreno_recover(struct msm_gpu *gpu)
@@ -244,7 +255,7 @@ void adreno_submit(struct msm_gpu gpu, struct msm_gem_submit submit, · 19 unmodified lines
244	255	{
245	256	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
246	257	struct msm_drm_private *priv = gpu->dev->dev_private;
247		− struct msm_ringbuffer *ring = gpu->rb;
	258	+ struct msm_ringbuffer *ring = submit->ring;
248	259	unsigned i;
249	260
250	261	for (i = 0; i < submit->nr_cmds; i++) {
@@ -267,7 +278,7 @@ void adreno_submit(struct msm_gpu gpu, struct msm_gem_submit submit, · 16 unmodified lines
267	278	}
268	279
269	280	OUT_PKT0(ring, REG_AXXX_CP_SCRATCH_REG2, 1);
270		− OUT_RING(ring, submit->fence->seqno);
	281	+ OUT_RING(ring, submit->seqno);
271	282
272	283	if (adreno_is_a3xx(adreno_gpu) \|\| adreno_is_a4xx(adreno_gpu)) {
273	284	/* Flush HLSQ lazy updates to make sure there is nothing
@@ -283,8 +294,8 @@ void adreno_submit(struct msm_gpu gpu, struct msm_gem_submit submit, · 9 unmodified lines
283	294
284	295	OUT_PKT3(ring, CP_EVENT_WRITE, 3);
285	296	OUT_RING(ring, CACHE_FLUSH_TS);
286		− OUT_RING(ring, rbmemptr(gpu, fence));
287		− OUT_RING(ring, submit->fence->seqno);
	297	+ OUT_RING(ring, rbmemptr(ring, fence));
	298	+ OUT_RING(ring, submit->seqno);
288	299
289	300	/* we could maybe be clever and only CP_COND_EXEC the interrupt: */
290	301	OUT_PKT3(ring, CP_INTERRUPT, 1);
@@ -310,10 +321,10 @@ void adreno_submit(struct msm_gpu gpu, struct msm_gem_submit submit, · 19 unmodified lines
310	321	}
311	322	#endif
312	323
313		− gpu->funcs->flush(gpu);
	324	+ gpu->funcs->flush(gpu, ring);
314	325	}
315	326
316		−void adreno_flush(struct msm_gpu *gpu)
	327	+void adreno_flush(struct msm_gpu gpu, struct msm_ringbuffer ring)
317	328	{
318	329	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
319	330	uint32_t wptr;
@@ -323,7 +334,7 @@ void adreno_flush(struct msm_gpu *gpu) · 3 unmodified lines
323	334	* to account for the possibility that the last command fit exactly into
324	335	* the ringbuffer and rb->next hasn't wrapped to zero yet
325	336	*/
326		− wptr = get_wptr(gpu->rb) & ((gpu->rb->size / 4) - 1);
	337	+ wptr = get_wptr(ring) % (MSM_GPU_RINGBUFFER_SZ >> 2);
327	338
328	339	/* ensure writes to ringbuffer have hit system memory: */
329	340	mb();
@@ -331,17 +342,18 @@ void adreno_flush(struct msm_gpu *gpu) · 1 unmodified line
331	342	adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_WPTR, wptr);
332	343	}
333	344
334		−bool adreno_idle(struct msm_gpu *gpu)
	345	+bool adreno_idle(struct msm_gpu gpu, struct msm_ringbuffer ring)
335	346	{
336	347	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
337		− uint32_t wptr = get_wptr(gpu->rb);
	348	+ uint32_t wptr = get_wptr(ring);
338	349
339	350	/* wait for CP to drain ringbuffer: */
340		− if (!spin_until(get_rptr(adreno_gpu) == wptr))
	351	+ if (!spin_until(get_rptr(adreno_gpu, ring) == wptr))
341	352	return true;
342	353
343	354	/* TODO maybe we need to reset GPU here to recover from hang? */
344		− DRM_ERROR("%s: timeout waiting to drain ringbuffer!\n", gpu->name);
	355	+ DRM_ERROR("%s: timeout waiting to drain ringbuffer %d!\n", gpu->name,
	356	+ ring->id);
345	357	return false;
346	358	}
347	359
@@ -356,10 +368,16 @@ void adreno_show(struct msm_gpu gpu, struct seq_file m) · 8 unmodified lines
356	368	adreno_gpu->rev.major, adreno_gpu->rev.minor,
357	369	adreno_gpu->rev.patchid);
358	370
359		− seq_printf(m, "fence: %d/%d\n", gpu->memptrs->fence,
360		− gpu->fctx->last_fence);
361		− seq_printf(m, "rptr: %d\n", get_rptr(adreno_gpu));
362		− seq_printf(m, "rb wptr: %d\n", get_wptr(gpu->rb));
	371	+ for (i = 0; i < gpu->nr_rings; i++) {
	372	+ struct msm_ringbuffer *ring = gpu->rb[i];
	373	+
	374	+ seq_printf(m, "rb %d: fence: %d/%d\n", i,
	375	+ ring->memptrs->fence, ring->seqno);
	376	+
	377	+ seq_printf(m, " rptr: %d\n",
	378	+ get_rptr(adreno_gpu, ring));
	379	+ seq_printf(m, "rb wptr: %d\n", get_wptr(ring));
	380	+ }
363	381
364	382	/* dump these out in a form that can be parsed by demsm: */
365	383	seq_printf(m, "IO:region %s 00000000 00020000\n", gpu->name);
@@ -385,16 +403,23 @@ void adreno_show(struct msm_gpu gpu, struct seq_file m) · 19 unmodified lines
385	403	void adreno_dump_info(struct msm_gpu *gpu)
386	404	{
387	405	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
	406	+ int i;
388	407
389	408	printk("revision: %d (%d.%d.%d.%d)\n",
390	409	adreno_gpu->info->revn, adreno_gpu->rev.core,
391	410	adreno_gpu->rev.major, adreno_gpu->rev.minor,
392	411	adreno_gpu->rev.patchid);
393	412
394		− printk("fence: %d/%d\n", gpu->memptrs->fence,
395		− gpu->fctx->last_fence);
396		− printk("rptr: %d\n", get_rptr(adreno_gpu));
397		− printk("rb wptr: %d\n", get_wptr(gpu->rb));
	413	+ for (i = 0; i < gpu->nr_rings; i++) {
	414	+ struct msm_ringbuffer *ring = gpu->rb[i];
	415	+
	416	+ printk("rb %d: fence: %d/%d\n", i,
	417	+ ring->memptrs->fence,
	418	+ ring->seqno);
	419	+
	420	+ printk("rptr: %d\n", get_rptr(adreno_gpu, ring));
	421	+ printk("rb wptr: %d\n", get_wptr(ring));
	422	+ }
398	423	}
399	424
400	425	/* would be nice to not have to duplicate the _show() stuff with printk(): */
@@ -417,23 +442,26 @@ void adreno_dump(struct msm_gpu *gpu) · 16 unmodified lines
417	442	}
418	443	}
419	444
420		−static uint32_t ring_freewords(struct msm_gpu *gpu)
	445	+static uint32_t ring_freewords(struct msm_ringbuffer *ring)
421	446	{
422		− struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
423		− uint32_t size = gpu->rb->size / 4;
424		− uint32_t wptr = get_wptr(gpu->rb);
425		− uint32_t rptr = get_rptr(adreno_gpu);
	447	+ struct adreno_gpu *adreno_gpu = to_adreno_gpu(ring->gpu);
	448	+ uint32_t size = MSM_GPU_RINGBUFFER_SZ >> 2;
	449	+ uint32_t wptr = get_wptr(ring);
	450	+ uint32_t rptr = get_rptr(adreno_gpu, ring);
426	451	return (rptr + (size - 1) - wptr) % size;
427	452	}
428	453
429		−void adreno_wait_ring(struct msm_gpu *gpu, uint32_t ndwords)
	454	+void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords)
430	455	{
431		− if (spin_until(ring_freewords(gpu) >= ndwords))
432		− DRM_ERROR("%s: timeout waiting for ringbuffer space\n", gpu->name);
	456	+ if (spin_until(ring_freewords(ring) >= ndwords))
	457	+ DRM_DEV_ERROR(ring->gpu->dev->dev,
	458	+ "timeout waiting for space in ringubffer %d\n",
	459	+ ring->id);
433	460	}
434	461
435	462	int adreno_gpu_init(struct drm_device drm, struct platform_device pdev,
436		− struct adreno_gpu adreno_gpu, const struct adreno_gpu_funcs funcs)
	463	+ struct adreno_gpu *adreno_gpu,
	464	+ const struct adreno_gpu_funcs *funcs, int nr_rings)
437	465	{
438	466	struct adreno_platform_config *config = pdev->dev.platform_data;
439	467	struct msm_gpu_config adreno_gpu_config = { 0 };
@@ -460,7 +488,7 @@ int adreno_gpu_init(struct drm_device drm, struct platform_device pdev, · 20 unmodified lines
460	488	adreno_gpu_config.va_start = SZ_16M;
461	489	adreno_gpu_config.va_end = 0xffffffff;
462	490
463		− adreno_gpu_config.ringsz = RB_SIZE;
	491	+ adreno_gpu_config.nr_rings = nr_rings;
464	492
465	493	pm_runtime_set_autosuspend_delay(&pdev->dev, DRM_MSM_INACTIVE_PERIOD);
466	494	pm_runtime_use_autosuspend(&pdev->dev);

drivers/gpu/drm/msm/adreno/adreno_gpu.h+11−9

@@ -208,17 +208,19 @@ int adreno_hw_init(struct msm_gpu *gpu); · 207 unmodified lines
208	208	void adreno_recover(struct msm_gpu *gpu);
209	209	void adreno_submit(struct msm_gpu gpu, struct msm_gem_submit submit,
210	210	struct msm_file_private *ctx);
211		−void adreno_flush(struct msm_gpu *gpu);
212		−bool adreno_idle(struct msm_gpu *gpu);
	211	+void adreno_flush(struct msm_gpu gpu, struct msm_ringbuffer ring);
	212	+bool adreno_idle(struct msm_gpu gpu, struct msm_ringbuffer ring);
213	213	#ifdef CONFIG_DEBUG_FS
214	214	void adreno_show(struct msm_gpu gpu, struct seq_file m);
215	215	#endif
216	216	void adreno_dump_info(struct msm_gpu *gpu);
217	217	void adreno_dump(struct msm_gpu *gpu);
218		−void adreno_wait_ring(struct msm_gpu *gpu, uint32_t ndwords);
	218	+void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords);
	219	+struct msm_ringbuffer adreno_active_ring(struct msm_gpu gpu);
219	220
220	221	int adreno_gpu_init(struct drm_device drm, struct platform_device pdev,
221		− struct adreno_gpu gpu, const struct adreno_gpu_funcs funcs);
	222	+ struct adreno_gpu gpu, const struct adreno_gpu_funcs funcs,
	223	+ int nr_rings);
222	224	void adreno_gpu_cleanup(struct adreno_gpu *gpu);
223	225
224	226
@@ -227,7 +229,7 @@ void adreno_gpu_cleanup(struct adreno_gpu *gpu); · 2 unmodified lines
227	229	static inline void
228	230	OUT_PKT0(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
229	231	{
230		− adreno_wait_ring(ring->gpu, cnt+1);
	232	+ adreno_wait_ring(ring, cnt+1);
231	233	OUT_RING(ring, CP_TYPE0_PKT \| ((cnt-1) << 16) \| (regindx & 0x7FFF));
232	234	}
233	235
@@ -235,14 +237,14 @@ OUT_PKT0(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt) · 1 unmodified line
235	237	static inline void
236	238	OUT_PKT2(struct msm_ringbuffer *ring)
237	239	{
238		− adreno_wait_ring(ring->gpu, 1);
	240	+ adreno_wait_ring(ring, 1);
239	241	OUT_RING(ring, CP_TYPE2_PKT);
240	242	}
241	243
242	244	static inline void
243	245	OUT_PKT3(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
244	246	{
245		− adreno_wait_ring(ring->gpu, cnt+1);
	247	+ adreno_wait_ring(ring, cnt+1);
246	248	OUT_RING(ring, CP_TYPE3_PKT \| ((cnt-1) << 16) \| ((opcode & 0xFF) << 8));
247	249	}
248	250
@@ -264,14 +266,14 @@ static inline u32 PM4_PARITY(u32 val) · 15 unmodified lines
264	266	static inline void
265	267	OUT_PKT4(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
266	268	{
267		− adreno_wait_ring(ring->gpu, cnt + 1);
	269	+ adreno_wait_ring(ring, cnt + 1);
268	270	OUT_RING(ring, PKT4(regindx, cnt));
269	271	}
270	272
271	273	static inline void
272	274	OUT_PKT7(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
273	275	{
274		− adreno_wait_ring(ring->gpu, cnt + 1);
	276	+ adreno_wait_ring(ring, cnt + 1);
275	277	OUT_RING(ring, CP_TYPE7_PKT \| (cnt << 0) \| (PM4_PARITY(cnt) << 15) \|
276	278	((opcode & 0x7F) << 16) \| (PM4_PARITY(opcode) << 23));
277	279	}

drivers/gpu/drm/msm/msm_drv.c+17−6

@@ -507,7 +507,7 @@ static void load_gpu(struct drm_device *dev) · 506 unmodified lines
507	507	mutex_unlock(&init_lock);
508	508	}
509	509
510		−static int context_init(struct drm_file *file)
	510	+static int context_init(struct drm_device dev, struct drm_file file)
511	511	{
512	512	struct msm_file_private *ctx;
513	513
@@ -515,7 +515,7 @@ static int context_init(struct drm_file *file) · 1 unmodified line
515	515	if (!ctx)
516	516	return -ENOMEM;
517	517
518		− msm_submitqueue_init(ctx);
	518	+ msm_submitqueue_init(dev, ctx);
519	519
520	520	file->driver_priv = ctx;
521	521
@@ -529,7 +529,7 @@ static int msm_open(struct drm_device dev, struct drm_file file) · 7 unmodified lines
529	529	*/
530	530	load_gpu(dev);
531	531
532		− return context_init(file);
	532	+ return context_init(dev, file);
533	533	}
534	534
535	535	static void context_close(struct msm_file_private *ctx)
@@ -743,16 +743,27 @@ static int msm_ioctl_wait_fence(struct drm_device dev, void data, · 207 unmodified lines
743	743	struct msm_drm_private *priv = dev->dev_private;
744	744	struct drm_msm_wait_fence *args = data;
745	745	ktime_t timeout = to_ktime(args->timeout);
	746	+ struct msm_gpu_submitqueue *queue;
	747	+ struct msm_gpu *gpu = priv->gpu;
	748	+ int ret;
746	749
747	750	if (args->pad) {
748	751	DRM_ERROR("invalid pad: %08x\n", args->pad);
749	752	return -EINVAL;
750	753	}
751	754
752		− if (!priv->gpu)
	755	+ if (!gpu)
753	756	return 0;
754	757
755		− return msm_wait_fence(priv->gpu->fctx, args->fence, &timeout, true);
	758	+ queue = msm_submitqueue_get(file->driver_priv, args->queueid);
	759	+ if (!queue)
	760	+ return -ENOENT;
	761	+
	762	+ ret = msm_wait_fence(gpu->rb[queue->prio]->fctx, args->fence, &timeout,
	763	+ true);
	764	+
	765	+ msm_submitqueue_put(queue);
	766	+ return ret;
756	767	}
757	768
758	769	static int msm_ioctl_gem_madvise(struct drm_device dev, void data,
@@ -802,7 +813,7 @@ static int msm_ioctl_submitqueue_new(struct drm_device dev, void data, · 43 unmodified lines
802	813	if (args->flags & ~MSM_SUBMITQUEUE_FLAGS)
803	814	return -EINVAL;
804	815
805		− return msm_submitqueue_create(file->driver_priv, args->prio,
	816	+ return msm_submitqueue_create(dev, file->driver_priv, args->prio,
806	817	args->flags, &args->id);
807	818	}
808	819

drivers/gpu/drm/msm/msm_drv.h+5−3

@@ -74,6 +74,8 @@ struct msm_vblank_ctrl { · 73 unmodified lines
74	74	spinlock_t lock;
75	75	};
76	76
	77	+#define MSM_GPU_MAX_RINGS 1
	78	+
77	79	struct msm_drm_private {
78	80
79	81	struct drm_device *dev;
@@ -318,11 +320,11 @@ void msm_writel(u32 data, void __iomem *addr); · 238 unmodified lines
318	320	u32 msm_readl(const void __iomem *addr);
319	321
320	322	struct msm_gpu_submitqueue;
321		−int msm_submitqueue_init(struct msm_file_private *ctx);
	323	+int msm_submitqueue_init(struct drm_device drm, struct msm_file_private ctx);
322	324	struct msm_gpu_submitqueue msm_submitqueue_get(struct msm_file_private ctx,
323	325	u32 id);
324		−int msm_submitqueue_create(struct msm_file_private *ctx, u32 prio,
325		− u32 flags, u32 *id);
	326	+int msm_submitqueue_create(struct drm_device drm, struct msm_file_private ctx,
	327	+ u32 prio, u32 flags, u32 *id);
326	328	int msm_submitqueue_remove(struct msm_file_private *ctx, u32 id);
327	329	void msm_submitqueue_close(struct msm_file_private *ctx);
328	330

drivers/gpu/drm/msm/msm_fence.c+1−1

@@ -31,7 +31,7 @@ msm_fence_context_alloc(struct drm_device dev, const char name) · 30 unmodified lines
31	31	return ERR_PTR(-ENOMEM);
32	32
33	33	fctx->dev = dev;
34		− fctx->name = name;
	34	+ strncpy(fctx->name, name, sizeof(fctx->name));
35	35	fctx->context = dma_fence_context_alloc(1);
36	36	init_waitqueue_head(&fctx->event);
37	37	spin_lock_init(&fctx->spinlock);

drivers/gpu/drm/msm/msm_fence.h+1−1

@@ -22,7 +22,7 @@ · 21 unmodified lines
22	22
23	23	struct msm_fence_context {
24	24	struct drm_device *dev;
25		− const char *name;
	25	+ char name[32];
26	26	unsigned context;
27	27	/* last_fence == completed_fence --> no pending work */
28	28	uint32_t last_fence; /* last assigned fence */

drivers/gpu/drm/msm/msm_gem.h+3−1

@@ -138,13 +138,15 @@ void msm_gem_vunmap(struct drm_gem_object *obj, enum msm_gem_lock subclass); · 137 unmodified lines
138	138	struct msm_gem_submit {
139	139	struct drm_device *dev;
140	140	struct msm_gpu *gpu;
141		− struct list_head node; /* node in gpu submit_list */
	141	+ struct list_head node; /* node in ring submit list */
142	142	struct list_head bo_list;
143	143	struct ww_acquire_ctx ticket;
	144	+ uint32_t seqno; /* Sequence number of the submit on the ring */
144	145	struct dma_fence *fence;
145	146	struct msm_gpu_submitqueue *queue;
146	147	struct pid pid; / submitting process */
147	148	bool valid; /* true if no cmdstream patching needed */
	149	+ struct msm_ringbuffer *ring;
148	150	unsigned int nr_cmds;
149	151	unsigned int nr_bos;
150	152	struct {

drivers/gpu/drm/msm/msm_gem_submit.c+8−4

@@ -51,6 +51,7 @@ static struct msm_gem_submit submit_create(struct drm_device dev, · 50 unmodified lines
51	51	submit->pid = get_pid(task_pid(current));
52	52	submit->cmd = (void *)&submit->bos[nr_bos];
53	53	submit->queue = queue;
	54	+ submit->ring = gpu->rb[queue->prio];
54	55
55	56	/* initially, until copy_from_user() and bo lookup succeeds: */
56	57	submit->nr_bos = 0;
@@ -247,7 +248,8 @@ static int submit_fence_sync(struct msm_gem_submit *submit, bool no_implicit) · 190 unmodified lines
247	248	if (no_implicit)
248	249	continue;
249	250
250		− ret = msm_gem_sync_object(&msm_obj->base, submit->gpu->fctx, write);
	251	+ ret = msm_gem_sync_object(&msm_obj->base, submit->ring->fctx,
	252	+ write);
251	253	if (ret)
252	254	break;
253	255	}
@@ -410,6 +412,7 @@ int msm_ioctl_gem_submit(struct drm_device dev, void data, · 156 unmodified lines
410	412	struct dma_fence *in_fence = NULL;
411	413	struct sync_file *sync_file = NULL;
412	414	struct msm_gpu_submitqueue *queue;
	415	+ struct msm_ringbuffer *ring;
413	416	int out_fence_fd = -1;
414	417	unsigned i;
415	418	int ret;
@@ -430,6 +433,8 @@ int msm_ioctl_gem_submit(struct drm_device dev, void data, · 14 unmodified lines
430	433	if (!queue)
431	434	return -ENOENT;
432	435
	436	+ ring = gpu->rb[queue->prio];
	437	+
433	438	if (args->flags & MSM_SUBMIT_FENCE_FD_IN) {
434	439	in_fence = sync_file_get_fence(args->fence_fd);
435	440
@@ -440,7 +445,7 @@ int msm_ioctl_gem_submit(struct drm_device dev, void data, · 4 unmodified lines
440	445	* Wait if the fence is from a foreign context, or if the fence
441	446	* array contains any fence from a foreign context.
442	447	*/
443		− if (!dma_fence_match_context(in_fence, gpu->fctx->context)) {
	448	+ if (!dma_fence_match_context(in_fence, ring->fctx->context)) {
444	449	ret = dma_fence_wait(in_fence, true);
445	450	if (ret)
446	451	return ret;
@@ -543,8 +548,7 @@ int msm_ioctl_gem_submit(struct drm_device dev, void data, · 96 unmodified lines
543	548
544	549	submit->nr_cmds = i;
545	550
546		− submit->fence = msm_fence_alloc(gpu->fctx);
547		−
	551	+ submit->fence = msm_fence_alloc(ring->fctx);
548	552	if (IS_ERR(submit->fence)) {
549	553	ret = PTR_ERR(submit->fence);
550	554	submit->fence = NULL;

drivers/gpu/drm/msm/msm_gpu.c+111−52

@@ -221,6 +221,20 @@ int msm_gpu_hw_init(struct msm_gpu *gpu) · 220 unmodified lines
221	221	* Hangcheck detection for locked gpu:
222	222	*/
223	223
	224	+static void update_fences(struct msm_gpu gpu, struct msm_ringbuffer ring,
	225	+ uint32_t fence)
	226	+{
	227	+ struct msm_gem_submit *submit;
	228	+
	229	+ list_for_each_entry(submit, &ring->submits, node) {
	230	+ if (submit->seqno > fence)
	231	+ break;
	232	+
	233	+ msm_update_fence(submit->ring->fctx,
	234	+ submit->fence->seqno);
	235	+ }
	236	+}
	237	+
224	238	static void retire_submits(struct msm_gpu *gpu);
225	239
226	240	static void recover_worker(struct work_struct *work)
@@ -228,15 +242,34 @@ static void recover_worker(struct work_struct *work) · 1 unmodified line
228	242	struct msm_gpu *gpu = container_of(work, struct msm_gpu, recover_work);
229	243	struct drm_device *dev = gpu->dev;
230	244	struct msm_gem_submit *submit;
231		− uint32_t fence = gpu->memptrs->fence;
	245	+ struct msm_ringbuffer *cur_ring = gpu->funcs->active_ring(gpu);
	246	+ uint64_t fence;
	247	+ int i;
	248	+
	249	+ /* Update all the rings with the latest and greatest fence */
	250	+ for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) {
	251	+ struct msm_ringbuffer *ring = gpu->rb[i];
232	252
233		− msm_update_fence(gpu->fctx, fence + 1);
	253	+ fence = ring->memptrs->fence;
	254	+
	255	+ /*
	256	+ * For the current (faulting?) ring/submit advance the fence by
	257	+ * one more to clear the faulting submit
	258	+ */
	259	+ if (ring == cur_ring)
	260	+ fence = fence + 1;
	261	+
	262	+ update_fences(gpu, ring, fence);
	263	+ }
234	264
235	265	mutex_lock(&dev->struct_mutex);
236	266
	267	+
237	268	dev_err(dev->dev, "%s: hangcheck recover!\n", gpu->name);
238		− list_for_each_entry(submit, &gpu->submit_list, node) {
239		− if (submit->fence->seqno == (fence + 1)) {
	269	+ fence = cur_ring->memptrs->fence + 1;
	270	+
	271	+ list_for_each_entry(submit, &cur_ring->submits, node) {
	272	+ if (submit->seqno == fence) {
240	273	struct task_struct *task;
241	274
242	275	rcu_read_lock();
@@ -258,9 +291,16 @@ static void recover_worker(struct work_struct *work) · 15 unmodified lines
258	291	gpu->funcs->recover(gpu);
259	292	pm_runtime_put_sync(&gpu->pdev->dev);
260	293
261		− /* replay the remaining submits after the one that hung: */
262		− list_for_each_entry(submit, &gpu->submit_list, node) {
263		− gpu->funcs->submit(gpu, submit, NULL);
	294	+ /*
	295	+ * Replay all remaining submits starting with highest priority
	296	+ * ring
	297	+ */
	298	+
	299	+ for (i = gpu->nr_rings - 1; i >= 0; i--) {
	300	+ struct msm_ringbuffer *ring = gpu->rb[i];
	301	+
	302	+ list_for_each_entry(submit, &ring->submits, node)
	303	+ gpu->funcs->submit(gpu, submit, NULL);
264	304	}
265	305	}
266	306
@@ -281,25 +321,27 @@ static void hangcheck_handler(unsigned long data) · 14 unmodified lines
281	321	struct msm_gpu gpu = (struct msm_gpu )data;
282	322	struct drm_device *dev = gpu->dev;
283	323	struct msm_drm_private *priv = dev->dev_private;
284		− uint32_t fence = gpu->memptrs->fence;
	324	+ struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu);
	325	+ uint32_t fence = ring->memptrs->fence;
285	326
286		− if (fence != gpu->hangcheck_fence) {
	327	+ if (fence != ring->hangcheck_fence) {
287	328	/* some progress has been made.. ya! */
288		− gpu->hangcheck_fence = fence;
289		− } else if (fence < gpu->fctx->last_fence) {
	329	+ ring->hangcheck_fence = fence;
	330	+ } else if (fence < ring->seqno) {
290	331	/* no progress and not done.. hung! */
291		− gpu->hangcheck_fence = fence;
292		− dev_err(dev->dev, "%s: hangcheck detected gpu lockup!\n",
293		− gpu->name);
	332	+ ring->hangcheck_fence = fence;
	333	+ dev_err(dev->dev, "%s: hangcheck detected gpu lockup rb %d!\n",
	334	+ gpu->name, ring->id);
294	335	dev_err(dev->dev, "%s: completed fence: %u\n",
295	336	gpu->name, fence);
296	337	dev_err(dev->dev, "%s: submitted fence: %u\n",
297		− gpu->name, gpu->fctx->last_fence);
	338	+ gpu->name, ring->seqno);
	339	+
298	340	queue_work(priv->wq, &gpu->recover_work);
299	341	}
300	342
301	343	/* if still more pending work, reset the hangcheck timer: */
302		− if (gpu->fctx->last_fence > gpu->hangcheck_fence)
	344	+ if (ring->seqno > ring->hangcheck_fence)
303	345	hangcheck_timer_reset(gpu);
304	346
305	347	/* workaround for missing irq: */
@@ -428,19 +470,18 @@ static void retire_submit(struct msm_gpu gpu, struct msm_gem_submit submit) · 122 unmodified lines
428	470	static void retire_submits(struct msm_gpu *gpu)
429	471	{
430	472	struct drm_device *dev = gpu->dev;
	473	+ struct msm_gem_submit submit, tmp;
	474	+ int i;
431	475
432	476	WARN_ON(!mutex_is_locked(&dev->struct_mutex));
433	477
434		− while (!list_empty(&gpu->submit_list)) {
435		− struct msm_gem_submit *submit;
436		−
437		− submit = list_first_entry(&gpu->submit_list,
438		− struct msm_gem_submit, node);
	478	+ /* Retire the commits starting with highest priority */
	479	+ for (i = gpu->nr_rings - 1; i >= 0; i--) {
	480	+ struct msm_ringbuffer *ring = gpu->rb[i];
439	481
440		− if (dma_fence_is_signaled(submit->fence)) {
441		− retire_submit(gpu, submit);
442		− } else {
443		− break;
	482	+ list_for_each_entry_safe(submit, tmp, &ring->submits, node) {
	483	+ if (dma_fence_is_signaled(submit->fence))
	484	+ retire_submit(gpu, submit);
444	485	}
445	486	}
446	487	}
@@ -449,9 +490,10 @@ static void retire_worker(struct work_struct *work) · 2 unmodified lines
449	490	{
450	491	struct msm_gpu *gpu = container_of(work, struct msm_gpu, retire_work);
451	492	struct drm_device *dev = gpu->dev;
452		− uint32_t fence = gpu->memptrs->fence;
	493	+ int i;
453	494
454		− msm_update_fence(gpu->fctx, fence);
	495	+ for (i = 0; i < gpu->nr_rings; i++)
	496	+ update_fences(gpu, gpu->rb[i], gpu->rb[i]->memptrs->fence);
455	497
456	498	mutex_lock(&dev->struct_mutex);
457	499	retire_submits(gpu);
@@ -472,6 +514,7 @@ void msm_gpu_submit(struct msm_gpu gpu, struct msm_gem_submit submit, · 14 unmodified lines
472	514	{
473	515	struct drm_device *dev = gpu->dev;
474	516	struct msm_drm_private *priv = dev->dev_private;
	517	+ struct msm_ringbuffer *ring = submit->ring;
475	518	int i;
476	519
477	520	WARN_ON(!mutex_is_locked(&dev->struct_mutex));
@@ -480,7 +523,9 @@ void msm_gpu_submit(struct msm_gpu gpu, struct msm_gem_submit submit, · 2 unmodified lines
480	523
481	524	msm_gpu_hw_init(gpu);
482	525
483		− list_add_tail(&submit->node, &gpu->submit_list);
	526	+ submit->seqno = ++ring->seqno;
	527	+
	528	+ list_add_tail(&submit->node, &ring->submits);
484	529
485	530	msm_rd_dump_submit(submit);
486	531
@@ -605,7 +650,9 @@ int msm_gpu_init(struct drm_device drm, struct platform_device pdev, · 118 unmodified lines
605	650	struct msm_gpu gpu, const struct msm_gpu_funcs funcs,
606	651	const char name, struct msm_gpu_config config)
607	652	{
608		− int ret;
	653	+ int i, ret, nr_rings = config->nr_rings;
	654	+ void *memptrs;
	655	+ uint64_t memptrs_iova;
609	656
610	657	if (WARN_ON(gpu->num_perfcntrs > ARRAY_SIZE(gpu->last_cntrs)))
611	658	gpu->num_perfcntrs = ARRAY_SIZE(gpu->last_cntrs);
@@ -613,18 +660,11 @@ int msm_gpu_init(struct drm_device drm, struct platform_device pdev, · 1 unmodified line
613	660	gpu->dev = drm;
614	661	gpu->funcs = funcs;
615	662	gpu->name = name;
616		− gpu->fctx = msm_fence_context_alloc(drm, name);
617		− if (IS_ERR(gpu->fctx)) {
618		− ret = PTR_ERR(gpu->fctx);
619		− gpu->fctx = NULL;
620		− goto fail;
621		− }
622	663
623	664	INIT_LIST_HEAD(&gpu->active_list);
624	665	INIT_WORK(&gpu->retire_work, retire_worker);
625	666	INIT_WORK(&gpu->recover_work, recover_worker);
626	667
627		− INIT_LIST_HEAD(&gpu->submit_list);
628	668
629	669	setup_timer(&gpu->hangcheck_timer, hangcheck_handler,
630	670	(unsigned long)gpu);
@@ -689,29 +729,47 @@ int msm_gpu_init(struct drm_device drm, struct platform_device pdev, · 58 unmodified lines
689	729	goto fail;
690	730	}
691	731
692		− gpu->memptrs = msm_gem_kernel_new(drm, sizeof(*gpu->memptrs_bo),
	732	+ memptrs = msm_gem_kernel_new(drm, sizeof(*gpu->memptrs_bo),
693	733	MSM_BO_UNCACHED, gpu->aspace, &gpu->memptrs_bo,
694		− &gpu->memptrs_iova);
	734	+ &memptrs_iova);
695	735
696		− if (IS_ERR(gpu->memptrs)) {
697		− ret = PTR_ERR(gpu->memptrs);
698		− gpu->memptrs = NULL;
	736	+ if (IS_ERR(memptrs)) {
	737	+ ret = PTR_ERR(memptrs);
699	738	dev_err(drm->dev, "could not allocate memptrs: %d\n", ret);
700	739	goto fail;
701	740	}
702	741
703		− /* Create ringbuffer: */
704		− gpu->rb = msm_ringbuffer_new(gpu, config->ringsz);
705		− if (IS_ERR(gpu->rb)) {
706		− ret = PTR_ERR(gpu->rb);
707		− gpu->rb = NULL;
708		− dev_err(drm->dev, "could not create ringbuffer: %d\n", ret);
709		− goto fail;
	742	+ if (nr_rings > ARRAY_SIZE(gpu->rb)) {
	743	+ DRM_DEV_INFO_ONCE(drm->dev, "Only creating %lu ringbuffers\n",
	744	+ ARRAY_SIZE(gpu->rb));
	745	+ nr_rings = ARRAY_SIZE(gpu->rb);
710	746	}
711	747
	748	+ /* Create ringbuffer(s): */
	749	+ for (i = 0; i < nr_rings; i++) {
	750	+ gpu->rb[i] = msm_ringbuffer_new(gpu, i, memptrs, memptrs_iova);
	751	+
	752	+ if (IS_ERR(gpu->rb[i])) {
	753	+ ret = PTR_ERR(gpu->rb[i]);
	754	+ dev_err(drm->dev,
	755	+ "could not create ringbuffer %d: %d\n", i, ret);
	756	+ goto fail;
	757	+ }
	758	+
	759	+ memptrs += sizeof(struct msm_rbmemptrs);
	760	+ memptrs_iova += sizeof(struct msm_rbmemptrs);
	761	+ }
	762	+
	763	+ gpu->nr_rings = nr_rings;
	764	+
712	765	return 0;
713	766
714	767	fail:
	768	+ for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) {
	769	+ msm_ringbuffer_destroy(gpu->rb[i]);
	770	+ gpu->rb[i] = NULL;
	771	+ }
	772	+
715	773	if (gpu->memptrs_bo) {
716	774	msm_gem_put_vaddr(gpu->memptrs_bo);
717	775	msm_gem_put_iova(gpu->memptrs_bo, gpu->aspace);
@@ -724,16 +782,17 @@ fail: · 6 unmodified lines
724	782
725	783	void msm_gpu_cleanup(struct msm_gpu *gpu)
726	784	{
	785	+ int i;
	786	+
727	787	DBG("%s", gpu->name);
728	788
729	789	WARN_ON(!list_empty(&gpu->active_list));
730	790
731	791	bs_fini(gpu);
732	792
733		− if (gpu->rb) {
734		− if (gpu->rb_iova)
735		− msm_gem_put_iova(gpu->rb->bo, gpu->aspace);
736		− msm_ringbuffer_destroy(gpu->rb);
	793	+ for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) {
	794	+ msm_ringbuffer_destroy(gpu->rb[i]);
	795	+ gpu->rb[i] = NULL;
737	796	}
738	797
739	798	if (gpu->memptrs_bo) {

drivers/gpu/drm/msm/msm_gpu.h+18−24

@@ -33,7 +33,7 @@ struct msm_gpu_config { · 32 unmodified lines
33	33	const char *irqname;
34	34	uint64_t va_start;
35	35	uint64_t va_end;
36		− unsigned int ringsz;
	36	+ unsigned int nr_rings;
37	37	};
38	38
39	39	/* So far, with hardware that I've seen to date, we can have:
@@ -57,8 +57,9 @@ struct msm_gpu_funcs { · 17 unmodified lines
57	57	int (pm_resume)(struct msm_gpu gpu);
58	58	void (submit)(struct msm_gpu gpu, struct msm_gem_submit *submit,
59	59	struct msm_file_private *ctx);
60		− void (flush)(struct msm_gpu gpu);
	60	+ void (flush)(struct msm_gpu gpu, struct msm_ringbuffer *ring);
61	61	irqreturn_t (irq)(struct msm_gpu irq);
	62	+ struct msm_ringbuffer (active_ring)(struct msm_gpu *gpu);
62	63	void (recover)(struct msm_gpu gpu);
63	64	void (destroy)(struct msm_gpu gpu);
64	65	#ifdef CONFIG_DEBUG_FS
@@ -67,14 +68,6 @@ struct msm_gpu_funcs { · 2 unmodified lines
67	68	#endif
68	69	};
69	70
70		−#define rbmemptr(gpu, member) \
71		− ((gpu)->memptrs_iova + offsetof(struct msm_rbmemptrs, member))
72		−
73		−struct msm_rbmemptrs {
74		− volatile uint32_t rptr;
75		− volatile uint32_t fence;
76		−};
77		−
78	71	struct msm_gpu {
79	72	const char *name;
80	73	struct drm_device *dev;
@@ -93,16 +86,12 @@ struct msm_gpu { · 12 unmodified lines
93	86	const struct msm_gpu_perfcntr *perfcntrs;
94	87	uint32_t num_perfcntrs;
95	88
96		− /* ringbuffer: */
97		− struct msm_ringbuffer *rb;
98		− uint64_t rb_iova;
	89	+ struct msm_ringbuffer *rb[MSM_GPU_MAX_RINGS];
	90	+ int nr_rings;
99	91
100	92	/* list of GEM active objects: */
101	93	struct list_head active_list;
102	94
103		− /* fencing: */
104		− struct msm_fence_context *fctx;
105		−
106	95	/* does gpu need hw_init? */
107	96	bool needs_hw_init;
108	97
@@ -133,21 +122,26 @@ struct msm_gpu { · 24 unmodified lines
133	122	#define DRM_MSM_HANGCHECK_PERIOD 500 /* in ms */
134	123	#define DRM_MSM_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_MSM_HANGCHECK_PERIOD)
135	124	struct timer_list hangcheck_timer;
136		− uint32_t hangcheck_fence;
137	125	struct work_struct recover_work;
138	126
139		− struct list_head submit_list;
140		−
141		− struct msm_rbmemptrs *memptrs;
142	127	struct drm_gem_object *memptrs_bo;
143		− uint64_t memptrs_iova;
144		−
145		−
146	128	};
147	129
	130	+/* It turns out that all targets use the same ringbuffer size */
	131	+#define MSM_GPU_RINGBUFFER_SZ SZ_32K
	132	+
148	133	static inline bool msm_gpu_active(struct msm_gpu *gpu)
149	134	{
150		− return gpu->fctx->last_fence > gpu->memptrs->fence;
	135	+ int i;
	136	+
	137	+ for (i = 0; i < gpu->nr_rings; i++) {
	138	+ struct msm_ringbuffer *ring = gpu->rb[i];
	139	+
	140	+ if (ring->seqno > ring->memptrs->fence)
	141	+ return true;
	142	+ }
	143	+
	144	+ return false;
151	145	}
152	146
153	147	/* Perf-Counters:

drivers/gpu/drm/msm/msm_ringbuffer.c+24−10

@@ -18,13 +18,15 @@ · 17 unmodified lines
18	18	#include "msm_ringbuffer.h"
19	19	#include "msm_gpu.h"
20	20
21		−struct msm_ringbuffer msm_ringbuffer_new(struct msm_gpu gpu, int size)
	21	+struct msm_ringbuffer msm_ringbuffer_new(struct msm_gpu gpu, int id,
	22	+ void *memptrs, uint64_t memptrs_iova)
22	23	{
23	24	struct msm_ringbuffer *ring;
	25	+ char name[32];
24	26	int ret;
25	27
26		− if (WARN_ON(!is_power_of_2(size)))
27		− return ERR_PTR(-EINVAL);
	28	+ /* We assume everwhere that MSM_GPU_RINGBUFFER_SZ is a power of 2 */
	29	+ BUILD_BUG_ON(!is_power_of_2(MSM_GPU_RINGBUFFER_SZ));
28	30
29	31	ring = kzalloc(sizeof(*ring), GFP_KERNEL);
30	32	if (!ring) {
@@ -33,32 +35,44 @@ struct msm_ringbuffer msm_ringbuffer_new(struct msm_gpu gpu, int size) · 2 unmodified lines
33	35	}
34	36
35	37	ring->gpu = gpu;
36		−
	38	+ ring->id = id;
37	39	/* Pass NULL for the iova pointer - we will map it later */
38		− ring->start = msm_gem_kernel_new(gpu->dev, size, MSM_BO_WC,
39		− gpu->aspace, &ring->bo, NULL);
	40	+ ring->start = msm_gem_kernel_new(gpu->dev, MSM_GPU_RINGBUFFER_SZ,
	41	+ MSM_BO_WC, gpu->aspace, &ring->bo, NULL);
40	42
41	43	if (IS_ERR(ring->start)) {
42	44	ret = PTR_ERR(ring->start);
43	45	ring->start = 0;
44	46	goto fail;
45	47	}
46		− ring->end = ring->start + (size / 4);
	48	+ ring->end = ring->start + (MSM_GPU_RINGBUFFER_SZ >> 2);
47	49	ring->cur = ring->start;
48	50
49		− ring->size = size;
	51	+ ring->memptrs = memptrs;
	52	+ ring->memptrs_iova = memptrs_iova;
	53	+
	54	+ INIT_LIST_HEAD(&ring->submits);
	55	+
	56	+ snprintf(name, sizeof(name), "gpu-ring-%d", ring->id);
	57	+
	58	+ ring->fctx = msm_fence_context_alloc(gpu->dev, name);
50	59
51	60	return ring;
52	61
53	62	fail:
54		− if (ring)
55		− msm_ringbuffer_destroy(ring);
	63	+ msm_ringbuffer_destroy(ring);
56	64	return ERR_PTR(ret);
57	65	}
58	66
59	67	void msm_ringbuffer_destroy(struct msm_ringbuffer *ring)
60	68	{
	69	+ if (IS_ERR_OR_NULL(ring))
	70	+ return;
	71	+
	72	+ msm_fence_context_free(ring->fctx);
	73	+
61	74	if (ring->bo) {
	75	+ msm_gem_put_iova(ring->bo, ring->gpu->aspace);
62	76	msm_gem_put_vaddr(ring->bo);
63	77	drm_gem_object_unreference_unlocked(ring->bo);
64	78	}

drivers/gpu/drm/msm/msm_ringbuffer.h+18−2

@@ -20,14 +20,30 @@ · 19 unmodified lines
20	20
21	21	#include "msm_drv.h"
22	22
	23	+#define rbmemptr(ring, member) \
	24	+ ((ring)->memptrs_iova + offsetof(struct msm_rbmemptrs, member))
	25	+
	26	+struct msm_rbmemptrs {
	27	+ volatile uint32_t rptr;
	28	+ volatile uint32_t fence;
	29	+};
	30	+
23	31	struct msm_ringbuffer {
24	32	struct msm_gpu *gpu;
25		− int size;
	33	+ int id;
26	34	struct drm_gem_object *bo;
27	35	uint32_t start, end, *cur;
	36	+ struct list_head submits;
	37	+ uint64_t iova;
	38	+ uint32_t seqno;
	39	+ uint32_t hangcheck_fence;
	40	+ struct msm_rbmemptrs *memptrs;
	41	+ uint64_t memptrs_iova;
	42	+ struct msm_fence_context *fctx;
28	43	};
29	44
30		−struct msm_ringbuffer msm_ringbuffer_new(struct msm_gpu gpu, int size);
	45	+struct msm_ringbuffer msm_ringbuffer_new(struct msm_gpu gpu, int id,
	46	+ void *memptrs, uint64_t memptrs_iova);
31	47	void msm_ringbuffer_destroy(struct msm_ringbuffer *ring);
32	48
33	49	/* ringbuffer helpers (the parts that are same for a3xx/a2xx/z180..) */

drivers/gpu/drm/msm/msm_submitqueue.c+22−5

@@ -60,9 +60,10 @@ void msm_submitqueue_close(struct msm_file_private *ctx) · 59 unmodified lines
60	60	msm_submitqueue_put(entry);
61	61	}
62	62
63		−int msm_submitqueue_create(struct msm_file_private *ctx, u32 prio, u32 flags,
64		− u32 *id)
	63	+int msm_submitqueue_create(struct drm_device drm, struct msm_file_private ctx,
	64	+ u32 prio, u32 flags, u32 *id)
65	65	{
	66	+ struct msm_drm_private *priv = drm->dev_private;
66	67	struct msm_gpu_submitqueue *queue;
67	68
68	69	if (!ctx)
@@ -75,7 +76,13 @@ int msm_submitqueue_create(struct msm_file_private *ctx, u32 prio, u32 flags, · 6 unmodified lines
75	76
76	77	kref_init(&queue->ref);
77	78	queue->flags = flags;
78		− queue->prio = prio;
	79	+
	80	+ if (priv->gpu) {
	81	+ if (prio >= priv->gpu->nr_rings)
	82	+ return -EINVAL;
	83	+
	84	+ queue->prio = prio;
	85	+ }
79	86
80	87	write_lock(&ctx->queuelock);
81	88
@@ -91,16 +98,26 @@ int msm_submitqueue_create(struct msm_file_private *ctx, u32 prio, u32 flags, · 9 unmodified lines
91	98	return 0;
92	99	}
93	100
94		−int msm_submitqueue_init(struct msm_file_private *ctx)
	101	+int msm_submitqueue_init(struct drm_device drm, struct msm_file_private ctx)
95	102	{
	103	+ struct msm_drm_private *priv = drm->dev_private;
	104	+ int default_prio;
	105	+
96	106	if (!ctx)
97	107	return 0;
98	108
	109	+ /*
	110	+ * Select priority 2 as the "default priority" unless nr_rings is less
	111	+ * than 2 and then pick the lowest pirority
	112	+ */
	113	+ default_prio = priv->gpu ?
	114	+ clamp_t(uint32_t, 2, 0, priv->gpu->nr_rings - 1) : 0;
	115	+
99	116	INIT_LIST_HEAD(&ctx->submitqueues);
100	117
101	118	rwlock_init(&ctx->queuelock);
102	119
103		− return msm_submitqueue_create(ctx, 2, 0, NULL);
	120	+ return msm_submitqueue_create(drm, ctx, default_prio, 0, NULL);
104	121	}
105	122
106	123	int msm_submitqueue_remove(struct msm_file_private *ctx, u32 id)

include/dt-bindings/msm/msm-bus-ids.h+887−0

@@ -0,0 +1,887 @@
	1	+/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
	2	+ *
	3	+ * This program is free software; you can redistribute it and/or modify
	4	+ * it under the terms of the GNU General Public License version 2 and
	5	+ * only version 2 as published by the Free Software Foundation.
	6	+ *
	7	+ * This program is distributed in the hope that it will be useful,
	8	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	9	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	10	+ * GNU General Public License for more details.
	11	+ */
	12	+
	13	+#ifndef __MSM_BUS_IDS_H
	14	+#define __MSM_BUS_IDS_H
	15	+
	16	+/* Aggregation types */
	17	+#define AGG_SCHEME_NONE 0
	18	+#define AGG_SCHEME_LEG 1
	19	+#define AGG_SCHEME_1 2
	20	+
	21	+/* Topology related enums */
	22	+#define MSM_BUS_FAB_DEFAULT 0
	23	+#define MSM_BUS_FAB_APPSS 0
	24	+#define MSM_BUS_FAB_SYSTEM 1024
	25	+#define MSM_BUS_FAB_MMSS 2048
	26	+#define MSM_BUS_FAB_SYSTEM_FPB 3072
	27	+#define MSM_BUS_FAB_CPSS_FPB 4096
	28	+
	29	+#define MSM_BUS_FAB_BIMC 0
	30	+#define MSM_BUS_FAB_SYS_NOC 1024
	31	+#define MSM_BUS_FAB_MMSS_NOC 2048
	32	+#define MSM_BUS_FAB_OCMEM_NOC 3072
	33	+#define MSM_BUS_FAB_PERIPH_NOC 4096
	34	+#define MSM_BUS_FAB_CONFIG_NOC 5120
	35	+#define MSM_BUS_FAB_OCMEM_VNOC 6144
	36	+#define MSM_BUS_FAB_MMSS_AHB 2049
	37	+#define MSM_BUS_FAB_A0_NOC 6145
	38	+#define MSM_BUS_FAB_A1_NOC 6146
	39	+#define MSM_BUS_FAB_A2_NOC 6147
	40	+#define MSM_BUS_FAB_GNOC 6148
	41	+#define MSM_BUS_FAB_CR_VIRT 6149
	42	+
	43	+#define MSM_BUS_MASTER_FIRST 1
	44	+#define MSM_BUS_MASTER_AMPSS_M0 1
	45	+#define MSM_BUS_MASTER_AMPSS_M1 2
	46	+#define MSM_BUS_APPSS_MASTER_FAB_MMSS 3
	47	+#define MSM_BUS_APPSS_MASTER_FAB_SYSTEM 4
	48	+#define MSM_BUS_SYSTEM_MASTER_FAB_APPSS 5
	49	+#define MSM_BUS_MASTER_SPS 6
	50	+#define MSM_BUS_MASTER_ADM_PORT0 7
	51	+#define MSM_BUS_MASTER_ADM_PORT1 8
	52	+#define MSM_BUS_SYSTEM_MASTER_ADM1_PORT0 9
	53	+#define MSM_BUS_MASTER_ADM1_PORT1 10
	54	+#define MSM_BUS_MASTER_LPASS_PROC 11
	55	+#define MSM_BUS_MASTER_MSS_PROCI 12
	56	+#define MSM_BUS_MASTER_MSS_PROCD 13
	57	+#define MSM_BUS_MASTER_MSS_MDM_PORT0 14
	58	+#define MSM_BUS_MASTER_LPASS 15
	59	+#define MSM_BUS_SYSTEM_MASTER_CPSS_FPB 16
	60	+#define MSM_BUS_SYSTEM_MASTER_SYSTEM_FPB 17
	61	+#define MSM_BUS_SYSTEM_MASTER_MMSS_FPB 18
	62	+#define MSM_BUS_MASTER_ADM1_CI 19
	63	+#define MSM_BUS_MASTER_ADM0_CI 20
	64	+#define MSM_BUS_MASTER_MSS_MDM_PORT1 21
	65	+#define MSM_BUS_MASTER_MDP_PORT0 22
	66	+#define MSM_BUS_MASTER_MDP_PORT1 23
	67	+#define MSM_BUS_MMSS_MASTER_ADM1_PORT0 24
	68	+#define MSM_BUS_MASTER_ROTATOR 25
	69	+#define MSM_BUS_MASTER_GRAPHICS_3D 26
	70	+#define MSM_BUS_MASTER_JPEG_DEC 27
	71	+#define MSM_BUS_MASTER_GRAPHICS_2D_CORE0 28
	72	+#define MSM_BUS_MASTER_VFE 29
	73	+#define MSM_BUS_MASTER_VFE0 MSM_BUS_MASTER_VFE
	74	+#define MSM_BUS_MASTER_VPE 30
	75	+#define MSM_BUS_MASTER_JPEG_ENC 31
	76	+#define MSM_BUS_MASTER_GRAPHICS_2D_CORE1 32
	77	+#define MSM_BUS_MMSS_MASTER_APPS_FAB 33
	78	+#define MSM_BUS_MASTER_HD_CODEC_PORT0 34
	79	+#define MSM_BUS_MASTER_HD_CODEC_PORT1 35
	80	+#define MSM_BUS_MASTER_SPDM 36
	81	+#define MSM_BUS_MASTER_RPM 37
	82	+#define MSM_BUS_MASTER_MSS 38
	83	+#define MSM_BUS_MASTER_RIVA 39
	84	+#define MSM_BUS_MASTER_SNOC_VMEM 40
	85	+#define MSM_BUS_MASTER_MSS_SW_PROC 41
	86	+#define MSM_BUS_MASTER_MSS_FW_PROC 42
	87	+#define MSM_BUS_MASTER_HMSS 43
	88	+#define MSM_BUS_MASTER_GSS_NAV 44
	89	+#define MSM_BUS_MASTER_PCIE 45
	90	+#define MSM_BUS_MASTER_SATA 46
	91	+#define MSM_BUS_MASTER_CRYPTO 47
	92	+#define MSM_BUS_MASTER_VIDEO_CAP 48
	93	+#define MSM_BUS_MASTER_GRAPHICS_3D_PORT1 49
	94	+#define MSM_BUS_MASTER_VIDEO_ENC 50
	95	+#define MSM_BUS_MASTER_VIDEO_DEC 51
	96	+#define MSM_BUS_MASTER_LPASS_AHB 52
	97	+#define MSM_BUS_MASTER_QDSS_BAM 53
	98	+#define MSM_BUS_MASTER_SNOC_CFG 54
	99	+#define MSM_BUS_MASTER_CRYPTO_CORE0 55
	100	+#define MSM_BUS_MASTER_CRYPTO_CORE1 56
	101	+#define MSM_BUS_MASTER_MSS_NAV 57
	102	+#define MSM_BUS_MASTER_OCMEM_DMA 58
	103	+#define MSM_BUS_MASTER_WCSS 59
	104	+#define MSM_BUS_MASTER_QDSS_ETR 60
	105	+#define MSM_BUS_MASTER_USB3 61
	106	+#define MSM_BUS_MASTER_JPEG 62
	107	+#define MSM_BUS_MASTER_VIDEO_P0 63
	108	+#define MSM_BUS_MASTER_VIDEO_P1 64
	109	+#define MSM_BUS_MASTER_MSS_PROC 65
	110	+#define MSM_BUS_MASTER_JPEG_OCMEM 66
	111	+#define MSM_BUS_MASTER_MDP_OCMEM 67
	112	+#define MSM_BUS_MASTER_VIDEO_P0_OCMEM 68
	113	+#define MSM_BUS_MASTER_VIDEO_P1_OCMEM 69
	114	+#define MSM_BUS_MASTER_VFE_OCMEM 70
	115	+#define MSM_BUS_MASTER_CNOC_ONOC_CFG 71
	116	+#define MSM_BUS_MASTER_RPM_INST 72
	117	+#define MSM_BUS_MASTER_RPM_DATA 73
	118	+#define MSM_BUS_MASTER_RPM_SYS 74
	119	+#define MSM_BUS_MASTER_DEHR 75
	120	+#define MSM_BUS_MASTER_QDSS_DAP 76
	121	+#define MSM_BUS_MASTER_TIC 77
	122	+#define MSM_BUS_MASTER_SDCC_1 78
	123	+#define MSM_BUS_MASTER_SDCC_3 79
	124	+#define MSM_BUS_MASTER_SDCC_4 80
	125	+#define MSM_BUS_MASTER_SDCC_2 81
	126	+#define MSM_BUS_MASTER_TSIF 82
	127	+#define MSM_BUS_MASTER_BAM_DMA 83
	128	+#define MSM_BUS_MASTER_BLSP_2 84
	129	+#define MSM_BUS_MASTER_USB_HSIC 85
	130	+#define MSM_BUS_MASTER_BLSP_1 86
	131	+#define MSM_BUS_MASTER_USB_HS 87
	132	+#define MSM_BUS_MASTER_PNOC_CFG 88
	133	+#define MSM_BUS_MASTER_V_OCMEM_GFX3D 89
	134	+#define MSM_BUS_MASTER_IPA 90
	135	+#define MSM_BUS_MASTER_QPIC 91
	136	+#define MSM_BUS_MASTER_MDPE 92
	137	+#define MSM_BUS_MASTER_USB_HS2 93
	138	+#define MSM_BUS_MASTER_VPU 94
	139	+#define MSM_BUS_MASTER_UFS 95
	140	+#define MSM_BUS_MASTER_BCAST 96
	141	+#define MSM_BUS_MASTER_CRYPTO_CORE2 97
	142	+#define MSM_BUS_MASTER_EMAC 98
	143	+#define MSM_BUS_MASTER_VPU_1 99
	144	+#define MSM_BUS_MASTER_PCIE_1 100
	145	+#define MSM_BUS_MASTER_USB3_1 101
	146	+#define MSM_BUS_MASTER_CNOC_MNOC_MMSS_CFG 102
	147	+#define MSM_BUS_MASTER_CNOC_MNOC_CFG 103
	148	+#define MSM_BUS_MASTER_TCU_0 104
	149	+#define MSM_BUS_MASTER_TCU_1 105
	150	+#define MSM_BUS_MASTER_CPP 106
	151	+#define MSM_BUS_MASTER_AUDIO 107
	152	+#define MSM_BUS_MASTER_PCIE_2 108
	153	+#define MSM_BUS_MASTER_VFE1 109
	154	+#define MSM_BUS_MASTER_XM_USB_HS1 110
	155	+#define MSM_BUS_MASTER_PCNOC_BIMC_1 111
	156	+#define MSM_BUS_MASTER_BIMC_PCNOC 112
	157	+#define MSM_BUS_MASTER_XI_USB_HSIC 113
	158	+#define MSM_BUS_MASTER_SGMII 114
	159	+#define MSM_BUS_SPMI_FETCHER 115
	160	+#define MSM_BUS_MASTER_GNOC_BIMC 116
	161	+#define MSM_BUS_MASTER_CRVIRT_A2NOC 117
	162	+#define MSM_BUS_MASTER_CNOC_A2NOC 118
	163	+#define MSM_BUS_MASTER_WLAN 119
	164	+#define MSM_BUS_MASTER_MSS_CE 120
	165	+#define MSM_BUS_MASTER_CDSP_PROC 121
	166	+#define MSM_BUS_MASTER_GNOC_SNOC 122
	167	+#define MSM_BUS_MASTER_PIMEM 123
	168	+#define MSM_BUS_MASTER_MASTER_LAST 124
	169	+
	170	+#define MSM_BUS_SYSTEM_FPB_MASTER_SYSTEM MSM_BUS_SYSTEM_MASTER_SYSTEM_FPB
	171	+#define MSM_BUS_CPSS_FPB_MASTER_SYSTEM MSM_BUS_SYSTEM_MASTER_CPSS_FPB
	172	+
	173	+#define MSM_BUS_SNOC_MM_INT_0 10000
	174	+#define MSM_BUS_SNOC_MM_INT_1 10001
	175	+#define MSM_BUS_SNOC_MM_INT_2 10002
	176	+#define MSM_BUS_SNOC_MM_INT_BIMC 10003
	177	+#define MSM_BUS_SNOC_INT_0 10004
	178	+#define MSM_BUS_SNOC_INT_1 10005
	179	+#define MSM_BUS_SNOC_INT_BIMC 10006
	180	+#define MSM_BUS_SNOC_BIMC_0_MAS 10007
	181	+#define MSM_BUS_SNOC_BIMC_1_MAS 10008
	182	+#define MSM_BUS_SNOC_QDSS_INT 10009
	183	+#define MSM_BUS_PNOC_SNOC_MAS 10010
	184	+#define MSM_BUS_PNOC_SNOC_SLV 10011
	185	+#define MSM_BUS_PNOC_INT_0 10012
	186	+#define MSM_BUS_PNOC_INT_1 10013
	187	+#define MSM_BUS_PNOC_M_0 10014
	188	+#define MSM_BUS_PNOC_M_1 10015
	189	+#define MSM_BUS_BIMC_SNOC_MAS 10016
	190	+#define MSM_BUS_BIMC_SNOC_SLV 10017
	191	+#define MSM_BUS_PNOC_SLV_0 10018
	192	+#define MSM_BUS_PNOC_SLV_1 10019
	193	+#define MSM_BUS_PNOC_SLV_2 10020
	194	+#define MSM_BUS_PNOC_SLV_3 10021
	195	+#define MSM_BUS_PNOC_SLV_4 10022
	196	+#define MSM_BUS_PNOC_SLV_8 10023
	197	+#define MSM_BUS_PNOC_SLV_9 10024
	198	+#define MSM_BUS_SNOC_BIMC_0_SLV 10025
	199	+#define MSM_BUS_SNOC_BIMC_1_SLV 10026
	200	+#define MSM_BUS_MNOC_BIMC_MAS 10027
	201	+#define MSM_BUS_MNOC_BIMC_SLV 10028
	202	+#define MSM_BUS_BIMC_MNOC_MAS 10029
	203	+#define MSM_BUS_BIMC_MNOC_SLV 10030
	204	+#define MSM_BUS_SNOC_BIMC_MAS 10031
	205	+#define MSM_BUS_SNOC_BIMC_SLV 10032
	206	+#define MSM_BUS_CNOC_SNOC_MAS 10033
	207	+#define MSM_BUS_CNOC_SNOC_SLV 10034
	208	+#define MSM_BUS_SNOC_CNOC_MAS 10035
	209	+#define MSM_BUS_SNOC_CNOC_SLV 10036
	210	+#define MSM_BUS_OVNOC_SNOC_MAS 10037
	211	+#define MSM_BUS_OVNOC_SNOC_SLV 10038
	212	+#define MSM_BUS_SNOC_OVNOC_MAS 10039
	213	+#define MSM_BUS_SNOC_OVNOC_SLV 10040
	214	+#define MSM_BUS_SNOC_PNOC_MAS 10041
	215	+#define MSM_BUS_SNOC_PNOC_SLV 10042
	216	+#define MSM_BUS_BIMC_INT_APPS_EBI 10043
	217	+#define MSM_BUS_BIMC_INT_APPS_SNOC 10044
	218	+#define MSM_BUS_SNOC_BIMC_2_MAS 10045
	219	+#define MSM_BUS_SNOC_BIMC_2_SLV 10046
	220	+#define MSM_BUS_PNOC_SLV_5 10047
	221	+#define MSM_BUS_PNOC_SLV_7 10048
	222	+#define MSM_BUS_PNOC_INT_2 10049
	223	+#define MSM_BUS_PNOC_INT_3 10050
	224	+#define MSM_BUS_PNOC_INT_4 10051
	225	+#define MSM_BUS_PNOC_INT_5 10052
	226	+#define MSM_BUS_PNOC_INT_6 10053
	227	+#define MSM_BUS_PNOC_INT_7 10054
	228	+#define MSM_BUS_BIMC_SNOC_1_MAS 10055
	229	+#define MSM_BUS_BIMC_SNOC_1_SLV 10056
	230	+#define MSM_BUS_PNOC_A1NOC_MAS 10057
	231	+#define MSM_BUS_PNOC_A1NOC_SLV 10058
	232	+#define MSM_BUS_CNOC_A1NOC_MAS 10059
	233	+#define MSM_BUS_A0NOC_SNOC_MAS 10060
	234	+#define MSM_BUS_A0NOC_SNOC_SLV 10061
	235	+#define MSM_BUS_A1NOC_SNOC_SLV 10062
	236	+#define MSM_BUS_A1NOC_SNOC_MAS 10063
	237	+#define MSM_BUS_A2NOC_SNOC_MAS 10064
	238	+#define MSM_BUS_A2NOC_SNOC_SLV 10065
	239	+#define MSM_BUS_SNOC_INT_2 10066
	240	+#define MSM_BUS_A0NOC_QDSS_INT 10067
	241	+#define MSM_BUS_INT_LAST 10068
	242	+
	243	+#define MSM_BUS_INT_TEST_ID 20000
	244	+#define MSM_BUS_INT_TEST_LAST 20050
	245	+
	246	+#define MSM_BUS_SLAVE_FIRST 512
	247	+#define MSM_BUS_SLAVE_EBI_CH0 512
	248	+#define MSM_BUS_SLAVE_EBI_CH1 513
	249	+#define MSM_BUS_SLAVE_AMPSS_L2 514
	250	+#define MSM_BUS_APPSS_SLAVE_FAB_MMSS 515
	251	+#define MSM_BUS_APPSS_SLAVE_FAB_SYSTEM 516
	252	+#define MSM_BUS_SYSTEM_SLAVE_FAB_APPS 517
	253	+#define MSM_BUS_SLAVE_SPS 518
	254	+#define MSM_BUS_SLAVE_SYSTEM_IMEM 519
	255	+#define MSM_BUS_SLAVE_AMPSS 520
	256	+#define MSM_BUS_SLAVE_MSS 521
	257	+#define MSM_BUS_SLAVE_LPASS 522
	258	+#define MSM_BUS_SYSTEM_SLAVE_CPSS_FPB 523
	259	+#define MSM_BUS_SYSTEM_SLAVE_SYSTEM_FPB 524
	260	+#define MSM_BUS_SYSTEM_SLAVE_MMSS_FPB 525
	261	+#define MSM_BUS_SLAVE_CORESIGHT 526
	262	+#define MSM_BUS_SLAVE_RIVA 527
	263	+#define MSM_BUS_SLAVE_SMI 528
	264	+#define MSM_BUS_MMSS_SLAVE_FAB_APPS 529
	265	+#define MSM_BUS_MMSS_SLAVE_FAB_APPS_1 530
	266	+#define MSM_BUS_SLAVE_MM_IMEM 531
	267	+#define MSM_BUS_SLAVE_CRYPTO 532
	268	+#define MSM_BUS_SLAVE_SPDM 533
	269	+#define MSM_BUS_SLAVE_RPM 534
	270	+#define MSM_BUS_SLAVE_RPM_MSG_RAM 535
	271	+#define MSM_BUS_SLAVE_MPM 536
	272	+#define MSM_BUS_SLAVE_PMIC1_SSBI1_A 537
	273	+#define MSM_BUS_SLAVE_PMIC1_SSBI1_B 538
	274	+#define MSM_BUS_SLAVE_PMIC1_SSBI1_C 539
	275	+#define MSM_BUS_SLAVE_PMIC2_SSBI2_A 540
	276	+#define MSM_BUS_SLAVE_PMIC2_SSBI2_B 541
	277	+#define MSM_BUS_SLAVE_GSBI1_UART 542
	278	+#define MSM_BUS_SLAVE_GSBI2_UART 543
	279	+#define MSM_BUS_SLAVE_GSBI3_UART 544
	280	+#define MSM_BUS_SLAVE_GSBI4_UART 545
	281	+#define MSM_BUS_SLAVE_GSBI5_UART 546
	282	+#define MSM_BUS_SLAVE_GSBI6_UART 547
	283	+#define MSM_BUS_SLAVE_GSBI7_UART 548
	284	+#define MSM_BUS_SLAVE_GSBI8_UART 549
	285	+#define MSM_BUS_SLAVE_GSBI9_UART 550
	286	+#define MSM_BUS_SLAVE_GSBI10_UART 551
	287	+#define MSM_BUS_SLAVE_GSBI11_UART 552
	288	+#define MSM_BUS_SLAVE_GSBI12_UART 553
	289	+#define MSM_BUS_SLAVE_GSBI1_QUP 554
	290	+#define MSM_BUS_SLAVE_GSBI2_QUP 555
	291	+#define MSM_BUS_SLAVE_GSBI3_QUP 556
	292	+#define MSM_BUS_SLAVE_GSBI4_QUP 557
	293	+#define MSM_BUS_SLAVE_GSBI5_QUP 558
	294	+#define MSM_BUS_SLAVE_GSBI6_QUP 559
	295	+#define MSM_BUS_SLAVE_GSBI7_QUP 560
	296	+#define MSM_BUS_SLAVE_GSBI8_QUP 561
	297	+#define MSM_BUS_SLAVE_GSBI9_QUP 562
	298	+#define MSM_BUS_SLAVE_GSBI10_QUP 563
	299	+#define MSM_BUS_SLAVE_GSBI11_QUP 564
	300	+#define MSM_BUS_SLAVE_GSBI12_QUP 565
	301	+#define MSM_BUS_SLAVE_EBI2_NAND 566
	302	+#define MSM_BUS_SLAVE_EBI2_CS0 567
	303	+#define MSM_BUS_SLAVE_EBI2_CS1 568
	304	+#define MSM_BUS_SLAVE_EBI2_CS2 569
	305	+#define MSM_BUS_SLAVE_EBI2_CS3 570
	306	+#define MSM_BUS_SLAVE_EBI2_CS4 571
	307	+#define MSM_BUS_SLAVE_EBI2_CS5 572
	308	+#define MSM_BUS_SLAVE_USB_FS1 573
	309	+#define MSM_BUS_SLAVE_USB_FS2 574
	310	+#define MSM_BUS_SLAVE_TSIF 575
	311	+#define MSM_BUS_SLAVE_MSM_TSSC 576
	312	+#define MSM_BUS_SLAVE_MSM_PDM 577
	313	+#define MSM_BUS_SLAVE_MSM_DIMEM 578
	314	+#define MSM_BUS_SLAVE_MSM_TCSR 579
	315	+#define MSM_BUS_SLAVE_MSM_PRNG 580
	316	+#define MSM_BUS_SLAVE_GSS 581
	317	+#define MSM_BUS_SLAVE_SATA 582
	318	+#define MSM_BUS_SLAVE_USB3 583
	319	+#define MSM_BUS_SLAVE_WCSS 584
	320	+#define MSM_BUS_SLAVE_OCIMEM 585
	321	+#define MSM_BUS_SLAVE_SNOC_OCMEM 586
	322	+#define MSM_BUS_SLAVE_SERVICE_SNOC 587
	323	+#define MSM_BUS_SLAVE_QDSS_STM 588
	324	+#define MSM_BUS_SLAVE_CAMERA_CFG 589
	325	+#define MSM_BUS_SLAVE_DISPLAY_CFG 590
	326	+#define MSM_BUS_SLAVE_OCMEM_CFG 591
	327	+#define MSM_BUS_SLAVE_CPR_CFG 592
	328	+#define MSM_BUS_SLAVE_CPR_XPU_CFG 593
	329	+#define MSM_BUS_SLAVE_MISC_CFG 594
	330	+#define MSM_BUS_SLAVE_MISC_XPU_CFG 595
	331	+#define MSM_BUS_SLAVE_VENUS_CFG 596
	332	+#define MSM_BUS_SLAVE_MISC_VENUS_CFG 597
	333	+#define MSM_BUS_SLAVE_GRAPHICS_3D_CFG 598
	334	+#define MSM_BUS_SLAVE_MMSS_CLK_CFG 599
	335	+#define MSM_BUS_SLAVE_MMSS_CLK_XPU_CFG 600
	336	+#define MSM_BUS_SLAVE_MNOC_MPU_CFG 601
	337	+#define MSM_BUS_SLAVE_ONOC_MPU_CFG 602
	338	+#define MSM_BUS_SLAVE_SERVICE_MNOC 603
	339	+#define MSM_BUS_SLAVE_OCMEM 604
	340	+#define MSM_BUS_SLAVE_SERVICE_ONOC 605
	341	+#define MSM_BUS_SLAVE_SDCC_1 606
	342	+#define MSM_BUS_SLAVE_SDCC_3 607
	343	+#define MSM_BUS_SLAVE_SDCC_2 608
	344	+#define MSM_BUS_SLAVE_SDCC_4 609
	345	+#define MSM_BUS_SLAVE_BAM_DMA 610
	346	+#define MSM_BUS_SLAVE_BLSP_2 611
	347	+#define MSM_BUS_SLAVE_USB_HSIC 612
	348	+#define MSM_BUS_SLAVE_BLSP_1 613
	349	+#define MSM_BUS_SLAVE_USB_HS 614
	350	+#define MSM_BUS_SLAVE_PDM 615
	351	+#define MSM_BUS_SLAVE_PERIPH_APU_CFG 616
	352	+#define MSM_BUS_SLAVE_PNOC_MPU_CFG 617
	353	+#define MSM_BUS_SLAVE_PRNG 618
	354	+#define MSM_BUS_SLAVE_SERVICE_PNOC 619
	355	+#define MSM_BUS_SLAVE_CLK_CTL 620
	356	+#define MSM_BUS_SLAVE_CNOC_MSS 621
	357	+#define MSM_BUS_SLAVE_SECURITY 622
	358	+#define MSM_BUS_SLAVE_TCSR 623
	359	+#define MSM_BUS_SLAVE_TLMM 624
	360	+#define MSM_BUS_SLAVE_CRYPTO_0_CFG 625
	361	+#define MSM_BUS_SLAVE_CRYPTO_1_CFG 626
	362	+#define MSM_BUS_SLAVE_IMEM_CFG 627
	363	+#define MSM_BUS_SLAVE_MESSAGE_RAM 628
	364	+#define MSM_BUS_SLAVE_BIMC_CFG 629
	365	+#define MSM_BUS_SLAVE_BOOT_ROM 630
	366	+#define MSM_BUS_SLAVE_CNOC_MNOC_MMSS_CFG 631
	367	+#define MSM_BUS_SLAVE_PMIC_ARB 632
	368	+#define MSM_BUS_SLAVE_SPDM_WRAPPER 633
	369	+#define MSM_BUS_SLAVE_DEHR_CFG 634
	370	+#define MSM_BUS_SLAVE_QDSS_CFG 635
	371	+#define MSM_BUS_SLAVE_RBCPR_CFG 636
	372	+#define MSM_BUS_SLAVE_RBCPR_QDSS_APU_CFG 637
	373	+#define MSM_BUS_SLAVE_SNOC_MPU_CFG 638
	374	+#define MSM_BUS_SLAVE_CNOC_ONOC_CFG 639
	375	+#define MSM_BUS_SLAVE_CNOC_MNOC_CFG 640
	376	+#define MSM_BUS_SLAVE_PNOC_CFG 641
	377	+#define MSM_BUS_SLAVE_SNOC_CFG 642
	378	+#define MSM_BUS_SLAVE_EBI1_DLL_CFG 643
	379	+#define MSM_BUS_SLAVE_PHY_APU_CFG 644
	380	+#define MSM_BUS_SLAVE_EBI1_PHY_CFG 645
	381	+#define MSM_BUS_SLAVE_SERVICE_CNOC 646
	382	+#define MSM_BUS_SLAVE_IPS_CFG 647
	383	+#define MSM_BUS_SLAVE_QPIC 648
	384	+#define MSM_BUS_SLAVE_DSI_CFG 649
	385	+#define MSM_BUS_SLAVE_UFS_CFG 650
	386	+#define MSM_BUS_SLAVE_RBCPR_CX_CFG 651
	387	+#define MSM_BUS_SLAVE_RBCPR_MX_CFG 652
	388	+#define MSM_BUS_SLAVE_PCIE_CFG 653
	389	+#define MSM_BUS_SLAVE_USB_PHYS_CFG 654
	390	+#define MSM_BUS_SLAVE_VIDEO_CAP_CFG 655
	391	+#define MSM_BUS_SLAVE_AVSYNC_CFG 656
	392	+#define MSM_BUS_SLAVE_CRYPTO_2_CFG 657
	393	+#define MSM_BUS_SLAVE_VPU_CFG 658
	394	+#define MSM_BUS_SLAVE_BCAST_CFG 659
	395	+#define MSM_BUS_SLAVE_KLM_CFG 660
	396	+#define MSM_BUS_SLAVE_GENI_IR_CFG 661
	397	+#define MSM_BUS_SLAVE_OCMEM_GFX 662
	398	+#define MSM_BUS_SLAVE_CATS_128 663
	399	+#define MSM_BUS_SLAVE_OCMEM_64 664
	400	+#define MSM_BUS_SLAVE_PCIE_0 665
	401	+#define MSM_BUS_SLAVE_PCIE_1 666
	402	+#define MSM_BUS_SLAVE_PCIE_0_CFG 667
	403	+#define MSM_BUS_SLAVE_PCIE_1_CFG 668
	404	+#define MSM_BUS_SLAVE_SRVC_MNOC 669
	405	+#define MSM_BUS_SLAVE_USB_HS2 670
	406	+#define MSM_BUS_SLAVE_AUDIO 671
	407	+#define MSM_BUS_SLAVE_TCU 672
	408	+#define MSM_BUS_SLAVE_APPSS 673
	409	+#define MSM_BUS_SLAVE_PCIE_PARF 674
	410	+#define MSM_BUS_SLAVE_USB3_PHY_CFG 675
	411	+#define MSM_BUS_SLAVE_IPA_CFG 676
	412	+#define MSM_BUS_SLAVE_A0NOC_SNOC 677
	413	+#define MSM_BUS_SLAVE_A1NOC_SNOC 678
	414	+#define MSM_BUS_SLAVE_A2NOC_SNOC 679
	415	+#define MSM_BUS_SLAVE_HMSS_L3 680
	416	+#define MSM_BUS_SLAVE_PIMEM_CFG 681
	417	+#define MSM_BUS_SLAVE_DCC_CFG 682
	418	+#define MSM_BUS_SLAVE_QDSS_RBCPR_APU_CFG 683
	419	+#define MSM_BUS_SLAVE_PCIE_2_CFG 684
	420	+#define MSM_BUS_SLAVE_PCIE20_AHB2PHY 685
	421	+#define MSM_BUS_SLAVE_A0NOC_CFG 686
	422	+#define MSM_BUS_SLAVE_A1NOC_CFG 687
	423	+#define MSM_BUS_SLAVE_A2NOC_CFG 688
	424	+#define MSM_BUS_SLAVE_A1NOC_MPU_CFG 689
	425	+#define MSM_BUS_SLAVE_A2NOC_MPU_CFG 690
	426	+#define MSM_BUS_SLAVE_A0NOC_SMMU_CFG 691
	427	+#define MSM_BUS_SLAVE_A1NOC_SMMU_CFG 692
	428	+#define MSM_BUS_SLAVE_A2NOC_SMMU_CFG 693
	429	+#define MSM_BUS_SLAVE_LPASS_SMMU_CFG 694
	430	+#define MSM_BUS_SLAVE_MMAGIC_CFG 695
	431	+#define MSM_BUS_SLAVE_VENUS_THROTTLE_CFG 696
	432	+#define MSM_BUS_SLAVE_SSC_CFG 697
	433	+#define MSM_BUS_SLAVE_DSA_CFG 698
	434	+#define MSM_BUS_SLAVE_DSA_MPU_CFG 699
	435	+#define MSM_BUS_SLAVE_DISPLAY_THROTTLE_CFG 700
	436	+#define MSM_BUS_SLAVE_SMMU_CPP_CFG 701
	437	+#define MSM_BUS_SLAVE_SMMU_JPEG_CFG 702
	438	+#define MSM_BUS_SLAVE_SMMU_MDP_CFG 703
	439	+#define MSM_BUS_SLAVE_SMMU_ROTATOR_CFG 704
	440	+#define MSM_BUS_SLAVE_SMMU_VENUS_CFG 705
	441	+#define MSM_BUS_SLAVE_SMMU_VFE_CFG 706
	442	+#define MSM_BUS_SLAVE_A0NOC_MPU_CFG 707
	443	+#define MSM_BUS_SLAVE_VMEM_CFG 708
	444	+#define MSM_BUS_SLAVE_CAMERA_THROTTLE_CFG 709
	445	+#define MSM_BUS_SLAVE_VMEM 710
	446	+#define MSM_BUS_SLAVE_AHB2PHY 711
	447	+#define MSM_BUS_SLAVE_PIMEM 712
	448	+#define MSM_BUS_SLAVE_SNOC_VMEM 713
	449	+#define MSM_BUS_SLAVE_PCIE_2 714
	450	+#define MSM_BUS_SLAVE_RBCPR_MX 715
	451	+#define MSM_BUS_SLAVE_RBCPR_CX 716
	452	+#define MSM_BUS_SLAVE_BIMC_PCNOC 717
	453	+#define MSM_BUS_SLAVE_PCNOC_BIMC_1 718
	454	+#define MSM_BUS_SLAVE_SGMII 719
	455	+#define MSM_BUS_SLAVE_SPMI_FETCHER 720
	456	+#define MSM_BUS_PNOC_SLV_6 721
	457	+#define MSM_BUS_SLAVE_MMSS_SMMU_CFG 722
	458	+#define MSM_BUS_SLAVE_WLAN 723
	459	+#define MSM_BUS_SLAVE_CRVIRT_A2NOC 724
	460	+#define MSM_BUS_SLAVE_CNOC_A2NOC 725
	461	+#define MSM_BUS_SLAVE_GLM 726
	462	+#define MSM_BUS_SLAVE_GNOC_BIMC 727
	463	+#define MSM_BUS_SLAVE_GNOC_SNOC 728
	464	+#define MSM_BUS_SLAVE_QM_CFG 729
	465	+#define MSM_BUS_SLAVE_TLMM_EAST 730
	466	+#define MSM_BUS_SLAVE_TLMM_NORTH 731
	467	+#define MSM_BUS_SLAVE_TLMM_WEST 732
	468	+#define MSM_BUS_SLAVE_SKL 733
	469	+#define MSM_BUS_SLAVE_LPASS_TCM 734
	470	+#define MSM_BUS_SLAVE_TLMM_SOUTH 735
	471	+#define MSM_BUS_SLAVE_TLMM_CENTER 736
	472	+#define MSM_BUS_MSS_NAV_CE_MPU_CFG 737
	473	+#define MSM_BUS_SLAVE_A2NOC_THROTTLE_CFG 738
	474	+#define MSM_BUS_SLAVE_CDSP 739
	475	+#define MSM_BUS_SLAVE_CDSP_SMMU_CFG 740
	476	+#define MSM_BUS_SLAVE_LPASS_MPU_CFG 741
	477	+#define MSM_BUS_SLAVE_CSI_PHY_CFG 742
	478	+#define MSM_BUS_SLAVE_LAST 743
	479	+
	480	+#define MSM_BUS_SYSTEM_FPB_SLAVE_SYSTEM MSM_BUS_SYSTEM_SLAVE_SYSTEM_FPB
	481	+#define MSM_BUS_CPSS_FPB_SLAVE_SYSTEM MSM_BUS_SYSTEM_SLAVE_CPSS_FPB
	482	+
	483	+/*
	484	+ * ID's used in RPM messages
	485	+ */
	486	+#define ICBID_MASTER_APPSS_PROC 0
	487	+#define ICBID_MASTER_MSS_PROC 1
	488	+#define ICBID_MASTER_MNOC_BIMC 2
	489	+#define ICBID_MASTER_SNOC_BIMC 3
	490	+#define ICBID_MASTER_SNOC_BIMC_0 ICBID_MASTER_SNOC_BIMC
	491	+#define ICBID_MASTER_CNOC_MNOC_MMSS_CFG 4
	492	+#define ICBID_MASTER_CNOC_MNOC_CFG 5
	493	+#define ICBID_MASTER_GFX3D 6
	494	+#define ICBID_MASTER_JPEG 7
	495	+#define ICBID_MASTER_MDP 8
	496	+#define ICBID_MASTER_MDP0 ICBID_MASTER_MDP
	497	+#define ICBID_MASTER_MDPS ICBID_MASTER_MDP
	498	+#define ICBID_MASTER_VIDEO 9
	499	+#define ICBID_MASTER_VIDEO_P0 ICBID_MASTER_VIDEO
	500	+#define ICBID_MASTER_VIDEO_P1 10
	501	+#define ICBID_MASTER_VFE 11
	502	+#define ICBID_MASTER_VFE0 ICBID_MASTER_VFE
	503	+#define ICBID_MASTER_CNOC_ONOC_CFG 12
	504	+#define ICBID_MASTER_JPEG_OCMEM 13
	505	+#define ICBID_MASTER_MDP_OCMEM 14
	506	+#define ICBID_MASTER_VIDEO_P0_OCMEM 15
	507	+#define ICBID_MASTER_VIDEO_P1_OCMEM 16
	508	+#define ICBID_MASTER_VFE_OCMEM 17
	509	+#define ICBID_MASTER_LPASS_AHB 18
	510	+#define ICBID_MASTER_QDSS_BAM 19
	511	+#define ICBID_MASTER_SNOC_CFG 20
	512	+#define ICBID_MASTER_BIMC_SNOC 21
	513	+#define ICBID_MASTER_BIMC_SNOC_0 ICBID_MASTER_BIMC_SNOC
	514	+#define ICBID_MASTER_CNOC_SNOC 22
	515	+#define ICBID_MASTER_CRYPTO 23
	516	+#define ICBID_MASTER_CRYPTO_CORE0 ICBID_MASTER_CRYPTO
	517	+#define ICBID_MASTER_CRYPTO_CORE1 24
	518	+#define ICBID_MASTER_LPASS_PROC 25
	519	+#define ICBID_MASTER_MSS 26
	520	+#define ICBID_MASTER_MSS_NAV 27
	521	+#define ICBID_MASTER_OCMEM_DMA 28
	522	+#define ICBID_MASTER_PNOC_SNOC 29
	523	+#define ICBID_MASTER_WCSS 30
	524	+#define ICBID_MASTER_QDSS_ETR 31
	525	+#define ICBID_MASTER_USB3 32
	526	+#define ICBID_MASTER_USB3_0 ICBID_MASTER_USB3
	527	+#define ICBID_MASTER_SDCC_1 33
	528	+#define ICBID_MASTER_SDCC_3 34
	529	+#define ICBID_MASTER_SDCC_2 35
	530	+#define ICBID_MASTER_SDCC_4 36
	531	+#define ICBID_MASTER_TSIF 37
	532	+#define ICBID_MASTER_BAM_DMA 38
	533	+#define ICBID_MASTER_BLSP_2 39
	534	+#define ICBID_MASTER_USB_HSIC 40
	535	+#define ICBID_MASTER_BLSP_1 41
	536	+#define ICBID_MASTER_USB_HS 42
	537	+#define ICBID_MASTER_USB_HS1 ICBID_MASTER_USB_HS
	538	+#define ICBID_MASTER_PNOC_CFG 43
	539	+#define ICBID_MASTER_SNOC_PNOC 44
	540	+#define ICBID_MASTER_RPM_INST 45
	541	+#define ICBID_MASTER_RPM_DATA 46
	542	+#define ICBID_MASTER_RPM_SYS 47
	543	+#define ICBID_MASTER_DEHR 48
	544	+#define ICBID_MASTER_QDSS_DAP 49
	545	+#define ICBID_MASTER_SPDM 50
	546	+#define ICBID_MASTER_TIC 51
	547	+#define ICBID_MASTER_SNOC_CNOC 52
	548	+#define ICBID_MASTER_GFX3D_OCMEM 53
	549	+#define ICBID_MASTER_GFX3D_GMEM ICBID_MASTER_GFX3D_OCMEM
	550	+#define ICBID_MASTER_OVIRT_SNOC 54
	551	+#define ICBID_MASTER_SNOC_OVIRT 55
	552	+#define ICBID_MASTER_SNOC_GVIRT ICBID_MASTER_SNOC_OVIRT
	553	+#define ICBID_MASTER_ONOC_OVIRT 56
	554	+#define ICBID_MASTER_USB_HS2 57
	555	+#define ICBID_MASTER_QPIC 58
	556	+#define ICBID_MASTER_IPA 59
	557	+#define ICBID_MASTER_DSI 60
	558	+#define ICBID_MASTER_MDP1 61
	559	+#define ICBID_MASTER_MDPE ICBID_MASTER_MDP1
	560	+#define ICBID_MASTER_VPU_PROC 62
	561	+#define ICBID_MASTER_VPU 63
	562	+#define ICBID_MASTER_VPU0 ICBID_MASTER_VPU
	563	+#define ICBID_MASTER_CRYPTO_CORE2 64
	564	+#define ICBID_MASTER_PCIE_0 65
	565	+#define ICBID_MASTER_PCIE_1 66
	566	+#define ICBID_MASTER_SATA 67
	567	+#define ICBID_MASTER_UFS 68
	568	+#define ICBID_MASTER_USB3_1 69
	569	+#define ICBID_MASTER_VIDEO_OCMEM 70
	570	+#define ICBID_MASTER_VPU1 71
	571	+#define ICBID_MASTER_VCAP 72
	572	+#define ICBID_MASTER_EMAC 73
	573	+#define ICBID_MASTER_BCAST 74
	574	+#define ICBID_MASTER_MMSS_PROC 75
	575	+#define ICBID_MASTER_SNOC_BIMC_1 76
	576	+#define ICBID_MASTER_SNOC_PCNOC 77
	577	+#define ICBID_MASTER_AUDIO 78
	578	+#define ICBID_MASTER_MM_INT_0 79
	579	+#define ICBID_MASTER_MM_INT_1 80
	580	+#define ICBID_MASTER_MM_INT_2 81
	581	+#define ICBID_MASTER_MM_INT_BIMC 82
	582	+#define ICBID_MASTER_MSS_INT 83
	583	+#define ICBID_MASTER_PCNOC_CFG 84
	584	+#define ICBID_MASTER_PCNOC_INT_0 85
	585	+#define ICBID_MASTER_PCNOC_INT_1 86
	586	+#define ICBID_MASTER_PCNOC_M_0 87
	587	+#define ICBID_MASTER_PCNOC_M_1 88
	588	+#define ICBID_MASTER_PCNOC_S_0 89
	589	+#define ICBID_MASTER_PCNOC_S_1 90
	590	+#define ICBID_MASTER_PCNOC_S_2 91
	591	+#define ICBID_MASTER_PCNOC_S_3 92
	592	+#define ICBID_MASTER_PCNOC_S_4 93
	593	+#define ICBID_MASTER_PCNOC_S_6 94
	594	+#define ICBID_MASTER_PCNOC_S_7 95
	595	+#define ICBID_MASTER_PCNOC_S_8 96
	596	+#define ICBID_MASTER_PCNOC_S_9 97
	597	+#define ICBID_MASTER_QDSS_INT 98
	598	+#define ICBID_MASTER_SNOC_INT_0 99
	599	+#define ICBID_MASTER_SNOC_INT_1 100
	600	+#define ICBID_MASTER_SNOC_INT_BIMC 101
	601	+#define ICBID_MASTER_TCU_0 102
	602	+#define ICBID_MASTER_TCU_1 103
	603	+#define ICBID_MASTER_BIMC_INT_0 104
	604	+#define ICBID_MASTER_BIMC_INT_1 105
	605	+#define ICBID_MASTER_CAMERA 106
	606	+#define ICBID_MASTER_RICA 107
	607	+#define ICBID_MASTER_SNOC_BIMC_2 108
	608	+#define ICBID_MASTER_BIMC_SNOC_1 109
	609	+#define ICBID_MASTER_A0NOC_SNOC 110
	610	+#define ICBID_MASTER_A1NOC_SNOC 111
	611	+#define ICBID_MASTER_A2NOC_SNOC 112
	612	+#define ICBID_MASTER_PIMEM 113
	613	+#define ICBID_MASTER_SNOC_VMEM 114
	614	+#define ICBID_MASTER_CPP 115
	615	+#define ICBID_MASTER_CNOC_A1NOC 116
	616	+#define ICBID_MASTER_PNOC_A1NOC 117
	617	+#define ICBID_MASTER_HMSS 118
	618	+#define ICBID_MASTER_PCIE_2 119
	619	+#define ICBID_MASTER_ROTATOR 120
	620	+#define ICBID_MASTER_VENUS_VMEM 121
	621	+#define ICBID_MASTER_DCC 122
	622	+#define ICBID_MASTER_MCDMA 123
	623	+#define ICBID_MASTER_PCNOC_INT_2 124
	624	+#define ICBID_MASTER_PCNOC_INT_3 125
	625	+#define ICBID_MASTER_PCNOC_INT_4 126
	626	+#define ICBID_MASTER_PCNOC_INT_5 127
	627	+#define ICBID_MASTER_PCNOC_INT_6 128
	628	+#define ICBID_MASTER_PCNOC_S_5 129
	629	+#define ICBID_MASTER_SENSORS_AHB 130
	630	+#define ICBID_MASTER_SENSORS_PROC 131
	631	+#define ICBID_MASTER_QSPI 132
	632	+#define ICBID_MASTER_VFE1 133
	633	+#define ICBID_MASTER_SNOC_INT_2 134
	634	+#define ICBID_MASTER_SMMNOC_BIMC 135
	635	+#define ICBID_MASTER_CRVIRT_A1NOC 136
	636	+#define ICBID_MASTER_XM_USB_HS1 137
	637	+#define ICBID_MASTER_XI_USB_HS1 138
	638	+#define ICBID_MASTER_PCNOC_BIMC_1 139
	639	+#define ICBID_MASTER_BIMC_PCNOC 140
	640	+#define ICBID_MASTER_XI_HSIC 141
	641	+#define ICBID_MASTER_SGMII 142
	642	+#define ICBID_MASTER_SPMI_FETCHER 143
	643	+#define ICBID_MASTER_GNOC_BIMC 144
	644	+#define ICBID_MASTER_CRVIRT_A2NOC 145
	645	+#define ICBID_MASTER_CNOC_A2NOC 146
	646	+#define ICBID_MASTER_WLAN 147
	647	+#define ICBID_MASTER_MSS_CE 148
	648	+#define ICBID_MASTER_CDSP_PROC 149
	649	+#define ICBID_MASTER_GNOC_SNOC 150
	650	+
	651	+#define ICBID_SLAVE_EBI1 0
	652	+#define ICBID_SLAVE_APPSS_L2 1
	653	+#define ICBID_SLAVE_BIMC_SNOC 2
	654	+#define ICBID_SLAVE_BIMC_SNOC_0 ICBID_SLAVE_BIMC_SNOC
	655	+#define ICBID_SLAVE_CAMERA_CFG 3
	656	+#define ICBID_SLAVE_DISPLAY_CFG 4
	657	+#define ICBID_SLAVE_OCMEM_CFG 5
	658	+#define ICBID_SLAVE_CPR_CFG 6
	659	+#define ICBID_SLAVE_CPR_XPU_CFG 7
	660	+#define ICBID_SLAVE_MISC_CFG 8
	661	+#define ICBID_SLAVE_MISC_XPU_CFG 9
	662	+#define ICBID_SLAVE_VENUS_CFG 10
	663	+#define ICBID_SLAVE_GFX3D_CFG 11
	664	+#define ICBID_SLAVE_MMSS_CLK_CFG 12
	665	+#define ICBID_SLAVE_MMSS_CLK_XPU_CFG 13
	666	+#define ICBID_SLAVE_MNOC_MPU_CFG 14
	667	+#define ICBID_SLAVE_ONOC_MPU_CFG 15
	668	+#define ICBID_SLAVE_MNOC_BIMC 16
	669	+#define ICBID_SLAVE_SERVICE_MNOC 17
	670	+#define ICBID_SLAVE_OCMEM 18
	671	+#define ICBID_SLAVE_GMEM ICBID_SLAVE_OCMEM
	672	+#define ICBID_SLAVE_SERVICE_ONOC 19
	673	+#define ICBID_SLAVE_APPSS 20
	674	+#define ICBID_SLAVE_LPASS 21
	675	+#define ICBID_SLAVE_USB3 22
	676	+#define ICBID_SLAVE_USB3_0 ICBID_SLAVE_USB3
	677	+#define ICBID_SLAVE_WCSS 23
	678	+#define ICBID_SLAVE_SNOC_BIMC 24
	679	+#define ICBID_SLAVE_SNOC_BIMC_0 ICBID_SLAVE_SNOC_BIMC
	680	+#define ICBID_SLAVE_SNOC_CNOC 25
	681	+#define ICBID_SLAVE_IMEM 26
	682	+#define ICBID_SLAVE_OCIMEM ICBID_SLAVE_IMEM
	683	+#define ICBID_SLAVE_SNOC_OVIRT 27
	684	+#define ICBID_SLAVE_SNOC_GVIRT ICBID_SLAVE_SNOC_OVIRT
	685	+#define ICBID_SLAVE_SNOC_PNOC 28
	686	+#define ICBID_SLAVE_SNOC_PCNOC ICBID_SLAVE_SNOC_PNOC
	687	+#define ICBID_SLAVE_SERVICE_SNOC 29
	688	+#define ICBID_SLAVE_QDSS_STM 30
	689	+#define ICBID_SLAVE_SDCC_1 31
	690	+#define ICBID_SLAVE_SDCC_3 32
	691	+#define ICBID_SLAVE_SDCC_2 33
	692	+#define ICBID_SLAVE_SDCC_4 34
	693	+#define ICBID_SLAVE_TSIF 35
	694	+#define ICBID_SLAVE_BAM_DMA 36
	695	+#define ICBID_SLAVE_BLSP_2 37
	696	+#define ICBID_SLAVE_USB_HSIC 38
	697	+#define ICBID_SLAVE_BLSP_1 39
	698	+#define ICBID_SLAVE_USB_HS 40
	699	+#define ICBID_SLAVE_USB_HS1 ICBID_SLAVE_USB_HS
	700	+#define ICBID_SLAVE_PDM 41
	701	+#define ICBID_SLAVE_PERIPH_APU_CFG 42
	702	+#define ICBID_SLAVE_PNOC_MPU_CFG 43
	703	+#define ICBID_SLAVE_PRNG 44
	704	+#define ICBID_SLAVE_PNOC_SNOC 45
	705	+#define ICBID_SLAVE_PCNOC_SNOC ICBID_SLAVE_PNOC_SNOC
	706	+#define ICBID_SLAVE_SERVICE_PNOC 46
	707	+#define ICBID_SLAVE_CLK_CTL 47
	708	+#define ICBID_SLAVE_CNOC_MSS 48
	709	+#define ICBID_SLAVE_PCNOC_MSS ICBID_SLAVE_CNOC_MSS
	710	+#define ICBID_SLAVE_SECURITY 49
	711	+#define ICBID_SLAVE_TCSR 50
	712	+#define ICBID_SLAVE_TLMM 51
	713	+#define ICBID_SLAVE_CRYPTO_0_CFG 52
	714	+#define ICBID_SLAVE_CRYPTO_1_CFG 53
	715	+#define ICBID_SLAVE_IMEM_CFG 54
	716	+#define ICBID_SLAVE_MESSAGE_RAM 55
	717	+#define ICBID_SLAVE_BIMC_CFG 56
	718	+#define ICBID_SLAVE_BOOT_ROM 57
	719	+#define ICBID_SLAVE_CNOC_MNOC_MMSS_CFG 58
	720	+#define ICBID_SLAVE_PMIC_ARB 59
	721	+#define ICBID_SLAVE_SPDM_WRAPPER 60
	722	+#define ICBID_SLAVE_DEHR_CFG 61
	723	+#define ICBID_SLAVE_MPM 62
	724	+#define ICBID_SLAVE_QDSS_CFG 63
	725	+#define ICBID_SLAVE_RBCPR_CFG 64
	726	+#define ICBID_SLAVE_RBCPR_CX_CFG ICBID_SLAVE_RBCPR_CFG
	727	+#define ICBID_SLAVE_RBCPR_QDSS_APU_CFG 65
	728	+#define ICBID_SLAVE_CNOC_MNOC_CFG 66
	729	+#define ICBID_SLAVE_SNOC_MPU_CFG 67
	730	+#define ICBID_SLAVE_CNOC_ONOC_CFG 68
	731	+#define ICBID_SLAVE_PNOC_CFG 69
	732	+#define ICBID_SLAVE_SNOC_CFG 70
	733	+#define ICBID_SLAVE_EBI1_DLL_CFG 71
	734	+#define ICBID_SLAVE_PHY_APU_CFG 72
	735	+#define ICBID_SLAVE_EBI1_PHY_CFG 73
	736	+#define ICBID_SLAVE_RPM 74
	737	+#define ICBID_SLAVE_CNOC_SNOC 75
	738	+#define ICBID_SLAVE_SERVICE_CNOC 76
	739	+#define ICBID_SLAVE_OVIRT_SNOC 77
	740	+#define ICBID_SLAVE_OVIRT_OCMEM 78
	741	+#define ICBID_SLAVE_USB_HS2 79
	742	+#define ICBID_SLAVE_QPIC 80
	743	+#define ICBID_SLAVE_IPS_CFG 81
	744	+#define ICBID_SLAVE_DSI_CFG 82
	745	+#define ICBID_SLAVE_USB3_1 83
	746	+#define ICBID_SLAVE_PCIE_0 84
	747	+#define ICBID_SLAVE_PCIE_1 85
	748	+#define ICBID_SLAVE_PSS_SMMU_CFG 86
	749	+#define ICBID_SLAVE_CRYPTO_2_CFG 87
	750	+#define ICBID_SLAVE_PCIE_0_CFG 88
	751	+#define ICBID_SLAVE_PCIE_1_CFG 89
	752	+#define ICBID_SLAVE_SATA_CFG 90
	753	+#define ICBID_SLAVE_SPSS_GENI_IR 91
	754	+#define ICBID_SLAVE_UFS_CFG 92
	755	+#define ICBID_SLAVE_AVSYNC_CFG 93
	756	+#define ICBID_SLAVE_VPU_CFG 94
	757	+#define ICBID_SLAVE_USB_PHY_CFG 95
	758	+#define ICBID_SLAVE_RBCPR_MX_CFG 96
	759	+#define ICBID_SLAVE_PCIE_PARF 97
	760	+#define ICBID_SLAVE_VCAP_CFG 98
	761	+#define ICBID_SLAVE_EMAC_CFG 99
	762	+#define ICBID_SLAVE_BCAST_CFG 100
	763	+#define ICBID_SLAVE_KLM_CFG 101
	764	+#define ICBID_SLAVE_DISPLAY_PWM 102
	765	+#define ICBID_SLAVE_GENI 103
	766	+#define ICBID_SLAVE_SNOC_BIMC_1 104
	767	+#define ICBID_SLAVE_AUDIO 105
	768	+#define ICBID_SLAVE_CATS_0 106
	769	+#define ICBID_SLAVE_CATS_1 107
	770	+#define ICBID_SLAVE_MM_INT_0 108
	771	+#define ICBID_SLAVE_MM_INT_1 109
	772	+#define ICBID_SLAVE_MM_INT_2 110
	773	+#define ICBID_SLAVE_MM_INT_BIMC 111
	774	+#define ICBID_SLAVE_MMU_MODEM_XPU_CFG 112
	775	+#define ICBID_SLAVE_MSS_INT 113
	776	+#define ICBID_SLAVE_PCNOC_INT_0 114
	777	+#define ICBID_SLAVE_PCNOC_INT_1 115
	778	+#define ICBID_SLAVE_PCNOC_M_0 116
	779	+#define ICBID_SLAVE_PCNOC_M_1 117
	780	+#define ICBID_SLAVE_PCNOC_S_0 118
	781	+#define ICBID_SLAVE_PCNOC_S_1 119
	782	+#define ICBID_SLAVE_PCNOC_S_2 120
	783	+#define ICBID_SLAVE_PCNOC_S_3 121
	784	+#define ICBID_SLAVE_PCNOC_S_4 122
	785	+#define ICBID_SLAVE_PCNOC_S_6 123
	786	+#define ICBID_SLAVE_PCNOC_S_7 124
	787	+#define ICBID_SLAVE_PCNOC_S_8 125
	788	+#define ICBID_SLAVE_PCNOC_S_9 126
	789	+#define ICBID_SLAVE_PRNG_XPU_CFG 127
	790	+#define ICBID_SLAVE_QDSS_INT 128
	791	+#define ICBID_SLAVE_RPM_XPU_CFG 129
	792	+#define ICBID_SLAVE_SNOC_INT_0 130
	793	+#define ICBID_SLAVE_SNOC_INT_1 131
	794	+#define ICBID_SLAVE_SNOC_INT_BIMC 132
	795	+#define ICBID_SLAVE_TCU 133
	796	+#define ICBID_SLAVE_BIMC_INT_0 134
	797	+#define ICBID_SLAVE_BIMC_INT_1 135
	798	+#define ICBID_SLAVE_RICA_CFG 136
	799	+#define ICBID_SLAVE_SNOC_BIMC_2 137
	800	+#define ICBID_SLAVE_BIMC_SNOC_1 138
	801	+#define ICBID_SLAVE_PNOC_A1NOC 139
	802	+#define ICBID_SLAVE_SNOC_VMEM 140
	803	+#define ICBID_SLAVE_A0NOC_SNOC 141
	804	+#define ICBID_SLAVE_A1NOC_SNOC 142
	805	+#define ICBID_SLAVE_A2NOC_SNOC 143
	806	+#define ICBID_SLAVE_A0NOC_CFG 144
	807	+#define ICBID_SLAVE_A0NOC_MPU_CFG 145
	808	+#define ICBID_SLAVE_A0NOC_SMMU_CFG 146
	809	+#define ICBID_SLAVE_A1NOC_CFG 147
	810	+#define ICBID_SLAVE_A1NOC_MPU_CFG 148
	811	+#define ICBID_SLAVE_A1NOC_SMMU_CFG 149
	812	+#define ICBID_SLAVE_A2NOC_CFG 150
	813	+#define ICBID_SLAVE_A2NOC_MPU_CFG 151
	814	+#define ICBID_SLAVE_A2NOC_SMMU_CFG 152
	815	+#define ICBID_SLAVE_AHB2PHY 153
	816	+#define ICBID_SLAVE_CAMERA_THROTTLE_CFG 154
	817	+#define ICBID_SLAVE_DCC_CFG 155
	818	+#define ICBID_SLAVE_DISPLAY_THROTTLE_CFG 156
	819	+#define ICBID_SLAVE_DSA_CFG 157
	820	+#define ICBID_SLAVE_DSA_MPU_CFG 158
	821	+#define ICBID_SLAVE_SSC_MPU_CFG 159
	822	+#define ICBID_SLAVE_HMSS_L3 160
	823	+#define ICBID_SLAVE_LPASS_SMMU_CFG 161
	824	+#define ICBID_SLAVE_MMAGIC_CFG 162
	825	+#define ICBID_SLAVE_PCIE20_AHB2PHY 163
	826	+#define ICBID_SLAVE_PCIE_2 164
	827	+#define ICBID_SLAVE_PCIE_2_CFG 165
	828	+#define ICBID_SLAVE_PIMEM 166
	829	+#define ICBID_SLAVE_PIMEM_CFG 167
	830	+#define ICBID_SLAVE_QDSS_RBCPR_APU_CFG 168
	831	+#define ICBID_SLAVE_RBCPR_CX 169
	832	+#define ICBID_SLAVE_RBCPR_MX 170
	833	+#define ICBID_SLAVE_SMMU_CPP_CFG 171
	834	+#define ICBID_SLAVE_SMMU_JPEG_CFG 172
	835	+#define ICBID_SLAVE_SMMU_MDP_CFG 173
	836	+#define ICBID_SLAVE_SMMU_ROTATOR_CFG 174
	837	+#define ICBID_SLAVE_SMMU_VENUS_CFG 175
	838	+#define ICBID_SLAVE_SMMU_VFE_CFG 176
	839	+#define ICBID_SLAVE_SSC_CFG 177
	840	+#define ICBID_SLAVE_VENUS_THROTTLE_CFG 178
	841	+#define ICBID_SLAVE_VMEM 179
	842	+#define ICBID_SLAVE_VMEM_CFG 180
	843	+#define ICBID_SLAVE_QDSS_MPU_CFG 181
	844	+#define ICBID_SLAVE_USB3_PHY_CFG 182
	845	+#define ICBID_SLAVE_IPA_CFG 183
	846	+#define ICBID_SLAVE_PCNOC_INT_2 184
	847	+#define ICBID_SLAVE_PCNOC_INT_3 185
	848	+#define ICBID_SLAVE_PCNOC_INT_4 186
	849	+#define ICBID_SLAVE_PCNOC_INT_5 187
	850	+#define ICBID_SLAVE_PCNOC_INT_6 188
	851	+#define ICBID_SLAVE_PCNOC_S_5 189
	852	+#define ICBID_SLAVE_QSPI 190
	853	+#define ICBID_SLAVE_A1NOC_MS_MPU_CFG 191
	854	+#define ICBID_SLAVE_A2NOC_MS_MPU_CFG 192
	855	+#define ICBID_SLAVE_MODEM_Q6_SMMU_CFG 193
	856	+#define ICBID_SLAVE_MSS_MPU_CFG 194
	857	+#define ICBID_SLAVE_MSS_PROC_MS_MPU_CFG 195
	858	+#define ICBID_SLAVE_SKL 196
	859	+#define ICBID_SLAVE_SNOC_INT_2 197
	860	+#define ICBID_SLAVE_SMMNOC_BIMC 198
	861	+#define ICBID_SLAVE_CRVIRT_A1NOC 199
	862	+#define ICBID_SLAVE_SGMII 200
	863	+#define ICBID_SLAVE_QHS4_APPS 201
	864	+#define ICBID_SLAVE_BIMC_PCNOC 202
	865	+#define ICBID_SLAVE_PCNOC_BIMC_1 203
	866	+#define ICBID_SLAVE_SPMI_FETCHER 204
	867	+#define ICBID_SLAVE_MMSS_SMMU_CFG 205
	868	+#define ICBID_SLAVE_WLAN 206
	869	+#define ICBID_SLAVE_CRVIRT_A2NOC 207
	870	+#define ICBID_SLAVE_CNOC_A2NOC 208
	871	+#define ICBID_SLAVE_GLM 209
	872	+#define ICBID_SLAVE_GNOC_BIMC 210
	873	+#define ICBID_SLAVE_GNOC_SNOC 211
	874	+#define ICBID_SLAVE_QM_CFG 212
	875	+#define ICBID_SLAVE_TLMM_EAST 213
	876	+#define ICBID_SLAVE_TLMM_NORTH 214
	877	+#define ICBID_SLAVE_TLMM_WEST 215
	878	+#define ICBID_SLAVE_LPASS_TCM 216
	879	+#define ICBID_SLAVE_TLMM_SOUTH 217
	880	+#define ICBID_SLAVE_TLMM_CENTER 218
	881	+#define ICBID_SLAVE_MSS_NAV_CE_MPU_CFG 219
	882	+#define ICBID_SLAVE_A2NOC_THROTTLE_CFG 220
	883	+#define ICBID_SLAVE_CDSP 221
	884	+#define ICBID_SLAVE_CDSP_SMMU_CFG 222
	885	+#define ICBID_SLAVE_LPASS_MPU_CFG 223
	886	+#define ICBID_SLAVE_CSI_PHY_CFG 224
	887	+#endif

include/uapi/drm/msm_drm.h+1−0

@@ -232,6 +232,7 @@ struct drm_msm_wait_fence { · 231 unmodified lines
232	232	__u32 fence; /* in */
233	233	__u32 pad;
234	234	struct drm_msm_timespec timeout; /* in */
	235	+ __u32 queueid; /* in, submitqueue id */
235	236	};
236	237
237	238	/* madvise provides a way to tell the kernel in case a buffers contents

drm/msm: Support multiple ringbuffers

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