lael-labs/linux

Documentation/devicetree/bindings/ipmi/aspeed,ast2400-ibt-bmc.txtrenamed from Documentation/devicetree/bindings/ipmi/aspeed,ast2400-bt-bmc.txt+2−2

@@ -6,7 +6,7 @@ perform in-band IPMI communication with their host. · 5 unmodified lines
6		6
7	Required properties:	7	Required properties:
8		8
9	- compatible : should be "aspeed,ast2400-bt-bmc"	9	- compatible : should be "aspeed,ast2400-ibt-bmc"
10	- reg: physical address and size of the registers	10	- reg: physical address and size of the registers
11		11
12	Optional properties:	12	Optional properties:
@@ -17,7 +17,7 @@ Optional properties: · 4 unmodified lines
17	Example:	17	Example:
18		18
19	ibt@1e789140 {	19	ibt@1e789140 {
20	compatible = "aspeed,ast2400-bt-bmc";	20	compatible = "aspeed,ast2400-ibt-bmc";
21	reg = <0x1e789140 0x18>;	21	reg = <0x1e789140 0x18>;
22	interrupts = <8>;	22	interrupts = <8>;
23	};	23	};

Documentation/devicetree/bindings/sound/omap-abe-twl6040.txt+1−1

@@ -12,7 +12,7 @@ Required properties: · 11 unmodified lines
12		12
13	Optional properties:	13	Optional properties:
14	- ti,dmic: phandle for the OMAP dmic node if the machine have it connected	14	- ti,dmic: phandle for the OMAP dmic node if the machine have it connected
15	- ti,jack_detection: Need to be present if the board capable to detect jack	15	- ti,jack-detection: Need to be present if the board capable to detect jack
16	insertion, removal.	16	insertion, removal.
17		17
18	Available audio endpoints for the audio-routing table:	18	Available audio endpoints for the audio-routing table:

Documentation/i2c/i2c-topology+2−2

@@ -326,7 +326,7 @@ Two parent-locked sibling muxes · 325 unmodified lines
326		326
327	This is a good topology.	327	This is a good topology.
328		328
329	.--------.	329	.--------.
330	.----------. .--\| dev D1 \|	330	.----------. .--\| dev D1 \|
331	\| parent- \|--' '--------'	331	\| parent- \|--' '--------'
332	.--\| locked \| .--------.	332	.--\| locked \| .--------.
@@ -350,7 +350,7 @@ Mux-locked and parent-locked sibling muxes · 17 unmodified lines
350		350
351	This is a good topology.	351	This is a good topology.
352		352
353	.--------.	353	.--------.
354	.----------. .--\| dev D1 \|	354	.----------. .--\| dev D1 \|
355	\| mux- \|--' '--------'	355	\| mux- \|--' '--------'
356	.--\| locked \| .--------.	356	.--\| locked \| .--------.

Documentation/virtual/kvm/api.txt+11−0

@@ -777,6 +777,17 @@ Gets the current timestamp of kvmclock as seen by the current guest. In · 776 unmodified lines
777	conjunction with KVM_SET_CLOCK, it is used to ensure monotonicity on scenarios	777	conjunction with KVM_SET_CLOCK, it is used to ensure monotonicity on scenarios
778	such as migration.	778	such as migration.
779		779
		780	When KVM_CAP_ADJUST_CLOCK is passed to KVM_CHECK_EXTENSION, it returns the
		781	set of bits that KVM can return in struct kvm_clock_data's flag member.
		782
		783	The only flag defined now is KVM_CLOCK_TSC_STABLE. If set, the returned
		784	value is the exact kvmclock value seen by all VCPUs at the instant
		785	when KVM_GET_CLOCK was called. If clear, the returned value is simply
		786	CLOCK_MONOTONIC plus a constant offset; the offset can be modified
		787	with KVM_SET_CLOCK. KVM will try to make all VCPUs follow this clock,
		788	but the exact value read by each VCPU could differ, because the host
		789	TSC is not stable.
		790
780	struct kvm_clock_data {	791	struct kvm_clock_data {
781	__u64 clock; /* kvmclock current value */	792	__u64 clock; /* kvmclock current value */
782	__u32 flags;	793	__u32 flags;

MAINTAINERS+1−0

@@ -7086,6 +7086,7 @@ F: drivers/scsi/53c700* · 7085 unmodified lines
7086	LED SUBSYSTEM	7086	LED SUBSYSTEM
7087	M: Richard Purdie <rpurdie@rpsys.net>	7087	M: Richard Purdie <rpurdie@rpsys.net>
7088	M: Jacek Anaszewski <j.anaszewski@samsung.com>	7088	M: Jacek Anaszewski <j.anaszewski@samsung.com>
		7089	M: Pavel Machek <pavel@ucw.cz>
7089	L: linux-leds@vger.kernel.org	7090	L: linux-leds@vger.kernel.org
7090	T: git git://git.kernel.org/pub/scm/linux/kernel/git/j.anaszewski/linux-leds.git	7091	T: git git://git.kernel.org/pub/scm/linux/kernel/git/j.anaszewski/linux-leds.git
7091	S: Maintained	7092	S: Maintained

Makefile+4−3

@@ -1,7 +1,7 @@
1	VERSION = 4	1	VERSION = 4
2	PATCHLEVEL = 9	2	PATCHLEVEL = 9
3	SUBLEVEL = 0	3	SUBLEVEL = 0
4	EXTRAVERSION = -rc5	4	EXTRAVERSION = -rc6
5	NAME = Psychotic Stoned Sheep	5	NAME = Psychotic Stoned Sheep
6		6
7	# DOCUMENTATION	7	# DOCUMENTATION
@@ -399,11 +399,12 @@ KBUILD_CFLAGS := -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs \ · 391 unmodified lines
399	-fno-strict-aliasing -fno-common \	399	-fno-strict-aliasing -fno-common \
400	-Werror-implicit-function-declaration \	400	-Werror-implicit-function-declaration \
401	-Wno-format-security \	401	-Wno-format-security \
402	-std=gnu89	402	-std=gnu89 $(call cc-option,-fno-PIE)
		403
403		404
404	KBUILD_AFLAGS_KERNEL :=	405	KBUILD_AFLAGS_KERNEL :=
405	KBUILD_CFLAGS_KERNEL :=	406	KBUILD_CFLAGS_KERNEL :=
406	KBUILD_AFLAGS := -D__ASSEMBLY__	407	KBUILD_AFLAGS := -D__ASSEMBLY__ $(call cc-option,-fno-PIE)
407	KBUILD_AFLAGS_MODULE := -DMODULE	408	KBUILD_AFLAGS_MODULE := -DMODULE
408	KBUILD_CFLAGS_MODULE := -DMODULE	409	KBUILD_CFLAGS_MODULE := -DMODULE
409	KBUILD_LDFLAGS_MODULE := -T $(srctree)/scripts/module-common.lds	410	KBUILD_LDFLAGS_MODULE := -T $(srctree)/scripts/module-common.lds

arch/arm/boot/dts/imx53-qsb.dts+7−7

@@ -64,8 +64,8 @@ · 63 unmodified lines
64	};	64	};
65		65
66	ldo3_reg: ldo3 {	66	ldo3_reg: ldo3 {
67	regulator-min-microvolt = <600000>;	67	regulator-min-microvolt = <1725000>;
68	regulator-max-microvolt = <1800000>;	68	regulator-max-microvolt = <3300000>;
69	regulator-always-on;	69	regulator-always-on;
70	};	70	};
71		71
@@ -76,8 +76,8 @@ · 4 unmodified lines
76	};	76	};
77		77
78	ldo5_reg: ldo5 {	78	ldo5_reg: ldo5 {
79	regulator-min-microvolt = <1725000>;	79	regulator-min-microvolt = <1200000>;
80	regulator-max-microvolt = <3300000>;	80	regulator-max-microvolt = <3600000>;
81	regulator-always-on;	81	regulator-always-on;
82	};	82	};
83		83
@@ -100,14 +100,14 @@ · 16 unmodified lines
100	};	100	};
101		101
102	ldo9_reg: ldo9 {	102	ldo9_reg: ldo9 {
103	regulator-min-microvolt = <1200000>;	103	regulator-min-microvolt = <1250000>;
104	regulator-max-microvolt = <3600000>;	104	regulator-max-microvolt = <3600000>;
105	regulator-always-on;	105	regulator-always-on;
106	};	106	};
107		107
108	ldo10_reg: ldo10 {	108	ldo10_reg: ldo10 {
109	regulator-min-microvolt = <1250000>;	109	regulator-min-microvolt = <1200000>;
110	regulator-max-microvolt = <3650000>;	110	regulator-max-microvolt = <3600000>;
111	regulator-always-on;	111	regulator-always-on;
112	};	112	};
113	};	113	};

arch/arm/boot/dts/logicpd-som-lv.dtsi+5−0

 		};
 	};
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x80000000 0>;
+	};
 	wl12xx_vmmc: wl12xx_vmmc {
 		compatible = "regulator-fixed";
 		regulator-name = "vwl1271";

arch/arm/boot/dts/logicpd-torpedo-som.dtsi+2−2

@@ -13,9 +13,9 @@ · 12 unmodified lines
13	};	13	};
14	};	14	};
15		15
16	memory@0 {	16	memory@80000000 {
17	device_type = "memory";	17	device_type = "memory";
18	reg = <0 0>;	18	reg = <0x80000000 0>;
19	};	19	};
20		20
21	leds {	21	leds {

arch/arm/boot/dts/omap5-board-common.dtsi+4−3

 		compatible = "ti,abe-twl6040";
 		ti,model = "omap5-uevm";
+		ti,jack-detection;
 		ti,mclk-freq = <19200000>;
 		ti,mcpdm = <&mcpdm>;
 			ti,backup-battery-charge-high-current;
 		};
-		gpadc {
+		gpadc: gpadc {
 			compatible = "ti,palmas-gpadc";
 			interrupts = <18 0
 				      16 0
 				smps6_reg: smps6 {
 					/* VDD_DDR3 - over VDD_SMPS6 */
 					regulator-name = "smps6";
-					regulator-min-microvolt = <1200000>;
+					regulator-min-microvolt = <1350000>;
-					regulator-max-microvolt = <1200000>;
+					regulator-max-microvolt = <1350000>;
 					regulator-always-on;
 					regulator-boot-on;
 				};

arch/arm/boot/dts/stih410-b2260.dts+1−1

@@ -74,7 +74,7 @@ · 73 unmodified lines
74	/* Low speed expansion connector */	74	/* Low speed expansion connector */
75	spi0: spi@9844000 {	75	spi0: spi@9844000 {
76	label = "LS-SPI0";	76	label = "LS-SPI0";
77	cs-gpio = <&pio30 3 0>;	77	cs-gpios = <&pio30 3 0>;
78	status = "okay";	78	status = "okay";
79	};	79	};
80		80

arch/arm/boot/dts/sun8i-a23-a33.dtsi+4−0

 			uart1_pins_a: uart1@0 {
 				allwinner,pins = "PG6", "PG7";
 				allwinner,function = "uart1";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 			};
 			uart1_pins_cts_rts_a: uart1-cts-rts@0 {
 				allwinner,pins = "PG8", "PG9";
 				allwinner,function = "uart1";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 			};
 			mmc0_pins_a: mmc0@0 {

arch/arm/kernel/traps.c+20−0

@@ -74,6 +74,26 @@ void dump_backtrace_entry(unsigned long where, unsigned long from, unsigned long · 73 unmodified lines
74	dump_mem("", "Exception stack", frame + 4, frame + 4 + sizeof(struct pt_regs));	74	dump_mem("", "Exception stack", frame + 4, frame + 4 + sizeof(struct pt_regs));
75	}	75	}
76		76
		77	void dump_backtrace_stm(u32 *stack, u32 instruction)
		78	{
		79	char str[80], *p;
		80	unsigned int x;
		81	int reg;
		82
		83	for (reg = 10, x = 0, p = str; reg >= 0; reg--) {
		84	if (instruction & BIT(reg)) {
		85	p += sprintf(p, " r%d:%08x", reg, *stack--);
		86	if (++x == 6) {
		87	x = 0;
		88	p = str;
		89	printk("%s\n", str);
		90	}
		91	}
		92	}
		93	if (p != str)
		94	printk("%s\n", str);
		95	}
		96
77	#ifndef CONFIG_ARM_UNWIND	97	#ifndef CONFIG_ARM_UNWIND
78	/*	98	/*
79	* Stack pointers should always be within the kernels view of	99	* Stack pointers should always be within the kernels view of

arch/arm/kernel/vmlinux-xip.lds.S+5−0

  * Written by Martin Mares <mj@atrey.karlin.mff.cuni.cz>
  */
+/* No __ro_after_init data in the .rodata section - which will always be ro */
+#define RO_AFTER_INIT_DATA
 #include <asm-generic/vmlinux.lds.h>
 #include <asm/cache.h>
 #include <asm/thread_info.h>
 		. = ALIGN(PAGE_SIZE);
 		__init_end = .;
+		*(.data..ro_after_init)
 		NOSAVE_DATA
 		CACHELINE_ALIGNED_DATA(L1_CACHE_BYTES)
 		READ_MOSTLY_DATA(L1_CACHE_BYTES)

arch/arm/lib/backtrace.S+3−34

@@ -10,6 +10,7 @@ · 9 unmodified lines
10	* 27/03/03 Ian Molton Clean up CONFIG_CPU	10	* 27/03/03 Ian Molton Clean up CONFIG_CPU
11	*	11	*
12	*/	12	*/
		13	#include <linux/kern_levels.h>
13	#include <linux/linkage.h>	14	#include <linux/linkage.h>
14	#include <asm/assembler.h>	15	#include <asm/assembler.h>
15	.text	16	.text
@@ -83,13 +84,13 @@ for_each_frame: tst frame, mask @ Check for address exceptions · 67 unmodified lines
83	teq r3, r1, lsr #11	84	teq r3, r1, lsr #11
84	ldreq r0, [frame, #-8] @ get sp	85	ldreq r0, [frame, #-8] @ get sp
85	subeq r0, r0, #4 @ point at the last arg	86	subeq r0, r0, #4 @ point at the last arg
86	bleq .Ldumpstm @ dump saved registers	87	bleq dump_backtrace_stm @ dump saved registers
87		88
88	1004: ldr r1, [sv_pc, #0] @ if stmfd sp!, {..., fp, ip, lr, pc}	89	1004: ldr r1, [sv_pc, #0] @ if stmfd sp!, {..., fp, ip, lr, pc}
89	ldr r3, .Ldsi @ instruction exists,	90	ldr r3, .Ldsi @ instruction exists,
90	teq r3, r1, lsr #11	91	teq r3, r1, lsr #11
91	subeq r0, frame, #16	92	subeq r0, frame, #16
92	bleq .Ldumpstm @ dump saved registers	93	bleq dump_backtrace_stm @ dump saved registers
93		94
94	teq sv_fp, #0 @ zero saved fp means	95	teq sv_fp, #0 @ zero saved fp means
95	beq no_frame @ no further frames	96	beq no_frame @ no further frames
@@ -112,38 +113,6 @@ ENDPROC(c_backtrace) · 16 unmodified lines
112	.long 1004b, 1006b	113	.long 1004b, 1006b
113	.popsection	114	.popsection
114		115
115	#define instr r4
116	#define reg r5
117	#define stack r6
118
119	.Ldumpstm: stmfd sp!, {instr, reg, stack, r7, lr}
120	mov stack, r0
121	mov instr, r1
122	mov reg, #10
123	mov r7, #0
124	1: mov r3, #1
125	ARM( tst instr, r3, lsl reg )
126	THUMB( lsl r3, reg )
127	THUMB( tst instr, r3 )
128	beq 2f
129	add r7, r7, #1
130	teq r7, #6
131	moveq r7, #0
132	adr r3, .Lcr
133	addne r3, r3, #1 @ skip newline
134	ldr r2, [stack], #-4
135	mov r1, reg
136	adr r0, .Lfp
137	bl printk
138	2: subs reg, reg, #1
139	bpl 1b
140	teq r7, #0
141	adrne r0, .Lcr
142	blne printk
143	ldmfd sp!, {instr, reg, stack, r7, pc}
144
145	.Lfp: .asciz " r%d:%08x%s"
146	.Lcr: .asciz "\n"
147	.Lbad: .asciz "Backtrace aborted due to bad frame pointer <%p>\n"	116	.Lbad: .asciz "Backtrace aborted due to bad frame pointer <%p>\n"
148	.align	117	.align
149	.Ldsi: .word 0xe92dd800 >> 11 @ stmfd sp!, {... fp, ip, lr, pc}	118	.Ldsi: .word 0xe92dd800 >> 11 @ stmfd sp!, {... fp, ip, lr, pc}

arch/arm/mach-omap2/Kconfig+1−0

@@ -71,6 +71,7 @@ config SOC_AM43XX · 70 unmodified lines
71	select HAVE_ARM_TWD	71	select HAVE_ARM_TWD
72	select ARM_ERRATA_754322	72	select ARM_ERRATA_754322
73	select ARM_ERRATA_775420	73	select ARM_ERRATA_775420
		74	select OMAP_INTERCONNECT
74		75
75	config SOC_DRA7XX	76	config SOC_DRA7XX
76	bool "TI DRA7XX"	77	bool "TI DRA7XX"

arch/arm/mach-omap2/id.c+11−5

@@ -205,11 +205,15 @@ void __init omap2xxx_check_revision(void) · 204 unmodified lines
205		205
206	#define OMAP3_SHOW_FEATURE(feat) \	206	#define OMAP3_SHOW_FEATURE(feat) \
207	if (omap3_has_ ##feat()) \	207	if (omap3_has_ ##feat()) \
208	printk(#feat" ");	208	n += scnprintf(buf + n, sizeof(buf) - n, #feat " ");
209		209
210	static void __init omap3_cpuinfo(void)	210	static void __init omap3_cpuinfo(void)
211	{	211	{
212	const char *cpu_name;	212	const char *cpu_name;
		213	char buf[64];
		214	int n = 0;
		215
		216	memset(buf, 0, sizeof(buf));
213		217
214	/*	218	/*
215	* OMAP3430 and OMAP3530 are assumed to be same.	219	* OMAP3430 and OMAP3530 are assumed to be same.
@@ -241,10 +245,10 @@ static void __init omap3_cpuinfo(void) · 25 unmodified lines
241	cpu_name = "OMAP3503";	245	cpu_name = "OMAP3503";
242	}	246	}
243		247
244	sprintf(soc_name, "%s", cpu_name);	248	scnprintf(soc_name, sizeof(soc_name), "%s", cpu_name);
245		249
246	/* Print verbose information */	250	/* Print verbose information */
247	pr_info("%s %s (", soc_name, soc_rev);	251	n += scnprintf(buf, sizeof(buf) - n, "%s %s (", soc_name, soc_rev);
248		252
249	OMAP3_SHOW_FEATURE(l2cache);	253	OMAP3_SHOW_FEATURE(l2cache);
250	OMAP3_SHOW_FEATURE(iva);	254	OMAP3_SHOW_FEATURE(iva);
@@ -252,8 +256,10 @@ static void __init omap3_cpuinfo(void) · 1 unmodified line
252	OMAP3_SHOW_FEATURE(neon);	256	OMAP3_SHOW_FEATURE(neon);
253	OMAP3_SHOW_FEATURE(isp);	257	OMAP3_SHOW_FEATURE(isp);
254	OMAP3_SHOW_FEATURE(192mhz_clk);	258	OMAP3_SHOW_FEATURE(192mhz_clk);
255		259	if (*(buf + n - 1) == ' ')
256	printk(")\n");	260	n--;
		261	n += scnprintf(buf + n, sizeof(buf) - n, ")\n");
		262	pr_info("%s", buf);
257	}	263	}
258		264
259	#define OMAP3_CHECK_FEATURE(status,feat) \	265	#define OMAP3_CHECK_FEATURE(status,feat) \

arch/arm/mach-omap2/prm3xxx.c+3−0

 	if (has_uart4) {
 		en_uart4_mask = OMAP3630_EN_UART4_MASK;
 		grpsel_uart4_mask = OMAP3630_GRPSEL_UART4_MASK;
+	} else {
+		en_uart4_mask = 0;
+		grpsel_uart4_mask = 0;
 	}
 	/* Enable wakeups in PER */

arch/arm/mach-omap2/voltage.c+6−0

 		return -ENODATA;
 	}
+	if (!voltdm->volt_data) {
+		pr_err("%s: No voltage data defined for vdd_%s\n",
+			__func__, voltdm->name);
+		return -ENODATA;
+	}
 	/* Adjust voltage to the exact voltage from the OPP table */
 	for (i = 0; voltdm->volt_data[i].volt_nominal != 0; i++) {
 		if (voltdm->volt_data[i].volt_nominal >= target_volt) {

arch/arm/mm/dma-mapping.c+1−1

@@ -1167,7 +1167,7 @@ static int __init dma_debug_do_init(void) · 1166 unmodified lines
1167	dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);	1167	dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
1168	return 0;	1168	return 0;
1169	}	1169	}
1170	fs_initcall(dma_debug_do_init);	1170	core_initcall(dma_debug_do_init);
1171		1171
1172	#ifdef CONFIG_ARM_DMA_USE_IOMMU	1172	#ifdef CONFIG_ARM_DMA_USE_IOMMU
1173		1173

arch/arm/mm/proc-v7m.S+1−1

@@ -96,7 +96,7 @@ ENTRY(cpu_cm7_proc_fin) · 95 unmodified lines
96	ret lr	96	ret lr
97	ENDPROC(cpu_cm7_proc_fin)	97	ENDPROC(cpu_cm7_proc_fin)
98		98
99	.section ".text.init", #alloc, #execinstr	99	.section ".init.text", #alloc, #execinstr
100		100
101	__v7m_cm7_setup:	101	__v7m_cm7_setup:
102	mov r8, #(V7M_SCB_CCR_DC \| V7M_SCB_CCR_IC\| V7M_SCB_CCR_BP)	102	mov r8, #(V7M_SCB_CCR_DC \| V7M_SCB_CCR_IC\| V7M_SCB_CCR_BP)

arch/arm64/boot/dts/marvell/armada-37xx.dtsi+2−2

@@ -105,7 +105,7 @@ · 104 unmodified lines
105	status = "disabled";	105	status = "disabled";
106	};	106	};
107		107
108	nb_perih_clk: nb-periph-clk@13000{	108	nb_periph_clk: nb-periph-clk@13000 {
109	compatible = "marvell,armada-3700-periph-clock-nb";	109	compatible = "marvell,armada-3700-periph-clock-nb";
110	reg = <0x13000 0x100>;	110	reg = <0x13000 0x100>;
111	clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,	111	clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
@@ -113,7 +113,7 @@ · 1 unmodified line
113	#clock-cells = <1>;	113	#clock-cells = <1>;
114	};	114	};
115		115
116	sb_perih_clk: sb-periph-clk@18000{	116	sb_periph_clk: sb-periph-clk@18000 {
117	compatible = "marvell,armada-3700-periph-clock-sb";	117	compatible = "marvell,armada-3700-periph-clock-sb";
118	reg = <0x18000 0x100>;	118	reg = <0x18000 0x100>;
119	clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,	119	clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,

arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi+3−3

@@ -130,8 +130,8 @@ · 129 unmodified lines
130	reg = <0x700600 0x50>;	130	reg = <0x700600 0x50>;
131	#address-cells = <0x1>;	131	#address-cells = <0x1>;
132	#size-cells = <0x0>;	132	#size-cells = <0x0>;
133	cell-index = <1>;	133	cell-index = <3>;
134	clocks = <&cps_syscon0 0 3>;	134	clocks = <&cps_syscon0 1 21>;
135	status = "disabled";	135	status = "disabled";
136	};	136	};
137		137
@@ -140,7 +140,7 @@ · 2 unmodified lines
140	reg = <0x700680 0x50>;	140	reg = <0x700680 0x50>;
141	#address-cells = <1>;	141	#address-cells = <1>;
142	#size-cells = <0>;	142	#size-cells = <0>;
143	cell-index = <2>;	143	cell-index = <4>;
144	clocks = <&cps_syscon0 1 21>;	144	clocks = <&cps_syscon0 1 21>;
145	status = "disabled";	145	status = "disabled";
146	};	146	};

arch/arm64/include/asm/perf_event.h+9−1

@@ -46,7 +46,15 @@ · 45 unmodified lines
46	#define ARMV8_PMU_EVTYPE_MASK 0xc800ffff /* Mask for writable bits */	46	#define ARMV8_PMU_EVTYPE_MASK 0xc800ffff /* Mask for writable bits */
47	#define ARMV8_PMU_EVTYPE_EVENT 0xffff /* Mask for EVENT bits */	47	#define ARMV8_PMU_EVTYPE_EVENT 0xffff /* Mask for EVENT bits */
48		48
49	#define ARMV8_PMU_EVTYPE_EVENT_SW_INCR 0 /* Software increment event */	49	/*
		50	* PMUv3 event types: required events
		51	*/
		52	#define ARMV8_PMUV3_PERFCTR_SW_INCR 0x00
		53	#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL 0x03
		54	#define ARMV8_PMUV3_PERFCTR_L1D_CACHE 0x04
		55	#define ARMV8_PMUV3_PERFCTR_BR_MIS_PRED 0x10
		56	#define ARMV8_PMUV3_PERFCTR_CPU_CYCLES 0x11
		57	#define ARMV8_PMUV3_PERFCTR_BR_PRED 0x12
50		58
51	/*	59	/*
52	* Event filters for PMUv3	60	* Event filters for PMUv3

arch/arm64/kernel/perf_event.c+1−9

 /*
  * ARMv8 PMUv3 Performance Events handling code.
- * Common event types.
+ * Common event types (some are defined in asm/perf_event.h).
  */
-/* Required events. */
-#define ARMV8_PMUV3_PERFCTR_SW_INCR				0x00
-#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL			0x03
-#define ARMV8_PMUV3_PERFCTR_L1D_CACHE				0x04
-#define ARMV8_PMUV3_PERFCTR_BR_MIS_PRED				0x10
-#define ARMV8_PMUV3_PERFCTR_CPU_CYCLES				0x11
-#define ARMV8_PMUV3_PERFCTR_BR_PRED				0x12
 /* At least one of the following is required. */
 #define ARMV8_PMUV3_PERFCTR_INST_RETIRED			0x08
 #define ARMV8_PMUV3_PERFCTR_INST_SPEC				0x1B

arch/arm64/kvm/sys_regs.c+8−2

 			idx = ARMV8_PMU_CYCLE_IDX;
 		} else {
-			BUG();
+			return false;
 		}
+	} else if (r->CRn == 0 && r->CRm == 9) {
+		/* PMCCNTR */
+		if (pmu_access_event_counter_el0_disabled(vcpu))
+			return false;
+		idx = ARMV8_PMU_CYCLE_IDX;
 	} else if (r->CRn == 14 && (r->CRm & 12) == 8) {
 		/* PMEVCNTRn_EL0 */
 		if (pmu_access_event_counter_el0_disabled(vcpu))
 		idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
 	} else {
-		BUG();
+		return false;
 	}
 	if (!pmu_counter_idx_valid(vcpu, idx))

arch/powerpc/include/asm/exception-64s.h+12−3

  */
 #define LOAD_HANDLER(reg, label)					\
 	ld	reg,PACAKBASE(r13);	/* get high part of &label */	\
-	ori	reg,reg,(FIXED_SYMBOL_ABS_ADDR(label))@l;
+	ori	reg,reg,FIXED_SYMBOL_ABS_ADDR(label);
 #define __LOAD_HANDLER(reg, label)					\
 	ld	reg,PACAKBASE(r13);					\
 	std	ra,offset(r13);						\
 END_FTR_SECTION_NESTED(ftr,ftr,943)
-#define EXCEPTION_PROLOG_0(area)					\
+#define EXCEPTION_PROLOG_0_PACA(area)					\
-	GET_PACA(r13);							\
 	std	r9,area+EX_R9(r13);	/* save r9 */			\
 	OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR);			\
 	HMT_MEDIUM;							\
 	std	r10,area+EX_R10(r13);	/* save r10 - r12 */		\
 	OPT_GET_SPR(r10, SPRN_CFAR, CPU_FTR_CFAR)
+#define EXCEPTION_PROLOG_0(area)					\
+	GET_PACA(r13);							\
+	EXCEPTION_PROLOG_0_PACA(area)
 #define __EXCEPTION_PROLOG_1(area, extra, vec)				\
 	OPT_SAVE_REG_TO_PACA(area+EX_PPR, r9, CPU_FTR_HAS_PPR);		\
 	OPT_SAVE_REG_TO_PACA(area+EX_CFAR, r10, CPU_FTR_CFAR);		\
 	EXCEPTION_PROLOG_1(area, extra, vec);				\
 	EXCEPTION_PROLOG_PSERIES_1(label, h);
+/* Have the PACA in r13 already */
+#define EXCEPTION_PROLOG_PSERIES_PACA(area, label, h, extra, vec)	\
+	EXCEPTION_PROLOG_0_PACA(area);					\
+	EXCEPTION_PROLOG_1(area, extra, vec);				\
+	EXCEPTION_PROLOG_PSERIES_1(label, h);
 #define __KVMTEST(h, n)							\
 	lbz	r10,HSTATE_IN_GUEST(r13);				\
 	cmpwi	r10,0;							\

arch/powerpc/include/asm/ppc-opcode.h+1−0

@@ -460,5 +460,6 @@ · 459 unmodified lines
460		460
461	#define PPC_SLBIA(IH) stringify_in_c(.long PPC_INST_SLBIA \| \	461	#define PPC_SLBIA(IH) stringify_in_c(.long PPC_INST_SLBIA \| \
462	((IH & 0x7) << 21))	462	((IH & 0x7) << 21))
		463	#define PPC_INVALIDATE_ERAT PPC_SLBIA(7)
463		464
464	#endif /* _ASM_POWERPC_PPC_OPCODE_H */	465	#endif /* _ASM_POWERPC_PPC_OPCODE_H */

arch/powerpc/kernel/exceptions-64s.S+8−3

 EXC_REAL_BEGIN(system_reset, 0x100, 0x200)
 	SET_SCRATCH0(r13)
-	EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common, EXC_STD,
+	GET_PACA(r13)
+	clrrdi	r13,r13,1 /* Last bit of HSPRG0 is set if waking from winkle */
+	EXCEPTION_PROLOG_PSERIES_PACA(PACA_EXGEN, system_reset_common, EXC_STD,
 				 IDLETEST, 0x100)
 EXC_REAL_END(system_reset, 0x100, 0x200)
 #ifdef CONFIG_PPC_P7_NAP
 EXC_COMMON_BEGIN(system_reset_idle_common)
+BEGIN_FTR_SECTION
+	GET_PACA(r13) /* Restore HSPRG0 to get the winkle bit in r13 */
+END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
 	bl	pnv_restore_hyp_resource
 	li	r0,PNV_THREAD_RUNNING
 	SET_SCRATCH0(r13)		/* save r13 */
 	/*
 	 * Running native on arch 2.06 or later, we may wakeup from winkle
-	 * inside machine check. If yes, then last bit of HSPGR0 would be set
+	 * inside machine check. If yes, then last bit of HSPRG0 would be set
 	 * to 1. Hence clear it unconditionally.
 	 */
 	GET_PACA(r13)
 	/*
 	 * Go back to winkle. Please note that this thread was woken up in
 	 * machine check from winkle and have not restored the per-subcore
-	 * state. Hence before going back to winkle, set last bit of HSPGR0
+	 * state. Hence before going back to winkle, set last bit of HSPRG0
 	 * to 1. This will make sure that if this thread gets woken up
 	 * again at reset vector 0x100 then it will get chance to restore
 	 * the subcore state.

arch/powerpc/kernel/process.c+21−21

@@ -1215,7 +1215,7 @@ static void show_instructions(struct pt_regs *regs) · 1214 unmodified lines
1215	int instr;	1215	int instr;
1216		1216
1217	if (!(i % 8))	1217	if (!(i % 8))
1218	printk("\n");	1218	pr_cont("\n");
1219		1219
1220	#if !defined(CONFIG_BOOKE)	1220	#if !defined(CONFIG_BOOKE)
1221	/* If executing with the IMMU off, adjust pc rather	1221	/* If executing with the IMMU off, adjust pc rather
@@ -1227,18 +1227,18 @@ static void show_instructions(struct pt_regs *regs) · 5 unmodified lines
1227		1227
1228	if (!__kernel_text_address(pc) \|\|	1228	if (!__kernel_text_address(pc) \|\|
1229	probe_kernel_address((unsigned int __user *)pc, instr)) {	1229	probe_kernel_address((unsigned int __user *)pc, instr)) {
1230	printk(KERN_CONT "XXXXXXXX ");	1230	pr_cont("XXXXXXXX ");
1231	} else {	1231	} else {
1232	if (regs->nip == pc)	1232	if (regs->nip == pc)
1233	printk(KERN_CONT "<%08x> ", instr);	1233	pr_cont("<%08x> ", instr);
1234	else	1234	else
1235	printk(KERN_CONT "%08x ", instr);	1235	pr_cont("%08x ", instr);
1236	}	1236	}
1237		1237
1238	pc += sizeof(int);	1238	pc += sizeof(int);
1239	}	1239	}
1240		1240
1241	printk("\n");	1241	pr_cont("\n");
1242	}	1242	}
1243		1243
1244	struct regbit {	1244	struct regbit {
@@ -1282,7 +1282,7 @@ static void print_bits(unsigned long val, struct regbit bits, const char sep) · 37 unmodified lines
1282		1282
1283	for (; bits->bit; ++bits)	1283	for (; bits->bit; ++bits)
1284	if (val & bits->bit) {	1284	if (val & bits->bit) {
1285	printk("%s%s", s, bits->name);	1285	pr_cont("%s%s", s, bits->name);
1286	s = sep;	1286	s = sep;
1287	}	1287	}
1288	}	1288	}
@@ -1305,9 +1305,9 @@ static void print_tm_bits(unsigned long val) · 16 unmodified lines
1305	* T: Transactional (bit 34)	1305	* T: Transactional (bit 34)
1306	*/	1306	*/
1307	if (val & (MSR_TM \| MSR_TS_S \| MSR_TS_T)) {	1307	if (val & (MSR_TM \| MSR_TS_S \| MSR_TS_T)) {
1308	printk(",TM[");	1308	pr_cont(",TM[");
1309	print_bits(val, msr_tm_bits, "");	1309	print_bits(val, msr_tm_bits, "");
1310	printk("]");	1310	pr_cont("]");
1311	}	1311	}
1312	}	1312	}
1313	#else	1313	#else
@@ -1316,10 +1316,10 @@ static void print_tm_bits(unsigned long val) {} · 2 unmodified lines
1316		1316
1317	static void print_msr_bits(unsigned long val)	1317	static void print_msr_bits(unsigned long val)
1318	{	1318	{
1319	printk("<");	1319	pr_cont("<");
1320	print_bits(val, msr_bits, ",");	1320	print_bits(val, msr_bits, ",");
1321	print_tm_bits(val);	1321	print_tm_bits(val);
1322	printk(">");	1322	pr_cont(">");
1323	}	1323	}
1324		1324
1325	#ifdef CONFIG_PPC64	1325	#ifdef CONFIG_PPC64
@@ -1347,29 +1347,29 @@ void show_regs(struct pt_regs * regs) · 21 unmodified lines
1347	printk(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer);	1347	printk(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer);
1348	trap = TRAP(regs);	1348	trap = TRAP(regs);
1349	if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR))	1349	if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR))
1350	printk("CFAR: "REG" ", regs->orig_gpr3);	1350	pr_cont("CFAR: "REG" ", regs->orig_gpr3);
1351	if (trap == 0x200 \|\| trap == 0x300 \|\| trap == 0x600)	1351	if (trap == 0x200 \|\| trap == 0x300 \|\| trap == 0x600)
1352	#if defined(CONFIG_4xx) \|\| defined(CONFIG_BOOKE)	1352	#if defined(CONFIG_4xx) \|\| defined(CONFIG_BOOKE)
1353	printk("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr);	1353	pr_cont("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr);
1354	#else	1354	#else
1355	printk("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr);	1355	pr_cont("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr);
1356	#endif	1356	#endif
1357	#ifdef CONFIG_PPC64	1357	#ifdef CONFIG_PPC64
1358	printk("SOFTE: %ld ", regs->softe);	1358	pr_cont("SOFTE: %ld ", regs->softe);
1359	#endif	1359	#endif
1360	#ifdef CONFIG_PPC_TRANSACTIONAL_MEM	1360	#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1361	if (MSR_TM_ACTIVE(regs->msr))	1361	if (MSR_TM_ACTIVE(regs->msr))
1362	printk("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch);	1362	pr_cont("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch);
1363	#endif	1363	#endif
1364		1364
1365	for (i = 0; i < 32; i++) {	1365	for (i = 0; i < 32; i++) {
1366	if ((i % REGS_PER_LINE) == 0)	1366	if ((i % REGS_PER_LINE) == 0)
1367	printk("\nGPR%02d: ", i);	1367	pr_cont("\nGPR%02d: ", i);
1368	printk(REG " ", regs->gpr[i]);	1368	pr_cont(REG " ", regs->gpr[i]);
1369	if (i == LAST_VOLATILE && !FULL_REGS(regs))	1369	if (i == LAST_VOLATILE && !FULL_REGS(regs))
1370	break;	1370	break;
1371	}	1371	}
1372	printk("\n");	1372	pr_cont("\n");
1373	#ifdef CONFIG_KALLSYMS	1373	#ifdef CONFIG_KALLSYMS
1374	/*	1374	/*
1375	* Lookup NIP late so we have the best change of getting the	1375	* Lookup NIP late so we have the best change of getting the
@@ -1900,14 +1900,14 @@ void show_stack(struct task_struct tsk, unsigned long stack) · 524 unmodified lines
1900	printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip);	1900	printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip);
1901	#ifdef CONFIG_FUNCTION_GRAPH_TRACER	1901	#ifdef CONFIG_FUNCTION_GRAPH_TRACER
1902	if ((ip == rth) && curr_frame >= 0) {	1902	if ((ip == rth) && curr_frame >= 0) {
1903	printk(" (%pS)",	1903	pr_cont(" (%pS)",
1904	(void *)current->ret_stack[curr_frame].ret);	1904	(void *)current->ret_stack[curr_frame].ret);
1905	curr_frame--;	1905	curr_frame--;
1906	}	1906	}
1907	#endif	1907	#endif
1908	if (firstframe)	1908	if (firstframe)
1909	printk(" (unreliable)");	1909	pr_cont(" (unreliable)");
1910	printk("\n");	1910	pr_cont("\n");
1911	}	1911	}
1912	firstframe = 0;	1912	firstframe = 0;
1913		1913

arch/powerpc/kernel/setup_64.c+14−6

 		if (firmware_has_feature(FW_FEATURE_OPAL))
 			opal_configure_cores();
-		/* Enable AIL if supported, and we are in hypervisor mode */
+		/* AIL on native is done in cpu_ready_for_interrupts() */
-		if (early_cpu_has_feature(CPU_FTR_HVMODE) &&
-		    early_cpu_has_feature(CPU_FTR_ARCH_207S)) {
-			unsigned long lpcr = mfspr(SPRN_LPCR);
-			mtspr(SPRN_LPCR, lpcr | LPCR_AIL_3);
-		}
 	}
 }
 static void cpu_ready_for_interrupts(void)
 {
+	/*
+	 * Enable AIL if supported, and we are in hypervisor mode. This
+	 * is called once for every processor.
+	 *
+	 * If we are not in hypervisor mode the job is done once for
+	 * the whole partition in configure_exceptions().
+	 */
+	if (early_cpu_has_feature(CPU_FTR_HVMODE) &&
+	    early_cpu_has_feature(CPU_FTR_ARCH_207S)) {
+		unsigned long lpcr = mfspr(SPRN_LPCR);
+		mtspr(SPRN_LPCR, lpcr | LPCR_AIL_3);
+	}
 	/* Set IR and DR in PACA MSR */
 	get_paca()->kernel_msr = MSR_KERNEL;
 }

arch/powerpc/mm/hash_utils_64.c+4−0

 {
 	/* Initialize hash table for that CPU */
 	if (!firmware_has_feature(FW_FEATURE_LPAR)) {
+		if (cpu_has_feature(CPU_FTR_POWER9_DD1))
+			update_hid_for_hash();
 		if (!cpu_has_feature(CPU_FTR_ARCH_300))
 			mtspr(SPRN_SDR1, _SDR1);
 		else

arch/powerpc/mm/pgtable-radix.c+4−0

@@ -388,6 +388,10 @@ void radix__early_init_mmu_secondary(void) · 387 unmodified lines
388	* update partition table control register and UPRT	388	* update partition table control register and UPRT
389	*/	389	*/
390	if (!firmware_has_feature(FW_FEATURE_LPAR)) {	390	if (!firmware_has_feature(FW_FEATURE_LPAR)) {
		391
		392	if (cpu_has_feature(CPU_FTR_POWER9_DD1))
		393	update_hid_for_radix();
		394
391	lpcr = mfspr(SPRN_LPCR);	395	lpcr = mfspr(SPRN_LPCR);
392	mtspr(SPRN_LPCR, lpcr \| LPCR_UPRT \| LPCR_HR);	396	mtspr(SPRN_LPCR, lpcr \| LPCR_UPRT \| LPCR_HR);
393		397

arch/powerpc/mm/tlb-radix.c+4−0

 	for (set = 0; set < POWER9_TLB_SETS_RADIX ; set++) {
 		__tlbiel_pid(pid, set, ric);
 	}
+	if (cpu_has_feature(CPU_FTR_POWER9_DD1))
+		asm volatile(PPC_INVALIDATE_ERAT : : :"memory");
 	return;
 }
 	asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
 		     : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
 	asm volatile("ptesync": : :"memory");
+	if (cpu_has_feature(CPU_FTR_POWER9_DD1))
+		asm volatile(PPC_INVALIDATE_ERAT : : :"memory");
 }
 static inline void _tlbie_va(unsigned long va, unsigned long pid,

arch/sparc/Kconfig+23−0

@@ -43,6 +43,7 @@ config SPARC · 42 unmodified lines
43	select ARCH_HAS_SG_CHAIN	43	select ARCH_HAS_SG_CHAIN
44	select CPU_NO_EFFICIENT_FFS	44	select CPU_NO_EFFICIENT_FFS
45	select HAVE_ARCH_HARDENED_USERCOPY	45	select HAVE_ARCH_HARDENED_USERCOPY
		46	select PROVE_LOCKING_SMALL if PROVE_LOCKING
46		47
47	config SPARC32	48	config SPARC32
48	def_bool !64BIT	49	def_bool !64BIT
@@ -89,6 +90,14 @@ config ARCH_DEFCONFIG · 40 unmodified lines
89	config ARCH_PROC_KCORE_TEXT	90	config ARCH_PROC_KCORE_TEXT
90	def_bool y	91	def_bool y
91		92
		93	config ARCH_ATU
		94	bool
		95	default y if SPARC64
		96
		97	config ARCH_DMA_ADDR_T_64BIT
		98	bool
		99	default y if ARCH_ATU
		100
92	config IOMMU_HELPER	101	config IOMMU_HELPER
93	bool	102	bool
94	default y if SPARC64	103	default y if SPARC64
@@ -304,6 +313,20 @@ config ARCH_SPARSEMEM_ENABLE · 209 unmodified lines
304	config ARCH_SPARSEMEM_DEFAULT	313	config ARCH_SPARSEMEM_DEFAULT
305	def_bool y if SPARC64	314	def_bool y if SPARC64
306		315
		316	config FORCE_MAX_ZONEORDER
		317	int "Maximum zone order"
		318	default "13"
		319	help
		320	The kernel memory allocator divides physically contiguous memory
		321	blocks into "zones", where each zone is a power of two number of
		322	pages. This option selects the largest power of two that the kernel
		323	keeps in the memory allocator. If you need to allocate very large
		324	blocks of physically contiguous memory, then you may need to
		325	increase this value.
		326
		327	This config option is actually maximum order plus one. For example,
		328	a value of 13 means that the largest free memory block is 2^12 pages.
		329
307	source "mm/Kconfig"	330	source "mm/Kconfig"
308		331
309	if SPARC64	332	if SPARC64

arch/sparc/include/asm/hypervisor.h+343−0

@@ -2335,6 +2335,348 @@ unsigned long sun4v_vintr_set_target(unsigned long dev_handle, · 2334 unmodified lines
2335	*/	2335	*/
2336	#define HV_FAST_PCI_MSG_SETVALID 0xd3	2336	#define HV_FAST_PCI_MSG_SETVALID 0xd3
2337		2337
		2338	/* PCI IOMMU v2 definitions and services
		2339	*
		2340	* While the PCI IO definitions above is valid IOMMU v2 adds new PCI IO
		2341	* definitions and services.
		2342	*
		2343	* CTE Clump Table Entry. First level table entry in the ATU.
		2344	*
		2345	* pci_device_list
		2346	* A 32-bit aligned list of pci_devices.
		2347	*
		2348	* pci_device_listp
		2349	* real address of a pci_device_list. 32-bit aligned.
		2350	*
		2351	* iotte IOMMU translation table entry.
		2352	*
		2353	* iotte_attributes
		2354	* IO Attributes for IOMMU v2 mappings. In addition to
		2355	* read, write IOMMU v2 supports relax ordering
		2356	*
		2357	* io_page_list A 64-bit aligned list of real addresses. Each real
		2358	* address in an io_page_list must be properly aligned
		2359	* to the pagesize of the given IOTSB.
		2360	*
		2361	* io_page_list_p Real address of an io_page_list, 64-bit aligned.
		2362	*
		2363	* IOTSB IO Translation Storage Buffer. An aligned table of
		2364	* IOTTEs. Each IOTSB has a pagesize, table size, and
		2365	* virtual address associated with it that must match
		2366	* a pagesize and table size supported by the un-derlying
		2367	* hardware implementation. The alignment requirements
		2368	* for an IOTSB depend on the pagesize used for that IOTSB.
		2369	* Each IOTTE in an IOTSB maps one pagesize-sized page.
		2370	* The size of the IOTSB dictates how large of a virtual
		2371	* address space the IOTSB is capable of mapping.
		2372	*
		2373	* iotsb_handle An opaque identifier for an IOTSB. A devhandle plus
		2374	* iotsb_handle represents a binding of an IOTSB to a
		2375	* PCI root complex.
		2376	*
		2377	* iotsb_index Zero-based IOTTE number within an IOTSB.
		2378	*/
		2379
		2380	/* The index_count argument consists of two fields:
		2381	* bits 63:48 #iottes and bits 47:0 iotsb_index
		2382	*/
		2383	#define HV_PCI_IOTSB_INDEX_COUNT(__iottes, __iotsb_index) \
		2384	(((u64)(__iottes) << 48UL) \| ((u64)(__iotsb_index)))
		2385
		2386	/* pci_iotsb_conf()
		2387	* TRAP: HV_FAST_TRAP
		2388	* FUNCTION: HV_FAST_PCI_IOTSB_CONF
		2389	* ARG0: devhandle
		2390	* ARG1: r_addr
		2391	* ARG2: size
		2392	* ARG3: pagesize
		2393	* ARG4: iova
		2394	* RET0: status
		2395	* RET1: iotsb_handle
		2396	* ERRORS: EINVAL Invalid devhandle, size, iova, or pagesize
		2397	* EBADALIGN r_addr is not properly aligned
		2398	* ENORADDR r_addr is not a valid real address
		2399	* ETOOMANY No further IOTSBs may be configured
		2400	* EBUSY Duplicate devhandle, raddir, iova combination
		2401	*
		2402	* Create an IOTSB suitable for the PCI root complex identified by devhandle,
		2403	* for the DMA virtual address defined by the argument iova.
		2404	*
		2405	* r_addr is the properly aligned base address of the IOTSB and size is the
		2406	* IOTSB (table) size in bytes.The IOTSB is required to be zeroed prior to
		2407	* being configured. If it contains any values other than zeros then the
		2408	* behavior is undefined.
		2409	*
		2410	* pagesize is the size of each page in the IOTSB. Note that the combination of
		2411	* size (table size) and pagesize must be valid.
		2412	*
		2413	* virt is the DMA virtual address this IOTSB will map.
		2414	*
		2415	* If successful, the opaque 64-bit handle iotsb_handle is returned in ret1.
		2416	* Once configured, privileged access to the IOTSB memory is prohibited and
		2417	* creates undefined behavior. The only permitted access is indirect via these
		2418	* services.
		2419	*/
		2420	#define HV_FAST_PCI_IOTSB_CONF 0x190
		2421
		2422	/* pci_iotsb_info()
		2423	* TRAP: HV_FAST_TRAP
		2424	* FUNCTION: HV_FAST_PCI_IOTSB_INFO
		2425	* ARG0: devhandle
		2426	* ARG1: iotsb_handle
		2427	* RET0: status
		2428	* RET1: r_addr
		2429	* RET2: size
		2430	* RET3: pagesize
		2431	* RET4: iova
		2432	* RET5: #bound
		2433	* ERRORS: EINVAL Invalid devhandle or iotsb_handle
		2434	*
		2435	* This service returns configuration information about an IOTSB previously
		2436	* created with pci_iotsb_conf.
		2437	*
		2438	* iotsb_handle value 0 may be used with this service to inquire about the
		2439	* legacy IOTSB that may or may not exist. If the service succeeds, the return
		2440	* values describe the legacy IOTSB and I/O virtual addresses mapped by that
		2441	* table. However, the table base address r_addr may contain the value -1 which
		2442	* indicates a memory range that cannot be accessed or be reclaimed.
		2443	*
		2444	* The return value #bound contains the number of PCI devices that iotsb_handle
		2445	* is currently bound to.
		2446	*/
		2447	#define HV_FAST_PCI_IOTSB_INFO 0x191
		2448
		2449	/* pci_iotsb_unconf()
		2450	* TRAP: HV_FAST_TRAP
		2451	* FUNCTION: HV_FAST_PCI_IOTSB_UNCONF
		2452	* ARG0: devhandle
		2453	* ARG1: iotsb_handle
		2454	* RET0: status
		2455	* ERRORS: EINVAL Invalid devhandle or iotsb_handle
		2456	* EBUSY The IOTSB is bound and may not be unconfigured
		2457	*
		2458	* This service unconfigures the IOTSB identified by the devhandle and
		2459	* iotsb_handle arguments, previously created with pci_iotsb_conf.
		2460	* The IOTSB must not be currently bound to any device or the service will fail
		2461	*
		2462	* If the call succeeds, iotsb_handle is no longer valid.
		2463	*/
		2464	#define HV_FAST_PCI_IOTSB_UNCONF 0x192
		2465
		2466	/* pci_iotsb_bind()
		2467	* TRAP: HV_FAST_TRAP
		2468	* FUNCTION: HV_FAST_PCI_IOTSB_BIND
		2469	* ARG0: devhandle
		2470	* ARG1: iotsb_handle
		2471	* ARG2: pci_device
		2472	* RET0: status
		2473	* ERRORS: EINVAL Invalid devhandle, iotsb_handle, or pci_device
		2474	* EBUSY A PCI function is already bound to an IOTSB at the same
		2475	* address range as specified by devhandle, iotsb_handle.
		2476	*
		2477	* This service binds the PCI function specified by the argument pci_device to
		2478	* the IOTSB specified by the arguments devhandle and iotsb_handle.
		2479	*
		2480	* The PCI device function is bound to the specified IOTSB with the IOVA range
		2481	* specified when the IOTSB was configured via pci_iotsb_conf. If the function
		2482	* is already bound then it is unbound first.
		2483	*/
		2484	#define HV_FAST_PCI_IOTSB_BIND 0x193
		2485
		2486	/* pci_iotsb_unbind()
		2487	* TRAP: HV_FAST_TRAP
		2488	* FUNCTION: HV_FAST_PCI_IOTSB_UNBIND
		2489	* ARG0: devhandle
		2490	* ARG1: iotsb_handle
		2491	* ARG2: pci_device
		2492	* RET0: status
		2493	* ERRORS: EINVAL Invalid devhandle, iotsb_handle, or pci_device
		2494	* ENOMAP The PCI function was not bound to the specified IOTSB
		2495	*
		2496	* This service unbinds the PCI device specified by the argument pci_device
		2497	* from the IOTSB identified * by the arguments devhandle and iotsb_handle.
		2498	*
		2499	* If the PCI device is not bound to the specified IOTSB then this service will
		2500	* fail with status ENOMAP
		2501	*/
		2502	#define HV_FAST_PCI_IOTSB_UNBIND 0x194
		2503
		2504	/* pci_iotsb_get_binding()
		2505	* TRAP: HV_FAST_TRAP
		2506	* FUNCTION: HV_FAST_PCI_IOTSB_GET_BINDING
		2507	* ARG0: devhandle
		2508	* ARG1: iotsb_handle
		2509	* ARG2: iova
		2510	* RET0: status
		2511	* RET1: iotsb_handle
		2512	* ERRORS: EINVAL Invalid devhandle, pci_device, or iova
		2513	* ENOMAP The PCI function is not bound to an IOTSB at iova
		2514	*
		2515	* This service returns the IOTSB binding, iotsb_handle, for a given pci_device
		2516	* and DMA virtual address, iova.
		2517	*
		2518	* iova must be the base address of a DMA virtual address range as defined by
		2519	* the iommu-address-ranges property in the root complex device node defined
		2520	* by the argument devhandle.
		2521	*/
		2522	#define HV_FAST_PCI_IOTSB_GET_BINDING 0x195
		2523
		2524	/* pci_iotsb_map()
		2525	* TRAP: HV_FAST_TRAP
		2526	* FUNCTION: HV_FAST_PCI_IOTSB_MAP
		2527	* ARG0: devhandle
		2528	* ARG1: iotsb_handle
		2529	* ARG2: index_count
		2530	* ARG3: iotte_attributes
		2531	* ARG4: io_page_list_p
		2532	* RET0: status
		2533	* RET1: #mapped
		2534	* ERRORS: EINVAL Invalid devhandle, iotsb_handle, #iottes,
		2535	* iotsb_index or iotte_attributes
		2536	* EBADALIGN Improperly aligned io_page_list_p or I/O page
		2537	* address in the I/O page list.
		2538	* ENORADDR Invalid io_page_list_p or I/O page address in
		2539	* the I/O page list.
		2540	*
		2541	* This service creates and flushes mappings in the IOTSB defined by the
		2542	* arguments devhandle, iotsb.
		2543	*
		2544	* The index_count argument consists of two fields. Bits 63:48 contain #iotte
		2545	* and bits 47:0 contain iotsb_index
		2546	*
		2547	* The first mapping is created in the IOTSB index specified by iotsb_index.
		2548	* Subsequent mappings are created at iotsb_index+1 and so on.
		2549	*
		2550	* The attributes of each mapping are defined by the argument iotte_attributes.
		2551	*
		2552	* The io_page_list_p specifies the real address of the 64-bit-aligned list of
		2553	* #iottes I/O page addresses. Each page address must be a properly aligned
		2554	* real address of a page to be mapped in the IOTSB. The first entry in the I/O
		2555	* page list contains the real address of the first page, the 2nd entry for the
		2556	* 2nd page, and so on.
		2557	*
		2558	* #iottes must be greater than zero.
		2559	*
		2560	* The return value #mapped is the actual number of mappings created, which may
		2561	* be less than or equal to the argument #iottes. If the function returns
		2562	* successfully with a #mapped value less than the requested #iottes then the
		2563	* caller should continue to invoke the service with updated iotsb_index,
		2564	* #iottes, and io_page_list_p arguments until all pages are mapped.
		2565	*
		2566	* This service must not be used to demap a mapping. In other words, all
		2567	* mappings must be valid and have one or both of the RW attribute bits set.
		2568	*
		2569	* Note:
		2570	* It is implementation-defined whether I/O page real address validity checking
		2571	* is done at time mappings are established or deferred until they are
		2572	* accessed.
		2573	*/
		2574	#define HV_FAST_PCI_IOTSB_MAP 0x196
		2575
		2576	/* pci_iotsb_map_one()
		2577	* TRAP: HV_FAST_TRAP
		2578	* FUNCTION: HV_FAST_PCI_IOTSB_MAP_ONE
		2579	* ARG0: devhandle
		2580	* ARG1: iotsb_handle
		2581	* ARG2: iotsb_index
		2582	* ARG3: iotte_attributes
		2583	* ARG4: r_addr
		2584	* RET0: status
		2585	* ERRORS: EINVAL Invalid devhandle,iotsb_handle, iotsb_index
		2586	* or iotte_attributes
		2587	* EBADALIGN Improperly aligned r_addr
		2588	* ENORADDR Invalid r_addr
		2589	*
		2590	* This service creates and flushes a single mapping in the IOTSB defined by the
		2591	* arguments devhandle, iotsb.
		2592	*
		2593	* The mapping for the page at r_addr is created at the IOTSB index specified by
		2594	* iotsb_index with the attributes iotte_attributes.
		2595	*
		2596	* This service must not be used to demap a mapping. In other words, the mapping
		2597	* must be valid and have one or both of the RW attribute bits set.
		2598	*
		2599	* Note:
		2600	* It is implementation-defined whether I/O page real address validity checking
		2601	* is done at time mappings are established or deferred until they are
		2602	* accessed.
		2603	*/
		2604	#define HV_FAST_PCI_IOTSB_MAP_ONE 0x197
		2605
		2606	/* pci_iotsb_demap()
		2607	* TRAP: HV_FAST_TRAP
		2608	* FUNCTION: HV_FAST_PCI_IOTSB_DEMAP
		2609	* ARG0: devhandle
		2610	* ARG1: iotsb_handle
		2611	* ARG2: iotsb_index
		2612	* ARG3: #iottes
		2613	* RET0: status
		2614	* RET1: #unmapped
		2615	* ERRORS: EINVAL Invalid devhandle, iotsb_handle, iotsb_index or #iottes
		2616	*
		2617	* This service unmaps and flushes up to #iottes mappings starting at index
		2618	* iotsb_index from the IOTSB defined by the arguments devhandle, iotsb.
		2619	*
		2620	* #iottes must be greater than zero.
		2621	*
		2622	* The actual number of IOTTEs unmapped is returned in #unmapped and may be less
		2623	* than or equal to the requested number of IOTTEs, #iottes.
		2624	*
		2625	* If #unmapped is less than #iottes, the caller should continue to invoke this
		2626	* service with updated iotsb_index and #iottes arguments until all pages are
		2627	* demapped.
		2628	*/
		2629	#define HV_FAST_PCI_IOTSB_DEMAP 0x198
		2630
		2631	/* pci_iotsb_getmap()
		2632	* TRAP: HV_FAST_TRAP
		2633	* FUNCTION: HV_FAST_PCI_IOTSB_GETMAP
		2634	* ARG0: devhandle
		2635	* ARG1: iotsb_handle
		2636	* ARG2: iotsb_index
		2637	* RET0: status
		2638	* RET1: r_addr
		2639	* RET2: iotte_attributes
		2640	* ERRORS: EINVAL Invalid devhandle, iotsb_handle, or iotsb_index
		2641	* ENOMAP No mapping was found
		2642	*
		2643	* This service returns the mapping specified by index iotsb_index from the
		2644	* IOTSB defined by the arguments devhandle, iotsb.
		2645	*
		2646	* Upon success, the real address of the mapping shall be returned in
		2647	* r_addr and thethe IOTTE mapping attributes shall be returned in
		2648	* iotte_attributes.
		2649	*
		2650	* The return value iotte_attributes may not include optional features used in
		2651	* the call to create the mapping.
		2652	*/
		2653	#define HV_FAST_PCI_IOTSB_GETMAP 0x199
		2654
		2655	/* pci_iotsb_sync_mappings()
		2656	* TRAP: HV_FAST_TRAP
		2657	* FUNCTION: HV_FAST_PCI_IOTSB_SYNC_MAPPINGS
		2658	* ARG0: devhandle
		2659	* ARG1: iotsb_handle
		2660	* ARG2: iotsb_index
		2661	* ARG3: #iottes
		2662	* RET0: status
		2663	* RET1: #synced
		2664	* ERROS: EINVAL Invalid devhandle, iotsb_handle, iotsb_index, or #iottes
		2665	*
		2666	* This service synchronizes #iottes mappings starting at index iotsb_index in
		2667	* the IOTSB defined by the arguments devhandle, iotsb.
		2668	*
		2669	* #iottes must be greater than zero.
		2670	*
		2671	* The actual number of IOTTEs synchronized is returned in #synced, which may
		2672	* be less than or equal to the requested number, #iottes.
		2673	*
		2674	* Upon a successful return, #synced is less than #iottes, the caller should
		2675	* continue to invoke this service with updated iotsb_index and #iottes
		2676	* arguments until all pages are synchronized.
		2677	*/
		2678	#define HV_FAST_PCI_IOTSB_SYNC_MAPPINGS 0x19a
		2679
2338	/* Logical Domain Channel services. */	2680	/* Logical Domain Channel services. */
2339		2681
2340	#define LDC_CHANNEL_DOWN 0	2682	#define LDC_CHANNEL_DOWN 0
@@ -2993,6 +3335,7 @@ unsigned long sun4v_m7_set_perfreg(unsigned long reg_num, · 652 unmodified lines
2993	#define HV_GRP_SDIO 0x0108	3335	#define HV_GRP_SDIO 0x0108
2994	#define HV_GRP_SDIO_ERR 0x0109	3336	#define HV_GRP_SDIO_ERR 0x0109
2995	#define HV_GRP_REBOOT_DATA 0x0110	3337	#define HV_GRP_REBOOT_DATA 0x0110
		3338	#define HV_GRP_ATU 0x0111
2996	#define HV_GRP_M7_PERF 0x0114	3339	#define HV_GRP_M7_PERF 0x0114
2997	#define HV_GRP_NIAG_PERF 0x0200	3340	#define HV_GRP_NIAG_PERF 0x0200
2998	#define HV_GRP_FIRE_PERF 0x0201	3341	#define HV_GRP_FIRE_PERF 0x0201

arch/sparc/include/asm/iommu_64.h+28−0

@@ -24,8 +24,36 @@ struct iommu_arena { · 23 unmodified lines
24	unsigned int limit;	24	unsigned int limit;
25	};	25	};
26		26
		27	#define ATU_64_SPACE_SIZE 0x800000000 /* 32G */
		28
		29	/* Data structures for SPARC ATU architecture */
		30	struct atu_iotsb {
		31	void table; / IOTSB table base virtual addr*/
		32	u64 ra; /* IOTSB table real addr */
		33	u64 dvma_size; /* ranges[3].size or OS slected 32G size */
		34	u64 dvma_base; /* ranges[3].base */
		35	u64 table_size; /* IOTSB table size */
		36	u64 page_size; /* IO PAGE size for IOTSB */
		37	u32 iotsb_num; /* tsbnum is same as iotsb_handle */
		38	};
		39
		40	struct atu_ranges {
		41	u64 base;
		42	u64 size;
		43	};
		44
		45	struct atu {
		46	struct atu_ranges *ranges;
		47	struct atu_iotsb *iotsb;
		48	struct iommu_map_table tbl;
		49	u64 base;
		50	u64 size;
		51	u64 dma_addr_mask;
		52	};
		53
27	struct iommu {	54	struct iommu {
28	struct iommu_map_table tbl;	55	struct iommu_map_table tbl;
		56	struct atu *atu;
29	spinlock_t lock;	57	spinlock_t lock;
30	u32 dma_addr_mask;	58	u32 dma_addr_mask;
31	iopte_t *page_table;	59	iopte_t *page_table;

arch/sparc/kernel/hvapi.c+1−0

@@ -39,6 +39,7 @@ static struct api_info api_table[] = { · 38 unmodified lines
39	{ .group = HV_GRP_SDIO, },	39	{ .group = HV_GRP_SDIO, },
40	{ .group = HV_GRP_SDIO_ERR, },	40	{ .group = HV_GRP_SDIO_ERR, },
41	{ .group = HV_GRP_REBOOT_DATA, },	41	{ .group = HV_GRP_REBOOT_DATA, },
		42	{ .group = HV_GRP_ATU, .flags = FLAG_PRE_API },
42	{ .group = HV_GRP_NIAG_PERF, .flags = FLAG_PRE_API },	43	{ .group = HV_GRP_NIAG_PERF, .flags = FLAG_PRE_API },
43	{ .group = HV_GRP_FIRE_PERF, },	44	{ .group = HV_GRP_FIRE_PERF, },
44	{ .group = HV_GRP_N2_CPU, },	45	{ .group = HV_GRP_N2_CPU, },

arch/sparc/kernel/iommu.c+6−2

 	struct iommu *iommu = dev->archdata.iommu;
 	u64 dma_addr_mask = iommu->dma_addr_mask;
-	if (device_mask >= (1UL << 32UL))
+	if (device_mask > DMA_BIT_MASK(32)) {
-		return 0;
+		if (iommu->atu)
+			dma_addr_mask = iommu->atu->dma_addr_mask;
+		else
+			return 0;
+	}
 	if ((device_mask & dma_addr_mask) == dma_addr_mask)
 		return 1;

arch/sparc/kernel/iommu_common.h+0−1

@@ -13,7 +13,6 @@ · 12 unmodified lines
13	#include <linux/scatterlist.h>	13	#include <linux/scatterlist.h>
14	#include <linux/device.h>	14	#include <linux/device.h>
15	#include <linux/iommu-helper.h>	15	#include <linux/iommu-helper.h>
16	#include <linux/scatterlist.h>
17		16
18	#include <asm/iommu.h>	17	#include <asm/iommu.h>
19		18

arch/sparc/kernel/pci_sun4v.c+360−58

@@ -44,6 +44,9 @@ static struct vpci_version vpci_versions[] = { · 43 unmodified lines
44	{ .major = 1, .minor = 1 },	44	{ .major = 1, .minor = 1 },
45	};	45	};
46		46
		47	static unsigned long vatu_major = 1;
		48	static unsigned long vatu_minor = 1;
		49
47	#define PGLIST_NENTS (PAGE_SIZE / sizeof(u64))	50	#define PGLIST_NENTS (PAGE_SIZE / sizeof(u64))
48		51
49	struct iommu_batch {	52	struct iommu_batch {
@@ -69,34 +72,57 @@ static inline void iommu_batch_start(struct device *dev, unsigned long prot, uns · 19 unmodified lines
69	}	72	}
70		73
71	/* Interrupts must be disabled. */	74	/* Interrupts must be disabled. */
72	static long iommu_batch_flush(struct iommu_batch *p)	75	static long iommu_batch_flush(struct iommu_batch *p, u64 mask)
73	{	76	{
74	struct pci_pbm_info *pbm = p->dev->archdata.host_controller;	77	struct pci_pbm_info *pbm = p->dev->archdata.host_controller;
		78	u64 *pglist = p->pglist;
		79	u64 index_count;
75	unsigned long devhandle = pbm->devhandle;	80	unsigned long devhandle = pbm->devhandle;
76	unsigned long prot = p->prot;	81	unsigned long prot = p->prot;
77	unsigned long entry = p->entry;	82	unsigned long entry = p->entry;
78	u64 *pglist = p->pglist;
79	unsigned long npages = p->npages;	83	unsigned long npages = p->npages;
		84	unsigned long iotsb_num;
		85	unsigned long ret;
		86	long num;
80		87
81	/* VPCI maj=1, min=[0,1] only supports read and write */	88	/* VPCI maj=1, min=[0,1] only supports read and write */
82	if (vpci_major < 2)	89	if (vpci_major < 2)
83	prot &= (HV_PCI_MAP_ATTR_READ \| HV_PCI_MAP_ATTR_WRITE);	90	prot &= (HV_PCI_MAP_ATTR_READ \| HV_PCI_MAP_ATTR_WRITE);
84		91
85	while (npages != 0) {	92	while (npages != 0) {
86	long num;	93	if (mask <= DMA_BIT_MASK(32)) {
87		94	num = pci_sun4v_iommu_map(devhandle,
88	num = pci_sun4v_iommu_map(devhandle, HV_PCI_TSBID(0, entry),	95	HV_PCI_TSBID(0, entry),
89	npages, prot, __pa(pglist));	96	npages,
90	if (unlikely(num < 0)) {	97	prot,
91	if (printk_ratelimit())	98	__pa(pglist));
92	printk("iommu_batch_flush: IOMMU map of "	99	if (unlikely(num < 0)) {
93	"[%08lx:%08llx:%lx:%lx:%lx] failed with "	100	pr_err_ratelimited("%s: IOMMU map of [%08lx:%08llx:%lx:%lx:%lx] failed with status %ld\n",
94	"status %ld\n",	101	__func__,
95	devhandle, HV_PCI_TSBID(0, entry),	102	devhandle,
96	npages, prot, __pa(pglist), num);	103	HV_PCI_TSBID(0, entry),
97	return -1;	104	npages, prot, __pa(pglist),
		105	num);
		106	return -1;
		107	}
		108	} else {
		109	index_count = HV_PCI_IOTSB_INDEX_COUNT(npages, entry),
		110	iotsb_num = pbm->iommu->atu->iotsb->iotsb_num;
		111	ret = pci_sun4v_iotsb_map(devhandle,
		112	iotsb_num,
		113	index_count,
		114	prot,
		115	__pa(pglist),
		116	&num);
		117	if (unlikely(ret != HV_EOK)) {
		118	pr_err_ratelimited("%s: ATU map of [%08lx:%lx:%llx:%lx:%lx] failed with status %ld\n",
		119	__func__,
		120	devhandle, iotsb_num,
		121	index_count, prot,
		122	__pa(pglist), ret);
		123	return -1;
		124	}
98	}	125	}
99
100	entry += num;	126	entry += num;
101	npages -= num;	127	npages -= num;
102	pglist += num;	128	pglist += num;
@@ -108,19 +134,19 @@ static long iommu_batch_flush(struct iommu_batch *p) · 5 unmodified lines
108	return 0;	134	return 0;
109	}	135	}
110		136
111	static inline void iommu_batch_new_entry(unsigned long entry)	137	static inline void iommu_batch_new_entry(unsigned long entry, u64 mask)
112	{	138	{
113	struct iommu_batch *p = this_cpu_ptr(&iommu_batch);	139	struct iommu_batch *p = this_cpu_ptr(&iommu_batch);
114		140
115	if (p->entry + p->npages == entry)	141	if (p->entry + p->npages == entry)
116	return;	142	return;
117	if (p->entry != ~0UL)	143	if (p->entry != ~0UL)
118	iommu_batch_flush(p);	144	iommu_batch_flush(p, mask);
119	p->entry = entry;	145	p->entry = entry;
120	}	146	}
121		147
122	/* Interrupts must be disabled. */	148	/* Interrupts must be disabled. */
123	static inline long iommu_batch_add(u64 phys_page)	149	static inline long iommu_batch_add(u64 phys_page, u64 mask)
124	{	150	{
125	struct iommu_batch *p = this_cpu_ptr(&iommu_batch);	151	struct iommu_batch *p = this_cpu_ptr(&iommu_batch);
126		152
@@ -128,28 +154,31 @@ static inline long iommu_batch_add(u64 phys_page) · 1 unmodified line
128		154
129	p->pglist[p->npages++] = phys_page;	155	p->pglist[p->npages++] = phys_page;
130	if (p->npages == PGLIST_NENTS)	156	if (p->npages == PGLIST_NENTS)
131	return iommu_batch_flush(p);	157	return iommu_batch_flush(p, mask);
132		158
133	return 0;	159	return 0;
134	}	160	}
135		161
136	/* Interrupts must be disabled. */	162	/* Interrupts must be disabled. */
137	static inline long iommu_batch_end(void)	163	static inline long iommu_batch_end(u64 mask)
138	{	164	{
139	struct iommu_batch *p = this_cpu_ptr(&iommu_batch);	165	struct iommu_batch *p = this_cpu_ptr(&iommu_batch);
140		166
141	BUG_ON(p->npages >= PGLIST_NENTS);	167	BUG_ON(p->npages >= PGLIST_NENTS);
142		168
143	return iommu_batch_flush(p);	169	return iommu_batch_flush(p, mask);
144	}	170	}
145		171
146	static void dma_4v_alloc_coherent(struct device dev, size_t size,	172	static void dma_4v_alloc_coherent(struct device dev, size_t size,
147	dma_addr_t *dma_addrp, gfp_t gfp,	173	dma_addr_t *dma_addrp, gfp_t gfp,
148	unsigned long attrs)	174	unsigned long attrs)
149	{	175	{
		176	u64 mask;
150	unsigned long flags, order, first_page, npages, n;	177	unsigned long flags, order, first_page, npages, n;
151	unsigned long prot = 0;	178	unsigned long prot = 0;
152	struct iommu *iommu;	179	struct iommu *iommu;
		180	struct atu *atu;
		181	struct iommu_map_table *tbl;
153	struct page *page;	182	struct page *page;
154	void *ret;	183	void *ret;
155	long entry;	184	long entry;
@@ -174,14 +203,21 @@ static void dma_4v_alloc_coherent(struct device dev, size_t size, · 18 unmodified lines
174	memset((char *)first_page, 0, PAGE_SIZE << order);	203	memset((char *)first_page, 0, PAGE_SIZE << order);
175		204
176	iommu = dev->archdata.iommu;	205	iommu = dev->archdata.iommu;
		206	atu = iommu->atu;
		207
		208	mask = dev->coherent_dma_mask;
		209	if (mask <= DMA_BIT_MASK(32))
		210	tbl = &iommu->tbl;
		211	else
		212	tbl = &atu->tbl;
177		213
178	entry = iommu_tbl_range_alloc(dev, &iommu->tbl, npages, NULL,	214	entry = iommu_tbl_range_alloc(dev, tbl, npages, NULL,
179	(unsigned long)(-1), 0);	215	(unsigned long)(-1), 0);
180		216
181	if (unlikely(entry == IOMMU_ERROR_CODE))	217	if (unlikely(entry == IOMMU_ERROR_CODE))
182	goto range_alloc_fail;	218	goto range_alloc_fail;
183		219
184	*dma_addrp = (iommu->tbl.table_map_base + (entry << IO_PAGE_SHIFT));	220	*dma_addrp = (tbl->table_map_base + (entry << IO_PAGE_SHIFT));
185	ret = (void *) first_page;	221	ret = (void *) first_page;
186	first_page = __pa(first_page);	222	first_page = __pa(first_page);
187		223
@@ -193,12 +229,12 @@ static void dma_4v_alloc_coherent(struct device dev, size_t size, · 5 unmodified lines
193	entry);	229	entry);
194		230
195	for (n = 0; n < npages; n++) {	231	for (n = 0; n < npages; n++) {
196	long err = iommu_batch_add(first_page + (n * PAGE_SIZE));	232	long err = iommu_batch_add(first_page + (n * PAGE_SIZE), mask);
197	if (unlikely(err < 0L))	233	if (unlikely(err < 0L))
198	goto iommu_map_fail;	234	goto iommu_map_fail;
199	}	235	}
200		236
201	if (unlikely(iommu_batch_end() < 0L))	237	if (unlikely(iommu_batch_end(mask) < 0L))
202	goto iommu_map_fail;	238	goto iommu_map_fail;
203		239
204	local_irq_restore(flags);	240	local_irq_restore(flags);
@@ -206,25 +242,71 @@ static void dma_4v_alloc_coherent(struct device dev, size_t size, · 1 unmodified line
206	return ret;	242	return ret;
207		243
208	iommu_map_fail:	244	iommu_map_fail:
209	iommu_tbl_range_free(&iommu->tbl, *dma_addrp, npages, IOMMU_ERROR_CODE);	245	iommu_tbl_range_free(tbl, *dma_addrp, npages, IOMMU_ERROR_CODE);
210		246
211	range_alloc_fail:	247	range_alloc_fail:
212	free_pages(first_page, order);	248	free_pages(first_page, order);
213	return NULL;	249	return NULL;
214	}	250	}
215		251
216	static void dma_4v_iommu_demap(void *demap_arg, unsigned long entry,	252	unsigned long dma_4v_iotsb_bind(unsigned long devhandle,
217	unsigned long npages)	253	unsigned long iotsb_num,
		254	struct pci_bus *bus_dev)
		255	{
		256	struct pci_dev *pdev;
		257	unsigned long err;
		258	unsigned int bus;
		259	unsigned int device;
		260	unsigned int fun;
		261
		262	list_for_each_entry(pdev, &bus_dev->devices, bus_list) {
		263	if (pdev->subordinate) {
		264	/* No need to bind pci bridge */
		265	dma_4v_iotsb_bind(devhandle, iotsb_num,
		266	pdev->subordinate);
		267	} else {
		268	bus = bus_dev->number;
		269	device = PCI_SLOT(pdev->devfn);
		270	fun = PCI_FUNC(pdev->devfn);
		271	err = pci_sun4v_iotsb_bind(devhandle, iotsb_num,
		272	HV_PCI_DEVICE_BUILD(bus,
		273	device,
		274	fun));
		275
		276	/* If bind fails for one device it is going to fail
		277	* for rest of the devices because we are sharing
		278	* IOTSB. So in case of failure simply return with
		279	* error.
		280	*/
		281	if (err)
		282	return err;
		283	}
		284	}
		285
		286	return 0;
		287	}
		288
		289	static void dma_4v_iommu_demap(struct device *dev, unsigned long devhandle,
		290	dma_addr_t dvma, unsigned long iotsb_num,
		291	unsigned long entry, unsigned long npages)
218	{	292	{
219	u32 devhandle = (u32 )demap_arg;
220	unsigned long num, flags;	293	unsigned long num, flags;
		294	unsigned long ret;
221		295
222	local_irq_save(flags);	296	local_irq_save(flags);
223	do {	297	do {
224	num = pci_sun4v_iommu_demap(devhandle,	298	if (dvma <= DMA_BIT_MASK(32)) {
225	HV_PCI_TSBID(0, entry),	299	num = pci_sun4v_iommu_demap(devhandle,
226	npages);	300	HV_PCI_TSBID(0, entry),
227		301	npages);
		302	} else {
		303	ret = pci_sun4v_iotsb_demap(devhandle, iotsb_num,
		304	entry, npages, &num);
		305	if (unlikely(ret != HV_EOK)) {
		306	pr_err_ratelimited("pci_iotsb_demap() failed with error: %ld\n",
		307	ret);
		308	}
		309	}
228	entry += num;	310	entry += num;
229	npages -= num;	311	npages -= num;
230	} while (npages != 0);	312	} while (npages != 0);
@@ -236,16 +318,28 @@ static void dma_4v_free_coherent(struct device dev, size_t size, void cpu, · 5 unmodified lines
236	{	318	{
237	struct pci_pbm_info *pbm;	319	struct pci_pbm_info *pbm;
238	struct iommu *iommu;	320	struct iommu *iommu;
		321	struct atu *atu;
		322	struct iommu_map_table *tbl;
239	unsigned long order, npages, entry;	323	unsigned long order, npages, entry;
		324	unsigned long iotsb_num;
240	u32 devhandle;	325	u32 devhandle;
241		326
242	npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;	327	npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
243	iommu = dev->archdata.iommu;	328	iommu = dev->archdata.iommu;
244	pbm = dev->archdata.host_controller;	329	pbm = dev->archdata.host_controller;
		330	atu = iommu->atu;
245	devhandle = pbm->devhandle;	331	devhandle = pbm->devhandle;
246	entry = ((dvma - iommu->tbl.table_map_base) >> IO_PAGE_SHIFT);	332
247	dma_4v_iommu_demap(&devhandle, entry, npages);	333	if (dvma <= DMA_BIT_MASK(32)) {
248	iommu_tbl_range_free(&iommu->tbl, dvma, npages, IOMMU_ERROR_CODE);	334	tbl = &iommu->tbl;
		335	iotsb_num = 0; /* we don't care for legacy iommu */
		336	} else {
		337	tbl = &atu->tbl;
		338	iotsb_num = atu->iotsb->iotsb_num;
		339	}
		340	entry = ((dvma - tbl->table_map_base) >> IO_PAGE_SHIFT);
		341	dma_4v_iommu_demap(dev, devhandle, dvma, iotsb_num, entry, npages);
		342	iommu_tbl_range_free(tbl, dvma, npages, IOMMU_ERROR_CODE);
249	order = get_order(size);	343	order = get_order(size);
250	if (order < 10)	344	if (order < 10)
251	free_pages((unsigned long)cpu, order);	345	free_pages((unsigned long)cpu, order);
@@ -257,13 +351,17 @@ static dma_addr_t dma_4v_map_page(struct device dev, struct page page, · 5 unmodified lines
257	unsigned long attrs)	351	unsigned long attrs)
258	{	352	{
259	struct iommu *iommu;	353	struct iommu *iommu;
		354	struct atu *atu;
		355	struct iommu_map_table *tbl;
		356	u64 mask;
260	unsigned long flags, npages, oaddr;	357	unsigned long flags, npages, oaddr;
261	unsigned long i, base_paddr;	358	unsigned long i, base_paddr;
262	u32 bus_addr, ret;
263	unsigned long prot;	359	unsigned long prot;
		360	dma_addr_t bus_addr, ret;
264	long entry;	361	long entry;
265		362
266	iommu = dev->archdata.iommu;	363	iommu = dev->archdata.iommu;
		364	atu = iommu->atu;
267		365
268	if (unlikely(direction == DMA_NONE))	366	if (unlikely(direction == DMA_NONE))
269	goto bad;	367	goto bad;
@@ -272,13 +370,19 @@ static dma_addr_t dma_4v_map_page(struct device dev, struct page page, · 2 unmodified lines
272	npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK);	370	npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK);
273	npages >>= IO_PAGE_SHIFT;	371	npages >>= IO_PAGE_SHIFT;
274		372
275	entry = iommu_tbl_range_alloc(dev, &iommu->tbl, npages, NULL,	373	mask = *dev->dma_mask;
		374	if (mask <= DMA_BIT_MASK(32))
		375	tbl = &iommu->tbl;
		376	else
		377	tbl = &atu->tbl;
		378
		379	entry = iommu_tbl_range_alloc(dev, tbl, npages, NULL,
276	(unsigned long)(-1), 0);	380	(unsigned long)(-1), 0);
277		381
278	if (unlikely(entry == IOMMU_ERROR_CODE))	382	if (unlikely(entry == IOMMU_ERROR_CODE))
279	goto bad;	383	goto bad;
280		384
281	bus_addr = (iommu->tbl.table_map_base + (entry << IO_PAGE_SHIFT));	385	bus_addr = (tbl->table_map_base + (entry << IO_PAGE_SHIFT));
282	ret = bus_addr \| (oaddr & ~IO_PAGE_MASK);	386	ret = bus_addr \| (oaddr & ~IO_PAGE_MASK);
283	base_paddr = __pa(oaddr & IO_PAGE_MASK);	387	base_paddr = __pa(oaddr & IO_PAGE_MASK);
284	prot = HV_PCI_MAP_ATTR_READ;	388	prot = HV_PCI_MAP_ATTR_READ;
@@ -293,11 +397,11 @@ static dma_addr_t dma_4v_map_page(struct device dev, struct page page, · 8 unmodified lines
293	iommu_batch_start(dev, prot, entry);	397	iommu_batch_start(dev, prot, entry);
294		398
295	for (i = 0; i < npages; i++, base_paddr += IO_PAGE_SIZE) {	399	for (i = 0; i < npages; i++, base_paddr += IO_PAGE_SIZE) {
296	long err = iommu_batch_add(base_paddr);	400	long err = iommu_batch_add(base_paddr, mask);
297	if (unlikely(err < 0L))	401	if (unlikely(err < 0L))
298	goto iommu_map_fail;	402	goto iommu_map_fail;
299	}	403	}
300	if (unlikely(iommu_batch_end() < 0L))	404	if (unlikely(iommu_batch_end(mask) < 0L))
301	goto iommu_map_fail;	405	goto iommu_map_fail;
302		406
303	local_irq_restore(flags);	407	local_irq_restore(flags);
@@ -310,7 +414,7 @@ bad: · 6 unmodified lines
310	return DMA_ERROR_CODE;	414	return DMA_ERROR_CODE;
311		415
312	iommu_map_fail:	416	iommu_map_fail:
313	iommu_tbl_range_free(&iommu->tbl, bus_addr, npages, IOMMU_ERROR_CODE);	417	iommu_tbl_range_free(tbl, bus_addr, npages, IOMMU_ERROR_CODE);
314	return DMA_ERROR_CODE;	418	return DMA_ERROR_CODE;
315	}	419	}
316		420
@@ -320,7 +424,10 @@ static void dma_4v_unmap_page(struct device *dev, dma_addr_t bus_addr, · 3 unmodified lines
320	{	424	{
321	struct pci_pbm_info *pbm;	425	struct pci_pbm_info *pbm;
322	struct iommu *iommu;	426	struct iommu *iommu;
		427	struct atu *atu;
		428	struct iommu_map_table *tbl;
323	unsigned long npages;	429	unsigned long npages;
		430	unsigned long iotsb_num;
324	long entry;	431	long entry;
325	u32 devhandle;	432	u32 devhandle;
326		433
@@ -332,14 +439,23 @@ static void dma_4v_unmap_page(struct device *dev, dma_addr_t bus_addr, · 5 unmodified lines
332		439
333	iommu = dev->archdata.iommu;	440	iommu = dev->archdata.iommu;
334	pbm = dev->archdata.host_controller;	441	pbm = dev->archdata.host_controller;
		442	atu = iommu->atu;
335	devhandle = pbm->devhandle;	443	devhandle = pbm->devhandle;
336		444
337	npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);	445	npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
338	npages >>= IO_PAGE_SHIFT;	446	npages >>= IO_PAGE_SHIFT;
339	bus_addr &= IO_PAGE_MASK;	447	bus_addr &= IO_PAGE_MASK;
340	entry = (bus_addr - iommu->tbl.table_map_base) >> IO_PAGE_SHIFT;	448
341	dma_4v_iommu_demap(&devhandle, entry, npages);	449	if (bus_addr <= DMA_BIT_MASK(32)) {
342	iommu_tbl_range_free(&iommu->tbl, bus_addr, npages, IOMMU_ERROR_CODE);	450	iotsb_num = 0; /* we don't care for legacy iommu */
		451	tbl = &iommu->tbl;
		452	} else {
		453	iotsb_num = atu->iotsb->iotsb_num;
		454	tbl = &atu->tbl;
		455	}
		456	entry = (bus_addr - tbl->table_map_base) >> IO_PAGE_SHIFT;
		457	dma_4v_iommu_demap(dev, devhandle, bus_addr, iotsb_num, entry, npages);
		458	iommu_tbl_range_free(tbl, bus_addr, npages, IOMMU_ERROR_CODE);
343	}	459	}
344		460
345	static int dma_4v_map_sg(struct device dev, struct scatterlist sglist,	461	static int dma_4v_map_sg(struct device dev, struct scatterlist sglist,
@@ -353,12 +469,17 @@ static int dma_4v_map_sg(struct device dev, struct scatterlist sglist, · 7 unmodified lines
353	unsigned long seg_boundary_size;	469	unsigned long seg_boundary_size;
354	int outcount, incount, i;	470	int outcount, incount, i;
355	struct iommu *iommu;	471	struct iommu *iommu;
		472	struct atu *atu;
		473	struct iommu_map_table *tbl;
		474	u64 mask;
356	unsigned long base_shift;	475	unsigned long base_shift;
357	long err;	476	long err;
358		477
359	BUG_ON(direction == DMA_NONE);	478	BUG_ON(direction == DMA_NONE);
360		479
361	iommu = dev->archdata.iommu;	480	iommu = dev->archdata.iommu;
		481	atu = iommu->atu;
		482
362	if (nelems == 0 \|\| !iommu)	483	if (nelems == 0 \|\| !iommu)
363	return 0;	484	return 0;
364		485
@@ -384,7 +505,15 @@ static int dma_4v_map_sg(struct device dev, struct scatterlist sglist, · 19 unmodified lines
384	max_seg_size = dma_get_max_seg_size(dev);	505	max_seg_size = dma_get_max_seg_size(dev);
385	seg_boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,	506	seg_boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
386	IO_PAGE_SIZE) >> IO_PAGE_SHIFT;	507	IO_PAGE_SIZE) >> IO_PAGE_SHIFT;
387	base_shift = iommu->tbl.table_map_base >> IO_PAGE_SHIFT;	508
		509	mask = *dev->dma_mask;
		510	if (mask <= DMA_BIT_MASK(32))
		511	tbl = &iommu->tbl;
		512	else
		513	tbl = &atu->tbl;
		514
		515	base_shift = tbl->table_map_base >> IO_PAGE_SHIFT;
		516
388	for_each_sg(sglist, s, nelems, i) {	517	for_each_sg(sglist, s, nelems, i) {
389	unsigned long paddr, npages, entry, out_entry = 0, slen;	518	unsigned long paddr, npages, entry, out_entry = 0, slen;
390		519
@@ -397,27 +526,26 @@ static int dma_4v_map_sg(struct device dev, struct scatterlist sglist, · 6 unmodified lines
397	/* Allocate iommu entries for that segment */	526	/* Allocate iommu entries for that segment */
398	paddr = (unsigned long) SG_ENT_PHYS_ADDRESS(s);	527	paddr = (unsigned long) SG_ENT_PHYS_ADDRESS(s);
399	npages = iommu_num_pages(paddr, slen, IO_PAGE_SIZE);	528	npages = iommu_num_pages(paddr, slen, IO_PAGE_SIZE);
400	entry = iommu_tbl_range_alloc(dev, &iommu->tbl, npages,	529	entry = iommu_tbl_range_alloc(dev, tbl, npages,
401	&handle, (unsigned long)(-1), 0);	530	&handle, (unsigned long)(-1), 0);
402		531
403	/* Handle failure */	532	/* Handle failure */
404	if (unlikely(entry == IOMMU_ERROR_CODE)) {	533	if (unlikely(entry == IOMMU_ERROR_CODE)) {
405	if (printk_ratelimit())	534	pr_err_ratelimited("iommu_alloc failed, iommu %p paddr %lx npages %lx\n",
406	printk(KERN_INFO "iommu_alloc failed, iommu %p paddr %lx"	535	tbl, paddr, npages);
407	" npages %lx\n", iommu, paddr, npages);
408	goto iommu_map_failed;	536	goto iommu_map_failed;
409	}	537	}
410		538
411	iommu_batch_new_entry(entry);	539	iommu_batch_new_entry(entry, mask);
412		540
413	/* Convert entry to a dma_addr_t */	541	/* Convert entry to a dma_addr_t */
414	dma_addr = iommu->tbl.table_map_base + (entry << IO_PAGE_SHIFT);	542	dma_addr = tbl->table_map_base + (entry << IO_PAGE_SHIFT);
415	dma_addr \|= (s->offset & ~IO_PAGE_MASK);	543	dma_addr \|= (s->offset & ~IO_PAGE_MASK);
416		544
417	/* Insert into HW table */	545	/* Insert into HW table */
418	paddr &= IO_PAGE_MASK;	546	paddr &= IO_PAGE_MASK;
419	while (npages--) {	547	while (npages--) {
420	err = iommu_batch_add(paddr);	548	err = iommu_batch_add(paddr, mask);
421	if (unlikely(err < 0L))	549	if (unlikely(err < 0L))
422	goto iommu_map_failed;	550	goto iommu_map_failed;
423	paddr += IO_PAGE_SIZE;	551	paddr += IO_PAGE_SIZE;
@@ -452,7 +580,7 @@ static int dma_4v_map_sg(struct device dev, struct scatterlist sglist, · 28 unmodified lines
452	dma_next = dma_addr + slen;	580	dma_next = dma_addr + slen;
453	}	581	}
454		582
455	err = iommu_batch_end();	583	err = iommu_batch_end(mask);
456		584
457	if (unlikely(err < 0L))	585	if (unlikely(err < 0L))
458	goto iommu_map_failed;	586	goto iommu_map_failed;
@@ -475,7 +603,7 @@ iommu_map_failed: · 16 unmodified lines
475	vaddr = s->dma_address & IO_PAGE_MASK;	603	vaddr = s->dma_address & IO_PAGE_MASK;
476	npages = iommu_num_pages(s->dma_address, s->dma_length,	604	npages = iommu_num_pages(s->dma_address, s->dma_length,
477	IO_PAGE_SIZE);	605	IO_PAGE_SIZE);
478	iommu_tbl_range_free(&iommu->tbl, vaddr, npages,	606	iommu_tbl_range_free(tbl, vaddr, npages,
479	IOMMU_ERROR_CODE);	607	IOMMU_ERROR_CODE);
480	/* XXX demap? XXX */	608	/* XXX demap? XXX */
481	s->dma_address = DMA_ERROR_CODE;	609	s->dma_address = DMA_ERROR_CODE;
@@ -496,13 +624,16 @@ static void dma_4v_unmap_sg(struct device dev, struct scatterlist sglist, · 14 unmodified lines
496	struct pci_pbm_info *pbm;	624	struct pci_pbm_info *pbm;
497	struct scatterlist *sg;	625	struct scatterlist *sg;
498	struct iommu *iommu;	626	struct iommu *iommu;
		627	struct atu *atu;
499	unsigned long flags, entry;	628	unsigned long flags, entry;
		629	unsigned long iotsb_num;
500	u32 devhandle;	630	u32 devhandle;
501		631
502	BUG_ON(direction == DMA_NONE);	632	BUG_ON(direction == DMA_NONE);
503		633
504	iommu = dev->archdata.iommu;	634	iommu = dev->archdata.iommu;
505	pbm = dev->archdata.host_controller;	635	pbm = dev->archdata.host_controller;
		636	atu = iommu->atu;
506	devhandle = pbm->devhandle;	637	devhandle = pbm->devhandle;
507		638
508	local_irq_save(flags);	639	local_irq_save(flags);
@@ -512,15 +643,24 @@ static void dma_4v_unmap_sg(struct device dev, struct scatterlist sglist, · 3 unmodified lines
512	dma_addr_t dma_handle = sg->dma_address;	643	dma_addr_t dma_handle = sg->dma_address;
513	unsigned int len = sg->dma_length;	644	unsigned int len = sg->dma_length;
514	unsigned long npages;	645	unsigned long npages;
515	struct iommu_map_table *tbl = &iommu->tbl;	646	struct iommu_map_table *tbl;
516	unsigned long shift = IO_PAGE_SHIFT;	647	unsigned long shift = IO_PAGE_SHIFT;
517		648
518	if (!len)	649	if (!len)
519	break;	650	break;
520	npages = iommu_num_pages(dma_handle, len, IO_PAGE_SIZE);	651	npages = iommu_num_pages(dma_handle, len, IO_PAGE_SIZE);
		652
		653	if (dma_handle <= DMA_BIT_MASK(32)) {
		654	iotsb_num = 0; /* we don't care for legacy iommu */
		655	tbl = &iommu->tbl;
		656	} else {
		657	iotsb_num = atu->iotsb->iotsb_num;
		658	tbl = &atu->tbl;
		659	}
521	entry = ((dma_handle - tbl->table_map_base) >> shift);	660	entry = ((dma_handle - tbl->table_map_base) >> shift);
522	dma_4v_iommu_demap(&devhandle, entry, npages);	661	dma_4v_iommu_demap(dev, devhandle, dma_handle, iotsb_num,
523	iommu_tbl_range_free(&iommu->tbl, dma_handle, npages,	662	entry, npages);
		663	iommu_tbl_range_free(tbl, dma_handle, npages,
524	IOMMU_ERROR_CODE);	664	IOMMU_ERROR_CODE);
525	sg = sg_next(sg);	665	sg = sg_next(sg);
526	}	666	}
@@ -581,6 +721,132 @@ static unsigned long probe_existing_entries(struct pci_pbm_info *pbm, · 54 unmodified lines
581	return cnt;	721	return cnt;
582	}	722	}
583		723
		724	static int pci_sun4v_atu_alloc_iotsb(struct pci_pbm_info *pbm)
		725	{
		726	struct atu *atu = pbm->iommu->atu;
		727	struct atu_iotsb *iotsb;
		728	void *table;
		729	u64 table_size;
		730	u64 iotsb_num;
		731	unsigned long order;
		732	unsigned long err;
		733
		734	iotsb = kzalloc(sizeof(*iotsb), GFP_KERNEL);
		735	if (!iotsb) {
		736	err = -ENOMEM;
		737	goto out_err;
		738	}
		739	atu->iotsb = iotsb;
		740
		741	/* calculate size of IOTSB */
		742	table_size = (atu->size / IO_PAGE_SIZE) * 8;
		743	order = get_order(table_size);
		744	table = (void *)__get_free_pages(GFP_KERNEL \| __GFP_ZERO, order);
		745	if (!table) {
		746	err = -ENOMEM;
		747	goto table_failed;
		748	}
		749	iotsb->table = table;
		750	iotsb->ra = __pa(table);
		751	iotsb->dvma_size = atu->size;
		752	iotsb->dvma_base = atu->base;
		753	iotsb->table_size = table_size;
		754	iotsb->page_size = IO_PAGE_SIZE;
		755
		756	/* configure and register IOTSB with HV */
		757	err = pci_sun4v_iotsb_conf(pbm->devhandle,
		758	iotsb->ra,
		759	iotsb->table_size,
		760	iotsb->page_size,
		761	iotsb->dvma_base,
		762	&iotsb_num);
		763	if (err) {
		764	pr_err(PFX "pci_iotsb_conf failed error: %ld\n", err);
		765	goto iotsb_conf_failed;
		766	}
		767	iotsb->iotsb_num = iotsb_num;
		768
		769	err = dma_4v_iotsb_bind(pbm->devhandle, iotsb_num, pbm->pci_bus);
		770	if (err) {
		771	pr_err(PFX "pci_iotsb_bind failed error: %ld\n", err);
		772	goto iotsb_conf_failed;
		773	}
		774
		775	return 0;
		776
		777	iotsb_conf_failed:
		778	free_pages((unsigned long)table, order);
		779	table_failed:
		780	kfree(iotsb);
		781	out_err:
		782	return err;
		783	}
		784
		785	static int pci_sun4v_atu_init(struct pci_pbm_info *pbm)
		786	{
		787	struct atu *atu = pbm->iommu->atu;
		788	unsigned long err;
		789	const u64 *ranges;
		790	u64 map_size, num_iotte;
		791	u64 dma_mask;
		792	const u32 *page_size;
		793	int len;
		794
		795	ranges = of_get_property(pbm->op->dev.of_node, "iommu-address-ranges",
		796	&len);
		797	if (!ranges) {
		798	pr_err(PFX "No iommu-address-ranges\n");
		799	return -EINVAL;
		800	}
		801
		802	page_size = of_get_property(pbm->op->dev.of_node, "iommu-pagesizes",
		803	NULL);
		804	if (!page_size) {
		805	pr_err(PFX "No iommu-pagesizes\n");
		806	return -EINVAL;
		807	}
		808
		809	/* There are 4 iommu-address-ranges supported. Each range is pair of
		810	* {base, size}. The ranges[0] and ranges[1] are 32bit address space
		811	* while ranges[2] and ranges[3] are 64bit space. We want to use 64bit
		812	* address ranges to support 64bit addressing. Because 'size' for
		813	* address ranges[2] and ranges[3] are same we can select either of
		814	* ranges[2] or ranges[3] for mapping. However due to 'size' is too
		815	* large for OS to allocate IOTSB we are using fix size 32G
		816	* (ATU_64_SPACE_SIZE) which is more than enough for all PCIe devices
		817	* to share.
		818	*/
		819	atu->ranges = (struct atu_ranges *)ranges;
		820	atu->base = atu->ranges[3].base;
		821	atu->size = ATU_64_SPACE_SIZE;
		822
		823	/* Create IOTSB */
		824	err = pci_sun4v_atu_alloc_iotsb(pbm);
		825	if (err) {
		826	pr_err(PFX "Error creating ATU IOTSB\n");
		827	return err;
		828	}
		829
		830	/* Create ATU iommu map.
		831	* One bit represents one iotte in IOTSB table.
		832	*/
		833	dma_mask = (roundup_pow_of_two(atu->size) - 1UL);
		834	num_iotte = atu->size / IO_PAGE_SIZE;
		835	map_size = num_iotte / 8;
		836	atu->tbl.table_map_base = atu->base;
		837	atu->dma_addr_mask = dma_mask;
		838	atu->tbl.map = kzalloc(map_size, GFP_KERNEL);
		839	if (!atu->tbl.map)
		840	return -ENOMEM;
		841
		842	iommu_tbl_pool_init(&atu->tbl, num_iotte, IO_PAGE_SHIFT,
		843	NULL, false /* no large_pool */,
		844	0 /* default npools */,
		845	false /* want span boundary checking */);
		846
		847	return 0;
		848	}
		849
584	static int pci_sun4v_iommu_init(struct pci_pbm_info *pbm)	850	static int pci_sun4v_iommu_init(struct pci_pbm_info *pbm)
585	{	851	{
586	static const u32 vdma_default[] = { 0x80000000, 0x80000000 };	852	static const u32 vdma_default[] = { 0x80000000, 0x80000000 };
@@ -918,6 +1184,18 @@ static int pci_sun4v_pbm_init(struct pci_pbm_info *pbm, · 331 unmodified lines
918		1184
919	pci_sun4v_scan_bus(pbm, &op->dev);	1185	pci_sun4v_scan_bus(pbm, &op->dev);
920		1186
		1187	/* if atu_init fails its not complete failure.
		1188	* we can still continue using legacy iommu.
		1189	*/
		1190	if (pbm->iommu->atu) {
		1191	err = pci_sun4v_atu_init(pbm);
		1192	if (err) {
		1193	kfree(pbm->iommu->atu);
		1194	pbm->iommu->atu = NULL;
		1195	pr_err(PFX "ATU init failed, err=%d\n", err);
		1196	}
		1197	}
		1198
921	pbm->next = pci_pbm_root;	1199	pbm->next = pci_pbm_root;
922	pci_pbm_root = pbm;	1200	pci_pbm_root = pbm;
923		1201
@@ -931,8 +1209,10 @@ static int pci_sun4v_probe(struct platform_device *op) · 7 unmodified lines
931	struct pci_pbm_info *pbm;	1209	struct pci_pbm_info *pbm;
932	struct device_node *dp;	1210	struct device_node *dp;
933	struct iommu *iommu;	1211	struct iommu *iommu;
		1212	struct atu *atu;
934	u32 devhandle;	1213	u32 devhandle;
935	int i, err = -ENODEV;	1214	int i, err = -ENODEV;
		1215	static bool hv_atu = true;
936		1216
937	dp = op->dev.of_node;	1217	dp = op->dev.of_node;
938		1218
@@ -954,6 +1234,19 @@ static int pci_sun4v_probe(struct platform_device *op) · 15 unmodified lines
954	pr_info(PFX "Registered hvapi major[%lu] minor[%lu]\n",	1234	pr_info(PFX "Registered hvapi major[%lu] minor[%lu]\n",
955	vpci_major, vpci_minor);	1235	vpci_major, vpci_minor);
956		1236
		1237	err = sun4v_hvapi_register(HV_GRP_ATU, vatu_major, &vatu_minor);
		1238	if (err) {
		1239	/* don't return an error if we fail to register the
		1240	* ATU group, but ATU hcalls won't be available.
		1241	*/
		1242	hv_atu = false;
		1243	pr_err(PFX "Could not register hvapi ATU err=%d\n",
		1244	err);
		1245	} else {
		1246	pr_info(PFX "Registered hvapi ATU major[%lu] minor[%lu]\n",
		1247	vatu_major, vatu_minor);
		1248	}
		1249
957	dma_ops = &sun4v_dma_ops;	1250	dma_ops = &sun4v_dma_ops;
958	}	1251	}
959		1252
@@ -991,6 +1284,14 @@ static int pci_sun4v_probe(struct platform_device *op) · 31 unmodified lines
991	}	1284	}
992		1285
993	pbm->iommu = iommu;	1286	pbm->iommu = iommu;
		1287	iommu->atu = NULL;
		1288	if (hv_atu) {
		1289	atu = kzalloc(sizeof(*atu), GFP_KERNEL);
		1290	if (!atu)
		1291	pr_err(PFX "Could not allocate atu\n");
		1292	else
		1293	iommu->atu = atu;
		1294	}
994		1295
995	err = pci_sun4v_pbm_init(pbm, op, devhandle);	1296	err = pci_sun4v_pbm_init(pbm, op, devhandle);
996	if (err)	1297	if (err)
@@ -1001,6 +1302,7 @@ static int pci_sun4v_probe(struct platform_device *op) · 4 unmodified lines
1001	return 0;	1302	return 0;
1002		1303
1003	out_free_iommu:	1304	out_free_iommu:
		1305	kfree(iommu->atu);
1004	kfree(pbm->iommu);	1306	kfree(pbm->iommu);
1005		1307
1006	out_free_controller:	1308	out_free_controller:

arch/sparc/kernel/pci_sun4v.h+21−0

@@ -89,4 +89,25 @@ unsigned long pci_sun4v_msg_setvalid(unsigned long devhandle, · 88 unmodified lines
89	unsigned long msinum,	89	unsigned long msinum,
90	unsigned long valid);	90	unsigned long valid);
91		91
		92	/* Sun4v HV IOMMU v2 APIs */
		93	unsigned long pci_sun4v_iotsb_conf(unsigned long devhandle,
		94	unsigned long ra,
		95	unsigned long table_size,
		96	unsigned long page_size,
		97	unsigned long dvma_base,
		98	u64 *iotsb_num);
		99	unsigned long pci_sun4v_iotsb_bind(unsigned long devhandle,
		100	unsigned long iotsb_num,
		101	unsigned int pci_device);
		102	unsigned long pci_sun4v_iotsb_map(unsigned long devhandle,
		103	unsigned long iotsb_num,
		104	unsigned long iotsb_index_iottes,
		105	unsigned long io_attributes,
		106	unsigned long io_page_list_pa,
		107	long *mapped);
		108	unsigned long pci_sun4v_iotsb_demap(unsigned long devhandle,
		109	unsigned long iotsb_num,
		110	unsigned long iotsb_index,
		111	unsigned long iottes,
		112	unsigned long *demapped);
92	#endif /* !(_PCI_SUN4V_H) */	113	#endif /* !(_PCI_SUN4V_H) */

arch/sparc/kernel/pci_sun4v_asm.S+68−0

@@ -360,3 +360,71 @@ ENTRY(pci_sun4v_msg_setvalid) · 359 unmodified lines
360	mov %o0, %o0	360	mov %o0, %o0
361	ENDPROC(pci_sun4v_msg_setvalid)	361	ENDPROC(pci_sun4v_msg_setvalid)
362		362
		363	/*
		364	* %o0: devhandle
		365	* %o1: r_addr
		366	* %o2: size
		367	* %o3: pagesize
		368	* %o4: virt
		369	* %o5: &iotsb_num/&iotsb_handle
		370	*
		371	* returns %o0: status
		372	* %o1: iotsb_num/iotsb_handle
		373	*/
		374	ENTRY(pci_sun4v_iotsb_conf)
		375	mov %o5, %g1
		376	mov HV_FAST_PCI_IOTSB_CONF, %o5
		377	ta HV_FAST_TRAP
		378	retl
		379	stx %o1, [%g1]
		380	ENDPROC(pci_sun4v_iotsb_conf)
		381
		382	/*
		383	* %o0: devhandle
		384	* %o1: iotsb_num/iotsb_handle
		385	* %o2: pci_device
		386	*
		387	* returns %o0: status
		388	*/
		389	ENTRY(pci_sun4v_iotsb_bind)
		390	mov HV_FAST_PCI_IOTSB_BIND, %o5
		391	ta HV_FAST_TRAP
		392	retl
		393	nop
		394	ENDPROC(pci_sun4v_iotsb_bind)
		395
		396	/*
		397	* %o0: devhandle
		398	* %o1: iotsb_num/iotsb_handle
		399	* %o2: index_count
		400	* %o3: iotte_attributes
		401	* %o4: io_page_list_p
		402	* %o5: &mapped
		403	*
		404	* returns %o0: status
		405	* %o1: #mapped
		406	*/
		407	ENTRY(pci_sun4v_iotsb_map)
		408	mov %o5, %g1
		409	mov HV_FAST_PCI_IOTSB_MAP, %o5
		410	ta HV_FAST_TRAP
		411	retl
		412	stx %o1, [%g1]
		413	ENDPROC(pci_sun4v_iotsb_map)
		414
		415	/*
		416	* %o0: devhandle
		417	* %o1: iotsb_num/iotsb_handle
		418	* %o2: iotsb_index
		419	* %o3: #iottes
		420	* %o4: &demapped
		421	*
		422	* returns %o0: status
		423	* %o1: #demapped
		424	*/
		425	ENTRY(pci_sun4v_iotsb_demap)
		426	mov HV_FAST_PCI_IOTSB_DEMAP, %o5
		427	ta HV_FAST_TRAP
		428	retl
		429	stx %o1, [%o4]
		430	ENDPROC(pci_sun4v_iotsb_demap)

arch/sparc/kernel/signal_32.c+2−2

@@ -89,7 +89,7 @@ asmlinkage void do_sigreturn(struct pt_regs *regs) · 88 unmodified lines
89	sf = (struct signal_frame __user *) regs->u_regs[UREG_FP];	89	sf = (struct signal_frame __user *) regs->u_regs[UREG_FP];
90		90
91	/* 1. Make sure we are not getting garbage from the user */	91	/* 1. Make sure we are not getting garbage from the user */
92	if (!invalid_frame_pointer(sf, sizeof(*sf)))	92	if (invalid_frame_pointer(sf, sizeof(*sf)))
93	goto segv_and_exit;	93	goto segv_and_exit;
94		94
95	if (get_user(ufp, &sf->info.si_regs.u_regs[UREG_FP]))	95	if (get_user(ufp, &sf->info.si_regs.u_regs[UREG_FP]))
@@ -150,7 +150,7 @@ asmlinkage void do_rt_sigreturn(struct pt_regs *regs) · 54 unmodified lines
150		150
151	synchronize_user_stack();	151	synchronize_user_stack();
152	sf = (struct rt_signal_frame __user *) regs->u_regs[UREG_FP];	152	sf = (struct rt_signal_frame __user *) regs->u_regs[UREG_FP];
153	if (!invalid_frame_pointer(sf, sizeof(*sf)))	153	if (invalid_frame_pointer(sf, sizeof(*sf)))
154	goto segv;	154	goto segv;
155		155
156	if (get_user(ufp, &sf->regs.u_regs[UREG_FP]))	156	if (get_user(ufp, &sf->regs.u_regs[UREG_FP]))

arch/sparc/mm/init_64.c+64−7

@@ -802,8 +802,10 @@ struct mdesc_mblock { · 801 unmodified lines
802	};	802	};
803	static struct mdesc_mblock *mblocks;	803	static struct mdesc_mblock *mblocks;
804	static int num_mblocks;	804	static int num_mblocks;
		805	static int find_numa_node_for_addr(unsigned long pa,
		806	struct node_mem_mask *pnode_mask);
805		807
806	static unsigned long ra_to_pa(unsigned long addr)	808	static unsigned long __init ra_to_pa(unsigned long addr)
807	{	809	{
808	int i;	810	int i;
809		811
@@ -819,8 +821,11 @@ static unsigned long ra_to_pa(unsigned long addr) · 9 unmodified lines
819	return addr;	821	return addr;
820	}	822	}
821		823
822	static int find_node(unsigned long addr)	824	static int __init find_node(unsigned long addr)
823	{	825	{
		826	static bool search_mdesc = true;
		827	static struct node_mem_mask last_mem_mask = { ~0UL, ~0UL };
		828	static int last_index;
824	int i;	829	int i;
825		830
826	addr = ra_to_pa(addr);	831	addr = ra_to_pa(addr);
@@ -830,13 +835,30 @@ static int find_node(unsigned long addr) · 3 unmodified lines
830	if ((addr & p->mask) == p->val)	835	if ((addr & p->mask) == p->val)
831	return i;	836	return i;
832	}	837	}
833	/* The following condition has been observed on LDOM guests.*/	838	/* The following condition has been observed on LDOM guests because
834	WARN_ONCE(1, "find_node: A physical address doesn't match a NUMA node"	839	* node_masks only contains the best latency mask and value.
835	" rule. Some physical memory will be owned by node 0.");	840	* LDOM guest's mdesc can contain a single latency group to
836	return 0;	841	* cover multiple address range. Print warning message only if the
		842	* address cannot be found in node_masks nor mdesc.
		843	*/
		844	if ((search_mdesc) &&
		845	((addr & last_mem_mask.mask) != last_mem_mask.val)) {
		846	/* find the available node in the mdesc */
		847	last_index = find_numa_node_for_addr(addr, &last_mem_mask);
		848	numadbg("find_node: latency group for address 0x%lx is %d\n",
		849	addr, last_index);
		850	if ((last_index < 0) \|\| (last_index >= num_node_masks)) {
		851	/* WARN_ONCE() and use default group 0 */
		852	WARN_ONCE(1, "find_node: A physical address doesn't match a NUMA node rule. Some physical memory will be owned by node 0.");
		853	search_mdesc = false;
		854	last_index = 0;
		855	}
		856	}
		857
		858	return last_index;
837	}	859	}
838		860
839	static u64 memblock_nid_range(u64 start, u64 end, int *nid)	861	static u64 __init memblock_nid_range(u64 start, u64 end, int *nid)
840	{	862	{
841	*nid = find_node(start);	863	*nid = find_node(start);
842	start += PAGE_SIZE;	864	start += PAGE_SIZE;
@@ -1160,6 +1182,41 @@ int __node_distance(int from, int to) · 317 unmodified lines
1160	return numa_latency[from][to];	1182	return numa_latency[from][to];
1161	}	1183	}
1162		1184
		1185	static int find_numa_node_for_addr(unsigned long pa,
		1186	struct node_mem_mask *pnode_mask)
		1187	{
		1188	struct mdesc_handle *md = mdesc_grab();
		1189	u64 node, arc;
		1190	int i = 0;
		1191
		1192	node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups");
		1193	if (node == MDESC_NODE_NULL)
		1194	goto out;
		1195
		1196	mdesc_for_each_node_by_name(md, node, "group") {
		1197	mdesc_for_each_arc(arc, md, node, MDESC_ARC_TYPE_FWD) {
		1198	u64 target = mdesc_arc_target(md, arc);
		1199	struct mdesc_mlgroup *m = find_mlgroup(target);
		1200
		1201	if (!m)
		1202	continue;
		1203	if ((pa & m->mask) == m->match) {
		1204	if (pnode_mask) {
		1205	pnode_mask->mask = m->mask;
		1206	pnode_mask->val = m->match;
		1207	}
		1208	mdesc_release(md);
		1209	return i;
		1210	}
		1211	}
		1212	i++;
		1213	}
		1214
		1215	out:
		1216	mdesc_release(md);
		1217	return -1;
		1218	}
		1219
1163	static int __init find_best_numa_node_for_mlgroup(struct mdesc_mlgroup *grp)	1220	static int __init find_best_numa_node_for_mlgroup(struct mdesc_mlgroup *grp)
1164	{	1221	{
1165	int i;	1222	int i;

arch/x86/kvm/irq_comm.c+27−31

@@ -156,6 +156,16 @@ int kvm_set_msi(struct kvm_kernel_irq_routing_entry *e, · 155 unmodified lines
156	}	156	}
157		157
158		158
		159	static int kvm_hv_set_sint(struct kvm_kernel_irq_routing_entry *e,
		160	struct kvm *kvm, int irq_source_id, int level,
		161	bool line_status)
		162	{
		163	if (!level)
		164	return -1;
		165
		166	return kvm_hv_synic_set_irq(kvm, e->hv_sint.vcpu, e->hv_sint.sint);
		167	}
		168
159	int kvm_arch_set_irq_inatomic(struct kvm_kernel_irq_routing_entry *e,	169	int kvm_arch_set_irq_inatomic(struct kvm_kernel_irq_routing_entry *e,
160	struct kvm *kvm, int irq_source_id, int level,	170	struct kvm *kvm, int irq_source_id, int level,
161	bool line_status)	171	bool line_status)
@@ -163,18 +173,26 @@ int kvm_arch_set_irq_inatomic(struct kvm_kernel_irq_routing_entry *e, · 1 unmodified line
163	struct kvm_lapic_irq irq;	173	struct kvm_lapic_irq irq;
164	int r;	174	int r;
165		175
166	if (unlikely(e->type != KVM_IRQ_ROUTING_MSI))	176	switch (e->type) {
167	return -EWOULDBLOCK;	177	case KVM_IRQ_ROUTING_HV_SINT:
		178	return kvm_hv_set_sint(e, kvm, irq_source_id, level,
		179	line_status);
168		180
169	if (kvm_msi_route_invalid(kvm, e))	181	case KVM_IRQ_ROUTING_MSI:
170	return -EINVAL;	182	if (kvm_msi_route_invalid(kvm, e))
		183	return -EINVAL;
171		184
172	kvm_set_msi_irq(kvm, e, &irq);	185	kvm_set_msi_irq(kvm, e, &irq);
173		186
174	if (kvm_irq_delivery_to_apic_fast(kvm, NULL, &irq, &r, NULL))	187	if (kvm_irq_delivery_to_apic_fast(kvm, NULL, &irq, &r, NULL))
175	return r;	188	return r;
176	else	189	break;
177	return -EWOULDBLOCK;	190
		191	default:
		192	break;
		193	}
		194
		195	return -EWOULDBLOCK;
178	}	196	}
179		197
180	int kvm_request_irq_source_id(struct kvm *kvm)	198	int kvm_request_irq_source_id(struct kvm *kvm)
@@ -254,16 +272,6 @@ void kvm_fire_mask_notifiers(struct kvm *kvm, unsigned irqchip, unsigned pin, · 73 unmodified lines
254	srcu_read_unlock(&kvm->irq_srcu, idx);	272	srcu_read_unlock(&kvm->irq_srcu, idx);
255	}	273	}
256		274
257	static int kvm_hv_set_sint(struct kvm_kernel_irq_routing_entry *e,
258	struct kvm *kvm, int irq_source_id, int level,
259	bool line_status)
260	{
261	if (!level)
262	return -1;
263
264	return kvm_hv_synic_set_irq(kvm, e->hv_sint.vcpu, e->hv_sint.sint);
265	}
266
267	int kvm_set_routing_entry(struct kvm *kvm,	275	int kvm_set_routing_entry(struct kvm *kvm,
268	struct kvm_kernel_irq_routing_entry *e,	276	struct kvm_kernel_irq_routing_entry *e,
269	const struct kvm_irq_routing_entry *ue)	277	const struct kvm_irq_routing_entry *ue)
@@ -423,18 +431,6 @@ void kvm_scan_ioapic_routes(struct kvm_vcpu *vcpu, · 153 unmodified lines
423	srcu_read_unlock(&kvm->irq_srcu, idx);	431	srcu_read_unlock(&kvm->irq_srcu, idx);
424	}	432	}
425		433
426	int kvm_arch_set_irq(struct kvm_kernel_irq_routing_entry irq, struct kvm kvm,
427	int irq_source_id, int level, bool line_status)
428	{
429	switch (irq->type) {
430	case KVM_IRQ_ROUTING_HV_SINT:
431	return kvm_hv_set_sint(irq, kvm, irq_source_id, level,
432	line_status);
433	default:
434	return -EWOULDBLOCK;
435	}
436	}
437
438	void kvm_arch_irq_routing_update(struct kvm *kvm)	434	void kvm_arch_irq_routing_update(struct kvm *kvm)
439	{	435	{
440	kvm_hv_irq_routing_update(kvm);	436	kvm_hv_irq_routing_update(kvm);

arch/x86/kvm/x86.c+34−13

 	struct kvm_shared_msrs *locals
 		= container_of(urn, struct kvm_shared_msrs, urn);
 	struct kvm_shared_msr_values *values;
+	unsigned long flags;
+	/*
+	 * Disabling irqs at this point since the following code could be
+	 * interrupted and executed through kvm_arch_hardware_disable()
+	 */
+	local_irq_save(flags);
+	if (locals->registered) {
+		locals->registered = false;
+		user_return_notifier_unregister(urn);
+	}
+	local_irq_restore(flags);
 	for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
 		values = &locals->values[slot];
 		if (values->host != values->curr) {
 			values->curr = values->host;
 		}
 	}
-	locals->registered = false;
-	user_return_notifier_unregister(urn);
 }
 static void shared_msr_update(unsigned slot, u32 msr)
 static u64 __get_kvmclock_ns(struct kvm *kvm)
 {
-	struct kvm_vcpu *vcpu = kvm_get_vcpu(kvm, 0);
 	struct kvm_arch *ka = &kvm->arch;
-	s64 ns;
+	struct pvclock_vcpu_time_info hv_clock;
-	if (vcpu->arch.hv_clock.flags & PVCLOCK_TSC_STABLE_BIT) {
+	spin_lock(&ka->pvclock_gtod_sync_lock);
-		u64 tsc = kvm_read_l1_tsc(vcpu, rdtsc());
+	if (!ka->use_master_clock) {
-		ns = __pvclock_read_cycles(&vcpu->arch.hv_clock, tsc);
+		spin_unlock(&ka->pvclock_gtod_sync_lock);
-	} else {
+		return ktime_get_boot_ns() + ka->kvmclock_offset;
-		ns = ktime_get_boot_ns() + ka->kvmclock_offset;
 	}
-	return ns;
+	hv_clock.tsc_timestamp = ka->master_cycle_now;
+	hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
+	spin_unlock(&ka->pvclock_gtod_sync_lock);
+	kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
+			   &hv_clock.tsc_shift,
+			   &hv_clock.tsc_to_system_mul);
+	return __pvclock_read_cycles(&hv_clock, rdtsc());
 }
 u64 get_kvmclock_ns(struct kvm *kvm)
 	case KVM_CAP_PIT_STATE2:
 	case KVM_CAP_SET_IDENTITY_MAP_ADDR:
 	case KVM_CAP_XEN_HVM:
-	case KVM_CAP_ADJUST_CLOCK:
 	case KVM_CAP_VCPU_EVENTS:
 	case KVM_CAP_HYPERV:
 	case KVM_CAP_HYPERV_VAPIC:
 #endif
 		r = 1;
 		break;
+	case KVM_CAP_ADJUST_CLOCK:
+		r = KVM_CLOCK_TSC_STABLE;
+		break;
 	case KVM_CAP_X86_SMM:
 		/* SMBASE is usually relocated above 1M on modern chipsets,
 		 * and SMM handlers might indeed rely on 4G segment limits,
 	};
 	case KVM_SET_VAPIC_ADDR: {
 		struct kvm_vapic_addr va;
+		int idx;
 		r = -EINVAL;
 		if (!lapic_in_kernel(vcpu))
 		r = -EFAULT;
 		if (copy_from_user(&va, argp, sizeof va))
 			goto out;
+		idx = srcu_read_lock(&vcpu->kvm->srcu);
 		r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
+		srcu_read_unlock(&vcpu->kvm->srcu, idx);
 		break;
 	}
 	case KVM_X86_SETUP_MCE: {
 		struct kvm_clock_data user_ns;
 		u64 now_ns;
-		now_ns = get_kvmclock_ns(kvm);
+		local_irq_disable();
+		now_ns = __get_kvmclock_ns(kvm);
 		user_ns.clock = now_ns;
-		user_ns.flags = 0;
+		user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
+		local_irq_enable();
 		memset(&user_ns.pad, 0, sizeof(user_ns.pad));
 		r = -EFAULT;

arch/x86/purgatory/Makefile+1−0

@@ -16,6 +16,7 @@ KCOV_INSTRUMENT := n · 15 unmodified lines
16		16
17	KBUILD_CFLAGS := -fno-strict-aliasing -Wall -Wstrict-prototypes -fno-zero-initialized-in-bss -fno-builtin -ffreestanding -c -MD -Os -mcmodel=large	17	KBUILD_CFLAGS := -fno-strict-aliasing -Wall -Wstrict-prototypes -fno-zero-initialized-in-bss -fno-builtin -ffreestanding -c -MD -Os -mcmodel=large
18	KBUILD_CFLAGS += -m$(BITS)	18	KBUILD_CFLAGS += -m$(BITS)
		19	KBUILD_CFLAGS += $(call cc-option,-fno-PIE)
19		20
20	$(obj)/purgatory.ro: $(PURGATORY_OBJS) FORCE	21	$(obj)/purgatory.ro: $(PURGATORY_OBJS) FORCE
21	$(call if_changed,ld)	22	$(call if_changed,ld)

arch/xtensa/include/uapi/asm/unistd.h+8−1

 #define __NR_pwritev2				347
 __SYSCALL(347, sys_pwritev2, 6)
-#define __NR_syscall_count			348
+#define __NR_pkey_mprotect			348
+__SYSCALL(348, sys_pkey_mprotect, 4)
+#define __NR_pkey_alloc				349
+__SYSCALL(349, sys_pkey_alloc, 2)
+#define __NR_pkey_free				350
+__SYSCALL(350, sys_pkey_free, 1)
+#define __NR_syscall_count			351
 /*
  * sysxtensa syscall handler

arch/xtensa/kernel/time.c+7−7

 {
 	of_clk_init(NULL);
 #ifdef CONFIG_XTENSA_CALIBRATE_CCOUNT
-	printk("Calibrating CPU frequency ");
+	pr_info("Calibrating CPU frequency ");
 	calibrate_ccount();
-	printk("%d.%02d MHz\n", (int)ccount_freq/1000000,
+	pr_cont("%d.%02d MHz\n",
-			(int)(ccount_freq/10000)%100);
+		(int)ccount_freq / 1000000,
+		(int)(ccount_freq / 10000) % 100);
 #else
 	ccount_freq = CONFIG_XTENSA_CPU_CLOCK*1000000UL;
 #endif
 void calibrate_delay(void)
 {
 	loops_per_jiffy = ccount_freq / HZ;
-	printk("Calibrating delay loop (skipped)... "
+	pr_info("Calibrating delay loop (skipped)... %lu.%02lu BogoMIPS preset\n",
-	       "%lu.%02lu BogoMIPS preset\n",
+		loops_per_jiffy / (1000000 / HZ),
-	       loops_per_jiffy/(1000000/HZ),
+		(loops_per_jiffy / (10000 / HZ)) % 100);
-	       (loops_per_jiffy/(10000/HZ)) % 100);
 }
 #endif

arch/xtensa/kernel/traps.c+22−52

@@ -465,26 +465,25 @@ void show_regs(struct pt_regs * regs) · 464 unmodified lines
465		465
466	for (i = 0; i < 16; i++) {	466	for (i = 0; i < 16; i++) {
467	if ((i % 8) == 0)	467	if ((i % 8) == 0)
468	printk(KERN_INFO "a%02d:", i);	468	pr_info("a%02d:", i);
469	printk(KERN_CONT " %08lx", regs->areg[i]);	469	pr_cont(" %08lx", regs->areg[i]);
470	}	470	}
471	printk(KERN_CONT "\n");	471	pr_cont("\n");
472		472	pr_info("pc: %08lx, ps: %08lx, depc: %08lx, excvaddr: %08lx\n",
473	printk("pc: %08lx, ps: %08lx, depc: %08lx, excvaddr: %08lx\n",	473	regs->pc, regs->ps, regs->depc, regs->excvaddr);
474	regs->pc, regs->ps, regs->depc, regs->excvaddr);	474	pr_info("lbeg: %08lx, lend: %08lx lcount: %08lx, sar: %08lx\n",
475	printk("lbeg: %08lx, lend: %08lx lcount: %08lx, sar: %08lx\n",	475	regs->lbeg, regs->lend, regs->lcount, regs->sar);
476	regs->lbeg, regs->lend, regs->lcount, regs->sar);
477	if (user_mode(regs))	476	if (user_mode(regs))
478	printk("wb: %08lx, ws: %08lx, wmask: %08lx, syscall: %ld\n",	477	pr_cont("wb: %08lx, ws: %08lx, wmask: %08lx, syscall: %ld\n",
479	regs->windowbase, regs->windowstart, regs->wmask,	478	regs->windowbase, regs->windowstart, regs->wmask,
480	regs->syscall);	479	regs->syscall);
481	}	480	}
482		481
483	static int show_trace_cb(struct stackframe frame, void data)	482	static int show_trace_cb(struct stackframe frame, void data)
484	{	483	{
485	if (kernel_text_address(frame->pc)) {	484	if (kernel_text_address(frame->pc)) {
486	printk(" [<%08lx>] ", frame->pc);	485	pr_cont(" [<%08lx>]", frame->pc);
487	print_symbol("%s\n", frame->pc);	486	print_symbol(" %s\n", frame->pc);
488	}	487	}
489	return 0;	488	return 0;
490	}	489	}
@@ -494,19 +493,13 @@ void show_trace(struct task_struct task, unsigned long sp) · 3 unmodified lines
494	if (!sp)	493	if (!sp)
495	sp = stack_pointer(task);	494	sp = stack_pointer(task);
496		495
497	printk("Call Trace:");	496	pr_info("Call Trace:\n");
498	#ifdef CONFIG_KALLSYMS
499	printk("\n");
500	#endif
501	walk_stackframe(sp, show_trace_cb, NULL);	497	walk_stackframe(sp, show_trace_cb, NULL);
502	printk("\n");	498	#ifndef CONFIG_KALLSYMS
		499	pr_cont("\n");
		500	#endif
503	}	501	}
504		502
505	/*
506	* This routine abuses get_user()/put_user() to reference pointers
507	* with at least a bit of error checking ...
508	*/
509
510	static int kstack_depth_to_print = 24;	503	static int kstack_depth_to_print = 24;
511		504
512	void show_stack(struct task_struct task, unsigned long sp)	505	void show_stack(struct task_struct task, unsigned long sp)
@@ -518,52 +511,29 @@ void show_stack(struct task_struct task, unsigned long sp) · 5 unmodified lines
518	sp = stack_pointer(task);	511	sp = stack_pointer(task);
519	stack = sp;	512	stack = sp;
520		513
521	printk("\nStack: ");	514	pr_info("Stack:\n");
522		515
523	for (i = 0; i < kstack_depth_to_print; i++) {	516	for (i = 0; i < kstack_depth_to_print; i++) {
524	if (kstack_end(sp))	517	if (kstack_end(sp))
525	break;	518	break;
526	if (i && ((i % 8) == 0))	519	pr_cont(" %08lx", *sp++);
527	printk("\n ");	520	if (i % 8 == 7)
528	printk("%08lx ", *sp++);	521	pr_cont("\n");
529	}	522	}
530	printk("\n");
531	show_trace(task, stack);	523	show_trace(task, stack);
532	}	524	}
533		525
534	void show_code(unsigned int *pc)
535	{
536	long i;
537
538	printk("\nCode:");
539
540	for(i = -3 ; i < 6 ; i++) {
541	unsigned long insn;
542	if (__get_user(insn, pc + i)) {
543	printk(" (Bad address in pc)\n");
544	break;
545	}
546	printk("%c%08lx%c",(i?' ':'<'),insn,(i?' ':'>'));
547	}
548	}
549
550	DEFINE_SPINLOCK(die_lock);	526	DEFINE_SPINLOCK(die_lock);
551		527
552	void die(const char * str, struct pt_regs * regs, long err)	528	void die(const char * str, struct pt_regs * regs, long err)
553	{	529	{
554	static int die_counter;	530	static int die_counter;
555	int nl = 0;
556		531
557	console_verbose();	532	console_verbose();
558	spin_lock_irq(&die_lock);	533	spin_lock_irq(&die_lock);
559		534
560	printk("%s: sig: %ld [#%d]\n", str, err, ++die_counter);	535	pr_info("%s: sig: %ld [#%d]%s\n", str, err, ++die_counter,
561	#ifdef CONFIG_PREEMPT	536	IS_ENABLED(CONFIG_PREEMPT) ? " PREEMPT" : "");
562	printk("PREEMPT ");
563	nl = 1;
564	#endif
565	if (nl)
566	printk("\n");
567	show_regs(regs);	537	show_regs(regs);
568	if (!user_mode(regs))	538	if (!user_mode(regs))
569	show_stack(NULL, (unsigned long*)regs->areg[1]);	539	show_stack(NULL, (unsigned long*)regs->areg[1]);

crypto/algif_hash.c+10−7

 	ahash_request_set_crypt(&ctx->req, NULL, ctx->result, 0);
-	if (ctx->more) {
+	if (!result) {
+		err = af_alg_wait_for_completion(
+				crypto_ahash_init(&ctx->req),
+				&ctx->completion);
+		if (err)
+			goto unlock;
+	}
+	if (!result || ctx->more) {
 		ctx->more = 0;
 		err = af_alg_wait_for_completion(crypto_ahash_final(&ctx->req),
 						 &ctx->completion);
 		if (err)
 			goto unlock;
-	} else if (!result) {
-		err = af_alg_wait_for_completion(
-				crypto_ahash_digest(&ctx->req),
-				&ctx->completion);
 	}
 	err = memcpy_to_msg(msg, ctx->result, len);
-	hash_free_result(sk, ctx);
 unlock:
+	hash_free_result(sk, ctx);
 	release_sock(sk);
 	return err ?: len;

drivers/acpi/acpica/tbfadt.c+4−6

 	u32 i;
 	/*
-	 * For ACPI 1.0 FADTs (revision 1), ensure that reserved fields which
+	 * For ACPI 1.0 FADTs (revision 1 or 2), ensure that reserved fields which
 	 * should be zero are indeed zero. This will workaround BIOSs that
 	 * inadvertently place values in these fields.
 	 *
 	 * The ACPI 1.0 reserved fields that will be zeroed are the bytes located
 	 * at offset 45, 55, 95, and the word located at offset 109, 110.
 	 *
-	 * Note: The FADT revision value is unreliable because of BIOS errors.
+	 * Note: The FADT revision value is unreliable. Only the length can be
-	 * The table length is instead used as the final word on the version.
+	 * trusted.
-	 *
-	 * Note: FADT revision 3 is the ACPI 2.0 version of the FADT.
 	 */
-	if (acpi_gbl_FADT.header.length <= ACPI_FADT_V3_SIZE) {
+	if (acpi_gbl_FADT.header.length <= ACPI_FADT_V2_SIZE) {
 		acpi_gbl_FADT.preferred_profile = 0;
 		acpi_gbl_FADT.pstate_control = 0;
 		acpi_gbl_FADT.cst_control = 0;

drivers/char/ipmi/bt-bmc.c+2−2

@@ -484,7 +484,7 @@ static int bt_bmc_remove(struct platform_device *pdev) · 483 unmodified lines
484	}	484	}
485		485
486	static const struct of_device_id bt_bmc_match[] = {	486	static const struct of_device_id bt_bmc_match[] = {
487	{ .compatible = "aspeed,ast2400-bt-bmc" },	487	{ .compatible = "aspeed,ast2400-ibt-bmc" },
488	{ },	488	{ },
489	};	489	};
490		490
@@ -502,4 +502,4 @@ module_platform_driver(bt_bmc_driver); · 11 unmodified lines
502	MODULE_DEVICE_TABLE(of, bt_bmc_match);	502	MODULE_DEVICE_TABLE(of, bt_bmc_match);
503	MODULE_LICENSE("GPL");	503	MODULE_LICENSE("GPL");
504	MODULE_AUTHOR("Alistair Popple <alistair@popple.id.au>");	504	MODULE_AUTHOR("Alistair Popple <alistair@popple.id.au>");
505	MODULE_DESCRIPTION("Linux device interface to the BT interface");	505	MODULE_DESCRIPTION("Linux device interface to the IPMI BT interface");

drivers/crypto/caam/caamalg.c+10−1

 		}
 		buf = it_page + it->offset;
-		len = min(tlen, it->length);
+		len = min_t(size_t, tlen, it->length);
 		print_hex_dump(level, prefix_str, prefix_type, rowsize,
 			       groupsize, buf, len, ascii);
 		tlen -= len;
 		if (!aes_inst && (alg_sel == OP_ALG_ALGSEL_AES))
 				continue;
+		/*
+		 * Check support for AES modes not available
+		 * on LP devices.
+		 */
+		if ((cha_vid & CHA_ID_LS_AES_MASK) == CHA_ID_LS_AES_LP)
+			if ((alg->class1_alg_type & OP_ALG_AAI_MASK) ==
+			     OP_ALG_AAI_XTS)
+				continue;
 		t_alg = caam_alg_alloc(alg);
 		if (IS_ERR(t_alg)) {
 			err = PTR_ERR(t_alg);

drivers/dma/Kconfig+1−0

@@ -306,6 +306,7 @@ config MMP_TDMA · 305 unmodified lines
306	depends on ARCH_MMP \|\| COMPILE_TEST	306	depends on ARCH_MMP \|\| COMPILE_TEST
307	select DMA_ENGINE	307	select DMA_ENGINE
308	select MMP_SRAM if ARCH_MMP	308	select MMP_SRAM if ARCH_MMP
		309	select GENERIC_ALLOCATOR
309	help	310	help
310	Support the MMP Two-Channel DMA engine.	311	Support the MMP Two-Channel DMA engine.
311	This engine used for MMP Audio DMA and pxa910 SQU.	312	This engine used for MMP Audio DMA and pxa910 SQU.

drivers/dma/cppi41.c+26−5

 		while (val) {
 			u32 desc, len;
+			int error;
+			error = pm_runtime_get(cdd->ddev.dev);
+			if (error < 0)
+				dev_err(cdd->ddev.dev, "%s pm runtime get: %i\n",
+					__func__, error);
 			q_num = __fls(val);
 			val &= ~(1 << q_num);
 			dma_cookie_complete(&c->txd);
 			dmaengine_desc_get_callback_invoke(&c->txd, NULL);
-			/* Paired with cppi41_dma_issue_pending */
 			pm_runtime_mark_last_busy(cdd->ddev.dev);
 			pm_runtime_put_autosuspend(cdd->ddev.dev);
 		}
 	int error;
 	error = pm_runtime_get_sync(cdd->ddev.dev);
-	if (error < 0)
+	if (error < 0) {
+		dev_err(cdd->ddev.dev, "%s pm runtime get: %i\n",
+			__func__, error);
+		pm_runtime_put_noidle(cdd->ddev.dev);
 		return error;
+	}
 	dma_cookie_init(chan);
 	dma_async_tx_descriptor_init(&c->txd, chan);
 	int error;
 	error = pm_runtime_get_sync(cdd->ddev.dev);
-	if (error < 0)
+	if (error < 0) {
+		pm_runtime_put_noidle(cdd->ddev.dev);
 		return;
+	}
 	WARN_ON(!list_empty(&cdd->pending));
 	struct cppi41_dd *cdd = c->cdd;
 	int error;
-	/* PM runtime paired with dmaengine_desc_get_callback_invoke */
 	error = pm_runtime_get(cdd->ddev.dev);
 	if ((error != -EINPROGRESS) && error < 0) {
+		pm_runtime_put_noidle(cdd->ddev.dev);
 		dev_err(cdd->ddev.dev, "Failed to pm_runtime_get: %i\n",
 			error);
 		push_desc_queue(c);
 	else
 		pending_desc(c);
+	pm_runtime_mark_last_busy(cdd->ddev.dev);
+	pm_runtime_put_autosuspend(cdd->ddev.dev);
 }
 static u32 get_host_pd0(u32 length)
 	deinit_cppi41(dev, cdd);
 err_init_cppi:
 	pm_runtime_dont_use_autosuspend(dev);
-	pm_runtime_put_sync(dev);
 err_get_sync:
+	pm_runtime_put_sync(dev);
 	pm_runtime_disable(dev);
 	iounmap(cdd->usbss_mem);
 	iounmap(cdd->ctrl_mem);
 static int cppi41_dma_remove(struct platform_device *pdev)
 {
 	struct cppi41_dd *cdd = platform_get_drvdata(pdev);
+	int error;
+	error = pm_runtime_get_sync(&pdev->dev);
+	if (error < 0)
+		dev_err(&pdev->dev, "%s could not pm_runtime_get: %i\n",
+			__func__, error);
 	of_dma_controller_free(pdev->dev.of_node);
 	dma_async_device_unregister(&cdd->ddev);

drivers/dma/edma.c+1−0

@@ -1628,6 +1628,7 @@ static int edma_alloc_chan_resources(struct dma_chan *chan) · 1627 unmodified lines
1628	if (echan->slot[0] < 0) {	1628	if (echan->slot[0] < 0) {
1629	dev_err(dev, "Entry slot allocation failed for channel %u\n",	1629	dev_err(dev, "Entry slot allocation failed for channel %u\n",
1630	EDMA_CHAN_SLOT(echan->ch_num));	1630	EDMA_CHAN_SLOT(echan->ch_num));
		1631	ret = echan->slot[0];
1631	goto err_slot;	1632	goto err_slot;
1632	}	1633	}
1633		1634

drivers/dma/sun6i-dma.c+1−1

@@ -578,7 +578,7 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_memcpy( · 577 unmodified lines
578		578
579	burst = convert_burst(8);	579	burst = convert_burst(8);
580	width = convert_buswidth(DMA_SLAVE_BUSWIDTH_4_BYTES);	580	width = convert_buswidth(DMA_SLAVE_BUSWIDTH_4_BYTES);
581	v_lli->cfg \|= DMA_CHAN_CFG_SRC_DRQ(DRQ_SDRAM) \|	581	v_lli->cfg = DMA_CHAN_CFG_SRC_DRQ(DRQ_SDRAM) \|
582	DMA_CHAN_CFG_DST_DRQ(DRQ_SDRAM) \|	582	DMA_CHAN_CFG_DST_DRQ(DRQ_SDRAM) \|
583	DMA_CHAN_CFG_DST_LINEAR_MODE \|	583	DMA_CHAN_CFG_DST_LINEAR_MODE \|
584	DMA_CHAN_CFG_SRC_LINEAR_MODE \|	584	DMA_CHAN_CFG_SRC_LINEAR_MODE \|

drivers/gpio/Kconfig+0−4

@@ -22,10 +22,6 @@ menuconfig GPIOLIB · 21 unmodified lines
22		22
23	if GPIOLIB	23	if GPIOLIB
24		24
25	config GPIO_DEVRES
26	def_bool y
27	depends on HAS_IOMEM
28
29	config OF_GPIO	25	config OF_GPIO
30	def_bool y	26	def_bool y
31	depends on OF	27	depends on OF

drivers/gpio/Makefile+1−1

@@ -2,7 +2,7 @@ · 1 unmodified line
2		2
3	ccflags-$(CONFIG_DEBUG_GPIO) += -DDEBUG	3	ccflags-$(CONFIG_DEBUG_GPIO) += -DDEBUG
4		4
5	obj-$(CONFIG_GPIO_DEVRES) += devres.o	5	obj-$(CONFIG_GPIOLIB) += devres.o
6	obj-$(CONFIG_GPIOLIB) += gpiolib.o	6	obj-$(CONFIG_GPIOLIB) += gpiolib.o
7	obj-$(CONFIG_GPIOLIB) += gpiolib-legacy.o	7	obj-$(CONFIG_GPIOLIB) += gpiolib-legacy.o
8	obj-$(CONFIG_OF_GPIO) += gpiolib-of.o	8	obj-$(CONFIG_OF_GPIO) += gpiolib-of.o

drivers/gpio/gpio-pca953x.c+2−2

 	bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
-	memcpy(reg_val, chip->reg_output, NBANK(chip));
 	mutex_lock(&chip->i2c_lock);
+	memcpy(reg_val, chip->reg_output, NBANK(chip));
 	for (bank = 0; bank < NBANK(chip); bank++) {
 		bank_mask = mask[bank / sizeof(*mask)] >>
 			   ((bank % sizeof(*mask)) * 8);
 		if (bank_mask) {
 			bank_val = bits[bank / sizeof(*bits)] >>
 				  ((bank % sizeof(*bits)) * 8);
+			bank_val &= bank_mask;
 			reg_val[bank] = (reg_val[bank] & ~bank_mask) | bank_val;
 		}
 	}
 	if (client->irq && irq_base != -1
 			&& (chip->driver_data & PCA_INT)) {
 		ret = pca953x_read_regs(chip,
 					chip->regs->input, chip->irq_stat);
 		if (ret)

drivers/gpio/gpio-tc3589x.c+1−1

@@ -97,7 +97,7 @@ static int tc3589x_gpio_get_direction(struct gpio_chip *chip, · 96 unmodified lines
97	if (ret < 0)	97	if (ret < 0)
98	return ret;	98	return ret;
99		99
100	return !!(ret & BIT(pos));	100	return !(ret & BIT(pos));
101	}	101	}
102		102
103	static int tc3589x_gpio_set_single_ended(struct gpio_chip *chip,	103	static int tc3589x_gpio_set_single_ended(struct gpio_chip *chip,

drivers/gpio/gpiolib.c+5−2

 	if (IS_ERR(desc))
 		return PTR_ERR(desc);
-	/* Flush direction if something changed behind our back */
+	/*
-	if (chip->get_direction) {
+	 * If it's fast: flush the direction setting if something changed
+	 * behind our back
+	 */
+	if (!chip->can_sleep && chip->get_direction) {
 		int dir = chip->get_direction(chip, offset);
 		if (dir)

drivers/gpu/drm/amd/amdgpu/amdgpu.h+1−0

@@ -459,6 +459,7 @@ struct amdgpu_bo { · 458 unmodified lines
459	u64 metadata_flags;	459	u64 metadata_flags;
460	void *metadata;	460	void *metadata;
461	u32 metadata_size;	461	u32 metadata_size;
		462	unsigned prime_shared_count;
462	/* list of all virtual address to which this bo	463	/* list of all virtual address to which this bo
463	* is associated to	464	* is associated to
464	*/	465	*/

drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c+1−1

@@ -132,7 +132,7 @@ static int amdgpu_bo_list_set(struct amdgpu_device *adev, · 131 unmodified lines
132	entry->priority = min(info[i].bo_priority,	132	entry->priority = min(info[i].bo_priority,
133	AMDGPU_BO_LIST_MAX_PRIORITY);	133	AMDGPU_BO_LIST_MAX_PRIORITY);
134	entry->tv.bo = &entry->robj->tbo;	134	entry->tv.bo = &entry->robj->tbo;
135	entry->tv.shared = true;	135	entry->tv.shared = !entry->robj->prime_shared_count;
136		136
137	if (entry->robj->prefered_domains == AMDGPU_GEM_DOMAIN_GDS)	137	if (entry->robj->prefered_domains == AMDGPU_GEM_DOMAIN_GDS)
138	gds_obj = entry->robj;	138	gds_obj = entry->robj;

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c+7−20

@@ -658,12 +658,10 @@ static bool amdgpu_vpost_needed(struct amdgpu_device *adev) · 657 unmodified lines
658	return false;	658	return false;
659		659
660	if (amdgpu_passthrough(adev)) {	660	if (amdgpu_passthrough(adev)) {
661	/* for FIJI: In whole GPU pass-through virtualization case	661	/* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
662	* old smc fw won't clear some registers (e.g. MEM_SIZE, BIOS_SCRATCH)	662	* some old smc fw still need driver do vPost otherwise gpu hang, while
663	* so amdgpu_card_posted return false and driver will incorrectly skip vPost.	663	* those smc fw version above 22.15 doesn't have this flaw, so we force
664	* but if we force vPost do in pass-through case, the driver reload will hang.	664	* vpost executed for smc version below 22.15
665	* whether doing vPost depends on amdgpu_card_posted if smc version is above
666	* 00160e00 for FIJI.
667	*/	665	*/
668	if (adev->asic_type == CHIP_FIJI) {	666	if (adev->asic_type == CHIP_FIJI) {
669	int err;	667	int err;
@@ -674,22 +672,11 @@ static bool amdgpu_vpost_needed(struct amdgpu_device *adev) · 4 unmodified lines
674	return true;	672	return true;
675		673
676	fw_ver = ((uint32_t )adev->pm.fw->data + 69);	674	fw_ver = ((uint32_t )adev->pm.fw->data + 69);
677	if (fw_ver >= 0x00160e00)	675	if (fw_ver < 0x00160e00)
678	return !amdgpu_card_posted(adev);	676	return true;
679	}	677	}
680	} else {
681	/* in bare-metal case, amdgpu_card_posted return false
682	* after system reboot/boot, and return true if driver
683	* reloaded.
684	* we shouldn't do vPost after driver reload otherwise GPU
685	* could hang.
686	*/
687	if (amdgpu_card_posted(adev))
688	return false;
689	}	678	}
690		679	return !amdgpu_card_posted(adev);
691	/* we assume vPost is neede for all other cases */
692	return true;
693	}	680	}
694		681
695	/**	682	/**

drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c+19−1

 	if (ret)
 		return ERR_PTR(ret);
+	bo->prime_shared_count = 1;
 	return &bo->gem_base;
 }
 int amdgpu_gem_prime_pin(struct drm_gem_object *obj)
 {
 	struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
-	int ret = 0;
+	long ret = 0;
 	ret = amdgpu_bo_reserve(bo, false);
 	if (unlikely(ret != 0))
 		return ret;
+	/*
+	 * Wait for all shared fences to complete before we switch to future
+	 * use of exclusive fence on this prime shared bo.
+	 */
+	ret = reservation_object_wait_timeout_rcu(bo->tbo.resv, true, false,
+						  MAX_SCHEDULE_TIMEOUT);
+	if (unlikely(ret < 0)) {
+		DRM_DEBUG_PRIME("Fence wait failed: %li\n", ret);
+		amdgpu_bo_unreserve(bo);
+		return ret;
+	}
 	/* pin buffer into GTT */
 	ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT, NULL);
+	if (likely(ret == 0))
+		bo->prime_shared_count++;
 	amdgpu_bo_unreserve(bo);
 	return ret;
 }
 		return;
 	amdgpu_bo_unpin(bo);
+	if (bo->prime_shared_count)
+		bo->prime_shared_count--;
 	amdgpu_bo_unreserve(bo);
 }

drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c+0−2

@@ -1469,8 +1469,6 @@ static int smu7_get_evv_voltages(struct pp_hwmgr *hwmgr) · 1468 unmodified lines
1469	table_info->vddgfx_lookup_table, vv_id, &sclk)) {	1469	table_info->vddgfx_lookup_table, vv_id, &sclk)) {
1470	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,	1470	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1471	PHM_PlatformCaps_ClockStretcher)) {	1471	PHM_PlatformCaps_ClockStretcher)) {
1472	if (table_info == NULL)
1473	return -EINVAL;
1474	sclk_table = table_info->vdd_dep_on_sclk;	1472	sclk_table = table_info->vdd_dep_on_sclk;
1475		1473
1476	for (j = 1; j < sclk_table->count; j++) {	1474	for (j = 1; j < sclk_table->count; j++) {

drivers/gpu/drm/arc/arcpgu_hdmi.c+17−142

@@ -14,170 +14,45 @@ · 13 unmodified lines
14	*	14	*
15	*/	15	*/
16		16
17	#include <drm/drm_crtc_helper.h>	17	#include <drm/drm_crtc.h>
18	#include <drm/drm_encoder_slave.h>	18	#include <drm/drm_encoder_slave.h>
19	#include <drm/drm_atomic_helper.h>
20		19
21	#include "arcpgu.h"	20	#include "arcpgu.h"
22		21
23	struct arcpgu_drm_connector {
24	struct drm_connector connector;
25	struct drm_encoder_slave *encoder_slave;
26	};
27
28	static int arcpgu_drm_connector_get_modes(struct drm_connector *connector)
29	{
30	const struct drm_encoder_slave_funcs *sfuncs;
31	struct drm_encoder_slave *slave;
32	struct arcpgu_drm_connector *con =
33	container_of(connector, struct arcpgu_drm_connector, connector);
34
35	slave = con->encoder_slave;
36	if (slave == NULL) {
37	dev_err(connector->dev->dev,
38	"connector_get_modes: cannot find slave encoder for connector\n");
39	return 0;
40	}
41
42	sfuncs = slave->slave_funcs;
43	if (sfuncs->get_modes == NULL)
44	return 0;
45
46	return sfuncs->get_modes(&slave->base, connector);
47	}
48
49	static enum drm_connector_status
50	arcpgu_drm_connector_detect(struct drm_connector *connector, bool force)
51	{
52	enum drm_connector_status status = connector_status_unknown;
53	const struct drm_encoder_slave_funcs *sfuncs;
54	struct drm_encoder_slave *slave;
55
56	struct arcpgu_drm_connector *con =
57	container_of(connector, struct arcpgu_drm_connector, connector);
58
59	slave = con->encoder_slave;
60	if (slave == NULL) {
61	dev_err(connector->dev->dev,
62	"connector_detect: cannot find slave encoder for connector\n");
63	return status;
64	}
65
66	sfuncs = slave->slave_funcs;
67	if (sfuncs && sfuncs->detect)
68	return sfuncs->detect(&slave->base, connector);
69
70	dev_err(connector->dev->dev, "connector_detect: could not detect slave funcs\n");
71	return status;
72	}
73
74	static void arcpgu_drm_connector_destroy(struct drm_connector *connector)
75	{
76	drm_connector_unregister(connector);
77	drm_connector_cleanup(connector);
78	}
79
80	static const struct drm_connector_helper_funcs
81	arcpgu_drm_connector_helper_funcs = {
82	.get_modes = arcpgu_drm_connector_get_modes,
83	};
84
85	static const struct drm_connector_funcs arcpgu_drm_connector_funcs = {
86	.dpms = drm_helper_connector_dpms,
87	.reset = drm_atomic_helper_connector_reset,
88	.detect = arcpgu_drm_connector_detect,
89	.fill_modes = drm_helper_probe_single_connector_modes,
90	.destroy = arcpgu_drm_connector_destroy,
91	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
92	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
93	};
94
95	static struct drm_encoder_helper_funcs arcpgu_drm_encoder_helper_funcs = {
96	.dpms = drm_i2c_encoder_dpms,
97	.mode_fixup = drm_i2c_encoder_mode_fixup,
98	.mode_set = drm_i2c_encoder_mode_set,
99	.prepare = drm_i2c_encoder_prepare,
100	.commit = drm_i2c_encoder_commit,
101	.detect = drm_i2c_encoder_detect,
102	};
103
104	static struct drm_encoder_funcs arcpgu_drm_encoder_funcs = {	22	static struct drm_encoder_funcs arcpgu_drm_encoder_funcs = {
105	.destroy = drm_encoder_cleanup,	23	.destroy = drm_encoder_cleanup,
106	};	24	};
107		25
108	int arcpgu_drm_hdmi_init(struct drm_device drm, struct device_node np)	26	int arcpgu_drm_hdmi_init(struct drm_device drm, struct device_node np)
109	{	27	{
110	struct arcpgu_drm_connector *arcpgu_connector;	28	struct drm_encoder *encoder;
111	struct drm_i2c_encoder_driver *driver;	29	struct drm_bridge *bridge;
112	struct drm_encoder_slave *encoder;	30
113	struct drm_connector *connector;	31	int ret = 0;
114	struct i2c_client *i2c_slave;
115	int ret;
116		32
117	encoder = devm_kzalloc(drm->dev, sizeof(*encoder), GFP_KERNEL);	33	encoder = devm_kzalloc(drm->dev, sizeof(*encoder), GFP_KERNEL);
118	if (encoder == NULL)	34	if (encoder == NULL)
119	return -ENOMEM;	35	return -ENOMEM;
120		36
121	i2c_slave = of_find_i2c_device_by_node(np);	37	/* Locate drm bridge from the hdmi encoder DT node */
122	if (!i2c_slave \|\| !i2c_get_clientdata(i2c_slave)) {	38	bridge = of_drm_find_bridge(np);
123	dev_err(drm->dev, "failed to find i2c slave encoder\n");	39	if (!bridge)
124	return -EPROBE_DEFER;
125	}
126
127	if (i2c_slave->dev.driver == NULL) {
128	dev_err(drm->dev, "failed to find i2c slave driver\n");
129	return -EPROBE_DEFER;	40	return -EPROBE_DEFER;
130	}
131		41
132	driver =	42	encoder->possible_crtcs = 1;
133	to_drm_i2c_encoder_driver(to_i2c_driver(i2c_slave->dev.driver));	43	encoder->possible_clones = 0;
134	ret = driver->encoder_init(i2c_slave, drm, encoder);	44	ret = drm_encoder_init(drm, encoder, &arcpgu_drm_encoder_funcs,
135	if (ret) {
136	dev_err(drm->dev, "failed to initialize i2c encoder slave\n");
137	return ret;
138	}
139
140	encoder->base.possible_crtcs = 1;
141	encoder->base.possible_clones = 0;
142	ret = drm_encoder_init(drm, &encoder->base, &arcpgu_drm_encoder_funcs,
143	DRM_MODE_ENCODER_TMDS, NULL);	45	DRM_MODE_ENCODER_TMDS, NULL);
144	if (ret)	46	if (ret)
145	return ret;	47	return ret;
146		48
147	drm_encoder_helper_add(&encoder->base,	49	/* Link drm_bridge to encoder */
148	&arcpgu_drm_encoder_helper_funcs);	50	bridge->encoder = encoder;
149		51	encoder->bridge = bridge;
150	arcpgu_connector = devm_kzalloc(drm->dev, sizeof(*arcpgu_connector),
151	GFP_KERNEL);
152	if (!arcpgu_connector) {
153	ret = -ENOMEM;
154	goto error_encoder_cleanup;
155	}
156
157	connector = &arcpgu_connector->connector;
158	drm_connector_helper_add(connector, &arcpgu_drm_connector_helper_funcs);
159	ret = drm_connector_init(drm, connector, &arcpgu_drm_connector_funcs,
160	DRM_MODE_CONNECTOR_HDMIA);
161	if (ret < 0) {
162	dev_err(drm->dev, "failed to initialize drm connector\n");
163	goto error_encoder_cleanup;
164	}
165		52
166	ret = drm_mode_connector_attach_encoder(connector, &encoder->base);	53	ret = drm_bridge_attach(drm, bridge);
167	if (ret < 0) {	54	if (ret)
168	dev_err(drm->dev, "could not attach connector to encoder\n");	55	drm_encoder_cleanup(encoder);
169	drm_connector_unregister(connector);
170	goto error_connector_cleanup;
171	}
172
173	arcpgu_connector->encoder_slave = encoder;
174
175	return 0;
176
177	error_connector_cleanup:
178	drm_connector_cleanup(connector);
179		56
180	error_encoder_cleanup:
181	drm_encoder_cleanup(&encoder->base);
182	return ret;	57	return ret;
183	}	58	}

drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c+11−2

 static void fsl_dcu_drm_crtc_atomic_flush(struct drm_crtc *crtc,
 					  struct drm_crtc_state *old_crtc_state)
 {
+	struct drm_device *dev = crtc->dev;
+	struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
 	struct drm_pending_vblank_event *event = crtc->state->event;
+	regmap_write(fsl_dev->regmap,
+		     DCU_UPDATE_MODE, DCU_UPDATE_MODE_READREG);
 	if (event) {
 		crtc->state->event = NULL;
 	}
 }
-static void fsl_dcu_drm_disable_crtc(struct drm_crtc *crtc)
+static void fsl_dcu_drm_crtc_atomic_disable(struct drm_crtc *crtc,
+					struct drm_crtc_state *old_crtc_state)
 {
 	struct drm_device *dev = crtc->dev;
 	struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
+	/* always disable planes on the CRTC */
+	drm_atomic_helper_disable_planes_on_crtc(old_crtc_state, true);
 	drm_crtc_vblank_off(crtc);
 	regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,
 }
 static const struct drm_crtc_helper_funcs fsl_dcu_drm_crtc_helper_funcs = {
+	.atomic_disable = fsl_dcu_drm_crtc_atomic_disable,
 	.atomic_flush = fsl_dcu_drm_crtc_atomic_flush,
-	.disable = fsl_dcu_drm_disable_crtc,
 	.enable = fsl_dcu_drm_crtc_enable,
 	.mode_set_nofb = fsl_dcu_drm_crtc_mode_set_nofb,
 };

drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c+0−4

 	regmap_write(fsl_dev->regmap, DCU_INT_STATUS, 0);
 	regmap_write(fsl_dev->regmap, DCU_INT_MASK, ~0);
-	regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
-		     DCU_UPDATE_MODE_READREG);
 	return ret;
 }
 		drm_handle_vblank(dev, 0);
 	regmap_write(fsl_dev->regmap, DCU_INT_STATUS, int_status);
-	regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
-		     DCU_UPDATE_MODE_READREG);
 	return IRQ_HANDLED;
 }

drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c+0−5

 			     DCU_LAYER_POST_SKIP(0) |
 			     DCU_LAYER_PRE_SKIP(0));
 	}
-	regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,
-			   DCU_MODE_DCU_MODE_MASK,
-			   DCU_MODE_DCU_MODE(DCU_MODE_NORMAL));
-	regmap_write(fsl_dev->regmap,
-		     DCU_UPDATE_MODE, DCU_UPDATE_MODE_READREG);
 	return;
 }

drivers/gpu/drm/i915/i915_gem_execbuffer.c+8−0

 	return ctx;
 }
+static bool gpu_write_needs_clflush(struct drm_i915_gem_object *obj)
+{
+	return !(obj->cache_level == I915_CACHE_NONE ||
+		 obj->cache_level == I915_CACHE_WT);
+}
 void i915_vma_move_to_active(struct i915_vma *vma,
 			     struct drm_i915_gem_request *req,
 			     unsigned int flags)
 		/* update for the implicit flush after a batch */
 		obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
+		if (!obj->cache_dirty && gpu_write_needs_clflush(obj))
+			obj->cache_dirty = true;
 	}
 	if (flags & EXEC_OBJECT_NEEDS_FENCE)

drivers/gpu/drm/i915/intel_bios.c+22−8

 	if (!child)
 		return;
-	aux_channel = child->raw[25];
+	aux_channel = child->common.aux_channel;
 	ddc_pin = child->common.ddc_pin;
 	is_dvi = child->common.device_type & DEVICE_TYPE_TMDS_DVI_SIGNALING;
 	return false;
 }
-bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port)
+static bool child_dev_is_dp_dual_mode(const union child_device_config *p_child,
+				      enum port port)
 {
 	static const struct {
 		u16 dp, hdmi;
 		[PORT_D] = { DVO_PORT_DPD, DVO_PORT_HDMID, },
 		[PORT_E] = { DVO_PORT_DPE, DVO_PORT_HDMIE, },
 	};
-	int i;
 	if (port == PORT_A || port >= ARRAY_SIZE(port_mapping))
 		return false;
-	if (!dev_priv->vbt.child_dev_num)
+	if ((p_child->common.device_type & DEVICE_TYPE_DP_DUAL_MODE_BITS) !=
+	    (DEVICE_TYPE_DP_DUAL_MODE & DEVICE_TYPE_DP_DUAL_MODE_BITS))
 		return false;
+	if (p_child->common.dvo_port == port_mapping[port].dp)
+		return true;
+	/* Only accept a HDMI dvo_port as DP++ if it has an AUX channel */
+	if (p_child->common.dvo_port == port_mapping[port].hdmi &&
+	    p_child->common.aux_channel != 0)
+		return true;
+	return false;
+}
+bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv,
+				     enum port port)
+{
+	int i;
 	for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
 		const union child_device_config *p_child =
 			&dev_priv->vbt.child_dev[i];
-		if ((p_child->common.dvo_port == port_mapping[port].dp ||
+		if (child_dev_is_dp_dual_mode(p_child, port))
-		     p_child->common.dvo_port == port_mapping[port].hdmi) &&
-		    (p_child->common.device_type & DEVICE_TYPE_DP_DUAL_MODE_BITS) ==
-		    (DEVICE_TYPE_DP_DUAL_MODE & DEVICE_TYPE_DP_DUAL_MODE_BITS))
 			return true;
 	}

drivers/gpu/drm/i915/intel_dp.c+0−10

 intel_dp_detect(struct drm_connector *connector, bool force)
 {
 	struct intel_dp *intel_dp = intel_attached_dp(connector);
-	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
-	struct intel_encoder *intel_encoder = &intel_dig_port->base;
 	enum drm_connector_status status = connector->status;
 	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
 		      connector->base.id, connector->name);
-	if (intel_dp->is_mst) {
-		/* MST devices are disconnected from a monitor POV */
-		intel_dp_unset_edid(intel_dp);
-		if (intel_encoder->type != INTEL_OUTPUT_EDP)
-			intel_encoder->type = INTEL_OUTPUT_DP;
-		return connector_status_disconnected;
-	}
 	/* If full detect is not performed yet, do a full detect */
 	if (!intel_dp->detect_done)
 		status = intel_dp_long_pulse(intel_dp->attached_connector);

drivers/gpu/drm/i915/intel_sprite.c+1−1

@@ -358,7 +358,7 @@ vlv_update_plane(struct drm_plane *dplane, · 357 unmodified lines
358	int plane = intel_plane->plane;	358	int plane = intel_plane->plane;
359	u32 sprctl;	359	u32 sprctl;
360	u32 sprsurf_offset, linear_offset;	360	u32 sprsurf_offset, linear_offset;
361	unsigned int rotation = dplane->state->rotation;	361	unsigned int rotation = plane_state->base.rotation;
362	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;	362	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
363	int crtc_x = plane_state->base.dst.x1;	363	int crtc_x = plane_state->base.dst.x1;
364	int crtc_y = plane_state->base.dst.y1;	364	int crtc_y = plane_state->base.dst.y1;

drivers/gpu/drm/i915/intel_vbt_defs.h+2−1

@@ -280,7 +280,8 @@ struct common_child_dev_config { · 279 unmodified lines
280	u8 dp_support:1;	280	u8 dp_support:1;
281	u8 tmds_support:1;	281	u8 tmds_support:1;
282	u8 support_reserved:5;	282	u8 support_reserved:5;
283	u8 not_common3[12];	283	u8 aux_channel;
		284	u8 not_common3[11];
284	u8 iboost_level;	285	u8 iboost_level;
285	} __packed;	286	} __packed;
286		287

drivers/gpu/drm/mediatek/mtk_disp_ovl.c+1−0

@@ -80,6 +80,7 @@ static void mtk_ovl_enable_vblank(struct mtk_ddp_comp *comp, · 79 unmodified lines
80	ddp_comp);	80	ddp_comp);
81		81
82	priv->crtc = crtc;	82	priv->crtc = crtc;
		83	writel(0x0, comp->regs + DISP_REG_OVL_INTSTA);
83	writel_relaxed(OVL_FME_CPL_INT, comp->regs + DISP_REG_OVL_INTEN);	84	writel_relaxed(OVL_FME_CPL_INT, comp->regs + DISP_REG_OVL_INTEN);
84	}	85	}
85		86

drivers/gpu/drm/mediatek/mtk_dpi.c+7−2

 	unsigned long pll_rate;
 	unsigned int factor;
+	/* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */
 	pix_rate = 1000UL * mode->clock;
-	if (mode->clock <= 74000)
+	if (mode->clock <= 27000)
+		factor = 16 * 3;
+	else if (mode->clock <= 84000)
 		factor = 8 * 3;
-	else
+	else if (mode->clock <= 167000)
 		factor = 4 * 3;
+	else
+		factor = 2 * 3;
 	pll_rate = pix_rate * factor;
 	dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n",

drivers/gpu/drm/mediatek/mtk_hdmi.c+11−6

 	phy_power_on(hdmi->phy);
 	mtk_hdmi_aud_output_config(hdmi, mode);
-	mtk_hdmi_setup_audio_infoframe(hdmi);
-	mtk_hdmi_setup_avi_infoframe(hdmi, mode);
-	mtk_hdmi_setup_spd_infoframe(hdmi, "mediatek", "On-chip HDMI");
-	if (mode->flags & DRM_MODE_FLAG_3D_MASK)
-		mtk_hdmi_setup_vendor_specific_infoframe(hdmi, mode);
 	mtk_hdmi_hw_vid_black(hdmi, false);
 	mtk_hdmi_hw_aud_unmute(hdmi);
 	mtk_hdmi_hw_send_av_unmute(hdmi);
 	hdmi->powered = true;
 }
+static void mtk_hdmi_send_infoframe(struct mtk_hdmi *hdmi,
+				    struct drm_display_mode *mode)
+{
+	mtk_hdmi_setup_audio_infoframe(hdmi);
+	mtk_hdmi_setup_avi_infoframe(hdmi, mode);
+	mtk_hdmi_setup_spd_infoframe(hdmi, "mediatek", "On-chip HDMI");
+	if (mode->flags & DRM_MODE_FLAG_3D_MASK)
+		mtk_hdmi_setup_vendor_specific_infoframe(hdmi, mode);
+}
 static void mtk_hdmi_bridge_enable(struct drm_bridge *bridge)
 {
 	struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
 	clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);
 	clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]);
 	phy_power_on(hdmi->phy);
+	mtk_hdmi_send_infoframe(hdmi, &hdmi->mode);
 	hdmi->enabled = true;
 }

drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c+30−12

 	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
 	unsigned int pre_div;
 	unsigned int div;
+	unsigned int pre_ibias;
+	unsigned int hdmi_ibias;
+	unsigned int imp_en;
 	dev_dbg(hdmi_phy->dev, "%s: %lu Hz, parent: %lu Hz\n", __func__,
 		rate, parent_rate);
 			  (0x1 << PLL_BR_SHIFT),
 			  RG_HDMITX_PLL_BP | RG_HDMITX_PLL_BC |
 			  RG_HDMITX_PLL_BR);
-	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, RG_HDMITX_PRD_IMP_EN);
+	if (rate < 165000000) {
+		mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3,
+					RG_HDMITX_PRD_IMP_EN);
+		pre_ibias = 0x3;
+		imp_en = 0x0;
+		hdmi_ibias = hdmi_phy->ibias;
+	} else {
+		mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON3,
+				      RG_HDMITX_PRD_IMP_EN);
+		pre_ibias = 0x6;
+		imp_en = 0xf;
+		hdmi_ibias = hdmi_phy->ibias_up;
+	}
 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4,
-			  (0x3 << PRD_IBIAS_CLK_SHIFT) |
+			  (pre_ibias << PRD_IBIAS_CLK_SHIFT) |
-			  (0x3 << PRD_IBIAS_D2_SHIFT) |
+			  (pre_ibias << PRD_IBIAS_D2_SHIFT) |
-			  (0x3 << PRD_IBIAS_D1_SHIFT) |
+			  (pre_ibias << PRD_IBIAS_D1_SHIFT) |
-			  (0x3 << PRD_IBIAS_D0_SHIFT),
+			  (pre_ibias << PRD_IBIAS_D0_SHIFT),
 			  RG_HDMITX_PRD_IBIAS_CLK |
 			  RG_HDMITX_PRD_IBIAS_D2 |
 			  RG_HDMITX_PRD_IBIAS_D1 |
 			  RG_HDMITX_PRD_IBIAS_D0);
 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON3,
-			  (0x0 << DRV_IMP_EN_SHIFT), RG_HDMITX_DRV_IMP_EN);
+			  (imp_en << DRV_IMP_EN_SHIFT),
+			  RG_HDMITX_DRV_IMP_EN);
 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6,
 			  (hdmi_phy->drv_imp_clk << DRV_IMP_CLK_SHIFT) |
 			  (hdmi_phy->drv_imp_d2 << DRV_IMP_D2_SHIFT) |
 			  RG_HDMITX_DRV_IMP_CLK | RG_HDMITX_DRV_IMP_D2 |
 			  RG_HDMITX_DRV_IMP_D1 | RG_HDMITX_DRV_IMP_D0);
 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON5,
-			  (hdmi_phy->ibias << DRV_IBIAS_CLK_SHIFT) |
+			  (hdmi_ibias << DRV_IBIAS_CLK_SHIFT) |
-			  (hdmi_phy->ibias << DRV_IBIAS_D2_SHIFT) |
+			  (hdmi_ibias << DRV_IBIAS_D2_SHIFT) |
-			  (hdmi_phy->ibias << DRV_IBIAS_D1_SHIFT) |
+			  (hdmi_ibias << DRV_IBIAS_D1_SHIFT) |
-			  (hdmi_phy->ibias << DRV_IBIAS_D0_SHIFT),
+			  (hdmi_ibias << DRV_IBIAS_D0_SHIFT),
-			  RG_HDMITX_DRV_IBIAS_CLK | RG_HDMITX_DRV_IBIAS_D2 |
+			  RG_HDMITX_DRV_IBIAS_CLK |
-			  RG_HDMITX_DRV_IBIAS_D1 | RG_HDMITX_DRV_IBIAS_D0);
+			  RG_HDMITX_DRV_IBIAS_D2 |
+			  RG_HDMITX_DRV_IBIAS_D1 |
+			  RG_HDMITX_DRV_IBIAS_D0);
 	return 0;
 }

drivers/gpu/drm/sun4i/sun4i_drv.c+2−2

@@ -142,9 +142,9 @@ static int sun4i_drv_bind(struct device *dev) · 141 unmodified lines
142		142
143	/* Create our layers */	143	/* Create our layers */
144	drv->layers = sun4i_layers_init(drm);	144	drv->layers = sun4i_layers_init(drm);
145	if (!drv->layers) {	145	if (IS_ERR(drv->layers)) {
146	dev_err(drm->dev, "Couldn't create the planes\n");	146	dev_err(drm->dev, "Couldn't create the planes\n");
147	ret = -EINVAL;	147	ret = PTR_ERR(drv->layers);
148	goto free_drm;	148	goto free_drm;
149	}	149	}
150		150

drivers/gpu/drm/sun4i/sun4i_rgb.c+8−12

 	DRM_DEBUG_DRIVER("Enabling RGB output\n");
-	if (!IS_ERR(tcon->panel)) {
+	if (!IS_ERR(tcon->panel))
 		drm_panel_prepare(tcon->panel);
-		drm_panel_enable(tcon->panel);
-	}
-	/* encoder->bridge can be NULL; drm_bridge_enable checks for it */
-	drm_bridge_enable(encoder->bridge);
 	sun4i_tcon_channel_enable(tcon, 0);
+	if (!IS_ERR(tcon->panel))
+		drm_panel_enable(tcon->panel);
 }
 static void sun4i_rgb_encoder_disable(struct drm_encoder *encoder)
 	DRM_DEBUG_DRIVER("Disabling RGB output\n");
-	sun4i_tcon_channel_disable(tcon, 0);
+	if (!IS_ERR(tcon->panel))
+		drm_panel_disable(tcon->panel);
-	/* encoder->bridge can be NULL; drm_bridge_disable checks for it */
+	sun4i_tcon_channel_disable(tcon, 0);
-	drm_bridge_disable(encoder->bridge);
-	if (!IS_ERR(tcon->panel)) {
+	if (!IS_ERR(tcon->panel))
-		drm_panel_disable(tcon->panel);
 		drm_panel_unprepare(tcon->panel);
-	}
 }
 static void sun4i_rgb_encoder_mode_set(struct drm_encoder *encoder,

drivers/i2c/Kconfig+0−1

@@ -59,7 +59,6 @@ config I2C_CHARDEV · 58 unmodified lines
59		59
60	config I2C_MUX	60	config I2C_MUX
61	tristate "I2C bus multiplexing support"	61	tristate "I2C bus multiplexing support"
62	depends on HAS_IOMEM
63	help	62	help
64	Say Y here if you want the I2C core to support the ability to	63	Say Y here if you want the I2C core to support the ability to
65	handle multiplexed I2C bus topologies, by presenting each	64	handle multiplexed I2C bus topologies, by presenting each

drivers/i2c/busses/i2c-digicolor.c+1−1

@@ -347,7 +347,7 @@ static int dc_i2c_probe(struct platform_device *pdev) · 346 unmodified lines
347		347
348	ret = i2c_add_adapter(&i2c->adap);	348	ret = i2c_add_adapter(&i2c->adap);
349	if (ret < 0) {	349	if (ret < 0) {
350	clk_unprepare(i2c->clk);	350	clk_disable_unprepare(i2c->clk);
351	return ret;	351	return ret;
352	}	352	}
353		353

drivers/i2c/muxes/Kconfig+1−0

@@ -63,6 +63,7 @@ config I2C_MUX_PINCTRL · 62 unmodified lines
63		63
64	config I2C_MUX_REG	64	config I2C_MUX_REG
65	tristate "Register-based I2C multiplexer"	65	tristate "Register-based I2C multiplexer"
		66	depends on HAS_IOMEM
66	help	67	help
67	If you say yes to this option, support will be included for a	68	If you say yes to this option, support will be included for a
68	register based I2C multiplexer. This driver provides access to	69	register based I2C multiplexer. This driver provides access to

drivers/i2c/muxes/i2c-demux-pinctrl.c+20−2

@@ -69,10 +69,28 @@ static int i2c_demux_activate_master(struct i2c_demux_pinctrl_priv *priv, u32 ne · 68 unmodified lines
69	goto err_with_revert;	69	goto err_with_revert;
70	}	70	}
71		71
72	p = devm_pinctrl_get_select(adap->dev.parent, priv->bus_name);	72	/*
		73	* Check if there are pinctrl states at all. Note: we cant' use
		74	* devm_pinctrl_get_select() because we need to distinguish between
		75	* the -ENODEV from devm_pinctrl_get() and pinctrl_lookup_state().
		76	*/
		77	p = devm_pinctrl_get(adap->dev.parent);
73	if (IS_ERR(p)) {	78	if (IS_ERR(p)) {
74	ret = PTR_ERR(p);	79	ret = PTR_ERR(p);
75	goto err_with_put;	80	/* continue if just no pinctrl states (e.g. i2c-gpio), otherwise exit */
		81	if (ret != -ENODEV)
		82	goto err_with_put;
		83	} else {
		84	/* there are states. check and use them */
		85	struct pinctrl_state *s = pinctrl_lookup_state(p, priv->bus_name);
		86
		87	if (IS_ERR(s)) {
		88	ret = PTR_ERR(s);
		89	goto err_with_put;
		90	}
		91	ret = pinctrl_select_state(p, s);
		92	if (ret < 0)
		93	goto err_with_put;
76	}	94	}
77		95
78	priv->chan[new_chan].parent_adap = adap;	96	priv->chan[new_chan].parent_adap = adap;

drivers/i2c/muxes/i2c-mux-pca954x.c+2−2

 				/* discard unconfigured channels */
 				break;
 			idle_disconnect_pd = pdata->modes[num].deselect_on_exit;
-			data->deselect |= (idle_disconnect_pd
-					   || idle_disconnect_dt) << num;
 		}
+		data->deselect |= (idle_disconnect_pd ||
+				   idle_disconnect_dt) << num;
 		ret = i2c_mux_add_adapter(muxc, force, num, class);

drivers/infiniband/core/addr.c+9−2

 struct resolve_cb_context {
 	struct rdma_dev_addr *addr;
 	struct completion comp;
+	int status;
 };
 static void resolve_cb(int status, struct sockaddr *src_addr,
 	     struct rdma_dev_addr *addr, void *context)
 {
-	memcpy(((struct resolve_cb_context *)context)->addr, addr, sizeof(struct
+	if (!status)
-				rdma_dev_addr));
+		memcpy(((struct resolve_cb_context *)context)->addr,
+		       addr, sizeof(struct rdma_dev_addr));
+	((struct resolve_cb_context *)context)->status = status;
 	complete(&((struct resolve_cb_context *)context)->comp);
 }
 	wait_for_completion(&ctx.comp);
+	ret = ctx.status;
+	if (ret)
+		return ret;
 	memcpy(dmac, dev_addr.dst_dev_addr, ETH_ALEN);
 	dev = dev_get_by_index(&init_net, dev_addr.bound_dev_if);
 	if (!dev)

drivers/infiniband/core/cm.c+110−16

@@ -80,6 +80,8 @@ static struct ib_cm { · 79 unmodified lines
80	__be32 random_id_operand;	80	__be32 random_id_operand;
81	struct list_head timewait_list;	81	struct list_head timewait_list;
82	struct workqueue_struct *wq;	82	struct workqueue_struct *wq;
		83	/* Sync on cm change port state */
		84	spinlock_t state_lock;
83	} cm;	85	} cm;
84		86
85	/* Counter indexes ordered by attribute ID */	87	/* Counter indexes ordered by attribute ID */
@@ -161,6 +163,8 @@ struct cm_port { · 75 unmodified lines
161	struct ib_mad_agent *mad_agent;	163	struct ib_mad_agent *mad_agent;
162	struct kobject port_obj;	164	struct kobject port_obj;
163	u8 port_num;	165	u8 port_num;
		166	struct list_head cm_priv_prim_list;
		167	struct list_head cm_priv_altr_list;
164	struct cm_counter_group counter_group[CM_COUNTER_GROUPS];	168	struct cm_counter_group counter_group[CM_COUNTER_GROUPS];
165	};	169	};
166		170
@@ -241,6 +245,12 @@ struct cm_id_private { · 74 unmodified lines
241	u8 service_timeout;	245	u8 service_timeout;
242	u8 target_ack_delay;	246	u8 target_ack_delay;
243		247
		248	struct list_head prim_list;
		249	struct list_head altr_list;
		250	/* Indicates that the send port mad is registered and av is set */
		251	int prim_send_port_not_ready;
		252	int altr_send_port_not_ready;
		253
244	struct list_head work_list;	254	struct list_head work_list;
245	atomic_t work_count;	255	atomic_t work_count;
246	};	256	};
@@ -259,20 +269,47 @@ static int cm_alloc_msg(struct cm_id_private *cm_id_priv, · 12 unmodified lines
259	struct ib_mad_agent *mad_agent;	269	struct ib_mad_agent *mad_agent;
260	struct ib_mad_send_buf *m;	270	struct ib_mad_send_buf *m;
261	struct ib_ah *ah;	271	struct ib_ah *ah;
		272	struct cm_av *av;
		273	unsigned long flags, flags2;
		274	int ret = 0;
262		275
		276	/* don't let the port to be released till the agent is down */
		277	spin_lock_irqsave(&cm.state_lock, flags2);
		278	spin_lock_irqsave(&cm.lock, flags);
		279	if (!cm_id_priv->prim_send_port_not_ready)
		280	av = &cm_id_priv->av;
		281	else if (!cm_id_priv->altr_send_port_not_ready &&
		282	(cm_id_priv->alt_av.port))
		283	av = &cm_id_priv->alt_av;
		284	else {
		285	pr_info("%s: not valid CM id\n", __func__);
		286	ret = -ENODEV;
		287	spin_unlock_irqrestore(&cm.lock, flags);
		288	goto out;
		289	}
		290	spin_unlock_irqrestore(&cm.lock, flags);
		291	/* Make sure the port haven't released the mad yet */
263	mad_agent = cm_id_priv->av.port->mad_agent;	292	mad_agent = cm_id_priv->av.port->mad_agent;
264	ah = ib_create_ah(mad_agent->qp->pd, &cm_id_priv->av.ah_attr);	293	if (!mad_agent) {
265	if (IS_ERR(ah))	294	pr_info("%s: not a valid MAD agent\n", __func__);
266	return PTR_ERR(ah);	295	ret = -ENODEV;
		296	goto out;
		297	}
		298	ah = ib_create_ah(mad_agent->qp->pd, &av->ah_attr);
		299	if (IS_ERR(ah)) {
		300	ret = PTR_ERR(ah);
		301	goto out;
		302	}
267		303
268	m = ib_create_send_mad(mad_agent, cm_id_priv->id.remote_cm_qpn,	304	m = ib_create_send_mad(mad_agent, cm_id_priv->id.remote_cm_qpn,
269	cm_id_priv->av.pkey_index,	305	av->pkey_index,
270	0, IB_MGMT_MAD_HDR, IB_MGMT_MAD_DATA,	306	0, IB_MGMT_MAD_HDR, IB_MGMT_MAD_DATA,
271	GFP_ATOMIC,	307	GFP_ATOMIC,
272	IB_MGMT_BASE_VERSION);	308	IB_MGMT_BASE_VERSION);
273	if (IS_ERR(m)) {	309	if (IS_ERR(m)) {
274	ib_destroy_ah(ah);	310	ib_destroy_ah(ah);
275	return PTR_ERR(m);	311	ret = PTR_ERR(m);
		312	goto out;
276	}	313	}
277		314
278	/* Timeout set by caller if response is expected. */	315	/* Timeout set by caller if response is expected. */
@@ -282,7 +319,10 @@ static int cm_alloc_msg(struct cm_id_private *cm_id_priv, · 3 unmodified lines
282	atomic_inc(&cm_id_priv->refcount);	319	atomic_inc(&cm_id_priv->refcount);
283	m->context[0] = cm_id_priv;	320	m->context[0] = cm_id_priv;
284	*msg = m;	321	*msg = m;
285	return 0;	322
		323	out:
		324	spin_unlock_irqrestore(&cm.state_lock, flags2);
		325	return ret;
286	}	326	}
287		327
288	static int cm_alloc_response_msg(struct cm_port *port,	328	static int cm_alloc_response_msg(struct cm_port *port,
@@ -352,7 +392,8 @@ static void cm_init_av_for_response(struct cm_port port, struct ib_wc wc, · 63 unmodified lines
352	grh, &av->ah_attr);	392	grh, &av->ah_attr);
353	}	393	}
354		394
355	static int cm_init_av_by_path(struct ib_sa_path_rec path, struct cm_av av)	395	static int cm_init_av_by_path(struct ib_sa_path_rec path, struct cm_av av,
		396	struct cm_id_private *cm_id_priv)
356	{	397	{
357	struct cm_device *cm_dev;	398	struct cm_device *cm_dev;
358	struct cm_port *port = NULL;	399	struct cm_port *port = NULL;
@@ -387,7 +428,17 @@ static int cm_init_av_by_path(struct ib_sa_path_rec path, struct cm_av av) · 28 unmodified lines
387	&av->ah_attr);	428	&av->ah_attr);
388	av->timeout = path->packet_life_time + 1;	429	av->timeout = path->packet_life_time + 1;
389		430
390	return 0;	431	spin_lock_irqsave(&cm.lock, flags);
		432	if (&cm_id_priv->av == av)
		433	list_add_tail(&cm_id_priv->prim_list, &port->cm_priv_prim_list);
		434	else if (&cm_id_priv->alt_av == av)
		435	list_add_tail(&cm_id_priv->altr_list, &port->cm_priv_altr_list);
		436	else
		437	ret = -EINVAL;
		438
		439	spin_unlock_irqrestore(&cm.lock, flags);
		440
		441	return ret;
391	}	442	}
392		443
393	static int cm_alloc_id(struct cm_id_private *cm_id_priv)	444	static int cm_alloc_id(struct cm_id_private *cm_id_priv)
@@ -677,6 +728,8 @@ struct ib_cm_id ib_create_cm_id(struct ib_device device, · 283 unmodified lines
677	spin_lock_init(&cm_id_priv->lock);	728	spin_lock_init(&cm_id_priv->lock);
678	init_completion(&cm_id_priv->comp);	729	init_completion(&cm_id_priv->comp);
679	INIT_LIST_HEAD(&cm_id_priv->work_list);	730	INIT_LIST_HEAD(&cm_id_priv->work_list);
		731	INIT_LIST_HEAD(&cm_id_priv->prim_list);
		732	INIT_LIST_HEAD(&cm_id_priv->altr_list);
680	atomic_set(&cm_id_priv->work_count, -1);	733	atomic_set(&cm_id_priv->work_count, -1);
681	atomic_set(&cm_id_priv->refcount, 1);	734	atomic_set(&cm_id_priv->refcount, 1);
682	return &cm_id_priv->id;	735	return &cm_id_priv->id;
@@ -892,6 +945,15 @@ retest: · 209 unmodified lines
892	break;	945	break;
893	}	946	}
894		947
		948	spin_lock_irq(&cm.lock);
		949	if (!list_empty(&cm_id_priv->altr_list) &&
		950	(!cm_id_priv->altr_send_port_not_ready))
		951	list_del(&cm_id_priv->altr_list);
		952	if (!list_empty(&cm_id_priv->prim_list) &&
		953	(!cm_id_priv->prim_send_port_not_ready))
		954	list_del(&cm_id_priv->prim_list);
		955	spin_unlock_irq(&cm.lock);
		956
895	cm_free_id(cm_id->local_id);	957	cm_free_id(cm_id->local_id);
896	cm_deref_id(cm_id_priv);	958	cm_deref_id(cm_id_priv);
897	wait_for_completion(&cm_id_priv->comp);	959	wait_for_completion(&cm_id_priv->comp);
@@ -1192,12 +1254,13 @@ int ib_send_cm_req(struct ib_cm_id *cm_id, · 294 unmodified lines
1192	goto out;	1254	goto out;
1193	}	1255	}
1194		1256
1195	ret = cm_init_av_by_path(param->primary_path, &cm_id_priv->av);	1257	ret = cm_init_av_by_path(param->primary_path, &cm_id_priv->av,
		1258	cm_id_priv);
1196	if (ret)	1259	if (ret)
1197	goto error1;	1260	goto error1;
1198	if (param->alternate_path) {	1261	if (param->alternate_path) {
1199	ret = cm_init_av_by_path(param->alternate_path,	1262	ret = cm_init_av_by_path(param->alternate_path,
1200	&cm_id_priv->alt_av);	1263	&cm_id_priv->alt_av, cm_id_priv);
1201	if (ret)	1264	if (ret)
1202	goto error1;	1265	goto error1;
1203	}	1266	}
@@ -1653,7 +1716,8 @@ static int cm_req_handler(struct cm_work *work) · 449 unmodified lines
1653	dev_put(gid_attr.ndev);	1716	dev_put(gid_attr.ndev);
1654	}	1717	}
1655	work->path[0].gid_type = gid_attr.gid_type;	1718	work->path[0].gid_type = gid_attr.gid_type;
1656	ret = cm_init_av_by_path(&work->path[0], &cm_id_priv->av);	1719	ret = cm_init_av_by_path(&work->path[0], &cm_id_priv->av,
		1720	cm_id_priv);
1657	}	1721	}
1658	if (ret) {	1722	if (ret) {
1659	int err = ib_get_cached_gid(work->port->cm_dev->ib_device,	1723	int err = ib_get_cached_gid(work->port->cm_dev->ib_device,
@@ -1672,7 +1736,8 @@ static int cm_req_handler(struct cm_work *work) · 12 unmodified lines
1672	goto rejected;	1736	goto rejected;
1673	}	1737	}
1674	if (req_msg->alt_local_lid) {	1738	if (req_msg->alt_local_lid) {
1675	ret = cm_init_av_by_path(&work->path[1], &cm_id_priv->alt_av);	1739	ret = cm_init_av_by_path(&work->path[1], &cm_id_priv->alt_av,
		1740	cm_id_priv);
1676	if (ret) {	1741	if (ret) {
1677	ib_send_cm_rej(cm_id, IB_CM_REJ_INVALID_ALT_GID,	1742	ib_send_cm_rej(cm_id, IB_CM_REJ_INVALID_ALT_GID,
1678	&work->path[0].sgid,	1743	&work->path[0].sgid,
@@ -2727,7 +2792,8 @@ int ib_send_cm_lap(struct ib_cm_id *cm_id, · 1048 unmodified lines
2727	goto out;	2792	goto out;
2728	}	2793	}
2729		2794
2730	ret = cm_init_av_by_path(alternate_path, &cm_id_priv->alt_av);	2795	ret = cm_init_av_by_path(alternate_path, &cm_id_priv->alt_av,
		2796	cm_id_priv);
2731	if (ret)	2797	if (ret)
2732	goto out;	2798	goto out;
2733	cm_id_priv->alt_av.timeout =	2799	cm_id_priv->alt_av.timeout =
@@ -2839,7 +2905,8 @@ static int cm_lap_handler(struct cm_work *work) · 105 unmodified lines
2839	cm_init_av_for_response(work->port, work->mad_recv_wc->wc,	2905	cm_init_av_for_response(work->port, work->mad_recv_wc->wc,
2840	work->mad_recv_wc->recv_buf.grh,	2906	work->mad_recv_wc->recv_buf.grh,
2841	&cm_id_priv->av);	2907	&cm_id_priv->av);
2842	cm_init_av_by_path(param->alternate_path, &cm_id_priv->alt_av);	2908	cm_init_av_by_path(param->alternate_path, &cm_id_priv->alt_av,
		2909	cm_id_priv);
2843	ret = atomic_inc_and_test(&cm_id_priv->work_count);	2910	ret = atomic_inc_and_test(&cm_id_priv->work_count);
2844	if (!ret)	2911	if (!ret)
2845	list_add_tail(&work->list, &cm_id_priv->work_list);	2912	list_add_tail(&work->list, &cm_id_priv->work_list);
@@ -3031,7 +3098,7 @@ int ib_send_cm_sidr_req(struct ib_cm_id *cm_id, · 185 unmodified lines
3031	return -EINVAL;	3098	return -EINVAL;
3032		3099
3033	cm_id_priv = container_of(cm_id, struct cm_id_private, id);	3100	cm_id_priv = container_of(cm_id, struct cm_id_private, id);
3034	ret = cm_init_av_by_path(param->path, &cm_id_priv->av);	3101	ret = cm_init_av_by_path(param->path, &cm_id_priv->av, cm_id_priv);
3035	if (ret)	3102	if (ret)
3036	goto out;	3103	goto out;
3037		3104
@@ -3468,7 +3535,9 @@ out: · 430 unmodified lines
3468	static int cm_migrate(struct ib_cm_id *cm_id)	3535	static int cm_migrate(struct ib_cm_id *cm_id)
3469	{	3536	{
3470	struct cm_id_private *cm_id_priv;	3537	struct cm_id_private *cm_id_priv;
		3538	struct cm_av tmp_av;
3471	unsigned long flags;	3539	unsigned long flags;
		3540	int tmp_send_port_not_ready;
3472	int ret = 0;	3541	int ret = 0;
3473		3542
3474	cm_id_priv = container_of(cm_id, struct cm_id_private, id);	3543	cm_id_priv = container_of(cm_id, struct cm_id_private, id);
@@ -3477,7 +3546,14 @@ static int cm_migrate(struct ib_cm_id *cm_id) · 2 unmodified lines
3477	(cm_id->lap_state == IB_CM_LAP_UNINIT \|\|	3546	(cm_id->lap_state == IB_CM_LAP_UNINIT \|\|
3478	cm_id->lap_state == IB_CM_LAP_IDLE)) {	3547	cm_id->lap_state == IB_CM_LAP_IDLE)) {
3479	cm_id->lap_state = IB_CM_LAP_IDLE;	3548	cm_id->lap_state = IB_CM_LAP_IDLE;
		3549	/* Swap address vector */
		3550	tmp_av = cm_id_priv->av;
3480	cm_id_priv->av = cm_id_priv->alt_av;	3551	cm_id_priv->av = cm_id_priv->alt_av;
		3552	cm_id_priv->alt_av = tmp_av;
		3553	/* Swap port send ready state */
		3554	tmp_send_port_not_ready = cm_id_priv->prim_send_port_not_ready;
		3555	cm_id_priv->prim_send_port_not_ready = cm_id_priv->altr_send_port_not_ready;
		3556	cm_id_priv->altr_send_port_not_ready = tmp_send_port_not_ready;
3481	} else	3557	} else
3482	ret = -EINVAL;	3558	ret = -EINVAL;
3483	spin_unlock_irqrestore(&cm_id_priv->lock, flags);	3559	spin_unlock_irqrestore(&cm_id_priv->lock, flags);
@@ -3888,6 +3964,9 @@ static void cm_add_one(struct ib_device *ib_device) · 404 unmodified lines
3888	port->cm_dev = cm_dev;	3964	port->cm_dev = cm_dev;
3889	port->port_num = i;	3965	port->port_num = i;
3890		3966
		3967	INIT_LIST_HEAD(&port->cm_priv_prim_list);
		3968	INIT_LIST_HEAD(&port->cm_priv_altr_list);
		3969
3891	ret = cm_create_port_fs(port);	3970	ret = cm_create_port_fs(port);
3892	if (ret)	3971	if (ret)
3893	goto error1;	3972	goto error1;
@@ -3945,6 +4024,8 @@ static void cm_remove_one(struct ib_device ib_device, void client_data) · 51 unmodified lines
3945	{	4024	{
3946	struct cm_device *cm_dev = client_data;	4025	struct cm_device *cm_dev = client_data;
3947	struct cm_port *port;	4026	struct cm_port *port;
		4027	struct cm_id_private *cm_id_priv;
		4028	struct ib_mad_agent *cur_mad_agent;
3948	struct ib_port_modify port_modify = {	4029	struct ib_port_modify port_modify = {
3949	.clr_port_cap_mask = IB_PORT_CM_SUP	4030	.clr_port_cap_mask = IB_PORT_CM_SUP
3950	};	4031	};
@@ -3968,15 +4049,27 @@ static void cm_remove_one(struct ib_device ib_device, void client_data) · 17 unmodified lines
3968		4049
3969	port = cm_dev->port[i-1];	4050	port = cm_dev->port[i-1];
3970	ib_modify_port(ib_device, port->port_num, 0, &port_modify);	4051	ib_modify_port(ib_device, port->port_num, 0, &port_modify);
		4052	/* Mark all the cm_id's as not valid */
		4053	spin_lock_irq(&cm.lock);
		4054	list_for_each_entry(cm_id_priv, &port->cm_priv_altr_list, altr_list)
		4055	cm_id_priv->altr_send_port_not_ready = 1;
		4056	list_for_each_entry(cm_id_priv, &port->cm_priv_prim_list, prim_list)
		4057	cm_id_priv->prim_send_port_not_ready = 1;
		4058	spin_unlock_irq(&cm.lock);
3971	/*	4059	/*
3972	* We flush the queue here after the going_down set, this	4060	* We flush the queue here after the going_down set, this
3973	* verify that no new works will be queued in the recv handler,	4061	* verify that no new works will be queued in the recv handler,
3974	* after that we can call the unregister_mad_agent	4062	* after that we can call the unregister_mad_agent
3975	*/	4063	*/
3976	flush_workqueue(cm.wq);	4064	flush_workqueue(cm.wq);
3977	ib_unregister_mad_agent(port->mad_agent);	4065	spin_lock_irq(&cm.state_lock);
		4066	cur_mad_agent = port->mad_agent;
		4067	port->mad_agent = NULL;
		4068	spin_unlock_irq(&cm.state_lock);
		4069	ib_unregister_mad_agent(cur_mad_agent);
3978	cm_remove_port_fs(port);	4070	cm_remove_port_fs(port);
3979	}	4071	}
		4072
3980	device_unregister(cm_dev->device);	4073	device_unregister(cm_dev->device);
3981	kfree(cm_dev);	4074	kfree(cm_dev);
3982	}	4075	}
@@ -3989,6 +4082,7 @@ static int __init ib_cm_init(void) · 6 unmodified lines
3989	INIT_LIST_HEAD(&cm.device_list);	4082	INIT_LIST_HEAD(&cm.device_list);
3990	rwlock_init(&cm.device_lock);	4083	rwlock_init(&cm.device_lock);
3991	spin_lock_init(&cm.lock);	4084	spin_lock_init(&cm.lock);
		4085	spin_lock_init(&cm.state_lock);
3992	cm.listen_service_table = RB_ROOT;	4086	cm.listen_service_table = RB_ROOT;
3993	cm.listen_service_id = be64_to_cpu(IB_CM_ASSIGN_SERVICE_ID);	4087	cm.listen_service_id = be64_to_cpu(IB_CM_ASSIGN_SERVICE_ID);
3994	cm.remote_id_table = RB_ROOT;	4088	cm.remote_id_table = RB_ROOT;

drivers/infiniband/core/cma.c+20−1

 	return 0;
 }
+static enum ib_gid_type cma_route_gid_type(enum rdma_network_type network_type,
+					   unsigned long supported_gids,
+					   enum ib_gid_type default_gid)
+{
+	if ((network_type == RDMA_NETWORK_IPV4 ||
+	     network_type == RDMA_NETWORK_IPV6) &&
+	    test_bit(IB_GID_TYPE_ROCE_UDP_ENCAP, &supported_gids))
+		return IB_GID_TYPE_ROCE_UDP_ENCAP;
+	return default_gid;
+}
 static int cma_resolve_iboe_route(struct rdma_id_private *id_priv)
 {
 	struct rdma_route *route = &id_priv->id.route;
 	route->num_paths = 1;
 	if (addr->dev_addr.bound_dev_if) {
+		unsigned long supported_gids;
 		ndev = dev_get_by_index(&init_net, addr->dev_addr.bound_dev_if);
 		if (!ndev) {
 			ret = -ENODEV;
 		route->path_rec->net = &init_net;
 		route->path_rec->ifindex = ndev->ifindex;
-		route->path_rec->gid_type = id_priv->gid_type;
+		supported_gids = roce_gid_type_mask_support(id_priv->id.device,
+							    id_priv->id.port_num);
+		route->path_rec->gid_type =
+			cma_route_gid_type(addr->dev_addr.network,
+					   supported_gids,
+					   id_priv->gid_type);
 	}
 	if (!ndev) {
 		ret = -ENODEV;

drivers/infiniband/core/umem.c+1−1

@@ -175,7 +175,7 @@ struct ib_umem ib_umem_get(struct ib_ucontext context, unsigned long addr, · 174 unmodified lines
175		175
176	cur_base = addr & PAGE_MASK;	176	cur_base = addr & PAGE_MASK;
177		177
178	if (npages == 0) {	178	if (npages == 0 \|\| npages > UINT_MAX) {
179	ret = -EINVAL;	179	ret = -EINVAL;
180	goto out;	180	goto out;
181	}	181	}

drivers/infiniband/core/uverbs_main.c+2−5

 			container_of(uobj, struct ib_uqp_object, uevent.uobject);
 		idr_remove_uobj(&ib_uverbs_qp_idr, uobj);
-		if (qp != qp->real_qp) {
+		if (qp == qp->real_qp)
-			ib_close_qp(qp);
-		} else {
 			ib_uverbs_detach_umcast(qp, uqp);
-			ib_destroy_qp(qp);
+		ib_destroy_qp(qp);
-		}
 		ib_uverbs_release_uevent(file, &uqp->uevent);
 		kfree(uqp);
 	}

drivers/infiniband/hw/cxgb4/cq.c+3−14

 	return ret;
 }
-static void invalidate_mr(struct c4iw_dev *rhp, u32 rkey)
-{
-	struct c4iw_mr *mhp;
-	unsigned long flags;
-	spin_lock_irqsave(&rhp->lock, flags);
-	mhp = get_mhp(rhp, rkey >> 8);
-	if (mhp)
-		mhp->attr.state = 0;
-	spin_unlock_irqrestore(&rhp->lock, flags);
-}
 /*
  * Get one cq entry from c4iw and map it to openib.
  *
 		    CQE_OPCODE(&cqe) == FW_RI_SEND_WITH_SE_INV) {
 			wc->ex.invalidate_rkey = CQE_WRID_STAG(&cqe);
 			wc->wc_flags |= IB_WC_WITH_INVALIDATE;
-			invalidate_mr(qhp->rhp, wc->ex.invalidate_rkey);
+			c4iw_invalidate_mr(qhp->rhp, wc->ex.invalidate_rkey);
 		}
 	} else {
 		switch (CQE_OPCODE(&cqe)) {
 			/* Invalidate the MR if the fastreg failed */
 			if (CQE_STATUS(&cqe) != T4_ERR_SUCCESS)
-				invalidate_mr(qhp->rhp, CQE_WRID_FR_STAG(&cqe));
+				c4iw_invalidate_mr(qhp->rhp,
+						   CQE_WRID_FR_STAG(&cqe));
 			break;
 		default:
 			printk(KERN_ERR MOD "Unexpected opcode %d "

drivers/infiniband/hw/cxgb4/iw_cxgb4.h+1−1

@@ -999,6 +999,6 @@ extern int db_coalescing_threshold; · 998 unmodified lines
999	extern int use_dsgl;	999	extern int use_dsgl;
1000	void c4iw_drain_rq(struct ib_qp *qp);	1000	void c4iw_drain_rq(struct ib_qp *qp);
1001	void c4iw_drain_sq(struct ib_qp *qp);	1001	void c4iw_drain_sq(struct ib_qp *qp);
1002		1002	void c4iw_invalidate_mr(struct c4iw_dev *rhp, u32 rkey);
1003		1003
1004	#endif	1004	#endif

drivers/infiniband/hw/cxgb4/mem.c+12−0

@@ -770,3 +770,15 @@ int c4iw_dereg_mr(struct ib_mr *ib_mr) · 769 unmodified lines
770	kfree(mhp);	770	kfree(mhp);
771	return 0;	771	return 0;
772	}	772	}
		773
		774	void c4iw_invalidate_mr(struct c4iw_dev *rhp, u32 rkey)
		775	{
		776	struct c4iw_mr *mhp;
		777	unsigned long flags;
		778
		779	spin_lock_irqsave(&rhp->lock, flags);
		780	mhp = get_mhp(rhp, rkey >> 8);
		781	if (mhp)
		782	mhp->attr.state = 0;
		783	spin_unlock_irqrestore(&rhp->lock, flags);
		784	}

drivers/infiniband/hw/cxgb4/qp.c+12−8

 	return 0;
 }
-static int build_inv_stag(struct c4iw_dev *dev, union t4_wr *wqe,
+static int build_inv_stag(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16)
-			  struct ib_send_wr *wr, u8 *len16)
 {
-	struct c4iw_mr *mhp = get_mhp(dev, wr->ex.invalidate_rkey >> 8);
-	mhp->attr.state = 0;
 	wqe->inv.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
 	wqe->inv.r2 = 0;
 	*len16 = DIV_ROUND_UP(sizeof wqe->inv, 16);
 	spin_lock_irqsave(&qhp->lock, flag);
 	if (t4_wq_in_error(&qhp->wq)) {
 		spin_unlock_irqrestore(&qhp->lock, flag);
+		*bad_wr = wr;
 		return -EINVAL;
 	}
 	num_wrs = t4_sq_avail(&qhp->wq);
 	if (num_wrs == 0) {
 		spin_unlock_irqrestore(&qhp->lock, flag);
+		*bad_wr = wr;
 		return -ENOMEM;
 	}
 	while (wr) {
 		case IB_WR_RDMA_READ_WITH_INV:
 			fw_opcode = FW_RI_RDMA_READ_WR;
 			swsqe->opcode = FW_RI_READ_REQ;
-			if (wr->opcode == IB_WR_RDMA_READ_WITH_INV)
+			if (wr->opcode == IB_WR_RDMA_READ_WITH_INV) {
+				c4iw_invalidate_mr(qhp->rhp,
+						   wr->sg_list[0].lkey);
 				fw_flags = FW_RI_RDMA_READ_INVALIDATE;
-			else
+			} else {
 				fw_flags = 0;
+			}
 			err = build_rdma_read(wqe, wr, &len16);
 			if (err)
 				break;
 				fw_flags |= FW_RI_LOCAL_FENCE_FLAG;
 			fw_opcode = FW_RI_INV_LSTAG_WR;
 			swsqe->opcode = FW_RI_LOCAL_INV;
-			err = build_inv_stag(qhp->rhp, wqe, wr, &len16);
+			err = build_inv_stag(wqe, wr, &len16);
+			c4iw_invalidate_mr(qhp->rhp, wr->ex.invalidate_rkey);
 			break;
 		default:
 			PDBG("%s post of type=%d TBD!\n", __func__,
 	spin_lock_irqsave(&qhp->lock, flag);
 	if (t4_wq_in_error(&qhp->wq)) {
 		spin_unlock_irqrestore(&qhp->lock, flag);
+		*bad_wr = wr;
 		return -EINVAL;
 	}
 	num_wrs = t4_rq_avail(&qhp->wq);
 	if (num_wrs == 0) {
 		spin_unlock_irqrestore(&qhp->lock, flag);
+		*bad_wr = wr;
 		return -ENOMEM;
 	}
 	while (wr) {

drivers/infiniband/hw/hfi1/affinity.c+0−72

@@ -775,75 +775,3 @@ void hfi1_put_proc_affinity(int cpu) · 774 unmodified lines
775	}	775	}
776	mutex_unlock(&affinity->lock);	776	mutex_unlock(&affinity->lock);
777	}	777	}
778
779	int hfi1_set_sdma_affinity(struct hfi1_devdata dd, const char buf,
780	size_t count)
781	{
782	struct hfi1_affinity_node *entry;
783	cpumask_var_t mask;
784	int ret, i;
785
786	mutex_lock(&node_affinity.lock);
787	entry = node_affinity_lookup(dd->node);
788
789	if (!entry) {
790	ret = -EINVAL;
791	goto unlock;
792	}
793
794	ret = zalloc_cpumask_var(&mask, GFP_KERNEL);
795	if (!ret) {
796	ret = -ENOMEM;
797	goto unlock;
798	}
799
800	ret = cpulist_parse(buf, mask);
801	if (ret)
802	goto out;
803
804	if (!cpumask_subset(mask, cpu_online_mask) \|\| cpumask_empty(mask)) {
805	dd_dev_warn(dd, "Invalid CPU mask\n");
806	ret = -EINVAL;
807	goto out;
808	}
809
810	/* reset the SDMA interrupt affinity details */
811	init_cpu_mask_set(&entry->def_intr);
812	cpumask_copy(&entry->def_intr.mask, mask);
813
814	/* Reassign the affinity for each SDMA interrupt. */
815	for (i = 0; i < dd->num_msix_entries; i++) {
816	struct hfi1_msix_entry *msix;
817
818	msix = &dd->msix_entries[i];
819	if (msix->type != IRQ_SDMA)
820	continue;
821
822	ret = get_irq_affinity(dd, msix);
823
824	if (ret)
825	break;
826	}
827	out:
828	free_cpumask_var(mask);
829	unlock:
830	mutex_unlock(&node_affinity.lock);
831	return ret ? ret : strnlen(buf, PAGE_SIZE);
832	}
833
834	int hfi1_get_sdma_affinity(struct hfi1_devdata dd, char buf)
835	{
836	struct hfi1_affinity_node *entry;
837
838	mutex_lock(&node_affinity.lock);
839	entry = node_affinity_lookup(dd->node);
840
841	if (!entry) {
842	mutex_unlock(&node_affinity.lock);
843	return -EINVAL;
844	}
845
846	cpumap_print_to_pagebuf(true, buf, &entry->def_intr.mask);
847	mutex_unlock(&node_affinity.lock);
848	return strnlen(buf, PAGE_SIZE);
849	}

drivers/infiniband/hw/hfi1/affinity.h+0−4

 /* Release a CPU used by a user process. */
 void hfi1_put_proc_affinity(int);
-int hfi1_get_sdma_affinity(struct hfi1_devdata *dd, char *buf);
-int hfi1_set_sdma_affinity(struct hfi1_devdata *dd, const char *buf,
-			   size_t count);
 struct hfi1_affinity_node {
 	int node;
 	struct cpu_mask_set def_intr;

drivers/infiniband/hw/hfi1/chip.c+9−18

 	/* leave shared count at zero for both global and VL15 */
 	write_global_credit(dd, vau, vl15buf, 0);
-	/* We may need some credits for another VL when sending packets
+	write_csr(dd, SEND_CM_CREDIT_VL15, (u64)vl15buf
-	 * with the snoop interface. Dividing it down the middle for VL15
+		  << SEND_CM_CREDIT_VL15_DEDICATED_LIMIT_VL_SHIFT);
-	 * and VL0 should suffice.
-	 */
-	if (unlikely(dd->hfi1_snoop.mode_flag == HFI1_PORT_SNOOP_MODE)) {
-		write_csr(dd, SEND_CM_CREDIT_VL15, (u64)(vl15buf >> 1)
-		    << SEND_CM_CREDIT_VL15_DEDICATED_LIMIT_VL_SHIFT);
-		write_csr(dd, SEND_CM_CREDIT_VL, (u64)(vl15buf >> 1)
-		    << SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SHIFT);
-	} else {
-		write_csr(dd, SEND_CM_CREDIT_VL15, (u64)vl15buf
-			<< SEND_CM_CREDIT_VL15_DEDICATED_LIMIT_VL_SHIFT);
-	}
 }
 /*
 	u32 mask = ~((1U << ppd->lmc) - 1);
 	u64 c1 = read_csr(ppd->dd, DCC_CFG_PORT_CONFIG1);
-	if (dd->hfi1_snoop.mode_flag)
-		dd_dev_info(dd, "Set lid/lmc while snooping");
 	c1 &= ~(DCC_CFG_PORT_CONFIG1_TARGET_DLID_SMASK
 		| DCC_CFG_PORT_CONFIG1_DLID_MASK_SMASK);
 	c1 |= ((ppd->lid & DCC_CFG_PORT_CONFIG1_TARGET_DLID_MASK)
 	mod_timer(&dd->synth_stats_timer, jiffies + HZ * SYNTH_CNT_TIME);
 }
-#define C_MAX_NAME 13 /* 12 chars + one for /0 */
+#define C_MAX_NAME 16 /* 15 chars + one for /0 */
 static int init_cntrs(struct hfi1_devdata *dd)
 {
 	int i, rcv_ctxts, j;
 	 * Any error printing is already done by the init code.
 	 * On return, we have the chip mapped.
 	 */
-	ret = hfi1_pcie_ddinit(dd, pdev, ent);
+	ret = hfi1_pcie_ddinit(dd, pdev);
 	if (ret < 0)
 		goto bail_free;
 	if (ret)
 		goto bail_free_cntrs;
+	init_completion(&dd->user_comp);
+	/* The user refcount starts with one to inidicate an active device */
+	atomic_set(&dd->user_refcount, 1);
 	goto bail;
 bail_free_rcverr:

drivers/infiniband/hw/hfi1/chip.h+3−0

@@ -320,6 +320,9 @@ · 319 unmodified lines
320	/* DC_DC8051_CFG_MODE.GENERAL bits */	320	/* DC_DC8051_CFG_MODE.GENERAL bits */
321	#define DISABLE_SELF_GUID_CHECK 0x2	321	#define DISABLE_SELF_GUID_CHECK 0x2
322		322
		323	/* Bad L2 frame error code */
		324	#define BAD_L2_ERR 0x6
		325
323	/*	326	/*
324	* Eager buffer minimum and maximum sizes supported by the hardware.	327	* Eager buffer minimum and maximum sizes supported by the hardware.
325	* All power-of-two sizes in between are supported as well.	328	* All power-of-two sizes in between are supported as well.

drivers/infiniband/hw/hfi1/driver.c+26−11

 					 dd->rhf_offset;
 		struct rvt_qp *qp;
 		struct ib_header *hdr;
-		struct ib_other_headers *ohdr;
 		struct rvt_dev_info *rdi = &dd->verbs_dev.rdi;
 		u64 rhf = rhf_to_cpu(rhf_addr);
 		u32 etype = rhf_rcv_type(rhf), qpn, bth1;
 		if (etype != RHF_RCV_TYPE_IB)
 			goto next;
-		hdr = hfi1_get_msgheader(dd, rhf_addr);
+		packet->hdr = hfi1_get_msgheader(dd, rhf_addr);
+		hdr = packet->hdr;
 		lnh = be16_to_cpu(hdr->lrh[0]) & 3;
-		if (lnh == HFI1_LRH_BTH)
+		if (lnh == HFI1_LRH_BTH) {
-			ohdr = &hdr->u.oth;
+			packet->ohdr = &hdr->u.oth;
-		else if (lnh == HFI1_LRH_GRH)
+		} else if (lnh == HFI1_LRH_GRH) {
-			ohdr = &hdr->u.l.oth;
+			packet->ohdr = &hdr->u.l.oth;
-		else
+			packet->rcv_flags |= HFI1_HAS_GRH;
+		} else {
 			goto next; /* just in case */
+		}
-		bth1 = be32_to_cpu(ohdr->bth[1]);
+		bth1 = be32_to_cpu(packet->ohdr->bth[1]);
 		is_ecn = !!(bth1 & (HFI1_FECN_SMASK | HFI1_BECN_SMASK));
 		if (!is_ecn)
 		/* turn off BECN, FECN */
 		bth1 &= ~(HFI1_FECN_SMASK | HFI1_BECN_SMASK);
-		ohdr->bth[1] = cpu_to_be32(bth1);
+		packet->ohdr->bth[1] = cpu_to_be32(bth1);
 next:
 		update_ps_mdata(&mdata, rcd);
 	}
 int process_receive_bypass(struct hfi1_packet *packet)
 {
+	struct hfi1_devdata *dd = packet->rcd->dd;
 	if (unlikely(rhf_err_flags(packet->rhf)))
 		handle_eflags(packet);
-	dd_dev_err(packet->rcd->dd,
+	dd_dev_err(dd,
 		   "Bypass packets are not supported in normal operation. Dropping\n");
-	incr_cntr64(&packet->rcd->dd->sw_rcv_bypass_packet_errors);
+	incr_cntr64(&dd->sw_rcv_bypass_packet_errors);
+	if (!(dd->err_info_rcvport.status_and_code & OPA_EI_STATUS_SMASK)) {
+		u64 *flits = packet->ebuf;
+		if (flits && !(packet->rhf & RHF_LEN_ERR)) {
+			dd->err_info_rcvport.packet_flit1 = flits[0];
+			dd->err_info_rcvport.packet_flit2 =
+				packet->tlen > sizeof(flits[0]) ? flits[1] : 0;
+		}
+		dd->err_info_rcvport.status_and_code |=
+			(OPA_EI_STATUS_SMASK | BAD_L2_ERR);
+	}
 	return RHF_RCV_CONTINUE;
 }

drivers/infiniband/hw/hfi1/file_ops.c+16−3

 					       struct hfi1_devdata,
 					       user_cdev);
+	if (!atomic_inc_not_zero(&dd->user_refcount))
+		return -ENXIO;
 	/* Just take a ref now. Not all opens result in a context assign */
 	kobject_get(&dd->kobj);
 		fd->rec_cpu_num = -1; /* no cpu affinity by default */
 		fd->mm = current->mm;
 		atomic_inc(&fd->mm->mm_count);
-	}
+		fp->private_data = fd;
+	} else {
+		fp->private_data = NULL;
+		if (atomic_dec_and_test(&dd->user_refcount))
+			complete(&dd->user_comp);
-	fp->private_data = fd;
+		return -ENOMEM;
+	}
-	return fd ? 0 : -ENOMEM;
+	return 0;
 }
 static long hfi1_file_ioctl(struct file *fp, unsigned int cmd,
 done:
 	mmdrop(fdata->mm);
 	kobject_put(&dd->kobj);
+	if (atomic_dec_and_test(&dd->user_refcount))
+		complete(&dd->user_comp);
 	kfree(fdata);
 	return 0;
 }

drivers/infiniband/hw/hfi1/hfi.h+34−55

@@ -367,26 +367,6 @@ struct hfi1_packet { · 366 unmodified lines
367	u8 etype;	367	u8 etype;
368	};	368	};
369		369
370	/*
371	* Private data for snoop/capture support.
372	*/
373	struct hfi1_snoop_data {
374	int mode_flag;
375	struct cdev cdev;
376	struct device *class_dev;
377	/* protect snoop data */
378	spinlock_t snoop_lock;
379	struct list_head queue;
380	wait_queue_head_t waitq;
381	void *filter_value;
382	int (filter_callback)(void hdr, void data, void value);
383	u64 dcc_cfg; /* saved value of DCC Cfg register */
384	};
385
386	/* snoop mode_flag values */
387	#define HFI1_PORT_SNOOP_MODE 1U
388	#define HFI1_PORT_CAPTURE_MODE 2U
389
390	struct rvt_sge_state;	370	struct rvt_sge_state;
391		371
392	/*	372	/*
@@ -613,8 +593,6 @@ struct hfi1_pportdata { · 220 unmodified lines
613	struct mutex hls_lock;	593	struct mutex hls_lock;
614	u32 host_link_state;	594	u32 host_link_state;
615		595
616	spinlock_t sdma_alllock ____cacheline_aligned_in_smp;
617
618	u32 lstate; /* logical link state */	596	u32 lstate; /* logical link state */
619		597
620	/* these are the "32 bit" regs */	598	/* these are the "32 bit" regs */
@@ -1104,8 +1082,6 @@ struct hfi1_devdata { · 483 unmodified lines
1104	char *portcntrnames;	1082	char *portcntrnames;
1105	size_t portcntrnameslen;	1083	size_t portcntrnameslen;
1106		1084
1107	struct hfi1_snoop_data hfi1_snoop;
1108
1109	struct err_info_rcvport err_info_rcvport;	1085	struct err_info_rcvport err_info_rcvport;
1110	struct err_info_constraint err_info_rcv_constraint;	1086	struct err_info_constraint err_info_rcv_constraint;
1111	struct err_info_constraint err_info_xmit_constraint;	1087	struct err_info_constraint err_info_xmit_constraint;
@@ -1141,8 +1117,8 @@ struct hfi1_devdata { · 29 unmodified lines
1141	rhf_rcv_function_ptr normal_rhf_rcv_functions[8];	1117	rhf_rcv_function_ptr normal_rhf_rcv_functions[8];
1142		1118
1143	/*	1119	/*
1144	* Handlers for outgoing data so that snoop/capture does not	1120	* Capability to have different send engines simply by changing a
1145	* have to have its hooks in the send path	1121	* pointer value.
1146	*/	1122	*/
1147	send_routine process_pio_send;	1123	send_routine process_pio_send;
1148	send_routine process_dma_send;	1124	send_routine process_dma_send;
@@ -1174,6 +1150,10 @@ struct hfi1_devdata { · 25 unmodified lines
1174	spinlock_t aspm_lock;	1150	spinlock_t aspm_lock;
1175	/* Number of verbs contexts which have disabled ASPM */	1151	/* Number of verbs contexts which have disabled ASPM */
1176	atomic_t aspm_disabled_cnt;	1152	atomic_t aspm_disabled_cnt;
		1153	/* Keeps track of user space clients */
		1154	atomic_t user_refcount;
		1155	/* Used to wait for outstanding user space clients before dev removal */
		1156	struct completion user_comp;
1177		1157
1178	struct hfi1_affinity *affinity;	1158	struct hfi1_affinity *affinity;
1179	struct rhashtable sdma_rht;	1159	struct rhashtable sdma_rht;
@@ -1221,8 +1201,6 @@ struct hfi1_devdata *hfi1_lookup(int unit); · 41 unmodified lines
1221	extern u32 hfi1_cpulist_count;	1201	extern u32 hfi1_cpulist_count;
1222	extern unsigned long *hfi1_cpulist;	1202	extern unsigned long *hfi1_cpulist;
1223		1203
1224	extern unsigned int snoop_drop_send;
1225	extern unsigned int snoop_force_capture;
1226	int hfi1_init(struct hfi1_devdata *, int);	1204	int hfi1_init(struct hfi1_devdata *, int);
1227	int hfi1_count_units(int npresentp, int nupp);	1205	int hfi1_count_units(int npresentp, int nupp);
1228	int hfi1_count_active_units(void);	1206	int hfi1_count_active_units(void);
@@ -1557,13 +1535,6 @@ void set_up_vl15(struct hfi1_devdata *dd, u8 vau, u16 vl15buf); · 328 unmodified lines
1557	void reset_link_credits(struct hfi1_devdata *dd);	1535	void reset_link_credits(struct hfi1_devdata *dd);
1558	void assign_remote_cm_au_table(struct hfi1_devdata *dd, u8 vcu);	1536	void assign_remote_cm_au_table(struct hfi1_devdata *dd, u8 vcu);
1559		1537
1560	int snoop_recv_handler(struct hfi1_packet *packet);
1561	int snoop_send_dma_handler(struct rvt_qp qp, struct hfi1_pkt_state ps,
1562	u64 pbc);
1563	int snoop_send_pio_handler(struct rvt_qp qp, struct hfi1_pkt_state ps,
1564	u64 pbc);
1565	void snoop_inline_pio_send(struct hfi1_devdata dd, struct pio_buf pbuf,
1566	u64 pbc, const void *from, size_t count);
1567	int set_buffer_control(struct hfi1_pportdata ppd, struct buffer_control bc);	1538	int set_buffer_control(struct hfi1_pportdata ppd, struct buffer_control bc);
1568		1539
1569	static inline struct hfi1_devdata dd_from_ppd(struct hfi1_pportdata ppd)	1540	static inline struct hfi1_devdata dd_from_ppd(struct hfi1_pportdata ppd)
@@ -1763,8 +1734,7 @@ int qsfp_dump(struct hfi1_pportdata ppd, char buf, int len); · 193 unmodified lines
1763		1734
1764	int hfi1_pcie_init(struct pci_dev , const struct pci_device_id );	1735	int hfi1_pcie_init(struct pci_dev , const struct pci_device_id );
1765	void hfi1_pcie_cleanup(struct pci_dev *);	1736	void hfi1_pcie_cleanup(struct pci_dev *);
1766	int hfi1_pcie_ddinit(struct hfi1_devdata , struct pci_dev ,	1737	int hfi1_pcie_ddinit(struct hfi1_devdata , struct pci_dev );
1767	const struct pci_device_id *);
1768	void hfi1_pcie_ddcleanup(struct hfi1_devdata *);	1738	void hfi1_pcie_ddcleanup(struct hfi1_devdata *);
1769	void hfi1_pcie_flr(struct hfi1_devdata *);	1739	void hfi1_pcie_flr(struct hfi1_devdata *);
1770	int pcie_speeds(struct hfi1_devdata *);	1740	int pcie_speeds(struct hfi1_devdata *);
@@ -1799,8 +1769,6 @@ int kdeth_process_expected(struct hfi1_packet *packet); · 28 unmodified lines
1799	int kdeth_process_eager(struct hfi1_packet *packet);	1769	int kdeth_process_eager(struct hfi1_packet *packet);
1800	int process_receive_invalid(struct hfi1_packet *packet);	1770	int process_receive_invalid(struct hfi1_packet *packet);
1801		1771
1802	extern rhf_rcv_function_ptr snoop_rhf_rcv_functions[8];
1803
1804	void update_sge(struct rvt_sge_state *ss, u32 length);	1772	void update_sge(struct rvt_sge_state *ss, u32 length);
1805		1773
1806	/* global module parameter variables */	1774	/* global module parameter variables */
@@ -1827,9 +1795,6 @@ extern struct mutex hfi1_mutex; · 20 unmodified lines
1827	#define DRIVER_NAME "hfi1"	1795	#define DRIVER_NAME "hfi1"
1828	#define HFI1_USER_MINOR_BASE 0	1796	#define HFI1_USER_MINOR_BASE 0
1829	#define HFI1_TRACE_MINOR 127	1797	#define HFI1_TRACE_MINOR 127
1830	#define HFI1_DIAGPKT_MINOR 128
1831	#define HFI1_DIAG_MINOR_BASE 129
1832	#define HFI1_SNOOP_CAPTURE_BASE 200
1833	#define HFI1_NMINORS 255	1798	#define HFI1_NMINORS 255
1834		1799
1835	#define PCI_VENDOR_ID_INTEL 0x8086	1800	#define PCI_VENDOR_ID_INTEL 0x8086
@@ -1848,7 +1813,13 @@ extern struct mutex hfi1_mutex; · 12 unmodified lines
1848	static inline u64 hfi1_pkt_default_send_ctxt_mask(struct hfi1_devdata *dd,	1813	static inline u64 hfi1_pkt_default_send_ctxt_mask(struct hfi1_devdata *dd,
1849	u16 ctxt_type)	1814	u16 ctxt_type)
1850	{	1815	{
1851	u64 base_sc_integrity =	1816	u64 base_sc_integrity;
		1817
		1818	/* No integrity checks if HFI1_CAP_NO_INTEGRITY is set */
		1819	if (HFI1_CAP_IS_KSET(NO_INTEGRITY))
		1820	return 0;
		1821
		1822	base_sc_integrity =
1852	SEND_CTXT_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK	1823	SEND_CTXT_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK
1853	\| SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK	1824	\| SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK
1854	\| SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK	1825	\| SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK
@@ -1863,7 +1834,6 @@ static inline u64 hfi1_pkt_default_send_ctxt_mask(struct hfi1_devdata *dd, · 8 unmodified lines
1863	\| SEND_CTXT_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK	1834	\| SEND_CTXT_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK
1864	\| SEND_CTXT_CHECK_ENABLE_CHECK_OPCODE_SMASK	1835	\| SEND_CTXT_CHECK_ENABLE_CHECK_OPCODE_SMASK
1865	\| SEND_CTXT_CHECK_ENABLE_CHECK_SLID_SMASK	1836	\| SEND_CTXT_CHECK_ENABLE_CHECK_SLID_SMASK
1866	\| SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK
1867	\| SEND_CTXT_CHECK_ENABLE_CHECK_VL_SMASK	1837	\| SEND_CTXT_CHECK_ENABLE_CHECK_VL_SMASK
1868	\| SEND_CTXT_CHECK_ENABLE_CHECK_ENABLE_SMASK;	1838	\| SEND_CTXT_CHECK_ENABLE_CHECK_ENABLE_SMASK;
1869		1839
@@ -1872,18 +1842,23 @@ static inline u64 hfi1_pkt_default_send_ctxt_mask(struct hfi1_devdata *dd, · 2 unmodified lines
1872	else	1842	else
1873	base_sc_integrity \|= HFI1_PKT_KERNEL_SC_INTEGRITY;	1843	base_sc_integrity \|= HFI1_PKT_KERNEL_SC_INTEGRITY;
1874		1844
1875	if (is_ax(dd))	1845	/* turn on send-side job key checks if !A0 */
1876	/* turn off send-side job key checks - A0 */	1846	if (!is_ax(dd))
1877	return base_sc_integrity &	1847	base_sc_integrity \|= SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK;
1878	~SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK;	1848
1879	return base_sc_integrity;	1849	return base_sc_integrity;
1880	}	1850	}
1881		1851
1882	static inline u64 hfi1_pkt_base_sdma_integrity(struct hfi1_devdata *dd)	1852	static inline u64 hfi1_pkt_base_sdma_integrity(struct hfi1_devdata *dd)
1883	{	1853	{
1884	u64 base_sdma_integrity =	1854	u64 base_sdma_integrity;
		1855
		1856	/* No integrity checks if HFI1_CAP_NO_INTEGRITY is set */
		1857	if (HFI1_CAP_IS_KSET(NO_INTEGRITY))
		1858	return 0;
		1859
		1860	base_sdma_integrity =
1885	SEND_DMA_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK	1861	SEND_DMA_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK
1886	\| SEND_DMA_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK
1887	\| SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK	1862	\| SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK
1888	\| SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_IB_PACKETS_SMASK	1863	\| SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_IB_PACKETS_SMASK
1889	\| SEND_DMA_CHECK_ENABLE_DISALLOW_BAD_PKT_LEN_SMASK	1864	\| SEND_DMA_CHECK_ENABLE_DISALLOW_BAD_PKT_LEN_SMASK
@@ -1895,14 +1870,18 @@ static inline u64 hfi1_pkt_base_sdma_integrity(struct hfi1_devdata *dd) · 5 unmodified lines
1895	\| SEND_DMA_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK	1870	\| SEND_DMA_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK
1896	\| SEND_DMA_CHECK_ENABLE_CHECK_OPCODE_SMASK	1871	\| SEND_DMA_CHECK_ENABLE_CHECK_OPCODE_SMASK
1897	\| SEND_DMA_CHECK_ENABLE_CHECK_SLID_SMASK	1872	\| SEND_DMA_CHECK_ENABLE_CHECK_SLID_SMASK
1898	\| SEND_DMA_CHECK_ENABLE_CHECK_JOB_KEY_SMASK
1899	\| SEND_DMA_CHECK_ENABLE_CHECK_VL_SMASK	1873	\| SEND_DMA_CHECK_ENABLE_CHECK_VL_SMASK
1900	\| SEND_DMA_CHECK_ENABLE_CHECK_ENABLE_SMASK;	1874	\| SEND_DMA_CHECK_ENABLE_CHECK_ENABLE_SMASK;
1901		1875
1902	if (is_ax(dd))	1876	if (!HFI1_CAP_IS_KSET(STATIC_RATE_CTRL))
1903	/* turn off send-side job key checks - A0 */	1877	base_sdma_integrity \|=
1904	return base_sdma_integrity &	1878	SEND_DMA_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK;
1905	~SEND_DMA_CHECK_ENABLE_CHECK_JOB_KEY_SMASK;	1879
		1880	/* turn on send-side job key checks if !A0 */
		1881	if (!is_ax(dd))
		1882	base_sdma_integrity \|=
		1883	SEND_DMA_CHECK_ENABLE_CHECK_JOB_KEY_SMASK;
		1884
1906	return base_sdma_integrity;	1885	return base_sdma_integrity;
1907	}	1886	}
1908		1887

drivers/infiniband/hw/hfi1/init.c+64−40

@@ -144,6 +144,8 @@ int hfi1_create_ctxts(struct hfi1_devdata *dd) · 143 unmodified lines
144	struct hfi1_ctxtdata *rcd;	144	struct hfi1_ctxtdata *rcd;
145		145
146	ppd = dd->pport + (i % dd->num_pports);	146	ppd = dd->pport + (i % dd->num_pports);
		147
		148	/* dd->rcd[i] gets assigned inside the callee */
147	rcd = hfi1_create_ctxtdata(ppd, i, dd->node);	149	rcd = hfi1_create_ctxtdata(ppd, i, dd->node);
148	if (!rcd) {	150	if (!rcd) {
149	dd_dev_err(dd,	151	dd_dev_err(dd,
@@ -169,8 +171,6 @@ int hfi1_create_ctxts(struct hfi1_devdata *dd) · 19 unmodified lines
169	if (!rcd->sc) {	171	if (!rcd->sc) {
170	dd_dev_err(dd,	172	dd_dev_err(dd,
171	"Unable to allocate kernel send context, failing\n");	173	"Unable to allocate kernel send context, failing\n");
172	dd->rcd[rcd->ctxt] = NULL;
173	hfi1_free_ctxtdata(dd, rcd);
174	goto nomem;	174	goto nomem;
175	}	175	}
176		176
@@ -178,9 +178,6 @@ int hfi1_create_ctxts(struct hfi1_devdata *dd) · 1 unmodified line
178	if (ret < 0) {	178	if (ret < 0) {
179	dd_dev_err(dd,	179	dd_dev_err(dd,
180	"Failed to setup kernel receive context, failing\n");	180	"Failed to setup kernel receive context, failing\n");
181	sc_free(rcd->sc);
182	dd->rcd[rcd->ctxt] = NULL;
183	hfi1_free_ctxtdata(dd, rcd);
184	ret = -EFAULT;	181	ret = -EFAULT;
185	goto bail;	182	goto bail;
186	}	183	}
@@ -196,6 +193,10 @@ int hfi1_create_ctxts(struct hfi1_devdata *dd) · 9 unmodified lines
196	nomem:	193	nomem:
197	ret = -ENOMEM;	194	ret = -ENOMEM;
198	bail:	195	bail:
		196	if (dd->rcd) {
		197	for (i = 0; i < dd->num_rcv_contexts; ++i)
		198	hfi1_free_ctxtdata(dd, dd->rcd[i]);
		199	}
199	kfree(dd->rcd);	200	kfree(dd->rcd);
200	dd->rcd = NULL;	201	dd->rcd = NULL;
201	return ret;	202	return ret;
@@ -216,7 +217,7 @@ struct hfi1_ctxtdata hfi1_create_ctxtdata(struct hfi1_pportdata ppd, u32 ctxt, · 14 unmodified lines
216	dd->num_rcv_contexts - dd->first_user_ctxt)	217	dd->num_rcv_contexts - dd->first_user_ctxt)
217	kctxt_ngroups = (dd->rcv_entries.nctxt_extra -	218	kctxt_ngroups = (dd->rcv_entries.nctxt_extra -
218	(dd->num_rcv_contexts - dd->first_user_ctxt));	219	(dd->num_rcv_contexts - dd->first_user_ctxt));
219	rcd = kzalloc(sizeof(*rcd), GFP_KERNEL);	220	rcd = kzalloc_node(sizeof(*rcd), GFP_KERNEL, numa);
220	if (rcd) {	221	if (rcd) {
221	u32 rcvtids, max_entries;	222	u32 rcvtids, max_entries;
222		223
@@ -261,13 +262,6 @@ struct hfi1_ctxtdata hfi1_create_ctxtdata(struct hfi1_pportdata ppd, u32 ctxt, · 38 unmodified lines
261	}	262	}
262	rcd->eager_base = base * dd->rcv_entries.group_size;	263	rcd->eager_base = base * dd->rcv_entries.group_size;
263		264
264	/* Validate and initialize Rcv Hdr Q variables */
265	if (rcvhdrcnt % HDRQ_INCREMENT) {
266	dd_dev_err(dd,
267	"ctxt%u: header queue count %d must be divisible by %lu\n",
268	rcd->ctxt, rcvhdrcnt, HDRQ_INCREMENT);
269	goto bail;
270	}
271	rcd->rcvhdrq_cnt = rcvhdrcnt;	265	rcd->rcvhdrq_cnt = rcvhdrcnt;
272	rcd->rcvhdrqentsize = hfi1_hdrq_entsize;	266	rcd->rcvhdrqentsize = hfi1_hdrq_entsize;
273	/*	267	/*
@@ -506,7 +500,6 @@ void hfi1_init_pportdata(struct pci_dev pdev, struct hfi1_pportdata ppd, · 232 unmodified lines
506	INIT_WORK(&ppd->qsfp_info.qsfp_work, qsfp_event);	500	INIT_WORK(&ppd->qsfp_info.qsfp_work, qsfp_event);
507		501
508	mutex_init(&ppd->hls_lock);	502	mutex_init(&ppd->hls_lock);
509	spin_lock_init(&ppd->sdma_alllock);
510	spin_lock_init(&ppd->qsfp_info.qsfp_lock);	503	spin_lock_init(&ppd->qsfp_info.qsfp_lock);
511		504
512	ppd->qsfp_info.ppd = ppd;	505	ppd->qsfp_info.ppd = ppd;
@@ -1399,28 +1392,43 @@ static void postinit_cleanup(struct hfi1_devdata *dd) · 886 unmodified lines
1399	hfi1_free_devdata(dd);	1392	hfi1_free_devdata(dd);
1400	}	1393	}
1401		1394
		1395	static int init_validate_rcvhdrcnt(struct device *dev, uint thecnt)
		1396	{
		1397	if (thecnt <= HFI1_MIN_HDRQ_EGRBUF_CNT) {
		1398	hfi1_early_err(dev, "Receive header queue count too small\n");
		1399	return -EINVAL;
		1400	}
		1401
		1402	if (thecnt > HFI1_MAX_HDRQ_EGRBUF_CNT) {
		1403	hfi1_early_err(dev,
		1404	"Receive header queue count cannot be greater than %u\n",
		1405	HFI1_MAX_HDRQ_EGRBUF_CNT);
		1406	return -EINVAL;
		1407	}
		1408
		1409	if (thecnt % HDRQ_INCREMENT) {
		1410	hfi1_early_err(dev, "Receive header queue count %d must be divisible by %lu\n",
		1411	thecnt, HDRQ_INCREMENT);
		1412	return -EINVAL;
		1413	}
		1414
		1415	return 0;
		1416	}
		1417
1402	static int init_one(struct pci_dev pdev, const struct pci_device_id ent)	1418	static int init_one(struct pci_dev pdev, const struct pci_device_id ent)
1403	{	1419	{
1404	int ret = 0, j, pidx, initfail;	1420	int ret = 0, j, pidx, initfail;
1405	struct hfi1_devdata *dd = ERR_PTR(-EINVAL);	1421	struct hfi1_devdata *dd;
1406	struct hfi1_pportdata *ppd;	1422	struct hfi1_pportdata *ppd;
1407		1423
1408	/* First, lock the non-writable module parameters */	1424	/* First, lock the non-writable module parameters */
1409	HFI1_CAP_LOCK();	1425	HFI1_CAP_LOCK();
1410		1426
1411	/* Validate some global module parameters */	1427	/* Validate some global module parameters */
1412	if (rcvhdrcnt <= HFI1_MIN_HDRQ_EGRBUF_CNT) {	1428	ret = init_validate_rcvhdrcnt(&pdev->dev, rcvhdrcnt);
1413	hfi1_early_err(&pdev->dev, "Header queue count too small\n");	1429	if (ret)
1414	ret = -EINVAL;
1415	goto bail;
1416	}
1417	if (rcvhdrcnt > HFI1_MAX_HDRQ_EGRBUF_CNT) {
1418	hfi1_early_err(&pdev->dev,
1419	"Receive header queue count cannot be greater than %u\n",
1420	HFI1_MAX_HDRQ_EGRBUF_CNT);
1421	ret = -EINVAL;
1422	goto bail;	1430	goto bail;
1423	}	1431
1424	/* use the encoding function as a sanitization check */	1432	/* use the encoding function as a sanitization check */
1425	if (!encode_rcv_header_entry_size(hfi1_hdrq_entsize)) {	1433	if (!encode_rcv_header_entry_size(hfi1_hdrq_entsize)) {
1426	hfi1_early_err(&pdev->dev, "Invalid HdrQ Entry size %u\n",	1434	hfi1_early_err(&pdev->dev, "Invalid HdrQ Entry size %u\n",
@@ -1461,26 +1469,25 @@ static int init_one(struct pci_dev pdev, const struct pci_device_id ent) · 34 unmodified lines
1461	if (ret)	1469	if (ret)
1462	goto bail;	1470	goto bail;
1463		1471
1464	/*	1472	if (!(ent->device == PCI_DEVICE_ID_INTEL0 \|\|
1465	* Do device-specific initialization, function table setup, dd	1473	ent->device == PCI_DEVICE_ID_INTEL1)) {
1466	* allocation, etc.
1467	*/
1468	switch (ent->device) {
1469	case PCI_DEVICE_ID_INTEL0:
1470	case PCI_DEVICE_ID_INTEL1:
1471	dd = hfi1_init_dd(pdev, ent);
1472	break;
1473	default:
1474	hfi1_early_err(&pdev->dev,	1474	hfi1_early_err(&pdev->dev,
1475	"Failing on unknown Intel deviceid 0x%x\n",	1475	"Failing on unknown Intel deviceid 0x%x\n",
1476	ent->device);	1476	ent->device);
1477	ret = -ENODEV;	1477	ret = -ENODEV;
		1478	goto clean_bail;
1478	}	1479	}
1479		1480
1480	if (IS_ERR(dd))	1481	/*
		1482	* Do device-specific initialization, function table setup, dd
		1483	* allocation, etc.
		1484	*/
		1485	dd = hfi1_init_dd(pdev, ent);
		1486
		1487	if (IS_ERR(dd)) {
1481	ret = PTR_ERR(dd);	1488	ret = PTR_ERR(dd);
1482	if (ret)
1483	goto clean_bail; /* error already printed */	1489	goto clean_bail; /* error already printed */
		1490	}
1484		1491
1485	ret = create_workqueues(dd);	1492	ret = create_workqueues(dd);
1486	if (ret)	1493	if (ret)
@@ -1538,12 +1545,31 @@ bail: · 51 unmodified lines
1538	return ret;	1545	return ret;
1539	}	1546	}
1540		1547
		1548	static void wait_for_clients(struct hfi1_devdata *dd)
		1549	{
		1550	/*
		1551	* Remove the device init value and complete the device if there is
		1552	* no clients or wait for active clients to finish.
		1553	*/
		1554	if (atomic_dec_and_test(&dd->user_refcount))
		1555	complete(&dd->user_comp);
		1556
		1557	wait_for_completion(&dd->user_comp);
		1558	}
		1559
1541	static void remove_one(struct pci_dev *pdev)	1560	static void remove_one(struct pci_dev *pdev)
1542	{	1561	{
1543	struct hfi1_devdata *dd = pci_get_drvdata(pdev);	1562	struct hfi1_devdata *dd = pci_get_drvdata(pdev);
1544		1563
1545	/* close debugfs files before ib unregister */	1564	/* close debugfs files before ib unregister */
1546	hfi1_dbg_ibdev_exit(&dd->verbs_dev);	1565	hfi1_dbg_ibdev_exit(&dd->verbs_dev);
		1566
		1567	/* remove the /dev hfi1 interface */
		1568	hfi1_device_remove(dd);
		1569
		1570	/* wait for existing user space clients to finish */
		1571	wait_for_clients(dd);
		1572
1547	/* unregister from IB core */	1573	/* unregister from IB core */
1548	hfi1_unregister_ib_device(dd);	1574	hfi1_unregister_ib_device(dd);
1549		1575
@@ -1558,8 +1584,6 @@ static void remove_one(struct pci_dev *pdev) · 8 unmodified lines
1558	/* wait until all of our (qsfp) queue_work() calls complete */	1584	/* wait until all of our (qsfp) queue_work() calls complete */
1559	flush_workqueue(ib_wq);	1585	flush_workqueue(ib_wq);
1560		1586
1561	hfi1_device_remove(dd);
1562
1563	postinit_cleanup(dd);	1587	postinit_cleanup(dd);
1564	}	1588	}
1565		1589

drivers/infiniband/hw/hfi1/pcie.c+1−2

  * fields required to re-initialize after a chip reset, or for
  * various other purposes
  */
-int hfi1_pcie_ddinit(struct hfi1_devdata *dd, struct pci_dev *pdev,
+int hfi1_pcie_ddinit(struct hfi1_devdata *dd, struct pci_dev *pdev)
-		     const struct pci_device_id *ent)
 {
 	unsigned long len;
 	resource_size_t addr;

drivers/infiniband/hw/hfi1/pio.c+3−10

 void set_pio_integrity(struct send_context *sc)
 {
 	struct hfi1_devdata *dd = sc->dd;
-	u64 reg = 0;
 	u32 hw_context = sc->hw_context;
 	int type = sc->type;
-	/*
+	write_kctxt_csr(dd, hw_context,
-	 * No integrity checks if HFI1_CAP_NO_INTEGRITY is set, or if
+			SC(CHECK_ENABLE),
-	 * we're snooping.
+			hfi1_pkt_default_send_ctxt_mask(dd, type));
-	 */
-	if (likely(!HFI1_CAP_IS_KSET(NO_INTEGRITY)) &&
-	    dd->hfi1_snoop.mode_flag != HFI1_PORT_SNOOP_MODE)
-		reg = hfi1_pkt_default_send_ctxt_mask(dd, type);
-	write_kctxt_csr(dd, hw_context, SC(CHECK_ENABLE), reg);
 }
 static u32 get_buffers_allocated(struct send_context *sc)

drivers/infiniband/hw/hfi1/rc.c+1−1

@@ -89,7 +89,7 @@ void hfi1_add_rnr_timer(struct rvt_qp *qp, u32 to) · 88 unmodified lines
89		89
90	lockdep_assert_held(&qp->s_lock);	90	lockdep_assert_held(&qp->s_lock);
91	qp->s_flags \|= RVT_S_WAIT_RNR;	91	qp->s_flags \|= RVT_S_WAIT_RNR;
92	qp->s_timer.expires = jiffies + usecs_to_jiffies(to);	92	priv->s_rnr_timer.expires = jiffies + usecs_to_jiffies(to);
93	add_timer(&priv->s_rnr_timer);	93	add_timer(&priv->s_rnr_timer);
94	}	94	}
95		95

drivers/infiniband/hw/hfi1/sdma.c+2−17

@@ -2009,11 +2009,6 @@ static void sdma_hw_start_up(struct sdma_engine *sde) · 2008 unmodified lines
2009	write_sde_csr(sde, SD(ENG_ERR_CLEAR), reg);	2009	write_sde_csr(sde, SD(ENG_ERR_CLEAR), reg);
2010	}	2010	}
2011		2011
2012	#define CLEAR_STATIC_RATE_CONTROL_SMASK(r) \
2013	(r &= ~SEND_DMA_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK)
2014
2015	#define SET_STATIC_RATE_CONTROL_SMASK(r) \
2016	(r \|= SEND_DMA_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK)
2017	/*	2012	/*
2018	* set_sdma_integrity	2013	* set_sdma_integrity
2019	*	2014	*
@@ -2022,19 +2017,9 @@ static void sdma_hw_start_up(struct sdma_engine *sde) · 2 unmodified lines
2022	static void set_sdma_integrity(struct sdma_engine *sde)	2017	static void set_sdma_integrity(struct sdma_engine *sde)
2023	{	2018	{
2024	struct hfi1_devdata *dd = sde->dd;	2019	struct hfi1_devdata *dd = sde->dd;
2025	u64 reg;
2026
2027	if (unlikely(HFI1_CAP_IS_KSET(NO_INTEGRITY)))
2028	return;
2029
2030	reg = hfi1_pkt_base_sdma_integrity(dd);
2031
2032	if (HFI1_CAP_IS_KSET(STATIC_RATE_CTRL))
2033	CLEAR_STATIC_RATE_CONTROL_SMASK(reg);
2034	else
2035	SET_STATIC_RATE_CONTROL_SMASK(reg);
2036		2020
2037	write_sde_csr(sde, SD(CHECK_ENABLE), reg);	2021	write_sde_csr(sde, SD(CHECK_ENABLE),
		2022	hfi1_pkt_base_sdma_integrity(dd));
2038	}	2023	}
2039		2024
2040	static void init_sdma_regs(	2025	static void init_sdma_regs(

drivers/infiniband/hw/hfi1/sysfs.c+0−25

@@ -49,7 +49,6 @@ · 48 unmodified lines
49	#include "hfi.h"	49	#include "hfi.h"
50	#include "mad.h"	50	#include "mad.h"
51	#include "trace.h"	51	#include "trace.h"
52	#include "affinity.h"
53		52
54	/*	53	/*
55	* Start of per-port congestion control structures and support code	54	* Start of per-port congestion control structures and support code
@@ -623,27 +622,6 @@ static ssize_t show_tempsense(struct device *device, · 567 unmodified lines
623	return ret;	622	return ret;
624	}	623	}
625		624
626	static ssize_t show_sdma_affinity(struct device *device,
627	struct device_attribute attr, char buf)
628	{
629	struct hfi1_ibdev *dev =
630	container_of(device, struct hfi1_ibdev, rdi.ibdev.dev);
631	struct hfi1_devdata *dd = dd_from_dev(dev);
632
633	return hfi1_get_sdma_affinity(dd, buf);
634	}
635
636	static ssize_t store_sdma_affinity(struct device *device,
637	struct device_attribute *attr,
638	const char *buf, size_t count)
639	{
640	struct hfi1_ibdev *dev =
641	container_of(device, struct hfi1_ibdev, rdi.ibdev.dev);
642	struct hfi1_devdata *dd = dd_from_dev(dev);
643
644	return hfi1_set_sdma_affinity(dd, buf, count);
645	}
646
647	/*	625	/*
648	* end of per-unit (or driver, in some cases, but replicated	626	* end of per-unit (or driver, in some cases, but replicated
649	* per unit) functions	627	* per unit) functions
@@ -658,8 +636,6 @@ static DEVICE_ATTR(serial, S_IRUGO, show_serial, NULL); · 8 unmodified lines
658	static DEVICE_ATTR(boardversion, S_IRUGO, show_boardversion, NULL);	636	static DEVICE_ATTR(boardversion, S_IRUGO, show_boardversion, NULL);
659	static DEVICE_ATTR(tempsense, S_IRUGO, show_tempsense, NULL);	637	static DEVICE_ATTR(tempsense, S_IRUGO, show_tempsense, NULL);
660	static DEVICE_ATTR(chip_reset, S_IWUSR, NULL, store_chip_reset);	638	static DEVICE_ATTR(chip_reset, S_IWUSR, NULL, store_chip_reset);
661	static DEVICE_ATTR(sdma_affinity, S_IWUSR \| S_IRUGO, show_sdma_affinity,
662	store_sdma_affinity);
663		639
664	static struct device_attribute *hfi1_attributes[] = {	640	static struct device_attribute *hfi1_attributes[] = {
665	&dev_attr_hw_rev,	641	&dev_attr_hw_rev,
@@ -670,7 +646,6 @@ static struct device_attribute *hfi1_attributes[] = { · 4 unmodified lines
670	&dev_attr_boardversion,	646	&dev_attr_boardversion,
671	&dev_attr_tempsense,	647	&dev_attr_tempsense,
672	&dev_attr_chip_reset,	648	&dev_attr_chip_reset,
673	&dev_attr_sdma_affinity,
674	};	649	};
675		650
676	int hfi1_create_port_files(struct ib_device *ibdev, u8 port_num,	651	int hfi1_create_port_files(struct ib_device *ibdev, u8 port_num,

drivers/infiniband/hw/hfi1/trace_rx.h+0−60

@@ -253,66 +253,6 @@ TRACE_EVENT(hfi1_mmu_invalidate, · 252 unmodified lines
253	)	253	)
254	);	254	);
255		255
256	#define SNOOP_PRN \
257	"slid %.4x dlid %.4x qpn 0x%.6x opcode 0x%.2x,%s " \
258	"svc lvl %d pkey 0x%.4x [header = %d bytes] [data = %d bytes]"
259
260	TRACE_EVENT(snoop_capture,
261	TP_PROTO(struct hfi1_devdata *dd,
262	int hdr_len,
263	struct ib_header *hdr,
264	int data_len,
265	void *data),
266	TP_ARGS(dd, hdr_len, hdr, data_len, data),
267	TP_STRUCT__entry(
268	DD_DEV_ENTRY(dd)
269	__field(u16, slid)
270	__field(u16, dlid)
271	__field(u32, qpn)
272	__field(u8, opcode)
273	__field(u8, sl)
274	__field(u16, pkey)
275	__field(u32, hdr_len)
276	__field(u32, data_len)
277	__field(u8, lnh)
278	__dynamic_array(u8, raw_hdr, hdr_len)
279	__dynamic_array(u8, raw_pkt, data_len)
280	),
281	TP_fast_assign(
282	struct ib_other_headers *ohdr;
283
284	__entry->lnh = (u8)(be16_to_cpu(hdr->lrh[0]) & 3);
285	if (__entry->lnh == HFI1_LRH_BTH)
286	ohdr = &hdr->u.oth;
287	else
288	ohdr = &hdr->u.l.oth;
289	DD_DEV_ASSIGN(dd);
290	__entry->slid = be16_to_cpu(hdr->lrh[3]);
291	__entry->dlid = be16_to_cpu(hdr->lrh[1]);
292	__entry->qpn = be32_to_cpu(ohdr->bth[1]) & RVT_QPN_MASK;
293	__entry->opcode = (be32_to_cpu(ohdr->bth[0]) >> 24) & 0xff;
294	__entry->sl = (u8)(be16_to_cpu(hdr->lrh[0]) >> 4) & 0xf;
295	__entry->pkey = be32_to_cpu(ohdr->bth[0]) & 0xffff;
296	__entry->hdr_len = hdr_len;
297	__entry->data_len = data_len;
298	memcpy(__get_dynamic_array(raw_hdr), hdr, hdr_len);
299	memcpy(__get_dynamic_array(raw_pkt), data, data_len);
300	),
301	TP_printk(
302	"[%s] " SNOOP_PRN,
303	__get_str(dev),
304	__entry->slid,
305	__entry->dlid,
306	__entry->qpn,
307	__entry->opcode,
308	show_ib_opcode(__entry->opcode),
309	__entry->sl,
310	__entry->pkey,
311	__entry->hdr_len,
312	__entry->data_len
313	)
314	);
315
316	#endif /* __HFI1_TRACE_RX_H */	256	#endif /* __HFI1_TRACE_RX_H */
317		257
318	#undef TRACE_INCLUDE_PATH	258	#undef TRACE_INCLUDE_PATH

drivers/infiniband/hw/hfi1/user_sdma.c+1−1

@@ -1144,7 +1144,7 @@ static int pin_vector_pages(struct user_sdma_request *req, · 1143 unmodified lines
1144	rb_node = hfi1_mmu_rb_extract(pq->handler,	1144	rb_node = hfi1_mmu_rb_extract(pq->handler,
1145	(unsigned long)iovec->iov.iov_base,	1145	(unsigned long)iovec->iov.iov_base,
1146	iovec->iov.iov_len);	1146	iovec->iov.iov_len);
1147	if (rb_node && !IS_ERR(rb_node))	1147	if (rb_node)
1148	node = container_of(rb_node, struct sdma_mmu_node, rb);	1148	node = container_of(rb_node, struct sdma_mmu_node, rb);
1149	else	1149	else
1150	rb_node = NULL;	1150	rb_node = NULL;

drivers/infiniband/hw/mlx4/ah.c+4−1

 	if (vlan_tag < 0x1000)
 		vlan_tag |= (ah_attr->sl & 7) << 13;
 	ah->av.eth.port_pd = cpu_to_be32(to_mpd(pd)->pdn | (ah_attr->port_num << 24));
-	ah->av.eth.gid_index = mlx4_ib_gid_index_to_real_index(ibdev, ah_attr->port_num, ah_attr->grh.sgid_index);
+	ret = mlx4_ib_gid_index_to_real_index(ibdev, ah_attr->port_num, ah_attr->grh.sgid_index);
+	if (ret < 0)
+		return ERR_PTR(ret);
+	ah->av.eth.gid_index = ret;
 	ah->av.eth.vlan = cpu_to_be16(vlan_tag);
 	ah->av.eth.hop_limit = ah_attr->grh.hop_limit;
 	if (ah_attr->static_rate) {

drivers/infiniband/hw/mlx4/cq.c+4−1

 	if (context)
 		if (ib_copy_to_udata(udata, &cq->mcq.cqn, sizeof (__u32))) {
 			err = -EFAULT;
-			goto err_dbmap;
+			goto err_cq_free;
 		}
 	return &cq->ibcq;
+err_cq_free:
+	mlx4_cq_free(dev->dev, &cq->mcq);
 err_dbmap:
 	if (context)
 		mlx4_ib_db_unmap_user(to_mucontext(context), &cq->db);

drivers/infiniband/hw/mlx5/cq.c+1−2

 		if (err)
 			goto err_create;
 	} else {
-		/* for now choose 64 bytes till we have a proper interface */
+		cqe_size = cache_line_size() == 128 ? 128 : 64;
-		cqe_size = 64;
 		err = create_cq_kernel(dev, cq, entries, cqe_size, &cqb,
 				       &index, &inlen);
 		if (err)

drivers/infiniband/hw/mlx5/main.c+7−4

@@ -2311,14 +2311,14 @@ static void mlx5_ib_event(struct mlx5_core_dev dev, void context, · 2310 unmodified lines
2311	{	2311	{
2312	struct mlx5_ib_dev ibdev = (struct mlx5_ib_dev )context;	2312	struct mlx5_ib_dev ibdev = (struct mlx5_ib_dev )context;
2313	struct ib_event ibev;	2313	struct ib_event ibev;
2314		2314	bool fatal = false;
2315	u8 port = 0;	2315	u8 port = 0;
2316		2316
2317	switch (event) {	2317	switch (event) {
2318	case MLX5_DEV_EVENT_SYS_ERROR:	2318	case MLX5_DEV_EVENT_SYS_ERROR:
2319	ibdev->ib_active = false;
2320	ibev.event = IB_EVENT_DEVICE_FATAL;	2319	ibev.event = IB_EVENT_DEVICE_FATAL;
2321	mlx5_ib_handle_internal_error(ibdev);	2320	mlx5_ib_handle_internal_error(ibdev);
		2321	fatal = true;
2322	break;	2322	break;
2323		2323
2324	case MLX5_DEV_EVENT_PORT_UP:	2324	case MLX5_DEV_EVENT_PORT_UP:
@@ -2372,6 +2372,9 @@ static void mlx5_ib_event(struct mlx5_core_dev dev, void context, · 47 unmodified lines
2372		2372
2373	if (ibdev->ib_active)	2373	if (ibdev->ib_active)
2374	ib_dispatch_event(&ibev);	2374	ib_dispatch_event(&ibev);
		2375
		2376	if (fatal)
		2377	ibdev->ib_active = false;
2375	}	2378	}
2376		2379
2377	static void get_ext_port_caps(struct mlx5_ib_dev *dev)	2380	static void get_ext_port_caps(struct mlx5_ib_dev *dev)
@@ -3117,7 +3120,7 @@ static void mlx5_ib_add(struct mlx5_core_dev mdev) · 739 unmodified lines
3117	}	3120	}
3118	err = init_node_data(dev);	3121	err = init_node_data(dev);
3119	if (err)	3122	if (err)
3120	goto err_dealloc;	3123	goto err_free_port;
3121		3124
3122	mutex_init(&dev->flow_db.lock);	3125	mutex_init(&dev->flow_db.lock);
3123	mutex_init(&dev->cap_mask_mutex);	3126	mutex_init(&dev->cap_mask_mutex);
@@ -3127,7 +3130,7 @@ static void mlx5_ib_add(struct mlx5_core_dev mdev) · 3 unmodified lines
3127	if (ll == IB_LINK_LAYER_ETHERNET) {	3130	if (ll == IB_LINK_LAYER_ETHERNET) {
3128	err = mlx5_enable_roce(dev);	3131	err = mlx5_enable_roce(dev);
3129	if (err)	3132	if (err)
3130	goto err_dealloc;	3133	goto err_free_port;
3131	}	3134	}
3132		3135
3133	err = create_dev_resources(&dev->devr);	3136	err = create_dev_resources(&dev->devr);

drivers/infiniband/hw/mlx5/mlx5_ib.h+2−0

 	struct mlx5_ib_resources	devr;
 	struct mlx5_mr_cache		cache;
 	struct timer_list		delay_timer;
+	/* Prevents soft lock on massive reg MRs */
+	struct mutex			slow_path_mutex;
 	int				fill_delay;
 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 	struct ib_odp_caps	odp_caps;

drivers/infiniband/hw/mlx5/mr.c+5−1

 	int err;
 	int i;
+	mutex_init(&dev->slow_path_mutex);
 	cache->wq = alloc_ordered_workqueue("mkey_cache", WQ_MEM_RECLAIM);
 	if (!cache->wq) {
 		mlx5_ib_warn(dev, "failed to create work queue\n");
 		goto error;
 	}
-	if (!mr)
+	if (!mr) {
+		mutex_lock(&dev->slow_path_mutex);
 		mr = reg_create(NULL, pd, virt_addr, length, umem, ncont,
 				page_shift, access_flags);
+		mutex_unlock(&dev->slow_path_mutex);
+	}
 	if (IS_ERR(mr)) {
 		err = PTR_ERR(mr);

drivers/infiniband/hw/mlx5/qp.c+10−2

 		mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
 			    qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
-			    to_mcq(init_attr->recv_cq)->mcq.cqn,
+			    init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1,
-			    to_mcq(init_attr->send_cq)->mcq.cqn);
+			    init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1);
 		qp->trans_qp.xrcdn = xrcdn;
 				 udata->inlen))
 		return ERR_PTR(-EOPNOTSUPP);
+	if (init_attr->log_ind_tbl_size >
+	    MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
+		mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
+			    init_attr->log_ind_tbl_size,
+			    MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
+		return ERR_PTR(-EINVAL);
+	}
 	min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
 	if (udata->outlen && udata->outlen < min_resp_len)
 		return ERR_PTR(-EINVAL);

drivers/infiniband/sw/rdmavt/dma.c+0−3

@@ -90,9 +90,6 @@ static u64 rvt_dma_map_page(struct ib_device dev, struct page page, · 89 unmodified lines
90	if (WARN_ON(!valid_dma_direction(direction)))	90	if (WARN_ON(!valid_dma_direction(direction)))
91	return BAD_DMA_ADDRESS;	91	return BAD_DMA_ADDRESS;
92		92
93	if (offset + size > PAGE_SIZE)
94	return BAD_DMA_ADDRESS;
95
96	addr = (u64)page_address(page);	93	addr = (u64)page_address(page);
97	if (addr)	94	if (addr)
98	addr += offset;	95	addr += offset;

drivers/infiniband/sw/rxe/rxe_net.c+2−6

 {
 	int err;
 	struct socket *sock;
-	struct udp_port_cfg udp_cfg;
+	struct udp_port_cfg udp_cfg = {0};
-	struct udp_tunnel_sock_cfg tnl_cfg;
+	struct udp_tunnel_sock_cfg tnl_cfg = {0};
-	memset(&udp_cfg, 0, sizeof(udp_cfg));
 	if (ipv6) {
 		udp_cfg.family = AF_INET6;
 		return ERR_PTR(err);
 	}
-	tnl_cfg.sk_user_data = NULL;
 	tnl_cfg.encap_type = 1;
 	tnl_cfg.encap_rcv = rxe_udp_encap_recv;
-	tnl_cfg.encap_destroy = NULL;
 	/* Setup UDP tunnel */
 	setup_udp_tunnel_sock(net, sock, &tnl_cfg);

drivers/infiniband/sw/rxe/rxe_qp.c+2−0

 	if (qp->sq.queue) {
 		__rxe_do_task(&qp->comp.task);
 		__rxe_do_task(&qp->req.task);
+		rxe_queue_reset(qp->sq.queue);
 	}
 	/* cleanup attributes */
 {
 	qp->req.state = QP_STATE_ERROR;
 	qp->resp.state = QP_STATE_ERROR;
+	qp->attr.qp_state = IB_QPS_ERR;
 	/* drain work and packet queues */
 	rxe_run_task(&qp->resp.task, 1);

drivers/infiniband/sw/rxe/rxe_queue.c+9−0

@@ -84,6 +84,15 @@ err1: · 83 unmodified lines
84	return -EINVAL;	84	return -EINVAL;
85	}	85	}
86		86
		87	inline void rxe_queue_reset(struct rxe_queue *q)
		88	{
		89	/* queue is comprised from header and the memory
		90	* of the actual queue. See "struct rxe_queue_buf" in rxe_queue.h
		91	* reset only the queue itself and not the management header
		92	*/
		93	memset(q->buf->data, 0, q->buf_size - sizeof(struct rxe_queue_buf));
		94	}
		95
87	struct rxe_queue rxe_queue_init(struct rxe_dev rxe,	96	struct rxe_queue rxe_queue_init(struct rxe_dev rxe,
88	int *num_elem,	97	int *num_elem,
89	unsigned int elem_size)	98	unsigned int elem_size)

drivers/infiniband/sw/rxe/rxe_queue.h+2−0

@@ -84,6 +84,8 @@ int do_mmap_info(struct rxe_dev *rxe, · 83 unmodified lines
84	size_t buf_size,	84	size_t buf_size,
85	struct rxe_mmap_info **ip_p);	85	struct rxe_mmap_info **ip_p);
86		86
		87	void rxe_queue_reset(struct rxe_queue *q);
		88
87	struct rxe_queue rxe_queue_init(struct rxe_dev rxe,	89	struct rxe_queue rxe_queue_init(struct rxe_dev rxe,
88	int *num_elem,	90	int *num_elem,
89	unsigned int elem_size);	91	unsigned int elem_size);

drivers/infiniband/sw/rxe/rxe_req.c+13−8

@@ -696,7 +696,8 @@ next_wqe: · 695 unmodified lines
696	qp->req.wqe_index);	696	qp->req.wqe_index);
697	wqe->state = wqe_state_done;	697	wqe->state = wqe_state_done;
698	wqe->status = IB_WC_SUCCESS;	698	wqe->status = IB_WC_SUCCESS;
699	goto complete;	699	__rxe_do_task(&qp->comp.task);
		700	return 0;
700	}	701	}
701	payload = mtu;	702	payload = mtu;
702	}	703	}
@@ -745,13 +746,17 @@ err: · 42 unmodified lines
745	wqe->status = IB_WC_LOC_PROT_ERR;	746	wqe->status = IB_WC_LOC_PROT_ERR;
746	wqe->state = wqe_state_error;	747	wqe->state = wqe_state_error;
747		748
748	complete:	749	/*
749	if (qp_type(qp) != IB_QPT_RC) {	750	* IBA Spec. Section 10.7.3.1 SIGNALED COMPLETIONS
750	while (rxe_completer(qp) == 0)	751	* ---------8<---------8<-------------
751	;	752	* ...Note that if a completion error occurs, a Work Completion
752	}	753	* will always be generated, even if the signaling
753		754	* indicator requests an Unsignaled Completion.
754	return 0;	755	* ---------8<---------8<-------------
		756	*/
		757	wqe->wr.send_flags \|= IB_SEND_SIGNALED;
		758	__rxe_do_task(&qp->comp.task);
		759	return -EAGAIN;
755		760
756	exit:	761	exit:
757	return -EAGAIN;	762	return -EAGAIN;

drivers/mailbox/pcc.c+7−6

 #include <linux/mailbox_controller.h>
 #include <linux/mailbox_client.h>
 #include <linux/io-64-nonatomic-lo-hi.h>
+#include <acpi/pcc.h>
 #include "mailbox.h"
 	if (chan->txdone_method == TXDONE_BY_POLL && cl->knows_txdone)
 		chan->txdone_method |= TXDONE_BY_ACK;
+	spin_unlock_irqrestore(&chan->lock, flags);
 	if (pcc_doorbell_irq[subspace_id] > 0) {
 		int rc;
 		if (unlikely(rc)) {
 			dev_err(dev, "failed to register PCC interrupt %d\n",
 				pcc_doorbell_irq[subspace_id]);
+			pcc_mbox_free_channel(chan);
 			chan = ERR_PTR(rc);
 		}
 	}
-	spin_unlock_irqrestore(&chan->lock, flags);
 	return chan;
 }
 EXPORT_SYMBOL_GPL(pcc_mbox_request_channel);
 		return;
 	}
+	if (pcc_doorbell_irq[id] > 0)
+		devm_free_irq(chan->mbox->dev, pcc_doorbell_irq[id], chan);
 	spin_lock_irqsave(&chan->lock, flags);
 	chan->cl = NULL;
 	chan->active_req = NULL;
 	if (chan->txdone_method == (TXDONE_BY_POLL | TXDONE_BY_ACK))
 		chan->txdone_method = TXDONE_BY_POLL;
-	if (pcc_doorbell_irq[id] > 0)
-		devm_free_irq(chan->mbox->dev, pcc_doorbell_irq[id], chan);
 	spin_unlock_irqrestore(&chan->lock, flags);
 }
 EXPORT_SYMBOL_GPL(pcc_mbox_free_channel);
 /**
  * pcc_send_data - Called from Mailbox Controller code. Used
  *		here only to ring the channel doorbell. The PCC client

drivers/mfd/intel-lpss-pci.c+9−22

 	.properties = apl_i2c_properties,
 };
-static const struct intel_lpss_platform_info kbl_info = {
-	.clk_rate = 120000000,
-};
-static const struct intel_lpss_platform_info kbl_uart_info = {
-	.clk_rate = 120000000,
-	.clk_con_id = "baudclk",
-};
-static const struct intel_lpss_platform_info kbl_i2c_info = {
-	.clk_rate = 133000000,
-};
 static const struct pci_device_id intel_lpss_pci_ids[] = {
 	/* BXT A-Step */
 	{ PCI_VDEVICE(INTEL, 0x0aac), (kernel_ulong_t)&bxt_i2c_info },
 	{ PCI_VDEVICE(INTEL, 0xa161), (kernel_ulong_t)&spt_i2c_info },
 	{ PCI_VDEVICE(INTEL, 0xa166), (kernel_ulong_t)&spt_uart_info },
 	/* KBL-H */
-	{ PCI_VDEVICE(INTEL, 0xa2a7), (kernel_ulong_t)&kbl_uart_info },
+	{ PCI_VDEVICE(INTEL, 0xa2a7), (kernel_ulong_t)&spt_uart_info },
-	{ PCI_VDEVICE(INTEL, 0xa2a8), (kernel_ulong_t)&kbl_uart_info },
+	{ PCI_VDEVICE(INTEL, 0xa2a8), (kernel_ulong_t)&spt_uart_info },
-	{ PCI_VDEVICE(INTEL, 0xa2a9), (kernel_ulong_t)&kbl_info },
+	{ PCI_VDEVICE(INTEL, 0xa2a9), (kernel_ulong_t)&spt_info },
-	{ PCI_VDEVICE(INTEL, 0xa2aa), (kernel_ulong_t)&kbl_info },
+	{ PCI_VDEVICE(INTEL, 0xa2aa), (kernel_ulong_t)&spt_info },
-	{ PCI_VDEVICE(INTEL, 0xa2e0), (kernel_ulong_t)&kbl_i2c_info },
+	{ PCI_VDEVICE(INTEL, 0xa2e0), (kernel_ulong_t)&spt_i2c_info },
-	{ PCI_VDEVICE(INTEL, 0xa2e1), (kernel_ulong_t)&kbl_i2c_info },
+	{ PCI_VDEVICE(INTEL, 0xa2e1), (kernel_ulong_t)&spt_i2c_info },
-	{ PCI_VDEVICE(INTEL, 0xa2e2), (kernel_ulong_t)&kbl_i2c_info },
+	{ PCI_VDEVICE(INTEL, 0xa2e2), (kernel_ulong_t)&spt_i2c_info },
-	{ PCI_VDEVICE(INTEL, 0xa2e3), (kernel_ulong_t)&kbl_i2c_info },
+	{ PCI_VDEVICE(INTEL, 0xa2e3), (kernel_ulong_t)&spt_i2c_info },
-	{ PCI_VDEVICE(INTEL, 0xa2e6), (kernel_ulong_t)&kbl_uart_info },
+	{ PCI_VDEVICE(INTEL, 0xa2e6), (kernel_ulong_t)&spt_uart_info },
 	{ }
 };
 MODULE_DEVICE_TABLE(pci, intel_lpss_pci_ids);

drivers/mfd/intel-lpss.c+0−3

@@ -502,9 +502,6 @@ int intel_lpss_suspend(struct device *dev) · 501 unmodified lines
502	for (i = 0; i < LPSS_PRIV_REG_COUNT; i++)	502	for (i = 0; i < LPSS_PRIV_REG_COUNT; i++)
503	lpss->priv_ctx[i] = readl(lpss->priv + i * 4);	503	lpss->priv_ctx[i] = readl(lpss->priv + i * 4);
504		504
505	/* Put the device into reset state */
506	writel(0, lpss->priv + LPSS_PRIV_RESETS);
507
508	return 0;	505	return 0;
509	}	506	}
510	EXPORT_SYMBOL_GPL(intel_lpss_suspend);	507	EXPORT_SYMBOL_GPL(intel_lpss_suspend);

drivers/mfd/intel_soc_pmic_bxtwc.c+4−2

 	BXTWC_THRM2_IRQ,
 	BXTWC_BCU_IRQ,
 	BXTWC_ADC_IRQ,
+	BXTWC_USBC_IRQ,
 	BXTWC_CHGR0_IRQ,
 	BXTWC_CHGR1_IRQ,
 	BXTWC_GPIO0_IRQ,
 	REGMAP_IRQ_REG(BXTWC_THRM2_IRQ, 2, 0xff),
 	REGMAP_IRQ_REG(BXTWC_BCU_IRQ, 3, 0x1f),
 	REGMAP_IRQ_REG(BXTWC_ADC_IRQ, 4, 0xff),
-	REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 5, 0x3f),
+	REGMAP_IRQ_REG(BXTWC_USBC_IRQ, 5, BIT(5)),
+	REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 5, 0x1f),
 	REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 6, 0x1f),
 	REGMAP_IRQ_REG(BXTWC_GPIO0_IRQ, 7, 0xff),
 	REGMAP_IRQ_REG(BXTWC_GPIO1_IRQ, 8, 0x3f),
 };
 static struct resource usbc_resources[] = {
-	DEFINE_RES_IRQ_NAMED(BXTWC_CHGR0_IRQ, "USBC"),
+	DEFINE_RES_IRQ(BXTWC_USBC_IRQ),
 };
 static struct resource charger_resources[] = {

drivers/mfd/mfd-core.c+2−0

@@ -399,6 +399,8 @@ int mfd_clone_cell(const char cell, const char *clones, size_t n_clones) · 398 unmodified lines
399	clones[i]);	399	clones[i]);
400	}	400	}
401		401
		402	put_device(dev);
		403
402	return 0;	404	return 0;
403	}	405	}
404	EXPORT_SYMBOL(mfd_clone_cell);	406	EXPORT_SYMBOL(mfd_clone_cell);

drivers/mfd/stmpe.c+2−0

@@ -851,6 +851,8 @@ static int stmpe_reset(struct stmpe *stmpe) · 850 unmodified lines
851	if (ret < 0)	851	if (ret < 0)
852	return ret;	852	return ret;
853		853
		854	msleep(10);
		855
854	timeout = jiffies + msecs_to_jiffies(100);	856	timeout = jiffies + msecs_to_jiffies(100);
855	while (time_before(jiffies, timeout)) {	857	while (time_before(jiffies, timeout)) {
856	ret = __stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL]);	858	ret = __stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL]);

drivers/net/dsa/b53/b53_common.c+4−12

 		vl->members |= BIT(port) | BIT(cpu_port);
 		if (untagged)
-			vl->untag |= BIT(port) | BIT(cpu_port);
+			vl->untag |= BIT(port);
 		else
-			vl->untag &= ~(BIT(port) | BIT(cpu_port));
+			vl->untag &= ~BIT(port);
+		vl->untag &= ~BIT(cpu_port);
 		b53_set_vlan_entry(dev, vid, vl);
 		b53_fast_age_vlan(dev, vid);
 	if (pvid) {
 		b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port),
 			    vlan->vid_end);
-		b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(cpu_port),
-			    vlan->vid_end);
 		b53_fast_age_vlan(dev, vid);
 	}
 }
 {
 	struct b53_device *dev = ds->priv;
 	bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
-	unsigned int cpu_port = dev->cpu_port;
 	struct b53_vlan *vl;
 	u16 vid;
 	u16 pvid;
 		b53_get_vlan_entry(dev, vid, vl);
 		vl->members &= ~BIT(port);
-		if ((vl->members & BIT(cpu_port)) == BIT(cpu_port))
-			vl->members = 0;
 		if (pvid == vid) {
 			if (is5325(dev) || is5365(dev))
 				pvid = 0;
 		}
-		if (untagged) {
+		if (untagged)
 			vl->untag &= ~(BIT(port));
-			if ((vl->untag & BIT(cpu_port)) == BIT(cpu_port))
-				vl->untag = 0;
-		}
 		b53_set_vlan_entry(dev, vid, vl);
 		b53_fast_age_vlan(dev, vid);
 	}
 	b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid);
-	b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(cpu_port), pvid);
 	b53_fast_age_vlan(dev, pvid);
 	return 0;

drivers/net/ethernet/arc/emac_main.c+4−3

 		if (ndev->flags & IFF_ALLMULTI) {
 			arc_reg_set(priv, R_LAFL, ~0);
 			arc_reg_set(priv, R_LAFH, ~0);
-		} else {
+		} else if (ndev->flags & IFF_MULTICAST) {
 			struct netdev_hw_addr *ha;
 			unsigned int filter[2] = { 0, 0 };
 			int bit;
 			arc_reg_set(priv, R_LAFL, filter[0]);
 			arc_reg_set(priv, R_LAFH, filter[1]);
+		} else {
+			arc_reg_set(priv, R_LAFL, 0);
+			arc_reg_set(priv, R_LAFH, 0);
 		}
 	}
 }
 	ndev->netdev_ops = &arc_emac_netdev_ops;
 	ndev->ethtool_ops = &arc_emac_ethtool_ops;
 	ndev->watchdog_timeo = TX_TIMEOUT;
-	/* FIXME :: no multicast support yet */
-	ndev->flags &= ~IFF_MULTICAST;
 	priv = netdev_priv(ndev);
 	priv->dev = dev;

drivers/net/ethernet/broadcom/bnxt/bnxt.c+4−0

 		napi_hash_del(&bnapi->napi);
 		netif_napi_del(&bnapi->napi);
 	}
+	/* We called napi_hash_del() before netif_napi_del(), we need
+	 * to respect an RCU grace period before freeing napi structures.
+	 */
+	synchronize_net();
 }
 static void bnxt_init_napi(struct bnxt *bp)

drivers/net/ethernet/cadence/macb.c+6−0

 		lp->skb_length = skb->len;
 		lp->skb_physaddr = dma_map_single(NULL, skb->data, skb->len,
 							DMA_TO_DEVICE);
+		if (dma_mapping_error(NULL, lp->skb_physaddr)) {
+			dev_kfree_skb_any(skb);
+			dev->stats.tx_dropped++;
+			netdev_err(dev, "%s: DMA mapping error\n", __func__);
+			return NETDEV_TX_OK;
+		}
 		/* Set address of the data in the Transmit Address register */
 		macb_writel(lp, TAR, lp->skb_physaddr);

drivers/net/ethernet/cavium/thunder/nic.h+36−28

@@ -47,7 +47,7 @@ · 46 unmodified lines
47		47
48	/* Min/Max packet size */	48	/* Min/Max packet size */
49	#define NIC_HW_MIN_FRS 64	49	#define NIC_HW_MIN_FRS 64
50	#define NIC_HW_MAX_FRS 9200 /* 9216 max packet including FCS */	50	#define NIC_HW_MAX_FRS 9190 /* Excluding L2 header and FCS */
51		51
52	/* Max pkinds */	52	/* Max pkinds */
53	#define NIC_MAX_PKIND 16	53	#define NIC_MAX_PKIND 16
@@ -178,11 +178,11 @@ enum tx_stats_reg_offset { · 124 unmodified lines
178		178
179	struct nicvf_hw_stats {	179	struct nicvf_hw_stats {
180	u64 rx_bytes;	180	u64 rx_bytes;
		181	u64 rx_frames;
181	u64 rx_ucast_frames;	182	u64 rx_ucast_frames;
182	u64 rx_bcast_frames;	183	u64 rx_bcast_frames;
183	u64 rx_mcast_frames;	184	u64 rx_mcast_frames;
184	u64 rx_fcs_errors;	185	u64 rx_drops;
185	u64 rx_l2_errors;
186	u64 rx_drop_red;	186	u64 rx_drop_red;
187	u64 rx_drop_red_bytes;	187	u64 rx_drop_red_bytes;
188	u64 rx_drop_overrun;	188	u64 rx_drop_overrun;
@@ -191,6 +191,19 @@ struct nicvf_hw_stats { · 2 unmodified lines
191	u64 rx_drop_mcast;	191	u64 rx_drop_mcast;
192	u64 rx_drop_l3_bcast;	192	u64 rx_drop_l3_bcast;
193	u64 rx_drop_l3_mcast;	193	u64 rx_drop_l3_mcast;
		194	u64 rx_fcs_errors;
		195	u64 rx_l2_errors;
		196
		197	u64 tx_bytes;
		198	u64 tx_frames;
		199	u64 tx_ucast_frames;
		200	u64 tx_bcast_frames;
		201	u64 tx_mcast_frames;
		202	u64 tx_drops;
		203	};
		204
		205	struct nicvf_drv_stats {
		206	/* CQE Rx errs */
194	u64 rx_bgx_truncated_pkts;	207	u64 rx_bgx_truncated_pkts;
195	u64 rx_jabber_errs;	208	u64 rx_jabber_errs;
196	u64 rx_fcs_errs;	209	u64 rx_fcs_errs;
@@ -216,34 +229,30 @@ struct nicvf_hw_stats { · 19 unmodified lines
216	u64 rx_l4_pclp;	229	u64 rx_l4_pclp;
217	u64 rx_truncated_pkts;	230	u64 rx_truncated_pkts;
218		231
219	u64 tx_bytes_ok;	232	/* CQE Tx errs */
220	u64 tx_ucast_frames_ok;	233	u64 tx_desc_fault;
221	u64 tx_bcast_frames_ok;	234	u64 tx_hdr_cons_err;
222	u64 tx_mcast_frames_ok;	235	u64 tx_subdesc_err;
223	u64 tx_drops;	236	u64 tx_max_size_exceeded;
224	};	237	u64 tx_imm_size_oflow;
225		238	u64 tx_data_seq_err;
226	struct nicvf_drv_stats {	239	u64 tx_mem_seq_err;
227	/* Rx */	240	u64 tx_lock_viol;
228	u64 rx_frames_ok;	241	u64 tx_data_fault;
229	u64 rx_frames_64;	242	u64 tx_tstmp_conflict;
230	u64 rx_frames_127;	243	u64 tx_tstmp_timeout;
231	u64 rx_frames_255;	244	u64 tx_mem_fault;
232	u64 rx_frames_511;	245	u64 tx_csum_overlap;
233	u64 rx_frames_1023;	246	u64 tx_csum_overflow;
234	u64 rx_frames_1518;	247
235	u64 rx_frames_jumbo;	248	/* driver debug stats */
236	u64 rx_drops;
237
238	u64 rcv_buffer_alloc_failures;	249	u64 rcv_buffer_alloc_failures;
239
240	/* Tx */
241	u64 tx_frames_ok;
242	u64 tx_drops;
243	u64 tx_tso;	250	u64 tx_tso;
244	u64 tx_timeout;	251	u64 tx_timeout;
245	u64 txq_stop;	252	u64 txq_stop;
246	u64 txq_wake;	253	u64 txq_wake;
		254
		255	struct u64_stats_sync syncp;
247	};	256	};
248		257
249	struct nicvf {	258	struct nicvf {
@@ -282,7 +291,6 @@ struct nicvf { · 32 unmodified lines
282		291
283	u8 node;	292	u8 node;
284	u8 cpi_alg;	293	u8 cpi_alg;
285	u16 mtu;
286	bool link_up;	294	bool link_up;
287	u8 duplex;	295	u8 duplex;
288	u32 speed;	296	u32 speed;
@@ -298,7 +306,7 @@ struct nicvf { · 9 unmodified lines
298		306
299	/* Stats */	307	/* Stats */
300	struct nicvf_hw_stats hw_stats;	308	struct nicvf_hw_stats hw_stats;
301	struct nicvf_drv_stats drv_stats;	309	struct nicvf_drv_stats __percpu *drv_stats;
302	struct bgx_stats bgx_stats;	310	struct bgx_stats bgx_stats;
303		311
304	/* MSI-X */	312	/* MSI-X */

drivers/net/ethernet/cavium/thunder/nic_main.c+26−11

@@ -11,6 +11,7 @@ · 10 unmodified lines
11	#include <linux/pci.h>	11	#include <linux/pci.h>
12	#include <linux/etherdevice.h>	12	#include <linux/etherdevice.h>
13	#include <linux/of.h>	13	#include <linux/of.h>
		14	#include <linux/if_vlan.h>
14		15
15	#include "nic_reg.h"	16	#include "nic_reg.h"
16	#include "nic.h"	17	#include "nic.h"
@@ -260,18 +261,31 @@ static void nic_get_bgx_stats(struct nicpf nic, struct bgx_stats_msg bgx) · 243 unmodified lines
260	/* Update hardware min/max frame size */	261	/* Update hardware min/max frame size */
261	static int nic_update_hw_frs(struct nicpf *nic, int new_frs, int vf)	262	static int nic_update_hw_frs(struct nicpf *nic, int new_frs, int vf)
262	{	263	{
263	if ((new_frs > NIC_HW_MAX_FRS) \|\| (new_frs < NIC_HW_MIN_FRS)) {	264	int bgx, lmac, lmac_cnt;
264	dev_err(&nic->pdev->dev,	265	u64 lmac_credits;
265	"Invalid MTU setting from VF%d rejected, should be between %d and %d\n",	266
266	vf, NIC_HW_MIN_FRS, NIC_HW_MAX_FRS);	267	if ((new_frs > NIC_HW_MAX_FRS) \|\| (new_frs < NIC_HW_MIN_FRS))
267	return 1;	268	return 1;
268	}
269	new_frs += ETH_HLEN;
270	if (new_frs <= nic->pkind.maxlen)
271	return 0;
272		269
273	nic->pkind.maxlen = new_frs;	270	bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
274	nic_reg_write(nic, NIC_PF_PKIND_0_15_CFG, (u64 )&nic->pkind);	271	lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
		272	lmac += bgx * MAX_LMAC_PER_BGX;
		273
		274	new_frs += VLAN_ETH_HLEN + ETH_FCS_LEN + 4;
		275
		276	/* Update corresponding LMAC credits */
		277	lmac_cnt = bgx_get_lmac_count(nic->node, bgx);
		278	lmac_credits = nic_reg_read(nic, NIC_PF_LMAC_0_7_CREDIT + (lmac * 8));
		279	lmac_credits &= ~(0xFFFFFULL << 12);
		280	lmac_credits \|= (((((48 * 1024) / lmac_cnt) - new_frs) / 16) << 12);
		281	nic_reg_write(nic, NIC_PF_LMAC_0_7_CREDIT + (lmac * 8), lmac_credits);
		282
		283	/* Enforce MTU in HW
		284	* This config is supported only from 88xx pass 2.0 onwards.
		285	*/
		286	if (!pass1_silicon(nic->pdev))
		287	nic_reg_write(nic,
		288	NIC_PF_LMAC_0_7_CFG2 + (lmac * 8), new_frs);
275	return 0;	289	return 0;
276	}	290	}
277		291
@@ -464,7 +478,7 @@ static int nic_init_hw(struct nicpf *nic) · 186 unmodified lines
464		478
465	/* PKIND configuration */	479	/* PKIND configuration */
466	nic->pkind.minlen = 0;	480	nic->pkind.minlen = 0;
467	nic->pkind.maxlen = NIC_HW_MAX_FRS + ETH_HLEN;	481	nic->pkind.maxlen = NIC_HW_MAX_FRS + VLAN_ETH_HLEN + ETH_FCS_LEN + 4;
468	nic->pkind.lenerr_en = 1;	482	nic->pkind.lenerr_en = 1;
469	nic->pkind.rx_hdr = 0;	483	nic->pkind.rx_hdr = 0;
470	nic->pkind.hdr_sl = 0;	484	nic->pkind.hdr_sl = 0;
@@ -837,6 +851,7 @@ static int nic_reset_stat_counters(struct nicpf *nic, · 366 unmodified lines
837	nic_reg_write(nic, reg_addr, 0);	851	nic_reg_write(nic, reg_addr, 0);
838	}	852	}
839	}	853	}
		854
840	return 0;	855	return 0;
841	}	856	}
842		857

drivers/net/ethernet/cavium/thunder/nic_reg.h+1−0

@@ -106,6 +106,7 @@ · 105 unmodified lines
106	#define NIC_PF_MPI_0_2047_CFG (0x210000)	106	#define NIC_PF_MPI_0_2047_CFG (0x210000)
107	#define NIC_PF_RSSI_0_4097_RQ (0x220000)	107	#define NIC_PF_RSSI_0_4097_RQ (0x220000)
108	#define NIC_PF_LMAC_0_7_CFG (0x240000)	108	#define NIC_PF_LMAC_0_7_CFG (0x240000)
		109	#define NIC_PF_LMAC_0_7_CFG2 (0x240100)
109	#define NIC_PF_LMAC_0_7_SW_XOFF (0x242000)	110	#define NIC_PF_LMAC_0_7_SW_XOFF (0x242000)
110	#define NIC_PF_LMAC_0_7_CREDIT (0x244000)	111	#define NIC_PF_LMAC_0_7_CREDIT (0x244000)
111	#define NIC_PF_CHAN_0_255_TX_CFG (0x400000)	112	#define NIC_PF_CHAN_0_255_TX_CFG (0x400000)

drivers/net/ethernet/cavium/thunder/nicvf_ethtool.c+59−46

 static const struct nicvf_stat nicvf_hw_stats[] = {
 	NICVF_HW_STAT(rx_bytes),
+	NICVF_HW_STAT(rx_frames),
 	NICVF_HW_STAT(rx_ucast_frames),
 	NICVF_HW_STAT(rx_bcast_frames),
 	NICVF_HW_STAT(rx_mcast_frames),
-	NICVF_HW_STAT(rx_fcs_errors),
+	NICVF_HW_STAT(rx_drops),
-	NICVF_HW_STAT(rx_l2_errors),
 	NICVF_HW_STAT(rx_drop_red),
 	NICVF_HW_STAT(rx_drop_red_bytes),
 	NICVF_HW_STAT(rx_drop_overrun),
 	NICVF_HW_STAT(rx_drop_mcast),
 	NICVF_HW_STAT(rx_drop_l3_bcast),
 	NICVF_HW_STAT(rx_drop_l3_mcast),
-	NICVF_HW_STAT(rx_bgx_truncated_pkts),
+	NICVF_HW_STAT(rx_fcs_errors),
-	NICVF_HW_STAT(rx_jabber_errs),
+	NICVF_HW_STAT(rx_l2_errors),
-	NICVF_HW_STAT(rx_fcs_errs),
+	NICVF_HW_STAT(tx_bytes),
-	NICVF_HW_STAT(rx_bgx_errs),
+	NICVF_HW_STAT(tx_frames),
-	NICVF_HW_STAT(rx_prel2_errs),
+	NICVF_HW_STAT(tx_ucast_frames),
-	NICVF_HW_STAT(rx_l2_hdr_malformed),
+	NICVF_HW_STAT(tx_bcast_frames),
-	NICVF_HW_STAT(rx_oversize),
+	NICVF_HW_STAT(tx_mcast_frames),
-	NICVF_HW_STAT(rx_undersize),
+	NICVF_HW_STAT(tx_drops),
-	NICVF_HW_STAT(rx_l2_len_mismatch),
-	NICVF_HW_STAT(rx_l2_pclp),
-	NICVF_HW_STAT(rx_ip_ver_errs),
-	NICVF_HW_STAT(rx_ip_csum_errs),
-	NICVF_HW_STAT(rx_ip_hdr_malformed),
-	NICVF_HW_STAT(rx_ip_payload_malformed),
-	NICVF_HW_STAT(rx_ip_ttl_errs),
-	NICVF_HW_STAT(rx_l3_pclp),
-	NICVF_HW_STAT(rx_l4_malformed),
-	NICVF_HW_STAT(rx_l4_csum_errs),
-	NICVF_HW_STAT(rx_udp_len_errs),
-	NICVF_HW_STAT(rx_l4_port_errs),
-	NICVF_HW_STAT(rx_tcp_flag_errs),
-	NICVF_HW_STAT(rx_tcp_offset_errs),
-	NICVF_HW_STAT(rx_l4_pclp),
-	NICVF_HW_STAT(rx_truncated_pkts),
-	NICVF_HW_STAT(tx_bytes_ok),
-	NICVF_HW_STAT(tx_ucast_frames_ok),
-	NICVF_HW_STAT(tx_bcast_frames_ok),
-	NICVF_HW_STAT(tx_mcast_frames_ok),
 };
 static const struct nicvf_stat nicvf_drv_stats[] = {
-	NICVF_DRV_STAT(rx_frames_ok),
+	NICVF_DRV_STAT(rx_bgx_truncated_pkts),
-	NICVF_DRV_STAT(rx_frames_64),
+	NICVF_DRV_STAT(rx_jabber_errs),
-	NICVF_DRV_STAT(rx_frames_127),
+	NICVF_DRV_STAT(rx_fcs_errs),
-	NICVF_DRV_STAT(rx_frames_255),
+	NICVF_DRV_STAT(rx_bgx_errs),
-	NICVF_DRV_STAT(rx_frames_511),
+	NICVF_DRV_STAT(rx_prel2_errs),
-	NICVF_DRV_STAT(rx_frames_1023),
+	NICVF_DRV_STAT(rx_l2_hdr_malformed),
-	NICVF_DRV_STAT(rx_frames_1518),
+	NICVF_DRV_STAT(rx_oversize),
-	NICVF_DRV_STAT(rx_frames_jumbo),
+	NICVF_DRV_STAT(rx_undersize),
-	NICVF_DRV_STAT(rx_drops),
+	NICVF_DRV_STAT(rx_l2_len_mismatch),
+	NICVF_DRV_STAT(rx_l2_pclp),
+	NICVF_DRV_STAT(rx_ip_ver_errs),
+	NICVF_DRV_STAT(rx_ip_csum_errs),
+	NICVF_DRV_STAT(rx_ip_hdr_malformed),
+	NICVF_DRV_STAT(rx_ip_payload_malformed),
+	NICVF_DRV_STAT(rx_ip_ttl_errs),
+	NICVF_DRV_STAT(rx_l3_pclp),
+	NICVF_DRV_STAT(rx_l4_malformed),
+	NICVF_DRV_STAT(rx_l4_csum_errs),
+	NICVF_DRV_STAT(rx_udp_len_errs),
+	NICVF_DRV_STAT(rx_l4_port_errs),
+	NICVF_DRV_STAT(rx_tcp_flag_errs),
+	NICVF_DRV_STAT(rx_tcp_offset_errs),
+	NICVF_DRV_STAT(rx_l4_pclp),
+	NICVF_DRV_STAT(rx_truncated_pkts),
+	NICVF_DRV_STAT(tx_desc_fault),
+	NICVF_DRV_STAT(tx_hdr_cons_err),
+	NICVF_DRV_STAT(tx_subdesc_err),
+	NICVF_DRV_STAT(tx_max_size_exceeded),
+	NICVF_DRV_STAT(tx_imm_size_oflow),
+	NICVF_DRV_STAT(tx_data_seq_err),
+	NICVF_DRV_STAT(tx_mem_seq_err),
+	NICVF_DRV_STAT(tx_lock_viol),
+	NICVF_DRV_STAT(tx_data_fault),
+	NICVF_DRV_STAT(tx_tstmp_conflict),
+	NICVF_DRV_STAT(tx_tstmp_timeout),
+	NICVF_DRV_STAT(tx_mem_fault),
+	NICVF_DRV_STAT(tx_csum_overlap),
+	NICVF_DRV_STAT(tx_csum_overflow),
 	NICVF_DRV_STAT(rcv_buffer_alloc_failures),
-	NICVF_DRV_STAT(tx_frames_ok),
 	NICVF_DRV_STAT(tx_tso),
-	NICVF_DRV_STAT(tx_drops),
 	NICVF_DRV_STAT(tx_timeout),
 	NICVF_DRV_STAT(txq_stop),
 	NICVF_DRV_STAT(txq_wake),
 				    struct ethtool_stats *stats, u64 *data)
 {
 	struct nicvf *nic = netdev_priv(netdev);
-	int stat;
+	int stat, tmp_stats;
-	int sqs;
+	int sqs, cpu;
 	nicvf_update_stats(nic);
 	for (stat = 0; stat < nicvf_n_hw_stats; stat++)
 		*(data++) = ((u64 *)&nic->hw_stats)
 				[nicvf_hw_stats[stat].index];
-	for (stat = 0; stat < nicvf_n_drv_stats; stat++)
+	for (stat = 0; stat < nicvf_n_drv_stats; stat++) {
-		*(data++) = ((u64 *)&nic->drv_stats)
+		tmp_stats = 0;
-				[nicvf_drv_stats[stat].index];
+		for_each_possible_cpu(cpu)
+			tmp_stats += ((u64 *)per_cpu_ptr(nic->drv_stats, cpu))
+				     [nicvf_drv_stats[stat].index];
+		*(data++) = tmp_stats;
+	}
 	nicvf_get_qset_stats(nic, stats, &data);

drivers/net/ethernet/cavium/thunder/nicvf_main.c+83−75

@@ -69,25 +69,6 @@ static inline u8 nicvf_netdev_qidx(struct nicvf *nic, u8 qidx) · 68 unmodified lines
69	return qidx;	69	return qidx;
70	}	70	}
71		71
72	static inline void nicvf_set_rx_frame_cnt(struct nicvf *nic,
73	struct sk_buff *skb)
74	{
75	if (skb->len <= 64)
76	nic->drv_stats.rx_frames_64++;
77	else if (skb->len <= 127)
78	nic->drv_stats.rx_frames_127++;
79	else if (skb->len <= 255)
80	nic->drv_stats.rx_frames_255++;
81	else if (skb->len <= 511)
82	nic->drv_stats.rx_frames_511++;
83	else if (skb->len <= 1023)
84	nic->drv_stats.rx_frames_1023++;
85	else if (skb->len <= 1518)
86	nic->drv_stats.rx_frames_1518++;
87	else
88	nic->drv_stats.rx_frames_jumbo++;
89	}
90
91	/* The Cavium ThunderX network controller can only be found in SoCs	72	/* The Cavium ThunderX network controller can only be found in SoCs
92	* containing the ThunderX ARM64 CPU implementation. All accesses to the device	73	* containing the ThunderX ARM64 CPU implementation. All accesses to the device
93	* registers on this platform are implicitly strongly ordered with respect	74	* registers on this platform are implicitly strongly ordered with respect
@@ -492,9 +473,6 @@ int nicvf_set_real_num_queues(struct net_device *netdev, · 398 unmodified lines
492	static int nicvf_init_resources(struct nicvf *nic)	473	static int nicvf_init_resources(struct nicvf *nic)
493	{	474	{
494	int err;	475	int err;
495	union nic_mbx mbx = {};
496
497	mbx.msg.msg = NIC_MBOX_MSG_CFG_DONE;
498		476
499	/* Enable Qset */	477	/* Enable Qset */
500	nicvf_qset_config(nic, true);	478	nicvf_qset_config(nic, true);
@@ -507,14 +485,10 @@ static int nicvf_init_resources(struct nicvf *nic) · 6 unmodified lines
507	return err;	485	return err;
508	}	486	}
509		487
510	/* Send VF config done msg to PF */
511	nicvf_write_to_mbx(nic, &mbx);
512
513	return 0;	488	return 0;
514	}	489	}
515		490
516	static void nicvf_snd_pkt_handler(struct net_device *netdev,	491	static void nicvf_snd_pkt_handler(struct net_device *netdev,
517	struct cmp_queue *cq,
518	struct cqe_send_t *cqe_tx,	492	struct cqe_send_t *cqe_tx,
519	int cqe_type, int budget,	493	int cqe_type, int budget,
520	unsigned int tx_pkts, unsigned int tx_bytes)	494	unsigned int tx_pkts, unsigned int tx_bytes)
@@ -536,7 +510,7 @@ static void nicvf_snd_pkt_handler(struct net_device *netdev, · 15 unmodified lines
536	__func__, cqe_tx->sq_qs, cqe_tx->sq_idx,	510	__func__, cqe_tx->sq_qs, cqe_tx->sq_idx,
537	cqe_tx->sqe_ptr, hdr->subdesc_cnt);	511	cqe_tx->sqe_ptr, hdr->subdesc_cnt);
538		512
539	nicvf_check_cqe_tx_errs(nic, cq, cqe_tx);	513	nicvf_check_cqe_tx_errs(nic, cqe_tx);
540	skb = (struct sk_buff *)sq->skbuff[cqe_tx->sqe_ptr];	514	skb = (struct sk_buff *)sq->skbuff[cqe_tx->sqe_ptr];
541	if (skb) {	515	if (skb) {
542	/* Check for dummy descriptor used for HW TSO offload on 88xx */	516	/* Check for dummy descriptor used for HW TSO offload on 88xx */
@@ -630,8 +604,6 @@ static void nicvf_rcv_pkt_handler(struct net_device *netdev, · 87 unmodified lines
630	return;	604	return;
631	}	605	}
632		606
633	nicvf_set_rx_frame_cnt(nic, skb);
634
635	nicvf_set_rxhash(netdev, cqe_rx, skb);	607	nicvf_set_rxhash(netdev, cqe_rx, skb);
636		608
637	skb_record_rx_queue(skb, rq_idx);	609	skb_record_rx_queue(skb, rq_idx);
@@ -703,7 +675,7 @@ loop: · 65 unmodified lines
703	work_done++;	675	work_done++;
704	break;	676	break;
705	case CQE_TYPE_SEND:	677	case CQE_TYPE_SEND:
706	nicvf_snd_pkt_handler(netdev, cq,	678	nicvf_snd_pkt_handler(netdev,
707	(void *)cq_desc, CQE_TYPE_SEND,	679	(void *)cq_desc, CQE_TYPE_SEND,
708	budget, &tx_pkts, &tx_bytes);	680	budget, &tx_pkts, &tx_bytes);
709	tx_done++;	681	tx_done++;
@@ -740,7 +712,7 @@ done: · 30 unmodified lines
740	nic = nic->pnicvf;	712	nic = nic->pnicvf;
741	if (netif_tx_queue_stopped(txq) && netif_carrier_ok(netdev)) {	713	if (netif_tx_queue_stopped(txq) && netif_carrier_ok(netdev)) {
742	netif_tx_start_queue(txq);	714	netif_tx_start_queue(txq);
743	nic->drv_stats.txq_wake++;	715	this_cpu_inc(nic->drv_stats->txq_wake);
744	if (netif_msg_tx_err(nic))	716	if (netif_msg_tx_err(nic))
745	netdev_warn(netdev,	717	netdev_warn(netdev,
746	"%s: Transmit queue wakeup SQ%d\n",	718	"%s: Transmit queue wakeup SQ%d\n",
@@ -1084,7 +1056,7 @@ static netdev_tx_t nicvf_xmit(struct sk_buff skb, struct net_device netdev) · 337 unmodified lines
1084		1056
1085	if (!netif_tx_queue_stopped(txq) && !nicvf_sq_append_skb(nic, skb)) {	1057	if (!netif_tx_queue_stopped(txq) && !nicvf_sq_append_skb(nic, skb)) {
1086	netif_tx_stop_queue(txq);	1058	netif_tx_stop_queue(txq);
1087	nic->drv_stats.txq_stop++;	1059	this_cpu_inc(nic->drv_stats->txq_stop);
1088	if (netif_msg_tx_err(nic))	1060	if (netif_msg_tx_err(nic))
1089	netdev_warn(netdev,	1061	netdev_warn(netdev,
1090	"%s: Transmit ring full, stopping SQ%d\n",	1062	"%s: Transmit ring full, stopping SQ%d\n",
@@ -1189,14 +1161,24 @@ int nicvf_stop(struct net_device *netdev) · 98 unmodified lines
1189	return 0;	1161	return 0;
1190	}	1162	}
1191		1163
		1164	static int nicvf_update_hw_max_frs(struct nicvf *nic, int mtu)
		1165	{
		1166	union nic_mbx mbx = {};
		1167
		1168	mbx.frs.msg = NIC_MBOX_MSG_SET_MAX_FRS;
		1169	mbx.frs.max_frs = mtu;
		1170	mbx.frs.vf_id = nic->vf_id;
		1171
		1172	return nicvf_send_msg_to_pf(nic, &mbx);
		1173	}
		1174
1192	int nicvf_open(struct net_device *netdev)	1175	int nicvf_open(struct net_device *netdev)
1193	{	1176	{
1194	int err, qidx;	1177	int cpu, err, qidx;
1195	struct nicvf *nic = netdev_priv(netdev);	1178	struct nicvf *nic = netdev_priv(netdev);
1196	struct queue_set *qs = nic->qs;	1179	struct queue_set *qs = nic->qs;
1197	struct nicvf_cq_poll *cq_poll = NULL;	1180	struct nicvf_cq_poll *cq_poll = NULL;
1198		1181	union nic_mbx mbx = {};
1199	nic->mtu = netdev->mtu;
1200		1182
1201	netif_carrier_off(netdev);	1183	netif_carrier_off(netdev);
1202		1184
@@ -1248,9 +1230,17 @@ int nicvf_open(struct net_device *netdev) · 45 unmodified lines
1248	if (nic->sqs_mode)	1230	if (nic->sqs_mode)
1249	nicvf_get_primary_vf_struct(nic);	1231	nicvf_get_primary_vf_struct(nic);
1250		1232
1251	/* Configure receive side scaling */	1233	/* Configure receive side scaling and MTU */
1252	if (!nic->sqs_mode)	1234	if (!nic->sqs_mode) {
1253	nicvf_rss_init(nic);	1235	nicvf_rss_init(nic);
		1236	if (nicvf_update_hw_max_frs(nic, netdev->mtu))
		1237	goto cleanup;
		1238
		1239	/* Clear percpu stats */
		1240	for_each_possible_cpu(cpu)
		1241	memset(per_cpu_ptr(nic->drv_stats, cpu), 0,
		1242	sizeof(struct nicvf_drv_stats));
		1243	}
1254		1244
1255	err = nicvf_register_interrupts(nic);	1245	err = nicvf_register_interrupts(nic);
1256	if (err)	1246	if (err)
@@ -1276,8 +1266,9 @@ int nicvf_open(struct net_device *netdev) · 19 unmodified lines
1276	for (qidx = 0; qidx < qs->rbdr_cnt; qidx++)	1266	for (qidx = 0; qidx < qs->rbdr_cnt; qidx++)
1277	nicvf_enable_intr(nic, NICVF_INTR_RBDR, qidx);	1267	nicvf_enable_intr(nic, NICVF_INTR_RBDR, qidx);
1278		1268
1279	nic->drv_stats.txq_stop = 0;	1269	/* Send VF config done msg to PF */
1280	nic->drv_stats.txq_wake = 0;	1270	mbx.msg.msg = NIC_MBOX_MSG_CFG_DONE;
		1271	nicvf_write_to_mbx(nic, &mbx);
1281		1272
1282	return 0;	1273	return 0;
1283	cleanup:	1274	cleanup:
@@ -1297,25 +1288,20 @@ napi_del: · 13 unmodified lines
1297	return err;	1288	return err;
1298	}	1289	}
1299		1290
1300	static int nicvf_update_hw_max_frs(struct nicvf *nic, int mtu)
1301	{
1302	union nic_mbx mbx = {};
1303
1304	mbx.frs.msg = NIC_MBOX_MSG_SET_MAX_FRS;
1305	mbx.frs.max_frs = mtu;
1306	mbx.frs.vf_id = nic->vf_id;
1307
1308	return nicvf_send_msg_to_pf(nic, &mbx);
1309	}
1310
1311	static int nicvf_change_mtu(struct net_device *netdev, int new_mtu)	1291	static int nicvf_change_mtu(struct net_device *netdev, int new_mtu)
1312	{	1292	{
1313	struct nicvf *nic = netdev_priv(netdev);	1293	struct nicvf *nic = netdev_priv(netdev);
		1294	int orig_mtu = netdev->mtu;
1314		1295
1315	if (nicvf_update_hw_max_frs(nic, new_mtu))
1316	return -EINVAL;
1317	netdev->mtu = new_mtu;	1296	netdev->mtu = new_mtu;
1318	nic->mtu = new_mtu;	1297
		1298	if (!netif_running(netdev))
		1299	return 0;
		1300
		1301	if (nicvf_update_hw_max_frs(nic, new_mtu)) {
		1302	netdev->mtu = orig_mtu;
		1303	return -EINVAL;
		1304	}
1319		1305
1320	return 0;	1306	return 0;
1321	}	1307	}
@@ -1373,9 +1359,10 @@ void nicvf_update_lmac_stats(struct nicvf *nic) · 51 unmodified lines
1373		1359
1374	void nicvf_update_stats(struct nicvf *nic)	1360	void nicvf_update_stats(struct nicvf *nic)
1375	{	1361	{
1376	int qidx;	1362	int qidx, cpu;
		1363	u64 tmp_stats = 0;
1377	struct nicvf_hw_stats *stats = &nic->hw_stats;	1364	struct nicvf_hw_stats *stats = &nic->hw_stats;
1378	struct nicvf_drv_stats *drv_stats = &nic->drv_stats;	1365	struct nicvf_drv_stats *drv_stats;
1379	struct queue_set *qs = nic->qs;	1366	struct queue_set *qs = nic->qs;
1380		1367
1381	#define GET_RX_STATS(reg) \	1368	#define GET_RX_STATS(reg) \
@@ -1398,21 +1385,33 @@ void nicvf_update_stats(struct nicvf *nic) · 16 unmodified lines
1398	stats->rx_drop_l3_bcast = GET_RX_STATS(RX_DRP_L3BCAST);	1385	stats->rx_drop_l3_bcast = GET_RX_STATS(RX_DRP_L3BCAST);
1399	stats->rx_drop_l3_mcast = GET_RX_STATS(RX_DRP_L3MCAST);	1386	stats->rx_drop_l3_mcast = GET_RX_STATS(RX_DRP_L3MCAST);
1400		1387
1401	stats->tx_bytes_ok = GET_TX_STATS(TX_OCTS);	1388	stats->tx_bytes = GET_TX_STATS(TX_OCTS);
1402	stats->tx_ucast_frames_ok = GET_TX_STATS(TX_UCAST);	1389	stats->tx_ucast_frames = GET_TX_STATS(TX_UCAST);
1403	stats->tx_bcast_frames_ok = GET_TX_STATS(TX_BCAST);	1390	stats->tx_bcast_frames = GET_TX_STATS(TX_BCAST);
1404	stats->tx_mcast_frames_ok = GET_TX_STATS(TX_MCAST);	1391	stats->tx_mcast_frames = GET_TX_STATS(TX_MCAST);
1405	stats->tx_drops = GET_TX_STATS(TX_DROP);	1392	stats->tx_drops = GET_TX_STATS(TX_DROP);
1406		1393
1407	drv_stats->tx_frames_ok = stats->tx_ucast_frames_ok +	1394	/* On T88 pass 2.0, the dummy SQE added for TSO notification
1408	stats->tx_bcast_frames_ok +	1395	* via CQE has 'dont_send' set. Hence HW drops the pkt pointed
1409	stats->tx_mcast_frames_ok;	1396	* pointed by dummy SQE and results in tx_drops counter being
1410	drv_stats->rx_frames_ok = stats->rx_ucast_frames +	1397	* incremented. Subtracting it from tx_tso counter will give
1411	stats->rx_bcast_frames +	1398	* exact tx_drops counter.
1412	stats->rx_mcast_frames;	1399	*/
1413	drv_stats->rx_drops = stats->rx_drop_red +	1400	if (nic->t88 && nic->hw_tso) {
1414	stats->rx_drop_overrun;	1401	for_each_possible_cpu(cpu) {
1415	drv_stats->tx_drops = stats->tx_drops;	1402	drv_stats = per_cpu_ptr(nic->drv_stats, cpu);
		1403	tmp_stats += drv_stats->tx_tso;
		1404	}
		1405	stats->tx_drops = tmp_stats - stats->tx_drops;
		1406	}
		1407	stats->tx_frames = stats->tx_ucast_frames +
		1408	stats->tx_bcast_frames +
		1409	stats->tx_mcast_frames;
		1410	stats->rx_frames = stats->rx_ucast_frames +
		1411	stats->rx_bcast_frames +
		1412	stats->rx_mcast_frames;
		1413	stats->rx_drops = stats->rx_drop_red +
		1414	stats->rx_drop_overrun;
1416		1415
1417	/* Update RQ and SQ stats */	1416	/* Update RQ and SQ stats */
1418	for (qidx = 0; qidx < qs->rq_cnt; qidx++)	1417	for (qidx = 0; qidx < qs->rq_cnt; qidx++)
@@ -1426,18 +1425,17 @@ static struct rtnl_link_stats64 nicvf_get_stats64(struct net_device netdev, · 7 unmodified lines
1426	{	1425	{
1427	struct nicvf *nic = netdev_priv(netdev);	1426	struct nicvf *nic = netdev_priv(netdev);
1428	struct nicvf_hw_stats *hw_stats = &nic->hw_stats;	1427	struct nicvf_hw_stats *hw_stats = &nic->hw_stats;
1429	struct nicvf_drv_stats *drv_stats = &nic->drv_stats;
1430		1428
1431	nicvf_update_stats(nic);	1429	nicvf_update_stats(nic);
1432		1430
1433	stats->rx_bytes = hw_stats->rx_bytes;	1431	stats->rx_bytes = hw_stats->rx_bytes;
1434	stats->rx_packets = drv_stats->rx_frames_ok;	1432	stats->rx_packets = hw_stats->rx_frames;
1435	stats->rx_dropped = drv_stats->rx_drops;	1433	stats->rx_dropped = hw_stats->rx_drops;
1436	stats->multicast = hw_stats->rx_mcast_frames;	1434	stats->multicast = hw_stats->rx_mcast_frames;
1437		1435
1438	stats->tx_bytes = hw_stats->tx_bytes_ok;	1436	stats->tx_bytes = hw_stats->tx_bytes;
1439	stats->tx_packets = drv_stats->tx_frames_ok;	1437	stats->tx_packets = hw_stats->tx_frames;
1440	stats->tx_dropped = drv_stats->tx_drops;	1438	stats->tx_dropped = hw_stats->tx_drops;
1441		1439
1442	return stats;	1440	return stats;
1443	}	1441	}
@@ -1450,7 +1448,7 @@ static void nicvf_tx_timeout(struct net_device *dev) · 6 unmodified lines
1450	netdev_warn(dev, "%s: Transmit timed out, resetting\n",	1448	netdev_warn(dev, "%s: Transmit timed out, resetting\n",
1451	dev->name);	1449	dev->name);
1452		1450
1453	nic->drv_stats.tx_timeout++;	1451	this_cpu_inc(nic->drv_stats->tx_timeout);
1454	schedule_work(&nic->reset_task);	1452	schedule_work(&nic->reset_task);
1455	}	1453	}
1456		1454
@@ -1584,6 +1582,12 @@ static int nicvf_probe(struct pci_dev pdev, const struct pci_device_id ent) · 127 unmodified lines
1584	goto err_free_netdev;	1582	goto err_free_netdev;
1585	}	1583	}
1586		1584
		1585	nic->drv_stats = netdev_alloc_pcpu_stats(struct nicvf_drv_stats);
		1586	if (!nic->drv_stats) {
		1587	err = -ENOMEM;
		1588	goto err_free_netdev;
		1589	}
		1590
1587	err = nicvf_set_qset_resources(nic);	1591	err = nicvf_set_qset_resources(nic);
1588	if (err)	1592	if (err)
1589	goto err_free_netdev;	1593	goto err_free_netdev;
@@ -1646,6 +1650,8 @@ err_unregister_interrupts: · 56 unmodified lines
1646	nicvf_unregister_interrupts(nic);	1650	nicvf_unregister_interrupts(nic);
1647	err_free_netdev:	1651	err_free_netdev:
1648	pci_set_drvdata(pdev, NULL);	1652	pci_set_drvdata(pdev, NULL);
		1653	if (nic->drv_stats)
		1654	free_percpu(nic->drv_stats);
1649	free_netdev(netdev);	1655	free_netdev(netdev);
1650	err_release_regions:	1656	err_release_regions:
1651	pci_release_regions(pdev);	1657	pci_release_regions(pdev);
@@ -1673,6 +1679,8 @@ static void nicvf_remove(struct pci_dev *pdev) · 21 unmodified lines
1673	unregister_netdev(pnetdev);	1679	unregister_netdev(pnetdev);
1674	nicvf_unregister_interrupts(nic);	1680	nicvf_unregister_interrupts(nic);
1675	pci_set_drvdata(pdev, NULL);	1681	pci_set_drvdata(pdev, NULL);
		1682	if (nic->drv_stats)
		1683	free_percpu(nic->drv_stats);
1676	free_netdev(netdev);	1684	free_netdev(netdev);
1677	pci_release_regions(pdev);	1685	pci_release_regions(pdev);
1678	pci_disable_device(pdev);	1686	pci_disable_device(pdev);

drivers/net/ethernet/cavium/thunder/nicvf_queues.c+67−51

 		nic->rb_page = alloc_pages(gfp | __GFP_COMP | __GFP_NOWARN,
 					   order);
 		if (!nic->rb_page) {
-			nic->drv_stats.rcv_buffer_alloc_failures++;
+			this_cpu_inc(nic->pnicvf->drv_stats->
+				     rcv_buffer_alloc_failures);
 			return -ENOMEM;
 		}
 		nic->rb_page_offset = 0;
 			      rbdr_idx, new_rb);
 next_rbdr:
 	/* Re-enable RBDR interrupts only if buffer allocation is success */
-	if (!nic->rb_alloc_fail && rbdr->enable)
+	if (!nic->rb_alloc_fail && rbdr->enable &&
+	    netif_running(nic->pnicvf->netdev))
 		nicvf_enable_intr(nic, NICVF_INTR_RBDR, rbdr_idx);
 	if (rbdr_idx)
 static void nicvf_free_snd_queue(struct nicvf *nic, struct snd_queue *sq)
 {
+	struct sk_buff *skb;
 	if (!sq)
 		return;
 	if (!sq->dmem.base)
 				  sq->dmem.q_len * TSO_HEADER_SIZE,
 				  sq->tso_hdrs, sq->tso_hdrs_phys);
+	/* Free pending skbs in the queue */
+	smp_rmb();
+	while (sq->head != sq->tail) {
+		skb = (struct sk_buff *)sq->skbuff[sq->head];
+		if (skb)
+			dev_kfree_skb_any(skb);
+		sq->head++;
+		sq->head &= (sq->dmem.q_len - 1);
+	}
 	kfree(sq->skbuff);
 	nicvf_free_q_desc_mem(nic, &sq->dmem);
 }
 {
 	union nic_mbx mbx = {};
-	/* Reset all RXQ's stats */
+	/* Reset all RQ/SQ and VF stats */
 	mbx.reset_stat.msg = NIC_MBOX_MSG_RESET_STAT_COUNTER;
+	mbx.reset_stat.rx_stat_mask = 0x3FFF;
+	mbx.reset_stat.tx_stat_mask = 0x1F;
 	mbx.reset_stat.rq_stat_mask = 0xFFFF;
+	mbx.reset_stat.sq_stat_mask = 0xFFFF;
 	nicvf_send_msg_to_pf(nic, &mbx);
 }
 	mbx.rq.cfg = (1ULL << 62) | (RQ_CQ_DROP << 8);
 	nicvf_send_msg_to_pf(nic, &mbx);
-	nicvf_queue_reg_write(nic, NIC_QSET_RQ_GEN_CFG, 0, 0x00);
+	if (!nic->sqs_mode && (qidx == 0)) {
-	if (!nic->sqs_mode)
+		/* Enable checking L3/L4 length and TCP/UDP checksums */
+		nicvf_queue_reg_write(nic, NIC_QSET_RQ_GEN_CFG, 0,
+				      (BIT(24) | BIT(23) | BIT(21)));
 		nicvf_config_vlan_stripping(nic, nic->netdev->features);
+	}
 	/* Enable Receive queue */
 	memset(&rq_cfg, 0, sizeof(struct rq_cfg));
 		hdr->tso_max_paysize = skb_shinfo(skb)->gso_size;
 		/* For non-tunneled pkts, point this to L2 ethertype */
 		hdr->inner_l3_offset = skb_network_offset(skb) - 2;
-		nic->drv_stats.tx_tso++;
+		this_cpu_inc(nic->pnicvf->drv_stats->tx_tso);
 	}
 }
 	nicvf_sq_doorbell(nic, skb, sq_num, desc_cnt);
-	nic->drv_stats.tx_tso++;
+	this_cpu_inc(nic->pnicvf->drv_stats->tx_tso);
 	return 1;
 }
 /* Check for errors in the receive cmp.queue entry */
 int nicvf_check_cqe_rx_errs(struct nicvf *nic, struct cqe_rx_t *cqe_rx)
 {
-	struct nicvf_hw_stats *stats = &nic->hw_stats;
 	if (!cqe_rx->err_level && !cqe_rx->err_opcode)
 		return 0;
 	switch (cqe_rx->err_opcode) {
 	case CQ_RX_ERROP_RE_PARTIAL:
-		stats->rx_bgx_truncated_pkts++;
+		this_cpu_inc(nic->drv_stats->rx_bgx_truncated_pkts);
 		break;
 	case CQ_RX_ERROP_RE_JABBER:
-		stats->rx_jabber_errs++;
+		this_cpu_inc(nic->drv_stats->rx_jabber_errs);
 		break;
 	case CQ_RX_ERROP_RE_FCS:
-		stats->rx_fcs_errs++;
+		this_cpu_inc(nic->drv_stats->rx_fcs_errs);
 		break;
 	case CQ_RX_ERROP_RE_RX_CTL:
-		stats->rx_bgx_errs++;
+		this_cpu_inc(nic->drv_stats->rx_bgx_errs);
 		break;
 	case CQ_RX_ERROP_PREL2_ERR:
-		stats->rx_prel2_errs++;
+		this_cpu_inc(nic->drv_stats->rx_prel2_errs);
 		break;
 	case CQ_RX_ERROP_L2_MAL:
-		stats->rx_l2_hdr_malformed++;
+		this_cpu_inc(nic->drv_stats->rx_l2_hdr_malformed);
 		break;
 	case CQ_RX_ERROP_L2_OVERSIZE:
-		stats->rx_oversize++;
+		this_cpu_inc(nic->drv_stats->rx_oversize);
 		break;
 	case CQ_RX_ERROP_L2_UNDERSIZE:
-		stats->rx_undersize++;
+		this_cpu_inc(nic->drv_stats->rx_undersize);
 		break;
 	case CQ_RX_ERROP_L2_LENMISM:
-		stats->rx_l2_len_mismatch++;
+		this_cpu_inc(nic->drv_stats->rx_l2_len_mismatch);
 		break;
 	case CQ_RX_ERROP_L2_PCLP:
-		stats->rx_l2_pclp++;
+		this_cpu_inc(nic->drv_stats->rx_l2_pclp);
 		break;
 	case CQ_RX_ERROP_IP_NOT:
-		stats->rx_ip_ver_errs++;
+		this_cpu_inc(nic->drv_stats->rx_ip_ver_errs);
 		break;
 	case CQ_RX_ERROP_IP_CSUM_ERR:
-		stats->rx_ip_csum_errs++;
+		this_cpu_inc(nic->drv_stats->rx_ip_csum_errs);
 		break;
 	case CQ_RX_ERROP_IP_MAL:
-		stats->rx_ip_hdr_malformed++;
+		this_cpu_inc(nic->drv_stats->rx_ip_hdr_malformed);
 		break;
 	case CQ_RX_ERROP_IP_MALD:
-		stats->rx_ip_payload_malformed++;
+		this_cpu_inc(nic->drv_stats->rx_ip_payload_malformed);
 		break;
 	case CQ_RX_ERROP_IP_HOP:
-		stats->rx_ip_ttl_errs++;
+		this_cpu_inc(nic->drv_stats->rx_ip_ttl_errs);
 		break;
 	case CQ_RX_ERROP_L3_PCLP:
-		stats->rx_l3_pclp++;
+		this_cpu_inc(nic->drv_stats->rx_l3_pclp);
 		break;
 	case CQ_RX_ERROP_L4_MAL:
-		stats->rx_l4_malformed++;
+		this_cpu_inc(nic->drv_stats->rx_l4_malformed);
 		break;
 	case CQ_RX_ERROP_L4_CHK:
-		stats->rx_l4_csum_errs++;
+		this_cpu_inc(nic->drv_stats->rx_l4_csum_errs);
 		break;
 	case CQ_RX_ERROP_UDP_LEN:
-		stats->rx_udp_len_errs++;
+		this_cpu_inc(nic->drv_stats->rx_udp_len_errs);
 		break;
 	case CQ_RX_ERROP_L4_PORT:
-		stats->rx_l4_port_errs++;
+		this_cpu_inc(nic->drv_stats->rx_l4_port_errs);
 		break;
 	case CQ_RX_ERROP_TCP_FLAG:
-		stats->rx_tcp_flag_errs++;
+		this_cpu_inc(nic->drv_stats->rx_tcp_flag_errs);
 		break;
 	case CQ_RX_ERROP_TCP_OFFSET:
-		stats->rx_tcp_offset_errs++;
+		this_cpu_inc(nic->drv_stats->rx_tcp_offset_errs);
 		break;
 	case CQ_RX_ERROP_L4_PCLP:
-		stats->rx_l4_pclp++;
+		this_cpu_inc(nic->drv_stats->rx_l4_pclp);
 		break;
 	case CQ_RX_ERROP_RBDR_TRUNC:
-		stats->rx_truncated_pkts++;
+		this_cpu_inc(nic->drv_stats->rx_truncated_pkts);
 		break;
 	}
 }
 /* Check for errors in the send cmp.queue entry */
-int nicvf_check_cqe_tx_errs(struct nicvf *nic,
+int nicvf_check_cqe_tx_errs(struct nicvf *nic, struct cqe_send_t *cqe_tx)
-			    struct cmp_queue *cq, struct cqe_send_t *cqe_tx)
 {
-	struct cmp_queue_stats *stats = &cq->stats;
 	switch (cqe_tx->send_status) {
 	case CQ_TX_ERROP_GOOD:
-		stats->tx.good++;
 		return 0;
 	case CQ_TX_ERROP_DESC_FAULT:
-		stats->tx.desc_fault++;
+		this_cpu_inc(nic->drv_stats->tx_desc_fault);
 		break;
 	case CQ_TX_ERROP_HDR_CONS_ERR:
-		stats->tx.hdr_cons_err++;
+		this_cpu_inc(nic->drv_stats->tx_hdr_cons_err);
 		break;
 	case CQ_TX_ERROP_SUBDC_ERR:
-		stats->tx.subdesc_err++;
+		this_cpu_inc(nic->drv_stats->tx_subdesc_err);
+		break;
+	case CQ_TX_ERROP_MAX_SIZE_VIOL:
+		this_cpu_inc(nic->drv_stats->tx_max_size_exceeded);
 		break;
 	case CQ_TX_ERROP_IMM_SIZE_OFLOW:
-		stats->tx.imm_size_oflow++;
+		this_cpu_inc(nic->drv_stats->tx_imm_size_oflow);
 		break;
 	case CQ_TX_ERROP_DATA_SEQUENCE_ERR:
-		stats->tx.data_seq_err++;
+		this_cpu_inc(nic->drv_stats->tx_data_seq_err);
 		break;
 	case CQ_TX_ERROP_MEM_SEQUENCE_ERR:
-		stats->tx.mem_seq_err++;
+		this_cpu_inc(nic->drv_stats->tx_mem_seq_err);
 		break;
 	case CQ_TX_ERROP_LOCK_VIOL:
-		stats->tx.lock_viol++;
+		this_cpu_inc(nic->drv_stats->tx_lock_viol);
 		break;
 	case CQ_TX_ERROP_DATA_FAULT:
-		stats->tx.data_fault++;
+		this_cpu_inc(nic->drv_stats->tx_data_fault);
 		break;
 	case CQ_TX_ERROP_TSTMP_CONFLICT:
-		stats->tx.tstmp_conflict++;
+		this_cpu_inc(nic->drv_stats->tx_tstmp_conflict);
 		break;
 	case CQ_TX_ERROP_TSTMP_TIMEOUT:
-		stats->tx.tstmp_timeout++;
+		this_cpu_inc(nic->drv_stats->tx_tstmp_timeout);
 		break;
 	case CQ_TX_ERROP_MEM_FAULT:
-		stats->tx.mem_fault++;
+		this_cpu_inc(nic->drv_stats->tx_mem_fault);
 		break;
 	case CQ_TX_ERROP_CK_OVERLAP:
-		stats->tx.csum_overlap++;
+		this_cpu_inc(nic->drv_stats->tx_csum_overlap);
 		break;
 	case CQ_TX_ERROP_CK_OFLOW:
-		stats->tx.csum_overflow++;
+		this_cpu_inc(nic->drv_stats->tx_csum_overflow);
 		break;
 	}

drivers/net/ethernet/cavium/thunder/nicvf_queues.h+2−22

 	CQ_TX_ERROP_DESC_FAULT = 0x10,
 	CQ_TX_ERROP_HDR_CONS_ERR = 0x11,
 	CQ_TX_ERROP_SUBDC_ERR = 0x12,
+	CQ_TX_ERROP_MAX_SIZE_VIOL = 0x13,
 	CQ_TX_ERROP_IMM_SIZE_OFLOW = 0x80,
 	CQ_TX_ERROP_DATA_SEQUENCE_ERR = 0x81,
 	CQ_TX_ERROP_MEM_SEQUENCE_ERR = 0x82,
 	CQ_TX_ERROP_ENUM_LAST = 0x8a,
 };
-struct cmp_queue_stats {
-	struct tx_stats {
-		u64 good;
-		u64 desc_fault;
-		u64 hdr_cons_err;
-		u64 subdesc_err;
-		u64 imm_size_oflow;
-		u64 data_seq_err;
-		u64 mem_seq_err;
-		u64 lock_viol;
-		u64 data_fault;
-		u64 tstmp_conflict;
-		u64 tstmp_timeout;
-		u64 mem_fault;
-		u64 csum_overlap;
-		u64 csum_overflow;
-	} tx;
-} ____cacheline_aligned_in_smp;
 enum RQ_SQ_STATS {
 	RQ_SQ_STATS_OCTS,
 	RQ_SQ_STATS_PKTS,
 	spinlock_t	lock;  /* lock to serialize processing CQEs */
 	void		*desc;
 	struct q_desc_mem   dmem;
-	struct cmp_queue_stats	stats;
 	int		irq;
 } ____cacheline_aligned_in_smp;
 void nicvf_update_rq_stats(struct nicvf *nic, int rq_idx);
 void nicvf_update_sq_stats(struct nicvf *nic, int sq_idx);
 int nicvf_check_cqe_rx_errs(struct nicvf *nic, struct cqe_rx_t *cqe_rx);
-int nicvf_check_cqe_tx_errs(struct nicvf *nic,
+int nicvf_check_cqe_tx_errs(struct nicvf *nic, struct cqe_send_t *cqe_tx);
-			    struct cmp_queue *cq, struct cqe_send_t *cqe_tx);
 #endif /* NICVF_QUEUES_H */

drivers/net/ethernet/cavium/thunder/thunder_bgx.c+2−2

@@ -1242,8 +1242,8 @@ static int bgx_probe(struct pci_dev pdev, const struct pci_device_id ent) · 1241 unmodified lines
1242		1242
1243	pci_read_config_word(pdev, PCI_DEVICE_ID, &sdevid);	1243	pci_read_config_word(pdev, PCI_DEVICE_ID, &sdevid);
1244	if (sdevid != PCI_DEVICE_ID_THUNDER_RGX) {	1244	if (sdevid != PCI_DEVICE_ID_THUNDER_RGX) {
1245	bgx->bgx_id =	1245	bgx->bgx_id = (pci_resource_start(pdev,
1246	(pci_resource_start(pdev, PCI_CFG_REG_BAR_NUM) >> 24) & 1;	1246	PCI_CFG_REG_BAR_NUM) >> 24) & BGX_ID_MASK;
1247	bgx->bgx_id += nic_get_node_id(pdev) * MAX_BGX_PER_NODE;	1247	bgx->bgx_id += nic_get_node_id(pdev) * MAX_BGX_PER_NODE;
1248	bgx->max_lmac = MAX_LMAC_PER_BGX;	1248	bgx->max_lmac = MAX_LMAC_PER_BGX;
1249	bgx_vnic[bgx->bgx_id] = bgx;	1249	bgx_vnic[bgx->bgx_id] = bgx;

drivers/net/ethernet/cavium/thunder/thunder_bgx.h+2−0

@@ -28,6 +28,8 @@ · 27 unmodified lines
28	#define MAX_DMAC_PER_LMAC 8	28	#define MAX_DMAC_PER_LMAC 8
29	#define MAX_FRAME_SIZE 9216	29	#define MAX_FRAME_SIZE 9216
30		30
		31	#define BGX_ID_MASK 0x3
		32
31	#define MAX_DMAC_PER_LMAC_TNS_BYPASS_MODE 2	33	#define MAX_DMAC_PER_LMAC_TNS_BYPASS_MODE 2
32		34
33	/* Registers */	35	/* Registers */

drivers/net/ethernet/chelsio/cxgb4/sge.c+0−1

@@ -2997,7 +2997,6 @@ void free_rspq_fl(struct adapter adap, struct sge_rspq rq, · 2996 unmodified lines
2997	rq->cntxt_id, fl_id, 0xffff);	2997	rq->cntxt_id, fl_id, 0xffff);
2998	dma_free_coherent(adap->pdev_dev, (rq->size + 1) * rq->iqe_len,	2998	dma_free_coherent(adap->pdev_dev, (rq->size + 1) * rq->iqe_len,
2999	rq->desc, rq->phys_addr);	2999	rq->desc, rq->phys_addr);
3000	napi_hash_del(&rq->napi);
3001	netif_napi_del(&rq->napi);	3000	netif_napi_del(&rq->napi);
3002	rq->netdev = NULL;	3001	rq->netdev = NULL;
3003	rq->cntxt_id = rq->abs_id = 0;	3002	rq->cntxt_id = rq->abs_id = 0;

drivers/net/ethernet/emulex/benet/be_main.c+0−1

@@ -2796,7 +2796,6 @@ static void be_evt_queues_destroy(struct be_adapter *adapter) · 2795 unmodified lines
2796	if (eqo->q.created) {	2796	if (eqo->q.created) {
2797	be_eq_clean(eqo);	2797	be_eq_clean(eqo);
2798	be_cmd_q_destroy(adapter, &eqo->q, QTYPE_EQ);	2798	be_cmd_q_destroy(adapter, &eqo->q, QTYPE_EQ);
2799	napi_hash_del(&eqo->napi);
2800	netif_napi_del(&eqo->napi);	2799	netif_napi_del(&eqo->napi);
2801	free_cpumask_var(eqo->affinity_mask);	2800	free_cpumask_var(eqo->affinity_mask);
2802	}	2801	}

drivers/net/ethernet/marvell/sky2.c+13−0

@@ -5218,6 +5218,19 @@ static SIMPLE_DEV_PM_OPS(sky2_pm_ops, sky2_suspend, sky2_resume); · 5217 unmodified lines
5218		5218
5219	static void sky2_shutdown(struct pci_dev *pdev)	5219	static void sky2_shutdown(struct pci_dev *pdev)
5220	{	5220	{
		5221	struct sky2_hw *hw = pci_get_drvdata(pdev);
		5222	int port;
		5223
		5224	for (port = 0; port < hw->ports; port++) {
		5225	struct net_device *ndev = hw->dev[port];
		5226
		5227	rtnl_lock();
		5228	if (netif_running(ndev)) {
		5229	dev_close(ndev);
		5230	netif_device_detach(ndev);
		5231	}
		5232	rtnl_unlock();
		5233	}
5221	sky2_suspend(&pdev->dev);	5234	sky2_suspend(&pdev->dev);
5222	pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev));	5235	pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev));
5223	pci_set_power_state(pdev, PCI_D3hot);	5236	pci_set_power_state(pdev, PCI_D3hot);

drivers/net/ethernet/stmicro/stmmac/Kconfig+1−1

@@ -118,7 +118,7 @@ config DWMAC_STI · 117 unmodified lines
118	config DWMAC_STM32	118	config DWMAC_STM32
119	tristate "STM32 DWMAC support"	119	tristate "STM32 DWMAC support"
120	default ARCH_STM32	120	default ARCH_STM32
121	depends on OF && HAS_IOMEM	121	depends on OF && HAS_IOMEM && (ARCH_STM32 \|\| COMPILE_TEST)
122	select MFD_SYSCON	122	select MFD_SYSCON
123	---help---	123	---help---
124	Support for ethernet controller on STM32 SOCs.	124	Support for ethernet controller on STM32 SOCs.

drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c+2−2

@@ -63,8 +63,8 @@ · 62 unmodified lines
63	#define TSE_PCS_SGMII_LINK_TIMER_0 0x0D40	63	#define TSE_PCS_SGMII_LINK_TIMER_0 0x0D40
64	#define TSE_PCS_SGMII_LINK_TIMER_1 0x0003	64	#define TSE_PCS_SGMII_LINK_TIMER_1 0x0003
65	#define TSE_PCS_SW_RESET_TIMEOUT 100	65	#define TSE_PCS_SW_RESET_TIMEOUT 100
66	#define TSE_PCS_USE_SGMII_AN_MASK BIT(2)	66	#define TSE_PCS_USE_SGMII_AN_MASK BIT(1)
67	#define TSE_PCS_USE_SGMII_ENA BIT(1)	67	#define TSE_PCS_USE_SGMII_ENA BIT(0)
68		68
69	#define SGMII_ADAPTER_CTRL_REG 0x00	69	#define SGMII_ADAPTER_CTRL_REG 0x00
70	#define SGMII_ADAPTER_DISABLE 0x0001	70	#define SGMII_ADAPTER_DISABLE 0x0001

drivers/net/ethernet/stmicro/stmmac/common.h+14−10

 	unsigned long ip_csum_bypassed;
 	unsigned long ipv4_pkt_rcvd;
 	unsigned long ipv6_pkt_rcvd;
-	unsigned long rx_msg_type_ext_no_ptp;
+	unsigned long no_ptp_rx_msg_type_ext;
-	unsigned long rx_msg_type_sync;
+	unsigned long ptp_rx_msg_type_sync;
-	unsigned long rx_msg_type_follow_up;
+	unsigned long ptp_rx_msg_type_follow_up;
-	unsigned long rx_msg_type_delay_req;
+	unsigned long ptp_rx_msg_type_delay_req;
-	unsigned long rx_msg_type_delay_resp;
+	unsigned long ptp_rx_msg_type_delay_resp;
-	unsigned long rx_msg_type_pdelay_req;
+	unsigned long ptp_rx_msg_type_pdelay_req;
-	unsigned long rx_msg_type_pdelay_resp;
+	unsigned long ptp_rx_msg_type_pdelay_resp;
-	unsigned long rx_msg_type_pdelay_follow_up;
+	unsigned long ptp_rx_msg_type_pdelay_follow_up;
+	unsigned long ptp_rx_msg_type_announce;
+	unsigned long ptp_rx_msg_type_management;
+	unsigned long ptp_rx_msg_pkt_reserved_type;
 	unsigned long ptp_frame_type;
 	unsigned long ptp_ver;
 	unsigned long timestamp_dropped;
 /* PTP and HW Timer helpers */
 struct stmmac_hwtimestamp {
 	void (*config_hw_tstamping) (void __iomem *ioaddr, u32 data);
-	u32 (*config_sub_second_increment) (void __iomem *ioaddr, u32 clk_rate);
+	u32 (*config_sub_second_increment)(void __iomem *ioaddr, u32 ptp_clock,
+					   int gmac4);
 	int (*init_systime) (void __iomem *ioaddr, u32 sec, u32 nsec);
 	int (*config_addend) (void __iomem *ioaddr, u32 addend);
 	int (*adjust_systime) (void __iomem *ioaddr, u32 sec, u32 nsec,
-			       int add_sub);
+			       int add_sub, int gmac4);
 	 u64(*get_systime) (void __iomem *ioaddr);
 };

drivers/net/ethernet/stmicro/stmmac/descs.h+12−8

@@ -155,14 +155,18 @@ · 154 unmodified lines
155	#define ERDES4_L3_L4_FILT_NO_MATCH_MASK GENMASK(27, 26)	155	#define ERDES4_L3_L4_FILT_NO_MATCH_MASK GENMASK(27, 26)
156		156
157	/* Extended RDES4 message type definitions */	157	/* Extended RDES4 message type definitions */
158	#define RDES_EXT_NO_PTP 0	158	#define RDES_EXT_NO_PTP 0x0
159	#define RDES_EXT_SYNC 1	159	#define RDES_EXT_SYNC 0x1
160	#define RDES_EXT_FOLLOW_UP 2	160	#define RDES_EXT_FOLLOW_UP 0x2
161	#define RDES_EXT_DELAY_REQ 3	161	#define RDES_EXT_DELAY_REQ 0x3
162	#define RDES_EXT_DELAY_RESP 4	162	#define RDES_EXT_DELAY_RESP 0x4
163	#define RDES_EXT_PDELAY_REQ 5	163	#define RDES_EXT_PDELAY_REQ 0x5
164	#define RDES_EXT_PDELAY_RESP 6	164	#define RDES_EXT_PDELAY_RESP 0x6
165	#define RDES_EXT_PDELAY_FOLLOW_UP 7	165	#define RDES_EXT_PDELAY_FOLLOW_UP 0x7
		166	#define RDES_PTP_ANNOUNCE 0x8
		167	#define RDES_PTP_MANAGEMENT 0x9
		168	#define RDES_PTP_SIGNALING 0xa
		169	#define RDES_PTP_PKT_RESERVED_TYPE 0xf
166		170
167	/* Basic descriptor structure for normal and alternate descriptors */	171	/* Basic descriptor structure for normal and alternate descriptors */
168	struct dma_desc {	172	struct dma_desc {

drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c+74−21

@@ -123,22 +123,29 @@ static int dwmac4_wrback_get_rx_status(void data, struct stmmac_extra_stats x, · 122 unmodified lines
123	x->ipv4_pkt_rcvd++;	123	x->ipv4_pkt_rcvd++;
124	if (rdes1 & RDES1_IPV6_HEADER)	124	if (rdes1 & RDES1_IPV6_HEADER)
125	x->ipv6_pkt_rcvd++;	125	x->ipv6_pkt_rcvd++;
126	if (message_type == RDES_EXT_SYNC)	126
127	x->rx_msg_type_sync++;	127	if (message_type == RDES_EXT_NO_PTP)
		128	x->no_ptp_rx_msg_type_ext++;
		129	else if (message_type == RDES_EXT_SYNC)
		130	x->ptp_rx_msg_type_sync++;
128	else if (message_type == RDES_EXT_FOLLOW_UP)	131	else if (message_type == RDES_EXT_FOLLOW_UP)
129	x->rx_msg_type_follow_up++;	132	x->ptp_rx_msg_type_follow_up++;
130	else if (message_type == RDES_EXT_DELAY_REQ)	133	else if (message_type == RDES_EXT_DELAY_REQ)
131	x->rx_msg_type_delay_req++;	134	x->ptp_rx_msg_type_delay_req++;
132	else if (message_type == RDES_EXT_DELAY_RESP)	135	else if (message_type == RDES_EXT_DELAY_RESP)
133	x->rx_msg_type_delay_resp++;	136	x->ptp_rx_msg_type_delay_resp++;
134	else if (message_type == RDES_EXT_PDELAY_REQ)	137	else if (message_type == RDES_EXT_PDELAY_REQ)
135	x->rx_msg_type_pdelay_req++;	138	x->ptp_rx_msg_type_pdelay_req++;
136	else if (message_type == RDES_EXT_PDELAY_RESP)	139	else if (message_type == RDES_EXT_PDELAY_RESP)
137	x->rx_msg_type_pdelay_resp++;	140	x->ptp_rx_msg_type_pdelay_resp++;
138	else if (message_type == RDES_EXT_PDELAY_FOLLOW_UP)	141	else if (message_type == RDES_EXT_PDELAY_FOLLOW_UP)
139	x->rx_msg_type_pdelay_follow_up++;	142	x->ptp_rx_msg_type_pdelay_follow_up++;
140	else	143	else if (message_type == RDES_PTP_ANNOUNCE)
141	x->rx_msg_type_ext_no_ptp++;	144	x->ptp_rx_msg_type_announce++;
		145	else if (message_type == RDES_PTP_MANAGEMENT)
		146	x->ptp_rx_msg_type_management++;
		147	else if (message_type == RDES_PTP_PKT_RESERVED_TYPE)
		148	x->ptp_rx_msg_pkt_reserved_type++;
142		149
143	if (rdes1 & RDES1_PTP_PACKET_TYPE)	150	if (rdes1 & RDES1_PTP_PACKET_TYPE)
144	x->ptp_frame_type++;	151	x->ptp_frame_type++;
@@ -205,14 +212,18 @@ static void dwmac4_rd_enable_tx_timestamp(struct dma_desc *p) · 60 unmodified lines
205		212
206	static int dwmac4_wrback_get_tx_timestamp_status(struct dma_desc *p)	213	static int dwmac4_wrback_get_tx_timestamp_status(struct dma_desc *p)
207	{	214	{
208	return (le32_to_cpu(p->des3) & TDES3_TIMESTAMP_STATUS)	215	/* Context type from W/B descriptor must be zero */
209	>> TDES3_TIMESTAMP_STATUS_SHIFT;	216	if (le32_to_cpu(p->des3) & TDES3_CONTEXT_TYPE)
		217	return -EINVAL;
		218
		219	/* Tx Timestamp Status is 1 so des0 and des1'll have valid values */
		220	if (le32_to_cpu(p->des3) & TDES3_TIMESTAMP_STATUS)
		221	return 0;
		222
		223	return 1;
210	}	224	}
211		225
212	/* NOTE: For RX CTX bit has to be checked before	226	static inline u64 dwmac4_get_timestamp(void *desc, u32 ats)
213	* HAVE a specific function for TX and another one for RX
214	*/
215	static u64 dwmac4_wrback_get_timestamp(void *desc, u32 ats)
216	{	227	{
217	struct dma_desc p = (struct dma_desc )desc;	228	struct dma_desc p = (struct dma_desc )desc;
218	u64 ns;	229	u64 ns;
@@ -224,12 +235,54 @@ static u64 dwmac4_wrback_get_timestamp(void *desc, u32 ats) · 5 unmodified lines
224	return ns;	235	return ns;
225	}	236	}
226		237
227	static int dwmac4_context_get_rx_timestamp_status(void *desc, u32 ats)	238	static int dwmac4_rx_check_timestamp(void *desc)
		239	{
		240	struct dma_desc p = (struct dma_desc )desc;
		241	u32 own, ctxt;
		242	int ret = 1;
		243
		244	own = p->des3 & RDES3_OWN;
		245	ctxt = ((p->des3 & RDES3_CONTEXT_DESCRIPTOR)
		246	>> RDES3_CONTEXT_DESCRIPTOR_SHIFT);
		247
		248	if (likely(!own && ctxt)) {
		249	if ((p->des0 == 0xffffffff) && (p->des1 == 0xffffffff))
		250	/* Corrupted value */
		251	ret = -EINVAL;
		252	else
		253	/* A valid Timestamp is ready to be read */
		254	ret = 0;
		255	}
		256
		257	/* Timestamp not ready */
		258	return ret;
		259	}
		260
		261	static int dwmac4_wrback_get_rx_timestamp_status(void *desc, u32 ats)
228	{	262	{
229	struct dma_desc p = (struct dma_desc )desc;	263	struct dma_desc p = (struct dma_desc )desc;
		264	int ret = -EINVAL;
		265
		266	/* Get the status from normal w/b descriptor */
		267	if (likely(p->des3 & TDES3_RS1V)) {
		268	if (likely(le32_to_cpu(p->des1) & RDES1_TIMESTAMP_AVAILABLE)) {
		269	int i = 0;
		270
		271	/* Check if timestamp is OK from context descriptor */
		272	do {
		273	ret = dwmac4_rx_check_timestamp(desc);
		274	if (ret < 0)
		275	goto exit;
		276	i++;
230		277
231	return (le32_to_cpu(p->des1) & RDES1_TIMESTAMP_AVAILABLE)	278	} while ((ret == 1) \|\| (i < 10));
232	>> RDES1_TIMESTAMP_AVAILABLE_SHIFT;	279
		280	if (i == 10)
		281	ret = -EBUSY;
		282	}
		283	}
		284	exit:
		285	return ret;
233	}	286	}
234		287
235	static void dwmac4_rd_init_rx_desc(struct dma_desc *p, int disable_rx_ic,	288	static void dwmac4_rd_init_rx_desc(struct dma_desc *p, int disable_rx_ic,
@@ -375,8 +428,8 @@ const struct stmmac_desc_ops dwmac4_desc_ops = { · 139 unmodified lines
375	.get_rx_frame_len = dwmac4_wrback_get_rx_frame_len,	428	.get_rx_frame_len = dwmac4_wrback_get_rx_frame_len,
376	.enable_tx_timestamp = dwmac4_rd_enable_tx_timestamp,	429	.enable_tx_timestamp = dwmac4_rd_enable_tx_timestamp,
377	.get_tx_timestamp_status = dwmac4_wrback_get_tx_timestamp_status,	430	.get_tx_timestamp_status = dwmac4_wrback_get_tx_timestamp_status,
378	.get_timestamp = dwmac4_wrback_get_timestamp,	431	.get_rx_timestamp_status = dwmac4_wrback_get_rx_timestamp_status,
379	.get_rx_timestamp_status = dwmac4_context_get_rx_timestamp_status,	432	.get_timestamp = dwmac4_get_timestamp,
380	.set_tx_ic = dwmac4_rd_set_tx_ic,	433	.set_tx_ic = dwmac4_rd_set_tx_ic,
381	.prepare_tx_desc = dwmac4_rd_prepare_tx_desc,	434	.prepare_tx_desc = dwmac4_rd_prepare_tx_desc,
382	.prepare_tso_tx_desc = dwmac4_rd_prepare_tso_tx_desc,	435	.prepare_tso_tx_desc = dwmac4_rd_prepare_tso_tx_desc,

drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h+4−0

 #define TDES3_CTXT_TCMSSV		BIT(26)
 /* TDES3 Common */
+#define	TDES3_RS1V			BIT(26)
+#define	TDES3_RS1V_SHIFT		26
 #define TDES3_LAST_DESCRIPTOR		BIT(28)
 #define TDES3_LAST_DESCRIPTOR_SHIFT	28
 #define TDES3_FIRST_DESCRIPTOR		BIT(29)
 #define TDES3_CONTEXT_TYPE		BIT(30)
+#define	TDES3_CONTEXT_TYPE_SHIFT	30
 /* TDS3 use for both format (read and write back) */
 #define TDES3_OWN			BIT(31)
 #define RDES3_LAST_DESCRIPTOR		BIT(28)
 #define RDES3_FIRST_DESCRIPTOR		BIT(29)
 #define RDES3_CONTEXT_DESCRIPTOR	BIT(30)
+#define RDES3_CONTEXT_DESCRIPTOR_SHIFT	30
 /* RDES3 (read format) */
 #define RDES3_BUFFER1_VALID_ADDR	BIT(24)

drivers/net/ethernet/stmicro/stmmac/enh_desc.c+18−10

@@ -150,22 +150,30 @@ static void enh_desc_get_ext_status(void data, struct stmmac_extra_stats x, · 149 unmodified lines
150	x->ipv4_pkt_rcvd++;	150	x->ipv4_pkt_rcvd++;
151	if (rdes4 & ERDES4_IPV6_PKT_RCVD)	151	if (rdes4 & ERDES4_IPV6_PKT_RCVD)
152	x->ipv6_pkt_rcvd++;	152	x->ipv6_pkt_rcvd++;
153	if (message_type == RDES_EXT_SYNC)	153
154	x->rx_msg_type_sync++;	154	if (message_type == RDES_EXT_NO_PTP)
		155	x->no_ptp_rx_msg_type_ext++;
		156	else if (message_type == RDES_EXT_SYNC)
		157	x->ptp_rx_msg_type_sync++;
155	else if (message_type == RDES_EXT_FOLLOW_UP)	158	else if (message_type == RDES_EXT_FOLLOW_UP)
156	x->rx_msg_type_follow_up++;	159	x->ptp_rx_msg_type_follow_up++;
157	else if (message_type == RDES_EXT_DELAY_REQ)	160	else if (message_type == RDES_EXT_DELAY_REQ)
158	x->rx_msg_type_delay_req++;	161	x->ptp_rx_msg_type_delay_req++;
159	else if (message_type == RDES_EXT_DELAY_RESP)	162	else if (message_type == RDES_EXT_DELAY_RESP)
160	x->rx_msg_type_delay_resp++;	163	x->ptp_rx_msg_type_delay_resp++;
161	else if (message_type == RDES_EXT_PDELAY_REQ)	164	else if (message_type == RDES_EXT_PDELAY_REQ)
162	x->rx_msg_type_pdelay_req++;	165	x->ptp_rx_msg_type_pdelay_req++;
163	else if (message_type == RDES_EXT_PDELAY_RESP)	166	else if (message_type == RDES_EXT_PDELAY_RESP)
164	x->rx_msg_type_pdelay_resp++;	167	x->ptp_rx_msg_type_pdelay_resp++;
165	else if (message_type == RDES_EXT_PDELAY_FOLLOW_UP)	168	else if (message_type == RDES_EXT_PDELAY_FOLLOW_UP)
166	x->rx_msg_type_pdelay_follow_up++;	169	x->ptp_rx_msg_type_pdelay_follow_up++;
167	else	170	else if (message_type == RDES_PTP_ANNOUNCE)
168	x->rx_msg_type_ext_no_ptp++;	171	x->ptp_rx_msg_type_announce++;
		172	else if (message_type == RDES_PTP_MANAGEMENT)
		173	x->ptp_rx_msg_type_management++;
		174	else if (message_type == RDES_PTP_PKT_RESERVED_TYPE)
		175	x->ptp_rx_msg_pkt_reserved_type++;
		176
169	if (rdes4 & ERDES4_PTP_FRAME_TYPE)	177	if (rdes4 & ERDES4_PTP_FRAME_TYPE)
170	x->ptp_frame_type++;	178	x->ptp_frame_type++;
171	if (rdes4 & ERDES4_PTP_VER)	179	if (rdes4 & ERDES4_PTP_VER)

drivers/net/ethernet/stmicro/stmmac/stmmac.h+1−0

@@ -128,6 +128,7 @@ struct stmmac_priv { · 127 unmodified lines
128	int irq_wake;	128	int irq_wake;
129	spinlock_t ptp_lock;	129	spinlock_t ptp_lock;
130	void __iomem *mmcaddr;	130	void __iomem *mmcaddr;
		131	void __iomem *ptpaddr;
131	u32 rx_tail_addr;	132	u32 rx_tail_addr;
132	u32 tx_tail_addr;	133	u32 tx_tail_addr;
133	u32 mss;	134	u32 mss;

drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c+11−8

@@ -115,14 +115,17 @@ static const struct stmmac_stats stmmac_gstrings_stats[] = { · 114 unmodified lines
115	STMMAC_STAT(ip_csum_bypassed),	115	STMMAC_STAT(ip_csum_bypassed),
116	STMMAC_STAT(ipv4_pkt_rcvd),	116	STMMAC_STAT(ipv4_pkt_rcvd),
117	STMMAC_STAT(ipv6_pkt_rcvd),	117	STMMAC_STAT(ipv6_pkt_rcvd),
118	STMMAC_STAT(rx_msg_type_ext_no_ptp),	118	STMMAC_STAT(no_ptp_rx_msg_type_ext),
119	STMMAC_STAT(rx_msg_type_sync),	119	STMMAC_STAT(ptp_rx_msg_type_sync),
120	STMMAC_STAT(rx_msg_type_follow_up),	120	STMMAC_STAT(ptp_rx_msg_type_follow_up),
121	STMMAC_STAT(rx_msg_type_delay_req),	121	STMMAC_STAT(ptp_rx_msg_type_delay_req),
122	STMMAC_STAT(rx_msg_type_delay_resp),	122	STMMAC_STAT(ptp_rx_msg_type_delay_resp),
123	STMMAC_STAT(rx_msg_type_pdelay_req),	123	STMMAC_STAT(ptp_rx_msg_type_pdelay_req),
124	STMMAC_STAT(rx_msg_type_pdelay_resp),	124	STMMAC_STAT(ptp_rx_msg_type_pdelay_resp),
125	STMMAC_STAT(rx_msg_type_pdelay_follow_up),	125	STMMAC_STAT(ptp_rx_msg_type_pdelay_follow_up),
		126	STMMAC_STAT(ptp_rx_msg_type_announce),
		127	STMMAC_STAT(ptp_rx_msg_type_management),
		128	STMMAC_STAT(ptp_rx_msg_pkt_reserved_type),
126	STMMAC_STAT(ptp_frame_type),	129	STMMAC_STAT(ptp_frame_type),
127	STMMAC_STAT(ptp_ver),	130	STMMAC_STAT(ptp_ver),
128	STMMAC_STAT(timestamp_dropped),	131	STMMAC_STAT(timestamp_dropped),

drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c+34−9

 }
 static u32 stmmac_config_sub_second_increment(void __iomem *ioaddr,
-					      u32 ptp_clock)
+					      u32 ptp_clock, int gmac4)
 {
 	u32 value = readl(ioaddr + PTP_TCR);
 	unsigned long data;
-	/* Convert the ptp_clock to nano second
+	/* For GMAC3.x, 4.x versions, convert the ptp_clock to nano second
-	 * formula = (2/ptp_clock) * 1000000000
+	 *	formula = (1/ptp_clock) * 1000000000
-	 * where, ptp_clock = 50MHz.
+	 * where ptp_clock is 50MHz if fine method is used to update system
 	 */
-	data = (2000000000ULL / ptp_clock);
+	if (value & PTP_TCR_TSCFUPDT)
+		data = (1000000000ULL / 50000000);
+	else
+		data = (1000000000ULL / ptp_clock);
 	/* 0.465ns accuracy */
 	if (!(value & PTP_TCR_TSCTRLSSR))
 		data = (data * 1000) / 465;
+	data &= PTP_SSIR_SSINC_MASK;
+	if (gmac4)
+		data = data << GMAC4_PTP_SSIR_SSINC_SHIFT;
 	writel(data, ioaddr + PTP_SSIR);
 	return data;
 }
 static int stmmac_adjust_systime(void __iomem *ioaddr, u32 sec, u32 nsec,
-				 int add_sub)
+				 int add_sub, int gmac4)
 {
 	u32 value;
 	int limit;
+	if (add_sub) {
+		/* If the new sec value needs to be subtracted with
+		 * the system time, then MAC_STSUR reg should be
+		 * programmed with (2^32 – <new_sec_value>)
+		 */
+		if (gmac4)
+			sec = (100000000ULL - sec);
+		value = readl(ioaddr + PTP_TCR);
+		if (value & PTP_TCR_TSCTRLSSR)
+			nsec = (PTP_DIGITAL_ROLLOVER_MODE - nsec);
+		else
+			nsec = (PTP_BINARY_ROLLOVER_MODE - nsec);
+	}
 	writel(sec, ioaddr + PTP_STSUR);
-	writel(((add_sub << PTP_STNSUR_ADDSUB_SHIFT) | nsec),
+	value = (add_sub << PTP_STNSUR_ADDSUB_SHIFT) | nsec;
-		ioaddr + PTP_STNSUR);
+	writel(value, ioaddr + PTP_STNSUR);
 	/* issue command to initialize the system time value */
 	value = readl(ioaddr + PTP_TCR);
 	value |= PTP_TCR_TSUPDT;
 {
 	u64 ns;
+	/* Get the TSSS value */
 	ns = readl(ioaddr + PTP_STNSR);
-	/* convert sec time value to nanosecond */
+	/* Get the TSS and convert sec time value to nanosecond */
 	ns += readl(ioaddr + PTP_STSR) * 1000000000ULL;
 	return ns;

drivers/net/ethernet/stmicro/stmmac/stmmac_main.c+48−45

@@ -342,18 +342,17 @@ out: · 341 unmodified lines
342		342
343	/* stmmac_get_tx_hwtstamp - get HW TX timestamps	343	/* stmmac_get_tx_hwtstamp - get HW TX timestamps
344	* @priv: driver private structure	344	* @priv: driver private structure
345	* @entry : descriptor index to be used.	345	* @p : descriptor pointer
346	* @skb : the socket buffer	346	* @skb : the socket buffer
347	* Description :	347	* Description :
348	* This function will read timestamp from the descriptor & pass it to stack.	348	* This function will read timestamp from the descriptor & pass it to stack.
349	* and also perform some sanity checks.	349	* and also perform some sanity checks.
350	*/	350	*/
351	static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,	351	static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
352	unsigned int entry, struct sk_buff *skb)	352	struct dma_desc p, struct sk_buff skb)
353	{	353	{
354	struct skb_shared_hwtstamps shhwtstamp;	354	struct skb_shared_hwtstamps shhwtstamp;
355	u64 ns;	355	u64 ns;
356	void *desc = NULL;
357		356
358	if (!priv->hwts_tx_en)	357	if (!priv->hwts_tx_en)
359	return;	358	return;
@@ -362,58 +361,55 @@ static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv, · 2 unmodified lines
362	if (likely(!skb \|\| !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))	361	if (likely(!skb \|\| !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
363	return;	362	return;
364		363
365	if (priv->adv_ts)
366	desc = (priv->dma_etx + entry);
367	else
368	desc = (priv->dma_tx + entry);
369
370	/* check tx tstamp status */	364	/* check tx tstamp status */
371	if (!priv->hw->desc->get_tx_timestamp_status((struct dma_desc *)desc))	365	if (!priv->hw->desc->get_tx_timestamp_status(p)) {
372	return;	366	/* get the valid tstamp */
		367	ns = priv->hw->desc->get_timestamp(p, priv->adv_ts);
373		368
374	/* get the valid tstamp */	369	memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
375	ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);	370	shhwtstamp.hwtstamp = ns_to_ktime(ns);
376		371
377	memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));	372	netdev_info(priv->dev, "get valid TX hw timestamp %llu\n", ns);
378	shhwtstamp.hwtstamp = ns_to_ktime(ns);	373	/* pass tstamp to stack */
379	/* pass tstamp to stack */	374	skb_tstamp_tx(skb, &shhwtstamp);
380	skb_tstamp_tx(skb, &shhwtstamp);	375	}
381		376
382	return;	377	return;
383	}	378	}
384		379
385	/* stmmac_get_rx_hwtstamp - get HW RX timestamps	380	/* stmmac_get_rx_hwtstamp - get HW RX timestamps
386	* @priv: driver private structure	381	* @priv: driver private structure
387	* @entry : descriptor index to be used.	382	* @p : descriptor pointer
		383	* @np : next descriptor pointer
388	* @skb : the socket buffer	384	* @skb : the socket buffer
389	* Description :	385	* Description :
390	* This function will read received packet's timestamp from the descriptor	386	* This function will read received packet's timestamp from the descriptor
391	* and pass it to stack. It also perform some sanity checks.	387	* and pass it to stack. It also perform some sanity checks.
392	*/	388	*/
393	static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv,	389	static void stmmac_get_rx_hwtstamp(struct stmmac_priv priv, struct dma_desc p,
394	unsigned int entry, struct sk_buff *skb)	390	struct dma_desc np, struct sk_buff skb)
395	{	391	{
396	struct skb_shared_hwtstamps *shhwtstamp = NULL;	392	struct skb_shared_hwtstamps *shhwtstamp = NULL;
397	u64 ns;	393	u64 ns;
398	void *desc = NULL;
399		394
400	if (!priv->hwts_rx_en)	395	if (!priv->hwts_rx_en)
401	return;	396	return;
402		397
403	if (priv->adv_ts)	398	/* Check if timestamp is available */
404	desc = (priv->dma_erx + entry);	399	if (!priv->hw->desc->get_rx_timestamp_status(p, priv->adv_ts)) {
405	else	400	/* For GMAC4, the valid timestamp is from CTX next desc. */
406	desc = (priv->dma_rx + entry);	401	if (priv->plat->has_gmac4)
407		402	ns = priv->hw->desc->get_timestamp(np, priv->adv_ts);
408	/* exit if rx tstamp is not valid */	403	else
409	if (!priv->hw->desc->get_rx_timestamp_status(desc, priv->adv_ts))	404	ns = priv->hw->desc->get_timestamp(p, priv->adv_ts);
410	return;
411		405
412	/* get valid tstamp */	406	netdev_info(priv->dev, "get valid RX hw timestamp %llu\n", ns);
413	ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);	407	shhwtstamp = skb_hwtstamps(skb);
414	shhwtstamp = skb_hwtstamps(skb);	408	memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
415	memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));	409	shhwtstamp->hwtstamp = ns_to_ktime(ns);
416	shhwtstamp->hwtstamp = ns_to_ktime(ns);	410	} else {
		411	netdev_err(priv->dev, "cannot get RX hw timestamp\n");
		412	}
417	}	413	}
418		414
419	/**	415	/**
@@ -600,17 +596,18 @@ static int stmmac_hwtstamp_ioctl(struct net_device dev, struct ifreq ifr) · 180 unmodified lines
600	priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;	596	priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
601		597
602	if (!priv->hwts_tx_en && !priv->hwts_rx_en)	598	if (!priv->hwts_tx_en && !priv->hwts_rx_en)
603	priv->hw->ptp->config_hw_tstamping(priv->ioaddr, 0);	599	priv->hw->ptp->config_hw_tstamping(priv->ptpaddr, 0);
604	else {	600	else {
605	value = (PTP_TCR_TSENA \| PTP_TCR_TSCFUPDT \| PTP_TCR_TSCTRLSSR \|	601	value = (PTP_TCR_TSENA \| PTP_TCR_TSCFUPDT \| PTP_TCR_TSCTRLSSR \|
606	tstamp_all \| ptp_v2 \| ptp_over_ethernet \|	602	tstamp_all \| ptp_v2 \| ptp_over_ethernet \|
607	ptp_over_ipv6_udp \| ptp_over_ipv4_udp \| ts_event_en \|	603	ptp_over_ipv6_udp \| ptp_over_ipv4_udp \| ts_event_en \|
608	ts_master_en \| snap_type_sel);	604	ts_master_en \| snap_type_sel);
609	priv->hw->ptp->config_hw_tstamping(priv->ioaddr, value);	605	priv->hw->ptp->config_hw_tstamping(priv->ptpaddr, value);
610		606
611	/* program Sub Second Increment reg */	607	/* program Sub Second Increment reg */
612	sec_inc = priv->hw->ptp->config_sub_second_increment(	608	sec_inc = priv->hw->ptp->config_sub_second_increment(
613	priv->ioaddr, priv->clk_ptp_rate);	609	priv->ptpaddr, priv->clk_ptp_rate,
		610	priv->plat->has_gmac4);
614	temp = div_u64(1000000000ULL, sec_inc);	611	temp = div_u64(1000000000ULL, sec_inc);
615		612
616	/* calculate default added value:	613	/* calculate default added value:
@@ -620,14 +617,14 @@ static int stmmac_hwtstamp_ioctl(struct net_device dev, struct ifreq ifr) · 3 unmodified lines
620	*/	617	*/
621	temp = (u64)(temp << 32);	618	temp = (u64)(temp << 32);
622	priv->default_addend = div_u64(temp, priv->clk_ptp_rate);	619	priv->default_addend = div_u64(temp, priv->clk_ptp_rate);
623	priv->hw->ptp->config_addend(priv->ioaddr,	620	priv->hw->ptp->config_addend(priv->ptpaddr,
624	priv->default_addend);	621	priv->default_addend);
625		622
626	/* initialize system time */	623	/* initialize system time */
627	ktime_get_real_ts64(&now);	624	ktime_get_real_ts64(&now);
628		625
629	/* lower 32 bits of tv_sec are safe until y2106 */	626	/* lower 32 bits of tv_sec are safe until y2106 */
630	priv->hw->ptp->init_systime(priv->ioaddr, (u32)now.tv_sec,	627	priv->hw->ptp->init_systime(priv->ptpaddr, (u32)now.tv_sec,
631	now.tv_nsec);	628	now.tv_nsec);
632	}	629	}
633		630
@@ -1341,7 +1338,7 @@ static void stmmac_tx_clean(struct stmmac_priv *priv) · 707 unmodified lines
1341	priv->dev->stats.tx_packets++;	1338	priv->dev->stats.tx_packets++;
1342	priv->xstats.tx_pkt_n++;	1339	priv->xstats.tx_pkt_n++;
1343	}	1340	}
1344	stmmac_get_tx_hwtstamp(priv, entry, skb);	1341	stmmac_get_tx_hwtstamp(priv, p, skb);
1345	}	1342	}
1346		1343
1347	if (likely(priv->tx_skbuff_dma[entry].buf)) {	1344	if (likely(priv->tx_skbuff_dma[entry].buf)) {
@@ -1487,10 +1484,13 @@ static void stmmac_mmc_setup(struct stmmac_priv *priv) · 139 unmodified lines
1487	unsigned int mode = MMC_CNTRL_RESET_ON_READ \| MMC_CNTRL_COUNTER_RESET \|	1484	unsigned int mode = MMC_CNTRL_RESET_ON_READ \| MMC_CNTRL_COUNTER_RESET \|
1488	MMC_CNTRL_PRESET \| MMC_CNTRL_FULL_HALF_PRESET;	1485	MMC_CNTRL_PRESET \| MMC_CNTRL_FULL_HALF_PRESET;
1489		1486
1490	if (priv->synopsys_id >= DWMAC_CORE_4_00)	1487	if (priv->synopsys_id >= DWMAC_CORE_4_00) {
		1488	priv->ptpaddr = priv->ioaddr + PTP_GMAC4_OFFSET;
1491	priv->mmcaddr = priv->ioaddr + MMC_GMAC4_OFFSET;	1489	priv->mmcaddr = priv->ioaddr + MMC_GMAC4_OFFSET;
1492	else	1490	} else {
		1491	priv->ptpaddr = priv->ioaddr + PTP_GMAC3_X_OFFSET;
1493	priv->mmcaddr = priv->ioaddr + MMC_GMAC3_X_OFFSET;	1492	priv->mmcaddr = priv->ioaddr + MMC_GMAC3_X_OFFSET;
		1493	}
1494		1494
1495	dwmac_mmc_intr_all_mask(priv->mmcaddr);	1495	dwmac_mmc_intr_all_mask(priv->mmcaddr);
1496		1496
@@ -2504,6 +2504,7 @@ static int stmmac_rx(struct stmmac_priv *priv, int limit) · 1007 unmodified lines
2504	while (count < limit) {	2504	while (count < limit) {
2505	int status;	2505	int status;
2506	struct dma_desc *p;	2506	struct dma_desc *p;
		2507	struct dma_desc *np;
2507		2508
2508	if (priv->extend_desc)	2509	if (priv->extend_desc)
2509	p = (struct dma_desc *)(priv->dma_erx + entry);	2510	p = (struct dma_desc *)(priv->dma_erx + entry);
@@ -2523,9 +2524,11 @@ static int stmmac_rx(struct stmmac_priv *priv, int limit) · 13 unmodified lines
2523	next_entry = priv->cur_rx;	2524	next_entry = priv->cur_rx;
2524		2525
2525	if (priv->extend_desc)	2526	if (priv->extend_desc)
2526	prefetch(priv->dma_erx + next_entry);	2527	np = (struct dma_desc *)(priv->dma_erx + next_entry);
2527	else	2528	else
2528	prefetch(priv->dma_rx + next_entry);	2529	np = priv->dma_rx + next_entry;
		2530
		2531	prefetch(np);
2529		2532
2530	if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status))	2533	if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status))
2531	priv->hw->desc->rx_extended_status(&priv->dev->stats,	2534	priv->hw->desc->rx_extended_status(&priv->dev->stats,
@@ -2635,14 +2638,14 @@ static int stmmac_rx(struct stmmac_priv *priv, int limit) · 103 unmodified lines
2635	DMA_FROM_DEVICE);	2638	DMA_FROM_DEVICE);
2636	}	2639	}
2637		2640
2638	stmmac_get_rx_hwtstamp(priv, entry, skb);
2639
2640	if (netif_msg_pktdata(priv)) {	2641	if (netif_msg_pktdata(priv)) {
2641	netdev_dbg(priv->dev, "frame received (%dbytes)",	2642	netdev_dbg(priv->dev, "frame received (%dbytes)",
2642	frame_len);	2643	frame_len);
2643	print_pkt(skb->data, frame_len);	2644	print_pkt(skb->data, frame_len);
2644	}	2645	}
2645		2646
		2647	stmmac_get_rx_hwtstamp(priv, p, np, skb);
		2648
2646	stmmac_rx_vlan(priv->dev, skb);	2649	stmmac_rx_vlan(priv->dev, skb);
2647		2650
2648	skb->protocol = eth_type_trans(skb, priv->dev);	2651	skb->protocol = eth_type_trans(skb, priv->dev);

drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c+5−4

 	spin_lock_irqsave(&priv->ptp_lock, flags);
-	priv->hw->ptp->config_addend(priv->ioaddr, addend);
+	priv->hw->ptp->config_addend(priv->ptpaddr, addend);
 	spin_unlock_irqrestore(&priv->ptp_lock, flags);
 	spin_lock_irqsave(&priv->ptp_lock, flags);
-	priv->hw->ptp->adjust_systime(priv->ioaddr, sec, nsec, neg_adj);
+	priv->hw->ptp->adjust_systime(priv->ptpaddr, sec, nsec, neg_adj,
+				      priv->plat->has_gmac4);
 	spin_unlock_irqrestore(&priv->ptp_lock, flags);
 	spin_lock_irqsave(&priv->ptp_lock, flags);
-	ns = priv->hw->ptp->get_systime(priv->ioaddr);
+	ns = priv->hw->ptp->get_systime(priv->ptpaddr);
 	spin_unlock_irqrestore(&priv->ptp_lock, flags);
 	spin_lock_irqsave(&priv->ptp_lock, flags);
-	priv->hw->ptp->init_systime(priv->ioaddr, ts->tv_sec, ts->tv_nsec);
+	priv->hw->ptp->init_systime(priv->ptpaddr, ts->tv_sec, ts->tv_nsec);
 	spin_unlock_irqrestore(&priv->ptp_lock, flags);

drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.h+37−35

   Author: Rayagond Kokatanur <rayagond@vayavyalabs.com>
 ******************************************************************************/
-#ifndef __STMMAC_PTP_H__
+#ifndef	__STMMAC_PTP_H__
-#define __STMMAC_PTP_H__
+#define	__STMMAC_PTP_H__
-/* IEEE 1588 PTP register offsets */
+#define	PTP_GMAC4_OFFSET	0xb00
-#define PTP_TCR		0x0700	/* Timestamp Control Reg */
+#define	PTP_GMAC3_X_OFFSET	0x700
-#define PTP_SSIR	0x0704	/* Sub-Second Increment Reg */
-#define PTP_STSR	0x0708	/* System Time – Seconds Regr */
-#define PTP_STNSR	0x070C	/* System Time – Nanoseconds Reg */
-#define PTP_STSUR	0x0710	/* System Time – Seconds Update Reg */
-#define PTP_STNSUR	0x0714	/* System Time – Nanoseconds Update Reg */
-#define PTP_TAR		0x0718	/* Timestamp Addend Reg */
-#define PTP_TTSR	0x071C	/* Target Time Seconds Reg */
-#define PTP_TTNSR	0x0720	/* Target Time Nanoseconds Reg */
-#define	PTP_STHWSR	0x0724	/* System Time - Higher Word Seconds Reg */
-#define PTP_TSR		0x0728	/* Timestamp Status */
-#define PTP_STNSUR_ADDSUB_SHIFT 31
+/* IEEE 1588 PTP register offsets */
+#define	PTP_TCR		0x00	/* Timestamp Control Reg */
+#define	PTP_SSIR	0x04	/* Sub-Second Increment Reg */
+#define	PTP_STSR	0x08	/* System Time – Seconds Regr */
+#define	PTP_STNSR	0x0c	/* System Time – Nanoseconds Reg */
+#define	PTP_STSUR	0x10	/* System Time – Seconds Update Reg */
+#define	PTP_STNSUR	0x14	/* System Time – Nanoseconds Update Reg */
+#define	PTP_TAR		0x18	/* Timestamp Addend Reg */
-/* PTP TCR defines */
+#define	PTP_STNSUR_ADDSUB_SHIFT	31
-#define PTP_TCR_TSENA		0x00000001 /* Timestamp Enable */
+#define	PTP_DIGITAL_ROLLOVER_MODE	0x3B9ACA00	/* 10e9-1 ns */
-#define PTP_TCR_TSCFUPDT	0x00000002 /* Timestamp Fine/Coarse Update */
+#define	PTP_BINARY_ROLLOVER_MODE	0x80000000	/* ~0.466 ns */
-#define PTP_TCR_TSINIT		0x00000004 /* Timestamp Initialize */
-#define PTP_TCR_TSUPDT		0x00000008 /* Timestamp Update */
-/* Timestamp Interrupt Trigger Enable */
-#define PTP_TCR_TSTRIG		0x00000010
-#define PTP_TCR_TSADDREG	0x00000020 /* Addend Reg Update */
-#define PTP_TCR_TSENALL		0x00000100 /* Enable Timestamp for All Frames */
-/* Timestamp Digital or Binary Rollover Control */
-#define PTP_TCR_TSCTRLSSR	0x00000200
+/* PTP Timestamp control register defines */
+#define	PTP_TCR_TSENA		BIT(0)	/* Timestamp Enable */
+#define	PTP_TCR_TSCFUPDT	BIT(1)	/* Timestamp Fine/Coarse Update */
+#define	PTP_TCR_TSINIT		BIT(2)	/* Timestamp Initialize */
+#define	PTP_TCR_TSUPDT		BIT(3)	/* Timestamp Update */
+#define	PTP_TCR_TSTRIG		BIT(4)	/* Timestamp Interrupt Trigger Enable */
+#define	PTP_TCR_TSADDREG	BIT(5)	/* Addend Reg Update */
+#define	PTP_TCR_TSENALL		BIT(8)	/* Enable Timestamp for All Frames */
+#define	PTP_TCR_TSCTRLSSR	BIT(9)	/* Digital or Binary Rollover Control */
 /* Enable PTP packet Processing for Version 2 Format */
-#define PTP_TCR_TSVER2ENA	0x00000400
+#define	PTP_TCR_TSVER2ENA	BIT(10)
 /* Enable Processing of PTP over Ethernet Frames */
-#define PTP_TCR_TSIPENA		0x00000800
+#define	PTP_TCR_TSIPENA		BIT(11)
 /* Enable Processing of PTP Frames Sent over IPv6-UDP */
-#define PTP_TCR_TSIPV6ENA	0x00001000
+#define	PTP_TCR_TSIPV6ENA	BIT(12)
 /* Enable Processing of PTP Frames Sent over IPv4-UDP */
-#define PTP_TCR_TSIPV4ENA	0x00002000
+#define	PTP_TCR_TSIPV4ENA	BIT(13)
 /* Enable Timestamp Snapshot for Event Messages */
-#define PTP_TCR_TSEVNTENA	0x00004000
+#define	PTP_TCR_TSEVNTENA	BIT(14)
 /* Enable Snapshot for Messages Relevant to Master */
-#define PTP_TCR_TSMSTRENA	0x00008000
+#define	PTP_TCR_TSMSTRENA	BIT(15)
 /* Select PTP packets for Taking Snapshots */
-#define PTP_TCR_SNAPTYPSEL_1	0x00010000
+#define	PTP_TCR_SNAPTYPSEL_1	GENMASK(17, 16)
 /* Enable MAC address for PTP Frame Filtering */
-#define PTP_TCR_TSENMACADDR	0x00040000
+#define	PTP_TCR_TSENMACADDR	BIT(18)
+/* SSIR defines */
+#define	PTP_SSIR_SSINC_MASK		0xff
+#define	GMAC4_PTP_SSIR_SSINC_SHIFT	16
-#endif /* __STMMAC_PTP_H__ */
+#endif	/* __STMMAC_PTP_H__ */

drivers/net/ethernet/sun/sunbmac.c+3−2

 	void __iomem *gregs        = bp->gregs;
 	void __iomem *cregs        = bp->creg;
 	void __iomem *bregs        = bp->bregs;
+	__u32 bblk_dvma = (__u32)bp->bblock_dvma;
 	unsigned char *e = &bp->dev->dev_addr[0];
 	/* Latch current counters into statistics. */
 		    bregs + BMAC_XIFCFG);
 	/* Tell the QEC where the ring descriptors are. */
-	sbus_writel(bp->bblock_dvma + bib_offset(be_rxd, 0),
+	sbus_writel(bblk_dvma + bib_offset(be_rxd, 0),
 		    cregs + CREG_RXDS);
-	sbus_writel(bp->bblock_dvma + bib_offset(be_txd, 0),
+	sbus_writel(bblk_dvma + bib_offset(be_txd, 0),
 		    cregs + CREG_TXDS);
 	/* Setup the FIFO pointers into QEC local memory. */

drivers/net/ethernet/sun/sunbmac.h+1−1

@@ -291,7 +291,7 @@ struct bigmac { · 290 unmodified lines
291	void __iomem bregs; / BigMAC Registers */	291	void __iomem bregs; / BigMAC Registers */
292	void __iomem tregs; / BigMAC Transceiver */	292	void __iomem tregs; / BigMAC Transceiver */
293	struct bmac_init_block bmac_block; / RX and TX descriptors */	293	struct bmac_init_block bmac_block; / RX and TX descriptors */
294	__u32 bblock_dvma; /* RX and TX descriptors */	294	dma_addr_t bblock_dvma; /* RX and TX descriptors */
295		295
296	spinlock_t lock;	296	spinlock_t lock;
297		297

drivers/net/ethernet/sun/sunqe.c+6−5

 {
 	struct qe_init_block *qb = qep->qe_block;
 	struct sunqe_buffers *qbufs = qep->buffers;
-	__u32 qbufs_dvma = qep->buffers_dvma;
+	__u32 qbufs_dvma = (__u32)qep->buffers_dvma;
 	int i;
 	qep->rx_new = qep->rx_old = qep->tx_new = qep->tx_old = 0;
 	void __iomem *mregs = qep->mregs;
 	void __iomem *gregs = qecp->gregs;
 	unsigned char *e = &qep->dev->dev_addr[0];
+	__u32 qblk_dvma = (__u32)qep->qblock_dvma;
 	u32 tmp;
 	int i;
 		return -EAGAIN;
 	/* Setup initial rx/tx init block pointers. */
-	sbus_writel(qep->qblock_dvma + qib_offset(qe_rxd, 0), cregs + CREG_RXDS);
+	sbus_writel(qblk_dvma + qib_offset(qe_rxd, 0), cregs + CREG_RXDS);
-	sbus_writel(qep->qblock_dvma + qib_offset(qe_txd, 0), cregs + CREG_TXDS);
+	sbus_writel(qblk_dvma + qib_offset(qe_txd, 0), cregs + CREG_TXDS);
 	/* Enable/mask the various irq's. */
 	sbus_writel(0, cregs + CREG_RIMASK);
 	struct net_device *dev = qep->dev;
 	struct qe_rxd *this;
 	struct sunqe_buffers *qbufs = qep->buffers;
-	__u32 qbufs_dvma = qep->buffers_dvma;
+	__u32 qbufs_dvma = (__u32)qep->buffers_dvma;
 	int elem = qep->rx_new;
 	u32 flags;
 {
 	struct sunqe *qep = netdev_priv(dev);
 	struct sunqe_buffers *qbufs = qep->buffers;
-	__u32 txbuf_dvma, qbufs_dvma = qep->buffers_dvma;
+	__u32 txbuf_dvma, qbufs_dvma = (__u32)qep->buffers_dvma;
 	unsigned char *txbuf;
 	int len, entry;

drivers/net/ethernet/sun/sunqe.h+2−2

@@ -334,12 +334,12 @@ struct sunqe { · 333 unmodified lines
334	void __iomem qcregs; / QEC per-channel Registers */	334	void __iomem qcregs; / QEC per-channel Registers */
335	void __iomem mregs; / Per-channel MACE Registers */	335	void __iomem mregs; / Per-channel MACE Registers */
336	struct qe_init_block qe_block; / RX and TX descriptors */	336	struct qe_init_block qe_block; / RX and TX descriptors */
337	__u32 qblock_dvma; /* RX and TX descriptors */	337	dma_addr_t qblock_dvma; /* RX and TX descriptors */
338	spinlock_t lock; /* Protects txfull state */	338	spinlock_t lock; /* Protects txfull state */
339	int rx_new, rx_old; /* RX ring extents */	339	int rx_new, rx_old; /* RX ring extents */
340	int tx_new, tx_old; /* TX ring extents */	340	int tx_new, tx_old; /* TX ring extents */
341	struct sunqe_buffers buffers; / CPU visible address. */	341	struct sunqe_buffers buffers; / CPU visible address. */
342	__u32 buffers_dvma; /* DVMA visible address. */	342	dma_addr_t buffers_dvma; /* DVMA visible address. */
343	struct sunqec *parent;	343	struct sunqec *parent;
344	u8 mconfig; /* Base MACE mconfig value */	344	u8 mconfig; /* Base MACE mconfig value */
345	struct platform_device op; / QE's OF device struct */	345	struct platform_device op; / QE's OF device struct */

drivers/net/ethernet/ti/cpsw.c+74−21

 			 * to the PHY is the Ethernet MAC DT node.
 			 */
 			ret = of_phy_register_fixed_link(slave_node);
-			if (ret)
+			if (ret) {
+				if (ret != -EPROBE_DEFER)
+					dev_err(&pdev->dev, "failed to register fixed-link phy: %d\n", ret);
 				return ret;
+			}
 			slave_data->phy_node = of_node_get(slave_node);
 		} else if (parp) {
 			u32 phyid;
 			}
 			snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
 				 PHY_ID_FMT, mdio->name, phyid);
+			put_device(&mdio->dev);
 		} else {
 			dev_err(&pdev->dev,
 				"No slave[%d] phy_id, phy-handle, or fixed-link property\n",
 	return 0;
 }
+static void cpsw_remove_dt(struct platform_device *pdev)
+{
+	struct net_device *ndev = platform_get_drvdata(pdev);
+	struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
+	struct cpsw_platform_data *data = &cpsw->data;
+	struct device_node *node = pdev->dev.of_node;
+	struct device_node *slave_node;
+	int i = 0;
+	for_each_available_child_of_node(node, slave_node) {
+		struct cpsw_slave_data *slave_data = &data->slave_data[i];
+		if (strcmp(slave_node->name, "slave"))
+			continue;
+		if (of_phy_is_fixed_link(slave_node)) {
+			struct phy_device *phydev;
+			phydev = of_phy_find_device(slave_node);
+			if (phydev) {
+				fixed_phy_unregister(phydev);
+				/* Put references taken by
+				 * of_phy_find_device() and
+				 * of_phy_register_fixed_link().
+				 */
+				phy_device_free(phydev);
+				phy_device_free(phydev);
+			}
+		}
+		of_node_put(slave_data->phy_node);
+		i++;
+		if (i == data->slaves)
+			break;
+	}
+	of_platform_depopulate(&pdev->dev);
+}
 static int cpsw_probe_dual_emac(struct cpsw_priv *priv)
 {
 	struct cpsw_common		*cpsw = priv->cpsw;
 	int irq;
 	cpsw = devm_kzalloc(&pdev->dev, sizeof(struct cpsw_common), GFP_KERNEL);
+	if (!cpsw)
+		return -ENOMEM;
 	cpsw->dev = &pdev->dev;
 	ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES);
 	/* Select default pin state */
 	pinctrl_pm_select_default_state(&pdev->dev);
-	if (cpsw_probe_dt(&cpsw->data, pdev)) {
+	/* Need to enable clocks with runtime PM api to access module
-		dev_err(&pdev->dev, "cpsw: platform data missing\n");
+	 * registers
-		ret = -ENODEV;
+	 */
+	ret = pm_runtime_get_sync(&pdev->dev);
+	if (ret < 0) {
+		pm_runtime_put_noidle(&pdev->dev);
 		goto clean_runtime_disable_ret;
 	}
+	ret = cpsw_probe_dt(&cpsw->data, pdev);
+	if (ret)
+		goto clean_dt_ret;
 	data = &cpsw->data;
 	cpsw->rx_ch_num = 1;
 	cpsw->tx_ch_num = 1;
 				    GFP_KERNEL);
 	if (!cpsw->slaves) {
 		ret = -ENOMEM;
-		goto clean_runtime_disable_ret;
+		goto clean_dt_ret;
 	}
 	for (i = 0; i < data->slaves; i++)
 		cpsw->slaves[i].slave_num = i;
 	if (IS_ERR(clk)) {
 		dev_err(priv->dev, "fck is not found\n");
 		ret = -ENODEV;
-		goto clean_runtime_disable_ret;
+		goto clean_dt_ret;
 	}
 	cpsw->bus_freq_mhz = clk_get_rate(clk) / 1000000;
 	ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
 	if (IS_ERR(ss_regs)) {
 		ret = PTR_ERR(ss_regs);
-		goto clean_runtime_disable_ret;
+		goto clean_dt_ret;
 	}
 	cpsw->regs = ss_regs;
-	/* Need to enable clocks with runtime PM api to access module
-	 * registers
-	 */
-	ret = pm_runtime_get_sync(&pdev->dev);
-	if (ret < 0) {
-		pm_runtime_put_noidle(&pdev->dev);
-		goto clean_runtime_disable_ret;
-	}
 	cpsw->version = readl(&cpsw->regs->id_ver);
-	pm_runtime_put_sync(&pdev->dev);
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 	cpsw->wr_regs = devm_ioremap_resource(&pdev->dev, res);
 	if (IS_ERR(cpsw->wr_regs)) {
 		ret = PTR_ERR(cpsw->wr_regs);
-		goto clean_runtime_disable_ret;
+		goto clean_dt_ret;
 	}
 	memset(&dma_params, 0, sizeof(dma_params));
 	default:
 		dev_err(priv->dev, "unknown version 0x%08x\n", cpsw->version);
 		ret = -ENODEV;
-		goto clean_runtime_disable_ret;
+		goto clean_dt_ret;
 	}
 	for (i = 0; i < cpsw->data.slaves; i++) {
 		struct cpsw_slave *slave = &cpsw->slaves[i];
 	if (!cpsw->dma) {
 		dev_err(priv->dev, "error initializing dma\n");
 		ret = -ENOMEM;
-		goto clean_runtime_disable_ret;
+		goto clean_dt_ret;
 	}
 	cpsw->txch[0] = cpdma_chan_create(cpsw->dma, 0, cpsw_tx_handler, 0);
 		ret = cpsw_probe_dual_emac(priv);
 		if (ret) {
 			cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
-			goto clean_ale_ret;
+			goto clean_unregister_netdev_ret;
 		}
 	}
+	pm_runtime_put(&pdev->dev);
 	return 0;
+clean_unregister_netdev_ret:
+	unregister_netdev(ndev);
 clean_ale_ret:
 	cpsw_ale_destroy(cpsw->ale);
 clean_dma_ret:
 	cpdma_ctlr_destroy(cpsw->dma);
+clean_dt_ret:
+	cpsw_remove_dt(pdev);
+	pm_runtime_put_sync(&pdev->dev);
 clean_runtime_disable_ret:
 	pm_runtime_disable(&pdev->dev);
 clean_ndev_ret:
 	cpsw_ale_destroy(cpsw->ale);
 	cpdma_ctlr_destroy(cpsw->dma);
-	of_platform_depopulate(&pdev->dev);
+	cpsw_remove_dt(pdev);
 	pm_runtime_put_sync(&pdev->dev);
 	pm_runtime_disable(&pdev->dev);
 	if (cpsw->data.dual_emac)

drivers/net/phy/fixed_phy.c+1−1

@@ -279,7 +279,7 @@ EXPORT_SYMBOL_GPL(fixed_phy_register); · 278 unmodified lines
279	void fixed_phy_unregister(struct phy_device *phy)	279	void fixed_phy_unregister(struct phy_device *phy)
280	{	280	{
281	phy_device_remove(phy);	281	phy_device_remove(phy);
282		282	of_node_put(phy->mdio.dev.of_node);
283	fixed_phy_del(phy->mdio.addr);	283	fixed_phy_del(phy->mdio.addr);
284	}	284	}
285	EXPORT_SYMBOL_GPL(fixed_phy_unregister);	285	EXPORT_SYMBOL_GPL(fixed_phy_unregister);

drivers/net/phy/vitesse.c+33−1

@@ -62,6 +62,10 @@ · 61 unmodified lines
62	/* Vitesse Extended Page Access Register */	62	/* Vitesse Extended Page Access Register */
63	#define MII_VSC82X4_EXT_PAGE_ACCESS 0x1f	63	#define MII_VSC82X4_EXT_PAGE_ACCESS 0x1f
64		64
		65	/* Vitesse VSC8601 Extended PHY Control Register 1 */
		66	#define MII_VSC8601_EPHY_CTL 0x17
		67	#define MII_VSC8601_EPHY_CTL_RGMII_SKEW (1 << 8)
		68
65	#define PHY_ID_VSC8234 0x000fc620	69	#define PHY_ID_VSC8234 0x000fc620
66	#define PHY_ID_VSC8244 0x000fc6c0	70	#define PHY_ID_VSC8244 0x000fc6c0
67	#define PHY_ID_VSC8514 0x00070670	71	#define PHY_ID_VSC8514 0x00070670
@@ -111,6 +115,34 @@ static int vsc824x_config_init(struct phy_device *phydev) · 43 unmodified lines
111	return err;	115	return err;
112	}	116	}
113		117
		118	/* This adds a skew for both TX and RX clocks, so the skew should only be
		119	* applied to "rgmii-id" interfaces. It may not work as expected
		120	* on "rgmii-txid", "rgmii-rxid" or "rgmii" interfaces. */
		121	static int vsc8601_add_skew(struct phy_device *phydev)
		122	{
		123	int ret;
		124
		125	ret = phy_read(phydev, MII_VSC8601_EPHY_CTL);
		126	if (ret < 0)
		127	return ret;
		128
		129	ret \|= MII_VSC8601_EPHY_CTL_RGMII_SKEW;
		130	return phy_write(phydev, MII_VSC8601_EPHY_CTL, ret);
		131	}
		132
		133	static int vsc8601_config_init(struct phy_device *phydev)
		134	{
		135	int ret = 0;
		136
		137	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
		138	ret = vsc8601_add_skew(phydev);
		139
		140	if (ret < 0)
		141	return ret;
		142
		143	return genphy_config_init(phydev);
		144	}
		145
114	static int vsc824x_ack_interrupt(struct phy_device *phydev)	146	static int vsc824x_ack_interrupt(struct phy_device *phydev)
115	{	147	{
116	int err = 0;	148	int err = 0;
@@ -275,7 +307,7 @@ static struct phy_driver vsc82xx_driver[] = { · 158 unmodified lines
275	.phy_id_mask = 0x000ffff0,	307	.phy_id_mask = 0x000ffff0,
276	.features = PHY_GBIT_FEATURES,	308	.features = PHY_GBIT_FEATURES,
277	.flags = PHY_HAS_INTERRUPT,	309	.flags = PHY_HAS_INTERRUPT,
278	.config_init = &genphy_config_init,	310	.config_init = &vsc8601_config_init,
279	.config_aneg = &genphy_config_aneg,	311	.config_aneg = &genphy_config_aneg,
280	.read_status = &genphy_read_status,	312	.read_status = &genphy_read_status,
281	.ack_interrupt = &vsc824x_ack_interrupt,	313	.ack_interrupt = &vsc824x_ack_interrupt,

drivers/net/virtio_net.c+5−0

 		netif_napi_del(&vi->rq[i].napi);
 	}
+	/* We called napi_hash_del() before netif_napi_del(),
+	 * we need to respect an RCU grace period before freeing vi->rq
+	 */
+	synchronize_net();
 	kfree(vi->rq);
 	kfree(vi->sq);
 }

drivers/net/wireless/mac80211_hwsim.c+1−1

@@ -819,7 +819,7 @@ static void mac80211_hwsim_set_tsf(struct ieee80211_hw *hw, · 818 unmodified lines
819	data->bcn_delta = do_div(delta, bcn_int);	819	data->bcn_delta = do_div(delta, bcn_int);
820	} else {	820	} else {
821	data->tsf_offset -= delta;	821	data->tsf_offset -= delta;
822	data->bcn_delta = -do_div(delta, bcn_int);	822	data->bcn_delta = -(s64)do_div(delta, bcn_int);
823	}	823	}
824	}	824	}
825		825

drivers/nvme/host/pci.c+4−14

 	result = nvme_enable_ctrl(&dev->ctrl, cap);
 	if (result)
-		goto free_nvmeq;
+		return result;
 	nvmeq->cq_vector = 0;
 	result = queue_request_irq(nvmeq);
 	if (result) {
 		nvmeq->cq_vector = -1;
-		goto free_nvmeq;
+		return result;
 	}
 	return result;
- free_nvmeq:
-	nvme_free_queues(dev, 0);
-	return result;
 }
 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
 	max = min(dev->max_qid, dev->queue_count - 1);
 	for (i = dev->online_queues; i <= max; i++) {
 		ret = nvme_create_queue(dev->queues[i], i);
-		if (ret) {
+		if (ret)
-			nvme_free_queues(dev, i);
 			break;
-		}
 	}
 	/*
 	result = queue_request_irq(adminq);
 	if (result) {
 		adminq->cq_vector = -1;
-		goto free_queues;
+		return result;
 	}
 	return nvme_create_io_queues(dev);
- free_queues:
-	nvme_free_queues(dev, 1);
-	return result;
 }
 static void nvme_del_queue_end(struct request *req, int error)

drivers/nvme/host/rdma.c+39−3

 	NVME_RDMA_Q_CONNECTED = (1 << 0),
 	NVME_RDMA_IB_QUEUE_ALLOCATED = (1 << 1),
 	NVME_RDMA_Q_DELETING = (1 << 2),
+	NVME_RDMA_Q_LIVE = (1 << 3),
 };
 struct nvme_rdma_queue {
 	for (i = 1; i < ctrl->queue_count; i++) {
 		ret = nvmf_connect_io_queue(&ctrl->ctrl, i);
-		if (ret)
+		if (ret) {
-			break;
+			dev_info(ctrl->ctrl.device,
+				"failed to connect i/o queue: %d\n", ret);
+			goto out_free_queues;
+		}
+		set_bit(NVME_RDMA_Q_LIVE, &ctrl->queues[i].flags);
 	}
+	return 0;
+out_free_queues:
+	nvme_rdma_free_io_queues(ctrl);
 	return ret;
 }
 	if (ret)
 		goto stop_admin_q;
+	set_bit(NVME_RDMA_Q_LIVE, &ctrl->queues[0].flags);
 	ret = nvme_enable_ctrl(&ctrl->ctrl, ctrl->cap);
 	if (ret)
 		goto stop_admin_q;
 	nvme_stop_keep_alive(&ctrl->ctrl);
-	for (i = 0; i < ctrl->queue_count; i++)
+	for (i = 0; i < ctrl->queue_count; i++) {
 		clear_bit(NVME_RDMA_Q_CONNECTED, &ctrl->queues[i].flags);
+		clear_bit(NVME_RDMA_Q_LIVE, &ctrl->queues[i].flags);
+	}
 	if (ctrl->queue_count > 1)
 		nvme_stop_queues(&ctrl->ctrl);
 	return BLK_EH_HANDLED;
 }
+/*
+ * We cannot accept any other command until the Connect command has completed.
+ */
+static inline bool nvme_rdma_queue_is_ready(struct nvme_rdma_queue *queue,
+		struct request *rq)
+{
+	if (unlikely(!test_bit(NVME_RDMA_Q_LIVE, &queue->flags))) {
+		struct nvme_command *cmd = (struct nvme_command *)rq->cmd;
+		if (rq->cmd_type != REQ_TYPE_DRV_PRIV ||
+		    cmd->common.opcode != nvme_fabrics_command ||
+		    cmd->fabrics.fctype != nvme_fabrics_type_connect)
+			return false;
+	}
+	return true;
+}
 static int nvme_rdma_queue_rq(struct blk_mq_hw_ctx *hctx,
 		const struct blk_mq_queue_data *bd)
 {
 	WARN_ON_ONCE(rq->tag < 0);
+	if (!nvme_rdma_queue_is_ready(queue, rq))
+		return BLK_MQ_RQ_QUEUE_BUSY;
 	dev = queue->device->dev;
 	ib_dma_sync_single_for_cpu(dev, sqe->dma,
 			sizeof(struct nvme_command), DMA_TO_DEVICE);
 	if (error)
 		goto out_cleanup_queue;
+	set_bit(NVME_RDMA_Q_LIVE, &ctrl->queues[0].flags);
 	error = nvmf_reg_read64(&ctrl->ctrl, NVME_REG_CAP, &ctrl->cap);
 	if (error) {
 		dev_err(ctrl->ctrl.device,

drivers/nvme/target/core.c+7−3

 void nvmet_ctrl_fatal_error(struct nvmet_ctrl *ctrl)
 {
-	ctrl->csts |= NVME_CSTS_CFS;
+	mutex_lock(&ctrl->lock);
-	INIT_WORK(&ctrl->fatal_err_work, nvmet_fatal_error_handler);
+	if (!(ctrl->csts & NVME_CSTS_CFS)) {
-	schedule_work(&ctrl->fatal_err_work);
+		ctrl->csts |= NVME_CSTS_CFS;
+		INIT_WORK(&ctrl->fatal_err_work, nvmet_fatal_error_handler);
+		schedule_work(&ctrl->fatal_err_work);
+	}
+	mutex_unlock(&ctrl->lock);
 }
 EXPORT_SYMBOL_GPL(nvmet_ctrl_fatal_error);

drivers/nvme/target/rdma.c+15−3

 static void nvmet_rdma_destroy_queue_ib(struct nvmet_rdma_queue *queue)
 {
+	ib_drain_qp(queue->cm_id->qp);
 	rdma_destroy_qp(queue->cm_id);
 	ib_free_cq(queue->cq);
 }
 	spin_lock_init(&queue->rsp_wr_wait_lock);
 	INIT_LIST_HEAD(&queue->free_rsps);
 	spin_lock_init(&queue->rsps_lock);
+	INIT_LIST_HEAD(&queue->queue_list);
 	queue->idx = ida_simple_get(&nvmet_rdma_queue_ida, 0, 0, GFP_KERNEL);
 	if (queue->idx < 0) {
 	if (disconnect) {
 		rdma_disconnect(queue->cm_id);
-		ib_drain_qp(queue->cm_id->qp);
 		schedule_work(&queue->release_work);
 	}
 }
 {
 	WARN_ON_ONCE(queue->state != NVMET_RDMA_Q_CONNECTING);
-	pr_err("failed to connect queue\n");
+	mutex_lock(&nvmet_rdma_queue_mutex);
+	if (!list_empty(&queue->queue_list))
+		list_del_init(&queue->queue_list);
+	mutex_unlock(&nvmet_rdma_queue_mutex);
+	pr_err("failed to connect queue %d\n", queue->idx);
 	schedule_work(&queue->release_work);
 }
 	case RDMA_CM_EVENT_ADDR_CHANGE:
 	case RDMA_CM_EVENT_DISCONNECTED:
 	case RDMA_CM_EVENT_TIMEWAIT_EXIT:
-		nvmet_rdma_queue_disconnect(queue);
+		/*
+		 * We might end up here when we already freed the qp
+		 * which means queue release sequence is in progress,
+		 * so don't get in the way...
+		 */
+		if (queue)
+			nvmet_rdma_queue_disconnect(queue);
 		break;
 	case RDMA_CM_EVENT_DEVICE_REMOVAL:
 		ret = nvmet_rdma_device_removal(cm_id, queue);

drivers/of/of_mdio.c+5−1

 		mdiodev = to_mdio_device(d);
 		if (mdiodev->flags & MDIO_DEVICE_FLAG_PHY)
 			return to_phy_device(d);
+		put_device(d);
 	}
 	return NULL;
 		status.link = 1;
 		status.duplex = of_property_read_bool(fixed_link_node,
 						      "full-duplex");
-		if (of_property_read_u32(fixed_link_node, "speed", &status.speed))
+		if (of_property_read_u32(fixed_link_node, "speed",
+					 &status.speed)) {
+			of_node_put(fixed_link_node);
 			return -EINVAL;
+		}
 		status.pause = of_property_read_bool(fixed_link_node, "pause");
 		status.asym_pause = of_property_read_bool(fixed_link_node,
 							  "asym-pause");

drivers/video/fbdev/amba-clcd-versatile.c+2−2

@@ -526,8 +526,8 @@ int versatile_clcd_init_panel(struct clcd_fb *fb, · 525 unmodified lines
526	np = of_find_matching_node_and_match(NULL, versatile_clcd_of_match,	526	np = of_find_matching_node_and_match(NULL, versatile_clcd_of_match,
527	&clcd_id);	527	&clcd_id);
528	if (!np) {	528	if (!np) {
529	dev_err(dev, "no Versatile syscon node\n");	529	/* Vexpress does not have this */
530	return -ENODEV;	530	return 0;
531	}	531	}
532	versatile_clcd_type = (enum versatile_clcd)clcd_id->data;	532	versatile_clcd_type = (enum versatile_clcd)clcd_id->data;
533		533

fs/crypto/fname.c+21−32

 static int fname_encrypt(struct inode *inode,
 			const struct qstr *iname, struct fscrypt_str *oname)
 {
-	u32 ciphertext_len;
 	struct skcipher_request *req = NULL;
 	DECLARE_FS_COMPLETION_RESULT(ecr);
 	struct fscrypt_info *ci = inode->i_crypt_info;
 	struct crypto_skcipher *tfm = ci->ci_ctfm;
 	int res = 0;
 	char iv[FS_CRYPTO_BLOCK_SIZE];
-	struct scatterlist src_sg, dst_sg;
+	struct scatterlist sg;
 	int padding = 4 << (ci->ci_flags & FS_POLICY_FLAGS_PAD_MASK);
-	char *workbuf, buf[32], *alloc_buf = NULL;
+	unsigned int lim;
-	unsigned lim;
+	unsigned int cryptlen;
 	lim = inode->i_sb->s_cop->max_namelen(inode);
 	if (iname->len <= 0 || iname->len > lim)
 		return -EIO;
-	ciphertext_len = max(iname->len, (u32)FS_CRYPTO_BLOCK_SIZE);
+	/*
-	ciphertext_len = round_up(ciphertext_len, padding);
+	 * Copy the filename to the output buffer for encrypting in-place and
-	ciphertext_len = min(ciphertext_len, lim);
+	 * pad it with the needed number of NUL bytes.
+	 */
+	cryptlen = max_t(unsigned int, iname->len, FS_CRYPTO_BLOCK_SIZE);
+	cryptlen = round_up(cryptlen, padding);
+	cryptlen = min(cryptlen, lim);
+	memcpy(oname->name, iname->name, iname->len);
+	memset(oname->name + iname->len, 0, cryptlen - iname->len);
-	if (ciphertext_len <= sizeof(buf)) {
+	/* Initialize the IV */
-		workbuf = buf;
+	memset(iv, 0, FS_CRYPTO_BLOCK_SIZE);
-	} else {
-		alloc_buf = kmalloc(ciphertext_len, GFP_NOFS);
-		if (!alloc_buf)
-			return -ENOMEM;
-		workbuf = alloc_buf;
-	}
-	/* Allocate request */
+	/* Set up the encryption request */
 	req = skcipher_request_alloc(tfm, GFP_NOFS);
 	if (!req) {
 		printk_ratelimited(KERN_ERR
-			"%s: crypto_request_alloc() failed\n", __func__);
+			"%s: skcipher_request_alloc() failed\n", __func__);
-		kfree(alloc_buf);
 		return -ENOMEM;
 	}
 	skcipher_request_set_callback(req,
 			CRYPTO_TFM_REQ_MAY_BACKLOG | CRYPTO_TFM_REQ_MAY_SLEEP,
 			fname_crypt_complete, &ecr);
+	sg_init_one(&sg, oname->name, cryptlen);
+	skcipher_request_set_crypt(req, &sg, &sg, cryptlen, iv);
-	/* Copy the input */
+	/* Do the encryption */
-	memcpy(workbuf, iname->name, iname->len);
-	if (iname->len < ciphertext_len)
-		memset(workbuf + iname->len, 0, ciphertext_len - iname->len);
-	/* Initialize IV */
-	memset(iv, 0, FS_CRYPTO_BLOCK_SIZE);
-	/* Create encryption request */
-	sg_init_one(&src_sg, workbuf, ciphertext_len);
-	sg_init_one(&dst_sg, oname->name, ciphertext_len);
-	skcipher_request_set_crypt(req, &src_sg, &dst_sg, ciphertext_len, iv);
 	res = crypto_skcipher_encrypt(req);
 	if (res == -EINPROGRESS || res == -EBUSY) {
+		/* Request is being completed asynchronously; wait for it */
 		wait_for_completion(&ecr.completion);
 		res = ecr.res;
 	}
-	kfree(alloc_buf);
 	skcipher_request_free(req);
 	if (res < 0) {
 		printk_ratelimited(KERN_ERR
 		return res;
 	}
-	oname->len = ciphertext_len;
+	oname->len = cryptlen;
 	return 0;
 }

fs/crypto/keyinfo.c+13−3

 	struct crypto_skcipher *ctfm;
 	const char *cipher_str;
 	int keysize;
-	u8 raw_key[FS_MAX_KEY_SIZE];
+	u8 *raw_key = NULL;
 	int res;
 	res = fscrypt_initialize();
 	if (res)
 		goto out;
+	/*
+	 * This cannot be a stack buffer because it is passed to the scatterlist
+	 * crypto API as part of key derivation.
+	 */
+	res = -ENOMEM;
+	raw_key = kmalloc(FS_MAX_KEY_SIZE, GFP_NOFS);
+	if (!raw_key)
+		goto out;
 	if (fscrypt_dummy_context_enabled(inode)) {
 		memset(raw_key, 0x42, FS_AES_256_XTS_KEY_SIZE);
 		goto got_key;
 	if (res)
 		goto out;
-	memzero_explicit(raw_key, sizeof(raw_key));
+	kzfree(raw_key);
+	raw_key = NULL;
 	if (cmpxchg(&inode->i_crypt_info, NULL, crypt_info) != NULL) {
 		put_crypt_info(crypt_info);
 		goto retry;
 	if (res == -ENOKEY)
 		res = 0;
 	put_crypt_info(crypt_info);
-	memzero_explicit(raw_key, sizeof(raw_key));
+	kzfree(raw_key);
 	return res;
 }

fs/ext4/ext4.h+1−0

@@ -235,6 +235,7 @@ struct ext4_io_submit { · 234 unmodified lines
235	#define EXT4_MAX_BLOCK_SIZE 65536	235	#define EXT4_MAX_BLOCK_SIZE 65536
236	#define EXT4_MIN_BLOCK_LOG_SIZE 10	236	#define EXT4_MIN_BLOCK_LOG_SIZE 10
237	#define EXT4_MAX_BLOCK_LOG_SIZE 16	237	#define EXT4_MAX_BLOCK_LOG_SIZE 16
		238	#define EXT4_MAX_CLUSTER_LOG_SIZE 30
238	#ifdef __KERNEL__	239	#ifdef __KERNEL__
239	# define EXT4_BLOCK_SIZE(s) ((s)->s_blocksize)	240	# define EXT4_BLOCK_SIZE(s) ((s)->s_blocksize)
240	#else	241	#else

fs/ext4/super.c+16−1

@@ -3565,7 +3565,15 @@ static int ext4_fill_super(struct super_block sb, void data, int silent) · 3564 unmodified lines
3565	if (blocksize < EXT4_MIN_BLOCK_SIZE \|\|	3565	if (blocksize < EXT4_MIN_BLOCK_SIZE \|\|
3566	blocksize > EXT4_MAX_BLOCK_SIZE) {	3566	blocksize > EXT4_MAX_BLOCK_SIZE) {
3567	ext4_msg(sb, KERN_ERR,	3567	ext4_msg(sb, KERN_ERR,
3568	"Unsupported filesystem blocksize %d", blocksize);	3568	"Unsupported filesystem blocksize %d (%d log_block_size)",
		3569	blocksize, le32_to_cpu(es->s_log_block_size));
		3570	goto failed_mount;
		3571	}
		3572	if (le32_to_cpu(es->s_log_block_size) >
		3573	(EXT4_MAX_BLOCK_LOG_SIZE - EXT4_MIN_BLOCK_LOG_SIZE)) {
		3574	ext4_msg(sb, KERN_ERR,
		3575	"Invalid log block size: %u",
		3576	le32_to_cpu(es->s_log_block_size));
3569	goto failed_mount;	3577	goto failed_mount;
3570	}	3578	}
3571		3579
@@ -3697,6 +3705,13 @@ static int ext4_fill_super(struct super_block sb, void data, int silent) · 125 unmodified lines
3697	"block size (%d)", clustersize, blocksize);	3705	"block size (%d)", clustersize, blocksize);
3698	goto failed_mount;	3706	goto failed_mount;
3699	}	3707	}
		3708	if (le32_to_cpu(es->s_log_cluster_size) >
		3709	(EXT4_MAX_CLUSTER_LOG_SIZE - EXT4_MIN_BLOCK_LOG_SIZE)) {
		3710	ext4_msg(sb, KERN_ERR,
		3711	"Invalid log cluster size: %u",
		3712	le32_to_cpu(es->s_log_cluster_size));
		3713	goto failed_mount;
		3714	}
3700	sbi->s_cluster_bits = le32_to_cpu(es->s_log_cluster_size) -	3715	sbi->s_cluster_bits = le32_to_cpu(es->s_log_cluster_size) -
3701	le32_to_cpu(es->s_log_block_size);	3716	le32_to_cpu(es->s_log_block_size);
3702	sbi->s_clusters_per_group =	3717	sbi->s_clusters_per_group =

fs/fuse/dir.c+5−0

 	.d_release	= fuse_dentry_release,
 };
+const struct dentry_operations fuse_root_dentry_operations = {
+	.d_init		= fuse_dentry_init,
+	.d_release	= fuse_dentry_release,
+};
 int fuse_valid_type(int m)
 {
 	return S_ISREG(m) || S_ISDIR(m) || S_ISLNK(m) || S_ISCHR(m) ||

fs/fuse/file.c+6−0

 {
 	struct inode *inode = page->mapping->host;
+	/* Haven't copied anything?  Skip zeroing, size extending, dirtying. */
+	if (!copied)
+		goto unlock;
 	if (!PageUptodate(page)) {
 		/* Zero any unwritten bytes at the end of the page */
 		size_t endoff = (pos + copied) & ~PAGE_MASK;
 	fuse_write_update_size(inode, pos + copied);
 	set_page_dirty(page);
+unlock:
 	unlock_page(page);
 	put_page(page);

fs/fuse/fuse_i.h+1−0

@@ -692,6 +692,7 @@ static inline u64 get_node_id(struct inode *inode) · 691 unmodified lines
692	extern const struct file_operations fuse_dev_operations;	692	extern const struct file_operations fuse_dev_operations;
693		693
694	extern const struct dentry_operations fuse_dentry_operations;	694	extern const struct dentry_operations fuse_dentry_operations;
		695	extern const struct dentry_operations fuse_root_dentry_operations;
695		696
696	/**	697	/**
697	* Inode to nodeid comparison.	698	* Inode to nodeid comparison.

fs/fuse/inode.c+2−1

 	err = -ENOMEM;
 	root = fuse_get_root_inode(sb, d.rootmode);
+	sb->s_d_op = &fuse_root_dentry_operations;
 	root_dentry = d_make_root(root);
 	if (!root_dentry)
 		goto err_dev_free;
-	/* only now - we want root dentry with NULL ->d_op */
+	/* Root dentry doesn't have .d_revalidate */
 	sb->s_d_op = &fuse_dentry_operations;
 	init_req = fuse_request_alloc(0);

fs/orangefs/orangefs-debugfs.c+2−0

 };
 const struct file_operations debug_help_fops = {
+	.owner		= THIS_MODULE,
 	.open           = orangefs_debug_help_open,
 	.read           = seq_read,
 	.release        = seq_release,
 };
 static const struct file_operations kernel_debug_fops = {
+	.owner		= THIS_MODULE,
 	.open           = orangefs_debug_open,
 	.read           = orangefs_debug_read,
 	.write		= orangefs_debug_write,

fs/xattr.c+14−8

@@ -170,7 +170,7 @@ int __vfs_setxattr_noperm(struct dentry dentry, const char name, · 169 unmodified lines
170	const void *value, size_t size, int flags)	170	const void *value, size_t size, int flags)
171	{	171	{
172	struct inode *inode = dentry->d_inode;	172	struct inode *inode = dentry->d_inode;
173	int error = -EOPNOTSUPP;	173	int error = -EAGAIN;
174	int issec = !strncmp(name, XATTR_SECURITY_PREFIX,	174	int issec = !strncmp(name, XATTR_SECURITY_PREFIX,
175	XATTR_SECURITY_PREFIX_LEN);	175	XATTR_SECURITY_PREFIX_LEN);
176		176
@@ -183,15 +183,21 @@ int __vfs_setxattr_noperm(struct dentry dentry, const char name, · 6 unmodified lines
183	security_inode_post_setxattr(dentry, name, value,	183	security_inode_post_setxattr(dentry, name, value,
184	size, flags);	184	size, flags);
185	}	185	}
186	} else if (issec) {	186	} else {
187	const char *suffix = name + XATTR_SECURITY_PREFIX_LEN;
188
189	if (unlikely(is_bad_inode(inode)))	187	if (unlikely(is_bad_inode(inode)))
190	return -EIO;	188	return -EIO;
191	error = security_inode_setsecurity(inode, suffix, value,	189	}
192	size, flags);	190	if (error == -EAGAIN) {
193	if (!error)	191	error = -EOPNOTSUPP;
194	fsnotify_xattr(dentry);	192
		193	if (issec) {
		194	const char *suffix = name + XATTR_SECURITY_PREFIX_LEN;
		195
		196	error = security_inode_setsecurity(inode, suffix, value,
		197	size, flags);
		198	if (!error)
		199	fsnotify_xattr(dentry);
		200	}
195	}	201	}
196		202
197	return error;	203	return error;

include/acpi/actbl.h+70−94

@@ -230,72 +230,62 @@ struct acpi_table_facs { · 229 unmodified lines
230	/* Fields common to all versions of the FADT */	230	/* Fields common to all versions of the FADT */
231		231
232	struct acpi_table_fadt {	232	struct acpi_table_fadt {
233	struct acpi_table_header header; /* [V1] Common ACPI table header */	233	struct acpi_table_header header; /* Common ACPI table header */
234	u32 facs; /* [V1] 32-bit physical address of FACS */	234	u32 facs; /* 32-bit physical address of FACS */
235	u32 dsdt; /* [V1] 32-bit physical address of DSDT */	235	u32 dsdt; /* 32-bit physical address of DSDT */
236	u8 model; /* [V1] System Interrupt Model (ACPI 1.0) - not used in ACPI 2.0+ */	236	u8 model; /* System Interrupt Model (ACPI 1.0) - not used in ACPI 2.0+ */
237	u8 preferred_profile; /* [V1] Conveys preferred power management profile to OSPM. */	237	u8 preferred_profile; /* Conveys preferred power management profile to OSPM. */
238	u16 sci_interrupt; /* [V1] System vector of SCI interrupt */	238	u16 sci_interrupt; /* System vector of SCI interrupt */
239	u32 smi_command; /* [V1] 32-bit Port address of SMI command port */	239	u32 smi_command; /* 32-bit Port address of SMI command port */
240	u8 acpi_enable; /* [V1] Value to write to SMI_CMD to enable ACPI */	240	u8 acpi_enable; /* Value to write to SMI_CMD to enable ACPI */
241	u8 acpi_disable; /* [V1] Value to write to SMI_CMD to disable ACPI */	241	u8 acpi_disable; /* Value to write to SMI_CMD to disable ACPI */
242	u8 s4_bios_request; /* [V1] Value to write to SMI_CMD to enter S4BIOS state */	242	u8 s4_bios_request; /* Value to write to SMI_CMD to enter S4BIOS state */
243	u8 pstate_control; /* [V1] Processor performance state control */	243	u8 pstate_control; /* Processor performance state control */
244	u32 pm1a_event_block; /* [V1] 32-bit port address of Power Mgt 1a Event Reg Blk */	244	u32 pm1a_event_block; /* 32-bit port address of Power Mgt 1a Event Reg Blk */
245	u32 pm1b_event_block; /* [V1] 32-bit port address of Power Mgt 1b Event Reg Blk */	245	u32 pm1b_event_block; /* 32-bit port address of Power Mgt 1b Event Reg Blk */
246	u32 pm1a_control_block; /* [V1] 32-bit port address of Power Mgt 1a Control Reg Blk */	246	u32 pm1a_control_block; /* 32-bit port address of Power Mgt 1a Control Reg Blk */
247	u32 pm1b_control_block; /* [V1] 32-bit port address of Power Mgt 1b Control Reg Blk */	247	u32 pm1b_control_block; /* 32-bit port address of Power Mgt 1b Control Reg Blk */
248	u32 pm2_control_block; /* [V1] 32-bit port address of Power Mgt 2 Control Reg Blk */	248	u32 pm2_control_block; /* 32-bit port address of Power Mgt 2 Control Reg Blk */
249	u32 pm_timer_block; /* [V1] 32-bit port address of Power Mgt Timer Ctrl Reg Blk */	249	u32 pm_timer_block; /* 32-bit port address of Power Mgt Timer Ctrl Reg Blk */
250	u32 gpe0_block; /* [V1] 32-bit port address of General Purpose Event 0 Reg Blk */	250	u32 gpe0_block; /* 32-bit port address of General Purpose Event 0 Reg Blk */
251	u32 gpe1_block; /* [V1] 32-bit port address of General Purpose Event 1 Reg Blk */	251	u32 gpe1_block; /* 32-bit port address of General Purpose Event 1 Reg Blk */
252	u8 pm1_event_length; /* [V1] Byte Length of ports at pm1x_event_block */	252	u8 pm1_event_length; /* Byte Length of ports at pm1x_event_block */
253	u8 pm1_control_length; /* [V1] Byte Length of ports at pm1x_control_block */	253	u8 pm1_control_length; /* Byte Length of ports at pm1x_control_block */
254	u8 pm2_control_length; /* [V1] Byte Length of ports at pm2_control_block */	254	u8 pm2_control_length; /* Byte Length of ports at pm2_control_block */
255	u8 pm_timer_length; /* [V1] Byte Length of ports at pm_timer_block */	255	u8 pm_timer_length; /* Byte Length of ports at pm_timer_block */
256	u8 gpe0_block_length; /* [V1] Byte Length of ports at gpe0_block */	256	u8 gpe0_block_length; /* Byte Length of ports at gpe0_block */
257	u8 gpe1_block_length; /* [V1] Byte Length of ports at gpe1_block */	257	u8 gpe1_block_length; /* Byte Length of ports at gpe1_block */
258	u8 gpe1_base; /* [V1] Offset in GPE number space where GPE1 events start */	258	u8 gpe1_base; /* Offset in GPE number space where GPE1 events start */
259	u8 cst_control; /* [V1] Support for the _CST object and C-States change notification */	259	u8 cst_control; /* Support for the _CST object and C-States change notification */
260	u16 c2_latency; /* [V1] Worst case HW latency to enter/exit C2 state */	260	u16 c2_latency; /* Worst case HW latency to enter/exit C2 state */
261	u16 c3_latency; /* [V1] Worst case HW latency to enter/exit C3 state */	261	u16 c3_latency; /* Worst case HW latency to enter/exit C3 state */
262	u16 flush_size; /* [V1] Processor memory cache line width, in bytes */	262	u16 flush_size; /* Processor memory cache line width, in bytes */
263	u16 flush_stride; /* [V1] Number of flush strides that need to be read */	263	u16 flush_stride; /* Number of flush strides that need to be read */
264	u8 duty_offset; /* [V1] Processor duty cycle index in processor P_CNT reg */	264	u8 duty_offset; /* Processor duty cycle index in processor P_CNT reg */
265	u8 duty_width; /* [V1] Processor duty cycle value bit width in P_CNT register */	265	u8 duty_width; /* Processor duty cycle value bit width in P_CNT register */
266	u8 day_alarm; /* [V1] Index to day-of-month alarm in RTC CMOS RAM */	266	u8 day_alarm; /* Index to day-of-month alarm in RTC CMOS RAM */
267	u8 month_alarm; /* [V1] Index to month-of-year alarm in RTC CMOS RAM */	267	u8 month_alarm; /* Index to month-of-year alarm in RTC CMOS RAM */
268	u8 century; /* [V1] Index to century in RTC CMOS RAM */	268	u8 century; /* Index to century in RTC CMOS RAM */
269	u16 boot_flags; /* [V3] IA-PC Boot Architecture Flags (see below for individual flags) */	269	u16 boot_flags; /* IA-PC Boot Architecture Flags (see below for individual flags) */
270	u8 reserved; /* [V1] Reserved, must be zero */	270	u8 reserved; /* Reserved, must be zero */
271	u32 flags; /* [V1] Miscellaneous flag bits (see below for individual flags) */	271	u32 flags; /* Miscellaneous flag bits (see below for individual flags) */
272	/* End of Version 1 FADT fields (ACPI 1.0) */	272	struct acpi_generic_address reset_register; /* 64-bit address of the Reset register */
273		273	u8 reset_value; /* Value to write to the reset_register port to reset the system */
274	struct acpi_generic_address reset_register; /* [V3] 64-bit address of the Reset register */	274	u16 arm_boot_flags; /* ARM-Specific Boot Flags (see below for individual flags) (ACPI 5.1) */
275	u8 reset_value; /* [V3] Value to write to the reset_register port to reset the system */	275	u8 minor_revision; /* FADT Minor Revision (ACPI 5.1) */
276	u16 arm_boot_flags; /* [V5] ARM-Specific Boot Flags (see below for individual flags) (ACPI 5.1) */	276	u64 Xfacs; /* 64-bit physical address of FACS */
277	u8 minor_revision; /* [V5] FADT Minor Revision (ACPI 5.1) */	277	u64 Xdsdt; /* 64-bit physical address of DSDT */
278	u64 Xfacs; /* [V3] 64-bit physical address of FACS */	278	struct acpi_generic_address xpm1a_event_block; /* 64-bit Extended Power Mgt 1a Event Reg Blk address */
279	u64 Xdsdt; /* [V3] 64-bit physical address of DSDT */	279	struct acpi_generic_address xpm1b_event_block; /* 64-bit Extended Power Mgt 1b Event Reg Blk address */
280	struct acpi_generic_address xpm1a_event_block; /* [V3] 64-bit Extended Power Mgt 1a Event Reg Blk address */	280	struct acpi_generic_address xpm1a_control_block; /* 64-bit Extended Power Mgt 1a Control Reg Blk address */
281	struct acpi_generic_address xpm1b_event_block; /* [V3] 64-bit Extended Power Mgt 1b Event Reg Blk address */	281	struct acpi_generic_address xpm1b_control_block; /* 64-bit Extended Power Mgt 1b Control Reg Blk address */
282	struct acpi_generic_address xpm1a_control_block; /* [V3] 64-bit Extended Power Mgt 1a Control Reg Blk address */	282	struct acpi_generic_address xpm2_control_block; /* 64-bit Extended Power Mgt 2 Control Reg Blk address */
283	struct acpi_generic_address xpm1b_control_block; /* [V3] 64-bit Extended Power Mgt 1b Control Reg Blk address */	283	struct acpi_generic_address xpm_timer_block; /* 64-bit Extended Power Mgt Timer Ctrl Reg Blk address */
284	struct acpi_generic_address xpm2_control_block; /* [V3] 64-bit Extended Power Mgt 2 Control Reg Blk address */	284	struct acpi_generic_address xgpe0_block; /* 64-bit Extended General Purpose Event 0 Reg Blk address */
285	struct acpi_generic_address xpm_timer_block; /* [V3] 64-bit Extended Power Mgt Timer Ctrl Reg Blk address */	285	struct acpi_generic_address xgpe1_block; /* 64-bit Extended General Purpose Event 1 Reg Blk address */
286	struct acpi_generic_address xgpe0_block; /* [V3] 64-bit Extended General Purpose Event 0 Reg Blk address */	286	struct acpi_generic_address sleep_control; /* 64-bit Sleep Control register (ACPI 5.0) */
287	struct acpi_generic_address xgpe1_block; /* [V3] 64-bit Extended General Purpose Event 1 Reg Blk address */	287	struct acpi_generic_address sleep_status; /* 64-bit Sleep Status register (ACPI 5.0) */
288	/* End of Version 3 FADT fields (ACPI 2.0) */	288	u64 hypervisor_id; /* Hypervisor Vendor ID (ACPI 6.0) */
289
290	struct acpi_generic_address sleep_control; /* [V4] 64-bit Sleep Control register (ACPI 5.0) */
291	/* End of Version 4 FADT fields (ACPI 3.0 and ACPI 4.0) (Field was originally reserved in ACPI 3.0) */
292
293	struct acpi_generic_address sleep_status; /* [V5] 64-bit Sleep Status register (ACPI 5.0) */
294	/* End of Version 5 FADT fields (ACPI 5.0) */
295
296	u64 hypervisor_id; /* [V6] Hypervisor Vendor ID (ACPI 6.0) */
297	/* End of Version 6 FADT fields (ACPI 6.0) */
298
299	};	289	};
300		290
301	/* Masks for FADT IA-PC Boot Architecture Flags (boot_flags) [Vx]=Introduced in this FADT revision */	291	/* Masks for FADT IA-PC Boot Architecture Flags (boot_flags) [Vx]=Introduced in this FADT revision */
@@ -311,8 +301,8 @@ struct acpi_table_fadt { · 9 unmodified lines
311		301
312	/* Masks for FADT ARM Boot Architecture Flags (arm_boot_flags) ACPI 5.1 */	302	/* Masks for FADT ARM Boot Architecture Flags (arm_boot_flags) ACPI 5.1 */
313		303
314	#define ACPI_FADT_PSCI_COMPLIANT (1) /* 00: [V5] PSCI 0.2+ is implemented */	304	#define ACPI_FADT_PSCI_COMPLIANT (1) /* 00: [V5+] PSCI 0.2+ is implemented */
315	#define ACPI_FADT_PSCI_USE_HVC (1<<1) /* 01: [V5] HVC must be used instead of SMC as the PSCI conduit */	305	#define ACPI_FADT_PSCI_USE_HVC (1<<1) /* 01: [V5+] HVC must be used instead of SMC as the PSCI conduit */
316		306
317	/* Masks for FADT flags */	307	/* Masks for FADT flags */
318		308
@@ -409,34 +399,20 @@ struct acpi_table_desc { · 90 unmodified lines
409	* match the expected length. In other words, the length of the	399	* match the expected length. In other words, the length of the
410	* FADT is the bottom line as to what the version really is.	400	* FADT is the bottom line as to what the version really is.
411	*	401	*
412	* NOTE: There is no officialy released V2 of the FADT. This	402	* For reference, the values below are as follows:
413	* version was used only for prototyping and testing during the	403	* FADT V1 size: 0x074
414	* 32-bit to 64-bit transition. V3 was the first official 64-bit	404	* FADT V2 size: 0x084
415	* version of the FADT.	405	* FADT V3 size: 0x0F4
416	*	406	* FADT V4 size: 0x0F4
417	* Update this list of defines when a new version of the FADT is	407	* FADT V5 size: 0x10C
418	* added to the ACPI specification. Note that the FADT version is	408	* FADT V6 size: 0x114
419	* only incremented when new fields are appended to the existing
420	* version. Therefore, the FADT version is competely independent
421	* from the version of the ACPI specification where it is
422	* defined.
423	*
424	* For reference, the various FADT lengths are as follows:
425	* FADT V1 size: 0x074 ACPI 1.0
426	* FADT V3 size: 0x0F4 ACPI 2.0
427	* FADT V4 size: 0x100 ACPI 3.0 and ACPI 4.0
428	* FADT V5 size: 0x10C ACPI 5.0
429	* FADT V6 size: 0x114 ACPI 6.0
430	*/	409	*/
431	#define ACPI_FADT_V1_SIZE (u32) (ACPI_FADT_OFFSET (flags) + 4) /* ACPI 1.0 */	410	#define ACPI_FADT_V1_SIZE (u32) (ACPI_FADT_OFFSET (flags) + 4)
432	#define ACPI_FADT_V3_SIZE (u32) (ACPI_FADT_OFFSET (sleep_control)) /* ACPI 2.0 */	411	#define ACPI_FADT_V2_SIZE (u32) (ACPI_FADT_OFFSET (minor_revision) + 1)
433	#define ACPI_FADT_V4_SIZE (u32) (ACPI_FADT_OFFSET (sleep_status)) /* ACPI 3.0 and ACPI 4.0 */	412	#define ACPI_FADT_V3_SIZE (u32) (ACPI_FADT_OFFSET (sleep_control))
434	#define ACPI_FADT_V5_SIZE (u32) (ACPI_FADT_OFFSET (hypervisor_id)) /* ACPI 5.0 */	413	#define ACPI_FADT_V5_SIZE (u32) (ACPI_FADT_OFFSET (hypervisor_id))
435	#define ACPI_FADT_V6_SIZE (u32) (sizeof (struct acpi_table_fadt)) /* ACPI 6.0 */	414	#define ACPI_FADT_V6_SIZE (u32) (sizeof (struct acpi_table_fadt))
436
437	/* Update these when new FADT versions are added */
438		415
439	#define ACPI_FADT_MAX_VERSION 6
440	#define ACPI_FADT_CONFORMANCE "ACPI 6.1 (FADT version 6)"	416	#define ACPI_FADT_CONFORMANCE "ACPI 6.1 (FADT version 6)"
441		417
442	#endif /* __ACTBL_H__ */	418	#endif /* __ACTBL_H__ */

include/acpi/platform/aclinux.h+3−0

@@ -191,6 +191,9 @@ · 190 unmodified lines
191	#ifndef __init	191	#ifndef __init
192	#define __init	192	#define __init
193	#endif	193	#endif
		194	#ifndef __iomem
		195	#define __iomem
		196	#endif
194		197
195	/* Host-dependent types and defines for user-space ACPICA */	198	/* Host-dependent types and defines for user-space ACPICA */
196		199

include/linux/bpf_verifier.h+3−2

   * are obviously wrong for any sort of memory access.
   */
 #define BPF_REGISTER_MAX_RANGE (1024 * 1024 * 1024)
-#define BPF_REGISTER_MIN_RANGE -(1024 * 1024 * 1024)
+#define BPF_REGISTER_MIN_RANGE -1
 struct bpf_reg_state {
 	enum bpf_reg_type type;
 	 * Used to determine if any memory access using this register will
 	 * result in a bad access.
 	 */
-	u64 min_value, max_value;
+	s64 min_value;
+	u64 max_value;
 	u32 id;
 	union {
 		/* valid when type == CONST_IMM | PTR_TO_STACK | UNKNOWN_VALUE */

include/linux/huge_mm.h+1−1

@@ -22,7 +22,7 @@ extern int mincore_huge_pmd(struct vm_area_struct vma, pmd_t pmd, · 21 unmodified lines
22	unsigned char *vec);	22	unsigned char *vec);
23	extern bool move_huge_pmd(struct vm_area_struct *vma, unsigned long old_addr,	23	extern bool move_huge_pmd(struct vm_area_struct *vma, unsigned long old_addr,
24	unsigned long new_addr, unsigned long old_end,	24	unsigned long new_addr, unsigned long old_end,
25	pmd_t old_pmd, pmd_t new_pmd);	25	pmd_t old_pmd, pmd_t new_pmd, bool *need_flush);
26	extern int change_huge_pmd(struct vm_area_struct vma, pmd_t pmd,	26	extern int change_huge_pmd(struct vm_area_struct vma, pmd_t pmd,
27	unsigned long addr, pgprot_t newprot,	27	unsigned long addr, pgprot_t newprot,
28	int prot_numa);	28	int prot_numa);

include/linux/sunrpc/svc_xprt.h+1−0

@@ -25,6 +25,7 @@ struct svc_xprt_ops { · 24 unmodified lines
25	void (xpo_detach)(struct svc_xprt );	25	void (xpo_detach)(struct svc_xprt );
26	void (xpo_free)(struct svc_xprt );	26	void (xpo_free)(struct svc_xprt );
27	int (xpo_secure_port)(struct svc_rqst );	27	int (xpo_secure_port)(struct svc_rqst );
		28	void (xpo_kill_temp_xprt)(struct svc_xprt );
28	};	29	};
29		30
30	struct svc_xprt_class {	31	struct svc_xprt_class {

include/net/gro_cells.h+3−0

@@ -68,6 +68,9 @@ static inline int gro_cells_init(struct gro_cells gcells, struct net_device de · 67 unmodified lines
68	struct gro_cell *cell = per_cpu_ptr(gcells->cells, i);	68	struct gro_cell *cell = per_cpu_ptr(gcells->cells, i);
69		69
70	__skb_queue_head_init(&cell->napi_skbs);	70	__skb_queue_head_init(&cell->napi_skbs);
		71
		72	set_bit(NAPI_STATE_NO_BUSY_POLL, &cell->napi.state);
		73
71	netif_napi_add(dev, &cell->napi, gro_cell_poll, 64);	74	netif_napi_add(dev, &cell->napi, gro_cell_poll, 64);
72	napi_enable(&cell->napi);	75	napi_enable(&cell->napi);
73	}	76	}

include/net/ip_fib.h+1−0

@@ -243,6 +243,7 @@ int fib_table_dump(struct fib_table table, struct sk_buff skb, · 242 unmodified lines
243	struct netlink_callback *cb);	243	struct netlink_callback *cb);
244	int fib_table_flush(struct net net, struct fib_table table);	244	int fib_table_flush(struct net net, struct fib_table table);
245	struct fib_table fib_trie_unmerge(struct fib_table main_tb);	245	struct fib_table fib_trie_unmerge(struct fib_table main_tb);
		246	void fib_table_flush_external(struct fib_table *table);
246	void fib_free_table(struct fib_table *tb);	247	void fib_free_table(struct fib_table *tb);
247		248
248	#ifndef CONFIG_IP_MULTIPLE_TABLES	249	#ifndef CONFIG_IP_MULTIPLE_TABLES

include/net/net_namespace.h+1−1

@@ -170,7 +170,7 @@ static inline struct net *copy_net_ns(unsigned long flags, · 169 unmodified lines
170	extern struct list_head net_namespace_list;	170	extern struct list_head net_namespace_list;
171		171
172	struct net *get_net_ns_by_pid(pid_t pid);	172	struct net *get_net_ns_by_pid(pid_t pid);
173	struct net *get_net_ns_by_fd(int pid);	173	struct net *get_net_ns_by_fd(int fd);
174		174
175	#ifdef CONFIG_SYSCTL	175	#ifdef CONFIG_SYSCTL
176	void ipx_register_sysctl(void);	176	void ipx_register_sysctl(void);

include/uapi/linux/kvm.h+7−0

 	__u8  pad[16];
 };
+/* For KVM_CAP_ADJUST_CLOCK */
+/* Do not use 1, KVM_CHECK_EXTENSION returned it before we had flags.  */
+#define KVM_CLOCK_TSC_STABLE		2
 struct kvm_clock_data {
 	__u64 clock;
 	__u32 flags;
 	__u32 pad[9];
 };
+/* For KVM_CAP_SW_TLB */
 #define KVM_MMU_FSL_BOOKE_NOHV		0
 #define KVM_MMU_FSL_BOOKE_HV		1

kernel/bpf/verifier.c+47−23

 				reg->map_ptr->value_size,
 				reg->id);
 		if (reg->min_value != BPF_REGISTER_MIN_RANGE)
-			verbose(",min_value=%llu",
+			verbose(",min_value=%lld",
-				(unsigned long long)reg->min_value);
+				(long long)reg->min_value);
 		if (reg->max_value != BPF_REGISTER_MAX_RANGE)
 			verbose(",max_value=%llu",
 				(unsigned long long)reg->max_value);
 			 * index'es we need to make sure that whatever we use
 			 * will have a set floor within our range.
 			 */
-			if ((s64)reg->min_value < 0) {
+			if (reg->min_value < 0) {
 				verbose("R%d min value is negative, either use unsigned index or do a if (index >=0) check.\n",
 					regno);
 				return -EACCES;
 {
 	if (reg->max_value > BPF_REGISTER_MAX_RANGE)
 		reg->max_value = BPF_REGISTER_MAX_RANGE;
-	if ((s64)reg->min_value < BPF_REGISTER_MIN_RANGE)
+	if (reg->min_value < BPF_REGISTER_MIN_RANGE ||
+	    reg->min_value > BPF_REGISTER_MAX_RANGE)
 		reg->min_value = BPF_REGISTER_MIN_RANGE;
 }
 				    struct bpf_insn *insn)
 {
 	struct bpf_reg_state *regs = env->cur_state.regs, *dst_reg;
-	u64 min_val = BPF_REGISTER_MIN_RANGE, max_val = BPF_REGISTER_MAX_RANGE;
+	s64 min_val = BPF_REGISTER_MIN_RANGE;
+	u64 max_val = BPF_REGISTER_MAX_RANGE;
 	u8 opcode = BPF_OP(insn->code);
 	dst_reg = &regs[insn->dst_reg];
 		return;
 	}
+	/* If one of our values was at the end of our ranges then we can't just
+	 * do our normal operations to the register, we need to set the values
+	 * to the min/max since they are undefined.
+	 */
+	if (min_val == BPF_REGISTER_MIN_RANGE)
+		dst_reg->min_value = BPF_REGISTER_MIN_RANGE;
+	if (max_val == BPF_REGISTER_MAX_RANGE)
+		dst_reg->max_value = BPF_REGISTER_MAX_RANGE;
 	switch (opcode) {
 	case BPF_ADD:
-		dst_reg->min_value += min_val;
+		if (dst_reg->min_value != BPF_REGISTER_MIN_RANGE)
-		dst_reg->max_value += max_val;
+			dst_reg->min_value += min_val;
+		if (dst_reg->max_value != BPF_REGISTER_MAX_RANGE)
+			dst_reg->max_value += max_val;
 		break;
 	case BPF_SUB:
-		dst_reg->min_value -= min_val;
+		if (dst_reg->min_value != BPF_REGISTER_MIN_RANGE)
-		dst_reg->max_value -= max_val;
+			dst_reg->min_value -= min_val;
+		if (dst_reg->max_value != BPF_REGISTER_MAX_RANGE)
+			dst_reg->max_value -= max_val;
 		break;
 	case BPF_MUL:
-		dst_reg->min_value *= min_val;
+		if (dst_reg->min_value != BPF_REGISTER_MIN_RANGE)
-		dst_reg->max_value *= max_val;
+			dst_reg->min_value *= min_val;
+		if (dst_reg->max_value != BPF_REGISTER_MAX_RANGE)
+			dst_reg->max_value *= max_val;
 		break;
 	case BPF_AND:
-		/* & is special since it could end up with 0 bits set. */
+		/* Disallow AND'ing of negative numbers, ain't nobody got time
-		dst_reg->min_value &= min_val;
+		 * for that.  Otherwise the minimum is 0 and the max is the max
+		 * value we could AND against.
+		 */
+		if (min_val < 0)
+			dst_reg->min_value = BPF_REGISTER_MIN_RANGE;
+		else
+			dst_reg->min_value = 0;
 		dst_reg->max_value = max_val;
 		break;
 	case BPF_LSH:
 		 */
 		if (min_val > ilog2(BPF_REGISTER_MAX_RANGE))
 			dst_reg->min_value = BPF_REGISTER_MIN_RANGE;
-		else
+		else if (dst_reg->min_value != BPF_REGISTER_MIN_RANGE)
 			dst_reg->min_value <<= min_val;
 		if (max_val > ilog2(BPF_REGISTER_MAX_RANGE))
 			dst_reg->max_value = BPF_REGISTER_MAX_RANGE;
-		else
+		else if (dst_reg->max_value != BPF_REGISTER_MAX_RANGE)
 			dst_reg->max_value <<= max_val;
 		break;
 	case BPF_RSH:
-		dst_reg->min_value >>= min_val;
+		/* RSH by a negative number is undefined, and the BPF_RSH is an
-		dst_reg->max_value >>= max_val;
+		 * unsigned shift, so make the appropriate casts.
-		break;
-	case BPF_MOD:
-		/* % is special since it is an unsigned modulus, so the floor
-		 * will always be 0.
 		 */
-		dst_reg->min_value = 0;
+		if (min_val < 0 || dst_reg->min_value < 0)
-		dst_reg->max_value = max_val - 1;
+			dst_reg->min_value = BPF_REGISTER_MIN_RANGE;
+		else
+			dst_reg->min_value =
+				(u64)(dst_reg->min_value) >> min_val;
+		if (dst_reg->max_value != BPF_REGISTER_MAX_RANGE)
+			dst_reg->max_value >>= max_val;
 		break;
 	default:
 		reset_reg_range_values(regs, insn->dst_reg);

kernel/locking/lockdep_internals.h+17−3

 #define LOCKF_USED_IN_IRQ_READ \
 		(LOCKF_USED_IN_HARDIRQ_READ | LOCKF_USED_IN_SOFTIRQ_READ)
+/*
+ * CONFIG_PROVE_LOCKING_SMALL is defined for sparc. Sparc requires .text,
+ * .data and .bss to fit in required 32MB limit for the kernel. With
+ * PROVE_LOCKING we could go over this limit and cause system boot-up problems.
+ * So, reduce the static allocations for lockdeps related structures so that
+ * everything fits in current required size limit.
+ */
+#ifdef CONFIG_PROVE_LOCKING_SMALL
 /*
  * MAX_LOCKDEP_ENTRIES is the maximum number of lock dependencies
  * we track.
  * table (if it's not there yet), and we check it for lock order
  * conflicts and deadlocks.
  */
+#define MAX_LOCKDEP_ENTRIES	16384UL
+#define MAX_LOCKDEP_CHAINS_BITS	15
+#define MAX_STACK_TRACE_ENTRIES	262144UL
+#else
 #define MAX_LOCKDEP_ENTRIES	32768UL
 #define MAX_LOCKDEP_CHAINS_BITS	16
-#define MAX_LOCKDEP_CHAINS	(1UL << MAX_LOCKDEP_CHAINS_BITS)
-#define MAX_LOCKDEP_CHAIN_HLOCKS (MAX_LOCKDEP_CHAINS*5)
 /*
  * Stack-trace: tightly packed array of stack backtrace
  * addresses. Protected by the hash_lock.
  */
 #define MAX_STACK_TRACE_ENTRIES	524288UL
+#endif
+#define MAX_LOCKDEP_CHAINS	(1UL << MAX_LOCKDEP_CHAINS_BITS)
+#define MAX_LOCKDEP_CHAIN_HLOCKS (MAX_LOCKDEP_CHAINS*5)
 extern struct list_head all_lock_classes;
 extern struct lock_chain lock_chains[];

kernel/trace/ftrace.c+23−1

 	/* Update rec->flags */
 	do_for_each_ftrace_rec(pg, rec) {
+		if (rec->flags & FTRACE_FL_DISABLED)
+			continue;
 		/* We need to update only differences of filter_hash */
 		in_old = !!ftrace_lookup_ip(old_hash, rec->ip);
 		in_new = !!ftrace_lookup_ip(new_hash, rec->ip);
 	/* Roll back what we did above */
 	do_for_each_ftrace_rec(pg, rec) {
+		if (rec->flags & FTRACE_FL_DISABLED)
+			continue;
 		if (rec == end)
 			goto err_out;
 		return;
 	do_for_each_ftrace_rec(pg, rec) {
+		if (rec->flags & FTRACE_FL_DISABLED)
+			continue;
 		failed = __ftrace_replace_code(rec, enable);
 		if (failed) {
 			ftrace_bug(failed, rec);
 		struct dyn_ftrace *rec;
 		do_for_each_ftrace_rec(pg, rec) {
-			if (FTRACE_WARN_ON_ONCE(rec->flags))
+			if (FTRACE_WARN_ON_ONCE(rec->flags & ~FTRACE_FL_DISABLED))
 				pr_warn("  %pS flags:%lx\n",
 					(void *)rec->ip, rec->flags);
 		} while_for_each_ftrace_rec();
 		goto out_unlock;
 	do_for_each_ftrace_rec(pg, rec) {
+		if (rec->flags & FTRACE_FL_DISABLED)
+			continue;
 		if (ftrace_match_record(rec, &func_g, mod_match, exclude_mod)) {
 			ret = enter_record(hash, rec, clear_filter);
 			if (ret < 0) {
 	do_for_each_ftrace_rec(pg, rec) {
+		if (rec->flags & FTRACE_FL_DISABLED)
+			continue;
 		if (!ftrace_match_record(rec, &func_g, NULL, 0))
 			continue;
 	do_for_each_ftrace_rec(pg, rec) {
+		if (rec->flags & FTRACE_FL_DISABLED)
+			continue;
 		if (ftrace_match_record(rec, &func_g, NULL, 0)) {
 			/* if it is in the array */
 			exists = false;

lib/Kconfig.debug+3−0

@@ -1085,6 +1085,9 @@ config PROVE_LOCKING · 1084 unmodified lines
1085		1085
1086	For more details, see Documentation/locking/lockdep-design.txt.	1086	For more details, see Documentation/locking/lockdep-design.txt.
1087		1087
		1088	config PROVE_LOCKING_SMALL
		1089	bool
		1090
1088	config LOCKDEP	1091	config LOCKDEP
1089	bool	1092	bool
1090	depends on DEBUG_KERNEL && TRACE_IRQFLAGS_SUPPORT && STACKTRACE_SUPPORT && LOCKDEP_SUPPORT	1093	depends on DEBUG_KERNEL && TRACE_IRQFLAGS_SUPPORT && STACKTRACE_SUPPORT && LOCKDEP_SUPPORT

lib/iov_iter.c+3−1

 	struct pipe_inode_info *pipe = i->pipe;
 	struct pipe_buffer *buf;
 	int idx = i->idx;
-	size_t off = i->iov_offset;
+	size_t off = i->iov_offset, orig_sz;
 	if (unlikely(i->count < size))
 		size = i->count;
+	orig_sz = size;
 	if (size) {
 		if (off) /* make it relative to the beginning of buffer */
 			pipe->nrbufs--;
 		}
 	}
+	i->count -= orig_sz;
 }
 void iov_iter_advance(struct iov_iter *i, size_t size)

mm/huge_memory.c+8−1

 bool move_huge_pmd(struct vm_area_struct *vma, unsigned long old_addr,
 		  unsigned long new_addr, unsigned long old_end,
-		  pmd_t *old_pmd, pmd_t *new_pmd)
+		  pmd_t *old_pmd, pmd_t *new_pmd, bool *need_flush)
 {
 	spinlock_t *old_ptl, *new_ptl;
 	pmd_t pmd;
 	struct mm_struct *mm = vma->vm_mm;
+	bool force_flush = false;
 	if ((old_addr & ~HPAGE_PMD_MASK) ||
 	    (new_addr & ~HPAGE_PMD_MASK) ||
 		new_ptl = pmd_lockptr(mm, new_pmd);
 		if (new_ptl != old_ptl)
 			spin_lock_nested(new_ptl, SINGLE_DEPTH_NESTING);
+		if (pmd_present(*old_pmd) && pmd_dirty(*old_pmd))
+			force_flush = true;
 		pmd = pmdp_huge_get_and_clear(mm, old_addr, old_pmd);
 		VM_BUG_ON(!pmd_none(*new_pmd));
 		set_pmd_at(mm, new_addr, new_pmd, pmd_mksoft_dirty(pmd));
 		if (new_ptl != old_ptl)
 			spin_unlock(new_ptl);
+		if (force_flush)
+			flush_tlb_range(vma, old_addr, old_addr + PMD_SIZE);
+		else
+			*need_flush = true;
 		spin_unlock(old_ptl);
 		return true;
 	}

mm/mremap.c+21−9

 static void move_ptes(struct vm_area_struct *vma, pmd_t *old_pmd,
 		unsigned long old_addr, unsigned long old_end,
 		struct vm_area_struct *new_vma, pmd_t *new_pmd,
-		unsigned long new_addr, bool need_rmap_locks)
+		unsigned long new_addr, bool need_rmap_locks, bool *need_flush)
 {
 	struct mm_struct *mm = vma->vm_mm;
 	pte_t *old_pte, *new_pte, pte;
 	spinlock_t *old_ptl, *new_ptl;
+	bool force_flush = false;
+	unsigned long len = old_end - old_addr;
 	/*
 	 * When need_rmap_locks is true, we take the i_mmap_rwsem and anon_vma
 				   new_pte++, new_addr += PAGE_SIZE) {
 		if (pte_none(*old_pte))
 			continue;
+		/*
+		 * We are remapping a dirty PTE, make sure to
+		 * flush TLB before we drop the PTL for the
+		 * old PTE or we may race with page_mkclean().
+		 */
+		if (pte_present(*old_pte) && pte_dirty(*old_pte))
+			force_flush = true;
 		pte = ptep_get_and_clear(mm, old_addr, old_pte);
 		pte = move_pte(pte, new_vma->vm_page_prot, old_addr, new_addr);
 		pte = move_soft_dirty_pte(pte);
 	if (new_ptl != old_ptl)
 		spin_unlock(new_ptl);
 	pte_unmap(new_pte - 1);
+	if (force_flush)
+		flush_tlb_range(vma, old_end - len, old_end);
+	else
+		*need_flush = true;
 	pte_unmap_unlock(old_pte - 1, old_ptl);
 	if (need_rmap_locks)
 		drop_rmap_locks(vma);
 				if (need_rmap_locks)
 					take_rmap_locks(vma);
 				moved = move_huge_pmd(vma, old_addr, new_addr,
-						    old_end, old_pmd, new_pmd);
+						    old_end, old_pmd, new_pmd,
+						    &need_flush);
 				if (need_rmap_locks)
 					drop_rmap_locks(vma);
-				if (moved) {
+				if (moved)
-					need_flush = true;
 					continue;
-				}
 			}
 			split_huge_pmd(vma, old_pmd, old_addr);
 			if (pmd_trans_unstable(old_pmd))
 			extent = next - new_addr;
 		if (extent > LATENCY_LIMIT)
 			extent = LATENCY_LIMIT;
-		move_ptes(vma, old_pmd, old_addr, old_addr + extent,
+		move_ptes(vma, old_pmd, old_addr, old_addr + extent, new_vma,
-			  new_vma, new_pmd, new_addr, need_rmap_locks);
+			  new_pmd, new_addr, need_rmap_locks, &need_flush);
-		need_flush = true;
 	}
-	if (likely(need_flush))
+	if (need_flush)
 		flush_tlb_range(vma, old_end-len, old_addr);
 	mmu_notifier_invalidate_range_end(vma->vm_mm, mmun_start, mmun_end);

net/batman-adv/hard-interface.c+1−0

@@ -851,6 +851,7 @@ void batadv_hardif_disable_interface(struct batadv_hard_iface *hard_iface, · 850 unmodified lines
851	batadv_softif_destroy_sysfs(hard_iface->soft_iface);	851	batadv_softif_destroy_sysfs(hard_iface->soft_iface);
852	}	852	}
853		853
		854	hard_iface->soft_iface = NULL;
854	batadv_hardif_put(hard_iface);	855	batadv_hardif_put(hard_iface);
855		856
856	out:	857	out:

net/batman-adv/tp_meter.c+1−0

@@ -834,6 +834,7 @@ static int batadv_tp_send(void *arg) · 833 unmodified lines
834	primary_if = batadv_primary_if_get_selected(bat_priv);	834	primary_if = batadv_primary_if_get_selected(bat_priv);
835	if (unlikely(!primary_if)) {	835	if (unlikely(!primary_if)) {
836	err = BATADV_TP_REASON_DST_UNREACHABLE;	836	err = BATADV_TP_REASON_DST_UNREACHABLE;
		837	tp_vars->reason = err;
837	goto out;	838	goto out;
838	}	839	}
839		840

net/core/net_namespace.c+2−0

@@ -218,6 +218,8 @@ int peernet2id_alloc(struct net net, struct net peer) · 217 unmodified lines
218	bool alloc;	218	bool alloc;
219	int id;	219	int id;
220		220
		221	if (atomic_read(&net->count) == 0)
		222	return NETNSA_NSID_NOT_ASSIGNED;
221	spin_lock_irqsave(&net->nsid_lock, flags);	223	spin_lock_irqsave(&net->nsid_lock, flags);
222	alloc = atomic_read(&peer->count) == 0 ? false : true;	224	alloc = atomic_read(&peer->count) == 0 ? false : true;
223	id = __peernet2id_alloc(net, peer, &alloc);	225	id = __peernet2id_alloc(net, peer, &alloc);

net/core/rtnetlink.c+14−8

 	if (dev->dev.parent && dev_is_pci(dev->dev.parent) &&
 	    (ext_filter_mask & RTEXT_FILTER_VF)) {
 		int num_vfs = dev_num_vf(dev->dev.parent);
-		size_t size = nla_total_size(sizeof(struct nlattr));
+		size_t size = nla_total_size(0);
-		size += nla_total_size(num_vfs * sizeof(struct nlattr));
 		size += num_vfs *
-			(nla_total_size(sizeof(struct ifla_vf_mac)) +
+			(nla_total_size(0) +
-			 nla_total_size(MAX_VLAN_LIST_LEN *
+			 nla_total_size(sizeof(struct ifla_vf_mac)) +
-					sizeof(struct nlattr)) +
+			 nla_total_size(sizeof(struct ifla_vf_vlan)) +
+			 nla_total_size(0) + /* nest IFLA_VF_VLAN_LIST */
 			 nla_total_size(MAX_VLAN_LIST_LEN *
 					sizeof(struct ifla_vf_vlan_info)) +
 			 nla_total_size(sizeof(struct ifla_vf_spoofchk)) +
+			 nla_total_size(sizeof(struct ifla_vf_tx_rate)) +
 			 nla_total_size(sizeof(struct ifla_vf_rate)) +
 			 nla_total_size(sizeof(struct ifla_vf_link_state)) +
 			 nla_total_size(sizeof(struct ifla_vf_rss_query_en)) +
+			 nla_total_size(0) + /* nest IFLA_VF_STATS */
 			 /* IFLA_VF_STATS_RX_PACKETS */
 			 nla_total_size_64bit(sizeof(__u64)) +
 			 /* IFLA_VF_STATS_TX_PACKETS */
 static size_t rtnl_xdp_size(const struct net_device *dev)
 {
-	size_t xdp_size = nla_total_size(1);	/* XDP_ATTACHED */
+	size_t xdp_size = nla_total_size(0) +	/* nest IFLA_XDP */
+			  nla_total_size(1);	/* XDP_ATTACHED */
 	if (!dev->netdev_ops->ndo_xdp)
 		return 0;
 		head = &net->dev_index_head[h];
 		hlist_for_each_entry(dev, head, index_hlist) {
 			if (link_dump_filtered(dev, master_idx, kind_ops))
-				continue;
+				goto cont;
 			if (idx < s_idx)
 				goto cont;
 			err = rtnl_fill_ifinfo(skb, dev, RTM_NEWLINK,
 static inline size_t rtnl_fdb_nlmsg_size(void)
 {
-	return NLMSG_ALIGN(sizeof(struct ndmsg)) + nla_total_size(ETH_ALEN);
+	return NLMSG_ALIGN(sizeof(struct ndmsg)) +
+	       nla_total_size(ETH_ALEN) +	/* NDA_LLADDR */
+	       nla_total_size(sizeof(u16)) +	/* NDA_VLAN */
+	       0;
 }
 static void rtnl_fdb_notify(struct net_device *dev, u8 *addr, u16 vid, int type,

net/ipv4/fib_frontend.c+15−5

@@ -151,7 +151,7 @@ static void fib_replace_table(struct net net, struct fib_table old, · 150 unmodified lines
151		151
152	int fib_unmerge(struct net *net)	152	int fib_unmerge(struct net *net)
153	{	153	{
154	struct fib_table old, new;	154	struct fib_table old, new, *main_table;
155		155
156	/* attempt to fetch local table if it has been allocated */	156	/* attempt to fetch local table if it has been allocated */
157	old = fib_get_table(net, RT_TABLE_LOCAL);	157	old = fib_get_table(net, RT_TABLE_LOCAL);
@@ -162,11 +162,21 @@ int fib_unmerge(struct net *net) · 4 unmodified lines
162	if (!new)	162	if (!new)
163	return -ENOMEM;	163	return -ENOMEM;
164		164
		165	/* table is already unmerged */
		166	if (new == old)
		167	return 0;
		168
165	/* replace merged table with clean table */	169	/* replace merged table with clean table */
166	if (new != old) {	170	fib_replace_table(net, old, new);
167	fib_replace_table(net, old, new);	171	fib_free_table(old);
168	fib_free_table(old);	172
169	}	173	/* attempt to fetch main table if it has been allocated */
		174	main_table = fib_get_table(net, RT_TABLE_MAIN);
		175	if (!main_table)
		176	return 0;
		177
		178	/* flush local entries from main table */
		179	fib_table_flush_external(main_table);
170		180
171	return 0;	181	return 0;
172	}	182	}

net/ipv4/fib_trie.c+68−1

@@ -1743,8 +1743,10 @@ struct fib_table fib_trie_unmerge(struct fib_table oldtb) · 1742 unmodified lines
1743	local_l = fib_find_node(lt, &local_tp, l->key);	1743	local_l = fib_find_node(lt, &local_tp, l->key);
1744		1744
1745	if (fib_insert_alias(lt, local_tp, local_l, new_fa,	1745	if (fib_insert_alias(lt, local_tp, local_l, new_fa,
1746	NULL, l->key))	1746	NULL, l->key)) {
		1747	kmem_cache_free(fn_alias_kmem, new_fa);
1747	goto out;	1748	goto out;
		1749	}
1748	}	1750	}
1749		1751
1750	/* stop loop if key wrapped back to 0 */	1752	/* stop loop if key wrapped back to 0 */
@@ -1760,6 +1762,71 @@ out: · 9 unmodified lines
1760	return NULL;	1762	return NULL;
1761	}	1763	}
1762		1764
		1765	/* Caller must hold RTNL */
		1766	void fib_table_flush_external(struct fib_table *tb)
		1767	{
		1768	struct trie t = (struct trie )tb->tb_data;
		1769	struct key_vector *pn = t->kv;
		1770	unsigned long cindex = 1;
		1771	struct hlist_node *tmp;
		1772	struct fib_alias *fa;
		1773
		1774	/* walk trie in reverse order */
		1775	for (;;) {
		1776	unsigned char slen = 0;
		1777	struct key_vector *n;
		1778
		1779	if (!(cindex--)) {
		1780	t_key pkey = pn->key;
		1781
		1782	/* cannot resize the trie vector */
		1783	if (IS_TRIE(pn))
		1784	break;
		1785
		1786	/* resize completed node */
		1787	pn = resize(t, pn);
		1788	cindex = get_index(pkey, pn);
		1789
		1790	continue;
		1791	}
		1792
		1793	/* grab the next available node */
		1794	n = get_child(pn, cindex);
		1795	if (!n)
		1796	continue;
		1797
		1798	if (IS_TNODE(n)) {
		1799	/* record pn and cindex for leaf walking */
		1800	pn = n;
		1801	cindex = 1ul << n->bits;
		1802
		1803	continue;
		1804	}
		1805
		1806	hlist_for_each_entry_safe(fa, tmp, &n->leaf, fa_list) {
		1807	/* if alias was cloned to local then we just
		1808	* need to remove the local copy from main
		1809	*/
		1810	if (tb->tb_id != fa->tb_id) {
		1811	hlist_del_rcu(&fa->fa_list);
		1812	alias_free_mem_rcu(fa);
		1813	continue;
		1814	}
		1815
		1816	/* record local slen */
		1817	slen = fa->fa_slen;
		1818	}
		1819
		1820	/* update leaf slen */
		1821	n->slen = slen;
		1822
		1823	if (hlist_empty(&n->leaf)) {
		1824	put_child_root(pn, n->key, NULL);
		1825	node_free(n);
		1826	}
		1827	}
		1828	}
		1829
1763	/* Caller must hold RTNL. */	1830	/* Caller must hold RTNL. */
1764	int fib_table_flush(struct net net, struct fib_table tb)	1831	int fib_table_flush(struct net net, struct fib_table tb)
1765	{	1832	{

net/ipv4/igmp.c+36−14

 }
 static void igmpv3_add_delrec(struct in_device *in_dev, struct ip_mc_list *im);
-static void igmpv3_del_delrec(struct in_device *in_dev, __be32 multiaddr);
+static void igmpv3_del_delrec(struct in_device *in_dev, struct ip_mc_list *im);
 static void igmpv3_clear_delrec(struct in_device *in_dev);
 static int sf_setstate(struct ip_mc_list *pmc);
 static void sf_markstate(struct ip_mc_list *pmc);
 	spin_unlock_bh(&in_dev->mc_tomb_lock);
 }
-static void igmpv3_del_delrec(struct in_device *in_dev, __be32 multiaddr)
+/*
+ * restore ip_mc_list deleted records
+ */
+static void igmpv3_del_delrec(struct in_device *in_dev, struct ip_mc_list *im)
 {
 	struct ip_mc_list *pmc, *pmc_prev;
-	struct ip_sf_list *psf, *psf_next;
+	struct ip_sf_list *psf;
+	struct net *net = dev_net(in_dev->dev);
+	__be32 multiaddr = im->multiaddr;
 	spin_lock_bh(&in_dev->mc_tomb_lock);
 	pmc_prev = NULL;
 			in_dev->mc_tomb = pmc->next;
 	}
 	spin_unlock_bh(&in_dev->mc_tomb_lock);
+	spin_lock_bh(&im->lock);
 	if (pmc) {
-		for (psf = pmc->tomb; psf; psf = psf_next) {
+		im->interface = pmc->interface;
-			psf_next = psf->sf_next;
+		im->crcount = in_dev->mr_qrv ?: net->ipv4.sysctl_igmp_qrv;
-			kfree(psf);
+		im->sfmode = pmc->sfmode;
+		if (pmc->sfmode == MCAST_INCLUDE) {
+			im->tomb = pmc->tomb;
+			im->sources = pmc->sources;
+			for (psf = im->sources; psf; psf = psf->sf_next)
+				psf->sf_crcount = im->crcount;
 		}
 		in_dev_put(pmc->interface);
-		kfree(pmc);
 	}
+	spin_unlock_bh(&im->lock);
 }
+/*
+ * flush ip_mc_list deleted records
+ */
 static void igmpv3_clear_delrec(struct in_device *in_dev)
 {
 	struct ip_mc_list *pmc, *nextpmc;
 	ip_mc_hash_add(in_dev, im);
 #ifdef CONFIG_IP_MULTICAST
-	igmpv3_del_delrec(in_dev, im->multiaddr);
+	igmpv3_del_delrec(in_dev, im);
 #endif
 	igmp_group_added(im);
 	if (!in_dev->dead)
 	ASSERT_RTNL();
-	for_each_pmc_rtnl(in_dev, pmc)
+	for_each_pmc_rtnl(in_dev, pmc) {
+#ifdef CONFIG_IP_MULTICAST
+		igmpv3_del_delrec(in_dev, pmc);
+#endif
 		igmp_group_added(pmc);
+	}
 }
 /* Device going down */
 	in_dev->mr_gq_running = 0;
 	if (del_timer(&in_dev->mr_gq_timer))
 		__in_dev_put(in_dev);
-	igmpv3_clear_delrec(in_dev);
 #endif
 	ip_mc_dec_group(in_dev, IGMP_ALL_HOSTS);
 #endif
 	ip_mc_inc_group(in_dev, IGMP_ALL_HOSTS);
-	for_each_pmc_rtnl(in_dev, pmc)
+	for_each_pmc_rtnl(in_dev, pmc) {
+#ifdef CONFIG_IP_MULTICAST
+		igmpv3_del_delrec(in_dev, pmc);
+#endif
 		igmp_group_added(pmc);
+	}
 }
 /*
 	/* Deactivate timers */
 	ip_mc_down(in_dev);
+#ifdef CONFIG_IP_MULTICAST
+	igmpv3_clear_delrec(in_dev);
+#endif
 	while ((i = rtnl_dereference(in_dev->mc_list)) != NULL) {
 		in_dev->mc_list = i->next_rcu;
 		in_dev->mc_count--;
-		/* We've dropped the groups in ip_mc_down already */
-		ip_mc_clear_src(i);
 		ip_ma_put(i);
 	}
 }

net/ipv4/tcp_cong.c+3−1

 	icsk->icsk_ca_ops = ca;
 	icsk->icsk_ca_setsockopt = 1;
-	if (sk->sk_state != TCP_CLOSE)
+	if (sk->sk_state != TCP_CLOSE) {
+		memset(icsk->icsk_ca_priv, 0, sizeof(icsk->icsk_ca_priv));
 		tcp_init_congestion_control(sk);
+	}
 }
 /* Manage refcounts on socket close. */

net/ipv4/udp.c+3−3

@@ -1743,10 +1743,10 @@ static int __udp4_lib_mcast_deliver(struct net net, struct sk_buff skb, · 1742 unmodified lines
1743		1743
1744	if (use_hash2) {	1744	if (use_hash2) {
1745	hash2_any = udp4_portaddr_hash(net, htonl(INADDR_ANY), hnum) &	1745	hash2_any = udp4_portaddr_hash(net, htonl(INADDR_ANY), hnum) &
1746	udp_table.mask;	1746	udptable->mask;
1747	hash2 = udp4_portaddr_hash(net, daddr, hnum) & udp_table.mask;	1747	hash2 = udp4_portaddr_hash(net, daddr, hnum) & udptable->mask;
1748	start_lookup:	1748	start_lookup:
1749	hslot = &udp_table.hash2[hash2];	1749	hslot = &udptable->hash2[hash2];
1750	offset = offsetof(typeof(*sk), __sk_common.skc_portaddr_node);	1750	offset = offsetof(typeof(*sk), __sk_common.skc_portaddr_node);
1751	}	1751	}
1752		1752

net/ipv6/ip6_tunnel.c+11−2

 	int mtu;
 	unsigned int psh_hlen = sizeof(struct ipv6hdr) + t->encap_hlen;
 	unsigned int max_headroom = psh_hlen;
+	bool use_cache = false;
 	u8 hop_limit;
 	int err = -1;
 		memcpy(&fl6->daddr, addr6, sizeof(fl6->daddr));
 		neigh_release(neigh);
-	} else if (!fl6->flowi6_mark)
+	} else if (!(t->parms.flags &
+		     (IP6_TNL_F_USE_ORIG_TCLASS | IP6_TNL_F_USE_ORIG_FWMARK))) {
+		/* enable the cache only only if the routing decision does
+		 * not depend on the current inner header value
+		 */
+		use_cache = true;
+	}
+	if (use_cache)
 		dst = dst_cache_get(&t->dst_cache);
 	if (!ip6_tnl_xmit_ctl(t, &fl6->saddr, &fl6->daddr))
 		if (t->encap.type != TUNNEL_ENCAP_NONE)
 			goto tx_err_dst_release;
 	} else {
-		if (!fl6->flowi6_mark && ndst)
+		if (use_cache && ndst)
 			dst_cache_set_ip6(&t->dst_cache, ndst, &fl6->saddr);
 	}
 	skb_dst_set(skb, dst);

net/ipv6/udp.c+3−3

@@ -691,10 +691,10 @@ static int __udp6_lib_mcast_deliver(struct net net, struct sk_buff skb, · 690 unmodified lines
691		691
692	if (use_hash2) {	692	if (use_hash2) {
693	hash2_any = udp6_portaddr_hash(net, &in6addr_any, hnum) &	693	hash2_any = udp6_portaddr_hash(net, &in6addr_any, hnum) &
694	udp_table.mask;	694	udptable->mask;
695	hash2 = udp6_portaddr_hash(net, daddr, hnum) & udp_table.mask;	695	hash2 = udp6_portaddr_hash(net, daddr, hnum) & udptable->mask;
696	start_lookup:	696	start_lookup:
697	hslot = &udp_table.hash2[hash2];	697	hslot = &udptable->hash2[hash2];
698	offset = offsetof(typeof(*sk), __sk_common.skc_portaddr_node);	698	offset = offsetof(typeof(*sk), __sk_common.skc_portaddr_node);
699	}	699	}
700		700

net/l2tp/l2tp_eth.c+1−1

@@ -97,7 +97,7 @@ static int l2tp_eth_dev_xmit(struct sk_buff skb, struct net_device dev) · 96 unmodified lines
97	unsigned int len = skb->len;	97	unsigned int len = skb->len;
98	int ret = l2tp_xmit_skb(session, skb, session->hdr_len);	98	int ret = l2tp_xmit_skb(session, skb, session->hdr_len);
99		99
100	if (likely(ret == NET_XMIT_SUCCESS)) {	100	if (likely(ret == NET_XMIT_SUCCESS \|\| ret == NET_XMIT_CN)) {
101	atomic_long_add(len, &priv->tx_bytes);	101	atomic_long_add(len, &priv->tx_bytes);
102	atomic_long_inc(&priv->tx_packets);	102	atomic_long_inc(&priv->tx_packets);
103	} else {	103	} else {

net/l2tp/l2tp_ip.c+3−2

 	int ret;
 	int chk_addr_ret;
-	if (!sock_flag(sk, SOCK_ZAPPED))
-		return -EINVAL;
 	if (addr_len < sizeof(struct sockaddr_l2tpip))
 		return -EINVAL;
 	if (addr->l2tp_family != AF_INET)
 	read_unlock_bh(&l2tp_ip_lock);
 	lock_sock(sk);
+	if (!sock_flag(sk, SOCK_ZAPPED))
+		goto out;
 	if (sk->sk_state != TCP_CLOSE || addr_len < sizeof(struct sockaddr_l2tpip))
 		goto out;

net/l2tp/l2tp_ip6.c+3−2

 	int addr_type;
 	int err;
-	if (!sock_flag(sk, SOCK_ZAPPED))
-		return -EINVAL;
 	if (addr->l2tp_family != AF_INET6)
 		return -EINVAL;
 	if (addr_len < sizeof(*addr))
 	lock_sock(sk);
 	err = -EINVAL;
+	if (!sock_flag(sk, SOCK_ZAPPED))
+		goto out_unlock;
 	if (sk->sk_state != TCP_CLOSE)
 		goto out_unlock;

net/mac80211/sta_info.c+1−1

@@ -688,7 +688,7 @@ static void __sta_info_recalc_tim(struct sta_info *sta, bool ignore_pending) · 687 unmodified lines
688	}	688	}
689		689
690	/* No need to do anything if the driver does all */	690	/* No need to do anything if the driver does all */
691	if (!local->ops->set_tim)	691	if (ieee80211_hw_check(&local->hw, AP_LINK_PS))
692	return;	692	return;
693		693
694	if (sta->dead)	694	if (sta->dead)

net/mac80211/tx.c+10−4

 				struct sta_info *sta,
 				struct sk_buff *skb)
 {
-	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
 	struct fq *fq = &local->fq;
 	struct ieee80211_vif *vif;
 	struct txq_info *txqi;
 	if (!txqi)
 		return false;
-	info->control.vif = vif;
 	spin_lock_bh(&fq->lock);
 	ieee80211_txq_enqueue(local, txqi, skb);
 	spin_unlock_bh(&fq->lock);
 	if (hdr->frame_control & cpu_to_le16(IEEE80211_STYPE_QOS_DATA)) {
 		tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK;
-		*ieee80211_get_qos_ctl(hdr) = tid;
 		hdr->seq_ctrl = ieee80211_tx_next_seq(sta, tid);
 	} else {
 		info->flags |= IEEE80211_TX_CTL_ASSIGN_SEQ;
 		      (tid_tx ? IEEE80211_TX_CTL_AMPDU : 0);
 	info->control.flags = IEEE80211_TX_CTRL_FAST_XMIT;
+	if (hdr->frame_control & cpu_to_le16(IEEE80211_STYPE_QOS_DATA)) {
+		tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK;
+		*ieee80211_get_qos_ctl(hdr) = tid;
+	}
 	__skb_queue_head_init(&tx.skbs);
 	tx.flags = IEEE80211_TX_UNICAST;
 		goto begin;
 	}
+	if (test_bit(IEEE80211_TXQ_AMPDU, &txqi->flags))
+		info->flags |= IEEE80211_TX_CTL_AMPDU;
+	else
+		info->flags &= ~IEEE80211_TX_CTL_AMPDU;
 	if (info->control.flags & IEEE80211_TX_CTRL_FAST_XMIT) {
 		struct sta_info *sta = container_of(txq->sta, struct sta_info,
 						    sta);

net/mac80211/vht.c+16−0

@@ -270,6 +270,22 @@ ieee80211_vht_cap_ie_to_sta_vht_cap(struct ieee80211_sub_if_data *sdata, · 269 unmodified lines
270	vht_cap->vht_mcs.tx_mcs_map \|= cpu_to_le16(peer_tx << i * 2);	270	vht_cap->vht_mcs.tx_mcs_map \|= cpu_to_le16(peer_tx << i * 2);
271	}	271	}
272		272
		273	/*
		274	* This is a workaround for VHT-enabled STAs which break the spec
		275	* and have the VHT-MCS Rx map filled in with value 3 for all eight
		276	* spacial streams, an example is AR9462.
		277	*
		278	* As per spec, in section 22.1.1 Introduction to the VHT PHY
		279	* A VHT STA shall support at least single spactial stream VHT-MCSs
		280	* 0 to 7 (transmit and receive) in all supported channel widths.
		281	*/
		282	if (vht_cap->vht_mcs.rx_mcs_map == cpu_to_le16(0xFFFF)) {
		283	vht_cap->vht_supported = false;
		284	sdata_info(sdata, "Ignoring VHT IE from %pM due to invalid rx_mcs_map\n",
		285	sta->addr);
		286	return;
		287	}
		288
273	/* finally set up the bandwidth */	289	/* finally set up the bandwidth */
274	switch (vht_cap->cap & IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_MASK) {	290	switch (vht_cap->cap & IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_MASK) {
275	case IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ:	291	case IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ:

net/sched/cls_api.c+3−2

 	for (it_chain = chain; (tp = rtnl_dereference(*it_chain)) != NULL;
 	     it_chain = &tp->next)
-		tfilter_notify(net, oskb, n, tp, 0, event, false);
+		tfilter_notify(net, oskb, n, tp, n->nlmsg_flags, event, false);
 }
 /* Select new prio value from the range, managed by kernel. */
 	if (!skb)
 		return -ENOBUFS;
-	if (tcf_fill_node(net, skb, tp, fh, portid, n->nlmsg_seq, 0, event) <= 0) {
+	if (tcf_fill_node(net, skb, tp, fh, portid, n->nlmsg_seq,
+			  n->nlmsg_flags, event) <= 0) {
 		kfree_skb(skb);
 		return -EINVAL;
 	}

net/socket.c+15−0

@@ -341,8 +341,23 @@ static const struct xattr_handler sockfs_xattr_handler = { · 340 unmodified lines
341	.get = sockfs_xattr_get,	341	.get = sockfs_xattr_get,
342	};	342	};
343		343
		344	static int sockfs_security_xattr_set(const struct xattr_handler *handler,
		345	struct dentry dentry, struct inode inode,
		346	const char suffix, const void value,
		347	size_t size, int flags)
		348	{
		349	/* Handled by LSM. */
		350	return -EAGAIN;
		351	}
		352
		353	static const struct xattr_handler sockfs_security_xattr_handler = {
		354	.prefix = XATTR_SECURITY_PREFIX,
		355	.set = sockfs_security_xattr_set,
		356	};
		357
344	static const struct xattr_handler *sockfs_xattr_handlers[] = {	358	static const struct xattr_handler *sockfs_xattr_handlers[] = {
345	&sockfs_xattr_handler,	359	&sockfs_xattr_handler,
		360	&sockfs_security_xattr_handler,
346	NULL	361	NULL
347	};	362	};
348		363

net/sunrpc/svc_xprt.c+1−10

 void svc_age_temp_xprts_now(struct svc_serv *serv, struct sockaddr *server_addr)
 {
 	struct svc_xprt *xprt;
-	struct svc_sock *svsk;
-	struct socket *sock;
 	struct list_head *le, *next;
 	LIST_HEAD(to_be_closed);
-	struct linger no_linger = {
-		.l_onoff = 1,
-		.l_linger = 0,
-	};
 	spin_lock_bh(&serv->sv_lock);
 	list_for_each_safe(le, next, &serv->sv_tempsocks) {
 		list_del_init(le);
 		xprt = list_entry(le, struct svc_xprt, xpt_list);
 		dprintk("svc_age_temp_xprts_now: closing %p\n", xprt);
-		svsk = container_of(xprt, struct svc_sock, sk_xprt);
+		xprt->xpt_ops->xpo_kill_temp_xprt(xprt);
-		sock = svsk->sk_sock;
-		kernel_setsockopt(sock, SOL_SOCKET, SO_LINGER,
-				  (char *)&no_linger, sizeof(no_linger));
 		svc_close_xprt(xprt);
 	}
 }

net/sunrpc/svcsock.c+21−0

 	return !test_bit(SOCK_NOSPACE, &svsk->sk_sock->flags);
 }
+static void svc_tcp_kill_temp_xprt(struct svc_xprt *xprt)
+{
+	struct svc_sock *svsk;
+	struct socket *sock;
+	struct linger no_linger = {
+		.l_onoff = 1,
+		.l_linger = 0,
+	};
+	svsk = container_of(xprt, struct svc_sock, sk_xprt);
+	sock = svsk->sk_sock;
+	kernel_setsockopt(sock, SOL_SOCKET, SO_LINGER,
+			  (char *)&no_linger, sizeof(no_linger));
+}
 /*
  * See net/ipv6/ip_sockglue.c : ip_cmsg_recv_pktinfo
  */
 	return NULL;
 }
+static void svc_udp_kill_temp_xprt(struct svc_xprt *xprt)
+{
+}
 static struct svc_xprt *svc_udp_create(struct svc_serv *serv,
 				       struct net *net,
 				       struct sockaddr *sa, int salen,
 	.xpo_has_wspace = svc_udp_has_wspace,
 	.xpo_accept = svc_udp_accept,
 	.xpo_secure_port = svc_sock_secure_port,
+	.xpo_kill_temp_xprt = svc_udp_kill_temp_xprt,
 };
 static struct svc_xprt_class svc_udp_class = {
 	.xpo_has_wspace = svc_tcp_has_wspace,
 	.xpo_accept = svc_tcp_accept,
 	.xpo_secure_port = svc_sock_secure_port,
+	.xpo_kill_temp_xprt = svc_tcp_kill_temp_xprt,
 };
 static struct svc_xprt_class svc_tcp_class = {

net/sunrpc/xprtrdma/svc_rdma_transport.c+6−0

 static void svc_rdma_free(struct svc_xprt *xprt);
 static int svc_rdma_has_wspace(struct svc_xprt *xprt);
 static int svc_rdma_secure_port(struct svc_rqst *);
+static void svc_rdma_kill_temp_xprt(struct svc_xprt *);
 static struct svc_xprt_ops svc_rdma_ops = {
 	.xpo_create = svc_rdma_create,
 	.xpo_has_wspace = svc_rdma_has_wspace,
 	.xpo_accept = svc_rdma_accept,
 	.xpo_secure_port = svc_rdma_secure_port,
+	.xpo_kill_temp_xprt = svc_rdma_kill_temp_xprt,
 };
 struct svc_xprt_class svc_rdma_class = {
 	return 1;
 }
+static void svc_rdma_kill_temp_xprt(struct svc_xprt *xprt)
+{
+}
 int svc_rdma_send(struct svcxprt_rdma *xprt, struct ib_send_wr *wr)
 {
 	struct ib_send_wr *bad_wr, *n_wr;

net/tipc/socket.c+1−47

@@ -1,7 +1,7 @@
1	/*	1	/*
2	* net/tipc/socket.c: TIPC socket API	2	* net/tipc/socket.c: TIPC socket API
3	*	3	*
4	* Copyright (c) 2001-2007, 2012-2015, Ericsson AB	4	* Copyright (c) 2001-2007, 2012-2016, Ericsson AB
5	* Copyright (c) 2004-2008, 2010-2013, Wind River Systems	5	* Copyright (c) 2004-2008, 2010-2013, Wind River Systems
6	* All rights reserved.	6	* All rights reserved.
7	*	7	*
@@ -127,54 +127,8 @@ static const struct proto_ops packet_ops; · 119 unmodified lines
127	static const struct proto_ops stream_ops;	127	static const struct proto_ops stream_ops;
128	static const struct proto_ops msg_ops;	128	static const struct proto_ops msg_ops;
129	static struct proto tipc_proto;	129	static struct proto tipc_proto;
130
131	static const struct rhashtable_params tsk_rht_params;	130	static const struct rhashtable_params tsk_rht_params;
132		131
133	/*
134	* Revised TIPC socket locking policy:
135	*
136	* Most socket operations take the standard socket lock when they start
137	* and hold it until they finish (or until they need to sleep). Acquiring
138	* this lock grants the owner exclusive access to the fields of the socket
139	* data structures, with the exception of the backlog queue. A few socket
140	* operations can be done without taking the socket lock because they only
141	* read socket information that never changes during the life of the socket.
142	*
143	* Socket operations may acquire the lock for the associated TIPC port if they
144	* need to perform an operation on the port. If any routine needs to acquire
145	* both the socket lock and the port lock it must take the socket lock first
146	* to avoid the risk of deadlock.
147	*
148	* The dispatcher handling incoming messages cannot grab the socket lock in
149	* the standard fashion, since invoked it runs at the BH level and cannot block.
150	* Instead, it checks to see if the socket lock is currently owned by someone,
151	* and either handles the message itself or adds it to the socket's backlog
152	* queue; in the latter case the queued message is processed once the process
153	* owning the socket lock releases it.
154	*
155	* NOTE: Releasing the socket lock while an operation is sleeping overcomes
156	* the problem of a blocked socket operation preventing any other operations
157	* from occurring. However, applications must be careful if they have
158	* multiple threads trying to send (or receive) on the same socket, as these
159	* operations might interfere with each other. For example, doing a connect
160	* and a receive at the same time might allow the receive to consume the
161	* ACK message meant for the connect. While additional work could be done
162	* to try and overcome this, it doesn't seem to be worthwhile at the present.
163	*
164	* NOTE: Releasing the socket lock while an operation is sleeping also ensures
165	* that another operation that must be performed in a non-blocking manner is
166	* not delayed for very long because the lock has already been taken.
167	*
168	* NOTE: This code assumes that certain fields of a port/socket pair are
169	* constant over its lifetime; such fields can be examined without taking
170	* the socket lock and/or port lock, and do not need to be re-read even
171	* after resuming processing after waiting. These fields include:
172	* - socket type
173	* - pointer to socket sk structure (aka tipc_sock structure)
174	* - pointer to port structure
175	* - port reference
176	*/
177
178	static u32 tsk_own_node(struct tipc_sock *tsk)	132	static u32 tsk_own_node(struct tipc_sock *tsk)
179	{	133	{
180	return msg_prevnode(&tsk->phdr);	134	return msg_prevnode(&tsk->phdr);

net/unix/af_unix.c+11−6

  *	Sleep until more data has arrived. But check for races..
  */
 static long unix_stream_data_wait(struct sock *sk, long timeo,
-				  struct sk_buff *last, unsigned int last_len)
+				  struct sk_buff *last, unsigned int last_len,
+				  bool freezable)
 {
 	struct sk_buff *tail;
 	DEFINE_WAIT(wait);
 		sk_set_bit(SOCKWQ_ASYNC_WAITDATA, sk);
 		unix_state_unlock(sk);
-		timeo = freezable_schedule_timeout(timeo);
+		if (freezable)
+			timeo = freezable_schedule_timeout(timeo);
+		else
+			timeo = schedule_timeout(timeo);
 		unix_state_lock(sk);
 		if (sock_flag(sk, SOCK_DEAD))
 	unsigned int splice_flags;
 };
-static int unix_stream_read_generic(struct unix_stream_read_state *state)
+static int unix_stream_read_generic(struct unix_stream_read_state *state,
+				    bool freezable)
 {
 	struct scm_cookie scm;
 	struct socket *sock = state->socket;
 			mutex_unlock(&u->iolock);
 			timeo = unix_stream_data_wait(sk, timeo, last,
-						      last_len);
+						      last_len, freezable);
 			if (signal_pending(current)) {
 				err = sock_intr_errno(timeo);
 		.flags = flags
 	};
-	return unix_stream_read_generic(&state);
+	return unix_stream_read_generic(&state, true);
 }
 static int unix_stream_splice_actor(struct sk_buff *skb,
 	    flags & SPLICE_F_NONBLOCK)
 		state.flags = MSG_DONTWAIT;
-	return unix_stream_read_generic(&state);
+	return unix_stream_read_generic(&state, false);
 }
 static int unix_shutdown(struct socket *sock, int mode)

net/wireless/core.h+1−0

@@ -71,6 +71,7 @@ struct cfg80211_registered_device { · 70 unmodified lines
71	struct list_head bss_list;	71	struct list_head bss_list;
72	struct rb_root bss_tree;	72	struct rb_root bss_tree;
73	u32 bss_generation;	73	u32 bss_generation;
		74	u32 bss_entries;
74	struct cfg80211_scan_request scan_req; / protected by RTNL */	75	struct cfg80211_scan_request scan_req; / protected by RTNL */
75	struct sk_buff *scan_msg;	76	struct sk_buff *scan_msg;
76	struct cfg80211_sched_scan_request __rcu *sched_scan_req;	77	struct cfg80211_sched_scan_request __rcu *sched_scan_req;

net/wireless/scan.c+69−0

@@ -57,6 +57,19 @@ · 56 unmodified lines
57	* also linked into the probe response struct.	57	* also linked into the probe response struct.
58	*/	58	*/
59		59
		60	/*
		61	* Limit the number of BSS entries stored in mac80211. Each one is
		62	* a bit over 4k at most, so this limits to roughly 4-5M of memory.
		63	* If somebody wants to really attack this though, they'd likely
		64	* use small beacons, and only one type of frame, limiting each of
		65	* the entries to a much smaller size (in order to generate more
		66	* entries in total, so overhead is bigger.)
		67	*/
		68	static int bss_entries_limit = 1000;
		69	module_param(bss_entries_limit, int, 0644);
		70	MODULE_PARM_DESC(bss_entries_limit,
		71	"limit to number of scan BSS entries (per wiphy, default 1000)");
		72
60	#define IEEE80211_SCAN_RESULT_EXPIRE (30 * HZ)	73	#define IEEE80211_SCAN_RESULT_EXPIRE (30 * HZ)
61		74
62	static void bss_free(struct cfg80211_internal_bss *bss)	75	static void bss_free(struct cfg80211_internal_bss *bss)
@@ -137,6 +150,10 @@ static bool __cfg80211_unlink_bss(struct cfg80211_registered_device *rdev, · 74 unmodified lines
137		150
138	list_del_init(&bss->list);	151	list_del_init(&bss->list);
139	rb_erase(&bss->rbn, &rdev->bss_tree);	152	rb_erase(&bss->rbn, &rdev->bss_tree);
		153	rdev->bss_entries--;
		154	WARN_ONCE((rdev->bss_entries == 0) ^ list_empty(&rdev->bss_list),
		155	"rdev bss entries[%d]/list[empty:%d] corruption\n",
		156	rdev->bss_entries, list_empty(&rdev->bss_list));
140	bss_ref_put(rdev, bss);	157	bss_ref_put(rdev, bss);
141	return true;	158	return true;
142	}	159	}
@@ -163,6 +180,40 @@ static void __cfg80211_bss_expire(struct cfg80211_registered_device *rdev, · 20 unmodified lines
163	rdev->bss_generation++;	180	rdev->bss_generation++;
164	}	181	}
165		182
		183	static bool cfg80211_bss_expire_oldest(struct cfg80211_registered_device *rdev)
		184	{
		185	struct cfg80211_internal_bss bss, oldest = NULL;
		186	bool ret;
		187
		188	lockdep_assert_held(&rdev->bss_lock);
		189
		190	list_for_each_entry(bss, &rdev->bss_list, list) {
		191	if (atomic_read(&bss->hold))
		192	continue;
		193
		194	if (!list_empty(&bss->hidden_list) &&
		195	!bss->pub.hidden_beacon_bss)
		196	continue;
		197
		198	if (oldest && time_before(oldest->ts, bss->ts))
		199	continue;
		200	oldest = bss;
		201	}
		202
		203	if (WARN_ON(!oldest))
		204	return false;
		205
		206	/*
		207	* The callers make sure to increase rdev->bss_generation if anything
		208	* gets removed (and a new entry added), so there's no need to also do
		209	* it here.
		210	*/
		211
		212	ret = __cfg80211_unlink_bss(rdev, oldest);
		213	WARN_ON(!ret);
		214	return ret;
		215	}
		216
166	void ___cfg80211_scan_done(struct cfg80211_registered_device *rdev,	217	void ___cfg80211_scan_done(struct cfg80211_registered_device *rdev,
167	bool send_message)	218	bool send_message)
168	{	219	{
@@ -689,6 +740,7 @@ static bool cfg80211_combine_bsses(struct cfg80211_registered_device *rdev, · 520 unmodified lines
689	const u8 *ie;	740	const u8 *ie;
690	int i, ssidlen;	741	int i, ssidlen;
691	u8 fold = 0;	742	u8 fold = 0;
		743	u32 n_entries = 0;
692		744
693	ies = rcu_access_pointer(new->pub.beacon_ies);	745	ies = rcu_access_pointer(new->pub.beacon_ies);
694	if (WARN_ON(!ies))	746	if (WARN_ON(!ies))
@@ -712,6 +764,12 @@ static bool cfg80211_combine_bsses(struct cfg80211_registered_device *rdev, · 17 unmodified lines
712	/* This is the bad part ... */	764	/* This is the bad part ... */
713		765
714	list_for_each_entry(bss, &rdev->bss_list, list) {	766	list_for_each_entry(bss, &rdev->bss_list, list) {
		767	/*
		768	* we're iterating all the entries anyway, so take the
		769	* opportunity to validate the list length accounting
		770	*/
		771	n_entries++;
		772
715	if (!ether_addr_equal(bss->pub.bssid, new->pub.bssid))	773	if (!ether_addr_equal(bss->pub.bssid, new->pub.bssid))
716	continue;	774	continue;
717	if (bss->pub.channel != new->pub.channel)	775	if (bss->pub.channel != new->pub.channel)
@@ -740,6 +798,10 @@ static bool cfg80211_combine_bsses(struct cfg80211_registered_device *rdev, · 22 unmodified lines
740	new->pub.beacon_ies);	798	new->pub.beacon_ies);
741	}	799	}
742		800
		801	WARN_ONCE(n_entries != rdev->bss_entries,
		802	"rdev bss entries[%d]/list[len:%d] corruption\n",
		803	rdev->bss_entries, n_entries);
		804
743	return true;	805	return true;
744	}	806	}
745		807
@@ -894,7 +956,14 @@ cfg80211_bss_update(struct cfg80211_registered_device *rdev, · 148 unmodified lines
894	}	956	}
895	}	957	}
896		958
		959	if (rdev->bss_entries >= bss_entries_limit &&
		960	!cfg80211_bss_expire_oldest(rdev)) {
		961	kfree(new);
		962	goto drop;
		963	}
		964
897	list_add_tail(&new->list, &rdev->bss_list);	965	list_add_tail(&new->list, &rdev->bss_list);
		966	rdev->bss_entries++;
898	rb_insert_bss(rdev, new);	967	rb_insert_bss(rdev, new);
899	found = new;	968	found = new;
900	}	969	}

net/wireless/util.c+2−1

 		   58500000,
 		   65000000,
 		   78000000,
-		   0,
+		/* not in the spec, but some devices use this: */
+		   86500000,
 		},
 		{  13500000,
 		   27000000,

scripts/Makefile.build+75−6

@@ -159,7 +159,8 @@ cmd_cpp_i_c = $(CPP) $(c_flags) -o $@ $< · 158 unmodified lines
159	$(obj)/%.i: $(src)/%.c FORCE	159	$(obj)/%.i: $(src)/%.c FORCE
160	$(call if_changed_dep,cpp_i_c)	160	$(call if_changed_dep,cpp_i_c)
161		161
162	cmd_gensymtypes = \	162	# These mirror gensymtypes_S and co below, keep them in synch.
		163	cmd_gensymtypes_c = \
163	$(CPP) -D__GENKSYMS__ $(c_flags) $< \| \	164	$(CPP) -D__GENKSYMS__ $(c_flags) $< \| \
164	$(GENKSYMS) $(if $(1), -T $(2)) \	165	$(GENKSYMS) $(if $(1), -T $(2)) \
165	$(patsubst y,-s _,$(CONFIG_HAVE_UNDERSCORE_SYMBOL_PREFIX)) \	166	$(patsubst y,-s _,$(CONFIG_HAVE_UNDERSCORE_SYMBOL_PREFIX)) \
@@ -169,7 +170,7 @@ cmd_gensymtypes = \ · 3 unmodified lines
169	quiet_cmd_cc_symtypes_c = SYM $(quiet_modtag) $@	170	quiet_cmd_cc_symtypes_c = SYM $(quiet_modtag) $@
170	cmd_cc_symtypes_c = \	171	cmd_cc_symtypes_c = \
171	set -e; \	172	set -e; \
172	$(call cmd_gensymtypes,true,$@) >/dev/null; \	173	$(call cmd_gensymtypes_c,true,$@) >/dev/null; \
173	test -s $@ \|\| rm -f $@	174	test -s $@ \|\| rm -f $@
174		175
175	$(obj)/%.symtypes : $(src)/%.c FORCE	176	$(obj)/%.symtypes : $(src)/%.c FORCE
@@ -198,9 +199,10 @@ else · 22 unmodified lines
198	# the actual value of the checksum generated by genksyms	199	# the actual value of the checksum generated by genksyms
199		200
200	cmd_cc_o_c = $(CC) $(c_flags) -c -o $(@D)/.tmp_$(@F) $<	201	cmd_cc_o_c = $(CC) $(c_flags) -c -o $(@D)/.tmp_$(@F) $<
201	cmd_modversions = \	202
		203	cmd_modversions_c = \
202	if $(OBJDUMP) -h $(@D)/.tmp_$(@F) \| grep -q __ksymtab; then \	204	if $(OBJDUMP) -h $(@D)/.tmp_$(@F) \| grep -q __ksymtab; then \
203	$(call cmd_gensymtypes,$(KBUILD_SYMTYPES),$(@:.o=.symtypes)) \	205	$(call cmd_gensymtypes_c,$(KBUILD_SYMTYPES),$(@:.o=.symtypes)) \
204	> $(@D)/.tmp_$(@F:.o=.ver); \	206	> $(@D)/.tmp_$(@F:.o=.ver); \
205	\	207	\
206	$(LD) $(LDFLAGS) -r -o $@ $(@D)/.tmp_$(@F) \	208	$(LD) $(LDFLAGS) -r -o $@ $(@D)/.tmp_$(@F) \
@@ -268,13 +270,14 @@ endif # CONFIG_STACK_VALIDATION · 61 unmodified lines
268	define rule_cc_o_c	270	define rule_cc_o_c
269	$(call echo-cmd,checksrc) $(cmd_checksrc) \	271	$(call echo-cmd,checksrc) $(cmd_checksrc) \
270	$(call cmd_and_fixdep,cc_o_c) \	272	$(call cmd_and_fixdep,cc_o_c) \
271	$(cmd_modversions) \	273	$(cmd_modversions_c) \
272	$(cmd_objtool) \	274	$(cmd_objtool) \
273	$(call echo-cmd,record_mcount) $(cmd_record_mcount)	275	$(call echo-cmd,record_mcount) $(cmd_record_mcount)
274	endef	276	endef
275		277
276	define rule_as_o_S	278	define rule_as_o_S
277	$(call cmd_and_fixdep,as_o_S) \	279	$(call cmd_and_fixdep,as_o_S) \
		280	$(cmd_modversions_S) \
278	$(cmd_objtool)	281	$(cmd_objtool)
279	endef	282	endef
280		283
@@ -314,6 +317,39 @@ modkern_aflags := $(KBUILD_AFLAGS_KERNEL) $(AFLAGS_KERNEL) · 33 unmodified lines
314	$(real-objs-m) : modkern_aflags := $(KBUILD_AFLAGS_MODULE) $(AFLAGS_MODULE)	317	$(real-objs-m) : modkern_aflags := $(KBUILD_AFLAGS_MODULE) $(AFLAGS_MODULE)
315	$(real-objs-m:.o=.s): modkern_aflags := $(KBUILD_AFLAGS_MODULE) $(AFLAGS_MODULE)	318	$(real-objs-m:.o=.s): modkern_aflags := $(KBUILD_AFLAGS_MODULE) $(AFLAGS_MODULE)
316		319
		320	# .S file exports must have their C prototypes defined in asm/asm-prototypes.h
		321	# or a file that it includes, in order to get versioned symbols. We build a
		322	# dummy C file that includes asm-prototypes and the EXPORT_SYMBOL lines from
		323	# the .S file (with trailing ';'), and run genksyms on that, to extract vers.
		324	#
		325	# This is convoluted. The .S file must first be preprocessed to run guards and
		326	# expand names, then the resulting exports must be constructed into plain
		327	# EXPORT_SYMBOL(symbol); to build our dummy C file, and that gets preprocessed
		328	# to make the genksyms input.
		329	#
		330	# These mirror gensymtypes_c and co above, keep them in synch.
		331	cmd_gensymtypes_S = \
		332	(echo "\#include <linux/kernel.h>" ; \
		333	echo "\#include <asm/asm-prototypes.h>" ; \
		334	$(CPP) $(a_flags) $< \| \
		335	grep "\<___EXPORT_SYMBOL\>" \| \
		336	sed 's/.___EXPORT_SYMBOL[[:space:]]$[a-zA-Z0-9_]$[[:space:]],.*/EXPORT_SYMBOL(\1);/' ) \| \
		337	$(CPP) -D__GENKSYMS__ $(c_flags) -xc - \| \
		338	$(GENKSYMS) $(if $(1), -T $(2)) \
		339	$(patsubst y,-s _,$(CONFIG_HAVE_UNDERSCORE_SYMBOL_PREFIX)) \
		340	$(if $(KBUILD_PRESERVE),-p) \
		341	-r $(firstword $(wildcard $(2:.symtypes=.symref) /dev/null))
		342
		343	quiet_cmd_cc_symtypes_S = SYM $(quiet_modtag) $@
		344	cmd_cc_symtypes_S = \
		345	set -e; \
		346	$(call cmd_gensymtypes_S,true,$@) >/dev/null; \
		347	test -s $@ \|\| rm -f $@
		348
		349	$(obj)/%.symtypes : $(src)/%.S FORCE
		350	$(call cmd,cc_symtypes_S)
		351
		352
317	quiet_cmd_cpp_s_S = CPP $(quiet_modtag) $@	353	quiet_cmd_cpp_s_S = CPP $(quiet_modtag) $@
318	cmd_cpp_s_S = $(CPP) $(a_flags) -o $@ $<	354	cmd_cpp_s_S = $(CPP) $(a_flags) -o $@ $<
319		355
@@ -321,7 +357,37 @@ $(obj)/%.s: $(src)/%.S FORCE · 1 unmodified line
321	$(call if_changed_dep,cpp_s_S)	357	$(call if_changed_dep,cpp_s_S)
322		358
323	quiet_cmd_as_o_S = AS $(quiet_modtag) $@	359	quiet_cmd_as_o_S = AS $(quiet_modtag) $@
324	cmd_as_o_S = $(CC) $(a_flags) -c -o $@ $<	360
		361	ifndef CONFIG_MODVERSIONS
		362	cmd_as_o_S = $(CC) $(a_flags) -c -o $@ $<
		363
		364	else
		365
		366	ASM_PROTOTYPES := $(wildcard $(srctree)/arch/$(SRCARCH)/include/asm/asm-prototypes.h)
		367
		368	ifeq ($(ASM_PROTOTYPES),)
		369	cmd_as_o_S = $(CC) $(a_flags) -c -o $@ $<
		370
		371	else
		372
		373	# versioning matches the C process described above, with difference that
		374	# we parse asm-prototypes.h C header to get function definitions.
		375
		376	cmd_as_o_S = $(CC) $(a_flags) -c -o $(@D)/.tmp_$(@F) $<
		377
		378	cmd_modversions_S = \
		379	if $(OBJDUMP) -h $(@D)/.tmp_$(@F) \| grep -q __ksymtab; then \
		380	$(call cmd_gensymtypes_S,$(KBUILD_SYMTYPES),$(@:.o=.symtypes)) \
		381	> $(@D)/.tmp_$(@F:.o=.ver); \
		382	\
		383	$(LD) $(LDFLAGS) -r -o $@ $(@D)/.tmp_$(@F) \
		384	-T $(@D)/.tmp_$(@F:.o=.ver); \
		385	rm -f $(@D)/.tmp_$(@F) $(@D)/.tmp_$(@F:.o=.ver); \
		386	else \
		387	mv -f $(@D)/.tmp_$(@F) $@; \
		388	fi;
		389	endif
		390	endif
325		391
326	$(obj)/%.o: $(src)/%.S $(objtool_obj) FORCE	392	$(obj)/%.o: $(src)/%.S $(objtool_obj) FORCE
327	$(call if_changed_rule,as_o_S)	393	$(call if_changed_rule,as_o_S)
@@ -430,6 +496,9 @@ cmd_export_list = $(OBJDUMP) -h $< \| \ · 102 unmodified lines
430		496
431	$(obj)/lib-ksyms.o: $(lib-target) FORCE	497	$(obj)/lib-ksyms.o: $(lib-target) FORCE
432	$(call if_changed,export_list)	498	$(call if_changed,export_list)
		499
		500	targets += $(obj)/lib-ksyms.o
		501
433	endif	502	endif
434		503
435	#	504	#

scripts/gcc-x86_64-has-stack-protector.sh+1−1

@@ -1,6 +1,6 @@
1	#!/bin/sh	1	#!/bin/sh
2		2
3	echo "int foo(void) { char X[200]; return 3; }" \| $* -S -x c -c -O0 -mcmodel=kernel -fstack-protector - -o - 2> /dev/null \| grep -q "%gs"	3	echo "int foo(void) { char X[200]; return 3; }" \| $* -S -x c -c -O0 -mcmodel=kernel -fno-PIE -fstack-protector - -o - 2> /dev/null \| grep -q "%gs"
4	if [ "$?" -eq "0" ] ; then	4	if [ "$?" -eq "0" ] ; then
5	echo y	5	echo y
6	else	6	else

security/apparmor/domain.c+4−2

 	/* released below */
 	cred = get_current_cred();
 	cxt = cred_cxt(cred);
-	profile = aa_cred_profile(cred);
+	profile = aa_get_newest_profile(aa_cred_profile(cred));
-	previous_profile = cxt->previous;
+	previous_profile = aa_get_newest_profile(cxt->previous);
 	if (unconfined(profile)) {
 		info = "unconfined";
 out:
 	aa_put_profile(hat);
 	kfree(name);
+	aa_put_profile(profile);
+	aa_put_profile(previous_profile);
 	put_cred(cred);
 	return error;

sound/pci/hda/patch_realtek.c+0−2

 		.v.pins = (const struct hda_pintbl[]) {
 			{ 0x15, 0x40f000f0 }, /* disabled */
 			{ 0x16, 0x40f000f0 }, /* disabled */
-			{ 0x18, 0x01014011 }, /* LO */
-			{ 0x1a, 0x01014012 }, /* LO */
 			{ }
 		}
 	},

sound/pci/hda/thinkpad_helper.c+2−1

@@ -13,7 +13,8 @@ static void (old_vmaster_hook)(void , int); · 12 unmodified lines
13	static bool is_thinkpad(struct hda_codec *codec)	13	static bool is_thinkpad(struct hda_codec *codec)
14	{	14	{
15	return (codec->core.subsystem_id >> 16 == 0x17aa) &&	15	return (codec->core.subsystem_id >> 16 == 0x17aa) &&
16	(acpi_dev_found("LEN0068") \|\| acpi_dev_found("IBM0068"));	16	(acpi_dev_found("LEN0068") \|\| acpi_dev_found("LEN0268") \|\|
		17	acpi_dev_found("IBM0068"));
17	}	18	}
18		19
19	static void update_tpacpi_mute_led(void *private_data, int enabled)	20	static void update_tpacpi_mute_led(void *private_data, int enabled)

sound/usb/card.c+2−1

@@ -315,7 +315,8 @@ static int snd_usb_audio_free(struct snd_usb_audio *chip) · 314 unmodified lines
315	snd_usb_endpoint_free(ep);	315	snd_usb_endpoint_free(ep);
316		316
317	mutex_destroy(&chip->mutex);	317	mutex_destroy(&chip->mutex);
318	dev_set_drvdata(&chip->dev->dev, NULL);	318	if (!atomic_read(&chip->shutdown))
		319	dev_set_drvdata(&chip->dev->dev, NULL);
319	kfree(chip);	320	kfree(chip);
320	return 0;	321	return 0;
321	}	322	}

tools/power/acpi/Makefile.config+12−11

@@ -8,18 +8,19 @@ · 7 unmodified lines
8	# as published by the Free Software Foundation; version 2	8	# as published by the Free Software Foundation; version 2
9	# of the License.	9	# of the License.
10		10
11	include ../../../../scripts/Makefile.include	11	ifeq ($(srctree),)
12		12	srctree := $(patsubst %/,%,$(dir $(shell pwd)))
13	OUTPUT=./	13	srctree := $(patsubst %/,%,$(dir $(srctree)))
14	ifeq ("$(origin O)", "command line")	14	#$(info Determined 'srctree' to be $(srctree))
15	OUTPUT := $(O)/
16	endif	15	endif
17		16
18	ifneq ($(OUTPUT),)	17	include $(srctree)/../../scripts/Makefile.include
19	# check that the output directory actually exists	18
20	OUTDIR := $(shell cd $(OUTPUT) && /bin/pwd)	19	OUTPUT=$(srctree)/
21	$(if $(OUTDIR),, $(error output directory "$(OUTPUT)" does not exist))	20	ifeq ("$(origin O)", "command line")
		21	OUTPUT := $(O)/power/acpi/
22	endif	22	endif
		23	#$(info Determined 'OUTPUT' to be $(OUTPUT))
23		24
24	# --- CONFIGURATION BEGIN ---	25	# --- CONFIGURATION BEGIN ---
25		26
@@ -70,8 +71,8 @@ WARNINGS := -Wall · 44 unmodified lines
70	WARNINGS += $(call cc-supports,-Wstrict-prototypes)	71	WARNINGS += $(call cc-supports,-Wstrict-prototypes)
71	WARNINGS += $(call cc-supports,-Wdeclaration-after-statement)	72	WARNINGS += $(call cc-supports,-Wdeclaration-after-statement)
72		73
73	KERNEL_INCLUDE := ../../../include	74	KERNEL_INCLUDE := $(OUTPUT)include
74	ACPICA_INCLUDE := ../../../drivers/acpi/acpica	75	ACPICA_INCLUDE := $(srctree)/../../../drivers/acpi/acpica
75	CFLAGS += -D_LINUX -I$(KERNEL_INCLUDE) -I$(ACPICA_INCLUDE)	76	CFLAGS += -D_LINUX -I$(KERNEL_INCLUDE) -I$(ACPICA_INCLUDE)
76	CFLAGS += $(WARNINGS)	77	CFLAGS += $(WARNINGS)
77		78

tools/power/acpi/Makefile.rules+27−13

 # as published by the Free Software Foundation; version 2
 # of the License.
-$(OUTPUT)$(TOOL): $(TOOL_OBJS) FORCE
+objdir := $(OUTPUT)tools/$(TOOL)/
-	$(ECHO) "  LD      " $@
+toolobjs := $(addprefix $(objdir),$(TOOL_OBJS))
-	$(QUIET) $(LD) $(CFLAGS) $(LDFLAGS) $(TOOL_OBJS) -L$(OUTPUT) -o $@
+$(OUTPUT)$(TOOL): $(toolobjs) FORCE
+	$(ECHO) "  LD      " $(subst $(OUTPUT),,$@)
+	$(QUIET) $(LD) $(CFLAGS) $(LDFLAGS) $(toolobjs) -L$(OUTPUT) -o $@
+	$(ECHO) "  STRIP   " $(subst $(OUTPUT),,$@)
 	$(QUIET) $(STRIPCMD) $@
-$(OUTPUT)%.o: %.c
+$(KERNEL_INCLUDE):
-	$(ECHO) "  CC      " $@
+	$(ECHO) "  MKDIR   " $(subst $(OUTPUT),,$@)
+	$(QUIET) mkdir -p $(KERNEL_INCLUDE)
+	$(ECHO) "  CP      " $(subst $(OUTPUT),,$@)
+	$(QUIET) cp -rf $(srctree)/../../../include/acpi $(KERNEL_INCLUDE)/
+$(objdir)%.o: %.c $(KERNEL_INCLUDE)
+	$(ECHO) "  CC      " $(subst $(OUTPUT),,$@)
 	$(QUIET) $(CC) -c $(CFLAGS) -o $@ $<
 all: $(OUTPUT)$(TOOL)
 clean:
-	-find $(OUTPUT) \( -not -type d \) \
+	$(ECHO) "  RMOBJ   " $(subst $(OUTPUT),,$(objdir))
-	-and \( -name '*~' -o -name '*.[oas]' \) \
+	$(QUIET) find $(objdir) \( -not -type d \)\
-	-type f -print \
+		 -and \( -name '*~' -o -name '*.[oas]' \)\
-	 | xargs rm -f
+		 -type f -print | xargs rm -f
-	-rm -f $(OUTPUT)$(TOOL)
+	$(ECHO) "  RM      " $(TOOL)
+	$(QUIET) rm -f $(OUTPUT)$(TOOL)
+	$(ECHO) "  RMINC   " $(subst $(OUTPUT),,$(KERNEL_INCLUDE))
+	$(QUIET) rm -rf $(KERNEL_INCLUDE)
 install-tools:
-	$(INSTALL) -d $(DESTDIR)${sbindir}
+	$(ECHO) "  INST    " $(TOOL)
-	$(INSTALL_PROGRAM) $(OUTPUT)$(TOOL) $(DESTDIR)${sbindir}
+	$(QUIET) $(INSTALL) -d $(DESTDIR)$(sbindir)
+	$(QUIET) $(INSTALL_PROGRAM) $(OUTPUT)$(TOOL) $(DESTDIR)$(sbindir)
 uninstall-tools:
-	- rm -f $(DESTDIR)${sbindir}/$(TOOL)
+	$(ECHO) "  UNINST  " $(TOOL)
+	$(QUIET) rm -f $(DESTDIR)$(sbindir)/$(TOOL)
 install: all install-tools $(EXTRA_INSTALL)
 uninstall: uninstall-tools $(EXTRA_UNINSTALL)

tools/power/acpi/tools/acpidbg/Makefile+1−3

 	../../os_specific/service_layers\
 	.
 CFLAGS += -DACPI_APPLICATION -DACPI_SINGLE_THREAD -DACPI_DEBUGGER\
-	-I.\
+	-I.
-	-I../../../../../drivers/acpi/acpica\
-	-I../../../../../include
 LDFLAGS += -lpthread
 TOOL_OBJS = \
 	acpidbg.o

tools/power/acpi/tools/acpidbg/acpidbg.c+7−1

 #include <acpi/acpi.h>
 /* Headers not included by include/acpi/platform/aclinux.h */
+#include <unistd.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <error.h>
 #include <stdbool.h>
 #include <fcntl.h>
 #include <assert.h>
-#include <linux/circ_buf.h>
+#include <sys/select.h>
+#include "../../../../../include/linux/circ_buf.h"
 #define ACPI_AML_FILE		"/sys/kernel/debug/acpi/acpidbg"
 #define ACPI_AML_SEC_TICK	1

tools/power/acpi/tools/acpidump/Makefile+6−6

 	./\
 	../../common\
 	../../os_specific/service_layers
-CFLAGS += -DACPI_DUMP_APP -I.\
+CFLAGS += -DACPI_DUMP_APP -I.
-	-I../../../../../drivers/acpi/acpica\
-	-I../../../../../include
 TOOL_OBJS = \
 	apdump.o\
 	apfiles.o\
 include ../../Makefile.rules
-install-man: ../../man/acpidump.8
+install-man: $(srctree)/man/acpidump.8
-	$(INSTALL_DATA) -D $< $(DESTDIR)${mandir}/man8/acpidump.8
+	$(ECHO) "  INST    " acpidump.8
+	$(QUIET) $(INSTALL_DATA) -D $< $(DESTDIR)$(mandir)/man8/acpidump.8
 uninstall-man:
-	- rm -f $(DESTDIR)${mandir}/man8/acpidump.8
+	$(ECHO) "  UNINST  " acpidump.8
+	$(QUIET) rm -f $(DESTDIR)$(mandir)/man8/acpidump.8

virt/kvm/arm/pmu.c+5−3

 			continue;
 		type = vcpu_sys_reg(vcpu, PMEVTYPER0_EL0 + i)
 		       & ARMV8_PMU_EVTYPE_EVENT;
-		if ((type == ARMV8_PMU_EVTYPE_EVENT_SW_INCR)
+		if ((type == ARMV8_PMUV3_PERFCTR_SW_INCR)
 		    && (enable & BIT(i))) {
 			reg = vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + i) + 1;
 			reg = lower_32_bits(reg);
 	eventsel = data & ARMV8_PMU_EVTYPE_EVENT;
 	/* Software increment event does't need to be backed by a perf event */
-	if (eventsel == ARMV8_PMU_EVTYPE_EVENT_SW_INCR)
+	if (eventsel == ARMV8_PMUV3_PERFCTR_SW_INCR &&
+	    select_idx != ARMV8_PMU_CYCLE_IDX)
 		return;
 	memset(&attr, 0, sizeof(struct perf_event_attr));
 	attr.exclude_kernel = data & ARMV8_PMU_EXCLUDE_EL1 ? 1 : 0;
 	attr.exclude_hv = 1; /* Don't count EL2 events */
 	attr.exclude_host = 1; /* Don't count host events */
-	attr.config = eventsel;
+	attr.config = (select_idx == ARMV8_PMU_CYCLE_IDX) ?
+		ARMV8_PMUV3_PERFCTR_CPU_CYCLES : eventsel;
 	counter = kvm_pmu_get_counter_value(vcpu, select_idx);
 	/* The initial sample period (overflow count) of an event. */

virt/kvm/async_pf.c+12−1

 	spin_lock(&vcpu->async_pf.lock);
 	list_add_tail(&apf->link, &vcpu->async_pf.done);
+	apf->vcpu = NULL;
 	spin_unlock(&vcpu->async_pf.lock);
 	/*
 void kvm_clear_async_pf_completion_queue(struct kvm_vcpu *vcpu)
 {
+	spin_lock(&vcpu->async_pf.lock);
 	/* cancel outstanding work queue item */
 	while (!list_empty(&vcpu->async_pf.queue)) {
 		struct kvm_async_pf *work =
 					 typeof(*work), queue);
 		list_del(&work->queue);
+		/*
+		 * We know it's present in vcpu->async_pf.done, do
+		 * nothing here.
+		 */
+		if (!work->vcpu)
+			continue;
+		spin_unlock(&vcpu->async_pf.lock);
 #ifdef CONFIG_KVM_ASYNC_PF_SYNC
 		flush_work(&work->work);
 #else
 			kmem_cache_free(async_pf_cache, work);
 		}
 #endif
+		spin_lock(&vcpu->async_pf.lock);
 	}
-	spin_lock(&vcpu->async_pf.lock);
 	while (!list_empty(&vcpu->async_pf.done)) {
 		struct kvm_async_pf *work =
 			list_first_entry(&vcpu->async_pf.done,