History

Merge tag 'mips_5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

Pull MIPS updates from Paul Burton: "A light batch this time around but significant improvements for certain systems: - Removal of readq & writeq for MIPS32 kernels where they would simply BUG() anyway, allowing drivers or other code that #ifdefs on their presence to work properly. - Improvements for Ingenic JZ4740 systems, including support for the external memory controller & pinmuxing fixes for qi_lb60/NanoNote systems. - Improvements for Lantiq systems, in particular around SMP & IPIs. - DT updates for ralink/MediaTek MT7628a systems to probe & configure a bunch more devices. - Miscellaneous cleanups & build fixes" * tag 'mips_5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (30 commits) MIPS: fix some more fall through errors in arch/mips MIPS: perf events: handle switch statement falling through warnings mips/kprobes: Export kprobe_fault_handler() MAINTAINERS: Add myself as Ingenic SoCs maintainer MIPS: ralink: mt7628a.dtsi: Add watchdog controller DT node MIPS: ralink: mt7628a.dtsi: Add SPI controller DT node MIPS: ralink: mt7628a.dtsi: Add GPIO controller DT node MIPS: ralink: mt7628a.dtsi: Add pinctrl DT properties to the UART nodes MIPS: ralink: mt7628a.dtsi: Add pinmux DT node MIPS: ralink: mt7628a.dtsi: Add SPDX GPL-2.0 license identifier MIPS: lantiq: Add SMP support for lantiq interrupt controller MIPS: lantiq: Shorten register names, remove unused macros MIPS: lantiq: Fix bitfield masking MIPS: lantiq: Remove unused macros MIPS: lantiq: Fix attributes of of_device_id structure MIPS: lantiq: Change variables to the same type as the source MIPS: lantiq: Move macro directly to iomem function mips: Remove q-accessors from non-64bit platforms FDDI: defza: Include linux/io-64-nonatomic-lo-hi.h MIPS: configs: Remove useless UEVENT_HELPER_PATH ...

Linus Torvalds committed 7 years ago

Commit fa121bb2 parents 7d4901c e5793cd50 files · +412 −192Browse files

Unified · Split

50 files
  1. MAINTAINERS +27 −0
  2. arch/mips/ar7/setup.c +1 −0
  3. arch/mips/ath79/setup.c +1 −1
  4. arch/mips/bcm63xx/dev-flash.c +1 −0
  5. arch/mips/boot/dts/ralink/mt7628a.dtsi +147 −1
  6. arch/mips/cavium-octeon/executive/cvmx-pko.c +1 −1
  7. arch/mips/configs/ar7_defconfig +0 −1
  8. arch/mips/configs/ath25_defconfig +0 −1
  9. arch/mips/configs/ath79_defconfig +0 −1
  10. arch/mips/configs/bcm63xx_defconfig +0 −1
  11. arch/mips/configs/bigsur_defconfig +0 −1
  12. arch/mips/configs/bmips_be_defconfig +0 −1
  13. arch/mips/configs/bmips_stb_defconfig +0 −1
  14. arch/mips/configs/cavium_octeon_defconfig +0 −1
  15. arch/mips/configs/ci20_defconfig +0 −1
  16. arch/mips/configs/cobalt_defconfig +0 −1
  17. arch/mips/configs/fuloong2e_defconfig +0 −1
  18. arch/mips/configs/gpr_defconfig +0 −1
  19. arch/mips/configs/ip27_defconfig +0 −1
  20. arch/mips/configs/ip32_defconfig +0 −1
  21. arch/mips/configs/lemote2f_defconfig +0 −2
  22. arch/mips/configs/loongson1b_defconfig +0 −1
  23. arch/mips/configs/loongson1c_defconfig +0 −1
  24. arch/mips/configs/loongson3_defconfig +0 −1
  25. arch/mips/configs/malta_defconfig +0 −1
  26. arch/mips/configs/malta_kvm_defconfig +0 −1
  27. arch/mips/configs/malta_kvm_guest_defconfig +0 −1
  28. arch/mips/configs/maltaup_xpa_defconfig +0 −1
  29. arch/mips/configs/mips_paravirt_defconfig +0 −1
  30. arch/mips/configs/omega2p_defconfig +0 −1
  31. arch/mips/configs/pistachio_defconfig +0 −1
  32. arch/mips/configs/pnx8335_stb225_defconfig +0 −1
  33. arch/mips/configs/qi_lb60_defconfig +0 −2
  34. arch/mips/configs/rb532_defconfig +0 −1
  35. arch/mips/configs/rt305x_defconfig +0 −1
  36. arch/mips/configs/sb1250_swarm_defconfig +0 −1
  37. arch/mips/configs/tb0219_defconfig +0 −1
  38. arch/mips/configs/tb0226_defconfig +0 −1
  39. arch/mips/configs/tb0287_defconfig +0 −1
  40. arch/mips/configs/vocore2_defconfig +0 −1
  41. arch/mips/configs/xway_defconfig +0 −1
  42. arch/mips/include/asm/cpu.h +60 −65
  43. arch/mips/include/asm/io.h +11 −0
  44. arch/mips/include/asm/mach-ralink/pinmux.h +0 −1
  45. arch/mips/jz4740/board-qi_lb60.c +8 −8
  46. arch/mips/kernel/ftrace.c +12 −11
  47. arch/mips/kernel/perf_event_mipsxx.c +15 −15
  48. arch/mips/lantiq/irq.c +126 −51
  49. drivers/memory/jz4780-nemc.c +1 −1
  50. drivers/net/fddi/defza.c +1 −0
MAINTAINERS+27−0
@@ -7955,6 +7955,33 @@ L: linux-mtd@lists.infradead.org · 7954 unmodified lines
7955S: Maintained7955S: Maintained
7956F: drivers/mtd/nand/raw/ingenic/7956F: drivers/mtd/nand/raw/ingenic/
7957 7957
7958INGENIC JZ47xx SoCs
7959M: Paul Cercueil <paul@crapouillou.net>
7960S: Maintained
7961F: arch/mips/boot/dts/ingenic/
7962F: arch/mips/include/asm/mach-jz4740/
7963F: arch/mips/jz4740/
7964F: drivers/clk/ingenic/
7965F: drivers/dma/dma-jz4780.c
7966F: drivers/gpu/drm/ingenic/
7967F: drivers/i2c/busses/i2c-jz4780.c
7968F: drivers/iio/adc/ingenic-adc.c
7969F: drivers/irqchip/irq-ingenic.c
7970F: drivers/memory/jz4780-nemc.c
7971F: drivers/mmc/host/jz4740_mmc.c
7972F: drivers/mtd/nand/raw/ingenic/
7973F: drivers/pinctrl/pinctrl-ingenic.c
7974F: drivers/power/supply/ingenic-battery.c
7975F: drivers/pwm/pwm-jz4740.c
7976F: drivers/rtc/rtc-jz4740.c
7977F: drivers/tty/serial/8250/8250_ingenic.c
7978F: drivers/usb/musb/jz4740.c
7979F: drivers/watchdog/jz4740_wdt.c
7980F: include/dt-bindings/iio/adc/ingenic,adc.h
7981F: include/linux/mfd/ingenic-tcu.h
7982F: sound/soc/jz4740/
7983F: sound/soc/codecs/jz47*
7984
7958INOTIFY7985INOTIFY
7959M: Jan Kara <jack@suse.cz>7986M: Jan Kara <jack@suse.cz>
7960R: Amir Goldstein <amir73il@gmail.com>7987R: Amir Goldstein <amir73il@gmail.com>
arch/mips/ar7/setup.c+1−0
@@ -57,6 +57,7 @@ const char *get_system_type(void) · 56 unmodified lines
57 case TITAN_CHIP_1060:57 case TITAN_CHIP_1060:
58 return "TI AR7 (TNETV1060)";58 return "TI AR7 (TNETV1060)";
59 }59 }
60 /* fall through */
60 default:61 default:
61 return "TI AR7 (unknown)";62 return "TI AR7 (unknown)";
62 }63 }
arch/mips/ath79/setup.c+1−1
@@ -153,7 +153,7 @@ static void __init ath79_detect_sys_type(void) · 152 unmodified lines
153 case REV_ID_MAJOR_QCA9533_V2:153 case REV_ID_MAJOR_QCA9533_V2:
154 ver = 2;154 ver = 2;
155 ath79_soc_rev = 2;155 ath79_soc_rev = 2;
156 /* drop through */156 /* fall through */
157 157
158 case REV_ID_MAJOR_QCA9533:158 case REV_ID_MAJOR_QCA9533:
159 ath79_soc = ATH79_SOC_QCA9533;159 ath79_soc = ATH79_SOC_QCA9533;
arch/mips/bcm63xx/dev-flash.c+1−0
@@ -94,6 +94,7 @@ static int __init bcm63xx_detect_flash_type(void) · 93 unmodified lines
94 case STRAPBUS_6368_BOOT_SEL_PARALLEL:94 case STRAPBUS_6368_BOOT_SEL_PARALLEL:
95 return BCM63XX_FLASH_TYPE_PARALLEL;95 return BCM63XX_FLASH_TYPE_PARALLEL;
96 }96 }
97 /* fall through */
97 default:98 default:
98 return -EINVAL;99 return -EINVAL;
99 }100 }
arch/mips/boot/dts/ralink/mt7628a.dtsi+147−1
@@ -1,3 +1,5 @@
1// SPDX-License-Identifier: GPL-2.0
2
1/ {3/ {
2 #address-cells = <1>;4 #address-cells = <1>;
3 #size-cells = <1>;5 #size-cells = <1>;
@@ -36,7 +38,113 @@ · 32 unmodified lines
36 38
37 sysc: system-controller@0 {39 sysc: system-controller@0 {
38 compatible = "ralink,mt7620a-sysc", "syscon";40 compatible = "ralink,mt7620a-sysc", "syscon";
39 reg = <0x0 0x100>;41 reg = <0x0 0x60>;
42 };
43
44 pinmux: pinmux@60 {
45 compatible = "pinctrl-single";
46 reg = <0x60 0x8>;
47 #address-cells = <1>;
48 #size-cells = <0>;
49 #pinctrl-cells = <2>;
50 pinctrl-single,bit-per-mux;
51 pinctrl-single,register-width = <32>;
52 pinctrl-single,function-mask = <0x1>;
53
54 pinmux_gpio_gpio: pinmux_gpio_gpio {
55 pinctrl-single,bits = <0x0 0x0 0x3>;
56 };
57
58 pinmux_spi_cs1_cs: pinmux_spi_cs1_cs {
59 pinctrl-single,bits = <0x0 0x0 0x30>;
60 };
61
62 pinmux_i2s_gpio: pinmux_i2s_gpio {
63 pinctrl-single,bits = <0x0 0x40 0xc0>;
64 };
65
66 pinmux_uart0_uart: pinmux_uart0_uart0 {
67 pinctrl-single,bits = <0x0 0x0 0x300>;
68 };
69
70 pinmux_sdmode_sdxc: pinmux_sdmode_sdxc {
71 pinctrl-single,bits = <0x0 0x0 0xc00>;
72 };
73
74 pinmux_sdmode_gpio: pinmux_sdmode_gpio {
75 pinctrl-single,bits = <0x0 0x400 0xc00>;
76 };
77
78 pinmux_spi_spi: pinmux_spi_spi {
79 pinctrl-single,bits = <0x0 0x0 0x1000>;
80 };
81
82 pinmux_refclk_gpio: pinmux_refclk_gpio {
83 pinctrl-single,bits = <0x0 0x40000 0x40000>;
84 };
85
86 pinmux_i2c_i2c: pinmux_i2c_i2c {
87 pinctrl-single,bits = <0x0 0x0 0x300000>;
88 };
89
90 pinmux_uart1_uart: pinmux_uart1_uart1 {
91 pinctrl-single,bits = <0x0 0x0 0x3000000>;
92 };
93
94 pinmux_uart2_uart: pinmux_uart2_uart {
95 pinctrl-single,bits = <0x0 0x0 0xc000000>;
96 };
97
98 pinmux_pwm0_pwm: pinmux_pwm0_pwm {
99 pinctrl-single,bits = <0x0 0x0 0x30000000>;
100 };
101
102 pinmux_pwm0_gpio: pinmux_pwm0_gpio {
103 pinctrl-single,bits = <0x0 0x10000000
104 0x30000000>;
105 };
106
107 pinmux_pwm1_pwm: pinmux_pwm1_pwm {
108 pinctrl-single,bits = <0x0 0x0 0xc0000000>;
109 };
110
111 pinmux_pwm1_gpio: pinmux_pwm1_gpio {
112 pinctrl-single,bits = <0x0 0x40000000
113 0xc0000000>;
114 };
115
116 pinmux_p0led_an_gpio: pinmux_p0led_an_gpio {
117 pinctrl-single,bits = <0x4 0x4 0xc>;
118 };
119
120 pinmux_p1led_an_gpio: pinmux_p1led_an_gpio {
121 pinctrl-single,bits = <0x4 0x10 0x30>;
122 };
123
124 pinmux_p2led_an_gpio: pinmux_p2led_an_gpio {
125 pinctrl-single,bits = <0x4 0x40 0xc0>;
126 };
127
128 pinmux_p3led_an_gpio: pinmux_p3led_an_gpio {
129 pinctrl-single,bits = <0x4 0x100 0x300>;
130 };
131
132 pinmux_p4led_an_gpio: pinmux_p4led_an_gpio {
133 pinctrl-single,bits = <0x4 0x400 0xc00>;
134 };
135 };
136
137 watchdog: watchdog@100 {
138 compatible = "mediatek,mt7621-wdt";
139 reg = <0x100 0x30>;
140
141 resets = <&resetc 8>;
142 reset-names = "wdt";
143
144 interrupt-parent = <&intc>;
145 interrupts = <24>;
146
147 status = "disabled";
40 };148 };
41 149
42 intc: interrupt-controller@200 {150 intc: interrupt-controller@200 {
@@ -62,10 +170,42 @@ · 19 unmodified lines
62 reg = <0x300 0x100>;170 reg = <0x300 0x100>;
63 };171 };
64 172
173 gpio: gpio@600 {
174 compatible = "mediatek,mt7621-gpio";
175 reg = <0x600 0x100>;
176
177 gpio-controller;
178 interrupt-controller;
179 #gpio-cells = <2>;
180 #interrupt-cells = <2>;
181
182 interrupt-parent = <&intc>;
183 interrupts = <6>;
184 };
185
186 spi: spi@b00 {
187 compatible = "ralink,mt7621-spi";
188 reg = <0xb00 0x100>;
189
190 pinctrl-names = "default";
191 pinctrl-0 = <&pinmux_spi_spi>;
192
193 resets = <&resetc 18>;
194 reset-names = "spi";
195
196 #address-cells = <1>;
197 #size-cells = <0>;
198
199 status = "disabled";
200 };
201
65 uart0: uartlite@c00 {202 uart0: uartlite@c00 {
66 compatible = "ns16550a";203 compatible = "ns16550a";
67 reg = <0xc00 0x100>;204 reg = <0xc00 0x100>;
68 205
206 pinctrl-names = "default";
207 pinctrl-0 = <&pinmux_uart0_uart>;
208
69 resets = <&resetc 12>;209 resets = <&resetc 12>;
70 reset-names = "uart0";210 reset-names = "uart0";
71 211
@@ -79,6 +219,9 @@ · 7 unmodified lines
79 compatible = "ns16550a";219 compatible = "ns16550a";
80 reg = <0xd00 0x100>;220 reg = <0xd00 0x100>;
81 221
222 pinctrl-names = "default";
223 pinctrl-0 = <&pinmux_uart1_uart>;
224
82 resets = <&resetc 19>;225 resets = <&resetc 19>;
83 reset-names = "uart1";226 reset-names = "uart1";
84 227
@@ -92,6 +235,9 @@ · 7 unmodified lines
92 compatible = "ns16550a";235 compatible = "ns16550a";
93 reg = <0xe00 0x100>;236 reg = <0xe00 0x100>;
94 237
238 pinctrl-names = "default";
239 pinctrl-0 = <&pinmux_uart2_uart>;
240
95 resets = <&resetc 20>;241 resets = <&resetc 20>;
96 reset-names = "uart2";242 reset-names = "uart2";
97 243
arch/mips/cavium-octeon/executive/cvmx-pko.c+1−1
@@ -485,11 +485,11 @@ cvmx_pko_status_t cvmx_pko_config_port(uint64_t port, uint64_t base_queue, · 484 unmodified lines
485 config.s.qos_mask = 0xff;485 config.s.qos_mask = 0xff;
486 break;486 break;
487 case CVMX_PKO_QUEUE_STATIC_PRIORITY:487 case CVMX_PKO_QUEUE_STATIC_PRIORITY:
488 /* Pass 1 will fall through to the error case */
489 if (!cvmx_octeon_is_pass1()) {488 if (!cvmx_octeon_is_pass1()) {
490 config.s.qos_mask = 0xff;489 config.s.qos_mask = 0xff;
491 break;490 break;
492 }491 }
492 /* fall through - to the error case, when Pass 1 */
493 default:493 default:
494 cvmx_dprintf("ERROR: cvmx_pko_config_port: Invalid "494 cvmx_dprintf("ERROR: cvmx_pko_config_port: Invalid "
495 "priority %llu\n",495 "priority %llu\n",
arch/mips/configs/ar7_defconfig+0−1
@@ -71,7 +71,6 @@ CONFIG_NET_ACT_POLICE=y · 70 unmodified lines
71CONFIG_HAMRADIO=y71CONFIG_HAMRADIO=y
72CONFIG_CFG80211=m72CONFIG_CFG80211=m
73CONFIG_MAC80211=m73CONFIG_MAC80211=m
74CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
75CONFIG_MTD=y74CONFIG_MTD=y
76CONFIG_MTD_BLOCK=y75CONFIG_MTD_BLOCK=y
77CONFIG_MTD_CFI=y76CONFIG_MTD_CFI=y
arch/mips/configs/ath25_defconfig+0−1
@@ -37,7 +37,6 @@ CONFIG_IP_ADVANCED_ROUTER=y · 36 unmodified lines
37CONFIG_CFG80211=m37CONFIG_CFG80211=m
38CONFIG_MAC80211=m38CONFIG_MAC80211=m
39CONFIG_MAC80211_DEBUGFS=y39CONFIG_MAC80211_DEBUGFS=y
40CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
41CONFIG_MTD=y40CONFIG_MTD=y
42CONFIG_MTD_REDBOOT_PARTS=y41CONFIG_MTD_REDBOOT_PARTS=y
43CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-242CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-2
arch/mips/configs/ath79_defconfig+0−1
@@ -37,7 +37,6 @@ CONFIG_IP_ADVANCED_ROUTER=y · 36 unmodified lines
37CONFIG_CFG80211=m37CONFIG_CFG80211=m
38CONFIG_MAC80211=m38CONFIG_MAC80211=m
39CONFIG_MAC80211_DEBUGFS=y39CONFIG_MAC80211_DEBUGFS=y
40CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
41CONFIG_MTD=y40CONFIG_MTD=y
42CONFIG_MTD_REDBOOT_PARTS=y41CONFIG_MTD_REDBOOT_PARTS=y
43CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-242CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-2
arch/mips/configs/bcm63xx_defconfig+0−1
@@ -34,7 +34,6 @@ CONFIG_INET=y · 33 unmodified lines
34CONFIG_CFG80211=y34CONFIG_CFG80211=y
35CONFIG_NL80211_TESTMODE=y35CONFIG_NL80211_TESTMODE=y
36CONFIG_MAC80211=y36CONFIG_MAC80211=y
37CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
38# CONFIG_STANDALONE is not set37# CONFIG_STANDALONE is not set
39# CONFIG_PREVENT_FIRMWARE_BUILD is not set38# CONFIG_PREVENT_FIRMWARE_BUILD is not set
40CONFIG_MTD=y39CONFIG_MTD=y
arch/mips/configs/bigsur_defconfig+0−1
@@ -99,7 +99,6 @@ CONFIG_BPQETHER=m · 98 unmodified lines
99CONFIG_BAYCOM_SER_FDX=m99CONFIG_BAYCOM_SER_FDX=m
100CONFIG_BAYCOM_SER_HDX=m100CONFIG_BAYCOM_SER_HDX=m
101CONFIG_YAM=m101CONFIG_YAM=m
102CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
103CONFIG_FW_LOADER=m102CONFIG_FW_LOADER=m
104CONFIG_BLK_DEV_LOOP=m103CONFIG_BLK_DEV_LOOP=m
105CONFIG_BLK_DEV_CRYPTOLOOP=m104CONFIG_BLK_DEV_CRYPTOLOOP=m
arch/mips/configs/bmips_be_defconfig+0−1
@@ -26,7 +26,6 @@ CONFIG_INET=y · 25 unmodified lines
26CONFIG_CFG80211=y26CONFIG_CFG80211=y
27CONFIG_NL80211_TESTMODE=y27CONFIG_NL80211_TESTMODE=y
28CONFIG_MAC80211=y28CONFIG_MAC80211=y
29CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
30CONFIG_DEVTMPFS=y29CONFIG_DEVTMPFS=y
31CONFIG_DEVTMPFS_MOUNT=y30CONFIG_DEVTMPFS_MOUNT=y
32# CONFIG_STANDALONE is not set31# CONFIG_STANDALONE is not set
arch/mips/configs/bmips_stb_defconfig+0−1
@@ -35,7 +35,6 @@ CONFIG_INET=y · 34 unmodified lines
35CONFIG_CFG80211=y35CONFIG_CFG80211=y
36CONFIG_NL80211_TESTMODE=y36CONFIG_NL80211_TESTMODE=y
37CONFIG_MAC80211=y37CONFIG_MAC80211=y
38CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
39CONFIG_DEVTMPFS=y38CONFIG_DEVTMPFS=y
40CONFIG_DEVTMPFS_MOUNT=y39CONFIG_DEVTMPFS_MOUNT=y
41# CONFIG_STANDALONE is not set40# CONFIG_STANDALONE is not set
arch/mips/configs/cavium_octeon_defconfig+0−1
@@ -42,7 +42,6 @@ CONFIG_IP_MROUTE=y · 41 unmodified lines
42CONFIG_IP_PIMSM_V1=y42CONFIG_IP_PIMSM_V1=y
43CONFIG_IP_PIMSM_V2=y43CONFIG_IP_PIMSM_V2=y
44CONFIG_SYN_COOKIES=y44CONFIG_SYN_COOKIES=y
45CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
46CONFIG_DEVTMPFS=y45CONFIG_DEVTMPFS=y
47# CONFIG_FW_LOADER is not set46# CONFIG_FW_LOADER is not set
48CONFIG_MTD=y47CONFIG_MTD=y
arch/mips/configs/ci20_defconfig+0−1
@@ -44,7 +44,6 @@ CONFIG_IP_PNP_DHCP=y · 43 unmodified lines
44# CONFIG_INET_DIAG is not set44# CONFIG_INET_DIAG is not set
45# CONFIG_IPV6 is not set45# CONFIG_IPV6 is not set
46# CONFIG_WIRELESS is not set46# CONFIG_WIRELESS is not set
47CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
48CONFIG_DEVTMPFS=y47CONFIG_DEVTMPFS=y
49# CONFIG_FW_LOADER is not set48# CONFIG_FW_LOADER is not set
50# CONFIG_ALLOW_DEV_COREDUMP is not set49# CONFIG_ALLOW_DEV_COREDUMP is not set
arch/mips/configs/cobalt_defconfig+0−1
@@ -14,7 +14,6 @@ CONFIG_NET_KEY=y · 13 unmodified lines
14CONFIG_NET_KEY_MIGRATE=y14CONFIG_NET_KEY_MIGRATE=y
15CONFIG_INET=y15CONFIG_INET=y
16# CONFIG_IPV6 is not set16# CONFIG_IPV6 is not set
17CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
18CONFIG_MTD=y17CONFIG_MTD=y
19CONFIG_MTD_JEDECPROBE=y18CONFIG_MTD_JEDECPROBE=y
20CONFIG_MTD_CFI_AMDSTD=y19CONFIG_MTD_CFI_AMDSTD=y
arch/mips/configs/fuloong2e_defconfig+0−1
@@ -83,7 +83,6 @@ CONFIG_IP_NF_ARPFILTER=m · 82 unmodified lines
83CONFIG_IP_NF_ARP_MANGLE=m83CONFIG_IP_NF_ARP_MANGLE=m
84CONFIG_PHONET=m84CONFIG_PHONET=m
85CONFIG_NET_9P=m85CONFIG_NET_9P=m
86CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
87CONFIG_FW_LOADER=m86CONFIG_FW_LOADER=m
88CONFIG_MTD=m87CONFIG_MTD=m
89CONFIG_MTD_BLOCK=m88CONFIG_MTD_BLOCK=m
arch/mips/configs/gpr_defconfig+0−1
@@ -249,7 +249,6 @@ CONFIG_WATCHDOG_NOWAYOUT=y · 248 unmodified lines
249CONFIG_SSB=m249CONFIG_SSB=m
250CONFIG_SSB_DRIVER_PCICORE=y250CONFIG_SSB_DRIVER_PCICORE=y
251# CONFIG_VGA_ARB is not set251# CONFIG_VGA_ARB is not set
252CONFIG_BACKLIGHT_LCD_SUPPORT=y
253# CONFIG_LCD_CLASS_DEVICE is not set252# CONFIG_LCD_CLASS_DEVICE is not set
254CONFIG_BACKLIGHT_CLASS_DEVICE=y253CONFIG_BACKLIGHT_CLASS_DEVICE=y
255# CONFIG_BACKLIGHT_GENERIC is not set254# CONFIG_BACKLIGHT_GENERIC is not set
arch/mips/configs/ip27_defconfig+0−1
@@ -91,7 +91,6 @@ CONFIG_NET_ACT_SKBEDIT=m · 90 unmodified lines
91CONFIG_CFG80211=m91CONFIG_CFG80211=m
92CONFIG_MAC80211=m92CONFIG_MAC80211=m
93CONFIG_RFKILL=m93CONFIG_RFKILL=m
94CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
95CONFIG_BLK_DEV_LOOP=y94CONFIG_BLK_DEV_LOOP=y
96CONFIG_BLK_DEV_CRYPTOLOOP=m95CONFIG_BLK_DEV_CRYPTOLOOP=m
97CONFIG_CDROM_PKTCDVD=m96CONFIG_CDROM_PKTCDVD=m
arch/mips/configs/ip32_defconfig+0−1
@@ -42,7 +42,6 @@ CONFIG_INET6_ESP=m · 41 unmodified lines
42CONFIG_INET6_IPCOMP=m42CONFIG_INET6_IPCOMP=m
43CONFIG_IPV6_TUNNEL=m43CONFIG_IPV6_TUNNEL=m
44CONFIG_NETWORK_SECMARK=y44CONFIG_NETWORK_SECMARK=y
45CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
46CONFIG_CONNECTOR=y45CONFIG_CONNECTOR=y
47CONFIG_BLK_DEV_LOOP=m46CONFIG_BLK_DEV_LOOP=m
48CONFIG_BLK_DEV_CRYPTOLOOP=m47CONFIG_BLK_DEV_CRYPTOLOOP=m
arch/mips/configs/lemote2f_defconfig+0−2
@@ -77,7 +77,6 @@ CONFIG_MAC80211=m · 76 unmodified lines
77CONFIG_MAC80211_LEDS=y77CONFIG_MAC80211_LEDS=y
78CONFIG_RFKILL=m78CONFIG_RFKILL=m
79CONFIG_RFKILL_INPUT=y79CONFIG_RFKILL_INPUT=y
80CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
81CONFIG_BLK_DEV_LOOP=y80CONFIG_BLK_DEV_LOOP=y
82CONFIG_BLK_DEV_CRYPTOLOOP=m81CONFIG_BLK_DEV_CRYPTOLOOP=m
83CONFIG_BLK_DEV_RAM=y82CONFIG_BLK_DEV_RAM=y
@@ -144,7 +143,6 @@ CONFIG_FB_TILEBLITTING=y · 60 unmodified lines
144CONFIG_FB_SIS=y143CONFIG_FB_SIS=y
145CONFIG_FB_SIS_300=y144CONFIG_FB_SIS_300=y
146CONFIG_FB_SIS_315=y145CONFIG_FB_SIS_315=y
147CONFIG_BACKLIGHT_LCD_SUPPORT=y
148# CONFIG_LCD_CLASS_DEVICE is not set146# CONFIG_LCD_CLASS_DEVICE is not set
149CONFIG_BACKLIGHT_CLASS_DEVICE=y147CONFIG_BACKLIGHT_CLASS_DEVICE=y
150CONFIG_BACKLIGHT_GENERIC=m148CONFIG_BACKLIGHT_GENERIC=m
arch/mips/configs/loongson1b_defconfig+0−1
@@ -34,7 +34,6 @@ CONFIG_SYN_COOKIES=y · 33 unmodified lines
34# CONFIG_INET_DIAG is not set34# CONFIG_INET_DIAG is not set
35# CONFIG_IPV6 is not set35# CONFIG_IPV6 is not set
36# CONFIG_WIRELESS is not set36# CONFIG_WIRELESS is not set
37CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
38CONFIG_DEVTMPFS=y37CONFIG_DEVTMPFS=y
39CONFIG_DEVTMPFS_MOUNT=y38CONFIG_DEVTMPFS_MOUNT=y
40# CONFIG_STANDALONE is not set39# CONFIG_STANDALONE is not set
arch/mips/configs/loongson1c_defconfig+0−1
@@ -35,7 +35,6 @@ CONFIG_SYN_COOKIES=y · 34 unmodified lines
35# CONFIG_INET_DIAG is not set35# CONFIG_INET_DIAG is not set
36# CONFIG_IPV6 is not set36# CONFIG_IPV6 is not set
37# CONFIG_WIRELESS is not set37# CONFIG_WIRELESS is not set
38CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
39CONFIG_DEVTMPFS=y38CONFIG_DEVTMPFS=y
40CONFIG_DEVTMPFS_MOUNT=y39CONFIG_DEVTMPFS_MOUNT=y
41# CONFIG_STANDALONE is not set40# CONFIG_STANDALONE is not set
arch/mips/configs/loongson3_defconfig+0−1
@@ -97,7 +97,6 @@ CONFIG_CFG80211_WEXT=y · 96 unmodified lines
97CONFIG_MAC80211=m97CONFIG_MAC80211=m
98CONFIG_RFKILL=m98CONFIG_RFKILL=m
99CONFIG_RFKILL_INPUT=y99CONFIG_RFKILL_INPUT=y
100CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
101CONFIG_DEVTMPFS=y100CONFIG_DEVTMPFS=y
102CONFIG_DEVTMPFS_MOUNT=y101CONFIG_DEVTMPFS_MOUNT=y
103CONFIG_MTD=m102CONFIG_MTD=m
arch/mips/configs/malta_defconfig+0−1
@@ -214,7 +214,6 @@ CONFIG_CFG80211=m · 213 unmodified lines
214CONFIG_MAC80211=m214CONFIG_MAC80211=m
215CONFIG_MAC80211_MESH=y215CONFIG_MAC80211_MESH=y
216CONFIG_RFKILL=m216CONFIG_RFKILL=m
217CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
218CONFIG_DEVTMPFS=y217CONFIG_DEVTMPFS=y
219CONFIG_CONNECTOR=m218CONFIG_CONNECTOR=m
220CONFIG_MTD=y219CONFIG_MTD=y
arch/mips/configs/malta_kvm_defconfig+0−1
@@ -219,7 +219,6 @@ CONFIG_CFG80211=m · 218 unmodified lines
219CONFIG_MAC80211=m219CONFIG_MAC80211=m
220CONFIG_MAC80211_MESH=y220CONFIG_MAC80211_MESH=y
221CONFIG_RFKILL=m221CONFIG_RFKILL=m
222CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
223CONFIG_DEVTMPFS=y222CONFIG_DEVTMPFS=y
224CONFIG_CONNECTOR=m223CONFIG_CONNECTOR=m
225CONFIG_MTD=y224CONFIG_MTD=y
arch/mips/configs/malta_kvm_guest_defconfig+0−1
@@ -216,7 +216,6 @@ CONFIG_CFG80211=m · 215 unmodified lines
216CONFIG_MAC80211=m216CONFIG_MAC80211=m
217CONFIG_MAC80211_MESH=y217CONFIG_MAC80211_MESH=y
218CONFIG_RFKILL=m218CONFIG_RFKILL=m
219CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
220CONFIG_DEVTMPFS=y219CONFIG_DEVTMPFS=y
221CONFIG_CONNECTOR=m220CONFIG_CONNECTOR=m
222CONFIG_MTD=y221CONFIG_MTD=y
arch/mips/configs/maltaup_xpa_defconfig+0−1
@@ -216,7 +216,6 @@ CONFIG_CFG80211=m · 215 unmodified lines
216CONFIG_MAC80211=m216CONFIG_MAC80211=m
217CONFIG_MAC80211_MESH=y217CONFIG_MAC80211_MESH=y
218CONFIG_RFKILL=m218CONFIG_RFKILL=m
219CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
220CONFIG_DEVTMPFS=y219CONFIG_DEVTMPFS=y
221CONFIG_DEVTMPFS_MOUNT=y220CONFIG_DEVTMPFS_MOUNT=y
222CONFIG_CONNECTOR=m221CONFIG_CONNECTOR=m
arch/mips/configs/mips_paravirt_defconfig+0−1
@@ -39,7 +39,6 @@ CONFIG_IP_PIMSM_V1=y · 38 unmodified lines
39CONFIG_IP_PIMSM_V2=y39CONFIG_IP_PIMSM_V2=y
40CONFIG_SYN_COOKIES=y40CONFIG_SYN_COOKIES=y
41# CONFIG_WIRELESS is not set41# CONFIG_WIRELESS is not set
42CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
43# CONFIG_FW_LOADER is not set42# CONFIG_FW_LOADER is not set
44CONFIG_BLK_DEV_LOOP=y43CONFIG_BLK_DEV_LOOP=y
45CONFIG_VIRTIO_BLK=y44CONFIG_VIRTIO_BLK=y
arch/mips/configs/omega2p_defconfig+0−1
@@ -42,7 +42,6 @@ CONFIG_INET=y · 41 unmodified lines
42# CONFIG_INET_DIAG is not set42# CONFIG_INET_DIAG is not set
43# CONFIG_IPV6 is not set43# CONFIG_IPV6 is not set
44# CONFIG_WIRELESS is not set44# CONFIG_WIRELESS is not set
45CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
46CONFIG_DEVTMPFS=y45CONFIG_DEVTMPFS=y
47# CONFIG_FW_LOADER is not set46# CONFIG_FW_LOADER is not set
48# CONFIG_ALLOW_DEV_COREDUMP is not set47# CONFIG_ALLOW_DEV_COREDUMP is not set
arch/mips/configs/pistachio_defconfig+0−1
@@ -214,7 +214,6 @@ CONFIG_IR_IMG_RC6=y · 213 unmodified lines
214CONFIG_MEDIA_SUPPORT=y214CONFIG_MEDIA_SUPPORT=y
215CONFIG_FB=y215CONFIG_FB=y
216CONFIG_FB_MODE_HELPERS=y216CONFIG_FB_MODE_HELPERS=y
217CONFIG_BACKLIGHT_LCD_SUPPORT=y
218# CONFIG_LCD_CLASS_DEVICE is not set217# CONFIG_LCD_CLASS_DEVICE is not set
219CONFIG_BACKLIGHT_CLASS_DEVICE=y218CONFIG_BACKLIGHT_CLASS_DEVICE=y
220CONFIG_SOUND=y219CONFIG_SOUND=y
arch/mips/configs/pnx8335_stb225_defconfig+0−1
@@ -25,7 +25,6 @@ CONFIG_IP_PNP=y · 24 unmodified lines
25CONFIG_IP_PNP_DHCP=y25CONFIG_IP_PNP_DHCP=y
26CONFIG_INET_AH=y26CONFIG_INET_AH=y
27# CONFIG_IPV6 is not set27# CONFIG_IPV6 is not set
28CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
29CONFIG_MTD=y28CONFIG_MTD=y
30CONFIG_MTD_CMDLINE_PARTS=y29CONFIG_MTD_CMDLINE_PARTS=y
31CONFIG_MTD_BLOCK=y30CONFIG_MTD_BLOCK=y
arch/mips/configs/qi_lb60_defconfig+0−2
@@ -41,7 +41,6 @@ CONFIG_TCP_CONG_ADVANCED=y · 40 unmodified lines
41CONFIG_TCP_CONG_WESTWOOD=y41CONFIG_TCP_CONG_WESTWOOD=y
42# CONFIG_TCP_CONG_HTCP is not set42# CONFIG_TCP_CONG_HTCP is not set
43# CONFIG_IPV6 is not set43# CONFIG_IPV6 is not set
44CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
45CONFIG_MTD=y44CONFIG_MTD=y
46CONFIG_MTD_BLOCK=y45CONFIG_MTD_BLOCK=y
47CONFIG_MTD_RAW_NAND=y46CONFIG_MTD_RAW_NAND=y
@@ -77,7 +76,6 @@ CONFIG_REGULATOR=y · 29 unmodified lines
77CONFIG_REGULATOR_FIXED_VOLTAGE=y76CONFIG_REGULATOR_FIXED_VOLTAGE=y
78CONFIG_FB=y77CONFIG_FB=y
79CONFIG_FB_JZ4740=y78CONFIG_FB_JZ4740=y
80CONFIG_BACKLIGHT_LCD_SUPPORT=y
81CONFIG_LCD_CLASS_DEVICE=y79CONFIG_LCD_CLASS_DEVICE=y
82# CONFIG_BACKLIGHT_CLASS_DEVICE is not set80# CONFIG_BACKLIGHT_CLASS_DEVICE is not set
83# CONFIG_VGA_CONSOLE is not set81# CONFIG_VGA_CONSOLE is not set
arch/mips/configs/rb532_defconfig+0−1
@@ -104,7 +104,6 @@ CONFIG_NET_ACT_MIRRED=m · 103 unmodified lines
104CONFIG_NET_ACT_IPT=m104CONFIG_NET_ACT_IPT=m
105CONFIG_NET_ACT_PEDIT=m105CONFIG_NET_ACT_PEDIT=m
106CONFIG_HAMRADIO=y106CONFIG_HAMRADIO=y
107CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
108CONFIG_MTD=y107CONFIG_MTD=y
109CONFIG_MTD_BLOCK=y108CONFIG_MTD_BLOCK=y
110CONFIG_MTD_BLOCK2MTD=y109CONFIG_MTD_BLOCK2MTD=y
arch/mips/configs/rt305x_defconfig+0−1
@@ -69,7 +69,6 @@ CONFIG_BRIDGE=y · 68 unmodified lines
69CONFIG_VLAN_8021Q=y69CONFIG_VLAN_8021Q=y
70CONFIG_NET_SCHED=y70CONFIG_NET_SCHED=y
71CONFIG_HAMRADIO=y71CONFIG_HAMRADIO=y
72CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
73CONFIG_MTD=y72CONFIG_MTD=y
74CONFIG_MTD_CMDLINE_PARTS=y73CONFIG_MTD_CMDLINE_PARTS=y
75CONFIG_MTD_BLOCK=y74CONFIG_MTD_BLOCK=y
arch/mips/configs/sb1250_swarm_defconfig+0−1
@@ -43,7 +43,6 @@ CONFIG_NETWORK_SECMARK=y · 42 unmodified lines
43CONFIG_CFG80211=m43CONFIG_CFG80211=m
44CONFIG_MAC80211=m44CONFIG_MAC80211=m
45CONFIG_RFKILL=m45CONFIG_RFKILL=m
46CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
47CONFIG_FW_LOADER=m46CONFIG_FW_LOADER=m
48CONFIG_CONNECTOR=m47CONFIG_CONNECTOR=m
49CONFIG_BLK_DEV_RAM=y48CONFIG_BLK_DEV_RAM=y
arch/mips/configs/tb0219_defconfig+0−1
@@ -28,7 +28,6 @@ CONFIG_SYN_COOKIES=y · 27 unmodified lines
28# CONFIG_INET_XFRM_MODE_BEET is not set28# CONFIG_INET_XFRM_MODE_BEET is not set
29# CONFIG_IPV6 is not set29# CONFIG_IPV6 is not set
30CONFIG_NETWORK_SECMARK=y30CONFIG_NETWORK_SECMARK=y
31CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
32CONFIG_BLK_DEV_LOOP=m31CONFIG_BLK_DEV_LOOP=m
33CONFIG_BLK_DEV_NBD=m32CONFIG_BLK_DEV_NBD=m
34CONFIG_BLK_DEV_RAM=y33CONFIG_BLK_DEV_RAM=y
arch/mips/configs/tb0226_defconfig+0−1
@@ -26,7 +26,6 @@ CONFIG_SYN_COOKIES=y · 25 unmodified lines
26# CONFIG_INET_XFRM_MODE_BEET is not set26# CONFIG_INET_XFRM_MODE_BEET is not set
27# CONFIG_IPV6 is not set27# CONFIG_IPV6 is not set
28CONFIG_NETWORK_SECMARK=y28CONFIG_NETWORK_SECMARK=y
29CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
30CONFIG_BLK_DEV_LOOP=m29CONFIG_BLK_DEV_LOOP=m
31CONFIG_BLK_DEV_NBD=m30CONFIG_BLK_DEV_NBD=m
32CONFIG_BLK_DEV_RAM=y31CONFIG_BLK_DEV_RAM=y
arch/mips/configs/tb0287_defconfig+0−1
@@ -30,7 +30,6 @@ CONFIG_TCP_CONG_BIC=y · 29 unmodified lines
30CONFIG_TCP_CONG_CUBIC=m30CONFIG_TCP_CONG_CUBIC=m
31# CONFIG_IPV6 is not set31# CONFIG_IPV6 is not set
32CONFIG_NETWORK_SECMARK=y32CONFIG_NETWORK_SECMARK=y
33CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
34CONFIG_BLK_DEV_LOOP=m33CONFIG_BLK_DEV_LOOP=m
35CONFIG_BLK_DEV_NBD=m34CONFIG_BLK_DEV_NBD=m
36CONFIG_BLK_DEV_RAM=y35CONFIG_BLK_DEV_RAM=y
arch/mips/configs/vocore2_defconfig+0−1
@@ -42,7 +42,6 @@ CONFIG_INET=y · 41 unmodified lines
42# CONFIG_INET_DIAG is not set42# CONFIG_INET_DIAG is not set
43# CONFIG_IPV6 is not set43# CONFIG_IPV6 is not set
44# CONFIG_WIRELESS is not set44# CONFIG_WIRELESS is not set
45CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
46CONFIG_DEVTMPFS=y45CONFIG_DEVTMPFS=y
47# CONFIG_FW_LOADER is not set46# CONFIG_FW_LOADER is not set
48# CONFIG_ALLOW_DEV_COREDUMP is not set47# CONFIG_ALLOW_DEV_COREDUMP is not set
arch/mips/configs/xway_defconfig+0−1
@@ -71,7 +71,6 @@ CONFIG_BRIDGE=y · 70 unmodified lines
71CONFIG_VLAN_8021Q=y71CONFIG_VLAN_8021Q=y
72CONFIG_NET_SCHED=y72CONFIG_NET_SCHED=y
73CONFIG_HAMRADIO=y73CONFIG_HAMRADIO=y
74CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
75CONFIG_MTD=y74CONFIG_MTD=y
76CONFIG_MTD_CMDLINE_PARTS=y75CONFIG_MTD_CMDLINE_PARTS=y
77CONFIG_MTD_BLOCK=y76CONFIG_MTD_BLOCK=y
arch/mips/include/asm/cpu.h+60−65
@@ -9,6 +9,8 @@ · 8 unmodified lines
9#ifndef _ASM_CPU_H9#ifndef _ASM_CPU_H
10#define _ASM_CPU_H10#define _ASM_CPU_H
11 11
12#include <linux/bits.h>
13
12/*14/*
13 As of the MIPS32 and MIPS64 specs from MTI, the PRId register (CP015 As of the MIPS32 and MIPS64 specs from MTI, the PRId register (CP0
14 register 15, select 0) is defined in this (backwards compatible) way:16 register 15, select 0) is defined in this (backwards compatible) way:
@@ -352,77 +354,70 @@ enum cpu_type_enum { · 337 unmodified lines
352 MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2 | \354 MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2 | \
353 MIPS_CPU_ISA_M64R6)355 MIPS_CPU_ISA_M64R6)
354 356
355/*
356 * Private version of BIT_ULL() to escape include file recursion hell.
357 * We soon will have to switch to another mechanism that will work with
358 * more than 64 bits anyway.
359 */
360#define MBIT_ULL(bit) (1ULL << (bit))
361
362/*357/*
363 * CPU Option encodings358 * CPU Option encodings
364 */359 */
365#define MIPS_CPU_TLB MBIT_ULL( 0) /* CPU has TLB */360#define MIPS_CPU_TLB BIT_ULL( 0) /* CPU has TLB */
366#define MIPS_CPU_4KEX MBIT_ULL( 1) /* "R4K" exception model */361#define MIPS_CPU_4KEX BIT_ULL( 1) /* "R4K" exception model */
367#define MIPS_CPU_3K_CACHE MBIT_ULL( 2) /* R3000-style caches */362#define MIPS_CPU_3K_CACHE BIT_ULL( 2) /* R3000-style caches */
368#define MIPS_CPU_4K_CACHE MBIT_ULL( 3) /* R4000-style caches */363#define MIPS_CPU_4K_CACHE BIT_ULL( 3) /* R4000-style caches */
369#define MIPS_CPU_TX39_CACHE MBIT_ULL( 4) /* TX3900-style caches */364#define MIPS_CPU_TX39_CACHE BIT_ULL( 4) /* TX3900-style caches */
370#define MIPS_CPU_FPU MBIT_ULL( 5) /* CPU has FPU */365#define MIPS_CPU_FPU BIT_ULL( 5) /* CPU has FPU */
371#define MIPS_CPU_32FPR MBIT_ULL( 6) /* 32 dbl. prec. FP registers */366#define MIPS_CPU_32FPR BIT_ULL( 6) /* 32 dbl. prec. FP registers */
372#define MIPS_CPU_COUNTER MBIT_ULL( 7) /* Cycle count/compare */367#define MIPS_CPU_COUNTER BIT_ULL( 7) /* Cycle count/compare */
373#define MIPS_CPU_WATCH MBIT_ULL( 8) /* watchpoint registers */368#define MIPS_CPU_WATCH BIT_ULL( 8) /* watchpoint registers */
374#define MIPS_CPU_DIVEC MBIT_ULL( 9) /* dedicated interrupt vector */369#define MIPS_CPU_DIVEC BIT_ULL( 9) /* dedicated interrupt vector */
375#define MIPS_CPU_VCE MBIT_ULL(10) /* virt. coherence conflict possible */370#define MIPS_CPU_VCE BIT_ULL(10) /* virt. coherence conflict possible */
376#define MIPS_CPU_CACHE_CDEX_P MBIT_ULL(11) /* Create_Dirty_Exclusive CACHE op */371#define MIPS_CPU_CACHE_CDEX_P BIT_ULL(11) /* Create_Dirty_Exclusive CACHE op */
377#define MIPS_CPU_CACHE_CDEX_S MBIT_ULL(12) /* ... same for seconary cache ... */372#define MIPS_CPU_CACHE_CDEX_S BIT_ULL(12) /* ... same for seconary cache ... */
378#define MIPS_CPU_MCHECK MBIT_ULL(13) /* Machine check exception */373#define MIPS_CPU_MCHECK BIT_ULL(13) /* Machine check exception */
379#define MIPS_CPU_EJTAG MBIT_ULL(14) /* EJTAG exception */374#define MIPS_CPU_EJTAG BIT_ULL(14) /* EJTAG exception */
380#define MIPS_CPU_NOFPUEX MBIT_ULL(15) /* no FPU exception */375#define MIPS_CPU_NOFPUEX BIT_ULL(15) /* no FPU exception */
381#define MIPS_CPU_LLSC MBIT_ULL(16) /* CPU has ll/sc instructions */376#define MIPS_CPU_LLSC BIT_ULL(16) /* CPU has ll/sc instructions */
382#define MIPS_CPU_INCLUSIVE_CACHES MBIT_ULL(17) /* P-cache subset enforced */377#define MIPS_CPU_INCLUSIVE_CACHES BIT_ULL(17) /* P-cache subset enforced */
383#define MIPS_CPU_PREFETCH MBIT_ULL(18) /* CPU has usable prefetch */378#define MIPS_CPU_PREFETCH BIT_ULL(18) /* CPU has usable prefetch */
384#define MIPS_CPU_VINT MBIT_ULL(19) /* CPU supports MIPSR2 vectored interrupts */379#define MIPS_CPU_VINT BIT_ULL(19) /* CPU supports MIPSR2 vectored interrupts */
385#define MIPS_CPU_VEIC MBIT_ULL(20) /* CPU supports MIPSR2 external interrupt controller mode */380#define MIPS_CPU_VEIC BIT_ULL(20) /* CPU supports MIPSR2 external interrupt controller mode */
386#define MIPS_CPU_ULRI MBIT_ULL(21) /* CPU has ULRI feature */381#define MIPS_CPU_ULRI BIT_ULL(21) /* CPU has ULRI feature */
387#define MIPS_CPU_PCI MBIT_ULL(22) /* CPU has Perf Ctr Int indicator */382#define MIPS_CPU_PCI BIT_ULL(22) /* CPU has Perf Ctr Int indicator */
388#define MIPS_CPU_RIXI MBIT_ULL(23) /* CPU has TLB Read/eXec Inhibit */383#define MIPS_CPU_RIXI BIT_ULL(23) /* CPU has TLB Read/eXec Inhibit */
389#define MIPS_CPU_MICROMIPS MBIT_ULL(24) /* CPU has microMIPS capability */384#define MIPS_CPU_MICROMIPS BIT_ULL(24) /* CPU has microMIPS capability */
390#define MIPS_CPU_TLBINV MBIT_ULL(25) /* CPU supports TLBINV/F */385#define MIPS_CPU_TLBINV BIT_ULL(25) /* CPU supports TLBINV/F */
391#define MIPS_CPU_SEGMENTS MBIT_ULL(26) /* CPU supports Segmentation Control registers */386#define MIPS_CPU_SEGMENTS BIT_ULL(26) /* CPU supports Segmentation Control registers */
392#define MIPS_CPU_EVA MBIT_ULL(27) /* CPU supports Enhanced Virtual Addressing */387#define MIPS_CPU_EVA BIT_ULL(27) /* CPU supports Enhanced Virtual Addressing */
393#define MIPS_CPU_HTW MBIT_ULL(28) /* CPU support Hardware Page Table Walker */388#define MIPS_CPU_HTW BIT_ULL(28) /* CPU support Hardware Page Table Walker */
394#define MIPS_CPU_RIXIEX MBIT_ULL(29) /* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */389#define MIPS_CPU_RIXIEX BIT_ULL(29) /* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */
395#define MIPS_CPU_MAAR MBIT_ULL(30) /* MAAR(I) registers are present */390#define MIPS_CPU_MAAR BIT_ULL(30) /* MAAR(I) registers are present */
396#define MIPS_CPU_FRE MBIT_ULL(31) /* FRE & UFE bits implemented */391#define MIPS_CPU_FRE BIT_ULL(31) /* FRE & UFE bits implemented */
397#define MIPS_CPU_RW_LLB MBIT_ULL(32) /* LLADDR/LLB writes are allowed */392#define MIPS_CPU_RW_LLB BIT_ULL(32) /* LLADDR/LLB writes are allowed */
398#define MIPS_CPU_LPA MBIT_ULL(33) /* CPU supports Large Physical Addressing */393#define MIPS_CPU_LPA BIT_ULL(33) /* CPU supports Large Physical Addressing */
399#define MIPS_CPU_CDMM MBIT_ULL(34) /* CPU has Common Device Memory Map */394#define MIPS_CPU_CDMM BIT_ULL(34) /* CPU has Common Device Memory Map */
400#define MIPS_CPU_BP_GHIST MBIT_ULL(35) /* R12K+ Branch Prediction Global History */395#define MIPS_CPU_BP_GHIST BIT_ULL(35) /* R12K+ Branch Prediction Global History */
401#define MIPS_CPU_SP MBIT_ULL(36) /* Small (1KB) page support */396#define MIPS_CPU_SP BIT_ULL(36) /* Small (1KB) page support */
402#define MIPS_CPU_FTLB MBIT_ULL(37) /* CPU has Fixed-page-size TLB */397#define MIPS_CPU_FTLB BIT_ULL(37) /* CPU has Fixed-page-size TLB */
403#define MIPS_CPU_NAN_LEGACY MBIT_ULL(38) /* Legacy NaN implemented */398#define MIPS_CPU_NAN_LEGACY BIT_ULL(38) /* Legacy NaN implemented */
404#define MIPS_CPU_NAN_2008 MBIT_ULL(39) /* 2008 NaN implemented */399#define MIPS_CPU_NAN_2008 BIT_ULL(39) /* 2008 NaN implemented */
405#define MIPS_CPU_VP MBIT_ULL(40) /* MIPSr6 Virtual Processors (multi-threading) */400#define MIPS_CPU_VP BIT_ULL(40) /* MIPSr6 Virtual Processors (multi-threading) */
406#define MIPS_CPU_LDPTE MBIT_ULL(41) /* CPU has ldpte/lddir instructions */401#define MIPS_CPU_LDPTE BIT_ULL(41) /* CPU has ldpte/lddir instructions */
407#define MIPS_CPU_MVH MBIT_ULL(42) /* CPU supports MFHC0/MTHC0 */402#define MIPS_CPU_MVH BIT_ULL(42) /* CPU supports MFHC0/MTHC0 */
408#define MIPS_CPU_EBASE_WG MBIT_ULL(43) /* CPU has EBase.WG */403#define MIPS_CPU_EBASE_WG BIT_ULL(43) /* CPU has EBase.WG */
409#define MIPS_CPU_BADINSTR MBIT_ULL(44) /* CPU has BadInstr register */404#define MIPS_CPU_BADINSTR BIT_ULL(44) /* CPU has BadInstr register */
410#define MIPS_CPU_BADINSTRP MBIT_ULL(45) /* CPU has BadInstrP register */405#define MIPS_CPU_BADINSTRP BIT_ULL(45) /* CPU has BadInstrP register */
411#define MIPS_CPU_CTXTC MBIT_ULL(46) /* CPU has [X]ConfigContext registers */406#define MIPS_CPU_CTXTC BIT_ULL(46) /* CPU has [X]ConfigContext registers */
412#define MIPS_CPU_PERF MBIT_ULL(47) /* CPU has MIPS performance counters */407#define MIPS_CPU_PERF BIT_ULL(47) /* CPU has MIPS performance counters */
413#define MIPS_CPU_GUESTCTL0EXT MBIT_ULL(48) /* CPU has VZ GuestCtl0Ext register */408#define MIPS_CPU_GUESTCTL0EXT BIT_ULL(48) /* CPU has VZ GuestCtl0Ext register */
414#define MIPS_CPU_GUESTCTL1 MBIT_ULL(49) /* CPU has VZ GuestCtl1 register */409#define MIPS_CPU_GUESTCTL1 BIT_ULL(49) /* CPU has VZ GuestCtl1 register */
415#define MIPS_CPU_GUESTCTL2 MBIT_ULL(50) /* CPU has VZ GuestCtl2 register */410#define MIPS_CPU_GUESTCTL2 BIT_ULL(50) /* CPU has VZ GuestCtl2 register */
416#define MIPS_CPU_GUESTID MBIT_ULL(51) /* CPU uses VZ ASE GuestID feature */411#define MIPS_CPU_GUESTID BIT_ULL(51) /* CPU uses VZ ASE GuestID feature */
417#define MIPS_CPU_DRG MBIT_ULL(52) /* CPU has VZ Direct Root to Guest (DRG) */412#define MIPS_CPU_DRG BIT_ULL(52) /* CPU has VZ Direct Root to Guest (DRG) */
418#define MIPS_CPU_UFR MBIT_ULL(53) /* CPU supports User mode FR switching */413#define MIPS_CPU_UFR BIT_ULL(53) /* CPU supports User mode FR switching */
419#define MIPS_CPU_SHARED_FTLB_RAM \414#define MIPS_CPU_SHARED_FTLB_RAM \
420 MBIT_ULL(54) /* CPU shares FTLB RAM with another */415 BIT_ULL(54) /* CPU shares FTLB RAM with another */
421#define MIPS_CPU_SHARED_FTLB_ENTRIES \416#define MIPS_CPU_SHARED_FTLB_ENTRIES \
422 MBIT_ULL(55) /* CPU shares FTLB entries with another */417 BIT_ULL(55) /* CPU shares FTLB entries with another */
423#define MIPS_CPU_MT_PER_TC_PERF_COUNTERS \418#define MIPS_CPU_MT_PER_TC_PERF_COUNTERS \
424 MBIT_ULL(56) /* CPU has perf counters implemented per TC (MIPSMT ASE) */419 BIT_ULL(56) /* CPU has perf counters implemented per TC (MIPSMT ASE) */
425#define MIPS_CPU_MMID MBIT_ULL(57) /* CPU supports MemoryMapIDs */420#define MIPS_CPU_MMID BIT_ULL(57) /* CPU supports MemoryMapIDs */
426 421
427/*422/*
428 * CPU ASE encodings423 * CPU ASE encodings
arch/mips/include/asm/io.h+11−0
@@ -460,7 +460,12 @@ __BUILD_MEMORY_PFX(, bwlq, type, 0) · 459 unmodified lines
460BUILDIO_MEM(b, u8)460BUILDIO_MEM(b, u8)
461BUILDIO_MEM(w, u16)461BUILDIO_MEM(w, u16)
462BUILDIO_MEM(l, u32)462BUILDIO_MEM(l, u32)
463#ifdef CONFIG_64BIT
463BUILDIO_MEM(q, u64)464BUILDIO_MEM(q, u64)
465#else
466__BUILD_MEMORY_PFX(__raw_, q, u64, 0)
467__BUILD_MEMORY_PFX(__mem_, q, u64, 0)
468#endif
464 469
465#define __BUILD_IOPORT_PFX(bus, bwlq, type) \470#define __BUILD_IOPORT_PFX(bus, bwlq, type) \
466 __BUILD_IOPORT_SINGLE(bus, bwlq, type, 1, 0,) \471 __BUILD_IOPORT_SINGLE(bus, bwlq, type, 1, 0,) \
@@ -486,12 +491,16 @@ __BUILDIO(q, u64) · 19 unmodified lines
486#define readb_relaxed __relaxed_readb491#define readb_relaxed __relaxed_readb
487#define readw_relaxed __relaxed_readw492#define readw_relaxed __relaxed_readw
488#define readl_relaxed __relaxed_readl493#define readl_relaxed __relaxed_readl
494#ifdef CONFIG_64BIT
489#define readq_relaxed __relaxed_readq495#define readq_relaxed __relaxed_readq
496#endif
490 497
491#define writeb_relaxed __relaxed_writeb498#define writeb_relaxed __relaxed_writeb
492#define writew_relaxed __relaxed_writew499#define writew_relaxed __relaxed_writew
493#define writel_relaxed __relaxed_writel500#define writel_relaxed __relaxed_writel
501#ifdef CONFIG_64BIT
494#define writeq_relaxed __relaxed_writeq502#define writeq_relaxed __relaxed_writeq
503#endif
495 504
496#define readb_be(addr) \505#define readb_be(addr) \
497 __raw_readb((__force unsigned *)(addr))506 __raw_readb((__force unsigned *)(addr))
@@ -514,8 +523,10 @@ __BUILDIO(q, u64) · 16 unmodified lines
514/*523/*
515 * Some code tests for these symbols524 * Some code tests for these symbols
516 */525 */
526#ifdef CONFIG_64BIT
517#define readq readq527#define readq readq
518#define writeq writeq528#define writeq writeq
529#endif
519 530
520#define __BUILD_MEMORY_STRING(bwlq, type) \531#define __BUILD_MEMORY_STRING(bwlq, type) \
521 \532 \
arch/mips/include/asm/mach-ralink/pinmux.h+0−1
@@ -1,6 +1,5 @@
1/* SPDX-License-Identifier: GPL-2.0-only */1/* SPDX-License-Identifier: GPL-2.0-only */
2/*2/*
3 *
4 * Copyright (C) 2012 John Crispin <john@phrozen.org>3 * Copyright (C) 2012 John Crispin <john@phrozen.org>
5 */4 */
6 5
arch/mips/jz4740/board-qi_lb60.c+8−8
@@ -466,27 +466,27 @@ static unsigned long pin_cfg_bias_disable[] = { · 465 unmodified lines
466static struct pinctrl_map pin_map[] __initdata = {466static struct pinctrl_map pin_map[] __initdata = {
467 /* NAND pin configuration */467 /* NAND pin configuration */
468 PIN_MAP_MUX_GROUP_DEFAULT("jz4740-nand",468 PIN_MAP_MUX_GROUP_DEFAULT("jz4740-nand",
469 "10010000.jz4740-pinctrl", "nand", "nand-cs1"),469 "10010000.pin-controller", "nand-cs1", "nand"),
470 470
471 /* fbdev pin configuration */471 /* fbdev pin configuration */
472 PIN_MAP_MUX_GROUP("jz4740-fb", PINCTRL_STATE_DEFAULT,472 PIN_MAP_MUX_GROUP("jz4740-fb", PINCTRL_STATE_DEFAULT,
473 "10010000.jz4740-pinctrl", "lcd", "lcd-8bit"),473 "10010000.pin-controller", "lcd-8bit", "lcd"),
474 PIN_MAP_MUX_GROUP("jz4740-fb", PINCTRL_STATE_SLEEP,474 PIN_MAP_MUX_GROUP("jz4740-fb", PINCTRL_STATE_SLEEP,
475 "10010000.jz4740-pinctrl", "lcd", "lcd-no-pins"),475 "10010000.pin-controller", "lcd-no-pins", "lcd"),
476 476
477 /* MMC pin configuration */477 /* MMC pin configuration */
478 PIN_MAP_MUX_GROUP_DEFAULT("jz4740-mmc.0",478 PIN_MAP_MUX_GROUP_DEFAULT("jz4740-mmc.0",
479 "10010000.jz4740-pinctrl", "mmc", "mmc-1bit"),479 "10010000.pin-controller", "mmc-1bit", "mmc"),
480 PIN_MAP_MUX_GROUP_DEFAULT("jz4740-mmc.0",480 PIN_MAP_MUX_GROUP_DEFAULT("jz4740-mmc.0",
481 "10010000.jz4740-pinctrl", "mmc", "mmc-4bit"),481 "10010000.pin-controller", "mmc-4bit", "mmc"),
482 PIN_MAP_CONFIGS_PIN_DEFAULT("jz4740-mmc.0",482 PIN_MAP_CONFIGS_PIN_DEFAULT("jz4740-mmc.0",
483 "10010000.jz4740-pinctrl", "PD0", pin_cfg_bias_disable),483 "10010000.pin-controller", "PD0", pin_cfg_bias_disable),
484 PIN_MAP_CONFIGS_PIN_DEFAULT("jz4740-mmc.0",484 PIN_MAP_CONFIGS_PIN_DEFAULT("jz4740-mmc.0",
485 "10010000.jz4740-pinctrl", "PD2", pin_cfg_bias_disable),485 "10010000.pin-controller", "PD2", pin_cfg_bias_disable),
486 486
487 /* PWM pin configuration */487 /* PWM pin configuration */
488 PIN_MAP_MUX_GROUP_DEFAULT("jz4740-pwm",488 PIN_MAP_MUX_GROUP_DEFAULT("jz4740-pwm",
489 "10010000.jz4740-pinctrl", "pwm4", "pwm4"),489 "10010000.pin-controller", "pwm4", "pwm4"),
490};490};
491 491
492 492
arch/mips/kernel/ftrace.c+12−11
@@ -333,20 +333,21 @@ void prepare_ftrace_return(unsigned long *parent_ra_addr, unsigned long self_ra, · 332 unmodified lines
333 return;333 return;
334 334
335 /*335 /*
336 * "parent_ra_addr" is the stack address saved the return address of336 * "parent_ra_addr" is the stack address where the return address of
337 * the caller of _mcount.337 * the caller of _mcount is saved.
338 *338 *
339 * if the gcc < 4.5, a leaf function does not save the return address339 * If gcc < 4.5, a leaf function does not save the return address
340 * in the stack address, so, we "emulate" one in _mcount's stack space,340 * in the stack address, so we "emulate" one in _mcount's stack space,
341 * and hijack it directly, but for a non-leaf function, it save the341 * and hijack it directly.
342 * return address to the its own stack space, we can not hijack it342 * For a non-leaf function, it does save the return address to its own
343 * directly, but need to find the real stack address,343 * stack space, so we can not hijack it directly, but need to find the
344 * ftrace_get_parent_addr() does it!344 * real stack address, which is done by ftrace_get_parent_addr().
345 *345 *
346 * if gcc>= 4.5, with the new -mmcount-ra-address option, for a346 * If gcc >= 4.5, with the new -mmcount-ra-address option, for a
347 * non-leaf function, the location of the return address will be saved347 * non-leaf function, the location of the return address will be saved
348 * to $12 for us, and for a leaf function, only put a zero into $12. we348 * to $12 for us.
349 * do it in ftrace_graph_caller of mcount.S.349 * For a leaf function, it just puts a zero into $12, so we handle
350 * it in ftrace_graph_caller() of mcount.S.
350 */351 */
351 352
352 /* old_parent_ra = *parent_ra_addr; */353 /* old_parent_ra = *parent_ra_addr; */
arch/mips/kernel/perf_event_mipsxx.c+15−15
@@ -790,15 +790,19 @@ static void reset_counters(void *arg) · 789 unmodified lines
790 case 4:790 case 4:
791 mipsxx_pmu_write_control(3, 0);791 mipsxx_pmu_write_control(3, 0);
792 mipspmu.write_counter(3, 0);792 mipspmu.write_counter(3, 0);
793 /* fall through */
793 case 3:794 case 3:
794 mipsxx_pmu_write_control(2, 0);795 mipsxx_pmu_write_control(2, 0);
795 mipspmu.write_counter(2, 0);796 mipspmu.write_counter(2, 0);
797 /* fall through */
796 case 2:798 case 2:
797 mipsxx_pmu_write_control(1, 0);799 mipsxx_pmu_write_control(1, 0);
798 mipspmu.write_counter(1, 0);800 mipspmu.write_counter(1, 0);
801 /* fall through */
799 case 1:802 case 1:
800 mipsxx_pmu_write_control(0, 0);803 mipsxx_pmu_write_control(0, 0);
801 mipspmu.write_counter(0, 0);804 mipspmu.write_counter(0, 0);
805 /* fall through */
802 }806 }
803}807}
804 808
@@ -1380,7 +1384,7 @@ static int mipsxx_pmu_handle_shared_irq(void) · 575 unmodified lines
1380 struct perf_sample_data data;1384 struct perf_sample_data data;
1381 unsigned int counters = mipspmu.num_counters;1385 unsigned int counters = mipspmu.num_counters;
1382 u64 counter;1386 u64 counter;
1383 int handled = IRQ_NONE;1387 int n, handled = IRQ_NONE;
1384 struct pt_regs *regs;1388 struct pt_regs *regs;
1385 1389
1386 if (cpu_has_perf_cntr_intr_bit && !(read_c0_cause() & CAUSEF_PCI))1390 if (cpu_has_perf_cntr_intr_bit && !(read_c0_cause() & CAUSEF_PCI))
@@ -1401,20 +1405,16 @@ static int mipsxx_pmu_handle_shared_irq(void) · 14 unmodified lines
1401 1405
1402 perf_sample_data_init(&data, 0, 0);1406 perf_sample_data_init(&data, 0, 0);
1403 1407
1404 switch (counters) {1408 for (n = counters - 1; n >= 0; n--) {
1405#define HANDLE_COUNTER(n) \1409 if (!test_bit(n, cpuc->used_mask))
1406 case n + 1: \1410 continue;
1407 if (test_bit(n, cpuc->used_mask)) { \1411
1408 counter = mipspmu.read_counter(n); \1412 counter = mipspmu.read_counter(n);
1409 if (counter & mipspmu.overflow) { \1413 if (!(counter & mipspmu.overflow))
1410 handle_associated_event(cpuc, n, &data, regs); \1414 continue;
1411 handled = IRQ_HANDLED; \1415
1412 } \1416 handle_associated_event(cpuc, n, &data, regs);
1413 }1417 handled = IRQ_HANDLED;
1414 HANDLE_COUNTER(3)
1415 HANDLE_COUNTER(2)
1416 HANDLE_COUNTER(1)
1417 HANDLE_COUNTER(0)
1418 }1418 }
1419 1419
1420#ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS1420#ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
arch/mips/lantiq/irq.c+126−51
@@ -20,13 +20,13 @@ · 19 unmodified lines
20#include <irq.h>20#include <irq.h>
21 21
22/* register definitions - internal irqs */22/* register definitions - internal irqs */
23#define LTQ_ICU_IM0_ISR 0x000023#define LTQ_ICU_ISR 0x0000
24#define LTQ_ICU_IM0_IER 0x000824#define LTQ_ICU_IER 0x0008
25#define LTQ_ICU_IM0_IOSR 0x001025#define LTQ_ICU_IOSR 0x0010
26#define LTQ_ICU_IM0_IRSR 0x001826#define LTQ_ICU_IRSR 0x0018
27#define LTQ_ICU_IM0_IMR 0x002027#define LTQ_ICU_IMR 0x0020
28#define LTQ_ICU_IM1_ISR 0x002828
29#define LTQ_ICU_OFFSET (LTQ_ICU_IM1_ISR - LTQ_ICU_IM0_ISR)29#define LTQ_ICU_IM_SIZE 0x28
30 30
31/* register definitions - external irqs */31/* register definitions - external irqs */
32#define LTQ_EIU_EXIN_C 0x000032#define LTQ_EIU_EXIN_C 0x0000
@@ -46,24 +46,25 @@ · 13 unmodified lines
46 */46 */
47#define LTQ_ICU_EBU_IRQ 2247#define LTQ_ICU_EBU_IRQ 22
48 48
49#define ltq_icu_w32(m, x, y) ltq_w32((x), ltq_icu_membase[m] + (y))49#define ltq_icu_w32(vpe, m, x, y) \
50#define ltq_icu_r32(m, x) ltq_r32(ltq_icu_membase[m] + (x))50 ltq_w32((x), ltq_icu_membase[vpe] + m*LTQ_ICU_IM_SIZE + (y))
51
52#define ltq_icu_r32(vpe, m, x) \
53 ltq_r32(ltq_icu_membase[vpe] + m*LTQ_ICU_IM_SIZE + (x))
51 54
52#define ltq_eiu_w32(x, y) ltq_w32((x), ltq_eiu_membase + (y))55#define ltq_eiu_w32(x, y) ltq_w32((x), ltq_eiu_membase + (y))
53#define ltq_eiu_r32(x) ltq_r32(ltq_eiu_membase + (x))56#define ltq_eiu_r32(x) ltq_r32(ltq_eiu_membase + (x))
54 57
55/* our 2 ipi interrupts for VSMP */
56#define MIPS_CPU_IPI_RESCHED_IRQ 0
57#define MIPS_CPU_IPI_CALL_IRQ 1
58
59/* we have a cascade of 8 irqs */58/* we have a cascade of 8 irqs */
60#define MIPS_CPU_IRQ_CASCADE 859#define MIPS_CPU_IRQ_CASCADE 8
61 60
62static int exin_avail;61static int exin_avail;
63static u32 ltq_eiu_irq[MAX_EIU];62static u32 ltq_eiu_irq[MAX_EIU];
64static void __iomem *ltq_icu_membase[MAX_IM];63static void __iomem *ltq_icu_membase[NR_CPUS];
65static void __iomem *ltq_eiu_membase;64static void __iomem *ltq_eiu_membase;
66static struct irq_domain *ltq_domain;65static struct irq_domain *ltq_domain;
66static DEFINE_SPINLOCK(ltq_eiu_lock);
67static DEFINE_RAW_SPINLOCK(ltq_icu_lock);
67static int ltq_perfcount_irq;68static int ltq_perfcount_irq;
68 69
69int ltq_eiu_get_irq(int exin)70int ltq_eiu_get_irq(int exin)
@@ -75,49 +76,84 @@ int ltq_eiu_get_irq(int exin) · 5 unmodified lines
75 76
76void ltq_disable_irq(struct irq_data *d)77void ltq_disable_irq(struct irq_data *d)
77{78{
78 u32 ier = LTQ_ICU_IM0_IER;79 unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
79 int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;80 unsigned long im = offset / INT_NUM_IM_OFFSET;
80 int im = offset / INT_NUM_IM_OFFSET;81 unsigned long flags;
82 int vpe;
81 83
82 offset %= INT_NUM_IM_OFFSET;84 offset %= INT_NUM_IM_OFFSET;
83 ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);85
86 raw_spin_lock_irqsave(&ltq_icu_lock, flags);
87 for_each_present_cpu(vpe) {
88 ltq_icu_w32(vpe, im,
89 ltq_icu_r32(vpe, im, LTQ_ICU_IER) & ~BIT(offset),
90 LTQ_ICU_IER);
91 }
92 raw_spin_unlock_irqrestore(&ltq_icu_lock, flags);
84}93}
85 94
86void ltq_mask_and_ack_irq(struct irq_data *d)95void ltq_mask_and_ack_irq(struct irq_data *d)
87{96{
88 u32 ier = LTQ_ICU_IM0_IER;97 unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
89 u32 isr = LTQ_ICU_IM0_ISR;98 unsigned long im = offset / INT_NUM_IM_OFFSET;
90 int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;99 unsigned long flags;
91 int im = offset / INT_NUM_IM_OFFSET;100 int vpe;
92 101
93 offset %= INT_NUM_IM_OFFSET;102 offset %= INT_NUM_IM_OFFSET;
94 ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);103
95 ltq_icu_w32(im, BIT(offset), isr);104 raw_spin_lock_irqsave(&ltq_icu_lock, flags);
105 for_each_present_cpu(vpe) {
106 ltq_icu_w32(vpe, im,
107 ltq_icu_r32(vpe, im, LTQ_ICU_IER) & ~BIT(offset),
108 LTQ_ICU_IER);
109 ltq_icu_w32(vpe, im, BIT(offset), LTQ_ICU_ISR);
110 }
111 raw_spin_unlock_irqrestore(&ltq_icu_lock, flags);
96}112}
97 113
98static void ltq_ack_irq(struct irq_data *d)114static void ltq_ack_irq(struct irq_data *d)
99{115{
100 u32 isr = LTQ_ICU_IM0_ISR;116 unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
101 int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;117 unsigned long im = offset / INT_NUM_IM_OFFSET;
102 int im = offset / INT_NUM_IM_OFFSET;118 unsigned long flags;
119 int vpe;
103 120
104 offset %= INT_NUM_IM_OFFSET;121 offset %= INT_NUM_IM_OFFSET;
105 ltq_icu_w32(im, BIT(offset), isr);122
123 raw_spin_lock_irqsave(&ltq_icu_lock, flags);
124 for_each_present_cpu(vpe) {
125 ltq_icu_w32(vpe, im, BIT(offset), LTQ_ICU_ISR);
126 }
127 raw_spin_unlock_irqrestore(&ltq_icu_lock, flags);
106}128}
107 129
108void ltq_enable_irq(struct irq_data *d)130void ltq_enable_irq(struct irq_data *d)
109{131{
110 u32 ier = LTQ_ICU_IM0_IER;132 unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
111 int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;133 unsigned long im = offset / INT_NUM_IM_OFFSET;
112 int im = offset / INT_NUM_IM_OFFSET;134 unsigned long flags;
135 int vpe;
113 136
114 offset %= INT_NUM_IM_OFFSET;137 offset %= INT_NUM_IM_OFFSET;
115 ltq_icu_w32(im, ltq_icu_r32(im, ier) | BIT(offset), ier);138
139 vpe = cpumask_first(irq_data_get_effective_affinity_mask(d));
140
141 /* This shouldn't be even possible, maybe during CPU hotplug spam */
142 if (unlikely(vpe >= nr_cpu_ids))
143 vpe = smp_processor_id();
144
145 raw_spin_lock_irqsave(&ltq_icu_lock, flags);
146
147 ltq_icu_w32(vpe, im, ltq_icu_r32(vpe, im, LTQ_ICU_IER) | BIT(offset),
148 LTQ_ICU_IER);
149
150 raw_spin_unlock_irqrestore(&ltq_icu_lock, flags);
116}151}
117 152
118static int ltq_eiu_settype(struct irq_data *d, unsigned int type)153static int ltq_eiu_settype(struct irq_data *d, unsigned int type)
119{154{
120 int i;155 int i;
156 unsigned long flags;
121 157
122 for (i = 0; i < exin_avail; i++) {158 for (i = 0; i < exin_avail; i++) {
123 if (d->hwirq == ltq_eiu_irq[i]) {159 if (d->hwirq == ltq_eiu_irq[i]) {
@@ -154,8 +190,11 @@ static int ltq_eiu_settype(struct irq_data *d, unsigned int type) · 30 unmodified lines
154 if (edge)190 if (edge)
155 irq_set_handler(d->hwirq, handle_edge_irq);191 irq_set_handler(d->hwirq, handle_edge_irq);
156 192
157 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_C) |193 spin_lock_irqsave(&ltq_eiu_lock, flags);
158 (val << (i * 4)), LTQ_EIU_EXIN_C);194 ltq_eiu_w32((ltq_eiu_r32(LTQ_EIU_EXIN_C) &
195 (~(7 << (i * 4)))) | (val << (i * 4)),
196 LTQ_EIU_EXIN_C);
197 spin_unlock_irqrestore(&ltq_eiu_lock, flags);
159 }198 }
160 }199 }
161 200
@@ -199,6 +238,21 @@ static void ltq_shutdown_eiu_irq(struct irq_data *d) · 37 unmodified lines
199 }238 }
200}239}
201 240
241#if defined(CONFIG_SMP)
242static int ltq_icu_irq_set_affinity(struct irq_data *d,
243 const struct cpumask *cpumask, bool force)
244{
245 struct cpumask tmask;
246
247 if (!cpumask_and(&tmask, cpumask, cpu_online_mask))
248 return -EINVAL;
249
250 irq_data_update_effective_affinity(d, &tmask);
251
252 return IRQ_SET_MASK_OK;
253}
254#endif
255
202static struct irq_chip ltq_irq_type = {256static struct irq_chip ltq_irq_type = {
203 .name = "icu",257 .name = "icu",
204 .irq_enable = ltq_enable_irq,258 .irq_enable = ltq_enable_irq,
@@ -207,6 +261,9 @@ static struct irq_chip ltq_irq_type = { · 2 unmodified lines
207 .irq_ack = ltq_ack_irq,261 .irq_ack = ltq_ack_irq,
208 .irq_mask = ltq_disable_irq,262 .irq_mask = ltq_disable_irq,
209 .irq_mask_ack = ltq_mask_and_ack_irq,263 .irq_mask_ack = ltq_mask_and_ack_irq,
264#if defined(CONFIG_SMP)
265 .irq_set_affinity = ltq_icu_irq_set_affinity,
266#endif
210};267};
211 268
212static struct irq_chip ltq_eiu_type = {269static struct irq_chip ltq_eiu_type = {
@@ -220,15 +277,19 @@ static struct irq_chip ltq_eiu_type = { · 7 unmodified lines
220 .irq_mask = ltq_disable_irq,277 .irq_mask = ltq_disable_irq,
221 .irq_mask_ack = ltq_mask_and_ack_irq,278 .irq_mask_ack = ltq_mask_and_ack_irq,
222 .irq_set_type = ltq_eiu_settype,279 .irq_set_type = ltq_eiu_settype,
280#if defined(CONFIG_SMP)
281 .irq_set_affinity = ltq_icu_irq_set_affinity,
282#endif
223};283};
224 284
225static void ltq_hw_irq_handler(struct irq_desc *desc)285static void ltq_hw_irq_handler(struct irq_desc *desc)
226{286{
227 int module = irq_desc_get_irq(desc) - 2;287 unsigned int module = irq_desc_get_irq(desc) - 2;
228 u32 irq;288 u32 irq;
229 int hwirq;289 irq_hw_number_t hwirq;
290 int vpe = smp_processor_id();
230 291
231 irq = ltq_icu_r32(module, LTQ_ICU_IM0_IOSR);292 irq = ltq_icu_r32(vpe, module, LTQ_ICU_IOSR);
232 if (irq == 0)293 if (irq == 0)
233 return;294 return;
234 295
@@ -249,6 +310,7 @@ static void ltq_hw_irq_handler(struct irq_desc *desc) · 14 unmodified lines
249static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)310static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
250{311{
251 struct irq_chip *chip = &ltq_irq_type;312 struct irq_chip *chip = &ltq_irq_type;
313 struct irq_data *data;
252 int i;314 int i;
253 315
254 if (hw < MIPS_CPU_IRQ_CASCADE)316 if (hw < MIPS_CPU_IRQ_CASCADE)
@@ -258,6 +320,10 @@ static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) · 3 unmodified lines
258 if (hw == ltq_eiu_irq[i])320 if (hw == ltq_eiu_irq[i])
259 chip = &ltq_eiu_type;321 chip = &ltq_eiu_type;
260 322
323 data = irq_get_irq_data(irq);
324
325 irq_data_update_effective_affinity(data, cpumask_of(0));
326
261 irq_set_chip_and_handler(irq, chip, handle_level_irq);327 irq_set_chip_and_handler(irq, chip, handle_level_irq);
262 328
263 return 0;329 return 0;
@@ -272,28 +338,37 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent) · 8 unmodified lines
272{338{
273 struct device_node *eiu_node;339 struct device_node *eiu_node;
274 struct resource res;340 struct resource res;
275 int i, ret;341 int i, ret, vpe;
276 342
277 for (i = 0; i < MAX_IM; i++) {343 /* load register regions of available ICUs */
278 if (of_address_to_resource(node, i, &res))344 for_each_possible_cpu(vpe) {
279 panic("Failed to get icu memory range");345 if (of_address_to_resource(node, vpe, &res))
346 panic("Failed to get icu%i memory range", vpe);
280 347
281 if (!request_mem_region(res.start, resource_size(&res),348 if (!request_mem_region(res.start, resource_size(&res),
282 res.name))349 res.name))
283 pr_err("Failed to request icu memory");350 pr_err("Failed to request icu%i memory\n", vpe);
284 351
285 ltq_icu_membase[i] = ioremap_nocache(res.start,352 ltq_icu_membase[vpe] = ioremap_nocache(res.start,
286 resource_size(&res));353 resource_size(&res));
287 if (!ltq_icu_membase[i])354
288 panic("Failed to remap icu memory");355 if (!ltq_icu_membase[vpe])
356 panic("Failed to remap icu%i memory", vpe);
289 }357 }
290 358
291 /* turn off all irqs by default */359 /* turn off all irqs by default */
292 for (i = 0; i < MAX_IM; i++) {360 for_each_possible_cpu(vpe) {
293 /* make sure all irqs are turned off by default */361 for (i = 0; i < MAX_IM; i++) {
294 ltq_icu_w32(i, 0, LTQ_ICU_IM0_IER);362 /* make sure all irqs are turned off by default */
295 /* clear all possibly pending interrupts */363 ltq_icu_w32(vpe, i, 0, LTQ_ICU_IER);
296 ltq_icu_w32(i, ~0, LTQ_ICU_IM0_ISR);364
365 /* clear all possibly pending interrupts */
366 ltq_icu_w32(vpe, i, ~0, LTQ_ICU_ISR);
367 ltq_icu_w32(vpe, i, ~0, LTQ_ICU_IMR);
368
369 /* clear resend */
370 ltq_icu_w32(vpe, i, 0, LTQ_ICU_IRSR);
371 }
297 }372 }
298 373
299 mips_cpu_irq_init();374 mips_cpu_irq_init();
@@ -347,7 +422,7 @@ unsigned int get_c0_compare_int(void) · 47 unmodified lines
347 return CP0_LEGACY_COMPARE_IRQ;422 return CP0_LEGACY_COMPARE_IRQ;
348}423}
349 424
350static struct of_device_id __initdata of_irq_ids[] = {425static const struct of_device_id of_irq_ids[] __initconst = {
351 { .compatible = "lantiq,icu", .data = icu_of_init },426 { .compatible = "lantiq,icu", .data = icu_of_init },
352 {},427 {},
353};428};
drivers/memory/jz4780-nemc.c+1−1
@@ -61,7 +61,7 @@ struct jz4780_nemc { · 60 unmodified lines
61 *61 *
62 * Return: The number of unique NEMC banks referred to by the specified NEMC62 * Return: The number of unique NEMC banks referred to by the specified NEMC
63 * child device. Unique here means that a device that references the same bank63 * child device. Unique here means that a device that references the same bank
64 * multiple times in the its "reg" property will only count once.64 * multiple times in its "reg" property will only count once.
65 */65 */
66unsigned int jz4780_nemc_num_banks(struct device *dev)66unsigned int jz4780_nemc_num_banks(struct device *dev)
67{67{
drivers/net/fddi/defza.c+1−0
@@ -33,6 +33,7 @@ · 32 unmodified lines
33#include <linux/init.h>33#include <linux/init.h>
34#include <linux/interrupt.h>34#include <linux/interrupt.h>
35#include <linux/io.h>35#include <linux/io.h>
36#include <linux/io-64-nonatomic-lo-hi.h>
36#include <linux/ioport.h>37#include <linux/ioport.h>
37#include <linux/kernel.h>38#include <linux/kernel.h>
38#include <linux/list.h>39#include <linux/list.h>

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