A protected VM accessing ID_AA64ISAR2_EL1 gets punished with an UNDEF, while it really should only get a zero back if the register is not handled by the hypervisor emulation (as mandated by the architecture). Introduce all the missing ID registers (including the unallocated ones), and have them to return 0.
Unified · Split
| @@ -243,15 +243,9 @@ u64 pvm_read_id_reg(const struct kvm_vcpu *vcpu, u32 id) · 242 unmodified lines | ||
| 243 | 243 | case SYS_ID_AA64MMFR2_EL1: |
| 244 | 244 | return get_pvm_id_aa64mmfr2(vcpu); |
| 245 | 245 | default: |
| 246 | − /* | |
| 247 | − * Should never happen because all cases are covered in | |
| 248 | − * pvm_sys_reg_descs[]. | |
| 249 | − */ | |
| 250 | − WARN_ON(1); | |
| 251 | − break; | |
| 246 | + /* Unhandled ID register, RAZ */ | |
| 247 | + return 0; | |
| 252 | 248 | } |
| 253 | − | |
| 254 | − return 0; | |
| 255 | 249 | } |
| 256 | 250 | |
| 257 | 251 | static u64 read_id_reg(const struct kvm_vcpu *vcpu, |
| @@ -332,6 +326,16 @@ static bool pvm_gic_read_sre(struct kvm_vcpu *vcpu, · 74 unmodified lines | ||
| 332 | 326 | /* Mark the specified system register as an AArch64 feature id register. */ |
| 333 | 327 | #define AARCH64(REG) { SYS_DESC(REG), .access = pvm_access_id_aarch64 } |
| 334 | 328 | |
| 329 | +/* | |
| 330 | + * sys_reg_desc initialiser for architecturally unallocated cpufeature ID | |
| 331 | + * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2 | |
| 332 | + * (1 <= crm < 8, 0 <= Op2 < 8). | |
| 333 | + */ | |
| 334 | +#define ID_UNALLOCATED(crm, op2) { \ | |
| 335 | + Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \ | |
| 336 | + .access = pvm_access_id_aarch64, \ | |
| 337 | +} | |
| 338 | + | |
| 335 | 339 | /* Mark the specified system register as Read-As-Zero/Write-Ignored */ |
| 336 | 340 | #define RAZ_WI(REG) { SYS_DESC(REG), .access = pvm_access_raz_wi } |
| 337 | 341 | |
| @@ -375,24 +379,46 @@ static const struct sys_reg_desc pvm_sys_reg_descs[] = { · 37 unmodified lines | ||
| 375 | 379 | AARCH32(SYS_MVFR0_EL1), |
| 376 | 380 | AARCH32(SYS_MVFR1_EL1), |
| 377 | 381 | AARCH32(SYS_MVFR2_EL1), |
| 382 | + ID_UNALLOCATED(3,3), | |
| 378 | 383 | AARCH32(SYS_ID_PFR2_EL1), |
| 379 | 384 | AARCH32(SYS_ID_DFR1_EL1), |
| 380 | 385 | AARCH32(SYS_ID_MMFR5_EL1), |
| 386 | + ID_UNALLOCATED(3,7), | |
| 381 | 387 | |
| 382 | 388 | /* AArch64 ID registers */ |
| 383 | 389 | /* CRm=4 */ |
| 384 | 390 | AARCH64(SYS_ID_AA64PFR0_EL1), |
| 385 | 391 | AARCH64(SYS_ID_AA64PFR1_EL1), |
| 392 | + ID_UNALLOCATED(4,2), | |
| 393 | + ID_UNALLOCATED(4,3), | |
| 386 | 394 | AARCH64(SYS_ID_AA64ZFR0_EL1), |
| 395 | + ID_UNALLOCATED(4,5), | |
| 396 | + ID_UNALLOCATED(4,6), | |
| 397 | + ID_UNALLOCATED(4,7), | |
| 387 | 398 | AARCH64(SYS_ID_AA64DFR0_EL1), |
| 388 | 399 | AARCH64(SYS_ID_AA64DFR1_EL1), |
| 400 | + ID_UNALLOCATED(5,2), | |
| 401 | + ID_UNALLOCATED(5,3), | |
| 389 | 402 | AARCH64(SYS_ID_AA64AFR0_EL1), |
| 390 | 403 | AARCH64(SYS_ID_AA64AFR1_EL1), |
| 404 | + ID_UNALLOCATED(5,6), | |
| 405 | + ID_UNALLOCATED(5,7), | |
| 391 | 406 | AARCH64(SYS_ID_AA64ISAR0_EL1), |
| 392 | 407 | AARCH64(SYS_ID_AA64ISAR1_EL1), |
| 408 | + AARCH64(SYS_ID_AA64ISAR2_EL1), | |
| 409 | + ID_UNALLOCATED(6,3), | |
| 410 | + ID_UNALLOCATED(6,4), | |
| 411 | + ID_UNALLOCATED(6,5), | |
| 412 | + ID_UNALLOCATED(6,6), | |
| 413 | + ID_UNALLOCATED(6,7), | |
| 393 | 414 | AARCH64(SYS_ID_AA64MMFR0_EL1), |
| 394 | 415 | AARCH64(SYS_ID_AA64MMFR1_EL1), |
| 395 | 416 | AARCH64(SYS_ID_AA64MMFR2_EL1), |
| 417 | + ID_UNALLOCATED(7,3), | |
| 418 | + ID_UNALLOCATED(7,4), | |
| 419 | + ID_UNALLOCATED(7,5), | |
| 420 | + ID_UNALLOCATED(7,6), | |
| 421 | + ID_UNALLOCATED(7,7), | |
| 396 | 422 | |
| 397 | 423 | /* Scalable Vector Registers are restricted. */ |
| 398 | 424 | |