lael-labs/linux

Documentation/admin-guide/media/rkisp1.rst+2−2

@@ -86,7 +86,7 @@ the driver through the rkisp_params node to improve image quality during a · 85 unmodified lines
86	video stream.	86	video stream.
87	The buffer format is defined by struct :c:type:`rkisp1_stat_buffer`, and	87	The buffer format is defined by struct :c:type:`rkisp1_stat_buffer`, and
88	userspace should set	88	userspace should set
89	:ref:`V4L2_META_FMT_RK_ISP1_STAT_3A <v4l2-meta-fmt-stat-rkisp1>` as the	89	:ref:`V4L2_META_FMT_RK_ISP1_STAT_3A <v4l2-meta-fmt-rk-isp1-stat-3a>` as the
90	dataformat.	90	dataformat.
91		91
92	.. _rkisp1_params:	92	.. _rkisp1_params:
@@ -100,7 +100,7 @@ and others. · 7 unmodified lines
100		100
101	The buffer format is defined by struct :c:type:`rkisp1_params_cfg`, and	101	The buffer format is defined by struct :c:type:`rkisp1_params_cfg`, and
102	userspace should set	102	userspace should set
103	:ref:`V4L2_META_FMT_RK_ISP1_PARAMS <v4l2-meta-fmt-params-rkisp1>` as the	103	:ref:`V4L2_META_FMT_RK_ISP1_PARAMS <v4l2-meta-fmt-rk-isp1-params>` as the
104	dataformat.	104	dataformat.
105		105
106		106

Documentation/devicetree/bindings/media/allwinner,sun4i-a10-video-engine.yaml+2−0

       - allwinner,sun7i-a20-video-engine
       - allwinner,sun8i-a33-video-engine
       - allwinner,sun8i-h3-video-engine
+      - allwinner,sun8i-v3s-video-engine
+      - allwinner,sun8i-r40-video-engine
       - allwinner,sun50i-a64-video-engine
       - allwinner,sun50i-h5-video-engine
       - allwinner,sun50i-h6-video-engine

Documentation/devicetree/bindings/media/amlogic,axg-ge2d.yaml+47−0

@@ -0,0 +1,47 @@
	1	# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
	2	# Copyright 2020 BayLibre, SAS
	3	%YAML 1.2
	4	---
	5	$id: "http://devicetree.org/schemas/media/amlogic,axg-ge2d.yaml#"
	6	$schema: "http://devicetree.org/meta-schemas/core.yaml#"
	7
	8	title: Amlogic GE2D Acceleration Unit
	9
	10	maintainers:
	11	- Neil Armstrong <narmstrong@baylibre.com>
	12
	13	properties:
	14	compatible:
	15	enum:
	16	- amlogic,axg-ge2d
	17
	18	interrupts:
	19	minItems: 1
	20
	21	reg:
	22	minItems: 1
	23
	24	resets:
	25	maxItems: 1
	26
	27	clocks:
	28	minItems: 1
	29
	30	required:
	31	- compatible
	32	- reg
	33	- interrupts
	34	- clocks
	35	- resets
	36
	37	additionalProperties: false
	38
	39	examples:
	40	- \|
	41	ge2d: ge2d@ff940000 {
	42	compatible = "amlogic,axg-ge2d";
	43	reg = <0xff940000 0x10000>;
	44	interrupts = <150>;
	45	clocks = <&clk_ge2d>;
	46	resets = <&reset_ge2d>;
	47	};

Documentation/devicetree/bindings/media/coda.txt+0−31

@@ -1,31 +0,0 @@
1	Chips&Media Coda multi-standard codec IP
2	========================================
3
4	Coda codec IPs are present in i.MX SoCs in various versions,
5	called VPU (Video Processing Unit).
6
7	Required properties:
8	- compatible : should be "fsl,<chip>-src" for i.MX SoCs:
9	(a) "fsl,imx27-vpu" for CodaDx6 present in i.MX27
10	(b) "fsl,imx51-vpu" for CodaHx4 present in i.MX51
11	(c) "fsl,imx53-vpu" for CODA7541 present in i.MX53
12	(d) "fsl,imx6q-vpu" for CODA960 present in i.MX6q
13	- reg: should be register base and length as documented in the
14	SoC reference manual
15	- interrupts : Should contain the VPU interrupt. For CODA960,
16	a second interrupt is needed for the MJPEG unit.
17	- clocks : Should contain the ahb and per clocks, in the order
18	determined by the clock-names property.
19	- clock-names : Should be "ahb", "per"
20	- iram : phandle pointing to the SRAM device node
21
22	Example:
23
24	vpu: vpu@63ff4000 {
25	compatible = "fsl,imx53-vpu";
26	reg = <0x63ff4000 0x1000>;
27	interrupts = <9>;
28	clocks = <&clks 63>, <&clks 63>;
29	clock-names = "ahb", "per";
30	iram = <&ocram>;
31	};

Documentation/devicetree/bindings/media/coda.yaml+108−0

@@ -0,0 +1,108 @@
	1	# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/media/coda.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: Chips&Media Coda multi-standard codec IP
	8
	9	maintainers:
	10	- Philipp Zabel <p.zabel@pengutronix.de>
	11
	12	description: \|-
	13	Coda codec IPs are present in i.MX SoCs in various versions,
	14	called VPU (Video Processing Unit).
	15
	16	properties:
	17	compatible:
	18	oneOf:
	19	- items:
	20	- const: fsl,imx27-vpu
	21	- const: cnm,codadx6
	22	- items:
	23	- const: fsl,imx51-vpu
	24	- const: cnm,codahx4
	25	- items:
	26	- const: fsl,imx53-vpu
	27	- const: cnm,coda7541
	28	- items:
	29	- enum:
	30	- fsl,imx6dl-vpu
	31	- fsl,imx6q-vpu
	32	- const: cnm,coda960
	33
	34	reg:
	35	maxItems: 1
	36
	37	clocks:
	38	items:
	39	- description: PER clock
	40	- description: AHB interface clock
	41
	42	clock-names:
	43	items:
	44	- const: per
	45	- const: ahb
	46
	47	resets:
	48	maxItems: 1
	49
	50	iram:
	51	$ref: /schemas/types.yaml#/definitions/phandle
	52	description: phandle pointing to the SRAM device node
	53	maxItems: 1
	54
	55	required:
	56	- compatible
	57	- reg
	58	- interrupts
	59	- clocks
	60	- clock-names
	61
	62	allOf:
	63	- if:
	64	properties:
	65	compatible:
	66	contains:
	67	const: cnm,coda960
	68	then:
	69	properties:
	70	interrupts:
	71	items:
	72	- description: BIT processor interrupt
	73	- description: JPEG unit interrupt
	74
	75	interrupt-names:
	76	items:
	77	- const: bit
	78	- const: jpeg
	79	else:
	80	properties:
	81	interrupts:
	82	items:
	83	- description: BIT processor interrupt
	84
	85	- if:
	86	properties:
	87	compatible:
	88	contains:
	89	enum:
	90	- fsl,imx6dl-vpu
	91	- fsl,imx6q-vpu
	92	then:
	93	properties:
	94	power-domains:
	95	$ref: /schemas/types.yaml#/definitions/phandle
	96	description: phandle pointing to the PU power domain
	97	maxItems: 1
	98
	99	examples:
	100	- \|
	101	vpu: video-codec@63ff4000 {
	102	compatible = "fsl,imx53-vpu", "cnm,coda7541";
	103	reg = <0x63ff4000 0x1000>;
	104	interrupts = <9>;
	105	clocks = <&clks 63>, <&clks 63>;
	106	clock-names = "per", "ahb";
	107	iram = <&ocram>;
	108	};

Documentation/devicetree/bindings/media/i2c/adv7604.txt+0−88

@@ -1,88 +0,0 @@
1	* Analog Devices ADV7604/11/12 video decoder with HDMI receiver
2
3	The ADV7604 and ADV7611/12 are multiformat video decoders with an integrated
4	HDMI receiver. The ADV7604 has four multiplexed HDMI inputs and one analog
5	input, and the ADV7611 has one HDMI input and no analog input. The 7612 is
6	similar to the 7611 but has 2 HDMI inputs.
7
8	These device tree bindings support the ADV7611/12 only at the moment.
9
10	Required Properties:
11
12	- compatible: Must contain one of the following
13	- "adi,adv7611" for the ADV7611
14	- "adi,adv7612" for the ADV7612
15
16	- reg: I2C slave addresses
17	The ADV76xx has up to thirteen 256-byte maps that can be accessed via the
18	main I2C ports. Each map has it own I2C address and acts as a standard
19	slave device on the I2C bus. The main address is mandatory, others are
20	optional and revert to defaults if not specified.
21
22	- hpd-gpios: References to the GPIOs that control the HDMI hot-plug
23	detection pins, one per HDMI input. The active flag indicates the GPIO
24	level that enables hot-plug detection.
25
26	The device node must contain one 'port' child node per device input and output
27	port, in accordance with the video interface bindings defined in
28	Documentation/devicetree/bindings/media/video-interfaces.txt. The port nodes
29	are numbered as follows.
30
31	Port ADV7611 ADV7612
32	------------------------------------------------------------
33	HDMI 0 0, 1
34	Digital output 1 2
35
36	The digital output port node must contain at least one endpoint.
37
38	Optional Properties:
39
40	- reset-gpios: Reference to the GPIO connected to the device's reset pin.
41	- default-input: Select which input is selected after reset.
42	- reg-names : Names of maps with programmable addresses.
43	It can contain any map needing a non-default address.
44	Possible maps names are :
45	"main", "avlink", "cec", "infoframe", "esdp", "dpp", "afe",
46	"rep", "edid", "hdmi", "test", "cp", "vdp"
47
48	Optional Endpoint Properties:
49
50	The following three properties are defined in video-interfaces.txt and are
51	valid for source endpoints only.
52
53	- hsync-active: Horizontal synchronization polarity. Defaults to active low.
54	- vsync-active: Vertical synchronization polarity. Defaults to active low.
55	- pclk-sample: Pixel clock polarity. Defaults to output on the falling edge.
56
57	If none of hsync-active, vsync-active and pclk-sample is specified the
58	endpoint will use embedded BT.656 synchronization.
59
60	Example:
61
62	hdmi_receiver@4c {
63	compatible = "adi,adv7611";
64	/*
65	* The edid page will be accessible @ 0x66 on the I2C bus. All
66	* other maps will retain their default addresses.
67	*/
68	reg = <0x4c>, <0x66>;
69	reg-names = "main", "edid";
70
71	reset-gpios = <&ioexp 0 GPIO_ACTIVE_LOW>;
72	hpd-gpios = <&ioexp 2 GPIO_ACTIVE_HIGH>;
73
74	#address-cells = <1>;
75	#size-cells = <0>;
76
77	default-input = <0>;
78
79	port@0 {
80	reg = <0>;
81	};
82	port@1 {
83	reg = <1>;
84	hdmi_in: endpoint {
85	remote-endpoint = <&ccdc_in>;
86	};
87	};
88	};

Documentation/devicetree/bindings/media/i2c/adv7604.yaml+178−0

@@ -0,0 +1,178 @@
	1	# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/media/i2c/adv7604.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: Analog Devices ADV7604/11/12 video decoder with HDMI receiver
	8
	9	maintainers:
	10	- Hans Verkuil <hverkuil-cisco@xs4all.nl>
	11
	12	description:
	13	The ADV7604 and ADV7611/12 are multiformat video decoders with an integrated
	14	HDMI receiver. The ADV7604 has four multiplexed HDMI inputs and one analog
	15	input, and the ADV7611 has one HDMI input and no analog input. The 7612 is
	16	similar to the 7611 but has 2 HDMI inputs.
	17
	18	These device tree bindings support the ADV7611/12 only at the moment.
	19
	20	properties:
	21	compatible:
	22	items:
	23	- enum:
	24	- adi,adv7611
	25	- adi,adv7612
	26
	27	reg:
	28	minItems: 1
	29	maxItems: 13
	30
	31	reg-names:
	32	minItems: 1
	33	maxItems: 13
	34	items:
	35	- const: main
	36	- enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ]
	37	- enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ]
	38	- enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ]
	39	- enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ]
	40	- enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ]
	41	- enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ]
	42	- enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ]
	43	- enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ]
	44	- enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ]
	45	- enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ]
	46	- enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ]
	47	- enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ]
	48
	49	interrupts:
	50	maxItems: 1
	51
	52	reset-gpios:
	53	maxItems: 1
	54
	55	hpd-gpios:
	56	minItems: 1
	57	description:
	58	References to the GPIOs that control the HDMI hot-plug detection pins,
	59	one per HDMI input. The active flag indicates the GPIO level that
	60	enables hot-plug detection.
	61
	62	default-input:
	63	maxItems: 1
	64	description:
	65	Select which input is selected after reset.
	66
	67	ports:
	68	type: object
	69	description:
	70	A node containing input and output port nodes with endpoint definitions
	71	as documented in
	72	Documentation/devicetree/bindings/media/video-interfaces.txt
	73
	74	required:
	75	- compatible
	76	- reg
	77
	78	additionalProperties: false
	79
	80	allOf:
	81	- if:
	82	properties:
	83	compatible:
	84	contains:
	85	const: adi,adv7611
	86	then:
	87	properties:
	88	ports:
	89	properties:
	90	'#address-cells':
	91	const: 1
	92	'#size-cells':
	93	const: 0
	94	port@0:
	95	type: object
	96	description: Input port
	97	port@1:
	98	type: object
	99	description: Output port
	100
	101	required:
	102	- port@1
	103
	104	additionalProperties: false
	105
	106	required:
	107	- ports
	108
	109	- if:
	110	properties:
	111	compatible:
	112	contains:
	113	const: adi,adv7612
	114	then:
	115	properties:
	116	ports:
	117	properties:
	118	'#address-cells':
	119	const: 1
	120	'#size-cells':
	121	const: 0
	122	port@2:
	123	type: object
	124	description: Output port
	125
	126	patternProperties:
	127	"^port@[0-1]$":
	128	type: object
	129	description: Input port
	130
	131	required:
	132	- port@2
	133
	134	additionalProperties: false
	135
	136	required:
	137	- ports
	138
	139	examples:
	140	- \|
	141	#include <dt-bindings/gpio/gpio.h>
	142
	143	i2c {
	144	#address-cells = <1>;
	145	#size-cells = <0>;
	146
	147	hdmi_receiver@4c {
	148	compatible = "adi,adv7611";
	149	/*
	150	* The edid page will be accessible @ 0x66 on the I2C bus. All
	151	* other maps will retain their default addresses.
	152	*/
	153	reg = <0x4c>, <0x66>;
	154	reg-names = "main", "edid";
	155
	156	reset-gpios = <&ioexp 0 GPIO_ACTIVE_LOW>;
	157	hpd-gpios = <&ioexp 2 GPIO_ACTIVE_HIGH>;
	158	default-input = <0>;
	159
	160	ports {
	161	#address-cells = <1>;
	162	#size-cells = <0>;
	163
	164	port@0 {
	165	reg = <0>;
	166	};
	167
	168	port@1 {
	169	reg = <1>;
	170	hdmi_in: endpoint {
	171	remote-endpoint = <&ccdc_in>;
	172	};
	173	};
	174	};
	175
	176
	177	};
	178	};

Documentation/devicetree/bindings/media/i2c/aptina,mt9v111.txt+0−46

@@ -1,46 +0,0 @@
1	* Aptina MT9V111 CMOS sensor
2	----------------------------
3
4	The Aptina MT9V111 is a 1/4-Inch VGA-format digital image sensor with a core
5	based on Aptina MT9V011 sensor and an integrated Image Flow Processor (IFP).
6
7	The sensor has an active pixel array of 640x480 pixels and can output a number
8	of image resolution and formats controllable through a simple two-wires
9	interface.
10
11	Required properties:
12	--------------------
13
14	- compatible: shall be "aptina,mt9v111".
15	- clocks: reference to the system clock input provider.
16
17	Optional properties:
18	--------------------
19
20	- enable-gpios: output enable signal, pin name "OE#". Active low.
21	- standby-gpios: low power state control signal, pin name "STANDBY".
22	Active high.
23	- reset-gpios: chip reset signal, pin name "RESET#". Active low.
24
25	The device node must contain one 'port' child node with one 'endpoint' child
26	sub-node for its digital output video port, in accordance with the video
27	interface bindings defined in:
28	Documentation/devicetree/bindings/media/video-interfaces.txt
29
30	Example:
31	--------
32
33	&i2c1 {
34	camera@48 {
35	compatible = "aptina,mt9v111";
36	reg = <0x48>;
37
38	clocks = <&camera_clk>;
39
40	port {
41	mt9v111_out: endpoint {
42	remote-endpoint = <&ceu_in>;
43	};
44	};
45	};
46	};

Documentation/devicetree/bindings/media/i2c/aptina,mt9v111.yaml+75−0

@@ -0,0 +1,75 @@
	1	# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/media/i2c/aptina,mt9v111.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: Aptina MT9V111 CMOS sensor
	8
	9	maintainers:
	10	- Jacopo Mondi <jacopo@jmondi.org>
	11
	12	description: \|
	13	The Aptina MT9V111 is a 1/4-Inch VGA-format digital image sensor with a core
	14	based on Aptina MT9V011 sensor and an integrated Image Flow Processor (IFP).
	15
	16	The sensor has an active pixel array of 640x480 pixels and can output a number
	17	of image resolutions and formats controllable through a simple two-wires
	18	interface.
	19
	20	properties:
	21	compatible:
	22	const: aptina,mt9v111
	23
	24	reg:
	25	maxItems: 1
	26
	27	clocks:
	28	maxItems: 1
	29
	30	enable-gpios:
	31	description: Enable signal, pin name "OE#". Active low.
	32	maxItems: 1
	33
	34	standby-gpios:
	35	description: \|
	36	Low power state control signal, pin name "STANDBY". Active high.
	37	maxItems: 1
	38
	39	reset-gpios:
	40	description: Chip reset signal, pin name "RESET#". Active low.
	41	maxItems: 1
	42
	43	port:
	44	type: object
	45	description: \|
	46	Output video port. See ../video-interfaces.txt.
	47
	48	required:
	49	- compatible
	50	- reg
	51	- clocks
	52	- port
	53
	54	additionalProperties: false
	55
	56	examples:
	57	- \|
	58	i2c0 {
	59	#address-cells = <1>;
	60	#size-cells = <0>;
	61
	62	camera@48 {
	63	compatible = "aptina,mt9v111";
	64	reg = <0x48>;
	65	clocks = <&camera_clk>;
	66
	67	port {
	68	mt9v111_out: endpoint {
	69	remote-endpoint = <&ceu_in>;
	70	};
	71	};
	72	};
	73	};
	74
	75	...

Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml+135−0

@@ -0,0 +1,135 @@
	1	# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	2	# Copyright (C) 2014--2020 Intel Corporation
	3
	4	$id: http://devicetree.org/schemas/media/i2c/mipi-ccs.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: MIPI CCS, SMIA++ and SMIA compliant camera sensors
	8
	9	maintainers:
	10	- Sakari Ailus <sakari.ailus@linux.intel.com>
	11
	12	description:
	13
	14	CCS (Camera Command Set) is a raw Bayer camera sensor standard defined by the
	15	MIPI Alliance; see
	16	<URL:https://www.mipi.org/specifications/camera-command-set>.
	17
	18	SMIA (Standard Mobile Imaging Architecture) is an image sensor standard
	19	defined jointly by Nokia and ST. SMIA++, defined by Nokia, is an extension of
	20	that.
	21
	22	More detailed documentation can be found in
	23	Documentation/devicetree/bindings/media/video-interfaces.txt .
	24
	25	properties:
	26	compatible:
	27	oneOf:
	28	- items:
	29	- const: mipi-ccs-1.1
	30	- const: mipi-ccs
	31	- items:
	32	- const: mipi-ccs-1.0
	33	- const: mipi-ccs
	34	- const: nokia,smia
	35
	36	reg:
	37	maxItems: 1
	38
	39	vana-supply:
	40	description: Analogue voltage supply (VANA), sensor dependent.
	41	maxItems: 1
	42
	43	vcore-supply:
	44	description: Core voltage supply (VCore), sensor dependent.
	45	maxItems: 1
	46
	47	vio-supply:
	48	description: I/O voltage supply (VIO), sensor dependent.
	49	maxItems: 1
	50
	51	clocks:
	52	description: External clock to the sensor.
	53	maxItems: 1
	54
	55	clock-frequency:
	56	description: Frequency of the external clock to the sensor in Hz.
	57
	58	reset-gpios:
	59	description: Reset GPIO. Also commonly called XSHUTDOWN in hardware
	60	documentation.
	61	maxItems: 1
	62
	63	flash-leds:
	64	description: Flash LED phandles. See ../video-interfaces.txt for details.
	65
	66	lens-focus:
	67	description: Lens focus controller phandles. See ../video-interfaces.txt
	68	for details.
	69
	70	rotation:
	71	description: Rotation of the sensor. See ../video-interfaces.txt for
	72	details.
	73	enum: [ 0, 180 ]
	74
	75	port:
	76	type: object
	77	properties:
	78	endpoint:
	79	type: object
	80	properties:
	81	link-frequencies:
	82	$ref: /schemas/types.yaml#/definitions/uint64-array
	83	description: List of allowed data link frequencies.
	84	data-lanes:
	85	minItems: 1
	86	maxItems: 8
	87	bus-type:
	88	description: The type of the data bus.
	89	oneOf:
	90	- const: 1 # CSI-2 C-PHY
	91	- const: 3 # CCP2
	92	- const: 4 # CSI-2 D-PHY
	93
	94	required:
	95	- link-frequencies
	96	- data-lanes
	97	- bus-type
	98
	99	required:
	100	- compatible
	101	- reg
	102	- clock-frequency
	103	- clocks
	104
	105	additionalProperties: false
	106
	107	examples:
	108	- \|
	109	#include <dt-bindings/gpio/gpio.h>
	110
	111	i2c2 {
	112	#address-cells = <1>;
	113	#size-cells = <0>;
	114
	115	clock-frequency = <400000>;
	116
	117	camera-sensor@10 {
	118	compatible = "mipi-ccs-1.0", "mipi-ccs";
	119	reg = <0x10>;
	120	reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
	121	vana-supply = <&vaux3>;
	122	clocks = <&omap3_isp 0>;
	123	clock-frequency = <9600000>;
	124	port {
	125	ccs_ep: endpoint {
	126	data-lanes = <1 2>;
	127	remote-endpoint = <&csi2a_ep>;
	128	link-frequencies = /bits/ 64 <199200000 210000000
	129	499200000>;
	130	bus-type = <4>;
	131	};
	132	};
	133	};
	134	};
	135	...

Documentation/devicetree/bindings/media/i2c/nokia,smia.txt+0−66

@@ -1,66 +0,0 @@
1	SMIA/SMIA++ sensor
2
3	SMIA (Standard Mobile Imaging Architecture) is an image sensor standard
4	defined jointly by Nokia and ST. SMIA++, defined by Nokia, is an extension
5	of that. These definitions are valid for both types of sensors.
6
7	More detailed documentation can be found in
8	Documentation/devicetree/bindings/media/video-interfaces.txt .
9
10	The device node should contain a "port" node which may contain one or more
11	endpoint nodes, in accordance with video interface bindings defined in
12	Documentation/devicetree/bindings/media/video-interfaces.txt .
13
14	Mandatory properties
15	--------------------
16
17	- compatible: "nokia,smia"
18	- reg: I2C address (0x10, or an alternative address)
19	- vana-supply: Analogue voltage supply (VANA), typically 2,8 volts (sensor
20	dependent).
21	- clocks: External clock to the sensor
22	- clock-frequency: Frequency of the external clock to the sensor
23	- link-frequencies: List of allowed data link frequencies. An array of
24	64-bit elements.
25
26
27	Optional properties
28	-------------------
29
30	- reset-gpios: XSHUTDOWN GPIO
31	- flash-leds: See ../video-interfaces.txt
32	- lens-focus: See ../video-interfaces.txt
33	- rotation: Integer property; valid values are 0 (sensor mounted upright)
34	and 180 (sensor mounted upside down). See
35	../video-interfaces.txt .
36
37
38	Endpoint node mandatory properties
39	----------------------------------
40
41	- data-lanes: <1..n>
42
43
44	Example
45	-------
46
47	&i2c2 {
48	clock-frequency = <400000>;
49
50	camera-sensor@10 {
51	compatible = "nokia,smia";
52	reg = <0x10>;
53	reset-gpios = <&gpio3 20 0>;
54	vana-supply = <&vaux3>;
55	clocks = <&omap3_isp 0>;
56	clock-frequency = <9600000>;
57	nokia,nvm-size = <512>; /* 8 * 64 */
58	link-frequencies = /bits/ 64 <199200000 210000000 499200000>;
59	port {
60	smiapp_ep: endpoint {
61	data-lanes = <1 2>;
62	remote-endpoint = <&csi2a_ep>;
63	};
64	};
65	};
66	};

Documentation/devicetree/bindings/media/i2c/ov2680.txt+0−46

@@ -1,46 +0,0 @@
1	* Omnivision OV2680 MIPI CSI-2 sensor
2
3	Required Properties:
4	- compatible: should be "ovti,ov2680".
5	- clocks: reference to the xvclk input clock.
6	- clock-names: should be "xvclk".
7	- DOVDD-supply: Digital I/O voltage supply.
8	- DVDD-supply: Digital core voltage supply.
9	- AVDD-supply: Analog voltage supply.
10
11	Optional Properties:
12	- reset-gpios: reference to the GPIO connected to the powerdown/reset pin,
13	if any. This is an active low signal to the OV2680.
14
15	The device node must contain one 'port' child node for its digital output
16	video port, and this port must have a single endpoint in accordance with
17	the video interface bindings defined in
18	Documentation/devicetree/bindings/media/video-interfaces.txt.
19
20	Endpoint node required properties for CSI-2 connection are:
21	- remote-endpoint: a phandle to the bus receiver's endpoint node.
22	- clock-lanes: should be set to <0> (clock lane on hardware lane 0).
23	- data-lanes: should be set to <1> (one CSI-2 lane supported).
24
25	Example:
26
27	&i2c2 {
28	ov2680: camera-sensor@36 {
29	compatible = "ovti,ov2680";
30	reg = <0x36>;
31	clocks = <&osc>;
32	clock-names = "xvclk";
33	reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
34	DOVDD-supply = <&sw2_reg>;
35	DVDD-supply = <&sw2_reg>;
36	AVDD-supply = <&reg_peri_3p15v>;
37
38	port {
39	ov2680_to_mipi: endpoint {
40	remote-endpoint = <&mipi_from_sensor>;
41	clock-lanes = <0>;
42	data-lanes = <1>;
43	};
44	};
45	};
46	};

Documentation/devicetree/bindings/media/i2c/ov772x.txt+0−40

@@ -1,40 +0,0 @@
1	* Omnivision OV7720/OV7725 CMOS sensor
2
3	The Omnivision OV7720/OV7725 sensor supports multiple resolutions output,
4	such as VGA, QVGA, and any size scaling down from CIF to 40x30. It also can
5	support the YUV422, RGB565/555/444, GRB422 or raw RGB output formats.
6
7	Required Properties:
8	- compatible: shall be one of
9	"ovti,ov7720"
10	"ovti,ov7725"
11	- clocks: reference to the xclk input clock.
12
13	Optional Properties:
14	- reset-gpios: reference to the GPIO connected to the RSTB pin which is
15	active low, if any.
16	- powerdown-gpios: reference to the GPIO connected to the PWDN pin which is
17	active high, if any.
18
19	The device node shall contain one 'port' child node with one child 'endpoint'
20	subnode for its digital output video port, in accordance with the video
21	interface bindings defined in Documentation/devicetree/bindings/media/
22	video-interfaces.txt.
23
24	Example:
25
26	&i2c0 {
27	ov772x: camera@21 {
28	compatible = "ovti,ov7725";
29	reg = <0x21>;
30	reset-gpios = <&axi_gpio_0 0 GPIO_ACTIVE_LOW>;
31	powerdown-gpios = <&axi_gpio_0 1 GPIO_ACTIVE_LOW>;
32	clocks = <&xclk>;
33
34	port {
35	ov772x_0: endpoint {
36	remote-endpoint = <&vcap1_in0>;
37	};
38	};
39	};
40	};

Documentation/devicetree/bindings/media/i2c/ovti,ov02a10.yaml+159−0

@@ -0,0 +1,159 @@
	1	# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
	2	# Copyright (c) 2020 MediaTek Inc.
	3	%YAML 1.2
	4	---
	5	$id: http://devicetree.org/schemas/media/i2c/ovti,ov02a10.yaml#
	6	$schema: http://devicetree.org/meta-schemas/core.yaml#
	7
	8	title: Omnivision OV02A10 CMOS Sensor Device Tree Bindings
	9
	10	maintainers:
	11	- Dongchun Zhu <dongchun.zhu@mediatek.com>
	12
	13	description: \|-
	14	The Omnivision OV02A10 is a low-cost, high performance, 1/5-inch, 2 megapixel
	15	image sensor, which is the latest production derived from Omnivision's CMOS
	16	image sensor technology. Ihis chip supports high frame rate speeds up to 30fps
	17	@ 1600x1200 (UXGA) resolution transferred over a 1-lane MIPI interface. The
	18	sensor output is available via CSI-2 serial data output.
	19
	20	properties:
	21	compatible:
	22	const: ovti,ov02a10
	23
	24	reg:
	25	maxItems: 1
	26
	27	clocks:
	28	maxItems: 1
	29
	30	clock-names:
	31	description:
	32	External clock for the sensor.
	33	items:
	34	- const: eclk
	35
	36	clock-frequency:
	37	description:
	38	Frequency of the eclk clock in Hz.
	39
	40	dovdd-supply:
	41	description:
	42	Definition of the regulator used as Digital I/O voltage supply.
	43
	44	avdd-supply:
	45	description:
	46	Definition of the regulator used as Analog voltage supply.
	47
	48	dvdd-supply:
	49	description:
	50	Definition of the regulator used as Digital core voltage supply.
	51
	52	powerdown-gpios:
	53	description:
	54	Must be the device tree identifier of the GPIO connected to the
	55	PD_PAD pin. This pin is used to place the OV02A10 into standby mode
	56	or shutdown mode. As the line needs to be high for the powerdown mode
	57	to be active, it should be marked GPIO_ACTIVE_HIGH.
	58	maxItems: 1
	59
	60	reset-gpios:
	61	description:
	62	Must be the device tree identifier of the GPIO connected to the
	63	RST_PD pin. If specified, it will be asserted during driver probe.
	64	As the line needs to be low for the reset to be active, it should be
	65	marked GPIO_ACTIVE_LOW.
	66	maxItems: 1
	67
	68	rotation:
	69	description:
	70	Definition of the sensor's placement.
	71	allOf:
	72	- $ref: "/schemas/types.yaml#/definitions/uint32"
	73	- enum:
	74	- 0 # Sensor Mounted Upright
	75	- 180 # Sensor Mounted Upside Down
	76	default: 0
	77
	78	# See ../video-interfaces.txt for details
	79	port:
	80	type: object
	81	additionalProperties: false
	82	description:
	83	Output port node, single endpoint describing the CSI-2 transmitter.
	84
	85	properties:
	86	endpoint:
	87	type: object
	88	additionalProperties: false
	89
	90	properties:
	91	link-frequencies: true
	92	ovti,mipi-clock-voltage:
	93	allOf:
	94	- $ref: "/schemas/types.yaml#/definitions/uint32"
	95	description:
	96	Definition of MIPI clock voltage unit. This entry corresponds to
	97	the link speed defined by the 'link-frequencies' property.
	98	If present, the value shall be in the range of 0-4.
	99	default: 4
	100	remote-endpoint: true
	101
	102	required:
	103	- link-frequencies
	104	- remote-endpoint
	105
	106	required:
	107	- endpoint
	108
	109	required:
	110	- compatible
	111	- reg
	112	- clocks
	113	- clock-names
	114	- clock-frequency
	115	- dovdd-supply
	116	- avdd-supply
	117	- dvdd-supply
	118	- powerdown-gpios
	119	- reset-gpios
	120	- port
	121
	122	additionalProperties: false
	123
	124	examples:
	125	- \|
	126	#include <dt-bindings/gpio/gpio.h>
	127
	128	i2c {
	129	#address-cells = <1>;
	130	#size-cells = <0>;
	131
	132	ov02a10: camera-sensor@3d {
	133	compatible = "ovti,ov02a10";
	134	reg = <0x3d>;
	135
	136	powerdown-gpios = <&pio 107 GPIO_ACTIVE_HIGH>;
	137	reset-gpios = <&pio 109 GPIO_ACTIVE_LOW>;
	138
	139	clocks = <&ov02a10_clk>;
	140	clock-names = "eclk";
	141	clock-frequency = <24000000>;
	142
	143	rotation = <180>;
	144
	145	dovdd-supply = <&ov02a10_dovdd>;
	146	avdd-supply = <&ov02a10_avdd>;
	147	dvdd-supply = <&ov02a10_dvdd>;
	148
	149	port {
	150	wcam_out: endpoint {
	151	link-frequencies = /bits/ 64 <390000000>;
	152	ovti,mipi-clock-voltage = <3>;
	153	remote-endpoint = <&mipi_in_wcam>;
	154	};
	155	};
	156	};
	157	};
	158
	159	...

Documentation/devicetree/bindings/media/i2c/ovti,ov2680.yaml+99−0

@@ -0,0 +1,99 @@
	1	# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/media/i2c/ovti,ov2680.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: Omnivision OV2680 CMOS Sensor
	8
	9	maintainers:
	10	- Rui Miguel Silva <rmfrfs@gmail.com>
	11
	12	description: \|-
	13	The OV2680 color sensor is a low voltage, high performance 1/5 inch UXGA (2
	14	megapixel) CMOS image sensor that provides a single-chip UXGA (1600 x 1200)
	15	camera. It provides full-frame, sub-sampled, or windowed 10-bit images in
	16	various formats via the control of the Serial Camera Control Bus (SCCB)
	17	interface. The OV2680 has an image array capable of operating at up to 30
	18	frames per second (fps) in UXGA resolution.
	19
	20	properties:
	21	compatible:
	22	const: ovti,ov2680
	23
	24	reg:
	25	maxItems: 1
	26
	27	clocks:
	28	maxItems: 1
	29
	30	clock-names:
	31	const: xvclk
	32
	33	reset-gpios:
	34	description:
	35	The phandle and specifier for the GPIO that controls sensor reset.
	36	This corresponds to the hardware pin XSHUTDOWN which is physically
	37	active low.
	38	maxItems: 1
	39
	40	dovdd-supply:
	41	description:
	42	Definition of the regulator used as interface power supply.
	43
	44	avdd-supply:
	45	description:
	46	Definition of the regulator used as analog power supply.
	47
	48	dvdd-supply:
	49	description:
	50	Definition of the regulator used as digital power supply.
	51
	52	port:
	53	type: object
	54	description:
	55	A node containing an output port node with an endpoint definition
	56	as documented in
	57	Documentation/devicetree/bindings/media/video-interfaces.txt
	58
	59	required:
	60	- compatible
	61	- reg
	62	- clocks
	63	- clock-names
	64	- dovdd-supply
	65	- avdd-supply
	66	- dvdd-supply
	67	- reset-gpios
	68	- port
	69
	70	additionalProperties: false
	71
	72	examples:
	73	- \|
	74	#include <dt-bindings/gpio/gpio.h>
	75
	76	i2c {
	77	#address-cells = <1>;
	78	#size-cells = <0>;
	79
	80	ov2680: camera-sensor@36 {
	81	compatible = "ovti,ov2680";
	82	reg = <0x36>;
	83	clocks = <&osc>;
	84	clock-names = "xvclk";
	85	reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
	86
	87	dovdd-supply = <&sw2_reg>;
	88	dvdd-supply = <&sw2_reg>;
	89	avdd-supply = <&reg_peri_3p15v>;
	90
	91	port {
	92	ov2680_to_mipi: endpoint {
	93	remote-endpoint = <&mipi_from_sensor>;
	94	};
	95	};
	96	};
	97	};
	98
	99	...

Documentation/devicetree/bindings/media/i2c/ovti,ov772x.yaml+134−0

@@ -0,0 +1,134 @@
	1	# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/media/i2c/ovti,ov772x.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: Omnivision OV7720/OV7725 CMOS sensor
	8
	9	maintainers:
	10	- Jacopo Mondi <jacopo@jmondi.org>
	11
	12	description: \|
	13	The Omnivision OV7720/OV7725 sensor supports multiple resolutions output,
	14	such as VGA, QVGA, and any size scaling down from CIF to 40x30. It also can
	15	support the YUV422, RGB565/555/444, GRB422 or raw RGB output formats.
	16
	17	properties:
	18	compatible:
	19	enum:
	20	- ovti,ov7720
	21	- ovti,ov7725
	22
	23	reg:
	24	maxItems: 1
	25
	26	clocks:
	27	maxItems: 1
	28
	29	reset-gpios:
	30	description: \|
	31	Reference to the GPIO connected to the RSTB pin which is active low.
	32	maxItems: 1
	33
	34	powerdown-gpios:
	35	description: \|
	36	Reference to the GPIO connected to the PWDN pin which is active high.
	37	maxItems: 1
	38
	39	port:
	40	type: object
	41	description: \|
	42	Video output port. See ../video-interfaces.txt.
	43
	44	properties:
	45	endpoint:
	46	type: object
	47
	48	properties:
	49	bus-type:
	50	enum: [5, 6]
	51
	52	bus-width:
	53	enum: [8, 10]
	54	default: 10
	55
	56	data-shift:
	57	enum: [0, 2]
	58	default: 0
	59
	60	hsync-active:
	61	enum: [0, 1]
	62	default: 1
	63
	64	vsync-active:
	65	enum: [0, 1]
	66	default: 1
	67
	68	pclk-sample:
	69	enum: [0, 1]
	70	default: 1
	71
	72	allOf:
	73	- if:
	74	properties:
	75	bus-type:
	76	const: 6
	77	then:
	78	properties:
	79	hsync-active: false
	80	vsync-active: false
	81
	82	- if:
	83	properties:
	84	bus-width:
	85	const: 10
	86	then:
	87	properties:
	88	data-shift:
	89	const: 0
	90
	91	required:
	92	- bus-type
	93
	94	unevaluatedProperties: false
	95
	96	additionalProperties: false
	97
	98	required:
	99	- compatible
	100	- reg
	101	- clocks
	102	- port
	103
	104	additionalProperties: false
	105
	106	examples:
	107	- \|
	108	#include <dt-bindings/gpio/gpio.h>
	109
	110	i2c0 {
	111	#address-cells = <1>;
	112	#size-cells = <0>;
	113	ov772x: camera@21 {
	114	compatible = "ovti,ov7725";
	115	reg = <0x21>;
	116	reset-gpios = <&axi_gpio_0 0 GPIO_ACTIVE_LOW>;
	117	powerdown-gpios = <&axi_gpio_0 1 GPIO_ACTIVE_LOW>;
	118	clocks = <&xclk>;
	119
	120	port {
	121	ov772x_0: endpoint {
	122	bus-type = <5>;
	123	vsync-active = <0>;
	124	hsync-active = <0>;
	125	pclk-sample = <0>;
	126	bus-width = <8>;
	127	data-shift = <0>;
	128	remote-endpoint = <&vcap1_in0>;
	129	};
	130	};
	131	};
	132	};
	133
	134	...

Documentation/devicetree/bindings/media/i2c/sony,imx214.txt+0−53

@@ -1,53 +0,0 @@
1	* Sony 1/3.06-Inch 13.13Mp CMOS Digital Image Sensor
2
3	The Sony imx214 is a 1/3.06-inch CMOS active pixel digital image sensor with
4	an active array size of 4224H x 3200V. It is programmable through an I2C
5	interface.
6	Image data is sent through MIPI CSI-2, through 2 or 4 lanes at a maximum
7	throughput of 1.2Gbps/lane.
8
9
10	Required Properties:
11	- compatible: Shall be "sony,imx214".
12	- reg: I2C bus address of the device. Depending on how the sensor is wired,
13	it shall be <0x10> or <0x1a>;
14	- enable-gpios: GPIO descriptor for the enable pin.
15	- vdddo-supply: Chip digital IO regulator (1.8V).
16	- vdda-supply: Chip analog regulator (2.7V).
17	- vddd-supply: Chip digital core regulator (1.12V).
18	- clocks: Reference to the xclk clock.
19	- clock-frequency: Frequency of the xclk clock.
20
21	Optional Properties:
22	- flash-leds: See ../video-interfaces.txt
23	- lens-focus: See ../video-interfaces.txt
24
25	The imx214 device node shall contain one 'port' child node with
26	an 'endpoint' subnode. For further reading on port node refer to
27	Documentation/devicetree/bindings/media/video-interfaces.txt.
28
29	Required Properties on endpoint:
30	- data-lanes: check ../video-interfaces.txt
31	- link-frequencies: check ../video-interfaces.txt
32	- remote-endpoint: check ../video-interfaces.txt
33
34	Example:
35
36	camera-sensor@1a {
37	compatible = "sony,imx214";
38	reg = <0x1a>;
39	vdddo-supply = <&pm8994_lvs1>;
40	vddd-supply = <&camera_vddd_1v12>;
41	vdda-supply = <&pm8994_l17>;
42	lens-focus = <&ad5820>;
43	enable-gpios = <&msmgpio 25 GPIO_ACTIVE_HIGH>;
44	clocks = <&mmcc CAMSS_MCLK0_CLK>;
45	clock-frequency = <24000000>;
46	port {
47	imx214_ep: endpoint {
48	data-lanes = <1 2 3 4>;
49	link-frequencies = /bits/ 64 <480000000>;
50	remote-endpoint = <&csiphy0_ep>;
51	};
52	};
53	};

Documentation/devicetree/bindings/media/i2c/sony,imx214.yaml+133−0

@@ -0,0 +1,133 @@
	1	# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/media/i2c/sony,imx214.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: Sony 1/3.06-Inch 13.13MP CMOS Digital Image Sensor
	8
	9	maintainers:
	10	- Ricardo Ribalda <ribalda@kernel.org>
	11
	12	description: \|
	13	The Sony IMX214 is a 1/3.06-inch CMOS active pixel digital image sensor with
	14	an active array size of 4224H x 3200V. It is programmable through an I2C
	15	interface. Image data is sent through MIPI CSI-2, through 2 or 4 lanes at a
	16	maximum throughput of 1.2Gbps/lane.
	17
	18	properties:
	19	compatible:
	20	const: sony,imx214
	21
	22	reg:
	23	enum:
	24	- 0x10
	25	- 0x1a
	26
	27	clocks:
	28	description: Reference to the xclk clock.
	29	maxItems: 1
	30
	31	clock-frequency:
	32	description: Frequency of the xclk clock in Hz.
	33
	34	enable-gpios:
	35	description: GPIO descriptor for the enable pin.
	36	maxItems: 1
	37
	38	vdddo-supply:
	39	description: Chip digital IO regulator (1.8V).
	40	maxItems: 1
	41
	42	vdda-supply:
	43	description: Chip analog regulator (2.7V).
	44	maxItems: 1
	45
	46	vddd-supply:
	47	description: Chip digital core regulator (1.12V).
	48	maxItems: 1
	49
	50	flash-leds:
	51	description: See ../video-interfaces.txt
	52
	53	lens-focus:
	54	description: See ../video-interfaces.txt
	55
	56	port:
	57	type: object
	58	description: \|
	59	Video output port. See ../video-interfaces.txt.
	60
	61	properties:
	62	endpoint:
	63	type: object
	64
	65	properties:
	66	data-lanes:
	67	$ref: /schemas/types.yaml#/definitions/uint32-array
	68	description: See ../video-interfaces.txt
	69	anyOf:
	70	- items:
	71	- const: 1
	72	- const: 2
	73	- items:
	74	- const: 1
	75	- const: 2
	76	- const: 3
	77	- const: 4
	78
	79	link-frequencies:
	80	$ref: /schemas/types.yaml#/definitions/uint64-array
	81	description: See ../video-interfaces.txt
	82
	83	required:
	84	- data-lanes
	85	- link-frequencies
	86
	87	unevaluatedProperties: false
	88
	89	additionalProperties: false
	90
	91	required:
	92	- compatible
	93	- reg
	94	- clocks
	95	- clock-frequency
	96	- enable-gpios
	97	- vdddo-supply
	98	- vdda-supply
	99	- vddd-supply
	100	- port
	101
	102	additionalProperties: false
	103
	104	examples:
	105	- \|
	106	#include <dt-bindings/gpio/gpio.h>
	107
	108	i2c0 {
	109	#address-cells = <1>;
	110	#size-cells = <0>;
	111
	112	camera-sensor@1a {
	113	compatible = "sony,imx214";
	114	reg = <0x1a>;
	115	vdddo-supply = <&pm8994_lvs1>;
	116	vddd-supply = <&camera_vddd_1v12>;
	117	vdda-supply = <&pm8994_l17>;
	118	lens-focus = <&ad5820>;
	119	enable-gpios = <&msmgpio 25 GPIO_ACTIVE_HIGH>;
	120	clocks = <&camera_clk>;
	121	clock-frequency = <24000000>;
	122
	123	port {
	124	imx214_ep: endpoint {
	125	data-lanes = <1 2 3 4>;
	126	link-frequencies = /bits/ 64 <480000000>;
	127	remote-endpoint = <&csiphy0_ep>;
	128	};
	129	};
	130	};
	131	};
	132
	133	...

Documentation/devicetree/bindings/media/imx7-csi.txt+0−42

@@ -1,42 +0,0 @@
1	Freescale i.MX7 CMOS Sensor Interface
2	=====================================
3
4	csi node
5	--------
6
7	This is device node for the CMOS Sensor Interface (CSI) which enables the chip
8	to connect directly to external CMOS image sensors.
9
10	Required properties:
11
12	- compatible : "fsl,imx7-csi" or "fsl,imx6ul-csi";
13	- reg : base address and length of the register set for the device;
14	- interrupts : should contain CSI interrupt;
15	- clocks : list of clock specifiers, see
16	Documentation/devicetree/bindings/clock/clock-bindings.txt for details;
17	- clock-names : must contain "mclk";
18
19	The device node shall contain one 'port' child node with one child 'endpoint'
20	node, according to the bindings defined in:
21	Documentation/devicetree/bindings/media/video-interfaces.txt.
22
23	In the following example a remote endpoint is a video multiplexer.
24
25	example:
26
27	csi: csi@30710000 {
28	#address-cells = <1>;
29	#size-cells = <0>;
30
31	compatible = "fsl,imx7-csi";
32	reg = <0x30710000 0x10000>;
33	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
34	clocks = <&clks IMX7D_CSI_MCLK_ROOT_CLK>;
35	clock-names = "mclk";
36
37	port {
38	csi_from_csi_mux: endpoint {
39	remote-endpoint = <&csi_mux_to_csi>;
40	};
41	};
42	};

Documentation/devicetree/bindings/media/imx7-mipi-csi2.txt+0−90

@@ -1,90 +0,0 @@
1	Freescale i.MX7 Mipi CSI2
2	=========================
3
4	mipi_csi2 node
5	--------------
6
7	This is the device node for the MIPI CSI-2 receiver core in i.MX7 SoC. It is
8	compatible with previous version of Samsung D-phy.
9
10	Required properties:
11
12	- compatible : "fsl,imx7-mipi-csi2";
13	- reg : base address and length of the register set for the device;
14	- interrupts : should contain MIPI CSIS interrupt;
15	- clocks : list of clock specifiers, see
16	Documentation/devicetree/bindings/clock/clock-bindings.txt for details;
17	- clock-names : must contain "pclk", "wrap" and "phy" entries, matching
18	entries in the clock property;
19	- power-domains : a phandle to the power domain, see
20	Documentation/devicetree/bindings/power/power_domain.txt for details.
21	- reset-names : should include following entry "mrst";
22	- resets : a list of phandle, should contain reset entry of
23	reset-names;
24	- phy-supply : from the generic phy bindings, a phandle to a regulator that
25	provides power to MIPI CSIS core;
26
27	Optional properties:
28
29	- clock-frequency : The IP's main (system bus) clock frequency in Hz, default
30	value when this property is not specified is 166 MHz;
31	- fsl,csis-hs-settle : differential receiver (HS-RX) settle time;
32
33	The device node should contain two 'port' child nodes with one child 'endpoint'
34	node, according to the bindings defined in:
35	Documentation/devicetree/bindings/ media/video-interfaces.txt.
36	The following are properties specific to those nodes.
37
38	port node
39	---------
40
41	- reg : (required) can take the values 0 or 1, where 0 shall be
42	related to the sink port and port 1 shall be the source
43	one;
44
45	endpoint node
46	-------------
47
48	- data-lanes : (required) an array specifying active physical MIPI-CSI2
49	data input lanes and their mapping to logical lanes; this
50	shall only be applied to port 0 (sink port), the array's
51	content is unused only its length is meaningful,
52	in this case the maximum length supported is 2;
53
54	example:
55
56	mipi_csi: mipi-csi@30750000 {
57	#address-cells = <1>;
58	#size-cells = <0>;
59
60	compatible = "fsl,imx7-mipi-csi2";
61	reg = <0x30750000 0x10000>;
62	interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
63	clocks = <&clks IMX7D_IPG_ROOT_CLK>,
64	<&clks IMX7D_MIPI_CSI_ROOT_CLK>,
65	<&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
66	clock-names = "pclk", "wrap", "phy";
67	clock-frequency = <166000000>;
68	power-domains = <&pgc_mipi_phy>;
69	phy-supply = <&reg_1p0d>;
70	resets = <&src IMX7_RESET_MIPI_PHY_MRST>;
71	reset-names = "mrst";
72	fsl,csis-hs-settle = <3>;
73
74	port@0 {
75	reg = <0>;
76
77	mipi_from_sensor: endpoint {
78	remote-endpoint = <&ov2680_to_mipi>;
79	data-lanes = <1>;
80	};
81	};
82
83	port@1 {
84	reg = <1>;
85
86	mipi_vc0_to_csi_mux: endpoint {
87	remote-endpoint = <&csi_mux_from_mipi_vc0>;
88	};
89	};
90	};

Documentation/devicetree/bindings/media/nxp,imx7-csi.yaml+71−0

@@ -0,0 +1,71 @@
	1	# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/media/nxp,imx7-csi.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: i.MX7 CMOS Sensor Interface
	8
	9	maintainers:
	10	- Rui Miguel Silva <rmfrfs@gmail.com>
	11
	12	description: \|
	13	This is device node for the CMOS Sensor Interface (CSI) which enables the
	14	chip to connect directly to external CMOS image sensors.
	15
	16	properties:
	17	compatible:
	18	enum:
	19	- fsl,imx7-csi
	20	- fsl,imx6ul-csi
	21
	22	reg:
	23	maxItems: 1
	24
	25	interrupts:
	26	maxItems: 1
	27
	28	clocks:
	29	maxItems: 1
	30
	31	clock-names:
	32	items:
	33	- const: mclk
	34
	35	port:
	36	type: object
	37	description:
	38	A node containing input port nodes with endpoint definitions as documented
	39	in Documentation/devicetree/bindings/media/video-interfaces.txt
	40
	41	required:
	42	- compatible
	43	- reg
	44	- interrupts
	45	- clocks
	46	- clock-names
	47	- port
	48
	49	additionalProperties: false
	50
	51	examples:
	52	- \|
	53	#include <dt-bindings/clock/imx7d-clock.h>
	54	#include <dt-bindings/interrupt-controller/arm-gic.h>
	55	#include <dt-bindings/interrupt-controller/irq.h>
	56
	57	csi: csi@30710000 {
	58	compatible = "fsl,imx7-csi";
	59	reg = <0x30710000 0x10000>;
	60	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	61	clocks = <&clks IMX7D_CSI_MCLK_ROOT_CLK>;
	62	clock-names = "mclk";
	63
	64	port {
	65	csi_from_csi_mux: endpoint {
	66	remote-endpoint = <&csi_mux_to_csi>;
	67	};
	68	};
	69	};
	70
	71	...

Documentation/devicetree/bindings/media/nxp,imx7-mipi-csi2.yaml+173−0

@@ -0,0 +1,173 @@
	1	# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/media/nxp,imx7-mipi-csi2.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: NXP i.MX7 Mipi CSI2
	8
	9	maintainers:
	10	- Rui Miguel Silva <rmfrfs@gmail.com>
	11
	12	description: \|
	13	This is the device node for the MIPI CSI-2 receiver core in i.MX7 soc. It is
	14	compatible with previous version of samsung d-phy.
	15
	16	properties:
	17	compatible:
	18	const: fsl,imx7-mipi-csi2
	19
	20	reg:
	21	maxItems: 1
	22
	23	interrupts:
	24	maxItems: 1
	25
	26	clocks:
	27	minItems: 3
	28	maxItems: 3
	29
	30	clock-names:
	31	items:
	32	- const: pclk
	33	- const: wrap
	34	- const: phy
	35
	36	power-domains:
	37	maxItems: 1
	38
	39	phy-supply:
	40	description:
	41	Phandle to a regulator that provides power to the PHY. This
	42	regulator will be managed during the PHY power on/off sequence.
	43
	44	resets:
	45	maxItems: 1
	46
	47	reset-names:
	48	const: mrst
	49
	50	clock-frequency:
	51	description:
	52	The IP main (system bus) clock frequency in Hertz
	53	default: 166000000
	54
	55	fsl,csis-hs-settle:
	56	$ref: /schemas/types.yaml#/definitions/uint32
	57	description:
	58	Differential receiver (HS-RX) settle time
	59
	60	ports:
	61	type: object
	62	description:
	63	A node containing input and output port nodes with endpoint definitions
	64	as documented in
	65	Documentation/devicetree/bindings/media/video-interfaces.txt
	66
	67	properties:
	68	'#address-cells':
	69	const: 1
	70
	71	'#size-cells':
	72	const: 0
	73
	74	port@0:
	75	type: object
	76	description:
	77	Input port node, single endpoint describing the CSI-2 transmitter.
	78
	79	properties:
	80	reg:
	81	const: 0
	82
	83	endpoint:
	84	type: object
	85
	86	properties:
	87	data-lanes:
	88	$ref: /schemas/types.yaml#/definitions/uint32-array
	89	description: See ../video-interfaces.txt
	90	oneOf:
	91	- items:
	92	- const: 1
	93	- items:
	94	- const: 1
	95	- const: 2
	96
	97	remote-endpoint: true
	98
	99	required:
	100	- data-lanes
	101	- remote-endpoint
	102
	103	additionalProperties: false
	104
	105	additionalProperties: false
	106
	107	port@1:
	108	type: object
	109	description:
	110	Output port node
	111
	112	required:
	113	- compatible
	114	- reg
	115	- interrupts
	116	- clocks
	117	- clock-names
	118	- power-domains
	119	- phy-supply
	120	- resets
	121	- reset-names
	122	- ports
	123
	124	additionalProperties: false
	125
	126	examples:
	127	- \|
	128	#include <dt-bindings/clock/imx7d-clock.h>
	129	#include <dt-bindings/interrupt-controller/arm-gic.h>
	130	#include <dt-bindings/interrupt-controller/irq.h>
	131	#include <dt-bindings/reset/imx7-reset.h>
	132
	133	mipi_csi: mipi-csi@30750000 {
	134	compatible = "fsl,imx7-mipi-csi2";
	135	reg = <0x30750000 0x10000>;
	136	interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
	137
	138	clocks = <&clks IMX7D_IPG_ROOT_CLK>,
	139	<&clks IMX7D_MIPI_CSI_ROOT_CLK>,
	140	<&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
	141	clock-names = "pclk", "wrap", "phy";
	142	clock-frequency = <166000000>;
	143
	144	power-domains = <&pgc_mipi_phy>;
	145	phy-supply = <&reg_1p0d>;
	146	resets = <&src IMX7_RESET_MIPI_PHY_MRST>;
	147	reset-names = "mrst";
	148	fsl,csis-hs-settle = <3>;
	149
	150	ports {
	151	#address-cells = <1>;
	152	#size-cells = <0>;
	153
	154	port@0 {
	155	reg = <0>;
	156
	157	mipi_from_sensor: endpoint {
	158	remote-endpoint = <&ov2680_to_mipi>;
	159	data-lanes = <1>;
	160	};
	161	};
	162
	163	port@1 {
	164	reg = <1>;
	165
	166	mipi_vc0_to_csi_mux: endpoint {
	167	remote-endpoint = <&csi_mux_from_mipi_vc0>;
	168	};
	169	};
	170	};
	171	};
	172
	173	...

Documentation/devicetree/bindings/media/qcom,camss.txt+7−0

 	Definition: Should contain one of:
 		- "qcom,msm8916-camss"
 		- "qcom,msm8996-camss"
+		- "qcom,sdm660-camss"
 - reg:
 	Usage: required
 	Value type: <prop-encoded-array>
 	Value type: <stringlist>
 	Definition: Should contain the following entries:
 		- "top_ahb"
+		- "throttle_axi"	(660 only)
 		- "ispif_ahb"
 		- "csiphy0_timer"
 		- "csiphy1_timer"
 		- "csiphy2_timer"	(8996 only)
+		- "csiphy_ahb2crif"	(660 only)
 		- "csi0_ahb"
 		- "csi0"
 		- "csi0_phy"
 		- "csi0_pix"
 		- "csi0_rdi"
+		- "cphy_csid0"		(660 only)
 		- "csi1_ahb"
 		- "csi1"
 		- "csi1_phy"
 		- "csi1_pix"
 		- "csi1_rdi"
+		- "cphy_csid1"		(660 only)
 		- "csi2_ahb"		(8996 only)
 		- "csi2"		(8996 only)
 		- "csi2_phy"		(8996 only)
 		- "csi2_pix"		(8996 only)
 		- "csi2_rdi"		(8996 only)
+		- "cphy_csid2"		(660 only)
 		- "csi3_ahb"		(8996 only)
 		- "csi3"		(8996 only)
 		- "csi3_phy"		(8996 only)
 		- "csi3_pix"		(8996 only)
 		- "csi3_rdi"		(8996 only)
+		- "cphy_csid3"		(660 only)
 		- "ahb"
 		- "vfe0"
 		- "csi_vfe0"

Documentation/devicetree/bindings/media/rc.yaml+2−0

       - rc-it913x-v2
       - rc-kaiomy
       - rc-khadas
+      - rc-khamsin
       - rc-kworld-315u
       - rc-kworld-pc150u
       - rc-kworld-plus-tv-analog
       - rc-npgtech
       - rc-odroid
       - rc-pctv-sedna
+      - rc-pine64
       - rc-pinnacle-color
       - rc-pinnacle-grey
       - rc-pinnacle-pctv-hd

Documentation/devicetree/bindings/media/rockchip-isp1.yamlrenamed from drivers/staging/media/rkisp1/Documentation/devicetree/bindings/media/rockchip-isp1.yaml+52−29

   interrupts:
     maxItems: 1
-  iommus:
+  clocks:
-    maxItems: 1
+    minItems: 3
+    items:
+      # isp0 and isp1
+      - description: ISP clock
+      - description: ISP AXI clock
+      - description: ISP AHB clock
+      # only for isp1
+      - description: ISP Pixel clock
-  power-domains:
+  clock-names:
+    minItems: 3
+    items:
+      # isp0 and isp1
+      - const: isp
+      - const: aclk
+      - const: hclk
+      # only for isp1
+      - const: pclk_isp
+  iommus:
     maxItems: 1
   phys:
   phy-names:
     const: dphy
-  clocks:
+  power-domains:
-    items:
+    maxItems: 1
-      - description: ISP clock
-      - description: ISP AXI clock clock
-      - description: ISP AXI clock  wrapper clock
-      - description: ISP AHB clock clock
-      - description: ISP AHB wrapper clock
-  clock-names:
-    items:
-      - const: clk_isp
-      - const: aclk_isp
-      - const: aclk_isp_wrap
-      - const: hclk_isp
-      - const: hclk_isp_wrap
   # See ./video-interfaces.txt for details
   ports:
               remote-endpoint: true
+        required:
+          - reg
+          - "#address-cells"
+          - "#size-cells"
     required:
+      - "#address-cells"
+      - "#size-cells"
       - port@0
 required:
   - compatible
+  - reg
   - interrupts
   - clocks
   - clock-names
-  - power-domains
   - iommus
   - phys
   - phy-names
+  - power-domains
   - ports
+if:
+  properties:
+    compatible:
+      contains:
+        const: rockchip,rk3399-cif-isp
+then:
+  properties:
+    clocks:
+      minItems: 3
+      maxItems: 4
+    clock-names:
+      minItems: 3
+      maxItems: 4
 additionalProperties: false
 examples:
     #include <dt-bindings/interrupt-controller/arm-gic.h>
     #include <dt-bindings/power/rk3399-power.h>
-    parent0: parent@0 {
+    parent0: parent {
         #address-cells = <2>;
         #size-cells = <2>;
             reg = <0x0 0xff910000 0x0 0x4000>;
             interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
             clocks = <&cru SCLK_ISP0>,
-                     <&cru ACLK_ISP0>, <&cru ACLK_ISP0_WRAPPER>,
+                     <&cru ACLK_ISP0_WRAPPER>,
-                     <&cru HCLK_ISP0>, <&cru HCLK_ISP0_WRAPPER>;
+                     <&cru HCLK_ISP0_WRAPPER>;
-            clock-names = "clk_isp",
+            clock-names = "isp", "aclk", "hclk";
-                          "aclk_isp", "aclk_isp_wrap",
-                          "hclk_isp", "hclk_isp_wrap";
-            power-domains = <&power RK3399_PD_ISP0>;
             iommus = <&isp0_mmu>;
             phys = <&dphy>;
             phy-names = "dphy";
+            power-domains = <&power RK3399_PD_ISP0>;
             ports {
                 #address-cells = <1>;
                 #size-cells = <0>;
                 port@0 {
+                    reg = <0>;
                     #address-cells = <1>;
                     #size-cells = <0>;
-                    reg = <0>;
                     mipi_in_wcam: endpoint@0 {
                         reg = <0>;
             };
         };
-        i2c7: i2c@ff160000 {
+        i2c7: i2c {
-            clock-frequency = <400000>;
             #address-cells = <1>;
             #size-cells = <0>;

Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml+38−0

@@ -44,6 +44,43 @@ properties: · 43 unmodified lines
44	bindings defined in	44	bindings defined in
45	Documentation/devicetree/bindings/media/video-interfaces.txt.	45	Documentation/devicetree/bindings/media/video-interfaces.txt.
46		46
		47	properties:
		48	endpoint:
		49	type: object
		50
		51	properties:
		52	bus-type:
		53	enum: [5, 6]
		54	default: 5
		55
		56	bus-width:
		57	enum: [8, 10, 12, 14]
		58	default: 8
		59
		60	remote-endpoint: true
		61
		62	allOf:
		63	- if:
		64	properties:
		65	bus-type:
		66	const: 6
		67
		68	then:
		69	properties:
		70	hsync-active: false
		71	vsync-active: false
		72	bus-width:
		73	enum: [8]
		74
		75	required:
		76	- remote-endpoint
		77	- bus-type
		78	- pclk-sample
		79
		80	unevaluatedProperties: false
		81
		82	additionalProperties: false
		83
47	required:	84	required:
48	- compatible	85	- compatible
49	- reg	86	- reg
@@ -75,6 +112,7 @@ examples: · 25 unmodified lines
75	port {	112	port {
76	dcmi_0: endpoint {	113	dcmi_0: endpoint {
77	remote-endpoint = <&ov5640_0>;	114	remote-endpoint = <&ov5640_0>;
		115	bus-type = <5>;
78	bus-width = <8>;	116	bus-width = <8>;
79	hsync-active = <0>;	117	hsync-active = <0>;
80	vsync-active = <0>;	118	vsync-active = <0>;

Documentation/driver-api/media/camera-sensor.rst+13−0

@@ -132,3 +132,16 @@ used to obtain device's power state after the power state transition: · 131 unmodified lines
132	The function returns a non-zero value if it succeeded getting the power count or	132	The function returns a non-zero value if it succeeded getting the power count or
133	runtime PM was disabled, in either of which cases the driver may proceed to	133	runtime PM was disabled, in either of which cases the driver may proceed to
134	access the device.	134	access the device.
		135
		136	Controls
		137	--------
		138
		139	For camera sensors that are connected to a bus where transmitter and receiver
		140	require common configuration set by drivers, such as CSI-2 or parallel (BT.601
		141	or BT.656) bus, the ``V4L2_CID_LINK_FREQ`` control is mandatory on transmitter
		142	drivers. Receiver drivers can use the ``V4L2_CID_LINK_FREQ`` to query the
		143	frequency used on the bus.
		144
		145	The transmitter drivers should also implement ``V4L2_CID_PIXEL_RATE`` control in
		146	order to tell the maximum pixel rate to the receiver. This is required on raw
		147	camera sensors.

Documentation/driver-api/media/cec-core.rst+2−2

@@ -143,7 +143,7 @@ To enable/disable the 'monitor all' mode:: · 142 unmodified lines
143	int (adap_monitor_all_enable)(struct cec_adapter adap, bool enable);	143	int (adap_monitor_all_enable)(struct cec_adapter adap, bool enable);
144		144
145	If enabled, then the adapter should be put in a mode to also monitor messages	145	If enabled, then the adapter should be put in a mode to also monitor messages
146	that not for us. Not all hardware supports this and this function is only	146	that are not for us. Not all hardware supports this and this function is only
147	called if the CEC_CAP_MONITOR_ALL capability is set. This callback is optional	147	called if the CEC_CAP_MONITOR_ALL capability is set. This callback is optional
148	(some hardware may always be in 'monitor all' mode).	148	(some hardware may always be in 'monitor all' mode).
149		149
@@ -335,7 +335,7 @@ So this must work: · 185 unmodified lines
335	$ cat einj.txt >error-inj	335	$ cat einj.txt >error-inj
336		336
337	The first callback is called when this file is read and it should show the	337	The first callback is called when this file is read and it should show the
338	the current error injection state::	338	current error injection state::
339		339
340	int (error_inj_show)(struct cec_adapter adap, struct seq_file *sf);	340	int (error_inj_show)(struct cec_adapter adap, struct seq_file *sf);
341		341

Documentation/driver-api/media/csi2.rst+3−4

 CSI-2 transmitter.
 The V4L2_CID_LINK_FREQ control is used to tell the receiver driver the
-frequency (and not the symbol rate) of the link. The
+frequency (and not the symbol rate) of the link. The V4L2_CID_PIXEL_RATE
-V4L2_CID_PIXEL_RATE is may be used by the receiver to obtain the pixel
+control may be used by the receiver to obtain the pixel rate the transmitter
-rate the transmitter uses. The
+uses. The :c:type:`v4l2_subdev_video_ops`->s_stream() callback provides an
-:c:type:`v4l2_subdev_video_ops`->s_stream() callback provides an
 ability to start and stop the stream.
 The value of the V4L2_CID_PIXEL_RATE is calculated as follows::

Documentation/driver-api/media/drivers/ccs/ccs-regs.asc+1041−0

@@ -0,0 +1,1041 @@
	1	# SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
	2	# Copyright (C) 2019--2020 Intel Corporation
	3
	4	# register rflags
	5	# - f field LSB MSB rflags
	6	# - e enum value # after a field
	7	# - e enum value [LSB MSB]
	8	# - b bool bit
	9	# - l arg name min max elsize [discontig...]
	10	#
	11	# rflags
	12	# 8, 16, 32 register bits (default is 8)
	13	# v1.1 defined in version 1.1
	14	# f formula
	15	# float_ireal iReal or IEEE 754; 32 bits
	16	# ireal unsigned iReal
	17
	18	# general status registers
	19	module_model_id 0x0000 16
	20	module_revision_number_major 0x0002 8
	21	frame_count 0x0005 8
	22	pixel_order 0x0006 8
	23	- e GRBG 0
	24	- e RGGB 1
	25	- e BGGR 2
	26	- e GBRG 3
	27	MIPI_CCS_version 0x0007 8
	28	- e v1_0 0x10
	29	- e v1_1 0x11
	30	- f major 4 7
	31	- f minor 0 3
	32	data_pedestal 0x0008 16
	33	module_manufacturer_id 0x000e 16
	34	module_revision_number_minor 0x0010 8
	35	module_date_year 0x0012 8
	36	module_date_month 0x0013 8
	37	module_date_day 0x0014 8
	38	module_date_phase 0x0015 8
	39	- f 0 2
	40	- e ts 0
	41	- e es 1
	42	- e cs 2
	43	- e mp 3
	44	sensor_model_id 0x0016 16
	45	sensor_revision_number 0x0018 8
	46	sensor_firmware_version 0x001a 8
	47	serial_number 0x001c 32
	48	sensor_manufacturer_id 0x0020 16
	49	sensor_revision_number_16 0x0022 16
	50
	51	# frame format description registers
	52	frame_format_model_type 0x0040 8
	53	- e 2-byte 1
	54	- e 4-byte 2
	55	frame_format_model_subtype 0x0041 8
	56	- f rows 0 3
	57	- f columns 4 7
	58	frame_format_descriptor(n) 0x0042 16 f
	59	- l n 0 14 2
	60	- f pixels 0 11
	61	- f pcode 12 15
	62	- e embedded 1
	63	- e dummy_pixel 2
	64	- e black_pixel 3
	65	- e dark_pixel 4
	66	- e visible_pixel 5
	67	- e manuf_specific_0 8
	68	- e manuf_specific_1 9
	69	- e manuf_specific_2 10
	70	- e manuf_specific_3 11
	71	- e manuf_specific_4 12
	72	- e manuf_specific_5 13
	73	- e manuf_specific_6 14
	74	frame_format_descriptor_4(n) 0x0060 32 f
	75	- l n 0 7 4
	76	- f pixels 0 15
	77	- f pcode 28 31
	78	- e embedded 1
	79	- e dummy_pixel 2
	80	- e black_pixel 3
	81	- e dark_pixel 4
	82	- e visible_pixel 5
	83	- e manuf_specific_0 8
	84	- e manuf_specific_1 9
	85	- e manuf_specific_2 10
	86	- e manuf_specific_3 11
	87	- e manuf_specific_4 12
	88	- e manuf_specific_5 13
	89	- e manuf_specific_6 14
	90
	91	# analog gain description registers
	92	analog_gain_capability 0x0080 16
	93	- e global 0
	94	- e alternate_global 2
	95	analog_gain_code_min 0x0084 16
	96	analog_gain_code_max 0x0086 16
	97	analog_gain_code_step 0x0088 16
	98	analog_gain_type 0x008a 16
	99	analog_gain_m0 0x008c 16
	100	analog_gain_c0 0x008e 16
	101	analog_gain_m1 0x0090 16
	102	analog_gain_c1 0x0092 16
	103	analog_linear_gain_min 0x0094 16 v1.1
	104	analog_linear_gain_max 0x0096 16 v1.1
	105	analog_linear_gain_step_size 0x0098 16 v1.1
	106	analog_exponential_gain_min 0x009a 16 v1.1
	107	analog_exponential_gain_max 0x009c 16 v1.1
	108	analog_exponential_gain_step_size 0x009e 16 v1.1
	109
	110	# data format description registers
	111	data_format_model_type 0x00c0 8
	112	- e normal 1
	113	- e extended 2
	114	data_format_model_subtype 0x00c1 8
	115	- f rows 0 3
	116	- f columns 4 7
	117	data_format_descriptor(n) 0x00c2 16 f
	118	- l n 0 15 2
	119	- f compressed 0 7
	120	- f uncompressed 8 15
	121
	122	# general set-up registers
	123	mode_select 0x0100 8
	124	- e software_standby 0
	125	- e streaming 1
	126	image_orientation 0x0101 8
	127	- b horizontal_mirror 0
	128	- b vertical_flip 1
	129	software_reset 0x0103 8
	130	- e off 0
	131	- e on 1
	132	grouped_parameter_hold 0x0104 8
	133	mask_corrupted_frames 0x0105 8
	134	- e allow 0
	135	- e mask 1
	136	fast_standby_ctrl 0x0106 8
	137	- e complete_frames 0
	138	- e frame_truncation 1
	139	CCI_address_ctrl 0x0107 8
	140	2nd_CCI_if_ctrl 0x0108 8
	141	- b enable 0
	142	- b ack 1
	143	2nd_CCI_address_ctrl 0x0109 8
	144	CSI_channel_identifier 0x0110 8
	145	CSI_signaling_mode 0x0111 8
	146	- e csi_2_dphy 2
	147	- e csi_2_cphy 3
	148	CSI_data_format 0x0112 16
	149	CSI_lane_mode 0x0114 8
	150	DPCM_Frame_DT 0x011d 8
	151	Bottom_embedded_data_DT 0x011e 8
	152	Bottom_embedded_data_VC 0x011f 8
	153
	154	gain_mode 0x0120 8
	155	- e global 0
	156	- e alternate 1
	157	ADC_bit_depth 0x0121 8
	158	emb_data_ctrl 0x0122 v1.1
	159	- b raw8_packing_for_raw16 0
	160	- b raw10_packing_for_raw20 1
	161	- b raw12_packing_for_raw24 2
	162
	163	GPIO_TRIG_mode 0x0130 8
	164	extclk_frequency_mhz 0x0136 16 ireal
	165	temp_sensor_ctrl 0x0138 8
	166	- b enable 0
	167	temp_sensor_mode 0x0139 8
	168	temp_sensor_output 0x013a 8
	169
	170	# integration time registers
	171	fine_integration_time 0x0200 16
	172	coarse_integration_time 0x0202 16
	173
	174	# analog gain registers
	175	analog_gain_code_global 0x0204 16
	176	analog_linear_gain_global 0x0206 16 v1.1
	177	analog_exponential_gain_global 0x0208 16 v1.1
	178
	179	# digital gain registers
	180	digital_gain_global 0x020e 16
	181
	182	# hdr control registers
	183	Short_analog_gain_global 0x0216 16
	184	Short_digital_gain_global 0x0218 16
	185
	186	HDR_mode 0x0220 8
	187	- b enabled 0
	188	- b separate_analog_gain 1
	189	- b upscaling 2
	190	- b reset_sync 3
	191	- b timing_mode 4
	192	- b exposure_ctrl_direct 5
	193	- b separate_digital_gain 6
	194	HDR_resolution_reduction 0x0221 8
	195	- f row 0 3
	196	- f column 4 7
	197	Exposure_ratio 0x0222 8
	198	HDR_internal_bit_depth 0x0223 8
	199	Direct_short_integration_time 0x0224 16
	200	Short_analog_linear_gain_global 0x0226 16 v1.1
	201	Short_analog_exponential_gain_global 0x0228 16 v1.1
	202
	203	# clock set-up registers
	204	vt_pix_clk_div 0x0300 16
	205	vt_sys_clk_div 0x0302 16
	206	pre_pll_clk_div 0x0304 16
	207	#vt_pre_pll_clk_div 0x0304 16
	208	pll_multiplier 0x0306 16
	209	#vt_pll_multiplier 0x0306 16
	210	op_pix_clk_div 0x0308 16
	211	op_sys_clk_div 0x030a 16
	212	op_pre_pll_clk_div 0x030c 16
	213	op_pll_multiplier 0x031e 16
	214	pll_mode 0x0310 8
	215	- f 0 0
	216	- e single 0
	217	- e dual 1
	218	op_pix_clk_div_rev 0x0312 16 v1.1
	219	op_sys_clk_div_rev 0x0314 16 v1.1
	220
	221	# frame timing registers
	222	frame_length_lines 0x0340 16
	223	line_length_pck 0x0342 16
	224
	225	# image size registers
	226	x_addr_start 0x0344 16
	227	y_addr_start 0x0346 16
	228	x_addr_end 0x0348 16
	229	y_addr_end 0x034a 16
	230	x_output_size 0x034c 16
	231	y_output_size 0x034e 16
	232
	233	# timing mode registers
	234	Frame_length_ctrl 0x0350 8
	235	- b automatic 0
	236	Timing_mode_ctrl 0x0352 8
	237	- b manual_readout 0
	238	- b delayed_exposure 1
	239	Start_readout_rs 0x0353 8
	240	- b manual_readout_start 0
	241	Frame_margin 0x0354 16
	242
	243	# sub-sampling registers
	244	x_even_inc 0x0380 16
	245	x_odd_inc 0x0382 16
	246	y_even_inc 0x0384 16
	247	y_odd_inc 0x0386 16
	248
	249	# monochrome readout registers
	250	monochrome_en 0x0390 v1.1
	251	- e enabled 0
	252
	253	# image scaling registers
	254	Scaling_mode 0x0400 16
	255	- e no_scaling 0
	256	- e horizontal 1
	257	scale_m 0x0404 16
	258	scale_n 0x0406 16
	259	digital_crop_x_offset 0x0408 16
	260	digital_crop_y_offset 0x040a 16
	261	digital_crop_image_width 0x040c 16
	262	digital_crop_image_height 0x040e 16
	263
	264	# image compression registers
	265	compression_mode 0x0500 16
	266	- e none 0
	267	- e dpcm_pcm_simple 1
	268
	269	# test pattern registers
	270	test_pattern_mode 0x0600 16
	271	- e none 0
	272	- e solid_color 1
	273	- e color_bars 2
	274	- e fade_to_grey 3
	275	- e pn9 4
	276	- e color_tile 5
	277	test_data_red 0x0602 16
	278	test_data_greenR 0x0604 16
	279	test_data_blue 0x0606 16
	280	test_data_greenB 0x0608 16
	281	value_step_size_smooth 0x060a 8
	282	value_step_size_quantised 0x060b 8
	283
	284	# phy configuration registers
	285	tclk_post 0x0800 8
	286	ths_prepare 0x0801 8
	287	ths_zero_min 0x0802 8
	288	ths_trail 0x0803 8
	289	tclk_trail_min 0x0804 8
	290	tclk_prepare 0x0805 8
	291	tclk_zero 0x0806 8
	292	tlpx 0x0807 8
	293	phy_ctrl 0x0808 8
	294	- e auto 0
	295	- e UI 1
	296	- e manual 2
	297	tclk_post_ex 0x080a 16
	298	ths_prepare_ex 0x080c 16
	299	ths_zero_min_ex 0x080e 16
	300	ths_trail_ex 0x0810 16
	301	tclk_trail_min_ex 0x0812 16
	302	tclk_prepare_ex 0x0814 16
	303	tclk_zero_ex 0x0816 16
	304	tlpx_ex 0x0818 16
	305
	306	# link rate register
	307	requested_link_rate 0x0820 32 u16.16
	308
	309	# equalization control registers
	310	DPHY_equalization_mode 0x0824 8 v1.1
	311	- b eq2 0
	312	PHY_equalization_ctrl 0x0825 8 v1.1
	313	- b enable 0
	314
	315	# d-phy preamble control registers
	316	DPHY_preamble_ctrl 0x0826 8 v1.1
	317	- b enable 0
	318	DPHY_preamble_length 0x0826 8 v1.1
	319
	320	# d-phy spread spectrum control registers
	321	PHY_SSC_ctrl 0x0828 8 v1.1
	322	- b enable 0
	323
	324	# manual lp control register
	325	manual_LP_ctrl 0x0829 8 v1.1
	326	- b enable 0
	327
	328	# additional phy configuration registers
	329	twakeup 0x082a v1.1
	330	tinit 0x082b v1.1
	331	ths_exit 0x082c v1.1
	332	ths_exit_ex 0x082e 16 v1.1
	333
	334	# phy calibration configuration registers
	335	PHY_periodic_calibration_ctrl 0x0830 8
	336	- b frame_blanking 0
	337	PHY_periodic_calibration_interval 0x0831 8
	338	PHY_init_calibration_ctrl 0x0832 8
	339	- b stream_start 0
	340	DPHY_calibration_mode 0x0833 8 v1.1
	341	- b also_alternate 0
	342	CPHY_calibration_mode 0x0834 8 v1.1
	343	- e format_1 0
	344	- e format_2 1
	345	- e format_3 2
	346	t3_calpreamble_length 0x0835 8 v1.1
	347	t3_calpreamble_length_per 0x0836 8 v1.1
	348	t3_calaltseq_length 0x0837 8 v1.1
	349	t3_calaltseq_length_per 0x0838 8 v1.1
	350	FM2_init_seed 0x083a 16 v1.1
	351	t3_caludefseq_length 0x083c 16 v1.1
	352	t3_caludefseq_length_per 0x083e 16 v1.1
	353
	354	# c-phy manual control registers
	355	TGR_Preamble_Length 0x0841 8
	356	- b preamable_prog_seq 7
	357	- f begin_preamble_length 0 5
	358	TGR_Post_Length 0x0842 8
	359	- f post_length 0 4
	360	TGR_Preamble_Prog_Sequence(n2) 0x0843
	361	- l n2 0 6 1
	362	- f symbol_n_1 3 5
	363	- f symbol_n 0 2
	364	t3_prepare 0x084e 16
	365	t3_lpx 0x0850 16
	366
	367	# alps control register
	368	ALPS_ctrl 0x085a 8
	369	- b lvlp_dphy 0
	370	- b lvlp_cphy 1
	371	- b alp_cphy 2
	372
	373	# lrte control registers
	374	TX_REG_CSI_EPD_EN_SSP_cphy 0x0860 16
	375	TX_REG_CSI_EPD_OP_SLP_cphy 0x0862 16
	376	TX_REG_CSI_EPD_EN_SSP_dphy 0x0864 16
	377	TX_REG_CSI_EPD_OP_SLP_dphy 0x0866 16
	378	TX_REG_CSI_EPD_MISC_OPTION_cphy 0x0868 v1.1
	379	TX_REG_CSI_EPD_MISC_OPTION_dphy 0x0869 v1.1
	380
	381	# scrambling control registers
	382	Scrambling_ctrl 0x0870
	383	- b enabled 0
	384	- f 2 3
	385	- e 1_seed_cphy 0
	386	- e 4_seed_cphy 3
	387	lane_seed_value(seed, lane) 0x0872 16
	388	- l seed 0 3 0x10
	389	- l lane 0 7 0x2
	390
	391	# usl control registers
	392	TX_USL_REV_ENTRY 0x08c0 16 v1.1
	393	TX_USL_REV_Clock_Counter 0x08c2 16 v1.1
	394	TX_USL_REV_LP_Counter 0x08c4 16 v1.1
	395	TX_USL_REV_Frame_Counter 0x08c6 16 v1.1
	396	TX_USL_REV_Chronological_Timer 0x08c8 16 v1.1
	397	TX_USL_FWD_ENTRY 0x08ca 16 v1.1
	398	TX_USL_GPIO 0x08cc 16 v1.1
	399	TX_USL_Operation 0x08ce 16 v1.1
	400	- b reset 0
	401	TX_USL_ALP_ctrl 0x08d0 16 v1.1
	402	- b clock_pause 0
	403	TX_USL_APP_BTA_ACK_TIMEOUT 0x08d2 16 v1.1
	404	TX_USL_SNS_BTA_ACK_TIMEOUT 0x08d2 16 v1.1
	405	USL_Clock_Mode_d_ctrl 0x08d2 v1.1
	406	- b cont_clock_standby 0
	407	- b cont_clock_vblank 1
	408	- b cont_clock_hblank 2
	409
	410	# binning configuration registers
	411	binning_mode 0x0900 8
	412	binning_type 0x0901 8
	413	binning_weighting 0x0902 8
	414
	415	# data transfer interface registers
	416	data_transfer_if_1_ctrl 0x0a00 8
	417	- b enable 0
	418	- b write 1
	419	- b clear_error 2
	420	data_transfer_if_1_status 0x0a01 8
	421	- b read_if_ready 0
	422	- b write_if_ready 1
	423	- b data_corrupted 2
	424	- b improper_if_usage 3
	425	data_transfer_if_1_page_select 0x0a02 8
	426	data_transfer_if_1_data(p) 0x0a04 8 f
	427	- l p 0 63 1
	428
	429	# image processing and sensor correction configuration registers
	430	shading_correction_en 0x0b00 8
	431	- b enable 0
	432	luminance_correction_level 0x0b01 8
	433	green_imbalance_filter_en 0x0b02 8
	434	- b enable 0
	435	mapped_defect_correct_en 0x0b05 8
	436	- b enable 0
	437	single_defect_correct_en 0x0b06 8
	438	- b enable 0
	439	dynamic_couplet_correct_en 0x0b08 8
	440	- b enable 0
	441	combined_defect_correct_en 0x0b0a 8
	442	- b enable 0
	443	module_specific_correction_en 0x0b0c 8
	444	- b enable 0
	445	dynamic_triplet_defect_correct_en 0x0b13 8
	446	- b enable 0
	447	NF_ctrl 0x0b15 8
	448	- b luma 0
	449	- b chroma 1
	450	- b combined 2
	451
	452	# optical black pixel readout registers
	453	OB_readout_control 0x0b30 8
	454	- b enable 0
	455	- b interleaving 1
	456	OB_virtual_channel 0x0b31 8
	457	OB_DT 0x0b32 8
	458	OB_data_format 0x0b33 8
	459
	460	# color temperature feedback registers
	461	color_temperature 0x0b8c 16
	462	absolute_gain_greenr 0x0b8e 16
	463	absolute_gain_red 0x0b90 16
	464	absolute_gain_blue 0x0b92 16
	465	absolute_gain_greenb 0x0b94 16
	466
	467	# cfa conversion registers
	468	CFA_conversion_ctrl 0x0ba0 v1.1
	469	- b bayer_conversion_enable 0
	470
	471	# flash strobe and sa strobe control registers
	472	flash_strobe_adjustment 0x0c12 8
	473	flash_strobe_start_point 0x0c14 16
	474	tflash_strobe_delay_rs_ctrl 0x0c16 16
	475	tflash_strobe_width_high_rs_ctrl 0x0c18 16
	476	flash_mode_rs 0x0c1a 8
	477	- b continuous 0
	478	- b truncate 1
	479	- b async 3
	480	flash_trigger_rs 0x0c1b 8
	481	flash_status 0x0c1c 8
	482	- b retimed 0
	483	sa_strobe_mode 0x0c1d 8
	484	- b continuous 0
	485	- b truncate 1
	486	- b async 3
	487	- b adjust_edge 4
	488	sa_strobe_start_point 0x0c1e 16
	489	tsa_strobe_delay_ctrl 0x0c20 16
	490	tsa_strobe_width_ctrl 0x0c22 16
	491	sa_strobe_trigger 0x0c24 8
	492	sa_strobe_status 0x0c25 8
	493	- b retimed 0
	494	tSA_strobe_re_delay_ctrl 0x0c30 16
	495	tSA_strobe_fe_delay_ctrl 0x0c32 16
	496
	497	# pdaf control registers
	498	PDAF_ctrl 0x0d00 16
	499	- b enable 0
	500	- b processed 1
	501	- b interleaved 2
	502	- b visible_pdaf_correction 3
	503	PDAF_VC 0x0d02 8
	504	PDAF_DT 0x0d03 8
	505	pd_x_addr_start 0x0d04 16
	506	pd_y_addr_start 0x0d06 16
	507	pd_x_addr_end 0x0d08 16
	508	pd_y_addr_end 0x0d0a 16
	509
	510	# bracketing interface configuration registers
	511	bracketing_LUT_ctrl 0x0e00 8
	512	bracketing_LUT_mode 0x0e01 8
	513	- b continue_streaming 0
	514	- b loop_mode 1
	515	bracketing_LUT_entry_ctrl 0x0e02 8
	516	bracketing_LUT_frame(n) 0x0e10 v1.1 f
	517	- l n 0 0xef 1
	518
	519	# integration time and gain parameter limit registers
	520	integration_time_capability 0x1000 16
	521	- b fine 0
	522	coarse_integration_time_min 0x1004 16
	523	coarse_integration_time_max_margin 0x1006 16
	524	fine_integration_time_min 0x1008 16
	525	fine_integration_time_max_margin 0x100a 16
	526
	527	# digital gain parameter limit registers
	528	digital_gain_capability 0x1081
	529	- e none 0
	530	- e global 2
	531	digital_gain_min 0x1084 16
	532	digital_gain_max 0x1086 16
	533	digital_gain_step_size 0x1088 16
	534
	535	# data pedestal capability registers
	536	Pedestal_capability 0x10e0 8 v1.1
	537
	538	# adc capability registers
	539	ADC_capability 0x10f0 8
	540	- b bit_depth_ctrl 0
	541	ADC_bit_depth_capability 0x10f4 32 v1.1
	542
	543	# video timing parameter limit registers
	544	min_ext_clk_freq_mhz 0x1100 32 float_ireal
	545	max_ext_clk_freq_mhz 0x1104 32 float_ireal
	546	min_pre_pll_clk_div 0x1108 16
	547	# min_vt_pre_pll_clk_div 0x1108 16
	548	max_pre_pll_clk_div 0x110a 16
	549	# max_vt_pre_pll_clk_div 0x110a 16
	550	min_pll_ip_clk_freq_mhz 0x110c 32 float_ireal
	551	# min_vt_pll_ip_clk_freq_mhz 0x110c 32 float_ireal
	552	max_pll_ip_clk_freq_mhz 0x1110 32 float_ireal
	553	# max_vt_pll_ip_clk_freq_mhz 0x1110 32 float_ireal
	554	min_pll_multiplier 0x1114 16
	555	# min_vt_pll_multiplier 0x1114 16
	556	max_pll_multiplier 0x1116 16
	557	# max_vt_pll_multiplier 0x1116 16
	558	min_pll_op_clk_freq_mhz 0x1118 32 float_ireal
	559	max_pll_op_clk_freq_mhz 0x111c 32 float_ireal
	560
	561	# video timing set-up capability registers
	562	min_vt_sys_clk_div 0x1120 16
	563	max_vt_sys_clk_div 0x1122 16
	564	min_vt_sys_clk_freq_mhz 0x1124 32 float_ireal
	565	max_vt_sys_clk_freq_mhz 0x1128 32 float_ireal
	566	min_vt_pix_clk_freq_mhz 0x112c 32 float_ireal
	567	max_vt_pix_clk_freq_mhz 0x1130 32 float_ireal
	568	min_vt_pix_clk_div 0x1134 16
	569	max_vt_pix_clk_div 0x1136 16
	570	clock_calculation 0x1138
	571	- b lane_speed 0
	572	- b link_decoupled 1
	573	- b dual_pll_op_sys_ddr 2
	574	- b dual_pll_op_pix_ddr 3
	575	num_of_vt_lanes 0x1139
	576	num_of_op_lanes 0x113a
	577	op_bits_per_lane 0x113b 8 v1.1
	578
	579	# frame timing parameter limits
	580	min_frame_length_lines 0x1140 16
	581	max_frame_length_lines 0x1142 16
	582	min_line_length_pck 0x1144 16
	583	max_line_length_pck 0x1146 16
	584	min_line_blanking_pck 0x1148 16
	585	min_frame_blanking_lines 0x114a 16
	586	min_line_length_pck_step_size 0x114c
	587	timing_mode_capability 0x114d
	588	- b auto_frame_length 0
	589	- b rolling_shutter_manual_readout 2
	590	- b delayed_exposure_start 3
	591	- b manual_exposure_embedded_data 4
	592	frame_margin_max_value 0x114e 16
	593	frame_margin_min_value 0x1150
	594	gain_delay_type 0x1151
	595	- e fixed 0
	596	- e variable 1
	597
	598	# output clock set-up capability registers
	599	min_op_sys_clk_div 0x1160 16
	600	max_op_sys_clk_div 0x1162 16
	601	min_op_sys_clk_freq_mhz 0x1164 32 float_ireal
	602	max_op_sys_clk_freq_mhz 0x1168 32 float_ireal
	603	min_op_pix_clk_div 0x116c 16
	604	max_op_pix_clk_div 0x116e 16
	605	min_op_pix_clk_freq_mhz 0x1170 32 float_ireal
	606	max_op_pix_clk_freq_mhz 0x1174 32 float_ireal
	607
	608	# image size parameter limit registers
	609	x_addr_min 0x1180 16
	610	y_addr_min 0x1182 16
	611	x_addr_max 0x1184 16
	612	y_addr_max 0x1186 16
	613	min_x_output_size 0x1188 16
	614	min_y_output_size 0x118a 16
	615	max_x_output_size 0x118c 16
	616	max_y_output_size 0x118e 16
	617
	618	x_addr_start_div_constant 0x1190 v1.1
	619	y_addr_start_div_constant 0x1191 v1.1
	620	x_addr_end_div_constant 0x1192 v1.1
	621	y_addr_end_div_constant 0x1193 v1.1
	622	x_size_div 0x1194 v1.1
	623	y_size_div 0x1195 v1.1
	624	x_output_div 0x1196 v1.1
	625	y_output_div 0x1197 v1.1
	626	non_flexible_resolution_support 0x1198 v1.1
	627	- b new_pix_addr 0
	628	- b new_output_res 1
	629	- b output_crop_no_pad 2
	630	- b output_size_lane_dep 3
	631
	632	min_op_pre_pll_clk_div 0x11a0 16
	633	max_op_pre_pll_clk_div 0x11a2 16
	634	min_op_pll_ip_clk_freq_mhz 0x11a4 32 float_ireal
	635	max_op_pll_ip_clk_freq_mhz 0x11a8 32 float_ireal
	636	min_op_pll_multiplier 0x11ac 16
	637	max_op_pll_multiplier 0x11ae 16
	638	min_op_pll_op_clk_freq_mhz 0x11b0 32 float_ireal
	639	max_op_pll_op_clk_freq_mhz 0x11b4 32 float_ireal
	640	clock_tree_pll_capability 0x11b8 8
	641	- b dual_pll 0
	642	- b single_pll 1
	643	- b ext_divider 2
	644	- b flexible_op_pix_clk_div 3
	645	clock_capa_type_capability 0x11b9 v1.1
	646	- b ireal 0
	647
	648	# sub-sampling parameters limit registers
	649	min_even_inc 0x11c0 16
	650	min_odd_inc 0x11c2 16
	651	max_even_inc 0x11c4 16
	652	max_odd_inc 0x11c6 16
	653	aux_subsamp_capability 0x11c8 v1.1
	654	- b factor_power_of_2 1
	655	aux_subsamp_mono_capability 0x11c9 v1.1
	656	- b factor_power_of_2 1
	657	monochrome_capability 0x11ca v1.1
	658	- e inc_odd 0
	659	- e inc_even 1
	660	pixel_readout_capability 0x11cb v1.1
	661	- e bayer 0
	662	- e monochrome 1
	663	- e bayer_and_mono 2
	664	min_even_inc_mono 0x11cc 16 v1.1
	665	max_even_inc_mono 0x11ce 16 v1.1
	666	min_odd_inc_mono 0x11d0 16 v1.1
	667	max_odd_inc_mono 0x11d2 16 v1.1
	668	min_even_inc_bc2 0x11d4 16 v1.1
	669	max_even_inc_bc2 0x11d6 16 v1.1
	670	min_odd_inc_bc2 0x11d8 16 v1.1
	671	max_odd_inc_bc2 0x11da 16 v1.1
	672	min_even_inc_mono_bc2 0x11dc 16 v1.1
	673	max_even_inc_mono_bc2 0x11de 16 v1.1
	674	min_odd_inc_mono_bc2 0x11f0 16 v1.1
	675	max_odd_inc_mono_bc2 0x11f2 16 v1.1
	676
	677	# image scaling limit parameters
	678	scaling_capability 0x1200 16
	679	- e none 0
	680	- e horizontal 1
	681	- e reserved 2
	682	scaler_m_min 0x1204 16
	683	scaler_m_max 0x1206 16
	684	scaler_n_min 0x1208 16
	685	scaler_n_max 0x120a 16
	686	digital_crop_capability 0x120e
	687	- e none 0
	688	- e input_crop 1
	689
	690	# hdr limit registers
	691	hdr_capability_1 0x1210
	692	- b 2x2_binning 0
	693	- b combined_analog_gain 1
	694	- b separate_analog_gain 2
	695	- b upscaling 3
	696	- b reset_sync 4
	697	- b direct_short_exp_timing 5
	698	- b direct_short_exp_synthesis 6
	699	min_hdr_bit_depth 0x1211
	700	hdr_resolution_sub_types 0x1212
	701	hdr_resolution_sub_type(n) 0x1213
	702	- l n 0 1 1
	703	- f row 0 3
	704	- f column 4 7
	705	hdr_capability_2 0x121b
	706	- b combined_digital_gain 0
	707	- b separate_digital_gain 1
	708	- b timing_mode 3
	709	- b synthesis_mode 4
	710	max_hdr_bit_depth 0x121c
	711
	712	# usl capability register
	713	usl_support_capability 0x1230 v1.1
	714	- b clock_tree 0
	715	- b rev_clock_tree 1
	716	- b rev_clock_calc 2
	717	usl_clock_mode_d_capability 0x1231 v1.1
	718	- b cont_clock_standby 0
	719	- b cont_clock_vblank 1
	720	- b cont_clock_hblank 2
	721	- b noncont_clock_standby 3
	722	- b noncont_clock_vblank 4
	723	- b noncont_clock_hblank 5
	724	min_op_sys_clk_div_rev 0x1234 v1.1
	725	max_op_sys_clk_div_rev 0x1236 v1.1
	726	min_op_pix_clk_div_rev 0x1238 v1.1
	727	max_op_pix_clk_div_rev 0x123a v1.1
	728	min_op_sys_clk_freq_rev_mhz 0x123c 32 v1.1 float_ireal
	729	max_op_sys_clk_freq_rev_mhz 0x1240 32 v1.1 float_ireal
	730	min_op_pix_clk_freq_rev_mhz 0x1244 32 v1.1 float_ireal
	731	max_op_pix_clk_freq_rev_mhz 0x1248 32 v1.1 float_ireal
	732	max_bitrate_rev_d_mode_mbps 0x124c 32 v1.1 ireal
	733	max_symrate_rev_c_mode_msps 0x1250 32 v1.1 ireal
	734
	735	# image compression capability registers
	736	compression_capability 0x1300
	737	- b dpcm_pcm_simple 0
	738
	739	# test mode capability registers
	740	test_mode_capability 0x1310 16
	741	- b solid_color 0
	742	- b color_bars 1
	743	- b fade_to_grey 2
	744	- b pn9 3
	745	- b color_tile 5
	746	pn9_data_format1 0x1312
	747	pn9_data_format2 0x1313
	748	pn9_data_format3 0x1314
	749	pn9_data_format4 0x1315
	750	pn9_misc_capability 0x1316
	751	- f num_pixels 0 2
	752	- b compression 3
	753	test_pattern_capability 0x1317 v1.1
	754	- b no_repeat 1
	755	pattern_size_div_m1 0x1318 v1.1
	756
	757	# fifo capability registers
	758	fifo_support_capability 0x1502
	759	- e none 0
	760	- e derating 1
	761	- e derating_overrating 2
	762
	763	# csi-2 capability registers
	764	phy_ctrl_capability 0x1600
	765	- b auto_phy_ctl 0
	766	- b ui_phy_ctl 1
	767	- b dphy_time_ui_reg_1_ctl 2
	768	- b dphy_time_ui_reg_2_ctl 3
	769	- b dphy_time_ctl 4
	770	- b dphy_ext_time_ui_reg_1_ctl 5
	771	- b dphy_ext_time_ui_reg_2_ctl 6
	772	- b dphy_ext_time_ctl 7
	773	csi_dphy_lane_mode_capability 0x1601
	774	- b 1_lane 0
	775	- b 2_lane 1
	776	- b 3_lane 2
	777	- b 4_lane 3
	778	- b 5_lane 4
	779	- b 6_lane 5
	780	- b 7_lane 6
	781	- b 8_lane 7
	782	csi_signaling_mode_capability 0x1602
	783	- b csi_dphy 2
	784	- b csi_cphy 3
	785	fast_standby_capability 0x1603
	786	- e no_frame_truncation 0
	787	- e frame_truncation 1
	788	csi_address_control_capability 0x1604
	789	- b cci_addr_change 0
	790	- b 2nd_cci_addr 1
	791	- b sw_changeable_2nd_cci_addr 2
	792	data_type_capability 0x1605
	793	- b dpcm_programmable 0
	794	- b bottom_embedded_dt_programmable 1
	795	- b bottom_embedded_vc_programmable 2
	796	- b ext_vc_range 3
	797	csi_cphy_lane_mode_capability 0x1606
	798	- b 1_lane 0
	799	- b 2_lane 1
	800	- b 3_lane 2
	801	- b 4_lane 3
	802	- b 5_lane 4
	803	- b 6_lane 5
	804	- b 7_lane 6
	805	- b 8_lane 7
	806	emb_data_capability 0x1607 v1.1
	807	- b two_bytes_per_raw16 0
	808	- b two_bytes_per_raw20 1
	809	- b two_bytes_per_raw24 2
	810	- b no_one_byte_per_raw16 3
	811	- b no_one_byte_per_raw20 4
	812	- b no_one_byte_per_raw24 5
	813	max_per_lane_bitrate_lane_d_mode_mbps(n) 0x1608 32 ireal
	814	- l n 0 7 4 4,0x32
	815	temp_sensor_capability 0x1618
	816	- b supported 0
	817	- b CCS_format 1
	818	- b reset_0x80 2
	819	max_per_lane_bitrate_lane_c_mode_mbps(n) 0x161a 32 ireal
	820	- l n 0 7 4 4,0x30
	821	dphy_equalization_capability 0x162b
	822	- b equalization_ctrl 0
	823	- b eq1 1
	824	- b eq2 2
	825	cphy_equalization_capability 0x162c
	826	- b equalization_ctrl 0
	827	dphy_preamble_capability 0x162d
	828	- b preamble_seq_ctrl 0
	829	dphy_ssc_capability 0x162e
	830	- b supported 0
	831	cphy_calibration_capability 0x162f
	832	- b manual 0
	833	- b manual_streaming 1
	834	- b format_1_ctrl 2
	835	- b format_2_ctrl 3
	836	- b format_3_ctrl 4
	837	dphy_calibration_capability 0x1630
	838	- b manual 0
	839	- b manual_streaming 1
	840	- b alternate_seq 2
	841	phy_ctrl_capability_2 0x1631
	842	- b tgr_length 0
	843	- b tgr_preamble_prog_seq 1
	844	- b extra_cphy_manual_timing 2
	845	- b clock_based_manual_cdphy 3
	846	- b clock_based_manual_dphy 4
	847	- b clock_based_manual_cphy 5
	848	- b manual_lp_dphy 6
	849	- b manual_lp_cphy 7
	850	lrte_cphy_capability 0x1632
	851	- b pdq_short 0
	852	- b spacer_short 1
	853	- b pdq_long 2
	854	- b spacer_long 3
	855	- b spacer_no_pdq 4
	856	lrte_dphy_capability 0x1633
	857	- b pdq_short_opt1 0
	858	- b spacer_short_opt1 1
	859	- b pdq_long_opt1 2
	860	- b spacer_long_opt1 3
	861	- b spacer_short_opt2 4
	862	- b spacer_long_opt2 5
	863	- b spacer_no_pdq_opt1 6
	864	- b spacer_variable_opt2 7
	865	alps_capability_dphy 0x1634
	866	- e lvlp_not_supported 0 0x3
	867	- e lvlp_supported 1 0x3
	868	- e controllable_lvlp 2 0x3
	869	alps_capability_cphy 0x1635
	870	- e lvlp_not_supported 0 0x3
	871	- e lvlp_supported 1 0x3
	872	- e controllable_lvlp 2 0x3
	873	- e alp_not_supported 0xc 0xc
	874	- e alp_supported 0xd 0xc
	875	- e controllable_alp 0xe 0xc
	876	scrambling_capability 0x1636
	877	- b scrambling_supported 0
	878	- f max_seeds_per_lane_c 1 2
	879	- e 1 0
	880	- e 4 3
	881	- f num_seed_regs 3 5
	882	- e 0 0
	883	- e 1 1
	884	- e 4 4
	885	- b num_seed_per_lane 6
	886	dphy_manual_constant 0x1637
	887	cphy_manual_constant 0x1638
	888	CSI2_interface_capability_misc 0x1639 v1.1
	889	- b eotp_short_pkt_opt2 0
	890	PHY_ctrl_capability_3 0x165c v1.1
	891	- b dphy_timing_not_multiple 0
	892	- b dphy_min_timing_value_1 1
	893	- b twakeup_supported 2
	894	- b tinit_supported 3
	895	- b ths_exit_supported 4
	896	- b cphy_timing_not_multiple 5
	897	- b cphy_min_timing_value_1 6
	898	dphy_sf 0x165d v1.1
	899	cphy_sf 0x165e v1.1
	900	- f twakeup 0 3
	901	- f tinit 4 7
	902	dphy_limits_1 0x165f v1.1
	903	- f ths_prepare 0 3
	904	- f ths_zero 4 7
	905	dphy_limits_2 0x1660 v1.1
	906	- f ths_trail 0 3
	907	- f tclk_trail_min 4 7
	908	dphy_limits_3 0x1661 v1.1
	909	- f tclk_prepare 0 3
	910	- f tclk_zero 4 7
	911	dphy_limits_4 0x1662 v1.1
	912	- f tclk_post 0 3
	913	- f tlpx 4 7
	914	dphy_limits_5 0x1663 v1.1
	915	- f ths_exit 0 3
	916	- f twakeup 4 7
	917	dphy_limits_6 0x1664 v1.1
	918	- f tinit 0 3
	919	cphy_limits_1 0x1665 v1.1
	920	- f t3_prepare_max 0 3
	921	- f t3_lpx_max 4 7
	922	cphy_limits_2 0x1666 v1.1
	923	- f ths_exit_max 0 3
	924	- f twakeup_max 4 7
	925	cphy_limits_3 0x1667 v1.1
	926	- f tinit_max 0 3
	927
	928	# binning capability registers
	929	min_frame_length_lines_bin 0x1700 16
	930	max_frame_length_lines_bin 0x1702 16
	931	min_line_length_pck_bin 0x1704 16
	932	max_line_length_pck_bin 0x1706 16
	933	min_line_blanking_pck_bin 0x1708 16
	934	fine_integration_time_min_bin 0x170a 16
	935	fine_integration_time_max_margin_bin 0x170c 16
	936	binning_capability 0x1710
	937	- e unsupported 0
	938	- e binning_then_subsampling 1
	939	- e subsampling_then_binning 2
	940	binning_weighting_capability 0x1711
	941	- b averaged 0
	942	- b summed 1
	943	- b bayer_corrected 2
	944	- b module_specific_weight 3
	945	binning_sub_types 0x1712
	946	binning_sub_type(n) 0x1713
	947	- l n 0 63 1
	948	- f row 0 3
	949	- f column 4 7
	950	binning_weighting_mono_capability 0x1771 v1.1
	951	- b averaged 0
	952	- b summed 1
	953	- b bayer_corrected 2
	954	- b module_specific_weight 3
	955	binning_sub_types_mono 0x1772 v1.1
	956	binning_sub_type_mono(n) 0x1773 v1.1 f
	957	- l n 0 63 1
	958
	959	# data transfer interface capability registers
	960	data_transfer_if_capability 0x1800
	961	- b supported 0
	962	- b polling 2
	963
	964	# sensor correction capability registers
	965	shading_correction_capability 0x1900
	966	- b color_shading 0
	967	- b luminance_correction 1
	968	green_imbalance_capability 0x1901
	969	- b supported 0
	970	module_specific_correction_capability 0x1903
	971	defect_correction_capability 0x1904 16
	972	- b mapped_defect 0
	973	- b dynamic_couplet 2
	974	- b dynamic_single 5
	975	- b combined_dynamic 8
	976	defect_correction_capability_2 0x1906 16
	977	- b dynamic_triplet 3
	978	nf_capability 0x1908
	979	- b luma 0
	980	- b chroma 1
	981	- b combined 2
	982
	983	# optical black readout capability registers
	984	ob_readout_capability 0x1980
	985	- b controllable_readout 0
	986	- b visible_pixel_readout 1
	987	- b different_vc_readout 2
	988	- b different_dt_readout 3
	989	- b prog_data_format 4
	990
	991	# color feedback capability registers
	992	color_feedback_capability 0x1987
	993	- b kelvin 0
	994	- b awb_gain 1
	995
	996	# cfa pattern capability registers
	997	CFA_pattern_capability 0x1990 v1.1
	998	- e bayer 0
	999	- e monochrome 1
	1000	- e 4x4_quad_bayer 2
	1001	- e vendor_specific 3
	1002	CFA_pattern_conversion_capability 0x1991 v1.1
	1003	- b bayer 0
	1004
	1005	# timer capability registers
	1006	flash_mode_capability 0x1a02
	1007	- b single_strobe 0
	1008	sa_strobe_mode_capability 0x1a03
	1009	- b fixed_width 0
	1010	- b edge_ctrl 1
	1011
	1012	# soft reset capability registers
	1013	reset_max_delay 0x1a10 v1.1
	1014	reset_min_time 0x1a11 v1.1
	1015
	1016	# pdaf capability registers
	1017	pdaf_capability_1 0x1b80
	1018	- b supported 0
	1019	- b processed_bottom_embedded 1
	1020	- b processed_interleaved 2
	1021	- b raw_bottom_embedded 3
	1022	- b raw_interleaved 4
	1023	- b visible_pdaf_correction 5
	1024	- b vc_interleaving 6
	1025	- b dt_interleaving 7
	1026	pdaf_capability_2 0x1b81
	1027	- b ROI 0
	1028	- b after_digital_crop 1
	1029	- b ctrl_retimed 2
	1030
	1031	# bracketing interface capability registers
	1032	bracketing_lut_capability_1 0x1c00
	1033	- b coarse_integration 0
	1034	- b global_analog_gain 1
	1035	- b flash 4
	1036	- b global_digital_gain 5
	1037	- b alternate_global_analog_gain 6
	1038	bracketing_lut_capability_2 0x1c01
	1039	- b single_bracketing_mode 0
	1040	- b looped_bracketing_mode 1
	1041	bracketing_lut_size 0x1c02

Documentation/driver-api/media/drivers/ccs/ccs.rst+82−0

@@ -0,0 +1,82 @@
	1	.. SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
	2
	3	.. include:: <isonum.txt>
	4
	5	MIPI CCS camera sensor driver
	6	=============================
	7
	8	The MIPI CCS camera sensor driver is a generic driver for `MIPI CCS
	9	<https://www.mipi.org/specifications/camera-command-set>`_ compliant
	10	camera sensors. It exposes three sub-devices representing the pixel array,
	11	the binner and the scaler.
	12
	13	As the capabilities of individual devices vary, the driver exposes
	14	interfaces based on the capabilities that exist in hardware.
	15
	16	Pixel Array sub-device
	17	----------------------
	18
	19	The pixel array sub-device represents the camera sensor's pixel matrix, as well
	20	as analogue crop functionality present in many compliant devices. The analogue
	21	crop is configured using the ``V4L2_SEL_TGT_CROP`` on the source pad (0) of the
	22	entity. The size of the pixel matrix can be obtained by getting the
	23	``V4L2_SEL_TGT_NATIVE_SIZE`` target.
	24
	25	Binner
	26	------
	27
	28	The binner sub-device represents the binning functionality on the sensor. For
	29	that purpose, selection target ``V4L2_SEL_TGT_COMPOSE`` is supported on the
	30	sink pad (0).
	31
	32	Additionally, if a device has no scaler or digital crop functionality, the
	33	source pad (1) expses another digital crop selection rectangle that can only
	34	crop at the end of the lines and frames.
	35
	36	Scaler
	37	------
	38
	39	The scaler sub-device represents the digital crop and scaling functionality of
	40	the sensor. The V4L2 selection target ``V4L2_SEL_TGT_CROP`` is used to
	41	configure the digital crop on the sink pad (0) when digital crop is supported.
	42	Scaling is configured using selection target ``V4L2_SEL_TGT_COMPOSE`` on the
	43	sink pad (0) as well.
	44
	45	Additionally, if the scaler sub-device exists, its source pad (1) exposes
	46	another digital crop selection rectangle that can only crop at the end of the
	47	lines and frames.
	48
	49	Digital and analogue crop
	50	-------------------------
	51
	52	Digital crop functionality is referred to as cropping that effectively works by
	53	dropping some data on the floor. Analogue crop, on the other hand, means that
	54	the cropped information is never retrieved. In case of camera sensors, the
	55	analogue data is never read from the pixel matrix that are outside the
	56	configured selection rectangle that designates crop. The difference has an
	57	effect in device timing and likely also in power consumption.
	58
	59	Register definition generator
	60	-----------------------------
	61
	62	The ccs-regs.asc file contains MIPI CCS register definitions that are used
	63	to produce C source code files for definitions that can be better used by
	64	programs written in C language. As there are many dependencies between the
	65	produced files, please do not modify them manually as it's error-prone and
	66	in vain, but instead change the script producing them.
	67
	68	Usage
	69	~~~~~
	70
	71	Conventionally the script is called this way to update the CCS driver
	72	definitions:
	73
	74	.. code-block:: none
	75
	76	$ Documentation/driver-api/media/drivers/ccs/mk-ccs-regs -k \
	77	-e drivers/media/i2c/ccs/ccs-regs.h \
	78	-L drivers/media/i2c/ccs/ccs-limits.h \
	79	-l drivers/media/i2c/ccs/ccs-limits.c \
	80	-c Documentation/driver-api/media/drivers/ccs/ccs-regs.asc
	81
	82	Copyright \|copy\| 2020 Intel Corporation

Documentation/driver-api/media/drivers/ccs/mk-ccs-regs+433−0

@@ -0,0 +1,433 @@
	1	#!/usr/bin/perl -w
	2	# SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
	3	# Copyright (C) 2019--2020 Intel Corporation
	4
	5	use Getopt::Long qw(:config no_ignore_case);
	6	use File::Basename;
	7
	8	my $ccsregs = "ccs-regs.asc";
	9	my $header;
	10	my $regarray;
	11	my $limitc;
	12	my $limith;
	13	my $kernel;
	14	my $help;
	15
	16	GetOptions("ccsregs\|c=s" => \$ccsregs,
	17	"header\|e=s" => \$header,
	18	"regarray\|r=s" => \$regarray,
	19	"limitc\|l=s" => \$limitc,
	20	"limith\|L=s" => \$limith,
	21	"kernel\|k" => \$kernel,
	22	"help\|h" => \$help) or die "can't parse options";
	23
	24	$help = 1 if ! defined $header \|\| ! defined $limitc \|\| ! defined $limith;
	25
	26	if (defined $help) {
	27	print <<EOH
	28	$0 - Create CCS register definitions for C
	29
	30	usage: $0 -c ccs-regs.asc -e header -r regarray -l limit-c -L limit-header [-k]
	31
	32	-c ccs register file
	33	-e header file name
	34	-r register description array file name
	35	-l limit and capability array file name
	36	-L limit and capability header file name
	37	-k generate files for kernel space consumption
	38	EOH
	39	;
	40	exit 0;
	41	}
	42
	43	my $lh_hdr = ! defined $kernel
	44	? '#include "ccs-os.h"' . "\n"
	45	: "#include <linux/bits.h>\n#include <linux/types.h>\n";
	46	my $uint32_t = ! defined $kernel ? 'uint32_t' : 'u32';
	47	my $uint16_t = ! defined $kernel ? 'uint16_t' : 'u16';
	48
	49	open(my $R, "< $ccsregs") or die "can't open $ccsregs";
	50
	51	open(my $H, "> $header") or die "can't open $header";
	52	my $A;
	53	if (defined $regarray) {
	54	open($A, "> $regarray") or die "can't open $regarray";
	55	}
	56	open(my $LC, "> $limitc") or die "can't open $limitc";
	57	open(my $LH, "> $limith") or die "can't open $limith";
	58
	59	my %this;
	60
	61	sub is_limit_reg($) {
	62	my $addr = hex $_[0];
	63
	64	return 0 if $addr < 0x40; # weed out status registers
	65	return 0 if $addr >= 0x100 && $addr < 0xfff; # weed out configuration registers
	66
	67	return 1;
	68	}
	69
	70	my $uc_header = basename uc $header;
	71	$uc_header =~ s/[^A-Z0-9]/_/g;
	72
	73	my $copyright = "/* Copyright (C) 2019--2020 Intel Corporation */\n";
	74	my $license = "SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause";
	75
	76	for my $fh ($A, $LC) {
	77	print $fh "// $license\n$copyright\n" if defined $fh;
	78	}
	79
	80	for my $fh ($H, $LH) {
	81	print $fh "/* $license */\n$copyright\n";
	82	}
	83
	84	sub bit_def($) {
	85	my $bit = shift @_;
	86
	87	return "BIT($bit)" if defined $kernel;
	88	return "(1U << $bit)" if $bit =~ /^[a-zA-Z0-9_]+$/;
	89	return "(1U << ($bit))";
	90	}
	91
	92	print $H <<EOF
	93	#ifndef __${uc_header}__
	94	#define __${uc_header}__
	95
	96	EOF
	97	;
	98
	99	print $H "#include <linux/bits.h>\n\n" if defined $kernel;
	100
	101	print $H <<EOF
	102	#define CCS_FL_BASE 16
	103	EOF
	104	;
	105
	106	print $H "#define CCS_FL_16BIT " . bit_def("CCS_FL_BASE") . "\n";
	107	print $H "#define CCS_FL_32BIT " . bit_def("CCS_FL_BASE + 1") . "\n";
	108	print $H "#define CCS_FL_FLOAT_IREAL " . bit_def("CCS_FL_BASE + 2") . "\n";
	109	print $H "#define CCS_FL_IREAL " . bit_def("CCS_FL_BASE + 3") . "\n";
	110
	111	print $H <<EOF
	112	#define CCS_R_ADDR(r) ((r) & 0xffff)
	113
	114	EOF
	115	;
	116
	117	print $A <<EOF
	118	#include <stdint.h>
	119	#include <stdio.h>
	120	#include "ccs-extra.h"
	121	#include "ccs-regs.h"
	122
	123	EOF
	124	if defined $A;
	125
	126	my $uc_limith = basename uc $limith;
	127	$uc_limith =~ s/[^A-Z0-9]/_/g;
	128
	129	print $LH <<EOF
	130	#ifndef __${uc_limith}__
	131	#define __${uc_limith}__
	132
	133	$lh_hdr
	134	struct ccs_limit {
	135	$uint32_t reg;
	136	$uint16_t size;
	137	$uint16_t flags;
	138	const char *name;
	139	};
	140
	141	EOF
	142	;
	143	print $LH "#define CCS_L_FL_SAME_REG " . bit_def(0) . "\n\n";
	144
	145	print $LH <<EOF
	146	extern const struct ccs_limit ccs_limits[];
	147
	148	EOF
	149	;
	150
	151	print $LC <<EOF
	152	#include "ccs-limits.h"
	153	#include "ccs-regs.h"
	154
	155	const struct ccs_limit ccs_limits[] = {
	156	EOF
	157	;
	158
	159	my $limitcount = 0;
	160	my $argdescs;
	161	my $reglist = "const struct ccs_reg_desc ccs_reg_desc[] = {\n";
	162
	163	sub name_split($$) {
	164	my ($name, $addr) = @_;
	165	my $args;
	166
	167	$name =~ /([^\(]+?)(\(.*)/;
	168	($name, $args) = ($1, $2);
	169	$args = [split /,\s*/, $args];
	170	foreach my $t (@$args) {
	171	$t =~ s/[]//g;
	172	$t =~ s/\//\\\//g;
	173	}
	174
	175	return ($name, $addr, $args);
	176	}
	177
	178	sub tabconv($) {
	179	$_ = shift;
	180
	181	my @l = split "\n", $_;
	182
	183	map {
	184	s/ {8,8}/\t/g;
	185	s/\t\K +//;
	186	} @l;
	187
	188	return (join "\n", @l) . "\n";
	189	}
	190
	191	sub elem_size(@) {
	192	my @flags = @_;
	193
	194	return 2 if grep /^16$/, @flags;
	195	return 4 if grep /^32$/, @flags;
	196	return 1;
	197	}
	198
	199	sub arr_size($) {
	200	my $this = $_[0];
	201	my $size = $this->{elsize};
	202	my $h = $this->{argparams};
	203
	204	foreach my $arg (@{$this->{args}}) {
	205	my $apref = $h->{$arg};
	206
	207	$size *= $apref->{max} - $apref->{min} + 1;
	208	}
	209
	210	return $size;
	211	}
	212
	213	sub print_args($$$) {
	214	my ($this, $postfix, $is_same_reg) = @_;
	215	my ($args, $argparams, $name) =
	216	($this->{args}, $this->{argparams}, $this->{name});
	217	my $varname = "ccs_reg_arg_" . (lc $name) . $postfix;
	218	my @mins;
	219	my @sorted_args = @{$this->{sorted_args}};
	220	my $lim_arg;
	221	my $size = arr_size($this);
	222
	223	$argdescs .= "static const struct ccs_reg_arg " . $varname . "[] = {\n";
	224
	225	foreach my $sorted_arg (@sorted_args) {
	226	push @mins, $argparams->{$sorted_arg}->{min};
	227	}
	228
	229	foreach my $sorted_arg (@sorted_args) {
	230	my $h = $argparams->{$sorted_arg};
	231
	232	$argdescs .= "\t{ \"$sorted_arg\", $h->{min}, $h->{max}, $h->{elsize} },\n";
	233
	234	$lim_arg .= defined $lim_arg ? ", $h->{min}" : "$h->{min}";
	235	}
	236
	237	$argdescs .= "};\n\n";
	238
	239	$reglist .= "\t{ CCS_R_" . (uc $name) . "(" . (join ",", (@mins)) .
	240	"), $size, sizeof($varname) / sizeof(*$varname)," .
	241	" \"" . (lc $name) . "\", $varname },\n";
	242
	243	print $LC tabconv sprintf "\t{ CCS_R_" . (uc $name) . "($lim_arg), " .
	244	$size . ", " . ($is_same_reg ? "CCS_L_FL_SAME_REG" : "0") .
	245	", \"$name" . (defined $this->{discontig} ? " $lim_arg" : "") . "\" },\n"
	246	if is_limit_reg $this->{base_addr};
	247	}
	248
	249	my $hdr_data;
	250
	251	while (<$R>) {
	252	chop;
	253	s/^\s*//;
	254	next if /^[#;]/ \|\| /^$/;
	255	if (s/^-\s*//) {
	256	if (s/^b\s*//) {
	257	my ($bit, $addr) = split /\t+/;
	258	$bit = uc $bit;
	259	$hdr_data .= sprintf "#define %-62s %s", "CCS_" . (uc ${this{name}}) ."_$bit", bit_def($addr) . "\n";
	260	} elsif (s/^f\s*//) {
	261	s/[,\.-]/_/g;
	262	my @a = split /\s+/;
	263	my ($msb, $lsb, $this_field) = reverse @a;
	264	@a = ( { "name" => "SHIFT", "addr" => $lsb, "fmt" => "%uU", },
	265	{ "name" => "MASK", "addr" => (1 << ($msb + 1)) - 1 - ((1 << $lsb) - 1), "fmt" => "0x%" . join(".", ($this{"elsize"} >> 2) x 2) . "x" } );
	266	$this{"field"} = $this_field;
	267	foreach my $ar (@a) {
	268	#print $ar->{fmt}."\n";
	269	$hdr_data .= sprintf "#define %-62s " . $ar->{"fmt"} . "\n", "CCS_" . (uc $this{"name"}) . (defined $this_field ? "_" . uc $this_field : "") . "_" . $ar->{"name"}, $ar->{"addr"} . "\n";
	270	}
	271	} elsif (s/^e\s*//) {
	272	s/[,\.-]/_/g;
	273	my ($enum, $addr) = split /\s+/;
	274	$enum = uc $enum;
	275	$hdr_data .= sprintf "#define %-62s %s", "CCS_" . (uc ${this{name}}) . (defined $this{"field"} ? "_" . uc $this{"field"} : "") ."_$enum", $addr . ($addr =~ /0x/i ? "" : "U") . "\n";
	276	} elsif (s/^l\s*//) {
	277	my ($arg, $min, $max, $elsize, @discontig) = split /\s+/;
	278	my $size;
	279
	280	foreach my $num ($min, $max) {
	281	$num = hex $num if $num =~ /0x/i;
	282	}
	283
	284	$hdr_data .= sprintf "#define %-62s %s", "CCS_LIM_" . (uc ${this{name}} . "_MIN_$arg"), $min . ($min =~ /0x/i ? "" : "U") . "\n";
	285	$hdr_data .= sprintf "#define %-62s %s", "CCS_LIM_" . (uc ${this{name}} . "_MAX_$arg"), $max . ($max =~ /0x/i ? "" : "U") . "\n";
	286
	287	my $h = $this{argparams};
	288
	289	$h->{$arg} = { "min" => $min,
	290	"max" => $max,
	291	"elsize" => $elsize =~ /^0x/ ? hex $elsize : $elsize,
	292	"discontig" => \@discontig };
	293
	294	$this{discontig} = $arg if @discontig;
	295
	296	next if $#{$this{args}} + 1 != scalar keys %{$this{argparams}};
	297
	298	my $reg_formula = "($this{addr}";
	299	my $lim_formula;
	300
	301	foreach my $arg (@{$this{args}}) {
	302	my $d = $h->{$arg}->{discontig};
	303	my $times = $h->{$arg}->{elsize} != 1 ?
	304	" * " . $h->{$arg}->{elsize} : "";
	305
	306	if (@$d) {
	307	my ($lim, $offset) = split /,/, $d->[0];
	308
	309	$reg_formula .= " + (($arg) < $lim ? ($arg)$times : $offset + (($arg) - $lim)$times)";
	310	} else {
	311	$reg_formula .= " + ($arg)$times";
	312	}
	313
	314	$lim_formula .= (defined $lim_formula ? " + " : "") . "($arg)$times";
	315	}
	316
	317	$reg_formula .= ")\n";
	318	$lim_formula =~ s/^$([a-z0-9]+)$$/$1/i;
	319
	320	print $H tabconv sprintf("#define %-62s %s", "CCS_R_" . (uc $this{name}) .
	321	$this{arglist}, $reg_formula);
	322
	323	print $H tabconv $hdr_data;
	324	undef $hdr_data;
	325
	326	# Sort arguments in descending order by size
	327	@{$this{sorted_args}} = sort {
	328	$h->{$a}->{elsize} <= $h->{$b}->{elsize}
	329	} @{$this{args}};
	330
	331	if (defined $this{discontig}) {
	332	my $da = $this{argparams}->{$this{discontig}};
	333	my ($first_discontig) = split /,/, $da->{discontig}->[0];
	334	my $max = $da->{max};
	335
	336	$da->{max} = $first_discontig - 1;
	337	print_args(\%this, "", 0);
	338
	339	$da->{min} = $da->{max} + 1;
	340	$da->{max} = $max;
	341	print_args(\%this, $first_discontig, 1);
	342	} else {
	343	print_args(\%this, "", 0);
	344	}
	345
	346	next unless is_limit_reg $this{base_addr};
	347
	348	print $LH tabconv sprintf "#define %-63s%s\n",
	349	"CCS_L_" . (uc $this{name}) . "_OFFSET(" .
	350	(join ", ", @{$this{args}}) . ")", "($lim_formula)";
	351	}
	352
	353	if (! @{$this{args}}) {
	354	print $H tabconv($hdr_data);
	355	undef $hdr_data;
	356	}
	357
	358	next;
	359	}
	360
	361	my ($name, $addr, @flags) = split /\t+/, $_;
	362	my $args = [];
	363
	364	my $sp;
	365
	366	($name, $addr, $args) = name_split($name, $addr) if /$.*$/;
	367
	368	$name =~ s/[,\.-]/_/g;
	369
	370	my $flagstring = "";
	371	my $size = elem_size(@flags);
	372	$flagstring .= "\| CCS_FL_16BIT " if $size eq "2";
	373	$flagstring .= "\| CCS_FL_32BIT " if $size eq "4";
	374	$flagstring .= "\| CCS_FL_FLOAT_IREAL " if grep /^float_ireal$/, @flags;
	375	$flagstring .= "\| CCS_FL_IREAL " if grep /^ireal$/, @flags;
	376	$flagstring =~ s/^\\| //;
	377	$flagstring =~ s/ $//;
	378	$flagstring = "($flagstring)" if $flagstring =~ /\\|/;
	379	my $base_addr = $addr;
	380	$addr = "($addr \| $flagstring)" if $flagstring ne "";
	381
	382	my $arglist = @$args ? "(" . (join ", ", @$args) . ")" : "";
	383	$hdr_data .= sprintf "#define %-62s %s\n", "CCS_R_" . (uc $name), $addr
	384	if !@$args;
	385
	386	$name =~ s/\(.*//;
	387
	388	%this = ( name => $name,
	389	addr => $addr,
	390	base_addr => $base_addr,
	391	argparams => {},
	392	args => $args,
	393	arglist => $arglist,
	394	elsize => $size,
	395	);
	396
	397	if (!@$args) {
	398	$reglist .= "\t{ CCS_R_" . (uc $name) . ", 1, 0, \"" . (lc $name) . "\", NULL },\n";
	399	print $H tabconv $hdr_data;
	400	undef $hdr_data;
	401
	402	print $LC tabconv sprintf "\t{ CCS_R_" . (uc $name) . ", " .
	403	$this{elsize} . ", 0, \"$name\" },\n"
	404	if is_limit_reg $this{base_addr};
	405	}
	406
	407	print $LH tabconv sprintf "#define %-63s%s\n",
	408	"CCS_L_" . (uc $this{name}), $limitcount++
	409	if is_limit_reg $this{base_addr};
	410	}
	411
	412	if (defined $A) {
	413	print $A $argdescs, $reglist;
	414
	415	print $A "\t{ 0 }\n";
	416
	417	print $A "};\n";
	418	}
	419
	420	print $H "\n#endif /* __${uc_header}__ */\n";
	421
	422	print $LH tabconv sprintf "#define %-63s%s\n", "CCS_L_LAST", $limitcount;
	423
	424	print $LH "\n#endif /* __${uc_limith}__ */\n";
	425
	426	print $LC "\t{ 0 } /* Guardian */\n";
	427	print $LC "};\n";
	428
	429	close($R);
	430	close($H);
	431	close($A) if defined $A;
	432	close($LC);
	433	close($LH);

Documentation/driver-api/media/drivers/index.rst+1−0

@@ -26,6 +26,7 @@ Video4Linux (V4L) drivers · 25 unmodified lines
26	tuners	26	tuners
27	vimc-devel	27	vimc-devel
28	zoran	28	zoran
		29	ccs/ccs
29		30
30		31
31	Digital TV drivers	32	Digital TV drivers

Documentation/driver-api/media/dtv-frontend.rst+3−3

Documentation/driver-api/media/v4l2-controls.rst+2−2

@@ -335,7 +335,7 @@ current and new values: · 334 unmodified lines
335	union v4l2_ctrl_ptr p_new;	335	union v4l2_ctrl_ptr p_new;
336	union v4l2_ctrl_ptr p_cur;	336	union v4l2_ctrl_ptr p_cur;
337		337
338	If the control has a simple s32 type type, then:	338	If the control has a simple s32 type, then:
339		339
340	.. code-block:: c	340	.. code-block:: c
341		341
@@ -349,7 +349,7 @@ Within the control ops you can freely use these. The val and cur.val speak for · 7 unmodified lines
349	themselves. The p_char pointers point to character buffers of length	349	themselves. The p_char pointers point to character buffers of length
350	ctrl->maximum + 1, and are always 0-terminated.	350	ctrl->maximum + 1, and are always 0-terminated.
351		351
352	Unless the control is marked volatile the p_cur field points to the the	352	Unless the control is marked volatile the p_cur field points to the
353	current cached control value. When you create a new control this value is made	353	current cached control value. When you create a new control this value is made
354	identical to the default value. After calling v4l2_ctrl_handler_setup() this	354	identical to the default value. After calling v4l2_ctrl_handler_setup() this
355	value is passed to the hardware. It is generally a good idea to call this	355	value is passed to the hardware. It is generally a good idea to call this

Documentation/driver-api/media/v4l2-dev.rst+1−1

@@ -212,7 +212,7 @@ types exist: · 211 unmodified lines
212	========================== ==================== ==============================	212	========================== ==================== ==============================
213		213
214	The last argument gives you a certain amount of control over the device	214	The last argument gives you a certain amount of control over the device
215	device node number used (i.e. the X in ``videoX``). Normally you will pass -1	215	node number used (i.e. the X in ``videoX``). Normally you will pass -1
216	to let the v4l2 framework pick the first free number. But sometimes users	216	to let the v4l2 framework pick the first free number. But sometimes users
217	want to select a specific node number. It is common that drivers allow	217	want to select a specific node number. It is common that drivers allow
218	the user to select a specific device node number through a driver module	218	the user to select a specific device node number through a driver module

Documentation/userspace-api/media/cec/cec-ioc-g-mode.rst+1−1

@@ -188,7 +188,7 @@ Available follower modes are: · 187 unmodified lines
188	in combination with :ref:`CEC_MODE_NO_INITIATOR <CEC-MODE-NO-INITIATOR>`, otherwise	188	in combination with :ref:`CEC_MODE_NO_INITIATOR <CEC-MODE-NO-INITIATOR>`, otherwise
189	the ``EINVAL`` error code will be returned. In 'monitor all' mode all messages	189	the ``EINVAL`` error code will be returned. In 'monitor all' mode all messages
190	this CEC device transmits and all messages it receives, including	190	this CEC device transmits and all messages it receives, including
191	directed messages for other CEC devices will be reported. This is	191	directed messages for other CEC devices, will be reported. This is
192	very useful for debugging, but not all devices support this. This	192	very useful for debugging, but not all devices support this. This
193	mode requires that the :ref:`CEC_CAP_MONITOR_ALL <CEC-CAP-MONITOR-ALL>` capability is set,	193	mode requires that the :ref:`CEC_CAP_MONITOR_ALL <CEC-CAP-MONITOR-ALL>` capability is set,
194	otherwise the ``EINVAL`` error code is returned. This is only allowed if	194	otherwise the ``EINVAL`` error code is returned. This is only allowed if

Documentation/userspace-api/media/dvb/audio.rst+1−1

@@ -8,7 +8,7 @@ Digital TV Audio Device · 7 unmodified lines
8		8
9	The Digital TV audio device controls the MPEG2 audio decoder of the Digital	9	The Digital TV audio device controls the MPEG2 audio decoder of the Digital
10	TV hardware. It can be accessed through ``/dev/dvb/adapter?/audio?``. Data	10	TV hardware. It can be accessed through ``/dev/dvb/adapter?/audio?``. Data
11	types and and ioctl definitions can be accessed by including	11	types and ioctl definitions can be accessed by including
12	``linux/dvb/audio.h`` in your application.	12	``linux/dvb/audio.h`` in your application.
13		13
14	Please note that some Digital TV cards don’t have their own MPEG decoder, which	14	Please note that some Digital TV cards don’t have their own MPEG decoder, which

Documentation/userspace-api/media/dvb/ca.rst+1−1

@@ -7,7 +7,7 @@ Digital TV CA Device · 6 unmodified lines
7	####################	7	####################
8		8
9	The Digital TV CA device controls the conditional access hardware. It	9	The Digital TV CA device controls the conditional access hardware. It
10	can be accessed through ``/dev/dvb/adapter?/ca?``. Data types and and ioctl	10	can be accessed through ``/dev/dvb/adapter?/ca?``. Data types and ioctl
11	definitions can be accessed by including ``linux/dvb/ca.h`` in your	11	definitions can be accessed by including ``linux/dvb/ca.h`` in your
12	application.	12	application.
13		13

Documentation/userspace-api/media/dvb/demux.rst+1−1

@@ -11,7 +11,7 @@ digital TV. If the driver and hardware supports, those filters are · 10 unmodified lines
11	implemented at the hardware. Otherwise, the Kernel provides a software	11	implemented at the hardware. Otherwise, the Kernel provides a software
12	emulation.	12	emulation.
13		13
14	It can be accessed through ``/dev/adapter?/demux?``. Data types and and	14	It can be accessed through ``/dev/adapter?/demux?``. Data types and
15	ioctl definitions can be accessed by including ``linux/dvb/dmx.h`` in	15	ioctl definitions can be accessed by including ``linux/dvb/dmx.h`` in
16	your application.	16	your application.
17		17

Documentation/userspace-api/media/dvb/dmx-qbuf.rst+1−1

@@ -50,7 +50,7 @@ by a :ref:`DMX_QUERYBUF` ioctl will do as well. · 49 unmodified lines
50	When ``DMX_QBUF`` is called with a pointer to this structure, it locks the	50	When ``DMX_QBUF`` is called with a pointer to this structure, it locks the
51	memory pages of the buffer in physical memory, so they cannot be swapped	51	memory pages of the buffer in physical memory, so they cannot be swapped
52	out to disk. Buffers remain locked until dequeued, until the	52	out to disk. Buffers remain locked until dequeued, until the
53	the device is closed.	53	device is closed.
54		54
55	Applications call the ``DMX_DQBUF`` ioctl to dequeue a filled	55	Applications call the ``DMX_DQBUF`` ioctl to dequeue a filled
56	(capturing) buffer from the driver's outgoing queue.	56	(capturing) buffer from the driver's outgoing queue.

Documentation/userspace-api/media/dvb/net.rst+1−1

@@ -23,7 +23,7 @@ types that are present on the transport stream. This is done through · 22 unmodified lines
23	virtual ``dvb?_?`` network interfaces, and will be controlled/routed via	23	virtual ``dvb?_?`` network interfaces, and will be controlled/routed via
24	the standard ip tools (like ip, route, netstat, ifconfig, etc).	24	the standard ip tools (like ip, route, netstat, ifconfig, etc).
25		25
26	Data types and and ioctl definitions are defined via ``linux/dvb/net.h``	26	Data types and ioctl definitions are defined via ``linux/dvb/net.h``
27	header.	27	header.
28		28
29		29

Documentation/userspace-api/media/dvb/video.rst+1−1

@@ -8,7 +8,7 @@ Digital TV Video Device · 7 unmodified lines
8		8
9	The Digital TV video device controls the MPEG2 video decoder of the Digital	9	The Digital TV video device controls the MPEG2 video decoder of the Digital
10	TV hardware. It can be accessed through /dev/dvb/adapter0/video0. Data	10	TV hardware. It can be accessed through /dev/dvb/adapter0/video0. Data
11	types and and ioctl definitions can be accessed by including	11	types and ioctl definitions can be accessed by including
12	linux/dvb/video.h in your application.	12	linux/dvb/video.h in your application.
13		13
14	Note that the Digital TV video device only controls decoding of the MPEG video	14	Note that the Digital TV video device only controls decoding of the MPEG video

Documentation/userspace-api/media/lirc.h.rst.exceptions+1−0

@@ -64,6 +64,7 @@ ignore symbol RC_PROTO_RCMM12 · 63 unmodified lines
64	ignore symbol RC_PROTO_RCMM24	64	ignore symbol RC_PROTO_RCMM24
65	ignore symbol RC_PROTO_RCMM32	65	ignore symbol RC_PROTO_RCMM32
66	ignore symbol RC_PROTO_XBOX_DVD	66	ignore symbol RC_PROTO_XBOX_DVD
		67	ignore symbol RC_PROTO_MAX
67		68
68	# Undocumented macros	69	# Undocumented macros
69		70

Documentation/userspace-api/media/rc/keytable.c.rst+1−1

@@ -1,4 +1,4 @@
1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later	1	.. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
2		2
3	file: uapi/v4l/keytable.c	3	file: uapi/v4l/keytable.c
4	=========================	4	=========================

Documentation/userspace-api/media/rc/lirc-dev-intro.rst+10−3

-.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
+.. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
 .. _lirc_dev_intro:
     This mode is for both sending and receiving IR.
-    For transmitting (aka sending), create a ``struct lirc_scancode`` with
+    For transmitting (aka sending), create a struct lirc_scancode with
     the desired scancode set in the ``scancode`` member, :c:type:`rc_proto`
     set to the :ref:`IR protocol <Remote_controllers_Protocols>`, and all other
     members set to 0. Write this struct to the lirc device.
-    For receiving, you read ``struct lirc_scancode`` from the LIRC device.
+    For receiving, you read struct lirc_scancode from the LIRC device.
     The ``scancode`` field is set to the received scancode and the
     :ref:`IR protocol <Remote_controllers_Protocols>` is set in
     :c:type:`rc_proto`. If the scancode maps to a valid key code, this is set
     This mode is used only for IR send.
+*************************************
+Data types used by LIRC_MODE_SCANCODE
+*************************************
+.. kernel-doc:: include/uapi/linux/lirc.h
+    :identifiers: lirc_scancode rc_proto
 ********************
 BPF based IR decoder
 ********************

Documentation/userspace-api/media/rc/lirc-dev.rst+1−1

@@ -1,4 +1,4 @@
1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later	1	.. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
2		2
3	.. _lirc_dev:	3	.. _lirc_dev:
4		4

Documentation/userspace-api/media/rc/lirc-func.rst+1−1

@@ -1,4 +1,4 @@
1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later	1	.. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
2		2
3	.. _lirc_func:	3	.. _lirc_func:
4		4

Documentation/userspace-api/media/rc/lirc-get-features.rst+1−1

@@ -1,4 +1,4 @@
1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later	1	.. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
2	.. c:namespace:: RC	2	.. c:namespace:: RC
3		3
4	.. _lirc_get_features:	4	.. _lirc_get_features:

Documentation/userspace-api/media/rc/lirc-get-rec-mode.rst+1−1

@@ -1,4 +1,4 @@
1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later	1	.. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
2	.. c:namespace:: RC	2	.. c:namespace:: RC
3		3
4	.. _lirc_get_rec_mode:	4	.. _lirc_get_rec_mode:

Documentation/userspace-api/media/rc/lirc-get-rec-resolution.rst+1−1

@@ -1,4 +1,4 @@
1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later	1	.. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
2	.. c:namespace:: RC	2	.. c:namespace:: RC
3		3
4	.. _lirc_get_rec_resolution:	4	.. _lirc_get_rec_resolution:

Documentation/userspace-api/media/rc/lirc-get-send-mode.rst+1−1

@@ -1,4 +1,4 @@
1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later	1	.. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
2	.. c:namespace:: RC	2	.. c:namespace:: RC
3		3
4	.. _lirc_get_send_mode:	4	.. _lirc_get_send_mode:

Documentation/userspace-api/media/rc/lirc-get-timeout.rst+1−1

@@ -1,4 +1,4 @@
1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later	1	.. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
2	.. c:namespace:: RC	2	.. c:namespace:: RC
3		3
4	.. _lirc_get_min_timeout:	4	.. _lirc_get_min_timeout:

Documentation/userspace-api/media/rc/lirc-header.rst+1−1

@@ -1,4 +1,4 @@
1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later	1	.. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
2		2
3	.. _lirc_header:	3	.. _lirc_header:
4		4

Documentation/userspace-api/media/rc/lirc-read.rst+1−1

@@ -1,4 +1,4 @@
1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later	1	.. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
2	.. c:namespace:: RC	2	.. c:namespace:: RC
3		3
4	.. _lirc-read:	4	.. _lirc-read:

Documentation/userspace-api/media/rc/lirc-set-measure-carrier-mode.rst+1−1

@@ -1,4 +1,4 @@
1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later	1	.. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
2	.. c:namespace:: RC	2	.. c:namespace:: RC
3		3
4	.. _lirc_set_measure_carrier_mode:	4	.. _lirc_set_measure_carrier_mode:

Documentation/userspace-api/media/rc/lirc-set-rec-carrier-range.rst+1−1

@@ -1,4 +1,4 @@
1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later	1	.. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
2	.. c:namespace:: RC	2	.. c:namespace:: RC
3		3
4	.. _lirc_set_rec_carrier_range:	4	.. _lirc_set_rec_carrier_range:

Documentation/userspace-api/media/rc/lirc-set-rec-carrier.rst+1−1

@@ -1,4 +1,4 @@
1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later	1	.. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
2	.. c:namespace:: RC	2	.. c:namespace:: RC
3		3
4	.. _lirc_set_rec_carrier:	4	.. _lirc_set_rec_carrier:

Documentation/userspace-api/media/rc/lirc-set-rec-timeout-reports.rst+1−1

@@ -1,4 +1,4 @@
1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later	1	.. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
2	.. c:namespace:: RC	2	.. c:namespace:: RC
3		3
4	.. _lirc_set_rec_timeout_reports:	4	.. _lirc_set_rec_timeout_reports:

Documentation/userspace-api/media/rc/lirc-set-rec-timeout.rst+1−1

@@ -1,4 +1,4 @@
1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later	1	.. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
2	.. c:namespace:: RC	2	.. c:namespace:: RC
3		3
4	.. _lirc_set_rec_timeout:	4	.. _lirc_set_rec_timeout:

Documentation/userspace-api/media/rc/lirc-set-send-carrier.rst+1−1

@@ -1,4 +1,4 @@
1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later	1	.. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
2	.. c:namespace:: RC	2	.. c:namespace:: RC
3		3
4	.. _lirc_set_send_carrier:	4	.. _lirc_set_send_carrier:

Documentation/userspace-api/media/rc/lirc-set-send-duty-cycle.rst+1−1

@@ -1,4 +1,4 @@
1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later	1	.. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
2	.. c:namespace:: RC	2	.. c:namespace:: RC
3		3
4	.. _lirc_set_send_duty_cycle:	4	.. _lirc_set_send_duty_cycle:

Documentation/userspace-api/media/rc/lirc-set-transmitter-mask.rst+1−1

@@ -1,4 +1,4 @@
1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later	1	.. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
2	.. c:namespace:: RC	2	.. c:namespace:: RC
3		3
4	.. _lirc_set_transmitter_mask:	4	.. _lirc_set_transmitter_mask:

Documentation/userspace-api/media/rc/lirc-set-wideband-receiver.rst+1−1

@@ -1,4 +1,4 @@
1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later	1	.. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
2	.. c:namespace:: RC	2	.. c:namespace:: RC
3		3
4	.. _lirc_set_wideband_receiver:	4	.. _lirc_set_wideband_receiver:

Documentation/userspace-api/media/rc/lirc-write.rst+1−1

@@ -1,4 +1,4 @@
1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later	1	.. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
2	.. c:namespace:: RC	2	.. c:namespace:: RC
3		3
4	.. _lirc-write:	4	.. _lirc-write:

Documentation/userspace-api/media/rc/rc-intro.rst+1−1

@@ -1,4 +1,4 @@
1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later	1	.. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
2		2
3	.. _Remote_controllers_Intro:	3	.. _Remote_controllers_Intro:
4		4

Documentation/userspace-api/media/rc/rc-protos.rst+1−1

@@ -1,4 +1,4 @@
1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later	1	.. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
2		2
3	.. _Remote_controllers_Protocols:	3	.. _Remote_controllers_Protocols:
4		4

Documentation/userspace-api/media/rc/rc-sysfs-nodes.rst+1−1

@@ -1,4 +1,4 @@
1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later	1	.. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
2		2
3	.. _remote_controllers_sysfs_nodes:	3	.. _remote_controllers_sysfs_nodes:
4		4

Documentation/userspace-api/media/rc/rc-table-change.rst+1−1

@@ -1,4 +1,4 @@
1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later	1	.. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
2		2
3	.. _Remote_controllers_table_change:	3	.. _Remote_controllers_table_change:
4		4

Documentation/userspace-api/media/rc/rc-tables.rst+1−1

@@ -1,4 +1,4 @@
1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later	1	.. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
2		2
3	.. _Remote_controllers_tables:	3	.. _Remote_controllers_tables:
4		4

Documentation/userspace-api/media/rc/remote_controllers.rst+1−1

@@ -1,4 +1,4 @@
1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later	1	.. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
2	.. include:: <isonum.txt>	2	.. include:: <isonum.txt>
3		3
4	.. _remote_controllers:	4	.. _remote_controllers:

Documentation/userspace-api/media/v4l/biblio.rst+11−1

@@ -270,7 +270,17 @@ EBU Tech 3213 · 269 unmodified lines
270	=============	270	=============
271		271
272		272
273	:title: E.B.U. Standard for Chromaticity Tolerances for Studio Monitors"	273	:title: E.B.U. Standard for Chromaticity Tolerances for Studio Monitors
		274
		275	:author: European Broadcast Union (http://www.ebu.ch)
		276
		277	.. _tech3321:
		278
		279	EBU Tech 3321
		280	=============
		281
		282
		283	:title: E.B.U. guidelines for Consumer Flat Panel Displays (FPDs)
274		284
275	:author: European Broadcast Union (http://www.ebu.ch)	285	:author: European Broadcast Union (http://www.ebu.ch)
276		286

Documentation/userspace-api/media/v4l/buffer.rst+1−1

@@ -604,7 +604,7 @@ Buffer Flags · 603 unmodified lines
604	:ref:`VIDIOC_DQBUF <VIDIOC_QBUF>` ioctl is called. Due to	604	:ref:`VIDIOC_DQBUF <VIDIOC_QBUF>` ioctl is called. Due to
605	hardware limitations, the last buffer may be empty. In this case	605	hardware limitations, the last buffer may be empty. In this case
606	the driver will set the ``bytesused`` field to 0, regardless of	606	the driver will set the ``bytesused`` field to 0, regardless of
607	the format. Any Any subsequent call to the	607	the format. Any subsequent call to the
608	:ref:`VIDIOC_DQBUF <VIDIOC_QBUF>` ioctl will not block anymore,	608	:ref:`VIDIOC_DQBUF <VIDIOC_QBUF>` ioctl will not block anymore,
609	but return an ``EPIPE`` error code.	609	but return an ``EPIPE`` error code.
610	* .. _`V4L2-BUF-FLAG-REQUEST-FD`:	610	* .. _`V4L2-BUF-FLAG-REQUEST-FD`:

Documentation/userspace-api/media/v4l/colorspaces-details.rst+3−2

 =========================================================
 The :ref:`tech3213` standard defines the colorspace used by PAL/SECAM
-in 1975. In practice this colorspace is obsolete and SMPTE 170M should
+in 1975. Note that this colorspace is not supported by the HDMI interface.
-be used instead. The default transfer function is
+Instead :ref:`tech3321` recommends that Rec. 709 is used instead for HDMI.
+The default transfer function is
 ``V4L2_XFER_FUNC_709``. The default Y'CbCr encoding is
 ``V4L2_YCBCR_ENC_601``. The default Y'CbCr quantization is limited
 range. The chromaticities of the primary colors and the white reference

Documentation/userspace-api/media/v4l/common.rst+1−0

@@ -44,6 +44,7 @@ applicable to all devices. · 43 unmodified lines
44	ext-ctrls-image-source	44	ext-ctrls-image-source
45	ext-ctrls-image-process	45	ext-ctrls-image-process
46	ext-ctrls-codec	46	ext-ctrls-codec
		47	ext-ctrls-codec-stateless
47	ext-ctrls-jpeg	48	ext-ctrls-jpeg
48	ext-ctrls-dv	49	ext-ctrls-dv
49	ext-ctrls-rf-tuner	50	ext-ctrls-rf-tuner

Documentation/userspace-api/media/v4l/dev-mem2mem.rst+1−1

@@ -32,7 +32,7 @@ file handle is visible through another file handle). · 31 unmodified lines
32	One of the most common memory-to-memory device is the codec. Codecs	32	One of the most common memory-to-memory device is the codec. Codecs
33	are more complicated than most and require additional setup for	33	are more complicated than most and require additional setup for
34	their codec parameters. This is done through codec controls.	34	their codec parameters. This is done through codec controls.
35	See :ref:`mpeg-controls`. More details on how to use codec memory-to-memory	35	See :ref:`codec-controls`. More details on how to use codec memory-to-memory
36	devices are given in the following sections.	36	devices are given in the following sections.
37		37
38	.. toctree::	38	.. toctree::

Documentation/userspace-api/media/v4l/ext-ctrls-codec-stateless.rst+793−0

@@ -0,0 +1,793 @@
	1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
	2
	3	.. _codec-stateless-controls:
	4
	5	*********************************
	6	Stateless Codec Control Reference
	7	*********************************
	8
	9	The Stateless Codec control class is intended to support
	10	stateless decoder and encoders (i.e. hardware accelerators).
	11
	12	These drivers are typically supported by the :ref:`stateless_decoder`,
	13	and deal with parsed pixel formats such as V4L2_PIX_FMT_H264_SLICE.
	14
	15	Stateless Codec Control ID
	16	==========================
	17
	18	.. _codec-stateless-control-id:
	19
	20	``V4L2_CID_CODEC_STATELESS_CLASS (class)``
	21	The Stateless Codec class descriptor.
	22
	23	.. _v4l2-codec-stateless-h264:
	24
	25	``V4L2_CID_STATELESS_H264_SPS (struct)``
	26	Specifies the sequence parameter set (as extracted from the
	27	bitstream) for the associated H264 slice data. This includes the
	28	necessary parameters for configuring a stateless hardware decoding
	29	pipeline for H264. The bitstream parameters are defined according
	30	to :ref:`h264`, section 7.4.2.1.1 "Sequence Parameter Set Data
	31	Semantics". For further documentation, refer to the above
	32	specification, unless there is an explicit comment stating
	33	otherwise.
	34
	35	.. c:type:: v4l2_ctrl_h264_sps
	36
	37	.. cssclass:: longtable
	38
	39	.. flat-table:: struct v4l2_ctrl_h264_sps
	40	:header-rows: 0
	41	:stub-columns: 0
	42	:widths: 1 1 2
	43
	44	* - __u8
	45	- ``profile_idc``
	46	-
	47	* - __u8
	48	- ``constraint_set_flags``
	49	- See :ref:`Sequence Parameter Set Constraints Set Flags <h264_sps_constraints_set_flags>`
	50	* - __u8
	51	- ``level_idc``
	52	-
	53	* - __u8
	54	- ``seq_parameter_set_id``
	55	-
	56	* - __u8
	57	- ``chroma_format_idc``
	58	-
	59	* - __u8
	60	- ``bit_depth_luma_minus8``
	61	-
	62	* - __u8
	63	- ``bit_depth_chroma_minus8``
	64	-
	65	* - __u8
	66	- ``log2_max_frame_num_minus4``
	67	-
	68	* - __u8
	69	- ``pic_order_cnt_type``
	70	-
	71	* - __u8
	72	- ``log2_max_pic_order_cnt_lsb_minus4``
	73	-
	74	* - __u8
	75	- ``max_num_ref_frames``
	76	-
	77	* - __u8
	78	- ``num_ref_frames_in_pic_order_cnt_cycle``
	79	-
	80	* - __s32
	81	- ``offset_for_ref_frame[255]``
	82	-
	83	* - __s32
	84	- ``offset_for_non_ref_pic``
	85	-
	86	* - __s32
	87	- ``offset_for_top_to_bottom_field``
	88	-
	89	* - __u16
	90	- ``pic_width_in_mbs_minus1``
	91	-
	92	* - __u16
	93	- ``pic_height_in_map_units_minus1``
	94	-
	95	* - __u32
	96	- ``flags``
	97	- See :ref:`Sequence Parameter Set Flags <h264_sps_flags>`
	98
	99	.. _h264_sps_constraints_set_flags:
	100
	101	``Sequence Parameter Set Constraints Set Flags``
	102
	103	.. cssclass:: longtable
	104
	105	.. flat-table::
	106	:header-rows: 0
	107	:stub-columns: 0
	108	:widths: 1 1 2
	109
	110	* - ``V4L2_H264_SPS_CONSTRAINT_SET0_FLAG``
	111	- 0x00000001
	112	-
	113	* - ``V4L2_H264_SPS_CONSTRAINT_SET1_FLAG``
	114	- 0x00000002
	115	-
	116	* - ``V4L2_H264_SPS_CONSTRAINT_SET2_FLAG``
	117	- 0x00000004
	118	-
	119	* - ``V4L2_H264_SPS_CONSTRAINT_SET3_FLAG``
	120	- 0x00000008
	121	-
	122	* - ``V4L2_H264_SPS_CONSTRAINT_SET4_FLAG``
	123	- 0x00000010
	124	-
	125	* - ``V4L2_H264_SPS_CONSTRAINT_SET5_FLAG``
	126	- 0x00000020
	127	-
	128
	129	.. _h264_sps_flags:
	130
	131	``Sequence Parameter Set Flags``
	132
	133	.. cssclass:: longtable
	134
	135	.. flat-table::
	136	:header-rows: 0
	137	:stub-columns: 0
	138	:widths: 1 1 2
	139
	140	* - ``V4L2_H264_SPS_FLAG_SEPARATE_COLOUR_PLANE``
	141	- 0x00000001
	142	-
	143	* - ``V4L2_H264_SPS_FLAG_QPPRIME_Y_ZERO_TRANSFORM_BYPASS``
	144	- 0x00000002
	145	-
	146	* - ``V4L2_H264_SPS_FLAG_DELTA_PIC_ORDER_ALWAYS_ZERO``
	147	- 0x00000004
	148	-
	149	* - ``V4L2_H264_SPS_FLAG_GAPS_IN_FRAME_NUM_VALUE_ALLOWED``
	150	- 0x00000008
	151	-
	152	* - ``V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY``
	153	- 0x00000010
	154	-
	155	* - ``V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD``
	156	- 0x00000020
	157	-
	158	* - ``V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE``
	159	- 0x00000040
	160	-
	161
	162	``V4L2_CID_STATELESS_H264_PPS (struct)``
	163	Specifies the picture parameter set (as extracted from the
	164	bitstream) for the associated H264 slice data. This includes the
	165	necessary parameters for configuring a stateless hardware decoding
	166	pipeline for H264. The bitstream parameters are defined according
	167	to :ref:`h264`, section 7.4.2.2 "Picture Parameter Set RBSP
	168	Semantics". For further documentation, refer to the above
	169	specification, unless there is an explicit comment stating
	170	otherwise.
	171
	172	.. c:type:: v4l2_ctrl_h264_pps
	173
	174	.. cssclass:: longtable
	175
	176	.. flat-table:: struct v4l2_ctrl_h264_pps
	177	:header-rows: 0
	178	:stub-columns: 0
	179	:widths: 1 1 2
	180
	181	* - __u8
	182	- ``pic_parameter_set_id``
	183	-
	184	* - __u8
	185	- ``seq_parameter_set_id``
	186	-
	187	* - __u8
	188	- ``num_slice_groups_minus1``
	189	-
	190	* - __u8
	191	- ``num_ref_idx_l0_default_active_minus1``
	192	-
	193	* - __u8
	194	- ``num_ref_idx_l1_default_active_minus1``
	195	-
	196	* - __u8
	197	- ``weighted_bipred_idc``
	198	-
	199	* - __s8
	200	- ``pic_init_qp_minus26``
	201	-
	202	* - __s8
	203	- ``pic_init_qs_minus26``
	204	-
	205	* - __s8
	206	- ``chroma_qp_index_offset``
	207	-
	208	* - __s8
	209	- ``second_chroma_qp_index_offset``
	210	-
	211	* - __u16
	212	- ``flags``
	213	- See :ref:`Picture Parameter Set Flags <h264_pps_flags>`
	214
	215	.. _h264_pps_flags:
	216
	217	``Picture Parameter Set Flags``
	218
	219	.. cssclass:: longtable
	220
	221	.. flat-table::
	222	:header-rows: 0
	223	:stub-columns: 0
	224	:widths: 1 1 2
	225
	226	* - ``V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE``
	227	- 0x00000001
	228	-
	229	* - ``V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT``
	230	- 0x00000002
	231	-
	232	* - ``V4L2_H264_PPS_FLAG_WEIGHTED_PRED``
	233	- 0x00000004
	234	-
	235	* - ``V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT``
	236	- 0x00000008
	237	-
	238	* - ``V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED``
	239	- 0x00000010
	240	-
	241	* - ``V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT``
	242	- 0x00000020
	243	-
	244	* - ``V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE``
	245	- 0x00000040
	246	-
	247	* - ``V4L2_H264_PPS_FLAG_SCALING_MATRIX_PRESENT``
	248	- 0x00000080
	249	- Indicates that ``V4L2_CID_STATELESS_H264_SCALING_MATRIX``
	250	must be used for this picture.
	251
	252	``V4L2_CID_STATELESS_H264_SCALING_MATRIX (struct)``
	253	Specifies the scaling matrix (as extracted from the bitstream) for
	254	the associated H264 slice data. The bitstream parameters are
	255	defined according to :ref:`h264`, section 7.4.2.1.1.1 "Scaling
	256	List Semantics". For further documentation, refer to the above
	257	specification, unless there is an explicit comment stating
	258	otherwise.
	259
	260	.. c:type:: v4l2_ctrl_h264_scaling_matrix
	261
	262	.. cssclass:: longtable
	263
	264	.. flat-table:: struct v4l2_ctrl_h264_scaling_matrix
	265	:header-rows: 0
	266	:stub-columns: 0
	267	:widths: 1 1 2
	268
	269	* - __u8
	270	- ``scaling_list_4x4[6][16]``
	271	- Scaling matrix after applying the inverse scanning process.
	272	Expected list order is Intra Y, Intra Cb, Intra Cr, Inter Y,
	273	Inter Cb, Inter Cr. The values on each scaling list are
	274	expected in raster scan order.
	275	* - __u8
	276	- ``scaling_list_8x8[6][64]``
	277	- Scaling matrix after applying the inverse scanning process.
	278	Expected list order is Intra Y, Inter Y, Intra Cb, Inter Cb,
	279	Intra Cr, Inter Cr. The values on each scaling list are
	280	expected in raster scan order.
	281
	282	``V4L2_CID_STATELESS_H264_SLICE_PARAMS (struct)``
	283	Specifies the slice parameters (as extracted from the bitstream)
	284	for the associated H264 slice data. This includes the necessary
	285	parameters for configuring a stateless hardware decoding pipeline
	286	for H264. The bitstream parameters are defined according to
	287	:ref:`h264`, section 7.4.3 "Slice Header Semantics". For further
	288	documentation, refer to the above specification, unless there is
	289	an explicit comment stating otherwise.
	290
	291	.. c:type:: v4l2_ctrl_h264_slice_params
	292
	293	.. cssclass:: longtable
	294
	295	.. flat-table:: struct v4l2_ctrl_h264_slice_params
	296	:header-rows: 0
	297	:stub-columns: 0
	298	:widths: 1 1 2
	299
	300	* - __u32
	301	- ``header_bit_size``
	302	- Offset in bits to slice_data() from the beginning of this slice.
	303	* - __u32
	304	- ``first_mb_in_slice``
	305	-
	306	* - __u8
	307	- ``slice_type``
	308	-
	309	* - __u8
	310	- ``colour_plane_id``
	311	-
	312	* - __u8
	313	- ``redundant_pic_cnt``
	314	-
	315	* - __u8
	316	- ``cabac_init_idc``
	317	-
	318	* - __s8
	319	- ``slice_qp_delta``
	320	-
	321	* - __s8
	322	- ``slice_qs_delta``
	323	-
	324	* - __u8
	325	- ``disable_deblocking_filter_idc``
	326	-
	327	* - __s8
	328	- ``slice_alpha_c0_offset_div2``
	329	-
	330	* - __s8
	331	- ``slice_beta_offset_div2``
	332	-
	333	* - __u8
	334	- ``num_ref_idx_l0_active_minus1``
	335	- If num_ref_idx_active_override_flag is not set, this field must be
	336	set to the value of num_ref_idx_l0_default_active_minus1.
	337	* - __u8
	338	- ``num_ref_idx_l1_active_minus1``
	339	- If num_ref_idx_active_override_flag is not set, this field must be
	340	set to the value of num_ref_idx_l1_default_active_minus1.
	341	* - __u8
	342	- ``reserved``
	343	- Applications and drivers must set this to zero.
	344	* - struct :c:type:`v4l2_h264_reference`
	345	- ``ref_pic_list0[32]``
	346	- Reference picture list after applying the per-slice modifications
	347	* - struct :c:type:`v4l2_h264_reference`
	348	- ``ref_pic_list1[32]``
	349	- Reference picture list after applying the per-slice modifications
	350	* - __u32
	351	- ``flags``
	352	- See :ref:`Slice Parameter Flags <h264_slice_flags>`
	353
	354	.. _h264_slice_flags:
	355
	356	``Slice Parameter Set Flags``
	357
	358	.. cssclass:: longtable
	359
	360	.. flat-table::
	361	:header-rows: 0
	362	:stub-columns: 0
	363	:widths: 1 1 2
	364
	365	* - ``V4L2_H264_SLICE_FLAG_DIRECT_SPATIAL_MV_PRED``
	366	- 0x00000001
	367	-
	368	* - ``V4L2_H264_SLICE_FLAG_SP_FOR_SWITCH``
	369	- 0x00000002
	370	-
	371
	372	``V4L2_CID_STATELESS_H264_PRED_WEIGHTS (struct)``
	373	Prediction weight table defined according to :ref:`h264`,
	374	section 7.4.3.2 "Prediction Weight Table Semantics".
	375	The prediction weight table must be passed by applications
	376	under the conditions explained in section 7.3.3 "Slice header
	377	syntax".
	378
	379	.. c:type:: v4l2_ctrl_h264_pred_weights
	380
	381	.. cssclass:: longtable
	382
	383	.. flat-table:: struct v4l2_ctrl_h264_pred_weights
	384	:header-rows: 0
	385	:stub-columns: 0
	386	:widths: 1 1 2
	387
	388	* - __u16
	389	- ``luma_log2_weight_denom``
	390	-
	391	* - __u16
	392	- ``chroma_log2_weight_denom``
	393	-
	394	* - struct :c:type:`v4l2_h264_weight_factors`
	395	- ``weight_factors[2]``
	396	- The weight factors at index 0 are the weight factors for the reference
	397	list 0, the one at index 1 for the reference list 1.
	398
	399	.. c:type:: v4l2_h264_weight_factors
	400
	401	.. cssclass:: longtable
	402
	403	.. flat-table:: struct v4l2_h264_weight_factors
	404	:header-rows: 0
	405	:stub-columns: 0
	406	:widths: 1 1 2
	407
	408	* - __s16
	409	- ``luma_weight[32]``
	410	-
	411	* - __s16
	412	- ``luma_offset[32]``
	413	-
	414	* - __s16
	415	- ``chroma_weight[32][2]``
	416	-
	417	* - __s16
	418	- ``chroma_offset[32][2]``
	419	-
	420
	421	``Picture Reference``
	422
	423	.. c:type:: v4l2_h264_reference
	424
	425	.. cssclass:: longtable
	426
	427	.. flat-table:: struct v4l2_h264_reference
	428	:header-rows: 0
	429	:stub-columns: 0
	430	:widths: 1 1 2
	431
	432	* - __u8
	433	- ``fields``
	434	- Specifies how the picture is referenced. See :ref:`Reference Fields <h264_ref_fields>`
	435	* - __u8
	436	- ``index``
	437	- Index into the :c:type:`v4l2_ctrl_h264_decode_params`.dpb array.
	438
	439	.. _h264_ref_fields:
	440
	441	``Reference Fields``
	442
	443	.. cssclass:: longtable
	444
	445	.. flat-table::
	446	:header-rows: 0
	447	:stub-columns: 0
	448	:widths: 1 1 2
	449
	450	* - ``V4L2_H264_TOP_FIELD_REF``
	451	- 0x1
	452	- The top field in field pair is used for short-term reference.
	453	* - ``V4L2_H264_BOTTOM_FIELD_REF``
	454	- 0x2
	455	- The bottom field in field pair is used for short-term reference.
	456	* - ``V4L2_H264_FRAME_REF``
	457	- 0x3
	458	- The frame (or the top/bottom fields, if it's a field pair)
	459	is used for short-term reference.
	460
	461	``V4L2_CID_STATELESS_H264_DECODE_PARAMS (struct)``
	462	Specifies the decode parameters (as extracted from the bitstream)
	463	for the associated H264 slice data. This includes the necessary
	464	parameters for configuring a stateless hardware decoding pipeline
	465	for H264. The bitstream parameters are defined according to
	466	:ref:`h264`. For further documentation, refer to the above
	467	specification, unless there is an explicit comment stating
	468	otherwise.
	469
	470	.. c:type:: v4l2_ctrl_h264_decode_params
	471
	472	.. cssclass:: longtable
	473
	474	.. flat-table:: struct v4l2_ctrl_h264_decode_params
	475	:header-rows: 0
	476	:stub-columns: 0
	477	:widths: 1 1 2
	478
	479	* - struct :c:type:`v4l2_h264_dpb_entry`
	480	- ``dpb[16]``
	481	-
	482	* - __u16
	483	- ``nal_ref_idc``
	484	- NAL reference ID value coming from the NAL Unit header
	485	* - __u16
	486	- ``frame_num``
	487	-
	488	* - __s32
	489	- ``top_field_order_cnt``
	490	- Picture Order Count for the coded top field
	491	* - __s32
	492	- ``bottom_field_order_cnt``
	493	- Picture Order Count for the coded bottom field
	494	* - __u16
	495	- ``idr_pic_id``
	496	-
	497	* - __u16
	498	- ``pic_order_cnt_lsb``
	499	-
	500	* - __s32
	501	- ``delta_pic_order_cnt_bottom``
	502	-
	503	* - __s32
	504	- ``delta_pic_order_cnt0``
	505	-
	506	* - __s32
	507	- ``delta_pic_order_cnt1``
	508	-
	509	* - __u32
	510	- ``dec_ref_pic_marking_bit_size``
	511	- Size in bits of the dec_ref_pic_marking() syntax element.
	512	* - __u32
	513	- ``pic_order_cnt_bit_size``
	514	- Combined size in bits of the picture order count related syntax
	515	elements: pic_order_cnt_lsb, delta_pic_order_cnt_bottom,
	516	delta_pic_order_cnt0, and delta_pic_order_cnt1.
	517	* - __u32
	518	- ``slice_group_change_cycle``
	519	-
	520	* - __u32
	521	- ``reserved``
	522	- Applications and drivers must set this to zero.
	523	* - __u32
	524	- ``flags``
	525	- See :ref:`Decode Parameters Flags <h264_decode_params_flags>`
	526
	527	.. _h264_decode_params_flags:
	528
	529	``Decode Parameters Flags``
	530
	531	.. cssclass:: longtable
	532
	533	.. flat-table::
	534	:header-rows: 0
	535	:stub-columns: 0
	536	:widths: 1 1 2
	537
	538	* - ``V4L2_H264_DECODE_PARAM_FLAG_IDR_PIC``
	539	- 0x00000001
	540	- That picture is an IDR picture
	541	* - ``V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC``
	542	- 0x00000002
	543	-
	544	* - ``V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD``
	545	- 0x00000004
	546	-
	547
	548	.. c:type:: v4l2_h264_dpb_entry
	549
	550	.. cssclass:: longtable
	551
	552	.. flat-table:: struct v4l2_h264_dpb_entry
	553	:header-rows: 0
	554	:stub-columns: 0
	555	:widths: 1 1 2
	556
	557	* - __u64
	558	- ``reference_ts``
	559	- Timestamp of the V4L2 capture buffer to use as reference, used
	560	with B-coded and P-coded frames. The timestamp refers to the
	561	``timestamp`` field in struct :c:type:`v4l2_buffer`. Use the
	562	:c:func:`v4l2_timeval_to_ns()` function to convert the struct
	563	:c:type:`timeval` in struct :c:type:`v4l2_buffer` to a __u64.
	564	* - __u32
	565	- ``pic_num``
	566	-
	567	* - __u16
	568	- ``frame_num``
	569	-
	570	* - __u8
	571	- ``fields``
	572	- Specifies how the DPB entry is referenced. See :ref:`Reference Fields <h264_ref_fields>`
	573	* - __u8
	574	- ``reserved[5]``
	575	- Applications and drivers must set this to zero.
	576	* - __s32
	577	- ``top_field_order_cnt``
	578	-
	579	* - __s32
	580	- ``bottom_field_order_cnt``
	581	-
	582	* - __u32
	583	- ``flags``
	584	- See :ref:`DPB Entry Flags <h264_dpb_flags>`
	585
	586	.. _h264_dpb_flags:
	587
	588	``DPB Entries Flags``
	589
	590	.. cssclass:: longtable
	591
	592	.. flat-table::
	593	:header-rows: 0
	594	:stub-columns: 0
	595	:widths: 1 1 2
	596
	597	* - ``V4L2_H264_DPB_ENTRY_FLAG_VALID``
	598	- 0x00000001
	599	- The DPB entry is valid (non-empty) and should be considered.
	600	* - ``V4L2_H264_DPB_ENTRY_FLAG_ACTIVE``
	601	- 0x00000002
	602	- The DPB entry is used for reference.
	603	* - ``V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM``
	604	- 0x00000004
	605	- The DPB entry is used for long-term reference.
	606	* - ``V4L2_H264_DPB_ENTRY_FLAG_FIELD``
	607	- 0x00000008
	608	- The DPB entry is a single field or a complementary field pair.
	609
	610	``V4L2_CID_STATELESS_H264_DECODE_MODE (enum)``
	611	Specifies the decoding mode to use. Currently exposes slice-based and
	612	frame-based decoding but new modes might be added later on.
	613	This control is used as a modifier for V4L2_PIX_FMT_H264_SLICE
	614	pixel format. Applications that support V4L2_PIX_FMT_H264_SLICE
	615	are required to set this control in order to specify the decoding mode
	616	that is expected for the buffer.
	617	Drivers may expose a single or multiple decoding modes, depending
	618	on what they can support.
	619
	620	.. c:type:: v4l2_stateless_h264_decode_mode
	621
	622	.. cssclass:: longtable
	623
	624	.. flat-table::
	625	:header-rows: 0
	626	:stub-columns: 0
	627	:widths: 1 1 2
	628
	629	* - ``V4L2_STATELESS_H264_DECODE_MODE_SLICE_BASED``
	630	- 0
	631	- Decoding is done at the slice granularity.
	632	The OUTPUT buffer must contain a single slice.
	633	When this mode is selected, the ``V4L2_CID_STATELESS_H264_SLICE_PARAMS``
	634	control shall be set. When multiple slices compose a frame,
	635	use of ``V4L2_BUF_CAP_SUPPORTS_M2M_HOLD_CAPTURE_BUF`` flag
	636	is required.
	637	* - ``V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED``
	638	- 1
	639	- Decoding is done at the frame granularity,
	640	The OUTPUT buffer must contain all slices needed to decode the
	641	frame. The OUTPUT buffer must also contain both fields.
	642	This mode will be supported by devices that
	643	parse the slice(s) header(s) in hardware. When this mode is
	644	selected, the ``V4L2_CID_STATELESS_H264_SLICE_PARAMS``
	645	control shall not be set.
	646
	647	``V4L2_CID_STATELESS_H264_START_CODE (enum)``
	648	Specifies the H264 slice start code expected for each slice.
	649	This control is used as a modifier for V4L2_PIX_FMT_H264_SLICE
	650	pixel format. Applications that support V4L2_PIX_FMT_H264_SLICE
	651	are required to set this control in order to specify the start code
	652	that is expected for the buffer.
	653	Drivers may expose a single or multiple start codes, depending
	654	on what they can support.
	655
	656	.. c:type:: v4l2_stateless_h264_start_code
	657
	658	.. cssclass:: longtable
	659
	660	.. flat-table::
	661	:header-rows: 0
	662	:stub-columns: 0
	663	:widths: 1 1 2
	664
	665	* - ``V4L2_STATELESS_H264_START_CODE_NONE``
	666	- 0
	667	- Selecting this value specifies that H264 slices are passed
	668	to the driver without any start code.
	669	* - ``V4L2_STATELESS_H264_START_CODE_ANNEX_B``
	670	- 1
	671	- Selecting this value specifies that H264 slices are expected
	672	to be prefixed by Annex B start codes. According to :ref:`h264`
	673	valid start codes can be 3-bytes 0x000001 or 4-bytes 0x00000001.
	674
	675
	676	.. _codec-stateless-fwht:
	677
	678	``V4L2_CID_STATELESS_FWHT_PARAMS (struct)``
	679	Specifies the FWHT (Fast Walsh Hadamard Transform) parameters (as extracted
	680	from the bitstream) for the associated FWHT data. This includes the necessary
	681	parameters for configuring a stateless hardware decoding pipeline for FWHT.
	682	This codec is specific to the vicodec test driver.
	683
	684	.. c:type:: v4l2_ctrl_fwht_params
	685
	686	.. cssclass:: longtable
	687
	688	.. tabularcolumns:: \|p{1.4cm}\|p{4.3cm}\|p{11.8cm}\|
	689
	690	.. flat-table:: struct v4l2_ctrl_fwht_params
	691	:header-rows: 0
	692	:stub-columns: 0
	693	:widths: 1 1 2
	694
	695	* - __u64
	696	- ``backward_ref_ts``
	697	- Timestamp of the V4L2 capture buffer to use as backward reference, used
	698	with P-coded frames. The timestamp refers to the
	699	``timestamp`` field in struct :c:type:`v4l2_buffer`. Use the
	700	:c:func:`v4l2_timeval_to_ns()` function to convert the struct
	701	:c:type:`timeval` in struct :c:type:`v4l2_buffer` to a __u64.
	702	* - __u32
	703	- ``version``
	704	- The version of the codec. Set to ``V4L2_FWHT_VERSION``.
	705	* - __u32
	706	- ``width``
	707	- The width of the frame.
	708	* - __u32
	709	- ``height``
	710	- The height of the frame.
	711	* - __u32
	712	- ``flags``
	713	- The flags of the frame, see :ref:`fwht-flags`.
	714	* - __u32
	715	- ``colorspace``
	716	- The colorspace of the frame, from enum :c:type:`v4l2_colorspace`.
	717	* - __u32
	718	- ``xfer_func``
	719	- The transfer function, from enum :c:type:`v4l2_xfer_func`.
	720	* - __u32
	721	- ``ycbcr_enc``
	722	- The Y'CbCr encoding, from enum :c:type:`v4l2_ycbcr_encoding`.
	723	* - __u32
	724	- ``quantization``
	725	- The quantization range, from enum :c:type:`v4l2_quantization`.
	726
	727
	728
	729	.. _fwht-flags:
	730
	731	FWHT Flags
	732	==========
	733
	734	.. cssclass:: longtable
	735
	736	.. tabularcolumns:: \|p{6.8cm}\|p{2.4cm}\|p{8.3cm}\|
	737
	738	.. flat-table::
	739	:header-rows: 0
	740	:stub-columns: 0
	741	:widths: 3 1 4
	742
	743	* - ``V4L2_FWHT_FL_IS_INTERLACED``
	744	- 0x00000001
	745	- Set if this is an interlaced format.
	746	* - ``V4L2_FWHT_FL_IS_BOTTOM_FIRST``
	747	- 0x00000002
	748	- Set if this is a bottom-first (NTSC) interlaced format.
	749	* - ``V4L2_FWHT_FL_IS_ALTERNATE``
	750	- 0x00000004
	751	- Set if each 'frame' contains just one field.
	752	* - ``V4L2_FWHT_FL_IS_BOTTOM_FIELD``
	753	- 0x00000008
	754	- If V4L2_FWHT_FL_IS_ALTERNATE was set, then this is set if this 'frame' is the
	755	bottom field, else it is the top field.
	756	* - ``V4L2_FWHT_FL_LUMA_IS_UNCOMPRESSED``
	757	- 0x00000010
	758	- Set if the Y' (luma) plane is uncompressed.
	759	* - ``V4L2_FWHT_FL_CB_IS_UNCOMPRESSED``
	760	- 0x00000020
	761	- Set if the Cb plane is uncompressed.
	762	* - ``V4L2_FWHT_FL_CR_IS_UNCOMPRESSED``
	763	- 0x00000040
	764	- Set if the Cr plane is uncompressed.
	765	* - ``V4L2_FWHT_FL_CHROMA_FULL_HEIGHT``
	766	- 0x00000080
	767	- Set if the chroma plane has the same height as the luma plane,
	768	else the chroma plane is half the height of the luma plane.
	769	* - ``V4L2_FWHT_FL_CHROMA_FULL_WIDTH``
	770	- 0x00000100
	771	- Set if the chroma plane has the same width as the luma plane,
	772	else the chroma plane is half the width of the luma plane.
	773	* - ``V4L2_FWHT_FL_ALPHA_IS_UNCOMPRESSED``
	774	- 0x00000200
	775	- Set if the alpha plane is uncompressed.
	776	* - ``V4L2_FWHT_FL_I_FRAME``
	777	- 0x00000400
	778	- Set if this is an I-frame.
	779	* - ``V4L2_FWHT_FL_COMPONENTS_NUM_MSK``
	780	- 0x00070000
	781	- The number of color components - 1.
	782	* - ``V4L2_FWHT_FL_PIXENC_MSK``
	783	- 0x00180000
	784	- The mask for the pixel encoding.
	785	* - ``V4L2_FWHT_FL_PIXENC_YUV``
	786	- 0x00080000
	787	- Set if the pixel encoding is YUV.
	788	* - ``V4L2_FWHT_FL_PIXENC_RGB``
	789	- 0x00100000
	790	- Set if the pixel encoding is RGB.
	791	* - ``V4L2_FWHT_FL_PIXENC_HSV``
	792	- 0x00180000
	793	- Set if the pixel encoding is HSV.

Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst+2−815

@@ -1,6 +1,6 @@
1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later	1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
2		2
3	.. _mpeg-controls:	3	.. _codec-controls:
4		4
5	***********************	5	***********************
6	Codec Control Reference	6	Codec Control Reference
@@ -26,7 +26,7 @@ Generic Codec Controls · 19 unmodified lines
26	Codec Control IDs	26	Codec Control IDs
27	-----------------	27	-----------------
28		28
29	``V4L2_CID_MPEG_CLASS (class)``	29	``V4L2_CID_CODEC_CLASS (class)``
30	The Codec class descriptor. Calling	30	The Codec class descriptor. Calling
31	:ref:`VIDIOC_QUERYCTRL` for this control will	31	:ref:`VIDIOC_QUERYCTRL` for this control will
32	return a description of this control class. This description can be	32	return a description of this control class. This description can be
@@ -1502,698 +1502,6 @@ enum v4l2_mpeg_video_h264_hierarchical_coding_type - · 1469 unmodified lines
1502	- Layer number	1502	- Layer number
1503		1503
1504		1504
1505	.. _v4l2-mpeg-h264:
1506
1507	``V4L2_CID_MPEG_VIDEO_H264_SPS (struct)``
1508	Specifies the sequence parameter set (as extracted from the
1509	bitstream) for the associated H264 slice data. This includes the
1510	necessary parameters for configuring a stateless hardware decoding
1511	pipeline for H264. The bitstream parameters are defined according
1512	to :ref:`h264`, section 7.4.2.1.1 "Sequence Parameter Set Data
1513	Semantics". For further documentation, refer to the above
1514	specification, unless there is an explicit comment stating
1515	otherwise.
1516
1517	.. note::
1518
1519	This compound control is not yet part of the public kernel API and
1520	it is expected to change.
1521
1522	.. c:type:: v4l2_ctrl_h264_sps
1523
1524	.. cssclass:: longtable
1525
1526	.. flat-table:: struct v4l2_ctrl_h264_sps
1527	:header-rows: 0
1528	:stub-columns: 0
1529	:widths: 1 1 2
1530
1531	* - __u8
1532	- ``profile_idc``
1533	-
1534	* - __u8
1535	- ``constraint_set_flags``
1536	- See :ref:`Sequence Parameter Set Constraints Set Flags <h264_sps_constraints_set_flags>`
1537	* - __u8
1538	- ``level_idc``
1539	-
1540	* - __u8
1541	- ``seq_parameter_set_id``
1542	-
1543	* - __u8
1544	- ``chroma_format_idc``
1545	-
1546	* - __u8
1547	- ``bit_depth_luma_minus8``
1548	-
1549	* - __u8
1550	- ``bit_depth_chroma_minus8``
1551	-
1552	* - __u8
1553	- ``log2_max_frame_num_minus4``
1554	-
1555	* - __u8
1556	- ``pic_order_cnt_type``
1557	-
1558	* - __u8
1559	- ``log2_max_pic_order_cnt_lsb_minus4``
1560	-
1561	* - __u8
1562	- ``max_num_ref_frames``
1563	-
1564	* - __u8
1565	- ``num_ref_frames_in_pic_order_cnt_cycle``
1566	-
1567	* - __s32
1568	- ``offset_for_ref_frame[255]``
1569	-
1570	* - __s32
1571	- ``offset_for_non_ref_pic``
1572	-
1573	* - __s32
1574	- ``offset_for_top_to_bottom_field``
1575	-
1576	* - __u16
1577	- ``pic_width_in_mbs_minus1``
1578	-
1579	* - __u16
1580	- ``pic_height_in_map_units_minus1``
1581	-
1582	* - __u32
1583	- ``flags``
1584	- See :ref:`Sequence Parameter Set Flags <h264_sps_flags>`
1585
1586	.. _h264_sps_constraints_set_flags:
1587
1588	``Sequence Parameter Set Constraints Set Flags``
1589
1590	.. cssclass:: longtable
1591
1592	.. flat-table::
1593	:header-rows: 0
1594	:stub-columns: 0
1595	:widths: 1 1 2
1596
1597	* - ``V4L2_H264_SPS_CONSTRAINT_SET0_FLAG``
1598	- 0x00000001
1599	-
1600	* - ``V4L2_H264_SPS_CONSTRAINT_SET1_FLAG``
1601	- 0x00000002
1602	-
1603	* - ``V4L2_H264_SPS_CONSTRAINT_SET2_FLAG``
1604	- 0x00000004
1605	-
1606	* - ``V4L2_H264_SPS_CONSTRAINT_SET3_FLAG``
1607	- 0x00000008
1608	-
1609	* - ``V4L2_H264_SPS_CONSTRAINT_SET4_FLAG``
1610	- 0x00000010
1611	-
1612	* - ``V4L2_H264_SPS_CONSTRAINT_SET5_FLAG``
1613	- 0x00000020
1614	-
1615
1616	.. _h264_sps_flags:
1617
1618	``Sequence Parameter Set Flags``
1619
1620	.. cssclass:: longtable
1621
1622	.. flat-table::
1623	:header-rows: 0
1624	:stub-columns: 0
1625	:widths: 1 1 2
1626
1627	* - ``V4L2_H264_SPS_FLAG_SEPARATE_COLOUR_PLANE``
1628	- 0x00000001
1629	-
1630	* - ``V4L2_H264_SPS_FLAG_QPPRIME_Y_ZERO_TRANSFORM_BYPASS``
1631	- 0x00000002
1632	-
1633	* - ``V4L2_H264_SPS_FLAG_DELTA_PIC_ORDER_ALWAYS_ZERO``
1634	- 0x00000004
1635	-
1636	* - ``V4L2_H264_SPS_FLAG_GAPS_IN_FRAME_NUM_VALUE_ALLOWED``
1637	- 0x00000008
1638	-
1639	* - ``V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY``
1640	- 0x00000010
1641	-
1642	* - ``V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD``
1643	- 0x00000020
1644	-
1645	* - ``V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE``
1646	- 0x00000040
1647	-
1648
1649	``V4L2_CID_MPEG_VIDEO_H264_PPS (struct)``
1650	Specifies the picture parameter set (as extracted from the
1651	bitstream) for the associated H264 slice data. This includes the
1652	necessary parameters for configuring a stateless hardware decoding
1653	pipeline for H264. The bitstream parameters are defined according
1654	to :ref:`h264`, section 7.4.2.2 "Picture Parameter Set RBSP
1655	Semantics". For further documentation, refer to the above
1656	specification, unless there is an explicit comment stating
1657	otherwise.
1658
1659	.. note::
1660
1661	This compound control is not yet part of the public kernel API and
1662	it is expected to change.
1663
1664	.. c:type:: v4l2_ctrl_h264_pps
1665
1666	.. cssclass:: longtable
1667
1668	.. flat-table:: struct v4l2_ctrl_h264_pps
1669	:header-rows: 0
1670	:stub-columns: 0
1671	:widths: 1 1 2
1672
1673	* - __u8
1674	- ``pic_parameter_set_id``
1675	-
1676	* - __u8
1677	- ``seq_parameter_set_id``
1678	-
1679	* - __u8
1680	- ``num_slice_groups_minus1``
1681	-
1682	* - __u8
1683	- ``num_ref_idx_l0_default_active_minus1``
1684	-
1685	* - __u8
1686	- ``num_ref_idx_l1_default_active_minus1``
1687	-
1688	* - __u8
1689	- ``weighted_bipred_idc``
1690	-
1691	* - __s8
1692	- ``pic_init_qp_minus26``
1693	-
1694	* - __s8
1695	- ``pic_init_qs_minus26``
1696	-
1697	* - __s8
1698	- ``chroma_qp_index_offset``
1699	-
1700	* - __s8
1701	- ``second_chroma_qp_index_offset``
1702	-
1703	* - __u16
1704	- ``flags``
1705	- See :ref:`Picture Parameter Set Flags <h264_pps_flags>`
1706
1707	.. _h264_pps_flags:
1708
1709	``Picture Parameter Set Flags``
1710
1711	.. cssclass:: longtable
1712
1713	.. flat-table::
1714	:header-rows: 0
1715	:stub-columns: 0
1716	:widths: 1 1 2
1717
1718	* - ``V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE``
1719	- 0x00000001
1720	-
1721	* - ``V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT``
1722	- 0x00000002
1723	-
1724	* - ``V4L2_H264_PPS_FLAG_WEIGHTED_PRED``
1725	- 0x00000004
1726	-
1727	* - ``V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT``
1728	- 0x00000008
1729	-
1730	* - ``V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED``
1731	- 0x00000010
1732	-
1733	* - ``V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT``
1734	- 0x00000020
1735	-
1736	* - ``V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE``
1737	- 0x00000040
1738	-
1739	* - ``V4L2_H264_PPS_FLAG_SCALING_MATRIX_PRESENT``
1740	- 0x00000080
1741	- Indicates that ``V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX``
1742	must be used for this picture.
1743
1744	``V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX (struct)``
1745	Specifies the scaling matrix (as extracted from the bitstream) for
1746	the associated H264 slice data. The bitstream parameters are
1747	defined according to :ref:`h264`, section 7.4.2.1.1.1 "Scaling
1748	List Semantics". For further documentation, refer to the above
1749	specification, unless there is an explicit comment stating
1750	otherwise.
1751
1752	.. note::
1753
1754	This compound control is not yet part of the public kernel API and
1755	it is expected to change.
1756
1757	.. c:type:: v4l2_ctrl_h264_scaling_matrix
1758
1759	.. cssclass:: longtable
1760
1761	.. flat-table:: struct v4l2_ctrl_h264_scaling_matrix
1762	:header-rows: 0
1763	:stub-columns: 0
1764	:widths: 1 1 2
1765
1766	* - __u8
1767	- ``scaling_list_4x4[6][16]``
1768	- Scaling matrix after applying the inverse scanning process.
1769	Expected list order is Intra Y, Intra Cb, Intra Cr, Inter Y,
1770	Inter Cb, Inter Cr. The values on each scaling list are
1771	expected in raster scan order.
1772	* - __u8
1773	- ``scaling_list_8x8[6][64]``
1774	- Scaling matrix after applying the inverse scanning process.
1775	Expected list order is Intra Y, Inter Y, Intra Cb, Inter Cb,
1776	Intra Cr, Inter Cr. The values on each scaling list are
1777	expected in raster scan order.
1778
1779	``V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS (struct)``
1780	Specifies the slice parameters (as extracted from the bitstream)
1781	for the associated H264 slice data. This includes the necessary
1782	parameters for configuring a stateless hardware decoding pipeline
1783	for H264. The bitstream parameters are defined according to
1784	:ref:`h264`, section 7.4.3 "Slice Header Semantics". For further
1785	documentation, refer to the above specification, unless there is
1786	an explicit comment stating otherwise.
1787
1788	.. note::
1789
1790	This compound control is not yet part of the public kernel API
1791	and it is expected to change.
1792
1793	.. c:type:: v4l2_ctrl_h264_slice_params
1794
1795	.. cssclass:: longtable
1796
1797	.. flat-table:: struct v4l2_ctrl_h264_slice_params
1798	:header-rows: 0
1799	:stub-columns: 0
1800	:widths: 1 1 2
1801
1802	* - __u32
1803	- ``header_bit_size``
1804	- Offset in bits to slice_data() from the beginning of this slice.
1805	* - __u32
1806	- ``first_mb_in_slice``
1807	-
1808	* - __u8
1809	- ``slice_type``
1810	-
1811	* - __u8
1812	- ``colour_plane_id``
1813	-
1814	* - __u8
1815	- ``redundant_pic_cnt``
1816	-
1817	* - __u8
1818	- ``cabac_init_idc``
1819	-
1820	* - __s8
1821	- ``slice_qp_delta``
1822	-
1823	* - __s8
1824	- ``slice_qs_delta``
1825	-
1826	* - __u8
1827	- ``disable_deblocking_filter_idc``
1828	-
1829	* - __s8
1830	- ``slice_alpha_c0_offset_div2``
1831	-
1832	* - __s8
1833	- ``slice_beta_offset_div2``
1834	-
1835	* - __u8
1836	- ``num_ref_idx_l0_active_minus1``
1837	- If num_ref_idx_active_override_flag is not set, this field must be
1838	set to the value of num_ref_idx_l0_default_active_minus1.
1839	* - __u8
1840	- ``num_ref_idx_l1_active_minus1``
1841	- If num_ref_idx_active_override_flag is not set, this field must be
1842	set to the value of num_ref_idx_l1_default_active_minus1.
1843	* - __u8
1844	- ``reserved``
1845	- Applications and drivers must set this to zero.
1846	* - struct :c:type:`v4l2_h264_reference`
1847	- ``ref_pic_list0[32]``
1848	- Reference picture list after applying the per-slice modifications
1849	* - struct :c:type:`v4l2_h264_reference`
1850	- ``ref_pic_list1[32]``
1851	- Reference picture list after applying the per-slice modifications
1852	* - __u32
1853	- ``flags``
1854	- See :ref:`Slice Parameter Flags <h264_slice_flags>`
1855
1856	.. _h264_slice_flags:
1857
1858	``Slice Parameter Set Flags``
1859
1860	.. cssclass:: longtable
1861
1862	.. flat-table::
1863	:header-rows: 0
1864	:stub-columns: 0
1865	:widths: 1 1 2
1866
1867	* - ``V4L2_H264_SLICE_FLAG_DIRECT_SPATIAL_MV_PRED``
1868	- 0x00000001
1869	-
1870	* - ``V4L2_H264_SLICE_FLAG_SP_FOR_SWITCH``
1871	- 0x00000002
1872	-
1873
1874	``V4L2_CID_MPEG_VIDEO_H264_PRED_WEIGHTS (struct)``
1875	Prediction weight table defined according to :ref:`h264`,
1876	section 7.4.3.2 "Prediction Weight Table Semantics".
1877	The prediction weight table must be passed by applications
1878	under the conditions explained in section 7.3.3 "Slice header
1879	syntax".
1880
1881	.. note::
1882
1883	This compound control is not yet part of the public kernel API and
1884	it is expected to change.
1885
1886	.. c:type:: v4l2_ctrl_h264_pred_weights
1887
1888	.. cssclass:: longtable
1889
1890	.. flat-table:: struct v4l2_ctrl_h264_pred_weights
1891	:header-rows: 0
1892	:stub-columns: 0
1893	:widths: 1 1 2
1894
1895	* - __u16
1896	- ``luma_log2_weight_denom``
1897	-
1898	* - __u16
1899	- ``chroma_log2_weight_denom``
1900	-
1901	* - struct :c:type:`v4l2_h264_weight_factors`
1902	- ``weight_factors[2]``
1903	- The weight factors at index 0 are the weight factors for the reference
1904	list 0, the one at index 1 for the reference list 1.
1905
1906	.. c:type:: v4l2_h264_weight_factors
1907
1908	.. cssclass:: longtable
1909
1910	.. flat-table:: struct v4l2_h264_weight_factors
1911	:header-rows: 0
1912	:stub-columns: 0
1913	:widths: 1 1 2
1914
1915	* - __s16
1916	- ``luma_weight[32]``
1917	-
1918	* - __s16
1919	- ``luma_offset[32]``
1920	-
1921	* - __s16
1922	- ``chroma_weight[32][2]``
1923	-
1924	* - __s16
1925	- ``chroma_offset[32][2]``
1926	-
1927
1928	``Picture Reference``
1929
1930	.. c:type:: v4l2_h264_reference
1931
1932	.. cssclass:: longtable
1933
1934	.. flat-table:: struct v4l2_h264_reference
1935	:header-rows: 0
1936	:stub-columns: 0
1937	:widths: 1 1 2
1938
1939	* - __u8
1940	- ``fields``
1941	- Specifies how the picture is referenced. See :ref:`Reference Fields <h264_ref_fields>`
1942	* - __u8
1943	- ``index``
1944	- Index into the :c:type:`v4l2_ctrl_h264_decode_params`.dpb array.
1945
1946	.. _h264_ref_fields:
1947
1948	``Reference Fields``
1949
1950	.. cssclass:: longtable
1951
1952	.. flat-table::
1953	:header-rows: 0
1954	:stub-columns: 0
1955	:widths: 1 1 2
1956
1957	* - ``V4L2_H264_TOP_FIELD_REF``
1958	- 0x1
1959	- The top field in field pair is used for short-term reference.
1960	* - ``V4L2_H264_BOTTOM_FIELD_REF``
1961	- 0x2
1962	- The bottom field in field pair is used for short-term reference.
1963	* - ``V4L2_H264_FRAME_REF``
1964	- 0x3
1965	- The frame (or the top/bottom fields, if it's a field pair)
1966	is used for short-term reference.
1967
1968	``V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS (struct)``
1969	Specifies the decode parameters (as extracted from the bitstream)
1970	for the associated H264 slice data. This includes the necessary
1971	parameters for configuring a stateless hardware decoding pipeline
1972	for H264. The bitstream parameters are defined according to
1973	:ref:`h264`. For further documentation, refer to the above
1974	specification, unless there is an explicit comment stating
1975	otherwise.
1976
1977	.. note::
1978
1979	This compound control is not yet part of the public kernel API and
1980	it is expected to change.
1981
1982	.. c:type:: v4l2_ctrl_h264_decode_params
1983
1984	.. cssclass:: longtable
1985
1986	.. flat-table:: struct v4l2_ctrl_h264_decode_params
1987	:header-rows: 0
1988	:stub-columns: 0
1989	:widths: 1 1 2
1990
1991	* - struct :c:type:`v4l2_h264_dpb_entry`
1992	- ``dpb[16]``
1993	-
1994	* - __u16
1995	- ``nal_ref_idc``
1996	- NAL reference ID value coming from the NAL Unit header
1997	* - __u16
1998	- ``frame_num``
1999	-
2000	* - __s32
2001	- ``top_field_order_cnt``
2002	- Picture Order Count for the coded top field
2003	* - __s32
2004	- ``bottom_field_order_cnt``
2005	- Picture Order Count for the coded bottom field
2006	* - __u16
2007	- ``idr_pic_id``
2008	-
2009	* - __u16
2010	- ``pic_order_cnt_lsb``
2011	-
2012	* - __s32
2013	- ``delta_pic_order_cnt_bottom``
2014	-
2015	* - __s32
2016	- ``delta_pic_order_cnt0``
2017	-
2018	* - __s32
2019	- ``delta_pic_order_cnt1``
2020	-
2021	* - __u32
2022	- ``dec_ref_pic_marking_bit_size``
2023	- Size in bits of the dec_ref_pic_marking() syntax element.
2024	* - __u32
2025	- ``pic_order_cnt_bit_size``
2026	- Combined size in bits of the picture order count related syntax
2027	elements: pic_order_cnt_lsb, delta_pic_order_cnt_bottom,
2028	delta_pic_order_cnt0, and delta_pic_order_cnt1.
2029	* - __u32
2030	- ``slice_group_change_cycle``
2031	-
2032	* - __u32
2033	- ``reserved``
2034	- Applications and drivers must set this to zero.
2035	* - __u32
2036	- ``flags``
2037	- See :ref:`Decode Parameters Flags <h264_decode_params_flags>`
2038
2039	.. _h264_decode_params_flags:
2040
2041	``Decode Parameters Flags``
2042
2043	.. cssclass:: longtable
2044
2045	.. flat-table::
2046	:header-rows: 0
2047	:stub-columns: 0
2048	:widths: 1 1 2
2049
2050	* - ``V4L2_H264_DECODE_PARAM_FLAG_IDR_PIC``
2051	- 0x00000001
2052	- That picture is an IDR picture
2053	* - ``V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC``
2054	- 0x00000002
2055	-
2056	* - ``V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD``
2057	- 0x00000004
2058	-
2059
2060	.. c:type:: v4l2_h264_dpb_entry
2061
2062	.. cssclass:: longtable
2063
2064	.. flat-table:: struct v4l2_h264_dpb_entry
2065	:header-rows: 0
2066	:stub-columns: 0
2067	:widths: 1 1 2
2068
2069	* - __u64
2070	- ``reference_ts``
2071	- Timestamp of the V4L2 capture buffer to use as reference, used
2072	with B-coded and P-coded frames. The timestamp refers to the
2073	``timestamp`` field in struct :c:type:`v4l2_buffer`. Use the
2074	:c:func:`v4l2_timeval_to_ns()` function to convert the struct
2075	:c:type:`timeval` in struct :c:type:`v4l2_buffer` to a __u64.
2076	* - __u32
2077	- ``pic_num``
2078	-
2079	* - __u16
2080	- ``frame_num``
2081	-
2082	* - __u8
2083	- ``fields``
2084	- Specifies how the DPB entry is referenced. See :ref:`Reference Fields <h264_ref_fields>`
2085	* - __u8
2086	- ``reserved[5]``
2087	- Applications and drivers must set this to zero.
2088	* - __s32
2089	- ``top_field_order_cnt``
2090	-
2091	* - __s32
2092	- ``bottom_field_order_cnt``
2093	-
2094	* - __u32
2095	- ``flags``
2096	- See :ref:`DPB Entry Flags <h264_dpb_flags>`
2097
2098	.. _h264_dpb_flags:
2099
2100	``DPB Entries Flags``
2101
2102	.. cssclass:: longtable
2103
2104	.. flat-table::
2105	:header-rows: 0
2106	:stub-columns: 0
2107	:widths: 1 1 2
2108
2109	* - ``V4L2_H264_DPB_ENTRY_FLAG_VALID``
2110	- 0x00000001
2111	- The DPB entry is valid (non-empty) and should be considered.
2112	* - ``V4L2_H264_DPB_ENTRY_FLAG_ACTIVE``
2113	- 0x00000002
2114	- The DPB entry is used for reference.
2115	* - ``V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM``
2116	- 0x00000004
2117	- The DPB entry is used for long-term reference.
2118	* - ``V4L2_H264_DPB_ENTRY_FLAG_FIELD``
2119	- 0x00000008
2120	- The DPB entry is a single field or a complementary field pair.
2121
2122	``V4L2_CID_MPEG_VIDEO_H264_DECODE_MODE (enum)``
2123	Specifies the decoding mode to use. Currently exposes slice-based and
2124	frame-based decoding but new modes might be added later on.
2125	This control is used as a modifier for V4L2_PIX_FMT_H264_SLICE
2126	pixel format. Applications that support V4L2_PIX_FMT_H264_SLICE
2127	are required to set this control in order to specify the decoding mode
2128	that is expected for the buffer.
2129	Drivers may expose a single or multiple decoding modes, depending
2130	on what they can support.
2131
2132	.. note::
2133
2134	This menu control is not yet part of the public kernel API and
2135	it is expected to change.
2136
2137	.. c:type:: v4l2_mpeg_video_h264_decode_mode
2138
2139	.. cssclass:: longtable
2140
2141	.. flat-table::
2142	:header-rows: 0
2143	:stub-columns: 0
2144	:widths: 1 1 2
2145
2146	* - ``V4L2_MPEG_VIDEO_H264_DECODE_MODE_SLICE_BASED``
2147	- 0
2148	- Decoding is done at the slice granularity.
2149	The OUTPUT buffer must contain a single slice.
2150	When this mode is selected, the ``V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS``
2151	control shall be set. When multiple slices compose a frame,
2152	use of ``V4L2_BUF_CAP_SUPPORTS_M2M_HOLD_CAPTURE_BUF`` flag
2153	is required.
2154	* - ``V4L2_MPEG_VIDEO_H264_DECODE_MODE_FRAME_BASED``
2155	- 1
2156	- Decoding is done at the frame granularity,
2157	The OUTPUT buffer must contain all slices needed to decode the
2158	frame. The OUTPUT buffer must also contain both fields.
2159	This mode will be supported by devices that
2160	parse the slice(s) header(s) in hardware. When this mode is
2161	selected, the ``V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS``
2162	control shall not be set.
2163
2164	``V4L2_CID_MPEG_VIDEO_H264_START_CODE (enum)``
2165	Specifies the H264 slice start code expected for each slice.
2166	This control is used as a modifier for V4L2_PIX_FMT_H264_SLICE
2167	pixel format. Applications that support V4L2_PIX_FMT_H264_SLICE
2168	are required to set this control in order to specify the start code
2169	that is expected for the buffer.
2170	Drivers may expose a single or multiple start codes, depending
2171	on what they can support.
2172
2173	.. note::
2174
2175	This menu control is not yet part of the public kernel API and
2176	it is expected to change.
2177
2178	.. c:type:: v4l2_mpeg_video_h264_start_code
2179
2180	.. cssclass:: longtable
2181
2182	.. flat-table::
2183	:header-rows: 0
2184	:stub-columns: 0
2185	:widths: 1 1 2
2186
2187	* - ``V4L2_MPEG_VIDEO_H264_START_CODE_NONE``
2188	- 0
2189	- Selecting this value specifies that H264 slices are passed
2190	to the driver without any start code.
2191	* - ``V4L2_MPEG_VIDEO_H264_START_CODE_ANNEX_B``
2192	- 1
2193	- Selecting this value specifies that H264 slices are expected
2194	to be prefixed by Annex B start codes. According to :ref:`h264`
2195	valid start codes can be 3-bytes 0x000001 or 4-bytes 0x00000001.
2196
2197	.. _v4l2-mpeg-mpeg2:	1505	.. _v4l2-mpeg-mpeg2:
2198		1506
2199	``V4L2_CID_MPEG_VIDEO_MPEG2_SLICE_PARAMS (struct)``	1507	``V4L2_CID_MPEG_VIDEO_MPEG2_SLICE_PARAMS (struct)``
@@ -2905,127 +2213,6 @@ enum v4l2_mpeg_mfc51_video_force_frame_type - · 705 unmodified lines
2905	- Force a non-coded frame.	2213	- Force a non-coded frame.
2906		2214
2907		2215
2908	.. _v4l2-mpeg-fwht:
2909
2910	``V4L2_CID_MPEG_VIDEO_FWHT_PARAMS (struct)``
2911	Specifies the fwht parameters (as extracted from the bitstream) for the
2912	associated FWHT data. This includes the necessary parameters for
2913	configuring a stateless hardware decoding pipeline for FWHT.
2914
2915	.. note::
2916
2917	This compound control is not yet part of the public kernel API and
2918	it is expected to change.
2919
2920	.. c:type:: v4l2_ctrl_fwht_params
2921
2922	.. cssclass:: longtable
2923
2924	.. tabularcolumns:: \|p{1.4cm}\|p{4.3cm}\|p{11.8cm}\|
2925
2926	.. flat-table:: struct v4l2_ctrl_fwht_params
2927	:header-rows: 0
2928	:stub-columns: 0
2929	:widths: 1 1 2
2930
2931	* - __u64
2932	- ``backward_ref_ts``
2933	- Timestamp of the V4L2 capture buffer to use as backward reference, used
2934	with P-coded frames. The timestamp refers to the
2935	``timestamp`` field in struct :c:type:`v4l2_buffer`. Use the
2936	:c:func:`v4l2_timeval_to_ns()` function to convert the struct
2937	:c:type:`timeval` in struct :c:type:`v4l2_buffer` to a __u64.
2938	* - __u32
2939	- ``version``
2940	- The version of the codec
2941	* - __u32
2942	- ``width``
2943	- The width of the frame
2944	* - __u32
2945	- ``height``
2946	- The height of the frame
2947	* - __u32
2948	- ``flags``
2949	- The flags of the frame, see :ref:`fwht-flags`.
2950	* - __u32
2951	- ``colorspace``
2952	- The colorspace of the frame, from enum :c:type:`v4l2_colorspace`.
2953	* - __u32
2954	- ``xfer_func``
2955	- The transfer function, from enum :c:type:`v4l2_xfer_func`.
2956	* - __u32
2957	- ``ycbcr_enc``
2958	- The Y'CbCr encoding, from enum :c:type:`v4l2_ycbcr_encoding`.
2959	* - __u32
2960	- ``quantization``
2961	- The quantization range, from enum :c:type:`v4l2_quantization`.
2962
2963
2964
2965	.. _fwht-flags:
2966
2967	FWHT Flags
2968	============
2969
2970	.. cssclass:: longtable
2971
2972	.. tabularcolumns:: \|p{6.8cm}\|p{2.4cm}\|p{8.3cm}\|
2973
2974	.. flat-table::
2975	:header-rows: 0
2976	:stub-columns: 0
2977	:widths: 3 1 4
2978
2979	* - ``FWHT_FL_IS_INTERLACED``
2980	- 0x00000001
2981	- Set if this is an interlaced format
2982	* - ``FWHT_FL_IS_BOTTOM_FIRST``
2983	- 0x00000002
2984	- Set if this is a bottom-first (NTSC) interlaced format
2985	* - ``FWHT_FL_IS_ALTERNATE``
2986	- 0x00000004
2987	- Set if each 'frame' contains just one field
2988	* - ``FWHT_FL_IS_BOTTOM_FIELD``
2989	- 0x00000008
2990	- If FWHT_FL_IS_ALTERNATE was set, then this is set if this 'frame' is the
2991	bottom field, else it is the top field.
2992	* - ``FWHT_FL_LUMA_IS_UNCOMPRESSED``
2993	- 0x00000010
2994	- Set if the luma plane is uncompressed
2995	* - ``FWHT_FL_CB_IS_UNCOMPRESSED``
2996	- 0x00000020
2997	- Set if the cb plane is uncompressed
2998	* - ``FWHT_FL_CR_IS_UNCOMPRESSED``
2999	- 0x00000040
3000	- Set if the cr plane is uncompressed
3001	* - ``FWHT_FL_CHROMA_FULL_HEIGHT``
3002	- 0x00000080
3003	- Set if the chroma plane has the same height as the luma plane,
3004	else the chroma plane is half the height of the luma plane
3005	* - ``FWHT_FL_CHROMA_FULL_WIDTH``
3006	- 0x00000100
3007	- Set if the chroma plane has the same width as the luma plane,
3008	else the chroma plane is half the width of the luma plane
3009	* - ``FWHT_FL_ALPHA_IS_UNCOMPRESSED``
3010	- 0x00000200
3011	- Set if the alpha plane is uncompressed
3012	* - ``FWHT_FL_I_FRAME``
3013	- 0x00000400
3014	- Set if this is an I-frame
3015	* - ``FWHT_FL_COMPONENTS_NUM_MSK``
3016	- 0x00070000
3017	- A 4-values flag - the number of components - 1
3018	* - ``FWHT_FL_PIXENC_YUV``
3019	- 0x00080000
3020	- Set if the pixel encoding is YUV
3021	* - ``FWHT_FL_PIXENC_RGB``
3022	- 0x00100000
3023	- Set if the pixel encoding is RGB
3024	* - ``FWHT_FL_PIXENC_HSV``
3025	- 0x00180000
3026	- Set if the pixel encoding is HSV
3027
3028
3029	CX2341x MPEG Controls	2216	CX2341x MPEG Controls
3030	=====================	2217	=====================
3031		2218

Documentation/userspace-api/media/v4l/ext-ctrls-image-source.rst+14−0

@@ -58,3 +58,17 @@ Image Source Control IDs · 57 unmodified lines
58	The unit cell consists of the whole area of the pixel, sensitive and	58	The unit cell consists of the whole area of the pixel, sensitive and
59	non-sensitive.	59	non-sensitive.
60	This control is required for automatic calibration of sensors/cameras.	60	This control is required for automatic calibration of sensors/cameras.
		61
		62	.. c:type:: v4l2_area
		63
		64	.. flat-table:: struct v4l2_area
		65	:header-rows: 0
		66	:stub-columns: 0
		67	:widths: 1 1 2
		68
		69	* - __u32
		70	- ``width``
		71	- Width of the area.
		72	* - __u32
		73	- ``height``
		74	- Height of the area.

Documentation/userspace-api/media/v4l/extended-controls.rst+4−4

@@ -55,8 +55,8 @@ controls in that array and a control class. Control classes are used to · 54 unmodified lines
55	group similar controls into a single class. For example, control class	55	group similar controls into a single class. For example, control class
56	``V4L2_CTRL_CLASS_USER`` contains all user controls (i. e. all controls	56	``V4L2_CTRL_CLASS_USER`` contains all user controls (i. e. all controls
57	that can also be set using the old :ref:`VIDIOC_S_CTRL <VIDIOC_G_CTRL>`	57	that can also be set using the old :ref:`VIDIOC_S_CTRL <VIDIOC_G_CTRL>`
58	ioctl). Control class ``V4L2_CTRL_CLASS_MPEG`` contains all controls	58	ioctl). Control class ``V4L2_CTRL_CLASS_CODEC`` contains controls
59	relating to MPEG encoding, etc.	59	relating to codecs.
60		60
61	All controls in the control array must belong to the specified control	61	All controls in the control array must belong to the specified control
62	class. An error is returned if this is not the case.	62	class. An error is returned if this is not the case.
@@ -130,9 +130,9 @@ control class is found: · 67 unmodified lines
130		130
131	.. code-block:: c	131	.. code-block:: c
132		132
133	qctrl.id = V4L2_CTRL_CLASS_MPEG \| V4L2_CTRL_FLAG_NEXT_CTRL;	133	qctrl.id = V4L2_CTRL_CLASS_CODEC \| V4L2_CTRL_FLAG_NEXT_CTRL;
134	while (0 == ioctl(fd, VIDIOC_QUERYCTRL, &qctrl)) {	134	while (0 == ioctl(fd, VIDIOC_QUERYCTRL, &qctrl)) {
135	if (V4L2_CTRL_ID2CLASS(qctrl.id) != V4L2_CTRL_CLASS_MPEG)	135	if (V4L2_CTRL_ID2CLASS(qctrl.id) != V4L2_CTRL_CLASS_CODEC)
136	break;	136	break;
137	/* ... */	137	/* ... */
138	qctrl.id \|= V4L2_CTRL_FLAG_NEXT_CTRL;	138	qctrl.id \|= V4L2_CTRL_FLAG_NEXT_CTRL;

Documentation/userspace-api/media/v4l/pixfmt-compressed.rst+17−20

       - H264 parsed slice data, including slice headers, either with or
 	without the start code, as extracted from the H264 bitstream.
 	This format is adapted for stateless video decoders that implement an
-	H264 pipeline (using the :ref:`mem2mem` and :ref:`media-request-api`).
+	H264 pipeline with the :ref:`stateless_decoder`.
 	This pixelformat has two modifiers that must be set at least once
-	through the ``V4L2_CID_MPEG_VIDEO_H264_DECODE_MODE``
+	through the ``V4L2_CID_STATELESS_H264_DECODE_MODE``
-        and ``V4L2_CID_MPEG_VIDEO_H264_START_CODE`` controls.
+        and ``V4L2_CID_STATELESS_H264_START_CODE`` controls.
 	In addition, metadata associated with the frame to decode are
-	required to be passed through the ``V4L2_CID_MPEG_VIDEO_H264_SPS``,
+	required to be passed through the ``V4L2_CID_STATELESS_H264_SPS``,
-	``V4L2_CID_MPEG_VIDEO_H264_PPS``,
+	``V4L2_CID_STATELESS_H264_PPS``,
-	``V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX``,
+	``V4L2_CID_STATELESS_H264_SCALING_MATRIX``,
-	``V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS`` and
+	``V4L2_CID_STATELESS_H264_SLICE_PARAMS`` and
-	``V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS`` controls.  See the
+	``V4L2_CID_STATELESS_H264_DECODE_PARAMS`` controls.  See the
-	:ref:`associated Codec Control IDs <v4l2-mpeg-h264>`.  Exactly
+	:ref:`associated Codec Control IDs <v4l2-codec-stateless-h264>`.
-	one output and one capture buffer must be provided for use
+        Exactly one output and one capture buffer must be provided for use
 	with this pixel format. The output buffer must contain the
 	appropriate number of macroblocks to decode a full
 	corresponding frame to the matching capture buffer.
 	7.3.2.8 "Slice layer without partitioning RBSP syntax" and the following
 	sections.
-	.. note::
-	   This format is not yet part of the public kernel API and it
-	   is expected to change.
     * .. _V4L2-PIX-FMT-H263:
       - ``V4L2_PIX_FMT_H263``
 	through the ``V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE``
         and ``V4L2_CID_MPEG_VIDEO_HEVC_START_CODE`` controls.
 	Metadata associated with the frame to decode is required to be passed
-	through the following controls :
+	through the following controls:
-        * ``V4L2_CID_MPEG_VIDEO_HEVC_SPS``
+        ``V4L2_CID_MPEG_VIDEO_HEVC_SPS``,
-        * ``V4L2_CID_MPEG_VIDEO_HEVC_PPS``
+        ``V4L2_CID_MPEG_VIDEO_HEVC_PPS``, and
-        * ``V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS``
+        ``V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS``.
 	See the :ref:`associated Codec Control IDs <v4l2-mpeg-hevc>`.
 	Buffers associated with this pixel format must contain the appropriate
 	number of macroblocks to decode a full corresponding frame.
       - ``V4L2_PIX_FMT_FWHT_STATELESS``
       - 'SFWH'
       - Same format as V4L2_PIX_FMT_FWHT but requires stateless codec implementation.
-	See the :ref:`associated Codec Control IDs <v4l2-mpeg-fwht>`.
+        Metadata associated with the frame to decode is required to be passed
+        through the ``V4L2_CID_STATELESS_FWHT_PARAMS`` control.
+	See the :ref:`associated Codec Control ID <codec-stateless-fwht>`.

Documentation/userspace-api/media/v4l/pixfmt-grey.rst+0−44

@@ -1,44 +0,0 @@
1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
2
3	.. _V4L2-PIX-FMT-GREY:
4
5	**************************
6	V4L2_PIX_FMT_GREY ('GREY')
7	**************************
8
9	Grey-scale image
10
11
12	Description
13	===========
14
15	This is a grey-scale image. It is really a degenerate Y'CbCr format
16	which simply contains no Cb or Cr data.
17
18	Byte Order.
19	Each cell is one byte.
20
21	.. flat-table::
22	:header-rows: 0
23	:stub-columns: 0
24
25	* - start + 0:
26	- Y'\ :sub:`00`
27	- Y'\ :sub:`01`
28	- Y'\ :sub:`02`
29	- Y'\ :sub:`03`
30	* - start + 4:
31	- Y'\ :sub:`10`
32	- Y'\ :sub:`11`
33	- Y'\ :sub:`12`
34	- Y'\ :sub:`13`
35	* - start + 8:
36	- Y'\ :sub:`20`
37	- Y'\ :sub:`21`
38	- Y'\ :sub:`22`
39	- Y'\ :sub:`23`
40	* - start + 12:
41	- Y'\ :sub:`30`
42	- Y'\ :sub:`31`
43	- Y'\ :sub:`32`
44	- Y'\ :sub:`33`

Documentation/userspace-api/media/v4l/pixfmt-m420.rst+2−57

@@ -67,60 +67,5 @@ Each cell is one byte. · 66 unmodified lines
67		67
68		68
69	Color Sample Location:	69	Color Sample Location:
70		70	Chroma samples are :ref:`interstitially sited<yuv-chroma-centered>`
71		71	horizontally and vertically.
72
73	.. flat-table::
74	:header-rows: 0
75	:stub-columns: 0
76
77	* -
78	- 0
79	-
80	- 1
81	- 2
82	-
83	- 3
84	* - 0
85	- Y
86	-
87	- Y
88	- Y
89	-
90	- Y
91	* -
92	-
93	- C
94	-
95	-
96	- C
97	-
98	* - 1
99	- Y
100	-
101	- Y
102	- Y
103	-
104	- Y
105	* -
106	* - 2
107	- Y
108	-
109	- Y
110	- Y
111	-
112	- Y
113	* -
114	-
115	- C
116	-
117	-
118	- C
119	-
120	* - 3
121	- Y
122	-
123	- Y
124	- Y
125	-
126	- Y

Documentation/userspace-api/media/v4l/pixfmt-meta-rkisp1.rst+4−3

@@ -1,7 +1,8 @@
1	.. SPDX-License-Identifier: GPL-2.0	1	.. SPDX-License-Identifier: GPL-2.0
2		2
3	.. _v4l2-meta-fmt-params-rkisp1:	3	.. _v4l2-meta-fmt-rk-isp1-params:
4	.. _v4l2-meta-fmt-stat-rkisp1:	4
		5	.. _v4l2-meta-fmt-rk-isp1-stat-3a:
5		6
6	*****************************************************************************	7	*****************************************************************************
7	V4L2_META_FMT_RK_ISP1_PARAMS ('rk1p'), V4L2_META_FMT_RK_ISP1_STAT_3A ('rk1s')	8	V4L2_META_FMT_RK_ISP1_PARAMS ('rk1p'), V4L2_META_FMT_RK_ISP1_STAT_3A ('rk1s')
@@ -46,4 +47,4 @@ important tuning tools using software control loop. · 38 unmodified lines
46	rkisp1 uAPI data types	47	rkisp1 uAPI data types
47	======================	48	======================
48		49
49	.. kernel-doc:: drivers/staging/media/rkisp1/uapi/rkisp1-config.h	50	.. kernel-doc:: include/uapi/linux/rkisp1-config.h

Documentation/userspace-api/media/v4l/pixfmt-nv12.rst+0−129

@@ -1,129 +0,0 @@
1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
2
3	.. _V4L2-PIX-FMT-NV12:
4	.. _V4L2-PIX-FMT-NV21:
5
6	******************************************************
7	V4L2_PIX_FMT_NV12 ('NV12'), V4L2_PIX_FMT_NV21 ('NV21')
8	******************************************************
9
10
11	V4L2_PIX_FMT_NV21
12	Formats with ½ horizontal and vertical chroma resolution, also known as
13	YUV 4:2:0. One luminance and one chrominance plane with alternating
14	chroma samples as opposed to ``V4L2_PIX_FMT_YVU420``
15
16
17	Description
18	===========
19
20	These are two-plane versions of the YUV 4:2:0 format. The three
21	components are separated into two sub-images or planes. The Y plane is
22	first. The Y plane has one byte per pixel. For ``V4L2_PIX_FMT_NV12``, a
23	combined CbCr plane immediately follows the Y plane in memory. The CbCr
24	plane is the same width, in bytes, as the Y plane (and of the image),
25	but is half as tall in pixels. Each CbCr pair belongs to four pixels.
26	For example, Cb\ :sub:`0`/Cr\ :sub:`0` belongs to Y'\ :sub:`00`,
27	Y'\ :sub:`01`, Y'\ :sub:`10`, Y'\ :sub:`11`. ``V4L2_PIX_FMT_NV21`` is
28	the same except the Cb and Cr bytes are swapped, the CrCb plane starts
29	with a Cr byte.
30
31	If the Y plane has pad bytes after each row, then the CbCr plane has as
32	many pad bytes after its rows.
33
34	Byte Order.
35	Each cell is one byte.
36
37
38	.. flat-table::
39	:header-rows: 0
40	:stub-columns: 0
41
42	* - start + 0:
43	- Y'\ :sub:`00`
44	- Y'\ :sub:`01`
45	- Y'\ :sub:`02`
46	- Y'\ :sub:`03`
47	* - start + 4:
48	- Y'\ :sub:`10`
49	- Y'\ :sub:`11`
50	- Y'\ :sub:`12`
51	- Y'\ :sub:`13`
52	* - start + 8:
53	- Y'\ :sub:`20`
54	- Y'\ :sub:`21`
55	- Y'\ :sub:`22`
56	- Y'\ :sub:`23`
57	* - start + 12:
58	- Y'\ :sub:`30`
59	- Y'\ :sub:`31`
60	- Y'\ :sub:`32`
61	- Y'\ :sub:`33`
62	* - start + 16:
63	- Cb\ :sub:`00`
64	- Cr\ :sub:`00`
65	- Cb\ :sub:`01`
66	- Cr\ :sub:`01`
67	* - start + 20:
68	- Cb\ :sub:`10`
69	- Cr\ :sub:`10`
70	- Cb\ :sub:`11`
71	- Cr\ :sub:`11`
72
73
74	Color Sample Location:
75
76	.. flat-table::
77	:header-rows: 0
78	:stub-columns: 0
79
80	* -
81	- 0
82	-
83	- 1
84	- 2
85	-
86	- 3
87	* - 0
88	- Y
89	-
90	- Y
91	- Y
92	-
93	- Y
94	* -
95	-
96	- C
97	-
98	-
99	- C
100	-
101	* - 1
102	- Y
103	-
104	- Y
105	- Y
106	-
107	- Y
108	* -
109	* - 2
110	- Y
111	-
112	- Y
113	- Y
114	-
115	- Y
116	* -
117	-
118	- C
119	-
120	-
121	- C
122	-
123	* - 3
124	- Y
125	-
126	- Y
127	- Y
128	-
129	- Y

Documentation/userspace-api/media/v4l/pixfmt-nv12m.rst+0−144

@@ -1,144 +0,0 @@
1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
2
3	.. _V4L2-PIX-FMT-NV12M:
4	.. _v4l2-pix-fmt-nv12mt-16x16:
5	.. _V4L2-PIX-FMT-NV21M:
6
7	***********************************************************************************
8	V4L2_PIX_FMT_NV12M ('NM12'), V4L2_PIX_FMT_NV21M ('NM21'), V4L2_PIX_FMT_NV12MT_16X16
9	***********************************************************************************
10
11
12	V4L2_PIX_FMT_NV21M
13	V4L2_PIX_FMT_NV12MT_16X16
14	Variation of ``V4L2_PIX_FMT_NV12`` and ``V4L2_PIX_FMT_NV21`` with planes
15	non contiguous in memory.
16
17
18	Description
19	===========
20
21	This is a multi-planar, two-plane version of the YUV 4:2:0 format. The
22	three components are separated into two sub-images or planes.
23	``V4L2_PIX_FMT_NV12M`` differs from ``V4L2_PIX_FMT_NV12`` in that the
24	two planes are non-contiguous in memory, i.e. the chroma plane do not
25	necessarily immediately follows the luma plane. The luminance data
26	occupies the first plane. The Y plane has one byte per pixel. In the
27	second plane there is a chrominance data with alternating chroma
28	samples. The CbCr plane is the same width, in bytes, as the Y plane (and
29	of the image), but is half as tall in pixels. Each CbCr pair belongs to
30	four pixels. For example, Cb\ :sub:`0`/Cr\ :sub:`0` belongs to
31	Y'\ :sub:`00`, Y'\ :sub:`01`, Y'\ :sub:`10`, Y'\ :sub:`11`.
32	``V4L2_PIX_FMT_NV12MT_16X16`` is the tiled version of
33	``V4L2_PIX_FMT_NV12M`` with 16x16 macroblock tiles. Here pixels are
34	arranged in 16x16 2D tiles and tiles are arranged in linear order in
35	memory. ``V4L2_PIX_FMT_NV21M`` is the same as ``V4L2_PIX_FMT_NV12M``
36	except the Cb and Cr bytes are swapped, the CrCb plane starts with a Cr
37	byte.
38
39	``V4L2_PIX_FMT_NV12M`` is intended to be used only in drivers and
40	applications that support the multi-planar API, described in
41	:ref:`planar-apis`.
42
43	If the Y plane has pad bytes after each row, then the CbCr plane has as
44	many pad bytes after its rows.
45
46	Byte Order.
47	Each cell is one byte.
48
49	.. flat-table::
50	:header-rows: 0
51	:stub-columns: 0
52
53	* - start0 + 0:
54	- Y'\ :sub:`00`
55	- Y'\ :sub:`01`
56	- Y'\ :sub:`02`
57	- Y'\ :sub:`03`
58	* - start0 + 4:
59	- Y'\ :sub:`10`
60	- Y'\ :sub:`11`
61	- Y'\ :sub:`12`
62	- Y'\ :sub:`13`
63	* - start0 + 8:
64	- Y'\ :sub:`20`
65	- Y'\ :sub:`21`
66	- Y'\ :sub:`22`
67	- Y'\ :sub:`23`
68	* - start0 + 12:
69	- Y'\ :sub:`30`
70	- Y'\ :sub:`31`
71	- Y'\ :sub:`32`
72	- Y'\ :sub:`33`
73	* -
74	* - start1 + 0:
75	- Cb\ :sub:`00`
76	- Cr\ :sub:`00`
77	- Cb\ :sub:`01`
78	- Cr\ :sub:`01`
79	* - start1 + 4:
80	- Cb\ :sub:`10`
81	- Cr\ :sub:`10`
82	- Cb\ :sub:`11`
83	- Cr\ :sub:`11`
84
85
86	Color Sample Location:
87
88
89
90	.. flat-table::
91	:header-rows: 0
92	:stub-columns: 0
93
94	* -
95	- 0
96	-
97	- 1
98	- 2
99	-
100	- 3
101	* - 0
102	- Y
103	-
104	- Y
105	- Y
106	-
107	- Y
108	* -
109	-
110	- C
111	-
112	-
113	- C
114	-
115	* - 1
116	- Y
117	-
118	- Y
119	- Y
120	-
121	- Y
122	* -
123	* - 2
124	- Y
125	-
126	- Y
127	- Y
128	-
129	- Y
130	* -
131	-
132	- C
133	-
134	-
135	-
136	- C
137	-
138	* - 3
139	- Y
140	-
141	- Y
142	- Y
143	-
144	- Y

Documentation/userspace-api/media/v4l/pixfmt-nv12mt.rst+0−60

@@ -1,60 +0,0 @@
1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
2
3	.. _V4L2-PIX-FMT-NV12MT:
4
5	****************************
6	V4L2_PIX_FMT_NV12MT ('TM12')
7	****************************
8
9	Formats with ½ horizontal and vertical chroma resolution. This format
10	has two planes - one for luminance and one for chrominance. Chroma
11	samples are interleaved. The difference to ``V4L2_PIX_FMT_NV12`` is the
12	memory layout. Pixels are grouped in macroblocks of 64x32 size. The
13	order of macroblocks in memory is also not standard.
14
15
16	Description
17	===========
18
19	This is the two-plane versions of the YUV 4:2:0 format where data is
20	grouped into 64x32 macroblocks. The three components are separated into
21	two sub-images or planes. The Y plane has one byte per pixel and pixels
22	are grouped into 64x32 macroblocks. The CbCr plane has the same width,
23	in bytes, as the Y plane (and the image), but is half as tall in pixels.
24	The chroma plane is also grouped into 64x32 macroblocks.
25
26	Width of the buffer has to be aligned to the multiple of 128, and height
27	alignment is 32. Every four adjacent buffers - two horizontally and two
28	vertically are grouped together and are located in memory in Z or
29	flipped Z order.
30
31	Layout of macroblocks in memory is presented in the following figure.
32
33
34	.. _nv12mt:
35
36	.. kernel-figure:: nv12mt.svg
37	:alt: nv12mt.svg
38	:align: center
39
40	V4L2_PIX_FMT_NV12MT macroblock Z shape memory layout
41
42	The requirement that width is multiple of 128 is implemented because,
43	the Z shape cannot be cut in half horizontally. In case the vertical
44	resolution of macroblocks is odd then the last row of macroblocks is
45	arranged in a linear order.
46
47	In case of chroma the layout is identical. Cb and Cr samples are
48	interleaved. Height of the buffer is aligned to 32.
49
50
51	.. _nv12mt_ex:
52
53	.. kernel-figure:: nv12mt_example.svg
54	:alt: nv12mt_example.svg
55	:align: center
56
57	Example V4L2_PIX_FMT_NV12MT memory layout of macroblocks
58
59	Memory layout of macroblocks of ``V4L2_PIX_FMT_NV12MT`` format in most
60	extreme case.

Documentation/userspace-api/media/v4l/pixfmt-nv16.rst+0−153

@@ -1,153 +0,0 @@
1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
2
3	.. _V4L2-PIX-FMT-NV16:
4	.. _V4L2-PIX-FMT-NV61:
5
6	******************************************************
7	V4L2_PIX_FMT_NV16 ('NV16'), V4L2_PIX_FMT_NV61 ('NV61')
8	******************************************************
9
10	V4L2_PIX_FMT_NV61
11	Formats with ½ horizontal chroma resolution, also known as YUV 4:2:2.
12	One luminance and one chrominance plane with alternating chroma samples
13	as opposed to ``V4L2_PIX_FMT_YVU420``
14
15
16	Description
17	===========
18
19	These are two-plane versions of the YUV 4:2:2 format. The three
20	components are separated into two sub-images or planes. The Y plane is
21	first. The Y plane has one byte per pixel. For ``V4L2_PIX_FMT_NV16``, a
22	combined CbCr plane immediately follows the Y plane in memory. The CbCr
23	plane is the same width and height, in bytes, as the Y plane (and of the
24	image). Each CbCr pair belongs to two pixels. For example,
25	Cb\ :sub:`0`/Cr\ :sub:`0` belongs to Y'\ :sub:`00`, Y'\ :sub:`01`.
26	``V4L2_PIX_FMT_NV61`` is the same except the Cb and Cr bytes are
27	swapped, the CrCb plane starts with a Cr byte.
28
29	If the Y plane has pad bytes after each row, then the CbCr plane has as
30	many pad bytes after its rows.
31
32	Byte Order.
33	Each cell is one byte.
34
35
36	.. flat-table::
37	:header-rows: 0
38	:stub-columns: 0
39
40	* - start + 0:
41	- Y'\ :sub:`00`
42	- Y'\ :sub:`01`
43	- Y'\ :sub:`02`
44	- Y'\ :sub:`03`
45	* - start + 4:
46	- Y'\ :sub:`10`
47	- Y'\ :sub:`11`
48	- Y'\ :sub:`12`
49	- Y'\ :sub:`13`
50	* - start + 8:
51	- Y'\ :sub:`20`
52	- Y'\ :sub:`21`
53	- Y'\ :sub:`22`
54	- Y'\ :sub:`23`
55	* - start + 12:
56	- Y'\ :sub:`30`
57	- Y'\ :sub:`31`
58	- Y'\ :sub:`32`
59	- Y'\ :sub:`33`
60	* - start + 16:
61	- Cb\ :sub:`00`
62	- Cr\ :sub:`00`
63	- Cb\ :sub:`01`
64	- Cr\ :sub:`01`
65	* - start + 20:
66	- Cb\ :sub:`10`
67	- Cr\ :sub:`10`
68	- Cb\ :sub:`11`
69	- Cr\ :sub:`11`
70	* - start + 24:
71	- Cb\ :sub:`20`
72	- Cr\ :sub:`20`
73	- Cb\ :sub:`21`
74	- Cr\ :sub:`21`
75	* - start + 28:
76	- Cb\ :sub:`30`
77	- Cr\ :sub:`30`
78	- Cb\ :sub:`31`
79	- Cr\ :sub:`31`
80
81
82	Color Sample Location:
83
84
85
86	.. flat-table::
87	:header-rows: 0
88	:stub-columns: 0
89
90	* -
91	- 0
92	-
93	- 1
94	- 2
95	-
96	- 3
97	* - 0
98	- Y
99	-
100	- Y
101	- Y
102	-
103	- Y
104	* -
105	-
106	- C
107	-
108	-
109	- C
110	-
111	* - 1
112	- Y
113	-
114	- Y
115	- Y
116	-
117	- Y
118	* -
119	-
120	- C
121	-
122	-
123	- C
124	-
125	* -
126	* - 2
127	- Y
128	-
129	- Y
130	- Y
131	-
132	- Y
133	* -
134	-
135	- C
136	-
137	-
138	- C
139	-
140	* - 3
141	- Y
142	-
143	- Y
144	- Y
145	-
146	- Y
147	* -
148	-
149	- C
150	-
151	-
152	- C
153	-

Documentation/userspace-api/media/v4l/pixfmt-nv16m.rst+0−157

@@ -1,157 +0,0 @@
1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
2
3	.. _V4L2-PIX-FMT-NV16M:
4	.. _v4l2-pix-fmt-nv61m:
5
6	********************************************************
7	V4L2_PIX_FMT_NV16M ('NM16'), V4L2_PIX_FMT_NV61M ('NM61')
8	********************************************************
9
10	V4L2_PIX_FMT_NV61M
11	Variation of ``V4L2_PIX_FMT_NV16`` and ``V4L2_PIX_FMT_NV61`` with planes
12	non contiguous in memory.
13
14
15	Description
16	===========
17
18	This is a multi-planar, two-plane version of the YUV 4:2:2 format. The
19	three components are separated into two sub-images or planes.
20	``V4L2_PIX_FMT_NV16M`` differs from ``V4L2_PIX_FMT_NV16`` in that the
21	two planes are non-contiguous in memory, i.e. the chroma plane does not
22	necessarily immediately follow the luma plane. The luminance data
23	occupies the first plane. The Y plane has one byte per pixel. In the
24	second plane there is chrominance data with alternating chroma samples.
25	The CbCr plane is the same width and height, in bytes, as the Y plane.
26	Each CbCr pair belongs to two pixels. For example,
27	Cb\ :sub:`0`/Cr\ :sub:`0` belongs to Y'\ :sub:`00`, Y'\ :sub:`01`.
28	``V4L2_PIX_FMT_NV61M`` is the same as ``V4L2_PIX_FMT_NV16M`` except the
29	Cb and Cr bytes are swapped, the CrCb plane starts with a Cr byte.
30
31	``V4L2_PIX_FMT_NV16M`` and ``V4L2_PIX_FMT_NV61M`` are intended to be
32	used only in drivers and applications that support the multi-planar API,
33	described in :ref:`planar-apis`.
34
35	Byte Order.
36	Each cell is one byte.
37
38
39	.. flat-table::
40	:header-rows: 0
41	:stub-columns: 0
42
43	* - start0 + 0:
44	- Y'\ :sub:`00`
45	- Y'\ :sub:`01`
46	- Y'\ :sub:`02`
47	- Y'\ :sub:`03`
48	* - start0 + 4:
49	- Y'\ :sub:`10`
50	- Y'\ :sub:`11`
51	- Y'\ :sub:`12`
52	- Y'\ :sub:`13`
53	* - start0 + 8:
54	- Y'\ :sub:`20`
55	- Y'\ :sub:`21`
56	- Y'\ :sub:`22`
57	- Y'\ :sub:`23`
58	* - start0 + 12:
59	- Y'\ :sub:`30`
60	- Y'\ :sub:`31`
61	- Y'\ :sub:`32`
62	- Y'\ :sub:`33`
63	* -
64	* - start1 + 0:
65	- Cb\ :sub:`00`
66	- Cr\ :sub:`00`
67	- Cb\ :sub:`02`
68	- Cr\ :sub:`02`
69	* - start1 + 4:
70	- Cb\ :sub:`10`
71	- Cr\ :sub:`10`
72	- Cb\ :sub:`12`
73	- Cr\ :sub:`12`
74	* - start1 + 8:
75	- Cb\ :sub:`20`
76	- Cr\ :sub:`20`
77	- Cb\ :sub:`22`
78	- Cr\ :sub:`22`
79	* - start1 + 12:
80	- Cb\ :sub:`30`
81	- Cr\ :sub:`30`
82	- Cb\ :sub:`32`
83	- Cr\ :sub:`32`
84
85
86	Color Sample Location:
87
88
89
90	.. flat-table::
91	:header-rows: 0
92	:stub-columns: 0
93
94	* -
95	- 0
96	-
97	- 1
98	- 2
99	-
100	- 3
101	* - 0
102	- Y
103	-
104	- Y
105	- Y
106	-
107	- Y
108	* -
109	-
110	- C
111	-
112	-
113	- C
114	-
115	* - 1
116	- Y
117	-
118	- Y
119	- Y
120	-
121	- Y
122	* -
123	-
124	- C
125	-
126	-
127	- C
128	-
129	* -
130	* - 2
131	- Y
132	-
133	- Y
134	- Y
135	-
136	- Y
137	* -
138	-
139	- C
140	-
141	-
142	- C
143	-
144	* - 3
145	- Y
146	-
147	- Y
148	- Y
149	-
150	- Y
151	* -
152	-
153	- C
154	-
155	-
156	- C
157	-

Documentation/userspace-api/media/v4l/pixfmt-nv24.rst+0−95

@@ -1,95 +0,0 @@
1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
2
3	.. _V4L2-PIX-FMT-NV24:
4	.. _V4L2-PIX-FMT-NV42:
5
6	******************************************************
7	V4L2_PIX_FMT_NV24 ('NV24'), V4L2_PIX_FMT_NV42 ('NV42')
8	******************************************************
9
10	V4L2_PIX_FMT_NV42
11	Formats with full horizontal and vertical chroma resolutions, also known
12	as YUV 4:4:4. One luminance and one chrominance plane with alternating
13	chroma samples as opposed to ``V4L2_PIX_FMT_YVU420``
14
15
16	Description
17	===========
18
19	These are two-plane versions of the YUV 4:4:4 format. The three
20	components are separated into two sub-images or planes. The Y plane is
21	first, with each Y sample stored in one byte per pixel. For
22	``V4L2_PIX_FMT_NV24``, a combined CbCr plane immediately follows the Y
23	plane in memory. The CbCr plane has the same width and height, in
24	pixels, as the Y plane (and the image). Each line contains one CbCr pair
25	per pixel, with each Cb and Cr sample stored in one byte.
26	``V4L2_PIX_FMT_NV42`` is the same except that the Cb and Cr samples are
27	swapped, the CrCb plane starts with a Cr sample.
28
29	If the Y plane has pad bytes after each row, then the CbCr plane has
30	twice as many pad bytes after its rows.
31
32	Byte Order.
33	Each cell is one byte.
34
35
36	.. flat-table::
37	:header-rows: 0
38	:stub-columns: 0
39
40	* - start + 0:
41	- Y'\ :sub:`00`
42	- Y'\ :sub:`01`
43	- Y'\ :sub:`02`
44	- Y'\ :sub:`03`
45	* - start + 4:
46	- Y'\ :sub:`10`
47	- Y'\ :sub:`11`
48	- Y'\ :sub:`12`
49	- Y'\ :sub:`13`
50	* - start + 8:
51	- Y'\ :sub:`20`
52	- Y'\ :sub:`21`
53	- Y'\ :sub:`22`
54	- Y'\ :sub:`23`
55	* - start + 12:
56	- Y'\ :sub:`30`
57	- Y'\ :sub:`31`
58	- Y'\ :sub:`32`
59	- Y'\ :sub:`33`
60	* - start + 16:
61	- Cb\ :sub:`00`
62	- Cr\ :sub:`00`
63	- Cb\ :sub:`01`
64	- Cr\ :sub:`01`
65	- Cb\ :sub:`02`
66	- Cr\ :sub:`02`
67	- Cb\ :sub:`03`
68	- Cr\ :sub:`03`
69	* - start + 24:
70	- Cb\ :sub:`10`
71	- Cr\ :sub:`10`
72	- Cb\ :sub:`11`
73	- Cr\ :sub:`11`
74	- Cb\ :sub:`12`
75	- Cr\ :sub:`12`
76	- Cb\ :sub:`13`
77	- Cr\ :sub:`13`
78	* - start + 32:
79	- Cb\ :sub:`20`
80	- Cr\ :sub:`20`
81	- Cb\ :sub:`21`
82	- Cr\ :sub:`21`
83	- Cb\ :sub:`22`
84	- Cr\ :sub:`22`
85	- Cb\ :sub:`23`
86	- Cr\ :sub:`23`
87	* - start + 40:
88	- Cb\ :sub:`30`
89	- Cr\ :sub:`30`
90	- Cb\ :sub:`31`
91	- Cr\ :sub:`31`
92	- Cb\ :sub:`32`
93	- Cr\ :sub:`32`
94	- Cb\ :sub:`33`
95	- Cr\ :sub:`33`

Documentation/userspace-api/media/v4l/pixfmt-packed-yuv.rst+199−213

@@ -6,12 +6,32 @@ · 5 unmodified lines
6	Packed YUV formats	6	Packed YUV formats
7	******************	7	******************
8		8
9	Description	9	Similarly to the packed RGB formats, the packed YUV formats store the Y, Cb and
10	===========	10	Cr components consecutively in memory. They may apply subsampling to the chroma
		11	components and thus differ in how they interlave the three components.
11		12
12	Similar to the packed RGB formats these formats store the Y, Cb and Cr	13	.. note::
13	component of each pixel in one 16 or 32 bit word.	14
		15	- In all the tables that follow, bit 7 is the most significant bit in a byte.
		16	- 'Y', 'Cb' and 'Cr' denote bits of the luma, blue chroma (also known as
		17	'U') and red chroma (also known as 'V') components respectively. 'A'
		18	denotes bits of the alpha component (if supported by the format), and 'X'
		19	denotes padding bits.
		20
		21
		22	4:4:4 Subsampling
		23	=================
14		24
		25	These formats do not subsample the chroma components and store each pixels as a
		26	full triplet of Y, Cb and Cr values.
		27
		28	The next table lists the packed YUV 4:4:4 formats with less than 8 bits per
		29	component. They are named based on the order of the Y, Cb and Cr components as
		30	seen in a 16-bit word, which is then stored in memory in little endian byte
		31	order, and on the number of bits for each component. For instance the YUV565
		32	format stores a pixel in a 16-bit word [15:0] laid out at as [Y'\ :sub:`4-0`
		33	Cb\ :sub:`5-0` Cr\ :sub:`4-0`], and stored in memory in two bytes,
		34	[Cb\ :sub:`2-0` Cr\ :sub:`4-0`] followed by [Y'\ :sub:`4-0` Cb\ :sub:`5-3`].
15		35
16	.. raw:: latex	36	.. raw:: latex
17		37
@@ -19,11 +39,9 @@ component of each pixel in one 16 or 32 bit word. · 1 unmodified line
19	\tiny	39	\tiny
20	\setlength{\tabcolsep}{2pt}	40	\setlength{\tabcolsep}{2pt}
21		41
22	.. _packed-yuv-formats:	42	.. tabularcolumns:: \|p{2.5cm}\|p{0.69cm}\|p{0.31cm}\|p{0.31cm}\|p{0.31cm}\|p{0.31cm}\|p{0.31cm}\|p{0.31cm}\|p{0.31cm}\|p{0.31cm}\|p{0.31cm}\|p{0.31cm}\|p{0.31cm}\|p{0.31cm}\|p{0.31cm}\|p{0.31cm}\|p{0.31cm}\|p{0.31cm}\|
23
24	.. tabularcolumns:: \|p{2.5cm}\|p{0.69cm}\|p{0.31cm}\|p{0.31cm}\|p{0.31cm}\|p{0.31cm}\|p{0.31cm}\|p{0.31cm}\|p{0.31cm}\|p{0.31cm}\|p{0.31cm}\|p{0.31cm}\|p{0.31cm}\|p{0.31cm}\|p{0.31cm}\|p{0.31cm}\|p{0.31cm}\|p{0.31cm}\|p{0.31cm}\|p{0.31cm}\|p{0.31cm}\|p{0.31cm}\|p{0.31cm}\|p{0.31cm}\|p{0.31cm}\|p{0.31cm}\|p{0.31cm}\|p{0.31cm}\|p{0.31cm}\|p{0.31cm}\|p{0.31cm}\|p{0.31cm}\|p{0.31cm}\|p{0.31cm}\|
25		43
26	.. flat-table:: Packed YUV Image Formats	44	.. flat-table:: Packed YUV 4:4:4 Image Formats (less than 8bpc)
27	:header-rows: 2	45	:header-rows: 2
28	:stub-columns: 0	46	:stub-columns: 0
29		47
@@ -34,10 +52,6 @@ component of each pixel in one 16 or 32 bit word. · 4 unmodified lines
34		52
35	- :cspan:`7` Byte 1	53	- :cspan:`7` Byte 1
36		54
37	- :cspan:`7` Byte 2
38
39	- :cspan:`7` Byte 3
40
41	* -	55	* -
42	-	56	-
43	- 7	57	- 7
@@ -58,24 +72,6 @@ component of each pixel in one 16 or 32 bit word. · 14 unmodified lines
58	- 1	72	- 1
59	- 0	73	- 0
60		74
61	- 7
62	- 6
63	- 5
64	- 4
65	- 3
66	- 2
67	- 1
68	- 0
69
70	- 7
71	- 6
72	- 5
73	- 4
74	- 3
75	- 2
76	- 1
77	- 0
78
79	* .. _V4L2-PIX-FMT-YUV444:	75	* .. _V4L2-PIX-FMT-YUV444:
80		76
81	- ``V4L2_PIX_FMT_YUV444``	77	- ``V4L2_PIX_FMT_YUV444``
@@ -99,8 +95,6 @@ component of each pixel in one 16 or 32 bit word. · 17 unmodified lines
99	- Y'\ :sub:`1`	95	- Y'\ :sub:`1`
100	- Y'\ :sub:`0`	96	- Y'\ :sub:`0`
101		97
102	- :cspan:`15`
103
104	* .. _V4L2-PIX-FMT-YUV555:	98	* .. _V4L2-PIX-FMT-YUV555:
105		99
106	- ``V4L2_PIX_FMT_YUV555``	100	- ``V4L2_PIX_FMT_YUV555``
@@ -124,7 +118,6 @@ component of each pixel in one 16 or 32 bit word. · 17 unmodified lines
124	- Cb\ :sub:`4`	118	- Cb\ :sub:`4`
125	- Cb\ :sub:`3`	119	- Cb\ :sub:`3`
126		120
127	- :cspan:`15`
128	* .. _V4L2-PIX-FMT-YUV565:	121	* .. _V4L2-PIX-FMT-YUV565:
129		122
130	- ``V4L2_PIX_FMT_YUV565``	123	- ``V4L2_PIX_FMT_YUV565``
@@ -148,226 +141,219 @@ component of each pixel in one 16 or 32 bit word. · 17 unmodified lines
148	- Cb\ :sub:`4`	141	- Cb\ :sub:`4`
149	- Cb\ :sub:`3`	142	- Cb\ :sub:`3`
150		143
151	- :cspan:`15`	144	.. raw:: latex
152		145
153	* .. _V4L2-PIX-FMT-YUV32:	146	\endgroup
154		147
155	- ``V4L2_PIX_FMT_YUV32``	148	.. note::
156	- 'YUV4'
157		149
158	- a\ :sub:`7`	150	For the YUV444 and YUV555 formats, the value of alpha bits is undefined
159	- a\ :sub:`6`	151	when reading from the driver, ignored when writing to the driver, except
160	- a\ :sub:`5`	152	when alpha blending has been negotiated for a :ref:`Video Overlay
161	- a\ :sub:`4`	153	<overlay>` or :ref:`Video Output Overlay <osd>`.
162	- a\ :sub:`3`
163	- a\ :sub:`2`
164	- a\ :sub:`1`
165	- a\ :sub:`0`
166		154
167	- Y'\ :sub:`7`
168	- Y'\ :sub:`6`
169	- Y'\ :sub:`5`
170	- Y'\ :sub:`4`
171	- Y'\ :sub:`3`
172	- Y'\ :sub:`2`
173	- Y'\ :sub:`1`
174	- Y'\ :sub:`0`
175		155
176	- Cb\ :sub:`7`	156	The next table lists the packed YUV 4:4:4 formats with 8 bits per component.
177	- Cb\ :sub:`6`	157	They are named based on the order of the Y, Cb and Cr components as stored in
178	- Cb\ :sub:`5`	158	memory, and on the total number of bits per pixel. For instance, the VUYX32
179	- Cb\ :sub:`4`	159	format stores a pixel with Cr\ :sub:`7-0` in the first byte, Cb\ :sub:`7-0` in
180	- Cb\ :sub:`3`	160	the second byte and Y'\ :sub:`7-0` in the third byte.
181	- Cb\ :sub:`2`
182	- Cb\ :sub:`1`
183	- Cb\ :sub:`0`
184		161
185	- Cr\ :sub:`7`	162	.. flat-table:: Packed YUV Image Formats (8bpc)
186	- Cr\ :sub:`6`	163	:header-rows: 1
187	- Cr\ :sub:`5`	164	:stub-columns: 0
188	- Cr\ :sub:`4`
189	- Cr\ :sub:`3`
190	- Cr\ :sub:`2`
191	- Cr\ :sub:`1`
192	- Cr\ :sub:`0`
193		165
194	* .. _V4L2-PIX-FMT-AYUV32:	166	* - Identifier
		167	- Code
		168	- Byte 0
		169	- Byte 1
		170	- Byte 2
		171	- Byte 3
195		172
196	- ``V4L2_PIX_FMT_AYUV32``	173	* .. _V4L2-PIX-FMT-YUV32:
197	- 'AYUV'
198		174
199	- a\ :sub:`7`	175	- ``V4L2_PIX_FMT_YUV32``
200	- a\ :sub:`6`	176	- 'YUV4'
201	- a\ :sub:`5`
202	- a\ :sub:`4`
203	- a\ :sub:`3`
204	- a\ :sub:`2`
205	- a\ :sub:`1`
206	- a\ :sub:`0`
207		177
208	- Y'\ :sub:`7`	178	- A\ :sub:`7-0`
209	- Y'\ :sub:`6`	179	- Y'\ :sub:`7-0`
210	- Y'\ :sub:`5`	180	- Cb\ :sub:`7-0`
211	- Y'\ :sub:`4`	181	- Cr\ :sub:`7-0`
212	- Y'\ :sub:`3`
213	- Y'\ :sub:`2`
214	- Y'\ :sub:`1`
215	- Y'\ :sub:`0`
216		182
217	- Cb\ :sub:`7`	183	* .. _V4L2-PIX-FMT-AYUV32:
218	- Cb\ :sub:`6`
219	- Cb\ :sub:`5`
220	- Cb\ :sub:`4`
221	- Cb\ :sub:`3`
222	- Cb\ :sub:`2`
223	- Cb\ :sub:`1`
224	- Cb\ :sub:`0`
225		184
226	- Cr\ :sub:`7`	185	- ``V4L2_PIX_FMT_AYUV32``
227	- Cr\ :sub:`6`	186	- 'AYUV'
228	- Cr\ :sub:`5`	187
229	- Cr\ :sub:`4`	188	- A\ :sub:`7-0`
230	- Cr\ :sub:`3`	189	- Y'\ :sub:`7-0`
231	- Cr\ :sub:`2`	190	- Cb\ :sub:`7-0`
232	- Cr\ :sub:`1`	191	- Cr\ :sub:`7-0`
233	- Cr\ :sub:`0`
234		192
235	* .. _V4L2-PIX-FMT-XYUV32:	193	* .. _V4L2-PIX-FMT-XYUV32:
236		194
237	- ``V4L2_PIX_FMT_XYUV32``	195	- ``V4L2_PIX_FMT_XYUV32``
238	- 'XYUV'	196	- 'XYUV'
239		197
240	-	198	- X\ :sub:`7-0`
241	-	199	- Y'\ :sub:`7-0`
242	-	200	- Cb\ :sub:`7-0`
243	-	201	- Cr\ :sub:`7-0`
244	-
245	-
246	-
247	-
248
249	- Y'\ :sub:`7`
250	- Y'\ :sub:`6`
251	- Y'\ :sub:`5`
252	- Y'\ :sub:`4`
253	- Y'\ :sub:`3`
254	- Y'\ :sub:`2`
255	- Y'\ :sub:`1`
256	- Y'\ :sub:`0`
257
258	- Cb\ :sub:`7`
259	- Cb\ :sub:`6`
260	- Cb\ :sub:`5`
261	- Cb\ :sub:`4`
262	- Cb\ :sub:`3`
263	- Cb\ :sub:`2`
264	- Cb\ :sub:`1`
265	- Cb\ :sub:`0`
266
267	- Cr\ :sub:`7`
268	- Cr\ :sub:`6`
269	- Cr\ :sub:`5`
270	- Cr\ :sub:`4`
271	- Cr\ :sub:`3`
272	- Cr\ :sub:`2`
273	- Cr\ :sub:`1`
274	- Cr\ :sub:`0`
275		202
276	* .. _V4L2-PIX-FMT-VUYA32:	203	* .. _V4L2-PIX-FMT-VUYA32:
277		204
278	- ``V4L2_PIX_FMT_VUYA32``	205	- ``V4L2_PIX_FMT_VUYA32``
279	- 'VUYA'	206	- 'VUYA'
280		207
281	- Cr\ :sub:`7`	208	- Cr\ :sub:`7-0`
282	- Cr\ :sub:`6`	209	- Cb\ :sub:`7-0`
283	- Cr\ :sub:`5`	210	- Y'\ :sub:`7-0`
284	- Cr\ :sub:`4`	211	- A\ :sub:`7-0`
285	- Cr\ :sub:`3`
286	- Cr\ :sub:`2`
287	- Cr\ :sub:`1`
288	- Cr\ :sub:`0`
289
290	- Cb\ :sub:`7`
291	- Cb\ :sub:`6`
292	- Cb\ :sub:`5`
293	- Cb\ :sub:`4`
294	- Cb\ :sub:`3`
295	- Cb\ :sub:`2`
296	- Cb\ :sub:`1`
297	- Cb\ :sub:`0`
298
299	- Y'\ :sub:`7`
300	- Y'\ :sub:`6`
301	- Y'\ :sub:`5`
302	- Y'\ :sub:`4`
303	- Y'\ :sub:`3`
304	- Y'\ :sub:`2`
305	- Y'\ :sub:`1`
306	- Y'\ :sub:`0`
307
308	- a\ :sub:`7`
309	- a\ :sub:`6`
310	- a\ :sub:`5`
311	- a\ :sub:`4`
312	- a\ :sub:`3`
313	- a\ :sub:`2`
314	- a\ :sub:`1`
315	- a\ :sub:`0`
316		212
317	* .. _V4L2-PIX-FMT-VUYX32:	213	* .. _V4L2-PIX-FMT-VUYX32:
318		214
319	- ``V4L2_PIX_FMT_VUYX32``	215	- ``V4L2_PIX_FMT_VUYX32``
320	- 'VUYX'	216	- 'VUYX'
321		217
322	- Cr\ :sub:`7`	218	- Cr\ :sub:`7-0`
323	- Cr\ :sub:`6`	219	- Cb\ :sub:`7-0`
324	- Cr\ :sub:`5`	220	- Y'\ :sub:`7-0`
325	- Cr\ :sub:`4`	221	- X\ :sub:`7-0`
326	- Cr\ :sub:`3`
327	- Cr\ :sub:`2`
328	- Cr\ :sub:`1`
329	- Cr\ :sub:`0`
330		222
331	- Cb\ :sub:`7`	223	.. note::
332	- Cb\ :sub:`6`
333	- Cb\ :sub:`5`
334	- Cb\ :sub:`4`
335	- Cb\ :sub:`3`
336	- Cb\ :sub:`2`
337	- Cb\ :sub:`1`
338	- Cb\ :sub:`0`
339		224
340	- Y'\ :sub:`7`	225	- The alpha component is expected to contain a meaningful value that can be
341	- Y'\ :sub:`6`	226	used by drivers and applications.
342	- Y'\ :sub:`5`	227	- The padding bits contain undefined values that must be ignored by all
343	- Y'\ :sub:`4`	228	applications and drivers.
		229
		230
		231	4:2:2 Subsampling
		232	=================
		233
		234	These formats, commonly referred to as YUYV or YUY2, subsample the chroma
		235	components horizontally by 2, storing 2 pixels in 4 bytes.
		236
		237	.. flat-table:: Packed YUV 4:2:2 Formats
		238	:header-rows: 1
		239	:stub-columns: 0
		240
		241	* - Identifier
		242	- Code
		243	- Byte 0
		244	- Byte 1
		245	- Byte 2
		246	- Byte 3
		247	- Byte 4
		248	- Byte 5
		249	- Byte 6
		250	- Byte 7
		251	* .. _V4L2-PIX-FMT-UYVY:
		252
		253	- ``V4L2_PIX_FMT_UYVY``
		254	- 'UYVY'
		255
		256	- Cb\ :sub:`0`
		257	- Y'\ :sub:`0`
		258	- Cr\ :sub:`0`
		259	- Y'\ :sub:`1`
		260	- Cb\ :sub:`2`
		261	- Y'\ :sub:`2`
		262	- Cr\ :sub:`2`
344	- Y'\ :sub:`3`	263	- Y'\ :sub:`3`
		264	* .. _V4L2-PIX-FMT-VYUY:
		265
		266	- ``V4L2_PIX_FMT_VYUY``
		267	- 'VYUY'
		268
		269	- Cr\ :sub:`0`
		270	- Y'\ :sub:`0`
		271	- Cb\ :sub:`0`
		272	- Y'\ :sub:`1`
		273	- Cr\ :sub:`2`
345	- Y'\ :sub:`2`	274	- Y'\ :sub:`2`
		275	- Cb\ :sub:`2`
		276	- Y'\ :sub:`3`
		277	* .. _V4L2-PIX-FMT-YUYV:
		278
		279	- ``V4L2_PIX_FMT_YUYV``
		280	- 'YUYV'
		281
		282	- Y'\ :sub:`0`
		283	- Cb\ :sub:`0`
346	- Y'\ :sub:`1`	284	- Y'\ :sub:`1`
		285	- Cr\ :sub:`0`
		286	- Y'\ :sub:`2`
		287	- Cb\ :sub:`2`
		288	- Y'\ :sub:`3`
		289	- Cr\ :sub:`2`
		290	* .. _V4L2-PIX-FMT-YVYU:
		291
		292	- ``V4L2_PIX_FMT_YVYU``
		293	- 'YVYU'
		294
347	- Y'\ :sub:`0`	295	- Y'\ :sub:`0`
		296	- Cr\ :sub:`0`
		297	- Y'\ :sub:`1`
		298	- Cb\ :sub:`0`
		299	- Y'\ :sub:`2`
		300	- Cr\ :sub:`2`
		301	- Y'\ :sub:`3`
		302	- Cb\ :sub:`2`
348		303
349	-	304	Color Sample Location:
350	-	305	Chroma samples are :ref:`interstitially sited<yuv-chroma-centered>`
351	-	306	horizontally.
352	-
353	-
354	-
355	-
356	-
357		307
358	.. raw:: latex
359		308
360	\endgroup	309	4:1:1 Subsampling
		310	=================
		311
		312	This format subsamples the chroma components horizontally by 4, storing 8
		313	pixels in 12 bytes.
		314
		315	.. flat-table:: Packed YUV 4:1:1 Formats
		316	:header-rows: 1
		317	:stub-columns: 0
		318
		319	* - Identifier
		320	- Code
		321	- Byte 0
		322	- Byte 1
		323	- Byte 2
		324	- Byte 3
		325	- Byte 4
		326	- Byte 5
		327	- Byte 6
		328	- Byte 7
		329	- Byte 8
		330	- Byte 9
		331	- Byte 10
		332	- Byte 11
		333	* .. _V4L2-PIX-FMT-Y41P:
		334
		335	- ``V4L2_PIX_FMT_Y41P``
		336	- 'Y41P'
		337
		338	- Cb\ :sub:`0`
		339	- Y'\ :sub:`0`
		340	- Cr\ :sub:`0`
		341	- Y'\ :sub:`1`
		342	- Cb\ :sub:`4`
		343	- Y'\ :sub:`2`
		344	- Cr\ :sub:`4`
		345	- Y'\ :sub:`3`
		346	- Y'\ :sub:`4`
		347	- Y'\ :sub:`5`
		348	- Y'\ :sub:`6`
		349	- Y'\ :sub:`7`
361		350
362	.. note::	351	.. note::
363		352
364	#) Bit 7 is the most significant bit;	353	Do not confuse ``V4L2_PIX_FMT_Y41P`` with
		354	:ref:`V4L2_PIX_FMT_YUV411P <V4L2-PIX-FMT-YUV411P>`. Y41P is derived from
		355	"YUV 4:1:1 packed", while YUV411P stands for "YUV 4:1:1 planar".
365		356
366	#) The value of a = alpha bits is undefined when reading from the driver,	357	Color Sample Location:
367	ignored when writing to the driver, except when alpha blending has	358	Chroma samples are :ref:`interstitially sited<yuv-chroma-centered>`
368	been negotiated for a :ref:`Video Overlay <overlay>` or	359	horizontally.
369	:ref:`Video Output Overlay <osd>` for the formats Y444, YUV555 and
370	YUV4. However, for formats AYUV32 and VUYA32, the alpha component is
371	expected to contain a meaningful value that can be used by drivers
372	and applications. And, the formats XYUV32 and VUYX32 contain undefined
373	alpha values that must be ignored by all applications and drivers.

Documentation/userspace-api/media/v4l/pixfmt-rgb.rst+185−486

@@ -6,13 +6,62 @@ · 5 unmodified lines
6	RGB Formats	6	RGB Formats
7	***********	7	***********
8		8
9	Description	9	These formats encode each pixel as a triplet of RGB values. They are packed
10	===========	10	formats, meaning that the RGB values for one pixel are stored consecutively in
11		11	memory and each pixel consumes an integer number of bytes. When the number of
12	These formats are designed to match the pixel formats of typical PC	12	bits required to store a pixel is not aligned to a byte boundary, the data is
13	graphics frame buffers. They occupy 8, 16, 24 or 32 bits per pixel.	13	padded with additional bits to fill the remaining byte.
14	These are all packed-pixel formats, meaning all the data for a pixel lie	14
15	next to each other in memory.	15	The formats differ by the number of bits per RGB component (typically but not
		16	always the same for all components), the order of components in memory, and the
		17	presence of an alpha component or additional padding bits.
		18
		19	The usage and value of the alpha bits in formats that support them (named ARGB
		20	or a permutation thereof, collectively referred to as alpha formats) depend on
		21	the device type and hardware operation. :ref:`Capture <capture>` devices
		22	(including capture queues of mem-to-mem devices) fill the alpha component in
		23	memory. When the device captures an alpha channel the alpha component will have
		24	a meaningful value. Otherwise, when the device doesn't capture an alpha channel
		25	but can set the alpha bit to a user-configurable value, the
		26	:ref:`V4L2_CID_ALPHA_COMPONENT <v4l2-alpha-component>` control is used to
		27	specify that alpha value, and the alpha component of all pixels will be set to
		28	the value specified by that control. Otherwise a corresponding format without
		29	an alpha component (XRGB or XBGR) must be used instead of an alpha format.
		30
		31	:ref:`Output <output>` devices (including output queues of mem-to-mem devices
		32	and :ref:`video output overlay <osd>` devices) read the alpha component from
		33	memory. When the device processes the alpha channel the alpha component must be
		34	filled with meaningful values by applications. Otherwise a corresponding format
		35	without an alpha component (XRGB or XBGR) must be used instead of an alpha
		36	format.
		37
		38	Formats that contain padding bits are named XRGB (or a permutation thereof).
		39	The padding bits contain undefined values and must be ignored by applications,
		40	devices and drivers, for both :ref:`capture` and :ref:`output` devices.
		41
		42	.. note::
		43
		44	- In all the tables that follow, bit 7 is the most significant bit in a byte.
		45	- 'r', 'g' and 'b' denote bits of the red, green and blue components
		46	respectively. 'a' denotes bits of the alpha component (if supported by the
		47	format), and 'x' denotes padding bits.
		48
		49
		50	Less Than 8 Bits Per Component
		51	==============================
		52
		53	These formats store an RGB triplet in one, two or four bytes. They are named
		54	based on the order of the RGB components as seen in a 8-, 16- or 32-bit word,
		55	which is then stored in memory in little endian byte order (unless otherwise
		56	noted by the presence of bit 31 in the 4CC value), and on the number of bits
		57	for each component. For instance, the RGB565 format stores a pixel in a 16-bit
		58	word [15:0] laid out at as [R\ :sub:`4` R\ :sub:`3` R\ :sub:`2` R\ :sub:`1`
		59	R\ :sub:`0` G\ :sub:`5` G\ :sub:`4` G\ :sub:`3` G\ :sub:`2` G\ :sub:`1`
		60	G\ :sub:`0` B\ :sub:`4` B\ :sub:`3` B\ :sub:`2` B\ :sub:`1` B\ :sub:`0`], and
		61	stored in memory in two bytes, [R\ :sub:`4` R\ :sub:`3` R\ :sub:`2` R\ :sub:`1`
		62	R\ :sub:`0` G\ :sub:`5` G\ :sub:`4` G\ :sub:`3`] followed by [G\ :sub:`2`
		63	G\ :sub:`1` G\ :sub:`0` B\ :sub:`4` B\ :sub:`3` B\ :sub:`2` B\ :sub:`1`
		64	B\ :sub:`0`].
16		65
17	.. raw:: latex	66	.. raw:: latex
18		67
@@ -23,7 +72,7 @@ next to each other in memory. · 4 unmodified lines
23	.. tabularcolumns:: \|p{2.8cm}\|p{2.0cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|	72	.. tabularcolumns:: \|p{2.8cm}\|p{2.0cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|p{0.22cm}\|
24		73
25		74
26	.. flat-table:: RGB Image Formats	75	.. flat-table:: RGB Formats With Less Than 8 Bits Per Component
27	:header-rows: 2	76	:header-rows: 2
28	:stub-columns: 0	77	:stub-columns: 0
29		78
@@ -121,10 +170,10 @@ next to each other in memory. · 91 unmodified lines
121	- b\ :sub:`1`	170	- b\ :sub:`1`
122	- b\ :sub:`0`	171	- b\ :sub:`0`
123		172
124	- `-`	173	- x
125	- `-`	174	- x
126	- `-`	175	- x
127	- `-`	176	- x
128	- r\ :sub:`3`	177	- r\ :sub:`3`
129	- r\ :sub:`2`	178	- r\ :sub:`2`
130	- r\ :sub:`1`	179	- r\ :sub:`1`
@@ -162,10 +211,10 @@ next to each other in memory. · 31 unmodified lines
162	- b\ :sub:`2`	211	- b\ :sub:`2`
163	- b\ :sub:`1`	212	- b\ :sub:`1`
164	- b\ :sub:`0`	213	- b\ :sub:`0`
165	- `-`	214	- x
166	- `-`	215	- x
167	- `-`	216	- x
168	- `-`	217	- x
169		218
170	- r\ :sub:`3`	219	- r\ :sub:`3`
171	- r\ :sub:`2`	220	- r\ :sub:`2`
@@ -213,10 +262,10 @@ next to each other in memory. · 41 unmodified lines
213	- r\ :sub:`1`	262	- r\ :sub:`1`
214	- r\ :sub:`0`	263	- r\ :sub:`0`
215		264
216	- `-`	265	- x
217	- `-`	266	- x
218	- `-`	267	- x
219	- `-`	268	- x
220	- b\ :sub:`3`	269	- b\ :sub:`3`
221	- b\ :sub:`2`	270	- b\ :sub:`2`
222	- b\ :sub:`1`	271	- b\ :sub:`1`
@@ -254,10 +303,10 @@ next to each other in memory. · 31 unmodified lines
254	- r\ :sub:`2`	303	- r\ :sub:`2`
255	- r\ :sub:`1`	304	- r\ :sub:`1`
256	- r\ :sub:`0`	305	- r\ :sub:`0`
257	- `-`	306	- x
258	- `-`	307	- x
259	- `-`	308	- x
260	- `-`	309	- x
261		310
262	- b\ :sub:`3`	311	- b\ :sub:`3`
263	- b\ :sub:`2`	312	- b\ :sub:`2`
@@ -305,7 +354,7 @@ next to each other in memory. · 41 unmodified lines
305	- b\ :sub:`1`	354	- b\ :sub:`1`
306	- b\ :sub:`0`	355	- b\ :sub:`0`
307		356
308	- `-`	357	- x
309	- r\ :sub:`4`	358	- r\ :sub:`4`
310	- r\ :sub:`3`	359	- r\ :sub:`3`
311	- r\ :sub:`2`	360	- r\ :sub:`2`
@@ -349,7 +398,7 @@ next to each other in memory. · 37 unmodified lines
349	- b\ :sub:`2`	398	- b\ :sub:`2`
350	- b\ :sub:`1`	399	- b\ :sub:`1`
351	- b\ :sub:`0`	400	- b\ :sub:`0`
352	- `-`	401	- x
353		402
354	- r\ :sub:`4`	403	- r\ :sub:`4`
355	- r\ :sub:`3`	404	- r\ :sub:`3`
@@ -397,7 +446,7 @@ next to each other in memory. · 41 unmodified lines
397	- r\ :sub:`1`	446	- r\ :sub:`1`
398	- r\ :sub:`0`	447	- r\ :sub:`0`
399		448
400	- `-`	449	- x
401	- b\ :sub:`4`	450	- b\ :sub:`4`
402	- b\ :sub:`3`	451	- b\ :sub:`3`
403	- b\ :sub:`2`	452	- b\ :sub:`2`
@@ -441,7 +490,7 @@ next to each other in memory. · 37 unmodified lines
441	- r\ :sub:`2`	490	- r\ :sub:`2`
442	- r\ :sub:`1`	491	- r\ :sub:`1`
443	- r\ :sub:`0`	492	- r\ :sub:`0`
444	- `-`	493	- x
445		494
446	- b\ :sub:`4`	495	- b\ :sub:`4`
447	- b\ :sub:`3`	496	- b\ :sub:`3`
@@ -503,7 +552,7 @@ next to each other in memory. · 55 unmodified lines
503	- ``V4L2_PIX_FMT_XRGB555X``	552	- ``V4L2_PIX_FMT_XRGB555X``
504	- 'XR15' \| (1 << 31)	553	- 'XR15' \| (1 << 31)
505		554
506	- `-`	555	- x
507	- r\ :sub:`4`	556	- r\ :sub:`4`
508	- r\ :sub:`3`	557	- r\ :sub:`3`
509	- r\ :sub:`2`	558	- r\ :sub:`2`
@@ -544,538 +593,188 @@ next to each other in memory. · 34 unmodified lines
544	- b\ :sub:`1`	593	- b\ :sub:`1`
545	- b\ :sub:`0`	594	- b\ :sub:`0`
546	-	595	-
547	* .. _V4L2-PIX-FMT-BGR24:	596	* .. _V4L2-PIX-FMT-BGR666:
548		597
549	- ``V4L2_PIX_FMT_BGR24``	598	- ``V4L2_PIX_FMT_BGR666``
550	- 'BGR3'	599	- 'BGRH'
551		600
552	- b\ :sub:`7`
553	- b\ :sub:`6`
554	- b\ :sub:`5`	601	- b\ :sub:`5`
555	- b\ :sub:`4`	602	- b\ :sub:`4`
556	- b\ :sub:`3`	603	- b\ :sub:`3`
557	- b\ :sub:`2`	604	- b\ :sub:`2`
558	- b\ :sub:`1`	605	- b\ :sub:`1`
559	- b\ :sub:`0`	606	- b\ :sub:`0`
560
561	- g\ :sub:`7`
562	- g\ :sub:`6`
563	- g\ :sub:`5`	607	- g\ :sub:`5`
564	- g\ :sub:`4`	608	- g\ :sub:`4`
		609
565	- g\ :sub:`3`	610	- g\ :sub:`3`
566	- g\ :sub:`2`	611	- g\ :sub:`2`
567	- g\ :sub:`1`	612	- g\ :sub:`1`
568	- g\ :sub:`0`	613	- g\ :sub:`0`
569
570	- r\ :sub:`7`
571	- r\ :sub:`6`
572	- r\ :sub:`5`	614	- r\ :sub:`5`
573	- r\ :sub:`4`	615	- r\ :sub:`4`
574	- r\ :sub:`3`	616	- r\ :sub:`3`
575	- r\ :sub:`2`	617	- r\ :sub:`2`
		618
576	- r\ :sub:`1`	619	- r\ :sub:`1`
577	- r\ :sub:`0`	620	- r\ :sub:`0`
578	-	621	- x
579	* .. _V4L2-PIX-FMT-RGB24:	622	- x
		623	- x
		624	- x
		625	- x
		626	- x
580		627
581	- ``V4L2_PIX_FMT_RGB24``	628	- x
582	- 'RGB3'	629	- x
		630	- x
		631	- x
		632	- x
		633	- x
		634	- x
		635	- x
583		636
584	- r\ :sub:`7`	637	.. raw:: latex
585	- r\ :sub:`6`
586	- r\ :sub:`5`
587	- r\ :sub:`4`
588	- r\ :sub:`3`
589	- r\ :sub:`2`
590	- r\ :sub:`1`
591	- r\ :sub:`0`
592		638
593	- g\ :sub:`7`	639	\endgroup
594	- g\ :sub:`6`
595	- g\ :sub:`5`
596	- g\ :sub:`4`
597	- g\ :sub:`3`
598	- g\ :sub:`2`
599	- g\ :sub:`1`
600	- g\ :sub:`0`
601		640
602	- b\ :sub:`7`
603	- b\ :sub:`6`
604	- b\ :sub:`5`
605	- b\ :sub:`4`
606	- b\ :sub:`3`
607	- b\ :sub:`2`
608	- b\ :sub:`1`
609	- b\ :sub:`0`
610	-
611	* .. _V4L2-PIX-FMT-BGR666:
612		641
613	- ``V4L2_PIX_FMT_BGR666``	642	8 Bits Per Component
614	- 'BGRH'	643	====================
615		644
616	- b\ :sub:`5`	645	These formats store an RGB triplet in three or four bytes. They are named based
617	- b\ :sub:`4`	646	on the order of the RGB components as stored in memory, and on the total number
618	- b\ :sub:`3`	647	of bits per pixel. For instance, RGB24 format stores a pixel with [R\ :sub:`7`
619	- b\ :sub:`2`	648	R\ :sub:`6` R\ :sub:`5` R\ :sub:`4` R\ :sub:`3` R\ :sub:`2` R\ :sub:`1`
620	- b\ :sub:`1`	649	R\ :sub:`0`] in the first byte, [G\ :sub:`7` G\ :sub:`6` G\ :sub:`5` G\ :sub:`4`
621	- b\ :sub:`0`	650	G\ :sub:`3` G\ :sub:`2` G\ :sub:`1` G\ :sub:`0`] in the second byte and
622	- g\ :sub:`5`	651	[B\ :sub:`7` B\ :sub:`6` B\ :sub:`5` B\ :sub:`4` B\ :sub:`3` B\ :sub:`2`
623	- g\ :sub:`4`	652	B\ :sub:`1` B\ :sub:`0`] in the third byte. This differs from the DRM format
		653	nomenclature that instead use the order of components as seen in a 24- or
		654	32-bit little endian word.
624		655
625	- g\ :sub:`3`	656	.. raw:: latex
626	- g\ :sub:`2`
627	- g\ :sub:`1`
628	- g\ :sub:`0`
629	- r\ :sub:`5`
630	- r\ :sub:`4`
631	- r\ :sub:`3`
632	- r\ :sub:`2`
633		657
634	- r\ :sub:`1`	658	\begingroup
635	- r\ :sub:`0`	659	\tiny
636	- `-`	660	\setlength{\tabcolsep}{2pt}
637	- `-`
638	- `-`
639	- `-`
640	- `-`
641	- `-`
642
643	- `-`
644	- `-`
645	- `-`
646	- `-`
647	- `-`
648	- `-`
649	- `-`
650	- `-`
651	* .. _V4L2-PIX-FMT-ABGR32:
652		661
653	- ``V4L2_PIX_FMT_ABGR32``	662	.. tabularcolumns:: \|p{2.8cm}\|p{2.0cm}\|p{2.0cm}\|p{2.0cm}\|p{2.0cm}\|p{2.0cm}\|p{2.0cm}\|p{2.0cm}\|
654	- 'AR24'
655		663
656	- b\ :sub:`7`
657	- b\ :sub:`6`
658	- b\ :sub:`5`
659	- b\ :sub:`4`
660	- b\ :sub:`3`
661	- b\ :sub:`2`
662	- b\ :sub:`1`
663	- b\ :sub:`0`
664		664
665	- g\ :sub:`7`	665	.. flat-table:: RGB Formats With 8 Bits Per Component
666	- g\ :sub:`6`	666	:header-rows: 1
667	- g\ :sub:`5`	667	:stub-columns: 0
668	- g\ :sub:`4`
669	- g\ :sub:`3`
670	- g\ :sub:`2`
671	- g\ :sub:`1`
672	- g\ :sub:`0`
673		668
674	- r\ :sub:`7`	669	* - Identifier
675	- r\ :sub:`6`	670	- Code
676	- r\ :sub:`5`	671	- Byte 0 in memory
677	- r\ :sub:`4`	672	- Byte 1
678	- r\ :sub:`3`	673	- Byte 2
679	- r\ :sub:`2`	674	- Byte 3
680	- r\ :sub:`1`	675	* .. _V4L2-PIX-FMT-BGR24:
681	- r\ :sub:`0`
682		676
683	- a\ :sub:`7`	677	- ``V4L2_PIX_FMT_BGR24``
684	- a\ :sub:`6`	678	- 'BGR3'
685	- a\ :sub:`5`
686	- a\ :sub:`4`
687	- a\ :sub:`3`
688	- a\ :sub:`2`
689	- a\ :sub:`1`
690	- a\ :sub:`0`
691	* .. _V4L2-PIX-FMT-XBGR32:
692		679
693	- ``V4L2_PIX_FMT_XBGR32``	680	- G\ :sub:`7-0`
694	- 'XR24'	681	- B\ :sub:`7-0`
		682	- R\ :sub:`7-0`
		683	-
		684	* .. _V4L2-PIX-FMT-RGB24:
695		685
696	- b\ :sub:`7`	686	- ``V4L2_PIX_FMT_RGB24``
697	- b\ :sub:`6`	687	- 'RGB3'
698	- b\ :sub:`5`
699	- b\ :sub:`4`
700	- b\ :sub:`3`
701	- b\ :sub:`2`
702	- b\ :sub:`1`
703	- b\ :sub:`0`
704		688
705	- g\ :sub:`7`	689	- R\ :sub:`7-0`
706	- g\ :sub:`6`	690	- G\ :sub:`7-0`
707	- g\ :sub:`5`	691	- B\ :sub:`7-0`
708	- g\ :sub:`4`	692	-
709	- g\ :sub:`3`	693	* .. _V4L2-PIX-FMT-ABGR32:
710	- g\ :sub:`2`
711	- g\ :sub:`1`
712	- g\ :sub:`0`
713		694
714	- r\ :sub:`7`	695	- ``V4L2_PIX_FMT_ABGR32``
715	- r\ :sub:`6`	696	- 'AR24'
716	- r\ :sub:`5`
717	- r\ :sub:`4`
718	- r\ :sub:`3`
719	- r\ :sub:`2`
720	- r\ :sub:`1`
721	- r\ :sub:`0`
722		697
723	- `-`	698	- B\ :sub:`7-0`
724	- `-`	699	- G\ :sub:`7-0`
725	- `-`	700	- R\ :sub:`7-0`
726	- `-`	701	- A\ :sub:`7-0`
727	- `-`	702	* .. _V4L2-PIX-FMT-XBGR32:
728	- `-`	703
729	- `-`	704	- ``V4L2_PIX_FMT_XBGR32``
730	- `-`	705	- 'XR24'
		706
		707	- B\ :sub:`7-0`
		708	- G\ :sub:`7-0`
		709	- R\ :sub:`7-0`
		710	- X\ :sub:`7-0`
731	* .. _V4L2-PIX-FMT-BGRA32:	711	* .. _V4L2-PIX-FMT-BGRA32:
732		712
733	- ``V4L2_PIX_FMT_BGRA32``	713	- ``V4L2_PIX_FMT_BGRA32``
734	- 'RA24'	714	- 'RA24'
735		715
736	- a\ :sub:`7`	716	- A\ :sub:`7-0`
737	- a\ :sub:`6`	717	- B\ :sub:`7-0`
738	- a\ :sub:`5`	718	- G\ :sub:`7-0`
739	- a\ :sub:`4`	719	- R\ :sub:`7-0`
740	- a\ :sub:`3`
741	- a\ :sub:`2`
742	- a\ :sub:`1`
743	- a\ :sub:`0`
744
745	- b\ :sub:`7`
746	- b\ :sub:`6`
747	- b\ :sub:`5`
748	- b\ :sub:`4`
749	- b\ :sub:`3`
750	- b\ :sub:`2`
751	- b\ :sub:`1`
752	- b\ :sub:`0`
753
754	- g\ :sub:`7`
755	- g\ :sub:`6`
756	- g\ :sub:`5`
757	- g\ :sub:`4`
758	- g\ :sub:`3`
759	- g\ :sub:`2`
760	- g\ :sub:`1`
761	- g\ :sub:`0`
762
763	- r\ :sub:`7`
764	- r\ :sub:`6`
765	- r\ :sub:`5`
766	- r\ :sub:`4`
767	- r\ :sub:`3`
768	- r\ :sub:`2`
769	- r\ :sub:`1`
770	- r\ :sub:`0`
771	* .. _V4L2-PIX-FMT-BGRX32:	720	* .. _V4L2-PIX-FMT-BGRX32:
772		721
773	- ``V4L2_PIX_FMT_BGRX32``	722	- ``V4L2_PIX_FMT_BGRX32``
774	- 'RX24'	723	- 'RX24'
775		724
776	- `-`	725	- X\ :sub:`7-0`
777	- `-`	726	- B\ :sub:`7-0`
778	- `-`	727	- G\ :sub:`7-0`
779	- `-`	728	- R\ :sub:`7-0`
780	- `-`
781	- `-`
782	- `-`
783	- `-`
784
785	- b\ :sub:`7`
786	- b\ :sub:`6`
787	- b\ :sub:`5`
788	- b\ :sub:`4`
789	- b\ :sub:`3`
790	- b\ :sub:`2`
791	- b\ :sub:`1`
792	- b\ :sub:`0`
793
794	- g\ :sub:`7`
795	- g\ :sub:`6`
796	- g\ :sub:`5`
797	- g\ :sub:`4`
798	- g\ :sub:`3`
799	- g\ :sub:`2`
800	- g\ :sub:`1`
801	- g\ :sub:`0`
802
803	- r\ :sub:`7`
804	- r\ :sub:`6`
805	- r\ :sub:`5`
806	- r\ :sub:`4`
807	- r\ :sub:`3`
808	- r\ :sub:`2`
809	- r\ :sub:`1`
810	- r\ :sub:`0`
811	* .. _V4L2-PIX-FMT-RGBA32:	729	* .. _V4L2-PIX-FMT-RGBA32:
812		730
813	- ``V4L2_PIX_FMT_RGBA32``	731	- ``V4L2_PIX_FMT_RGBA32``
814	- 'AB24'	732	- 'AB24'
815		733
816	- r\ :sub:`7`	734	- R\ :sub:`7-0`
817	- r\ :sub:`6`	735	- G\ :sub:`7-0`
818	- r\ :sub:`5`	736	- B\ :sub:`7-0`
819	- r\ :sub:`4`	737	- A\ :sub:`7-0`
820	- r\ :sub:`3`
821	- r\ :sub:`2`
822	- r\ :sub:`1`
823	- r\ :sub:`0`
824
825	- g\ :sub:`7`
826	- g\ :sub:`6`
827	- g\ :sub:`5`
828	- g\ :sub:`4`
829	- g\ :sub:`3`
830	- g\ :sub:`2`
831	- g\ :sub:`1`
832	- g\ :sub:`0`
833
834	- b\ :sub:`7`
835	- b\ :sub:`6`
836	- b\ :sub:`5`
837	- b\ :sub:`4`
838	- b\ :sub:`3`
839	- b\ :sub:`2`
840	- b\ :sub:`1`
841	- b\ :sub:`0`
842
843	- a\ :sub:`7`
844	- a\ :sub:`6`
845	- a\ :sub:`5`
846	- a\ :sub:`4`
847	- a\ :sub:`3`
848	- a\ :sub:`2`
849	- a\ :sub:`1`
850	- a\ :sub:`0`
851	* .. _V4L2-PIX-FMT-RGBX32:	738	* .. _V4L2-PIX-FMT-RGBX32:
852		739
853	- ``V4L2_PIX_FMT_RGBX32``	740	- ``V4L2_PIX_FMT_RGBX32``
854	- 'XB24'	741	- 'XB24'
855		742
856	- r\ :sub:`7`	743	- R\ :sub:`7-0`
857	- r\ :sub:`6`	744	- G\ :sub:`7-0`
858	- r\ :sub:`5`	745	- B\ :sub:`7-0`
859	- r\ :sub:`4`	746	- X\ :sub:`7-0`
860	- r\ :sub:`3`
861	- r\ :sub:`2`
862	- r\ :sub:`1`
863	- r\ :sub:`0`
864
865	- g\ :sub:`7`
866	- g\ :sub:`6`
867	- g\ :sub:`5`
868	- g\ :sub:`4`
869	- g\ :sub:`3`
870	- g\ :sub:`2`
871	- g\ :sub:`1`
872	- g\ :sub:`0`
873
874	- b\ :sub:`7`
875	- b\ :sub:`6`
876	- b\ :sub:`5`
877	- b\ :sub:`4`
878	- b\ :sub:`3`
879	- b\ :sub:`2`
880	- b\ :sub:`1`
881	- b\ :sub:`0`
882
883	- `-`
884	- `-`
885	- `-`
886	- `-`
887	- `-`
888	- `-`
889	- `-`
890	- `-`
891	* .. _V4L2-PIX-FMT-ARGB32:	747	* .. _V4L2-PIX-FMT-ARGB32:
892		748
893	- ``V4L2_PIX_FMT_ARGB32``	749	- ``V4L2_PIX_FMT_ARGB32``
894	- 'BA24'	750	- 'BA24'
895		751
896	- a\ :sub:`7`	752	- A\ :sub:`7-0`
897	- a\ :sub:`6`	753	- R\ :sub:`7-0`
898	- a\ :sub:`5`	754	- G\ :sub:`7-0`
899	- a\ :sub:`4`	755	- B\ :sub:`7-0`
900	- a\ :sub:`3`
901	- a\ :sub:`2`
902	- a\ :sub:`1`
903	- a\ :sub:`0`
904
905	- r\ :sub:`7`
906	- r\ :sub:`6`
907	- r\ :sub:`5`
908	- r\ :sub:`4`
909	- r\ :sub:`3`
910	- r\ :sub:`2`
911	- r\ :sub:`1`
912	- r\ :sub:`0`
913
914	- g\ :sub:`7`
915	- g\ :sub:`6`
916	- g\ :sub:`5`
917	- g\ :sub:`4`
918	- g\ :sub:`3`
919	- g\ :sub:`2`
920	- g\ :sub:`1`
921	- g\ :sub:`0`
922
923	- b\ :sub:`7`
924	- b\ :sub:`6`
925	- b\ :sub:`5`
926	- b\ :sub:`4`
927	- b\ :sub:`3`
928	- b\ :sub:`2`
929	- b\ :sub:`1`
930	- b\ :sub:`0`
931	* .. _V4L2-PIX-FMT-XRGB32:	756	* .. _V4L2-PIX-FMT-XRGB32:
932		757
933	- ``V4L2_PIX_FMT_XRGB32``	758	- ``V4L2_PIX_FMT_XRGB32``
934	- 'BX24'	759	- 'BX24'
935		760
936	- `-`	761	- X\ :sub:`7-0`
937	- `-`	762	- R\ :sub:`7-0`
938	- `-`	763	- G\ :sub:`7-0`
939	- `-`	764	- B\ :sub:`7-0`
940	- `-`
941	- `-`
942	- `-`
943	- `-`
944
945	- r\ :sub:`7`
946	- r\ :sub:`6`
947	- r\ :sub:`5`
948	- r\ :sub:`4`
949	- r\ :sub:`3`
950	- r\ :sub:`2`
951	- r\ :sub:`1`
952	- r\ :sub:`0`
953
954	- g\ :sub:`7`
955	- g\ :sub:`6`
956	- g\ :sub:`5`
957	- g\ :sub:`4`
958	- g\ :sub:`3`
959	- g\ :sub:`2`
960	- g\ :sub:`1`
961	- g\ :sub:`0`
962
963	- b\ :sub:`7`
964	- b\ :sub:`6`
965	- b\ :sub:`5`
966	- b\ :sub:`4`
967	- b\ :sub:`3`
968	- b\ :sub:`2`
969	- b\ :sub:`1`
970	- b\ :sub:`0`
971		765
972	.. raw:: latex	766	.. raw:: latex
973		767
974	\endgroup	768	\endgroup
975		769
976	.. note:: Bit 7 is the most significant bit.
977
978	The usage and value of the alpha bits (a) in the ARGB and ABGR formats
979	(collectively referred to as alpha formats) depend on the device type
980	and hardware operation. :ref:`Capture <capture>` devices (including
981	capture queues of mem-to-mem devices) fill the alpha component in
982	memory. When the device outputs an alpha channel the alpha component
983	will have a meaningful value. Otherwise, when the device doesn't output
984	an alpha channel but can set the alpha bit to a user-configurable value,
985	the :ref:`V4L2_CID_ALPHA_COMPONENT <v4l2-alpha-component>` control
986	is used to specify that alpha value, and the alpha component of all
987	pixels will be set to the value specified by that control. Otherwise a
988	corresponding format without an alpha component (XRGB or XBGR) must be
989	used instead of an alpha format.
990
991	:ref:`Output <output>` devices (including output queues of mem-to-mem
992	devices and :ref:`video output overlay <osd>` devices) read the alpha
993	component from memory. When the device processes the alpha channel the
994	alpha component must be filled with meaningful values by applications.
995	Otherwise a corresponding format without an alpha component (XRGB or
996	XBGR) must be used instead of an alpha format.
997
998	The XRGB and XBGR formats contain undefined bits (-). Applications,
999	devices and drivers must ignore those bits, for both
1000	:ref:`capture` and :ref:`output` devices.
1001
1002	Byte Order.
1003	Each cell is one byte.
1004
1005
1006	.. raw:: latex
1007
1008	\small
1009
1010	.. tabularcolumns:: \|p{3.1cm}\|p{0.8cm}\|p{0.8cm}\|p{0.8cm}\|p{0.8cm}\|p{0.8cm}\|p{0.8cm}\|p{0.8cm}\|p{0.8cm}\|p{0.8cm}\|p{0.8cm}\|p{0.8cm}\|p{0.8cm}\|
1011
1012	.. flat-table:: RGB byte order
1013	:header-rows: 0
1014	:stub-columns: 0
1015	:widths: 11 3 3 3 3 3 3 3 3 3 3 3 3
1016
1017	* - start + 0:
1018	- B\ :sub:`00`
1019	- G\ :sub:`00`
1020	- R\ :sub:`00`
1021	- B\ :sub:`01`
1022	- G\ :sub:`01`
1023	- R\ :sub:`01`
1024	- B\ :sub:`02`
1025	- G\ :sub:`02`
1026	- R\ :sub:`02`
1027	- B\ :sub:`03`
1028	- G\ :sub:`03`
1029	- R\ :sub:`03`
1030	* - start + 12:
1031	- B\ :sub:`10`
1032	- G\ :sub:`10`
1033	- R\ :sub:`10`
1034	- B\ :sub:`11`
1035	- G\ :sub:`11`
1036	- R\ :sub:`11`
1037	- B\ :sub:`12`
1038	- G\ :sub:`12`
1039	- R\ :sub:`12`
1040	- B\ :sub:`13`
1041	- G\ :sub:`13`
1042	- R\ :sub:`13`
1043	* - start + 24:
1044	- B\ :sub:`20`
1045	- G\ :sub:`20`
1046	- R\ :sub:`20`
1047	- B\ :sub:`21`
1048	- G\ :sub:`21`
1049	- R\ :sub:`21`
1050	- B\ :sub:`22`
1051	- G\ :sub:`22`
1052	- R\ :sub:`22`
1053	- B\ :sub:`23`
1054	- G\ :sub:`23`
1055	- R\ :sub:`23`
1056	* - start + 36:
1057	- B\ :sub:`30`
1058	- G\ :sub:`30`
1059	- R\ :sub:`30`
1060	- B\ :sub:`31`
1061	- G\ :sub:`31`
1062	- R\ :sub:`31`
1063	- B\ :sub:`32`
1064	- G\ :sub:`32`
1065	- R\ :sub:`32`
1066	- B\ :sub:`33`
1067	- G\ :sub:`33`
1068	- R\ :sub:`33`
1069
1070	.. raw:: latex
1071
1072	\normalsize
1073		770
1074	Formats defined in :ref:`pixfmt-rgb-deprecated` are deprecated and	771	Deprecated RGB Formats
1075	must not be used by new drivers. They are documented here for reference.	772	======================
1076	The meaning of their alpha bits ``(a)`` are ill-defined and interpreted as in
1077	either the corresponding ARGB or XRGB format, depending on the driver.
1078		773
		774	Formats defined in :ref:`pixfmt-rgb-deprecated` are deprecated and must not be
		775	used by new drivers. They are documented here for reference. The meaning of
		776	their alpha bits ``(a)`` is ill-defined and they are interpreted as in either
		777	the corresponding ARGB or XRGB format, depending on the driver.
1079		778
1080	.. raw:: latex	779	.. raw:: latex
1081		780

Documentation/userspace-api/media/v4l/pixfmt-uyvy.rst+0−110

@@ -1,110 +0,0 @@
1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
2
3	.. _V4L2-PIX-FMT-UYVY:
4
5	**************************
6	V4L2_PIX_FMT_UYVY ('UYVY')
7	**************************
8
9
10	Variation of ``V4L2_PIX_FMT_YUYV`` with different order of samples in
11	memory
12
13
14	Description
15	===========
16
17	In this format each four bytes is two pixels. Each four bytes is two
18	Y's, a Cb and a Cr. Each Y goes to one of the pixels, and the Cb and Cr
19	belong to both pixels. As you can see, the Cr and Cb components have
20	half the horizontal resolution of the Y component.
21
22	Byte Order.
23	Each cell is one byte.
24
25
26	.. flat-table::
27	:header-rows: 0
28	:stub-columns: 0
29
30	* - start + 0:
31	- Cb\ :sub:`00`
32	- Y'\ :sub:`00`
33	- Cr\ :sub:`00`
34	- Y'\ :sub:`01`
35	- Cb\ :sub:`01`
36	- Y'\ :sub:`02`
37	- Cr\ :sub:`01`
38	- Y'\ :sub:`03`
39	* - start + 8:
40	- Cb\ :sub:`10`
41	- Y'\ :sub:`10`
42	- Cr\ :sub:`10`
43	- Y'\ :sub:`11`
44	- Cb\ :sub:`11`
45	- Y'\ :sub:`12`
46	- Cr\ :sub:`11`
47	- Y'\ :sub:`13`
48	* - start + 16:
49	- Cb\ :sub:`20`
50	- Y'\ :sub:`20`
51	- Cr\ :sub:`20`
52	- Y'\ :sub:`21`
53	- Cb\ :sub:`21`
54	- Y'\ :sub:`22`
55	- Cr\ :sub:`21`
56	- Y'\ :sub:`23`
57	* - start + 24:
58	- Cb\ :sub:`30`
59	- Y'\ :sub:`30`
60	- Cr\ :sub:`30`
61	- Y'\ :sub:`31`
62	- Cb\ :sub:`31`
63	- Y'\ :sub:`32`
64	- Cr\ :sub:`31`
65	- Y'\ :sub:`33`
66
67
68	Color Sample Location:
69
70
71
72	.. flat-table::
73	:header-rows: 0
74	:stub-columns: 0
75
76	* -
77	- 0
78	-
79	- 1
80	- 2
81	-
82	- 3
83	* - 0
84	- Y
85	- C
86	- Y
87	- Y
88	- C
89	- Y
90	* - 1
91	- Y
92	- C
93	- Y
94	- Y
95	- C
96	- Y
97	* - 2
98	- Y
99	- C
100	- Y
101	- Y
102	- C
103	- Y
104	* - 3
105	- Y
106	- C
107	- Y
108	- Y
109	- C
110	- Y

Documentation/userspace-api/media/v4l/pixfmt-vyuy.rst+0−108

@@ -1,108 +0,0 @@
1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
2
3	.. _V4L2-PIX-FMT-VYUY:
4
5	**************************
6	V4L2_PIX_FMT_VYUY ('VYUY')
7	**************************
8
9
10	Variation of ``V4L2_PIX_FMT_YUYV`` with different order of samples in
11	memory
12
13
14	Description
15	===========
16
17	In this format each four bytes is two pixels. Each four bytes is two
18	Y's, a Cb and a Cr. Each Y goes to one of the pixels, and the Cb and Cr
19	belong to both pixels. As you can see, the Cr and Cb components have
20	half the horizontal resolution of the Y component.
21
22	Byte Order.
23	Each cell is one byte.
24
25
26	.. flat-table::
27	:header-rows: 0
28	:stub-columns: 0
29
30	* - start + 0:
31	- Cr\ :sub:`00`
32	- Y'\ :sub:`00`
33	- Cb\ :sub:`00`
34	- Y'\ :sub:`01`
35	- Cr\ :sub:`01`
36	- Y'\ :sub:`02`
37	- Cb\ :sub:`01`
38	- Y'\ :sub:`03`
39	* - start + 8:
40	- Cr\ :sub:`10`
41	- Y'\ :sub:`10`
42	- Cb\ :sub:`10`
43	- Y'\ :sub:`11`
44	- Cr\ :sub:`11`
45	- Y'\ :sub:`12`
46	- Cb\ :sub:`11`
47	- Y'\ :sub:`13`
48	* - start + 16:
49	- Cr\ :sub:`20`
50	- Y'\ :sub:`20`
51	- Cb\ :sub:`20`
52	- Y'\ :sub:`21`
53	- Cr\ :sub:`21`
54	- Y'\ :sub:`22`
55	- Cb\ :sub:`21`
56	- Y'\ :sub:`23`
57	* - start + 24:
58	- Cr\ :sub:`30`
59	- Y'\ :sub:`30`
60	- Cb\ :sub:`30`
61	- Y'\ :sub:`31`
62	- Cr\ :sub:`31`
63	- Y'\ :sub:`32`
64	- Cb\ :sub:`31`
65	- Y'\ :sub:`33`
66
67
68	Color Sample Location:
69
70	.. flat-table::
71	:header-rows: 0
72	:stub-columns: 0
73
74	* -
75	- 0
76	-
77	- 1
78	-
79	- 2
80	- 3
81	* - 0
82	- Y
83	- C
84	- Y
85	- Y
86	- C
87	- Y
88	* - 1
89	- Y
90	- C
91	- Y
92	- Y
93	- C
94	- Y
95	* - 2
96	- Y
97	- C
98	- Y
99	- Y
100	- C
101	- Y
102	* - 3
103	- Y
104	- C
105	- Y
106	- Y
107	- C
108	- Y

Documentation/userspace-api/media/v4l/pixfmt-y10.rst+0−65

@@ -1,65 +0,0 @@
1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
2
3	.. _V4L2-PIX-FMT-Y10:
4
5	*************************
6	V4L2_PIX_FMT_Y10 ('Y10 ')
7	*************************
8
9
10	Grey-scale image
11
12
13	Description
14	===========
15
16	This is a grey-scale image with a depth of 10 bits per pixel. Pixels are
17	stored in 16-bit words with unused high bits padded with 0. The least
18	significant byte is stored at lower memory addresses (little-endian).
19
20	Byte Order.
21	Each cell is one byte.
22
23
24
25
26	.. flat-table::
27	:header-rows: 0
28	:stub-columns: 0
29
30	* - start + 0:
31	- Y'\ :sub:`00low`
32	- Y'\ :sub:`00high`
33	- Y'\ :sub:`01low`
34	- Y'\ :sub:`01high`
35	- Y'\ :sub:`02low`
36	- Y'\ :sub:`02high`
37	- Y'\ :sub:`03low`
38	- Y'\ :sub:`03high`
39	* - start + 8:
40	- Y'\ :sub:`10low`
41	- Y'\ :sub:`10high`
42	- Y'\ :sub:`11low`
43	- Y'\ :sub:`11high`
44	- Y'\ :sub:`12low`
45	- Y'\ :sub:`12high`
46	- Y'\ :sub:`13low`
47	- Y'\ :sub:`13high`
48	* - start + 16:
49	- Y'\ :sub:`20low`
50	- Y'\ :sub:`20high`
51	- Y'\ :sub:`21low`
52	- Y'\ :sub:`21high`
53	- Y'\ :sub:`22low`
54	- Y'\ :sub:`22high`
55	- Y'\ :sub:`23low`
56	- Y'\ :sub:`23high`
57	* - start + 24:
58	- Y'\ :sub:`30low`
59	- Y'\ :sub:`30high`
60	- Y'\ :sub:`31low`
61	- Y'\ :sub:`31high`
62	- Y'\ :sub:`32low`
63	- Y'\ :sub:`32high`
64	- Y'\ :sub:`33low`
65	- Y'\ :sub:`33high`

Documentation/userspace-api/media/v4l/pixfmt-y10b.rst+0−33

@@ -1,33 +0,0 @@
1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
2
3	.. _V4L2-PIX-FMT-Y10BPACK:
4
5	******************************
6	V4L2_PIX_FMT_Y10BPACK ('Y10B')
7	******************************
8
9	Grey-scale image as a bit-packed array
10
11
12	Description
13	===========
14
15	This is a packed grey-scale image format with a depth of 10 bits per
16	pixel. Pixels are stored in a bit-packed array of 10bit bits per pixel,
17	with no padding between them and with the most significant bits coming
18	first from the left.
19
20	Bit-packed representation.
21
22	pixels cross the byte boundary and have a ratio of 5 bytes for each 4
23	pixels.
24
25	.. flat-table::
26	:header-rows: 0
27	:stub-columns: 0
28
29	* - Y'\ :sub:`00[9:2]`
30	- Y'\ :sub:`00[1:0]`\ Y'\ :sub:`01[9:4]`
31	- Y'\ :sub:`01[3:0]`\ Y'\ :sub:`02[9:6]`
32	- Y'\ :sub:`02[5:0]`\ Y'\ :sub:`03[9:8]`
33	- Y'\ :sub:`03[7:0]`

Documentation/userspace-api/media/v4l/pixfmt-y10p.rst+0−43

@@ -1,43 +0,0 @@
1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
2
3	.. _V4L2-PIX-FMT-Y10P:
4
5	******************************
6	V4L2_PIX_FMT_Y10P ('Y10P')
7	******************************
8
9	Grey-scale image as a MIPI RAW10 packed array
10
11
12	Description
13	===========
14
15	This is a packed grey-scale image format with a depth of 10 bits per
16	pixel. Every four consecutive pixels are packed into 5 bytes. Each of
17	the first 4 bytes contain the 8 high order bits of the pixels, and
18	the 5th byte contains the 2 least significants bits of each pixel,
19	in the same order.
20
21	Bit-packed representation.
22
23	.. raw:: latex
24
25	\small
26
27	.. tabularcolumns:: \|p{1.2cm}\|\|p{1.2cm}\|\|p{1.2cm}\|\|p{1.2cm}\|p{3.2cm}\|p{3.2cm}\|
28
29	.. flat-table::
30	:header-rows: 0
31	:stub-columns: 0
32	:widths: 8 8 8 8 64
33
34	* - Y'\ :sub:`00[9:2]`
35	- Y'\ :sub:`01[9:2]`
36	- Y'\ :sub:`02[9:2]`
37	- Y'\ :sub:`03[9:2]`
38	- Y'\ :sub:`03[1:0]`\ (bits 7--6) Y'\ :sub:`02[1:0]`\ (bits 5--4)
39	Y'\ :sub:`01[1:0]`\ (bits 3--2) Y'\ :sub:`00[1:0]`\ (bits 1--0)
40
41	.. raw:: latex
42
43	\normalsize

Documentation/userspace-api/media/v4l/pixfmt-y12.rst+0−65

@@ -1,65 +0,0 @@
1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
2
3	.. _V4L2-PIX-FMT-Y12:
4
5	*************************
6	V4L2_PIX_FMT_Y12 ('Y12 ')
7	*************************
8
9
10	Grey-scale image
11
12
13	Description
14	===========
15
16	This is a grey-scale image with a depth of 12 bits per pixel. Pixels are
17	stored in 16-bit words with unused high bits padded with 0. The least
18	significant byte is stored at lower memory addresses (little-endian).
19
20	Byte Order.
21	Each cell is one byte.
22
23
24
25
26	.. flat-table::
27	:header-rows: 0
28	:stub-columns: 0
29
30	* - start + 0:
31	- Y'\ :sub:`00low`
32	- Y'\ :sub:`00high`
33	- Y'\ :sub:`01low`
34	- Y'\ :sub:`01high`
35	- Y'\ :sub:`02low`
36	- Y'\ :sub:`02high`
37	- Y'\ :sub:`03low`
38	- Y'\ :sub:`03high`
39	* - start + 8:
40	- Y'\ :sub:`10low`
41	- Y'\ :sub:`10high`
42	- Y'\ :sub:`11low`
43	- Y'\ :sub:`11high`
44	- Y'\ :sub:`12low`
45	- Y'\ :sub:`12high`
46	- Y'\ :sub:`13low`
47	- Y'\ :sub:`13high`
48	* - start + 16:
49	- Y'\ :sub:`20low`
50	- Y'\ :sub:`20high`
51	- Y'\ :sub:`21low`
52	- Y'\ :sub:`21high`
53	- Y'\ :sub:`22low`
54	- Y'\ :sub:`22high`
55	- Y'\ :sub:`23low`
56	- Y'\ :sub:`23high`
57	* - start + 24:
58	- Y'\ :sub:`30low`
59	- Y'\ :sub:`30high`
60	- Y'\ :sub:`31low`
61	- Y'\ :sub:`31high`
62	- Y'\ :sub:`32low`
63	- Y'\ :sub:`32high`
64	- Y'\ :sub:`33low`
65	- Y'\ :sub:`33high`

Documentation/userspace-api/media/v4l/pixfmt-y14.rst+0−65

@@ -1,65 +0,0 @@
1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
2
3	.. _V4L2-PIX-FMT-Y14:
4
5	*************************
6	V4L2_PIX_FMT_Y14 ('Y14 ')
7	*************************
8
9
10	Grey-scale image
11
12
13	Description
14	===========
15
16	This is a grey-scale image with a depth of 14 bits per pixel. Pixels are
17	stored in 16-bit words with unused high bits padded with 0. The least
18	significant byte is stored at lower memory addresses (little-endian).
19
20	Byte Order.
21	Each cell is one byte.
22
23
24
25
26	.. flat-table::
27	:header-rows: 0
28	:stub-columns: 0
29
30	* - start + 0:
31	- Y'\ :sub:`00low`
32	- Y'\ :sub:`00high`
33	- Y'\ :sub:`01low`
34	- Y'\ :sub:`01high`
35	- Y'\ :sub:`02low`
36	- Y'\ :sub:`02high`
37	- Y'\ :sub:`03low`
38	- Y'\ :sub:`03high`
39	* - start + 8:
40	- Y'\ :sub:`10low`
41	- Y'\ :sub:`10high`
42	- Y'\ :sub:`11low`
43	- Y'\ :sub:`11high`
44	- Y'\ :sub:`12low`
45	- Y'\ :sub:`12high`
46	- Y'\ :sub:`13low`
47	- Y'\ :sub:`13high`
48	* - start + 16:
49	- Y'\ :sub:`20low`
50	- Y'\ :sub:`20high`
51	- Y'\ :sub:`21low`
52	- Y'\ :sub:`21high`
53	- Y'\ :sub:`22low`
54	- Y'\ :sub:`22high`
55	- Y'\ :sub:`23low`
56	- Y'\ :sub:`23high`
57	* - start + 24:
58	- Y'\ :sub:`30low`
59	- Y'\ :sub:`30high`
60	- Y'\ :sub:`31low`
61	- Y'\ :sub:`31high`
62	- Y'\ :sub:`32low`
63	- Y'\ :sub:`32high`
64	- Y'\ :sub:`33low`
65	- Y'\ :sub:`33high`

Documentation/userspace-api/media/v4l/pixfmt-y16-be.rst+0−69

@@ -1,69 +0,0 @@
1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
2
3	.. _V4L2-PIX-FMT-Y16-BE:
4
5	****************************************
6	V4L2_PIX_FMT_Y16_BE ('Y16 ' \| (1 << 31))
7	****************************************
8
9
10	Grey-scale image
11
12
13	Description
14	===========
15
16	This is a grey-scale image with a depth of 16 bits per pixel. The most
17	significant byte is stored at lower memory addresses (big-endian).
18
19	.. note::
20
21	The actual sampling precision may be lower than 16 bits, for
22	example 10 bits per pixel with values in range 0 to 1023.
23
24	Byte Order.
25	Each cell is one byte.
26
27
28
29
30	.. flat-table::
31	:header-rows: 0
32	:stub-columns: 0
33
34	* - start + 0:
35	- Y'\ :sub:`00high`
36	- Y'\ :sub:`00low`
37	- Y'\ :sub:`01high`
38	- Y'\ :sub:`01low`
39	- Y'\ :sub:`02high`
40	- Y'\ :sub:`02low`
41	- Y'\ :sub:`03high`
42	- Y'\ :sub:`03low`
43	* - start + 8:
44	- Y'\ :sub:`10high`
45	- Y'\ :sub:`10low`
46	- Y'\ :sub:`11high`
47	- Y'\ :sub:`11low`
48	- Y'\ :sub:`12high`
49	- Y'\ :sub:`12low`
50	- Y'\ :sub:`13high`
51	- Y'\ :sub:`13low`
52	* - start + 16:
53	- Y'\ :sub:`20high`
54	- Y'\ :sub:`20low`
55	- Y'\ :sub:`21high`
56	- Y'\ :sub:`21low`
57	- Y'\ :sub:`22high`
58	- Y'\ :sub:`22low`
59	- Y'\ :sub:`23high`
60	- Y'\ :sub:`23low`
61	* - start + 24:
62	- Y'\ :sub:`30high`
63	- Y'\ :sub:`30low`
64	- Y'\ :sub:`31high`
65	- Y'\ :sub:`31low`
66	- Y'\ :sub:`32high`
67	- Y'\ :sub:`32low`
68	- Y'\ :sub:`33high`
69	- Y'\ :sub:`33low`

Documentation/userspace-api/media/v4l/pixfmt-y16.rst+0−69

@@ -1,69 +0,0 @@
1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
2
3	.. _V4L2-PIX-FMT-Y16:
4
5	*************************
6	V4L2_PIX_FMT_Y16 ('Y16 ')
7	*************************
8
9
10	Grey-scale image
11
12
13	Description
14	===========
15
16	This is a grey-scale image with a depth of 16 bits per pixel. The least
17	significant byte is stored at lower memory addresses (little-endian).
18
19	.. note::
20
21	The actual sampling precision may be lower than 16 bits, for
22	example 10 bits per pixel with values in range 0 to 1023.
23
24	Byte Order.
25	Each cell is one byte.
26
27
28
29
30	.. flat-table::
31	:header-rows: 0
32	:stub-columns: 0
33
34	* - start + 0:
35	- Y'\ :sub:`00low`
36	- Y'\ :sub:`00high`
37	- Y'\ :sub:`01low`
38	- Y'\ :sub:`01high`
39	- Y'\ :sub:`02low`
40	- Y'\ :sub:`02high`
41	- Y'\ :sub:`03low`
42	- Y'\ :sub:`03high`
43	* - start + 8:
44	- Y'\ :sub:`10low`
45	- Y'\ :sub:`10high`
46	- Y'\ :sub:`11low`
47	- Y'\ :sub:`11high`
48	- Y'\ :sub:`12low`
49	- Y'\ :sub:`12high`
50	- Y'\ :sub:`13low`
51	- Y'\ :sub:`13high`
52	* - start + 16:
53	- Y'\ :sub:`20low`
54	- Y'\ :sub:`20high`
55	- Y'\ :sub:`21low`
56	- Y'\ :sub:`21high`
57	- Y'\ :sub:`22low`
58	- Y'\ :sub:`22high`
59	- Y'\ :sub:`23low`
60	- Y'\ :sub:`23high`
61	* - start + 24:
62	- Y'\ :sub:`30low`
63	- Y'\ :sub:`30high`
64	- Y'\ :sub:`31low`
65	- Y'\ :sub:`31high`
66	- Y'\ :sub:`32low`
67	- Y'\ :sub:`32high`
68	- Y'\ :sub:`33low`
69	- Y'\ :sub:`33high`

Documentation/userspace-api/media/v4l/pixfmt-y41p.rst+0−151

@@ -1,151 +0,0 @@
1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
2
3	.. _V4L2-PIX-FMT-Y41P:
4
5	**************************
6	V4L2_PIX_FMT_Y41P ('Y41P')
7	**************************
8
9
10	Format with ¼ horizontal chroma resolution, also known as YUV 4:1:1
11
12
13	Description
14	===========
15
16	In this format each 12 bytes is eight pixels. In the twelve bytes are
17	two CbCr pairs and eight Y's. The first CbCr pair goes with the first
18	four Y's, and the second CbCr pair goes with the other four Y's. The Cb
19	and Cr components have one fourth the horizontal resolution of the Y
20	component.
21
22	Do not confuse this format with
23	:ref:`V4L2_PIX_FMT_YUV411P <V4L2-PIX-FMT-YUV411P>`. Y41P is derived
24	from "YUV 4:1:1 packed", while YUV411P stands for "YUV 4:1:1
25	planar".
26
27	Byte Order.
28	Each cell is one byte.
29
30
31
32
33	.. flat-table::
34	:header-rows: 0
35	:stub-columns: 0
36
37	* - start + 0:
38	- Cb\ :sub:`00`
39	- Y'\ :sub:`00`
40	- Cr\ :sub:`00`
41	- Y'\ :sub:`01`
42	- Cb\ :sub:`01`
43	- Y'\ :sub:`02`
44	- Cr\ :sub:`01`
45	- Y'\ :sub:`03`
46	- Y'\ :sub:`04`
47	- Y'\ :sub:`05`
48	- Y'\ :sub:`06`
49	- Y'\ :sub:`07`
50	* - start + 12:
51	- Cb\ :sub:`10`
52	- Y'\ :sub:`10`
53	- Cr\ :sub:`10`
54	- Y'\ :sub:`11`
55	- Cb\ :sub:`11`
56	- Y'\ :sub:`12`
57	- Cr\ :sub:`11`
58	- Y'\ :sub:`13`
59	- Y'\ :sub:`14`
60	- Y'\ :sub:`15`
61	- Y'\ :sub:`16`
62	- Y'\ :sub:`17`
63	* - start + 24:
64	- Cb\ :sub:`20`
65	- Y'\ :sub:`20`
66	- Cr\ :sub:`20`
67	- Y'\ :sub:`21`
68	- Cb\ :sub:`21`
69	- Y'\ :sub:`22`
70	- Cr\ :sub:`21`
71	- Y'\ :sub:`23`
72	- Y'\ :sub:`24`
73	- Y'\ :sub:`25`
74	- Y'\ :sub:`26`
75	- Y'\ :sub:`27`
76	* - start + 36:
77	- Cb\ :sub:`30`
78	- Y'\ :sub:`30`
79	- Cr\ :sub:`30`
80	- Y'\ :sub:`31`
81	- Cb\ :sub:`31`
82	- Y'\ :sub:`32`
83	- Cr\ :sub:`31`
84	- Y'\ :sub:`33`
85	- Y'\ :sub:`34`
86	- Y'\ :sub:`35`
87	- Y'\ :sub:`36`
88	- Y'\ :sub:`37`
89
90
91	Color Sample Location:
92
93	.. flat-table::
94	:header-rows: 0
95	:stub-columns: 0
96
97	* -
98	- 0
99	- 1
100	-
101	- 2
102	- 3
103	- 4
104	- 5
105	-
106	- 6
107	- 7
108	* - 0
109	- Y
110	- Y
111	- C
112	- Y
113	- Y
114	- Y
115	- Y
116	- C
117	- Y
118	- Y
119	* - 1
120	- Y
121	- Y
122	- C
123	- Y
124	- Y
125	- Y
126	- Y
127	- C
128	- Y
129	- Y
130	* - 2
131	- Y
132	- Y
133	- C
134	- Y
135	- Y
136	- Y
137	- Y
138	- C
139	- Y
140	- Y
141	* - 3
142	- Y
143	- Y
144	- C
145	- Y
146	- Y
147	- Y
148	- Y
149	- C
150	- Y
151	- Y

Documentation/userspace-api/media/v4l/pixfmt-yuv-luma.rst+126−0

@@ -0,0 +1,126 @@
	1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
	2
	3	.. _yuv-luma-only:
	4
	5	*****************
	6	Luma-Only Formats
	7	*****************
	8
	9	This family of formats only store the luma component of a Y'CbCr image. They
	10	are often referred to as greyscale formats.
	11
	12	.. note::
	13
	14	- In all the tables that follow, bit 7 is the most significant bit in a byte.
	15	- Formats are described with the minimum number of pixels needed to create a
	16	byte-aligned repeating pattern. `...` indicates repetition of the pattern.
	17	- Y'\ :sub:`x`\ [9:2] denotes bits 9 to 2 of the Y' value for pixel at colum
	18	`x`.
	19	- `0` denotes padding bits set to 0.
	20
	21
	22	.. flat-table:: Luma-Only Image Formats
	23	:header-rows: 1
	24	:stub-columns: 0
	25
	26	* - Identifier
	27	- Code
	28	- Byte 0
	29	- Byte 1
	30	- Byte 2
	31	- Byte 3
	32	- Byte 4
	33
	34	* .. _V4L2-PIX-FMT-GREY:
	35
	36	- ``V4L2_PIX_FMT_GREY``
	37	- 'GREY'
	38
	39	- Y'\ :sub:`0`\ [7:0]
	40	- ...
	41	- ...
	42	- ...
	43	- ...
	44
	45	* .. _V4L2-PIX-FMT-Y10:
	46
	47	- ``V4L2_PIX_FMT_Y10``
	48	- 'Y10 '
	49
	50	- Y'\ :sub:`0`\ [7:0]
	51	- `000000` Y'\ :sub:`0`\ [9:8]
	52	- ...
	53	- ...
	54	- ...
	55
	56	* .. _V4L2-PIX-FMT-Y10BPACK:
	57
	58	- ``V4L2_PIX_FMT_Y10BPACK``
	59	- 'Y10B'
	60
	61	- Y'\ :sub:`0`\ [9:2]
	62	- Y'\ :sub:`0`\ [1:0] Y'\ :sub:`1`\ [9:4]
	63	- Y'\ :sub:`1`\ [3:0] Y'\ :sub:`2`\ [9:6]
	64	- Y'\ :sub:`2`\ [5:0] Y'\ :sub:`3`\ [9:8]
	65	- Y'\ :sub:`3`\ [7:0]
	66
	67	* .. _V4L2-PIX-FMT-Y10P:
	68
	69	- ``V4L2_PIX_FMT_Y10P``
	70	- 'Y10P'
	71
	72	- Y'\ :sub:`0`\ [7:0]
	73	- Y'\ :sub:`1`\ [9:8]
	74	- Y'\ :sub:`2`\ [9:2]
	75	- Y'\ :sub:`3`\ [9:2]
	76	- Y'\ :sub:`3`\ [1:0] Y'\ :sub:`2`\ [1:0] Y'\ :sub:`1`\ [1:0] Y'\ :sub:`0`\ [1:0]
	77
	78	* .. _V4L2-PIX-FMT-Y12:
	79
	80	- ``V4L2_PIX_FMT_Y12``
	81	- 'Y12 '
	82
	83	- Y'\ :sub:`0`\ [7:0]
	84	- `0000` Y'\ :sub:`0`\ [11:8]
	85	- ...
	86	- ...
	87	- ...
	88
	89	* .. _V4L2-PIX-FMT-Y14:
	90
	91	- ``V4L2_PIX_FMT_Y14``
	92	- 'Y14 '
	93
	94	- Y'\ :sub:`0`\ [7:0]
	95	- `00` Y'\ :sub:`0`\ [13:8]
	96	- ...
	97	- ...
	98	- ...
	99
	100	* .. _V4L2-PIX-FMT-Y16:
	101
	102	- ``V4L2_PIX_FMT_Y16``
	103	- 'Y16 '
	104
	105	- Y'\ :sub:`0`\ [7:0]
	106	- Y'\ :sub:`0`\ [15:8]
	107	- ...
	108	- ...
	109	- ...
	110
	111	* .. _V4L2-PIX-FMT-Y16-BE:
	112
	113	- ``V4L2_PIX_FMT_Y16_BE``
	114	- 'Y16 ' \| (1U << 31)
	115
	116	- Y'\ :sub:`0`\ [15:8]
	117	- Y'\ :sub:`0`\ [7:0]
	118	- ...
	119	- ...
	120	- ...
	121
	122	.. note::
	123
	124	For the Y16 and Y16_BE formats, the actual sampling precision may be lower
	125	than 16 bits. For example, 10 bits per pixel uses values in the range 0 to
	126	1023.

Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst+950−0

@@ -0,0 +1,950 @@
	1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
	2
	3	.. planar-yuv:
	4
	5	******************
	6	Planar YUV formats
	7	******************
	8
	9	Planar formats split luma and chroma data in separate memory regions. They
	10	exist in two variants:
	11
	12	- Semi-planar formats use two planes. The first plane is the luma plane and
	13	stores the Y components. The second plane is the chroma plane and stores the
	14	Cb and Cr components interleaved.
	15
	16	- Fully planar formats use three planes to store the Y, Cb and Cr components
	17	separately.
	18
	19	Within a plane, components are stored in pixel order, which may be linear or
	20	tiled. Padding may be supported at the end of the lines, and the line stride of
	21	the chroma planes may be constrained by the line stride of the luma plane.
	22
	23	Some planar formats allow planes to be placed in independent memory locations.
	24	They are identified by an 'M' suffix in their name (such as in
	25	``V4L2_PIX_FMT_NV12M``). Those formats are intended to be used only in drivers
	26	and applications that support the multi-planar API, described in
	27	:ref:`planar-apis`. Unless explicitly documented as supporting non-contiguous
	28	planes, formats require the planes to follow each other immediately in memory.
	29
	30
	31	Semi-Planar YUV Formats
	32	=======================
	33
	34	These formats are commonly referred to as NV formats (NV12, NV16, ...). They
	35	use two planes, and store the luma components in the first plane and the chroma
	36	components in the second plane. The Cb and Cr components are interleaved in the
	37	chroma plane, with Cb and Cr always stored in pairs. The chroma order is
	38	exposed as different formats.
	39
	40	For memory contiguous formats, the number of padding pixels at the end of the
	41	chroma lines is identical to the padding of the luma lines. Without horizontal
	42	subsampling, the chroma line stride (in bytes) is thus equal to twice the luma
	43	line stride. With horizontal subsampling by 2, the chroma line stride is equal
	44	to the luma line stride. Vertical subsampling doesn't affect the line stride.
	45
	46	For non-contiguous formats, no constraints are enforced by the format on the
	47	relationship between the luma and chroma line padding and stride.
	48
	49	All components are stored with the same number of bits per component.
	50
	51	.. flat-table:: Overview of Semi-Planar YUV Formats
	52	:header-rows: 1
	53	:stub-columns: 0
	54
	55	* - Identifier
	56	- Code
	57	- Bits per component
	58	- Subsampling
	59	- Chroma order [1]_
	60	- Contiguous [2]_
	61	- Tiling [3]_
	62	* - V4L2_PIX_FMT_NV12
	63	- 'NV12'
	64	- 8
	65	- 4:2:0
	66	- Cb, Cr
	67	- Yes
	68	- Linear
	69	* - V4L2_PIX_FMT_NV21
	70	- 'NV21'
	71	- 8
	72	- 4:2:0
	73	- Cr, Cr
	74	- Yes
	75	- Linear
	76	* - V4L2_PIX_FMT_NV12M
	77	- 'NM12'
	78	- 8
	79	- 4:2:0
	80	- Cb, Cr
	81	- No
	82	- Linear
	83	* - V4L2_PIX_FMT_NV21M
	84	- 'NM21'
	85	- 8
	86	- 4:2:0
	87	- Cr, Cr
	88	- No
	89	- Linear
	90	* - V4L2_PIX_FMT_NV12MT
	91	- 'TM12'
	92	- 8
	93	- 4:2:0
	94	- Cb, Cr
	95	- No
	96	- 64x32 macroblocks
	97
	98	Horizontal Z order
	99	* - V4L2_PIX_FMT_NV12MT_16X16
	100	- 'VM12'
	101	- 8
	102	- 4:2:2
	103	- Cb, Cr
	104	- No
	105	- 16x16 macroblocks
	106	* - V4L2_PIX_FMT_NV16
	107	- 'NV16'
	108	- 8
	109	- 4:2:2
	110	- Cb, Cr
	111	- Yes
	112	- Linear
	113	* - V4L2_PIX_FMT_NV61
	114	- 'NV61'
	115	- 8
	116	- 4:2:2
	117	- Cr, Cr
	118	- Yes
	119	- Linear
	120	* - V4L2_PIX_FMT_NV16M
	121	- 'NM16'
	122	- 8
	123	- 4:2:2
	124	- Cb, Cr
	125	- No
	126	- Linear
	127	* - V4L2_PIX_FMT_NV61M
	128	- 'NM61'
	129	- 8
	130	- 4:2:2
	131	- Cr, Cr
	132	- No
	133	- Linear
	134	* - V4L2_PIX_FMT_NV24
	135	- 'NV24'
	136	- 8
	137	- 4:4:4
	138	- Cb, Cr
	139	- Yes
	140	- Linear
	141	* - V4L2_PIX_FMT_NV42
	142	- 'NV42'
	143	- 8
	144	- 4:4:4
	145	- Cr, Cr
	146	- Yes
	147	- Linear
	148
	149	.. note::
	150
	151	.. [1] Order of chroma samples in the second plane
	152	.. [2] Indicates if planes have to be contiguous in memory or can be
	153	disjoint
	154	.. [3] Macroblock size in pixels
	155
	156
	157	Color Sample Location:
	158	Chroma samples are :ref:`interstitially sited<yuv-chroma-centered>`
	159	horizontally.
	160
	161
	162	.. _V4L2-PIX-FMT-NV12:
	163	.. _V4L2-PIX-FMT-NV21:
	164	.. _V4L2-PIX-FMT-NV12M:
	165	.. _V4L2-PIX-FMT-NV21M:
	166
	167	NV12, NV21, NV12M and NV21M
	168	---------------------------
	169
	170	Semi-planar YUV 4:2:0 formats. The chroma plane is subsampled by 2 in each
	171	direction. Chroma lines contain half the number of pixels and the same number
	172	of bytes as luma lines, and the chroma plane contains half the number of lines
	173	of the luma plane.
	174
	175	.. flat-table:: Sample 4x4 NV12 Image
	176	:header-rows: 0
	177	:stub-columns: 0
	178
	179	* - start + 0:
	180	- Y'\ :sub:`00`
	181	- Y'\ :sub:`01`
	182	- Y'\ :sub:`02`
	183	- Y'\ :sub:`03`
	184	* - start + 4:
	185	- Y'\ :sub:`10`
	186	- Y'\ :sub:`11`
	187	- Y'\ :sub:`12`
	188	- Y'\ :sub:`13`
	189	* - start + 8:
	190	- Y'\ :sub:`20`
	191	- Y'\ :sub:`21`
	192	- Y'\ :sub:`22`
	193	- Y'\ :sub:`23`
	194	* - start + 12:
	195	- Y'\ :sub:`30`
	196	- Y'\ :sub:`31`
	197	- Y'\ :sub:`32`
	198	- Y'\ :sub:`33`
	199	* - start + 16:
	200	- Cb\ :sub:`00`
	201	- Cr\ :sub:`00`
	202	- Cb\ :sub:`01`
	203	- Cr\ :sub:`01`
	204	* - start + 20:
	205	- Cb\ :sub:`10`
	206	- Cr\ :sub:`10`
	207	- Cb\ :sub:`11`
	208	- Cr\ :sub:`11`
	209
	210	.. flat-table:: Sample 4x4 NV12M Image
	211	:header-rows: 0
	212	:stub-columns: 0
	213
	214	* - start0 + 0:
	215	- Y'\ :sub:`00`
	216	- Y'\ :sub:`01`
	217	- Y'\ :sub:`02`
	218	- Y'\ :sub:`03`
	219	* - start0 + 4:
	220	- Y'\ :sub:`10`
	221	- Y'\ :sub:`11`
	222	- Y'\ :sub:`12`
	223	- Y'\ :sub:`13`
	224	* - start0 + 8:
	225	- Y'\ :sub:`20`
	226	- Y'\ :sub:`21`
	227	- Y'\ :sub:`22`
	228	- Y'\ :sub:`23`
	229	* - start0 + 12:
	230	- Y'\ :sub:`30`
	231	- Y'\ :sub:`31`
	232	- Y'\ :sub:`32`
	233	- Y'\ :sub:`33`
	234	* -
	235	* - start1 + 0:
	236	- Cb\ :sub:`00`
	237	- Cr\ :sub:`00`
	238	- Cb\ :sub:`01`
	239	- Cr\ :sub:`01`
	240	* - start1 + 4:
	241	- Cb\ :sub:`10`
	242	- Cr\ :sub:`10`
	243	- Cb\ :sub:`11`
	244	- Cr\ :sub:`11`
	245
	246
	247	.. _V4L2-PIX-FMT-NV12MT:
	248	.. _V4L2-PIX-FMT-NV12MT-16X16:
	249
	250	NV12MT and MV12MT_16X16
	251	-----------------------
	252
	253	Semi-planar YUV 4:2:0 formats, using macroblock tiling. The chroma plane is
	254	subsampled by 2 in each direction. Chroma lines contain half the number of
	255	pixels and the same number of bytes as luma lines, and the chroma plane
	256	contains half the number of lines of the luma plane.
	257
	258	``V4L2_PIX_FMT_NV12MT_16X16`` stores pixel in 2D 16x16 macroblocks, and stores
	259	macroblocks linearly in memory. The line stride and image height must be
	260	aligned to a multiple of 16. The layouts of the luma and chroma planes are
	261	identical.
	262
	263	``V4L2_PIX_FMT_NV12MT`` stores pixels in 2D 64x32 macroblocks, and stores 2x2
	264	groups of macroblocks in Z-order in memory, alternating Z and mirrored Z shapes
	265	horizontally. The line stride must be a multiple of 128 pixels to ensure an
	266	integer number of Z shapes. The image height must be a multiple of 32 pixels.
	267	If the vertical resolution is an odd number of macroblocks, the last row of
	268	macroblocks is stored in linear order. The layouts of the luma and chroma
	269	planes are identical.
	270
	271	.. _nv12mt:
	272
	273	.. kernel-figure:: nv12mt.svg
	274	:alt: nv12mt.svg
	275	:align: center
	276
	277	V4L2_PIX_FMT_NV12MT macroblock Z shape memory layout
	278
	279	.. _nv12mt_ex:
	280
	281	.. kernel-figure:: nv12mt_example.svg
	282	:alt: nv12mt_example.svg
	283	:align: center
	284
	285	Example V4L2_PIX_FMT_NV12MT memory layout of macroblocks
	286
	287
	288	.. _V4L2-PIX-FMT-NV16:
	289	.. _V4L2-PIX-FMT-NV61:
	290	.. _V4L2-PIX-FMT-NV16M:
	291	.. _V4L2-PIX-FMT-NV61M:
	292
	293	NV16, NV61, NV16M and NV61M
	294	---------------------------
	295
	296	Semi-planar YUV 4:2:2 formats. The chroma plane is subsampled by 2 in the
	297	horizontal direction. Chroma lines contain half the number of pixels and the
	298	same number of bytes as luma lines, and the chroma plane contains the same
	299	number of lines as the luma plane.
	300
	301	.. flat-table:: Sample 4x4 NV16 Image
	302	:header-rows: 0
	303	:stub-columns: 0
	304
	305	* - start + 0:
	306	- Y'\ :sub:`00`
	307	- Y'\ :sub:`01`
	308	- Y'\ :sub:`02`
	309	- Y'\ :sub:`03`
	310	* - start + 4:
	311	- Y'\ :sub:`10`
	312	- Y'\ :sub:`11`
	313	- Y'\ :sub:`12`
	314	- Y'\ :sub:`13`
	315	* - start + 8:
	316	- Y'\ :sub:`20`
	317	- Y'\ :sub:`21`
	318	- Y'\ :sub:`22`
	319	- Y'\ :sub:`23`
	320	* - start + 12:
	321	- Y'\ :sub:`30`
	322	- Y'\ :sub:`31`
	323	- Y'\ :sub:`32`
	324	- Y'\ :sub:`33`
	325	* - start + 16:
	326	- Cb\ :sub:`00`
	327	- Cr\ :sub:`00`
	328	- Cb\ :sub:`01`
	329	- Cr\ :sub:`01`
	330	* - start + 20:
	331	- Cb\ :sub:`10`
	332	- Cr\ :sub:`10`
	333	- Cb\ :sub:`11`
	334	- Cr\ :sub:`11`
	335	* - start + 24:
	336	- Cb\ :sub:`20`
	337	- Cr\ :sub:`20`
	338	- Cb\ :sub:`21`
	339	- Cr\ :sub:`21`
	340	* - start + 28:
	341	- Cb\ :sub:`30`
	342	- Cr\ :sub:`30`
	343	- Cb\ :sub:`31`
	344	- Cr\ :sub:`31`
	345
	346	.. flat-table:: Sample 4x4 NV16M Image
	347	:header-rows: 0
	348	:stub-columns: 0
	349
	350	* - start0 + 0:
	351	- Y'\ :sub:`00`
	352	- Y'\ :sub:`01`
	353	- Y'\ :sub:`02`
	354	- Y'\ :sub:`03`
	355	* - start0 + 4:
	356	- Y'\ :sub:`10`
	357	- Y'\ :sub:`11`
	358	- Y'\ :sub:`12`
	359	- Y'\ :sub:`13`
	360	* - start0 + 8:
	361	- Y'\ :sub:`20`
	362	- Y'\ :sub:`21`
	363	- Y'\ :sub:`22`
	364	- Y'\ :sub:`23`
	365	* - start0 + 12:
	366	- Y'\ :sub:`30`
	367	- Y'\ :sub:`31`
	368	- Y'\ :sub:`32`
	369	- Y'\ :sub:`33`
	370	* -
	371	* - start1 + 0:
	372	- Cb\ :sub:`00`
	373	- Cr\ :sub:`00`
	374	- Cb\ :sub:`02`
	375	- Cr\ :sub:`02`
	376	* - start1 + 4:
	377	- Cb\ :sub:`10`
	378	- Cr\ :sub:`10`
	379	- Cb\ :sub:`12`
	380	- Cr\ :sub:`12`
	381	* - start1 + 8:
	382	- Cb\ :sub:`20`
	383	- Cr\ :sub:`20`
	384	- Cb\ :sub:`22`
	385	- Cr\ :sub:`22`
	386	* - start1 + 12:
	387	- Cb\ :sub:`30`
	388	- Cr\ :sub:`30`
	389	- Cb\ :sub:`32`
	390	- Cr\ :sub:`32`
	391
	392
	393	.. _V4L2-PIX-FMT-NV24:
	394	.. _V4L2-PIX-FMT-NV42:
	395
	396	NV24 and NV42
	397	-------------
	398
	399	Semi-planar YUV 4:4:4 formats. The chroma plane is subsampled by 2 in the
	400	horizontal direction. Chroma lines contain half the number of pixels and the
	401	same number of bytes as luma lines, and the chroma plane contains the same
	402	number of lines as the luma plane.
	403
	404	.. flat-table:: Sample 4x4 NV24 Image
	405	:header-rows: 0
	406	:stub-columns: 0
	407
	408	* - start + 0:
	409	- Y'\ :sub:`00`
	410	- Y'\ :sub:`01`
	411	- Y'\ :sub:`02`
	412	- Y'\ :sub:`03`
	413	* - start + 4:
	414	- Y'\ :sub:`10`
	415	- Y'\ :sub:`11`
	416	- Y'\ :sub:`12`
	417	- Y'\ :sub:`13`
	418	* - start + 8:
	419	- Y'\ :sub:`20`
	420	- Y'\ :sub:`21`
	421	- Y'\ :sub:`22`
	422	- Y'\ :sub:`23`
	423	* - start + 12:
	424	- Y'\ :sub:`30`
	425	- Y'\ :sub:`31`
	426	- Y'\ :sub:`32`
	427	- Y'\ :sub:`33`
	428	* - start + 16:
	429	- Cb\ :sub:`00`
	430	- Cr\ :sub:`00`
	431	- Cb\ :sub:`01`
	432	- Cr\ :sub:`01`
	433	- Cb\ :sub:`02`
	434	- Cr\ :sub:`02`
	435	- Cb\ :sub:`03`
	436	- Cr\ :sub:`03`
	437	* - start + 24:
	438	- Cb\ :sub:`10`
	439	- Cr\ :sub:`10`
	440	- Cb\ :sub:`11`
	441	- Cr\ :sub:`11`
	442	- Cb\ :sub:`12`
	443	- Cr\ :sub:`12`
	444	- Cb\ :sub:`13`
	445	- Cr\ :sub:`13`
	446	* - start + 32:
	447	- Cb\ :sub:`20`
	448	- Cr\ :sub:`20`
	449	- Cb\ :sub:`21`
	450	- Cr\ :sub:`21`
	451	- Cb\ :sub:`22`
	452	- Cr\ :sub:`22`
	453	- Cb\ :sub:`23`
	454	- Cr\ :sub:`23`
	455	* - start + 40:
	456	- Cb\ :sub:`30`
	457	- Cr\ :sub:`30`
	458	- Cb\ :sub:`31`
	459	- Cr\ :sub:`31`
	460	- Cb\ :sub:`32`
	461	- Cr\ :sub:`32`
	462	- Cb\ :sub:`33`
	463	- Cr\ :sub:`33`
	464
	465
	466	Fully Planar YUV Formats
	467	========================
	468
	469	These formats store the Y, Cb and Cr components in three separate planes. The
	470	luma plane comes first, and the order of the two chroma planes varies between
	471	formats. The two chroma planes always use the same subsampling.
	472
	473	For memory contiguous formats, the number of padding pixels at the end of the
	474	chroma lines is identical to the padding of the luma lines. The chroma line
	475	stride (in bytes) is thus equal to the luma line stride divided by the
	476	horizontal subsampling factor. Vertical subsampling doesn't affect the line
	477	stride.
	478
	479	For non-contiguous formats, no constraints are enforced by the format on the
	480	relationship between the luma and chroma line padding and stride.
	481
	482	All components are stored with the same number of bits per component.
	483
	484	.. flat-table:: Overview of Fully Planar YUV Formats
	485	:header-rows: 1
	486	:stub-columns: 0
	487
	488	* - Identifier
	489	- Code
	490	- Bits per component
	491	- Subsampling
	492	- Planes order [4]_
	493	- Contiguous [5]_
	494
	495	* - V4L2_PIX_FMT_YUV410
	496	- 'YUV9'
	497	- 8
	498	- 4:1:0
	499	- Y, Cb, Cr
	500	- Yes
	501	* - V4L2_PIX_FMT_YVU410
	502	- 'YVU9'
	503	- 8
	504	- 4:1:0
	505	- Y, Cr, Cb
	506	- Yes
	507	* - V4L2_PIX_FMT_YUV411P
	508	- '411P'
	509	- 8
	510	- 4:1:1
	511	- Y, Cb, Cr
	512	- Yes
	513	* - V4L2_PIX_FMT_YUV420M
	514	- 'YM12'
	515	- 8
	516	- 4:2:0
	517	- Y, Cb, Cr
	518	- No
	519	* - V4L2_PIX_FMT_YVU420M
	520	- 'YM21'
	521	- 8
	522	- 4:2:0
	523	- Y, Cr, Cb
	524	- No
	525	* - V4L2_PIX_FMT_YUV420
	526	- 'YU12'
	527	- 8
	528	- 4:2:0
	529	- Y, Cb, Cr
	530	- Yes
	531	* - V4L2_PIX_FMT_YVU420
	532	- 'YV12'
	533	- 8
	534	- 4:2:0
	535	- Y, Cr, Cb
	536	- Yes
	537	* - V4L2_PIX_FMT_YUV422P
	538	- '422P'
	539	- 8
	540	- 4:2:2
	541	- Y, Cb, Cr
	542	- Yes
	543	* - V4L2_PIX_FMT_YUV422M
	544	- 'YM16'
	545	- 8
	546	- 4:2:2
	547	- Y, Cb, Cr
	548	- No
	549	* - V4L2_PIX_FMT_YVU422M
	550	- 'YM61'
	551	- 8
	552	- 4:2:2
	553	- Y, Cr, Cb
	554	- No
	555	* - V4L2_PIX_FMT_YUV444M
	556	- 'YM24'
	557	- 8
	558	- 4:4:4
	559	- Y, Cb, Cr
	560	- No
	561	* - V4L2_PIX_FMT_YVU444M
	562	- 'YM42'
	563	- 8
	564	- 4:4:4
	565	- Y, Cr, Cb
	566	- No
	567
	568	.. note::
	569
	570	.. [4] Order of luma and chroma planes
	571	.. [5] Indicates if planes have to be contiguous in memory or can be
	572	disjoint
	573
	574
	575	Color Sample Location:
	576	Chroma samples are :ref:`interstitially sited<yuv-chroma-centered>`
	577	horizontally.
	578
	579	.. _V4L2-PIX-FMT-YUV410:
	580	.. _V4L2-PIX-FMT-YVU410:
	581
	582	YUV410 and YVU410
	583	-----------------
	584
	585	Planar YUV 4:1:0 formats. The chroma planes are subsampled by 4 in each
	586	direction. Chroma lines contain a quarter of the number of pixels and bytes of
	587	the luma lines, and the chroma planes contain a quarter of the number of lines
	588	of the luma plane.
	589
	590	.. flat-table:: Sample 4x4 YUV410 Image
	591	:header-rows: 0
	592	:stub-columns: 0
	593
	594	* - start + 0:
	595	- Y'\ :sub:`00`
	596	- Y'\ :sub:`01`
	597	- Y'\ :sub:`02`
	598	- Y'\ :sub:`03`
	599	* - start + 4:
	600	- Y'\ :sub:`10`
	601	- Y'\ :sub:`11`
	602	- Y'\ :sub:`12`
	603	- Y'\ :sub:`13`
	604	* - start + 8:
	605	- Y'\ :sub:`20`
	606	- Y'\ :sub:`21`
	607	- Y'\ :sub:`22`
	608	- Y'\ :sub:`23`
	609	* - start + 12:
	610	- Y'\ :sub:`30`
	611	- Y'\ :sub:`31`
	612	- Y'\ :sub:`32`
	613	- Y'\ :sub:`33`
	614	* - start + 16:
	615	- Cr\ :sub:`00`
	616	* - start + 17:
	617	- Cb\ :sub:`00`
	618
	619
	620	.. _V4L2-PIX-FMT-YUV411P:
	621
	622	YUV411P
	623	-------
	624
	625	Planar YUV 4:1:1 formats. The chroma planes are subsampled by 4 in the
	626	horizontal direction. Chroma lines contain a quarter of the number of pixels
	627	and bytes of the luma lines, and the chroma planes contain the same number of
	628	lines as the luma plane.
	629
	630	.. flat-table:: Sample 4x4 YUV411P Image
	631	:header-rows: 0
	632	:stub-columns: 0
	633
	634	* - start + 0:
	635	- Y'\ :sub:`00`
	636	- Y'\ :sub:`01`
	637	- Y'\ :sub:`02`
	638	- Y'\ :sub:`03`
	639	* - start + 4:
	640	- Y'\ :sub:`10`
	641	- Y'\ :sub:`11`
	642	- Y'\ :sub:`12`
	643	- Y'\ :sub:`13`
	644	* - start + 8:
	645	- Y'\ :sub:`20`
	646	- Y'\ :sub:`21`
	647	- Y'\ :sub:`22`
	648	- Y'\ :sub:`23`
	649	* - start + 12:
	650	- Y'\ :sub:`30`
	651	- Y'\ :sub:`31`
	652	- Y'\ :sub:`32`
	653	- Y'\ :sub:`33`
	654	* - start + 16:
	655	- Cb\ :sub:`00`
	656	* - start + 17:
	657	- Cb\ :sub:`10`
	658	* - start + 18:
	659	- Cb\ :sub:`20`
	660	* - start + 19:
	661	- Cb\ :sub:`30`
	662	* - start + 20:
	663	- Cr\ :sub:`00`
	664	* - start + 21:
	665	- Cr\ :sub:`10`
	666	* - start + 22:
	667	- Cr\ :sub:`20`
	668	* - start + 23:
	669	- Cr\ :sub:`30`
	670
	671
	672	.. _V4L2-PIX-FMT-YUV420:
	673	.. _V4L2-PIX-FMT-YVU420:
	674	.. _V4L2-PIX-FMT-YUV420M:
	675	.. _V4L2-PIX-FMT-YVU420M:
	676
	677	YUV420, YVU420, YUV420M and YVU420M
	678	-----------------------------------
	679
	680	Planar YUV 4:2:0 formats. The chroma planes are subsampled by 2 in each
	681	direction. Chroma lines contain half of the number of pixels and bytes of the
	682	luma lines, and the chroma planes contain half of the number of lines of the
	683	luma plane.
	684
	685	.. flat-table:: Sample 4x4 YUV420 Image
	686	:header-rows: 0
	687	:stub-columns: 0
	688
	689	* - start + 0:
	690	- Y'\ :sub:`00`
	691	- Y'\ :sub:`01`
	692	- Y'\ :sub:`02`
	693	- Y'\ :sub:`03`
	694	* - start + 4:
	695	- Y'\ :sub:`10`
	696	- Y'\ :sub:`11`
	697	- Y'\ :sub:`12`
	698	- Y'\ :sub:`13`
	699	* - start + 8:
	700	- Y'\ :sub:`20`
	701	- Y'\ :sub:`21`
	702	- Y'\ :sub:`22`
	703	- Y'\ :sub:`23`
	704	* - start + 12:
	705	- Y'\ :sub:`30`
	706	- Y'\ :sub:`31`
	707	- Y'\ :sub:`32`
	708	- Y'\ :sub:`33`
	709	* - start + 16:
	710	- Cr\ :sub:`00`
	711	- Cr\ :sub:`01`
	712	* - start + 18:
	713	- Cr\ :sub:`10`
	714	- Cr\ :sub:`11`
	715	* - start + 20:
	716	- Cb\ :sub:`00`
	717	- Cb\ :sub:`01`
	718	* - start + 22:
	719	- Cb\ :sub:`10`
	720	- Cb\ :sub:`11`
	721
	722	.. flat-table:: Sample 4x4 YUV420M Image
	723	:header-rows: 0
	724	:stub-columns: 0
	725
	726	* - start0 + 0:
	727	- Y'\ :sub:`00`
	728	- Y'\ :sub:`01`
	729	- Y'\ :sub:`02`
	730	- Y'\ :sub:`03`
	731	* - start0 + 4:
	732	- Y'\ :sub:`10`
	733	- Y'\ :sub:`11`
	734	- Y'\ :sub:`12`
	735	- Y'\ :sub:`13`
	736	* - start0 + 8:
	737	- Y'\ :sub:`20`
	738	- Y'\ :sub:`21`
	739	- Y'\ :sub:`22`
	740	- Y'\ :sub:`23`
	741	* - start0 + 12:
	742	- Y'\ :sub:`30`
	743	- Y'\ :sub:`31`
	744	- Y'\ :sub:`32`
	745	- Y'\ :sub:`33`
	746	* -
	747	* - start1 + 0:
	748	- Cb\ :sub:`00`
	749	- Cb\ :sub:`01`
	750	* - start1 + 2:
	751	- Cb\ :sub:`10`
	752	- Cb\ :sub:`11`
	753	* -
	754	* - start2 + 0:
	755	- Cr\ :sub:`00`
	756	- Cr\ :sub:`01`
	757	* - start2 + 2:
	758	- Cr\ :sub:`10`
	759	- Cr\ :sub:`11`
	760
	761
	762	.. _V4L2-PIX-FMT-YUV422P:
	763	.. _V4L2-PIX-FMT-YUV422M:
	764	.. _V4L2-PIX-FMT-YVU422M:
	765
	766	YUV422P, YUV422M and YVU422M
	767	----------------------------
	768
	769	Planar YUV 4:2:2 formats. The chroma planes are subsampled by 2 in the
	770	horizontal direction. Chroma lines contain half of the number of pixels and
	771	bytes of the luma lines, and the chroma planes contain the same number of lines
	772	as the luma plane.
	773
	774	.. flat-table:: Sample 4x4 YUV422P Image
	775	:header-rows: 0
	776	:stub-columns: 0
	777
	778	* - start + 0:
	779	- Y'\ :sub:`00`
	780	- Y'\ :sub:`01`
	781	- Y'\ :sub:`02`
	782	- Y'\ :sub:`03`
	783	* - start + 4:
	784	- Y'\ :sub:`10`
	785	- Y'\ :sub:`11`
	786	- Y'\ :sub:`12`
	787	- Y'\ :sub:`13`
	788	* - start + 8:
	789	- Y'\ :sub:`20`
	790	- Y'\ :sub:`21`
	791	- Y'\ :sub:`22`
	792	- Y'\ :sub:`23`
	793	* - start + 12:
	794	- Y'\ :sub:`30`
	795	- Y'\ :sub:`31`
	796	- Y'\ :sub:`32`
	797	- Y'\ :sub:`33`
	798	* - start + 16:
	799	- Cb\ :sub:`00`
	800	- Cb\ :sub:`01`
	801	* - start + 18:
	802	- Cb\ :sub:`10`
	803	- Cb\ :sub:`11`
	804	* - start + 20:
	805	- Cb\ :sub:`20`
	806	- Cb\ :sub:`21`
	807	* - start + 22:
	808	- Cb\ :sub:`30`
	809	- Cb\ :sub:`31`
	810	* - start + 24:
	811	- Cr\ :sub:`00`
	812	- Cr\ :sub:`01`
	813	* - start + 26:
	814	- Cr\ :sub:`10`
	815	- Cr\ :sub:`11`
	816	* - start + 28:
	817	- Cr\ :sub:`20`
	818	- Cr\ :sub:`21`
	819	* - start + 30:
	820	- Cr\ :sub:`30`
	821	- Cr\ :sub:`31`
	822
	823	.. flat-table:: Sample 4x4 YUV422M Image
	824	:header-rows: 0
	825	:stub-columns: 0
	826
	827	* - start0 + 0:
	828	- Y'\ :sub:`00`
	829	- Y'\ :sub:`01`
	830	- Y'\ :sub:`02`
	831	- Y'\ :sub:`03`
	832	* - start0 + 4:
	833	- Y'\ :sub:`10`
	834	- Y'\ :sub:`11`
	835	- Y'\ :sub:`12`
	836	- Y'\ :sub:`13`
	837	* - start0 + 8:
	838	- Y'\ :sub:`20`
	839	- Y'\ :sub:`21`
	840	- Y'\ :sub:`22`
	841	- Y'\ :sub:`23`
	842	* - start0 + 12:
	843	- Y'\ :sub:`30`
	844	- Y'\ :sub:`31`
	845	- Y'\ :sub:`32`
	846	- Y'\ :sub:`33`
	847	* -
	848	* - start1 + 0:
	849	- Cb\ :sub:`00`
	850	- Cb\ :sub:`01`
	851	* - start1 + 2:
	852	- Cb\ :sub:`10`
	853	- Cb\ :sub:`11`
	854	* - start1 + 4:
	855	- Cb\ :sub:`20`
	856	- Cb\ :sub:`21`
	857	* - start1 + 6:
	858	- Cb\ :sub:`30`
	859	- Cb\ :sub:`31`
	860	* -
	861	* - start2 + 0:
	862	- Cr\ :sub:`00`
	863	- Cr\ :sub:`01`
	864	* - start2 + 2:
	865	- Cr\ :sub:`10`
	866	- Cr\ :sub:`11`
	867	* - start2 + 4:
	868	- Cr\ :sub:`20`
	869	- Cr\ :sub:`21`
	870	* - start2 + 6:
	871	- Cr\ :sub:`30`
	872	- Cr\ :sub:`31`
	873
	874
	875	.. _V4L2-PIX-FMT-YUV444M:
	876	.. _V4L2-PIX-FMT-YVU444M:
	877
	878	YUV444M and YVU444M
	879	-------------------
	880
	881	Planar YUV 4:4:4 formats. The chroma planes are no subsampled. Chroma lines
	882	contain the same number of pixels and bytes of the luma lines, and the chroma
	883	planes contain the same number of lines as the luma plane.
	884
	885	.. flat-table:: Sample 4x4 YUV444M Image
	886	:header-rows: 0
	887	:stub-columns: 0
	888
	889	* - start0 + 0:
	890	- Y'\ :sub:`00`
	891	- Y'\ :sub:`01`
	892	- Y'\ :sub:`02`
	893	- Y'\ :sub:`03`
	894	* - start0 + 4:
	895	- Y'\ :sub:`10`
	896	- Y'\ :sub:`11`
	897	- Y'\ :sub:`12`
	898	- Y'\ :sub:`13`
	899	* - start0 + 8:
	900	- Y'\ :sub:`20`
	901	- Y'\ :sub:`21`
	902	- Y'\ :sub:`22`
	903	- Y'\ :sub:`23`
	904	* - start0 + 12:
	905	- Y'\ :sub:`30`
	906	- Y'\ :sub:`31`
	907	- Y'\ :sub:`32`
	908	- Y'\ :sub:`33`
	909	* -
	910	* - start1 + 0:
	911	- Cb\ :sub:`00`
	912	- Cb\ :sub:`01`
	913	- Cb\ :sub:`02`
	914	- Cb\ :sub:`03`
	915	* - start1 + 4:
	916	- Cb\ :sub:`10`
	917	- Cb\ :sub:`11`
	918	- Cb\ :sub:`12`
	919	- Cb\ :sub:`13`
	920	* - start1 + 8:
	921	- Cb\ :sub:`20`
	922	- Cb\ :sub:`21`
	923	- Cb\ :sub:`22`
	924	- Cb\ :sub:`23`
	925	* - start1 + 12:
	926	- Cb\ :sub:`20`
	927	- Cb\ :sub:`21`
	928	- Cb\ :sub:`32`
	929	- Cb\ :sub:`33`
	930	* -
	931	* - start2 + 0:
	932	- Cr\ :sub:`00`
	933	- Cr\ :sub:`01`
	934	- Cr\ :sub:`02`
	935	- Cr\ :sub:`03`
	936	* - start2 + 4:
	937	- Cr\ :sub:`10`
	938	- Cr\ :sub:`11`
	939	- Cr\ :sub:`12`
	940	- Cr\ :sub:`13`
	941	* - start2 + 8:
	942	- Cr\ :sub:`20`
	943	- Cr\ :sub:`21`
	944	- Cr\ :sub:`22`
	945	- Cr\ :sub:`23`
	946	* - start2 + 12:
	947	- Cr\ :sub:`30`
	948	- Cr\ :sub:`31`
	949	- Cr\ :sub:`32`
	950	- Cr\ :sub:`33`

Documentation/userspace-api/media/v4l/pixfmt-yuv410.rst+0−127

@@ -1,127 +0,0 @@
1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
2
3	.. _V4L2-PIX-FMT-YVU410:
4	.. _v4l2-pix-fmt-yuv410:
5
6	**********************************************************
7	V4L2_PIX_FMT_YVU410 ('YVU9'), V4L2_PIX_FMT_YUV410 ('YUV9')
8	**********************************************************
9
10
11	V4L2_PIX_FMT_YUV410
12	Planar formats with ¼ horizontal and vertical chroma resolution, also
13	known as YUV 4:1:0
14
15
16	Description
17	===========
18
19	These are planar formats, as opposed to a packed format. The three
20	components are separated into three sub-images or planes. The Y plane is
21	first. The Y plane has one byte per pixel. For ``V4L2_PIX_FMT_YVU410``,
22	the Cr plane immediately follows the Y plane in memory. The Cr plane is
23	¼ the width and ¼ the height of the Y plane (and of the image). Each Cr
24	belongs to 16 pixels, a four-by-four square of the image. Following the
25	Cr plane is the Cb plane, just like the Cr plane.
26	``V4L2_PIX_FMT_YUV410`` is the same, except the Cb plane comes first,
27	then the Cr plane.
28
29	If the Y plane has pad bytes after each row, then the Cr and Cb planes
30	have ¼ as many pad bytes after their rows. In other words, four Cx rows
31	(including padding) are exactly as long as one Y row (including
32	padding).
33
34	Byte Order.
35	Each cell is one byte.
36
37
38
39
40	.. flat-table::
41	:header-rows: 0
42	:stub-columns: 0
43
44	* - start + 0:
45	- Y'\ :sub:`00`
46	- Y'\ :sub:`01`
47	- Y'\ :sub:`02`
48	- Y'\ :sub:`03`
49	* - start + 4:
50	- Y'\ :sub:`10`
51	- Y'\ :sub:`11`
52	- Y'\ :sub:`12`
53	- Y'\ :sub:`13`
54	* - start + 8:
55	- Y'\ :sub:`20`
56	- Y'\ :sub:`21`
57	- Y'\ :sub:`22`
58	- Y'\ :sub:`23`
59	* - start + 12:
60	- Y'\ :sub:`30`
61	- Y'\ :sub:`31`
62	- Y'\ :sub:`32`
63	- Y'\ :sub:`33`
64	* - start + 16:
65	- Cr\ :sub:`00`
66	* - start + 17:
67	- Cb\ :sub:`00`
68
69
70	Color Sample Location:
71
72
73
74	.. flat-table::
75	:header-rows: 0
76	:stub-columns: 0
77
78	* -
79	- 0
80	-
81	- 1
82	-
83	- 2
84	-
85	- 3
86	* - 0
87	- Y
88	-
89	- Y
90	-
91	- Y
92	-
93	- Y
94	* -
95	* - 1
96	- Y
97	-
98	- Y
99	-
100	- Y
101	-
102	- Y
103	* -
104	-
105	-
106	-
107	- C
108	-
109	-
110	-
111	* - 2
112	- Y
113	-
114	- Y
115	-
116	- Y
117	-
118	- Y
119	* -
120	* - 3
121	- Y
122	-
123	- Y
124	-
125	- Y
126	-
127	- Y

Documentation/userspace-api/media/v4l/pixfmt-yuv411p.rst+0−115

@@ -1,115 +0,0 @@
1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
2
3	.. _V4L2-PIX-FMT-YUV411P:
4
5	*****************************
6	V4L2_PIX_FMT_YUV411P ('411P')
7	*****************************
8
9
10	Format with ¼ horizontal chroma resolution, also known as YUV 4:1:1.
11	Planar layout as opposed to ``V4L2_PIX_FMT_Y41P``
12
13
14	Description
15	===========
16
17	This format is not commonly used. This is a planar format similar to the
18	4:2:2 planar format except with half as many chroma. The three
19	components are separated into three sub-images or planes. The Y plane is
20	first. The Y plane has one byte per pixel. The Cb plane immediately
21	follows the Y plane in memory. The Cb plane is ¼ the width of the Y
22	plane (and of the image). Each Cb belongs to 4 pixels all on the same
23	row. For example, Cb\ :sub:`0` belongs to Y'\ :sub:`00`, Y'\ :sub:`01`,
24	Y'\ :sub:`02` and Y'\ :sub:`03`. Following the Cb plane is the Cr plane,
25	just like the Cb plane.
26
27	If the Y plane has pad bytes after each row, then the Cr and Cb planes
28	have ¼ as many pad bytes after their rows. In other words, four C x rows
29	(including padding) is exactly as long as one Y row (including padding).
30
31	Byte Order.
32	Each cell is one byte.
33
34
35
36	.. flat-table::
37	:header-rows: 0
38	:stub-columns: 0
39
40	* - start + 0:
41	- Y'\ :sub:`00`
42	- Y'\ :sub:`01`
43	- Y'\ :sub:`02`
44	- Y'\ :sub:`03`
45	* - start + 4:
46	- Y'\ :sub:`10`
47	- Y'\ :sub:`11`
48	- Y'\ :sub:`12`
49	- Y'\ :sub:`13`
50	* - start + 8:
51	- Y'\ :sub:`20`
52	- Y'\ :sub:`21`
53	- Y'\ :sub:`22`
54	- Y'\ :sub:`23`
55	* - start + 12:
56	- Y'\ :sub:`30`
57	- Y'\ :sub:`31`
58	- Y'\ :sub:`32`
59	- Y'\ :sub:`33`
60	* - start + 16:
61	- Cb\ :sub:`00`
62	* - start + 17:
63	- Cb\ :sub:`10`
64	* - start + 18:
65	- Cb\ :sub:`20`
66	* - start + 19:
67	- Cb\ :sub:`30`
68	* - start + 20:
69	- Cr\ :sub:`00`
70	* - start + 21:
71	- Cr\ :sub:`10`
72	* - start + 22:
73	- Cr\ :sub:`20`
74	* - start + 23:
75	- Cr\ :sub:`30`
76
77
78	Color Sample Location:
79
80
81
82	.. flat-table::
83	:header-rows: 0
84	:stub-columns: 0
85
86	* -
87	- 0
88	- 1
89	-
90	- 2
91	- 3
92	* - 0
93	- Y
94	- Y
95	- C
96	- Y
97	- Y
98	* - 1
99	- Y
100	- Y
101	- C
102	- Y
103	- Y
104	* - 2
105	- Y
106	- Y
107	- C
108	- Y
109	- Y
110	* - 3
111	- Y
112	- Y
113	- C
114	- Y
115	- Y

Documentation/userspace-api/media/v4l/pixfmt-yuv420.rst+0−143

@@ -1,143 +0,0 @@
1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
2
3	.. _V4L2-PIX-FMT-YVU420:
4	.. _V4L2-PIX-FMT-YUV420:
5
6	**********************************************************
7	V4L2_PIX_FMT_YVU420 ('YV12'), V4L2_PIX_FMT_YUV420 ('YU12')
8	**********************************************************
9
10
11	V4L2_PIX_FMT_YUV420
12	Planar formats with ½ horizontal and vertical chroma resolution, also
13	known as YUV 4:2:0
14
15
16	Description
17	===========
18
19	These are planar formats, as opposed to a packed format. The three
20	components are separated into three sub- images or planes. The Y plane
21	is first. The Y plane has one byte per pixel. For
22	``V4L2_PIX_FMT_YVU420``, the Cr plane immediately follows the Y plane in
23	memory. The Cr plane is half the width and half the height of the Y
24	plane (and of the image). Each Cr belongs to four pixels, a two-by-two
25	square of the image. For example, Cr\ :sub:`0` belongs to Y'\ :sub:`00`,
26	Y'\ :sub:`01`, Y'\ :sub:`10`, and Y'\ :sub:`11`. Following the Cr plane
27	is the Cb plane, just like the Cr plane. ``V4L2_PIX_FMT_YUV420`` is the
28	same except the Cb plane comes first, then the Cr plane.
29
30	If the Y plane has pad bytes after each row, then the Cr and Cb planes
31	have half as many pad bytes after their rows. In other words, two Cx
32	rows (including padding) is exactly as long as one Y row (including
33	padding).
34
35	Byte Order.
36	Each cell is one byte.
37
38
39
40
41	.. flat-table::
42	:header-rows: 0
43	:stub-columns: 0
44
45	* - start + 0:
46	- Y'\ :sub:`00`
47	- Y'\ :sub:`01`
48	- Y'\ :sub:`02`
49	- Y'\ :sub:`03`
50	* - start + 4:
51	- Y'\ :sub:`10`
52	- Y'\ :sub:`11`
53	- Y'\ :sub:`12`
54	- Y'\ :sub:`13`
55	* - start + 8:
56	- Y'\ :sub:`20`
57	- Y'\ :sub:`21`
58	- Y'\ :sub:`22`
59	- Y'\ :sub:`23`
60	* - start + 12:
61	- Y'\ :sub:`30`
62	- Y'\ :sub:`31`
63	- Y'\ :sub:`32`
64	- Y'\ :sub:`33`
65	* - start + 16:
66	- Cr\ :sub:`00`
67	- Cr\ :sub:`01`
68	* - start + 18:
69	- Cr\ :sub:`10`
70	- Cr\ :sub:`11`
71	* - start + 20:
72	- Cb\ :sub:`00`
73	- Cb\ :sub:`01`
74	* - start + 22:
75	- Cb\ :sub:`10`
76	- Cb\ :sub:`11`
77
78
79	Color Sample Location:
80
81
82
83	.. flat-table::
84	:header-rows: 0
85	:stub-columns: 0
86
87	* -
88	- 0
89	-
90	- 1
91	-
92	- 2
93	-
94	- 3
95	* - 0
96	- Y
97	-
98	- Y
99	-
100	- Y
101	-
102	- Y
103	* -
104	-
105	- C
106	-
107	-
108	-
109	- C
110	-
111	* - 1
112	- Y
113	-
114	- Y
115	-
116	- Y
117	-
118	- Y
119	* -
120	* - 2
121	- Y
122	-
123	- Y
124	-
125	- Y
126	-
127	- Y
128	* -
129	-
130	- C
131	-
132	-
133	-
134	- C
135	-
136	* - 3
137	- Y
138	-
139	- Y
140	-
141	- Y
142	-
143	- Y

Documentation/userspace-api/media/v4l/pixfmt-yuv420m.rst+0−152

@@ -1,152 +0,0 @@
1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
2
3	.. _V4L2-PIX-FMT-YUV420M:
4	.. _v4l2-pix-fmt-yvu420m:
5
6	************************************************************
7	V4L2_PIX_FMT_YUV420M ('YM12'), V4L2_PIX_FMT_YVU420M ('YM21')
8	************************************************************
9
10
11	V4L2_PIX_FMT_YVU420M
12	Variation of ``V4L2_PIX_FMT_YUV420`` and ``V4L2_PIX_FMT_YVU420`` with
13	planes non contiguous in memory.
14
15
16	Description
17	===========
18
19	This is a multi-planar format, as opposed to a packed format. The three
20	components are separated into three sub-images or planes.
21
22	The Y plane is first. The Y plane has one byte per pixel. For
23	``V4L2_PIX_FMT_YUV420M`` the Cb data constitutes the second plane which
24	is half the width and half the height of the Y plane (and of the image).
25	Each Cb belongs to four pixels, a two-by-two square of the image. For
26	example, Cb\ :sub:`0` belongs to Y'\ :sub:`00`, Y'\ :sub:`01`,
27	Y'\ :sub:`10`, and Y'\ :sub:`11`. The Cr data, just like the Cb plane,
28	is in the third plane.
29
30	``V4L2_PIX_FMT_YVU420M`` is the same except the Cr data is stored in the
31	second plane and the Cb data in the third plane.
32
33	If the Y plane has pad bytes after each row, then the Cb and Cr planes
34	have half as many pad bytes after their rows. In other words, two Cx
35	rows (including padding) is exactly as long as one Y row (including
36	padding).
37
38	``V4L2_PIX_FMT_YUV420M`` and ``V4L2_PIX_FMT_YVU420M`` are intended to be
39	used only in drivers and applications that support the multi-planar API,
40	described in :ref:`planar-apis`.
41
42	Byte Order.
43	Each cell is one byte.
44
45
46
47
48	.. flat-table::
49	:header-rows: 0
50	:stub-columns: 0
51
52	* - start0 + 0:
53	- Y'\ :sub:`00`
54	- Y'\ :sub:`01`
55	- Y'\ :sub:`02`
56	- Y'\ :sub:`03`
57	* - start0 + 4:
58	- Y'\ :sub:`10`
59	- Y'\ :sub:`11`
60	- Y'\ :sub:`12`
61	- Y'\ :sub:`13`
62	* - start0 + 8:
63	- Y'\ :sub:`20`
64	- Y'\ :sub:`21`
65	- Y'\ :sub:`22`
66	- Y'\ :sub:`23`
67	* - start0 + 12:
68	- Y'\ :sub:`30`
69	- Y'\ :sub:`31`
70	- Y'\ :sub:`32`
71	- Y'\ :sub:`33`
72	* -
73	* - start1 + 0:
74	- Cb\ :sub:`00`
75	- Cb\ :sub:`01`
76	* - start1 + 2:
77	- Cb\ :sub:`10`
78	- Cb\ :sub:`11`
79	* -
80	* - start2 + 0:
81	- Cr\ :sub:`00`
82	- Cr\ :sub:`01`
83	* - start2 + 2:
84	- Cr\ :sub:`10`
85	- Cr\ :sub:`11`
86
87
88	Color Sample Location:
89
90
91
92	.. flat-table::
93	:header-rows: 0
94	:stub-columns: 0
95
96	* -
97	- 0
98	-
99	- 1
100	-
101	- 2
102	-
103	- 3
104	* - 0
105	- Y
106	-
107	- Y
108	-
109	- Y
110	-
111	- Y
112	* -
113	-
114	- C
115	-
116	-
117	-
118	- C
119	-
120	* - 1
121	- Y
122	-
123	- Y
124	-
125	- Y
126	-
127	- Y
128	* -
129	* - 2
130	- Y
131	-
132	- Y
133	-
134	- Y
135	-
136	- Y
137	* -
138	-
139	- C
140	-
141	-
142	-
143	- C
144	-
145	* - 3
146	- Y
147	-
148	- Y
149	-
150	- Y
151	-
152	- Y

Documentation/userspace-api/media/v4l/pixfmt-yuv422m.rst+0−141

@@ -1,141 +0,0 @@
1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
2
3	.. _V4L2-PIX-FMT-YUV422M:
4	.. _v4l2-pix-fmt-yvu422m:
5
6	************************************************************
7	V4L2_PIX_FMT_YUV422M ('YM16'), V4L2_PIX_FMT_YVU422M ('YM61')
8	************************************************************
9
10
11	V4L2_PIX_FMT_YVU422M
12	Planar formats with ½ horizontal resolution, also known as YUV and YVU
13	4:2:2
14
15
16	Description
17	===========
18
19	This is a multi-planar format, as opposed to a packed format. The three
20	components are separated into three sub-images or planes.
21
22	The Y plane is first. The Y plane has one byte per pixel. For
23	``V4L2_PIX_FMT_YUV422M`` the Cb data constitutes the second plane which
24	is half the width of the Y plane (and of the image). Each Cb belongs to
25	two pixels. For example, Cb\ :sub:`0` belongs to Y'\ :sub:`00`,
26	Y'\ :sub:`01`. The Cr data, just like the Cb plane, is in the third
27	plane.
28
29	``V4L2_PIX_FMT_YVU422M`` is the same except the Cr data is stored in the
30	second plane and the Cb data in the third plane.
31
32	If the Y plane has pad bytes after each row, then the Cb and Cr planes
33	have half as many pad bytes after their rows. In other words, two Cx
34	rows (including padding) is exactly as long as one Y row (including
35	padding).
36
37	``V4L2_PIX_FMT_YUV422M`` and ``V4L2_PIX_FMT_YVU422M`` are intended to be
38	used only in drivers and applications that support the multi-planar API,
39	described in :ref:`planar-apis`.
40
41	Byte Order.
42	Each cell is one byte.
43
44
45
46
47	.. flat-table::
48	:header-rows: 0
49	:stub-columns: 0
50
51	* - start0 + 0:
52	- Y'\ :sub:`00`
53	- Y'\ :sub:`01`
54	- Y'\ :sub:`02`
55	- Y'\ :sub:`03`
56	* - start0 + 4:
57	- Y'\ :sub:`10`
58	- Y'\ :sub:`11`
59	- Y'\ :sub:`12`
60	- Y'\ :sub:`13`
61	* - start0 + 8:
62	- Y'\ :sub:`20`
63	- Y'\ :sub:`21`
64	- Y'\ :sub:`22`
65	- Y'\ :sub:`23`
66	* - start0 + 12:
67	- Y'\ :sub:`30`
68	- Y'\ :sub:`31`
69	- Y'\ :sub:`32`
70	- Y'\ :sub:`33`
71	* -
72	* - start1 + 0:
73	- Cb\ :sub:`00`
74	- Cb\ :sub:`01`
75	* - start1 + 2:
76	- Cb\ :sub:`10`
77	- Cb\ :sub:`11`
78	* - start1 + 4:
79	- Cb\ :sub:`20`
80	- Cb\ :sub:`21`
81	* - start1 + 6:
82	- Cb\ :sub:`30`
83	- Cb\ :sub:`31`
84	* -
85	* - start2 + 0:
86	- Cr\ :sub:`00`
87	- Cr\ :sub:`01`
88	* - start2 + 2:
89	- Cr\ :sub:`10`
90	- Cr\ :sub:`11`
91	* - start2 + 4:
92	- Cr\ :sub:`20`
93	- Cr\ :sub:`21`
94	* - start2 + 6:
95	- Cr\ :sub:`30`
96	- Cr\ :sub:`31`
97
98
99	Color Sample Location:
100
101
102
103	.. flat-table::
104	:header-rows: 0
105	:stub-columns: 0
106
107	* -
108	- 0
109	-
110	- 1
111	- 2
112	-
113	- 3
114	* - 0
115	- Y
116	- C
117	- Y
118	- Y
119	- C
120	- Y
121	* - 1
122	- Y
123	- C
124	- Y
125	- Y
126	- C
127	- Y
128	* - 2
129	- Y
130	- C
131	- Y
132	- Y
133	- C
134	- Y
135	* - 3
136	- Y
137	- C
138	- Y
139	- Y
140	- C
141	- Y

Documentation/userspace-api/media/v4l/pixfmt-yuv422p.rst+0−129

@@ -1,129 +0,0 @@
1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
2
3	.. _V4L2-PIX-FMT-YUV422P:
4
5	*****************************
6	V4L2_PIX_FMT_YUV422P ('422P')
7	*****************************
8
9
10	Format with ½ horizontal chroma resolution, also known as YUV 4:2:2.
11	Planar layout as opposed to ``V4L2_PIX_FMT_YUYV``
12
13
14	Description
15	===========
16
17	This format is not commonly used. This is a planar version of the YUYV
18	format. The three components are separated into three sub-images or
19	planes. The Y plane is first. The Y plane has one byte per pixel. The Cb
20	plane immediately follows the Y plane in memory. The Cb plane is half
21	the width of the Y plane (and of the image). Each Cb belongs to two
22	pixels. For example, Cb\ :sub:`0` belongs to Y'\ :sub:`00`,
23	Y'\ :sub:`01`. Following the Cb plane is the Cr plane, just like the Cb
24	plane.
25
26	If the Y plane has pad bytes after each row, then the Cr and Cb planes
27	have half as many pad bytes after their rows. In other words, two Cx
28	rows (including padding) is exactly as long as one Y row (including
29	padding).
30
31	Byte Order.
32	Each cell is one byte.
33
34
35
36
37	.. flat-table::
38	:header-rows: 0
39	:stub-columns: 0
40
41	* - start + 0:
42	- Y'\ :sub:`00`
43	- Y'\ :sub:`01`
44	- Y'\ :sub:`02`
45	- Y'\ :sub:`03`
46	* - start + 4:
47	- Y'\ :sub:`10`
48	- Y'\ :sub:`11`
49	- Y'\ :sub:`12`
50	- Y'\ :sub:`13`
51	* - start + 8:
52	- Y'\ :sub:`20`
53	- Y'\ :sub:`21`
54	- Y'\ :sub:`22`
55	- Y'\ :sub:`23`
56	* - start + 12:
57	- Y'\ :sub:`30`
58	- Y'\ :sub:`31`
59	- Y'\ :sub:`32`
60	- Y'\ :sub:`33`
61	* - start + 16:
62	- Cb\ :sub:`00`
63	- Cb\ :sub:`01`
64	* - start + 18:
65	- Cb\ :sub:`10`
66	- Cb\ :sub:`11`
67	* - start + 20:
68	- Cb\ :sub:`20`
69	- Cb\ :sub:`21`
70	* - start + 22:
71	- Cb\ :sub:`30`
72	- Cb\ :sub:`31`
73	* - start + 24:
74	- Cr\ :sub:`00`
75	- Cr\ :sub:`01`
76	* - start + 26:
77	- Cr\ :sub:`10`
78	- Cr\ :sub:`11`
79	* - start + 28:
80	- Cr\ :sub:`20`
81	- Cr\ :sub:`21`
82	* - start + 30:
83	- Cr\ :sub:`30`
84	- Cr\ :sub:`31`
85
86
87	Color Sample Location:
88
89
90
91	.. flat-table::
92	:header-rows: 0
93	:stub-columns: 0
94
95	* -
96	- 0
97	-
98	- 1
99	- 2
100	-
101	- 3
102	* - 0
103	- Y
104	- C
105	- Y
106	- Y
107	- C
108	- Y
109	* - 1
110	- Y
111	- C
112	- Y
113	- Y
114	- C
115	- Y
116	* - 2
117	- Y
118	- C
119	- Y
120	- Y
121	- C
122	- Y
123	* - 3
124	- Y
125	- C
126	- Y
127	- Y
128	- C
129	- Y

Documentation/userspace-api/media/v4l/pixfmt-yuv444m.rst+0−141

@@ -1,141 +0,0 @@
1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
2
3	.. _V4L2-PIX-FMT-YUV444M:
4	.. _v4l2-pix-fmt-yvu444m:
5
6	************************************************************
7	V4L2_PIX_FMT_YUV444M ('YM24'), V4L2_PIX_FMT_YVU444M ('YM42')
8	************************************************************
9
10
11	V4L2_PIX_FMT_YVU444M
12	Planar formats with full horizontal resolution, also known as YUV and
13	YVU 4:4:4
14
15
16	Description
17	===========
18
19	This is a multi-planar format, as opposed to a packed format. The three
20	components are separated into three sub-images or planes.
21
22	The Y plane is first. The Y plane has one byte per pixel. For
23	``V4L2_PIX_FMT_YUV444M`` the Cb data constitutes the second plane which
24	is the same width and height as the Y plane (and as the image). The Cr
25	data, just like the Cb plane, is in the third plane.
26
27	``V4L2_PIX_FMT_YVU444M`` is the same except the Cr data is stored in the
28	second plane and the Cb data in the third plane.
29
30	If the Y plane has pad bytes after each row, then the Cb and Cr planes
31	have the same number of pad bytes after their rows.
32
33	``V4L2_PIX_FMT_YUV444M`` and ``V4L2_PIX_FMT_YUV444M`` are intended to be
34	used only in drivers and applications that support the multi-planar API,
35	described in :ref:`planar-apis`.
36
37	Byte Order.
38	Each cell is one byte.
39
40
41	.. flat-table::
42	:header-rows: 0
43	:stub-columns: 0
44
45	* - start0 + 0:
46	- Y'\ :sub:`00`
47	- Y'\ :sub:`01`
48	- Y'\ :sub:`02`
49	- Y'\ :sub:`03`
50	* - start0 + 4:
51	- Y'\ :sub:`10`
52	- Y'\ :sub:`11`
53	- Y'\ :sub:`12`
54	- Y'\ :sub:`13`
55	* - start0 + 8:
56	- Y'\ :sub:`20`
57	- Y'\ :sub:`21`
58	- Y'\ :sub:`22`
59	- Y'\ :sub:`23`
60	* - start0 + 12:
61	- Y'\ :sub:`30`
62	- Y'\ :sub:`31`
63	- Y'\ :sub:`32`
64	- Y'\ :sub:`33`
65	* -
66	* - start1 + 0:
67	- Cb\ :sub:`00`
68	- Cb\ :sub:`01`
69	- Cb\ :sub:`02`
70	- Cb\ :sub:`03`
71	* - start1 + 4:
72	- Cb\ :sub:`10`
73	- Cb\ :sub:`11`
74	- Cb\ :sub:`12`
75	- Cb\ :sub:`13`
76	* - start1 + 8:
77	- Cb\ :sub:`20`
78	- Cb\ :sub:`21`
79	- Cb\ :sub:`22`
80	- Cb\ :sub:`23`
81	* - start1 + 12:
82	- Cb\ :sub:`20`
83	- Cb\ :sub:`21`
84	- Cb\ :sub:`32`
85	- Cb\ :sub:`33`
86	* -
87	* - start2 + 0:
88	- Cr\ :sub:`00`
89	- Cr\ :sub:`01`
90	- Cr\ :sub:`02`
91	- Cr\ :sub:`03`
92	* - start2 + 4:
93	- Cr\ :sub:`10`
94	- Cr\ :sub:`11`
95	- Cr\ :sub:`12`
96	- Cr\ :sub:`13`
97	* - start2 + 8:
98	- Cr\ :sub:`20`
99	- Cr\ :sub:`21`
100	- Cr\ :sub:`22`
101	- Cr\ :sub:`23`
102	* - start2 + 12:
103	- Cr\ :sub:`30`
104	- Cr\ :sub:`31`
105	- Cr\ :sub:`32`
106	- Cr\ :sub:`33`
107
108
109	Color Sample Location:
110
111
112
113	.. flat-table::
114	:header-rows: 0
115	:stub-columns: 0
116
117	* -
118	- 0
119	- 1
120	- 2
121	- 3
122	* - 0
123	- YC
124	- YC
125	- YC
126	- YC
127	* - 1
128	- YC
129	- YC
130	- YC
131	- YC
132	* - 2
133	- YC
134	- YC
135	- YC
136	- YC
137	* - 3
138	- YC
139	- YC
140	- YC
141	- YC

Documentation/userspace-api/media/v4l/pixfmt-yuyv.rst+0−118

@@ -1,118 +0,0 @@
1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
2
3	.. _V4L2-PIX-FMT-YUYV:
4
5	**************************
6	V4L2_PIX_FMT_YUYV ('YUYV')
7	**************************
8
9
10	Packed format with ½ horizontal chroma resolution, also known as YUV
11	4:2:2
12
13
14	Description
15	===========
16
17	In this format each four bytes is two pixels. Each four bytes is two
18	Y's, a Cb and a Cr. Each Y goes to one of the pixels, and the Cb and Cr
19	belong to both pixels. As you can see, the Cr and Cb components have
20	half the horizontal resolution of the Y component. ``V4L2_PIX_FMT_YUYV``
21	is known in the Windows environment as YUY2.
22
23	Byte Order.
24	Each cell is one byte.
25
26
27
28
29	.. flat-table::
30	:header-rows: 0
31	:stub-columns: 0
32
33	* - start + 0:
34	- Y'\ :sub:`00`
35	- Cb\ :sub:`00`
36	- Y'\ :sub:`01`
37	- Cr\ :sub:`00`
38	- Y'\ :sub:`02`
39	- Cb\ :sub:`01`
40	- Y'\ :sub:`03`
41	- Cr\ :sub:`01`
42	* - start + 8:
43	- Y'\ :sub:`10`
44	- Cb\ :sub:`10`
45	- Y'\ :sub:`11`
46	- Cr\ :sub:`10`
47	- Y'\ :sub:`12`
48	- Cb\ :sub:`11`
49	- Y'\ :sub:`13`
50	- Cr\ :sub:`11`
51	* - start + 16:
52	- Y'\ :sub:`20`
53	- Cb\ :sub:`20`
54	- Y'\ :sub:`21`
55	- Cr\ :sub:`20`
56	- Y'\ :sub:`22`
57	- Cb\ :sub:`21`
58	- Y'\ :sub:`23`
59	- Cr\ :sub:`21`
60	* - start + 24:
61	- Y'\ :sub:`30`
62	- Cb\ :sub:`30`
63	- Y'\ :sub:`31`
64	- Cr\ :sub:`30`
65	- Y'\ :sub:`32`
66	- Cb\ :sub:`31`
67	- Y'\ :sub:`33`
68	- Cr\ :sub:`31`
69
70
71	Color Sample Location:
72
73
74
75	.. flat-table::
76	:header-rows: 0
77	:stub-columns: 0
78
79	* -
80	- 0
81	-
82	- 1
83	-
84	- 2
85	-
86	- 3
87	* - 0
88	- Y
89	- C
90	- Y
91	-
92	- Y
93	- C
94	- Y
95	* - 1
96	- Y
97	- C
98	- Y
99	-
100	- Y
101	- C
102	- Y
103	* - 2
104	- Y
105	- C
106	- Y
107	-
108	- Y
109	- C
110	- Y
111	* - 3
112	- Y
113	- C
114	- Y
115	-
116	- Y
117	- C
118	- Y

Documentation/userspace-api/media/v4l/pixfmt-yvyu.rst+0−108

@@ -1,108 +0,0 @@
1	.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
2
3	.. _V4L2-PIX-FMT-YVYU:
4
5	**************************
6	V4L2_PIX_FMT_YVYU ('YVYU')
7	**************************
8
9
10	Variation of ``V4L2_PIX_FMT_YUYV`` with different order of samples in
11	memory
12
13
14	Description
15	===========
16
17	In this format each four bytes is two pixels. Each four bytes is two
18	Y's, a Cb and a Cr. Each Y goes to one of the pixels, and the Cb and Cr
19	belong to both pixels. As you can see, the Cr and Cb components have
20	half the horizontal resolution of the Y component.
21
22	Byte Order.
23	Each cell is one byte.
24
25
26	.. flat-table::
27	:header-rows: 0
28	:stub-columns: 0
29
30	* - start + 0:
31	- Y'\ :sub:`00`
32	- Cr\ :sub:`00`
33	- Y'\ :sub:`01`
34	- Cb\ :sub:`00`
35	- Y'\ :sub:`02`
36	- Cr\ :sub:`01`
37	- Y'\ :sub:`03`
38	- Cb\ :sub:`01`
39	* - start + 8:
40	- Y'\ :sub:`10`
41	- Cr\ :sub:`10`
42	- Y'\ :sub:`11`
43	- Cb\ :sub:`10`
44	- Y'\ :sub:`12`
45	- Cr\ :sub:`11`
46	- Y'\ :sub:`13`
47	- Cb\ :sub:`11`
48	* - start + 16:
49	- Y'\ :sub:`20`
50	- Cr\ :sub:`20`
51	- Y'\ :sub:`21`
52	- Cb\ :sub:`20`
53	- Y'\ :sub:`22`
54	- Cr\ :sub:`21`
55	- Y'\ :sub:`23`
56	- Cb\ :sub:`21`
57	* - start + 24:
58	- Y'\ :sub:`30`
59	- Cr\ :sub:`30`
60	- Y'\ :sub:`31`
61	- Cb\ :sub:`30`
62	- Y'\ :sub:`32`
63	- Cr\ :sub:`31`
64	- Y'\ :sub:`33`
65	- Cb\ :sub:`31`
66
67
68	Color Sample Location:
69
70	.. flat-table::
71	:header-rows: 0
72	:stub-columns: 0
73
74	* -
75	- 0
76	-
77	- 1
78	- 2
79	-
80	- 3
81	* - 0
82	- Y
83	- C
84	- Y
85	- Y
86	- C
87	- Y
88	* - 1
89	- Y
90	- C
91	- Y
92	- Y
93	- C
94	- Y
95	* - 2
96	- Y
97	- C
98	- Y
99	- Y
100	- C
101	- Y
102	* - 3
103	- Y
104	- C
105	- Y
106	- Y
107	- C
108	- Y

Documentation/userspace-api/media/v4l/selection-api-configuration.rst+1−1

@@ -94,7 +94,7 @@ specified using :ref:`VIDIOC_S_FMT <VIDIOC_G_FMT>` ioctl. · 93 unmodified lines
94		94
95	The top left corner, width and height of the source rectangle, that is	95	The top left corner, width and height of the source rectangle, that is
96	the area from which image date are processed by the hardware, is given	96	the area from which image date are processed by the hardware, is given
97	by the ``V4L2_SEL_TGT_CROP``. Its coordinates are expressed in in the	97	by the ``V4L2_SEL_TGT_CROP``. Its coordinates are expressed in the
98	same coordinate system as the bounds rectangle. The active cropping area	98	same coordinate system as the bounds rectangle. The active cropping area
99	must lie completely inside the crop boundaries and the driver may	99	must lie completely inside the crop boundaries and the driver may
100	further adjust the requested size and/or position according to hardware	100	further adjust the requested size and/or position according to hardware

Documentation/userspace-api/media/v4l/subdev-formats.rst+27−0

@@ -7899,3 +7899,30 @@ formats. · 7898 unmodified lines
7899	- 0x5001	7899	- 0x5001
7900	- Interleaved raw UYVY and JPEG image format with embedded meta-data	7900	- Interleaved raw UYVY and JPEG image format with embedded meta-data
7901	used by Samsung S3C73MX camera sensors.	7901	used by Samsung S3C73MX camera sensors.
		7902
		7903	.. _v4l2-mbus-metadata-fmts:
		7904
		7905	Metadata Formats
		7906	^^^^^^^^^^^^^^^^
		7907
		7908	This section lists all metadata formats.
		7909
		7910	The following table lists the existing metadata formats.
		7911
		7912	.. tabularcolumns:: \|p{8.0cm}\|p{1.4cm}\|p{7.7cm}\|
		7913
		7914	.. flat-table:: Metadata formats
		7915	:header-rows: 1
		7916	:stub-columns: 0
		7917
		7918	* - Identifier
		7919	- Code
		7920	- Comments
		7921	* .. _MEDIA-BUS-FMT-METADATA-FIXED:
		7922
		7923	- MEDIA_BUS_FMT_METADATA_FIXED
		7924	- 0x7001
		7925	- This format should be used when the same driver handles
		7926	both sides of the link and the bus format is a fixed
		7927	metadata format that is not configurable from userspace.
		7928	Width and height will be set to 0 for this format.

Documentation/userspace-api/media/v4l/vidioc-g-ext-ctrls.rst+41−5

@@ -53,7 +53,7 @@ by the ``controls`` fields. · 52 unmodified lines
53	To get the current value of a set of controls applications initialize	53	To get the current value of a set of controls applications initialize
54	the ``id``, ``size`` and ``reserved2`` fields of each struct	54	the ``id``, ``size`` and ``reserved2`` fields of each struct
55	:c:type:`v4l2_ext_control` and call the	55	:c:type:`v4l2_ext_control` and call the
56	:ref:`VIDIOC_G_EXT_CTRLS <VIDIOC_G_EXT_CTRLS>` ioctl. String controls controls must also set the	56	:ref:`VIDIOC_G_EXT_CTRLS <VIDIOC_G_EXT_CTRLS>` ioctl. String controls must also set the
57	``string`` field. Controls of compound types	57	``string`` field. Controls of compound types
58	(``V4L2_CTRL_FLAG_HAS_PAYLOAD`` is set) must set the ``ptr`` field.	58	(``V4L2_CTRL_FLAG_HAS_PAYLOAD`` is set) must set the ``ptr`` field.
59		59
@@ -180,10 +180,38 @@ still cause this situation. · 120 unmodified lines
180	- ``p_u32``	180	- ``p_u32``
181	- A pointer to a matrix control of unsigned 32-bit values. Valid if	181	- A pointer to a matrix control of unsigned 32-bit values. Valid if
182	this control is of type ``V4L2_CTRL_TYPE_U32``.	182	this control is of type ``V4L2_CTRL_TYPE_U32``.
183	* - :c:type:`v4l2_area` *	183	* - struct :c:type:`v4l2_area` *
184	- ``p_area``	184	- ``p_area``
185	- A pointer to a struct :c:type:`v4l2_area`. Valid if this control is	185	- A pointer to a struct :c:type:`v4l2_area`. Valid if this control is
186	of type ``V4L2_CTRL_TYPE_AREA``.	186	of type ``V4L2_CTRL_TYPE_AREA``.
		187	* - struct :c:type:`v4l2_ctrl_h264_sps` *
		188	- ``p_h264_sps``
		189	- A pointer to a struct :c:type:`v4l2_ctrl_h264_sps`. Valid if this control is
		190	of type ``V4L2_CTRL_TYPE_H264_SPS``.
		191	* - struct :c:type:`v4l2_ctrl_h264_pps` *
		192	- ``p_h264_pps``
		193	- A pointer to a struct :c:type:`v4l2_ctrl_h264_pps`. Valid if this control is
		194	of type ``V4L2_CTRL_TYPE_H264_PPS``.
		195	* - struct :c:type:`v4l2_ctrl_h264_scaling_matrix` *
		196	- ``p_h264_scaling_matrix``
		197	- A pointer to a struct :c:type:`v4l2_ctrl_h264_scaling_matrix`. Valid if this control is
		198	of type ``V4L2_CTRL_TYPE_H264_SCALING_MATRIX``.
		199	* - struct :c:type:`v4l2_ctrl_h264_pred_weights` *
		200	- ``p_h264_pred_weights``
		201	- A pointer to a struct :c:type:`v4l2_ctrl_h264_pred_weights`. Valid if this control is
		202	of type ``V4L2_CTRL_TYPE_H264_PRED_WEIGHTS``.
		203	* - struct :c:type:`v4l2_ctrl_h264_slice_params` *
		204	- ``p_h264_slice_params``
		205	- A pointer to a struct :c:type:`v4l2_ctrl_h264_slice_params`. Valid if this control is
		206	of type ``V4L2_CTRL_TYPE_H264_SLICE_PARAMS``.
		207	* - struct :c:type:`v4l2_ctrl_h264_decode_params` *
		208	- ``p_h264_decode_params``
		209	- A pointer to a struct :c:type:`v4l2_ctrl_h264_decode_params`. Valid if this control is
		210	of type ``V4L2_CTRL_TYPE_H264_DECODE_PARAMS``.
		211	* - struct :c:type:`v4l2_ctrl_fwht_params` *
		212	- ``p_fwht_params``
		213	- A pointer to a struct :c:type:`v4l2_ctrl_fwht_params`. Valid if this control is
		214	of type ``V4L2_CTRL_TYPE_FWHT_PARAMS``.
187	* - void *	215	* - void *
188	- ``ptr``	216	- ``ptr``
189	- A pointer to a compound type which can be an N-dimensional array	217	- A pointer to a compound type which can be an N-dimensional array
@@ -322,10 +350,10 @@ still cause this situation. · 132 unmodified lines
322	:ref:`VIDIOC_S_CTRL <VIDIOC_G_CTRL>` and	350	:ref:`VIDIOC_S_CTRL <VIDIOC_G_CTRL>` and
323	:ref:`VIDIOC_G_CTRL <VIDIOC_G_CTRL>` ioctl belong to this	351	:ref:`VIDIOC_G_CTRL <VIDIOC_G_CTRL>` ioctl belong to this
324	class.	352	class.
325	* - ``V4L2_CTRL_CLASS_MPEG``	353	* - ``V4L2_CTRL_CLASS_CODEC``
326	- 0x990000	354	- 0x990000
327	- The class containing MPEG compression controls. These controls are	355	- The class containing stateful codec controls. These controls are
328	described in :ref:`mpeg-controls`.	356	described in :ref:`codec-controls`.
329	* - ``V4L2_CTRL_CLASS_CAMERA``	357	* - ``V4L2_CTRL_CLASS_CAMERA``
330	- 0x9a0000	358	- 0x9a0000
331	- The class containing camera controls. These controls are described	359	- The class containing camera controls. These controls are described
@@ -358,6 +386,14 @@ still cause this situation. · 26 unmodified lines
358	- 0xa20000	386	- 0xa20000
359	- The class containing RF tuner controls. These controls are	387	- The class containing RF tuner controls. These controls are
360	described in :ref:`rf-tuner-controls`.	388	described in :ref:`rf-tuner-controls`.
		389	* - ``V4L2_CTRL_CLASS_DETECT``
		390	- 0xa30000
		391	- The class containing motion or object detection controls. These controls
		392	are described in :ref:`detect-controls`.
		393	* - ``V4L2_CTRL_CLASS_CODEC_STATELESS``
		394	- 0xa40000
		395	- The class containing stateless codec controls. These controls are
		396	described in :ref:`codec-stateless-controls`.
361		397
362	Return Value	398	Return Value
363	============	399	============

Documentation/userspace-api/media/v4l/vidioc-g-output.rst+1−1

@@ -46,7 +46,7 @@ To select a video output applications store the number of the desired · 45 unmodified lines
46	output in an integer and call the :ref:`VIDIOC_S_OUTPUT <VIDIOC_G_OUTPUT>` ioctl with a	46	output in an integer and call the :ref:`VIDIOC_S_OUTPUT <VIDIOC_G_OUTPUT>` ioctl with a
47	pointer to this integer. Side effects are possible. For example outputs	47	pointer to this integer. Side effects are possible. For example outputs
48	may support different video standards, so the driver may implicitly	48	may support different video standards, so the driver may implicitly
49	switch the current standard. standard. Because of these possible side	49	switch the current standard. Because of these possible side
50	effects applications must select an output before querying or	50	effects applications must select an output before querying or
51	negotiating any other parameters.	51	negotiating any other parameters.
52		52

Documentation/userspace-api/media/v4l/vidioc-qbuf.rst+1−1

@@ -163,7 +163,7 @@ EINVAL · 162 unmodified lines
163	The buffer ``type`` is not supported, or the ``index`` is out of	163	The buffer ``type`` is not supported, or the ``index`` is out of
164	bounds, or no buffers have been allocated yet, or the ``userptr`` or	164	bounds, or no buffers have been allocated yet, or the ``userptr`` or
165	``length`` are invalid, or the ``V4L2_BUF_FLAG_REQUEST_FD`` flag was	165	``length`` are invalid, or the ``V4L2_BUF_FLAG_REQUEST_FD`` flag was
166	set but the the given ``request_fd`` was invalid, or ``m.fd`` was	166	set but the given ``request_fd`` was invalid, or ``m.fd`` was
167	an invalid DMABUF file descriptor.	167	an invalid DMABUF file descriptor.
168		168
169	EIO	169	EIO

Documentation/userspace-api/media/v4l/vidioc-queryctrl.rst+6−0

       - n/a
       - A struct :c:type:`v4l2_ctrl_h264_decode_params`, containing H264
 	decode parameters for stateless video decoders.
+    * - ``V4L2_CTRL_TYPE_FWHT_PARAMS``
+      - n/a
+      - n/a
+      - n/a
+      - A struct :c:type:`v4l2_ctrl_fwht_params`, containing FWHT
+	parameters for stateless video decoders.
     * - ``V4L2_CTRL_TYPE_HEVC_SPS``
       - n/a
       - n/a

Documentation/userspace-api/media/v4l/yuv-formats.rst+247−31

@@ -14,44 +14,260 @@ reconstructed by subtracting from the brightness component. See · 13 unmodified lines
14	:ref:`colorspaces` for conversion examples. YUV was chosen because	14	:ref:`colorspaces` for conversion examples. YUV was chosen because
15	early television would only transmit brightness information. To add	15	early television would only transmit brightness information. To add
16	color in a way compatible with existing receivers a new signal carrier	16	color in a way compatible with existing receivers a new signal carrier
17	was added to transmit the color difference signals. Secondary in the YUV	17	was added to transmit the color difference signals.
18	format the U and V components usually have lower resolution than the Y	18
19	component. This is an analog video compression technique taking	19
20	advantage of a property of the human visual system, being more sensitive	20	Subsampling
21	to brightness information.	21	===========
		22
		23	YUV formats commonly encode images with a lower resolution for the chroma
		24	components than for the luma component. This compression technique, taking
		25	advantage of the human eye being more sensitive to luminance than color
		26	differences, is called chroma subsampling.
		27
		28	While many combinations of subsampling factors in the horizontal and vertical
		29	direction are possible, common factors are 1 (no subsampling), 2 and 4, with
		30	horizontal subsampling always larger than or equal to vertical subsampling.
		31	Common combinations are named as follows.
		32
		33	- `4:4:4`: No subsampling
		34	- `4:2:2`: Horizontal subsampling by 2, no vertical subsampling
		35	- `4:2:0`: Horizontal subsampling by 2, vertical subsampling by 2
		36	- `4:1:1`: Horizontal subsampling by 4, no vertical subsampling
		37	- `4:1:0`: Horizontal subsampling by 4, vertical subsampling by 4
		38
		39	Subsampling the chroma component effectively creates chroma values that can be
		40	located in different spatial locations:
		41
		42	- .. _yuv-chroma-centered:
		43
		44	The subsampled chroma value may be calculated by simply averaging the chroma
		45	value of two consecutive pixels. It effectively models the chroma of a pixel
		46	sited between the two original pixels. This is referred to as centered or
		47	interstitially sited chroma.
		48
		49	- .. _yuv-chroma-cosited:
		50
		51	The other option is to subsample chroma values in a way that place them in
		52	the same spatial sites as the pixels. This may be performed by skipping every
		53	other chroma sample (creating aliasing artifacts), or with filters using an
		54	odd number of taps. This is referred to as co-sited chroma.
		55
		56	The following examples show different combination of chroma siting in a 4x4
		57	image.
		58
		59	.. flat-table:: 4:2:2 subsampling, interstitially sited
		60	:header-rows: 1
		61	:stub-columns: 1
		62
		63	* -
		64	- 0
		65	-
		66	- 1
		67	-
		68	- 2
		69	-
		70	- 3
		71	* - 0
		72	- Y
		73	- C
		74	- Y
		75	-
		76	- Y
		77	- C
		78	- Y
		79	* - 1
		80	- Y
		81	- C
		82	- Y
		83	-
		84	- Y
		85	- C
		86	- Y
		87	* - 2
		88	- Y
		89	- C
		90	- Y
		91	-
		92	- Y
		93	- C
		94	- Y
		95	* - 3
		96	- Y
		97	- C
		98	- Y
		99	-
		100	- Y
		101	- C
		102	- Y
		103
		104	.. flat-table:: 4:2:2 subsampling, co-sited
		105	:header-rows: 1
		106	:stub-columns: 1
		107
		108	* -
		109	- 0
		110	-
		111	- 1
		112	-
		113	- 2
		114	-
		115	- 3
		116	* - 0
		117	- Y/C
		118	-
		119	- Y
		120	-
		121	- Y/C
		122	-
		123	- Y
		124	* - 1
		125	- Y/C
		126	-
		127	- Y
		128	-
		129	- Y/C
		130	-
		131	- Y
		132	* - 2
		133	- Y/C
		134	-
		135	- Y
		136	-
		137	- Y/C
		138	-
		139	- Y
		140	* - 3
		141	- Y/C
		142	-
		143	- Y
		144	-
		145	- Y/C
		146	-
		147	- Y
		148
		149	.. flat-table:: 4:2:0 subsampling, horizontally interstitially sited, vertically co-sited
		150	:header-rows: 1
		151	:stub-columns: 1
		152
		153	* -
		154	- 0
		155	-
		156	- 1
		157	-
		158	- 2
		159	-
		160	- 3
		161	* - 0
		162	- Y
		163	- C
		164	- Y
		165	-
		166	- Y
		167	- C
		168	- Y
		169	* - 1
		170	- Y
		171	-
		172	- Y
		173	-
		174	- Y
		175	-
		176	- Y
		177	* - 2
		178	- Y
		179	- C
		180	- Y
		181	-
		182	- Y
		183	- C
		184	- Y
		185	* - 3
		186	- Y
		187	-
		188	- Y
		189	-
		190	- Y
		191	-
		192	- Y
		193
		194	.. flat-table:: 4:1:0 subsampling, horizontally and vertically interstitially sited
		195	:header-rows: 1
		196	:stub-columns: 1
		197
		198	* -
		199	- 0
		200	-
		201	- 1
		202	-
		203	- 2
		204	-
		205	- 3
		206	* - 0
		207	- Y
		208	-
		209	- Y
		210	-
		211	- Y
		212	-
		213	- Y
		214	* -
		215	-
		216	-
		217	-
		218	-
		219	-
		220	-
		221	-
		222	* - 1
		223	- Y
		224	-
		225	- Y
		226	-
		227	- Y
		228	-
		229	- Y
		230	* -
		231	-
		232	-
		233	-
		234	- C
		235	-
		236	-
		237	-
		238	* - 2
		239	- Y
		240	-
		241	- Y
		242	-
		243	- Y
		244	-
		245	- Y
		246	* -
		247	-
		248	-
		249	-
		250	-
		251	-
		252	-
		253	-
		254	* - 3
		255	- Y
		256	-
		257	- Y
		258	-
		259	- Y
		260	-
		261	- Y
22		262
23		263
24	.. toctree::	264	.. toctree::
25	:maxdepth: 1	265	:maxdepth: 1
26		266
27	pixfmt-packed-yuv	267	pixfmt-packed-yuv
28	pixfmt-grey	268	pixfmt-yuv-planar
29	pixfmt-y10	269	pixfmt-yuv-luma
30	pixfmt-y12
31	pixfmt-y14
32	pixfmt-y10b
33	pixfmt-y10p
34	pixfmt-y16
35	pixfmt-y16-be
36	pixfmt-y8i	270	pixfmt-y8i
37	pixfmt-y12i	271	pixfmt-y12i
38	pixfmt-uv8	272	pixfmt-uv8
39	pixfmt-yuyv
40	pixfmt-uyvy
41	pixfmt-yvyu
42	pixfmt-vyuy
43	pixfmt-y41p
44	pixfmt-yuv420
45	pixfmt-yuv420m
46	pixfmt-yuv422m
47	pixfmt-yuv444m
48	pixfmt-yuv410
49	pixfmt-yuv422p
50	pixfmt-yuv411p
51	pixfmt-nv12
52	pixfmt-nv12m
53	pixfmt-nv12mt
54	pixfmt-nv16
55	pixfmt-nv16m
56	pixfmt-nv24
57	pixfmt-m420	273	pixfmt-m420

Documentation/userspace-api/media/videodev2.h.rst.exceptions+2−0

 replace symbol V4L2_CTRL_TYPE_H264_SPS :c:type:`v4l2_ctrl_type`
 replace symbol V4L2_CTRL_TYPE_H264_PPS :c:type:`v4l2_ctrl_type`
 replace symbol V4L2_CTRL_TYPE_H264_SCALING_MATRIX :c:type:`v4l2_ctrl_type`
+replace symbol V4L2_CTRL_TYPE_H264_PRED_WEIGHTS :c:type:`v4l2_ctrl_type`
 replace symbol V4L2_CTRL_TYPE_H264_SLICE_PARAMS :c:type:`v4l2_ctrl_type`
 replace symbol V4L2_CTRL_TYPE_H264_DECODE_PARAMS :c:type:`v4l2_ctrl_type`
 replace symbol V4L2_CTRL_TYPE_HEVC_SPS :c:type:`v4l2_ctrl_type`
 replace symbol V4L2_CTRL_TYPE_HEVC_PPS :c:type:`v4l2_ctrl_type`
 replace symbol V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS :c:type:`v4l2_ctrl_type`
 replace symbol V4L2_CTRL_TYPE_AREA :c:type:`v4l2_ctrl_type`
+replace symbol V4L2_CTRL_TYPE_FWHT_PARAMS :c:type:`v4l2_ctrl_type`
 # V4L2 capability defines
 replace define V4L2_CAP_VIDEO_CAPTURE device-capabilities

MAINTAINERS+58−29

@@ -1073,6 +1073,7 @@ M: Hans Verkuil <hverkuil-cisco@xs4all.nl> · 1072 unmodified lines
1073	L: linux-media@vger.kernel.org	1073	L: linux-media@vger.kernel.org
1074	S: Maintained	1074	S: Maintained
1075	F: drivers/media/i2c/adv7604*	1075	F: drivers/media/i2c/adv7604*
		1076	F: Documentation/devicetree/bindings/media/i2c/adv7604.yaml
1076		1077
1077	ANALOG DEVICES INC ADV7842 DRIVER	1078	ANALOG DEVICES INC ADV7842 DRIVER
1078	M: Hans Verkuil <hverkuil-cisco@xs4all.nl>	1079	M: Hans Verkuil <hverkuil-cisco@xs4all.nl>
@@ -3880,9 +3881,8 @@ T: git git://linuxtv.org/media_tree.git · 2801 unmodified lines
3880	F: drivers/media/radio/radio-cadet*	3881	F: drivers/media/radio/radio-cadet*
3881		3882
3882	CAFE CMOS INTEGRATED CAMERA CONTROLLER DRIVER	3883	CAFE CMOS INTEGRATED CAMERA CONTROLLER DRIVER
3883	M: Jonathan Corbet <corbet@lwn.net>
3884	L: linux-media@vger.kernel.org	3884	L: linux-media@vger.kernel.org
3885	S: Maintained	3885	S: Orphan
3886	T: git git://linuxtv.org/media_tree.git	3886	T: git git://linuxtv.org/media_tree.git
3887	F: Documentation/admin-guide/media/cafe_ccic*	3887	F: Documentation/admin-guide/media/cafe_ccic*
3888	F: drivers/media/platform/marvell-ccic/	3888	F: drivers/media/platform/marvell-ccic/
@@ -4363,7 +4363,7 @@ CODA V4L2 MEM2MEM DRIVER · 474 unmodified lines
4363	M: Philipp Zabel <p.zabel@pengutronix.de>	4363	M: Philipp Zabel <p.zabel@pengutronix.de>
4364	L: linux-media@vger.kernel.org	4364	L: linux-media@vger.kernel.org
4365	S: Maintained	4365	S: Maintained
4366	F: Documentation/devicetree/bindings/media/coda.txt	4366	F: Documentation/devicetree/bindings/media/coda.yaml
4367	F: drivers/media/platform/coda/	4367	F: drivers/media/platform/coda/
4368		4368
4369	CODE OF CONDUCT	4369	CODE OF CONDUCT
@@ -10854,8 +10854,8 @@ L: linux-media@vger.kernel.org · 6484 unmodified lines
10854	S: Maintained	10854	S: Maintained
10855	T: git git://linuxtv.org/media_tree.git	10855	T: git git://linuxtv.org/media_tree.git
10856	F: Documentation/admin-guide/media/imx7.rst	10856	F: Documentation/admin-guide/media/imx7.rst
10857	F: Documentation/devicetree/bindings/media/imx7-csi.txt	10857	F: Documentation/devicetree/bindings/media/nxp,imx7-csi.yaml
10858	F: Documentation/devicetree/bindings/media/imx7-mipi-csi2.txt	10858	F: Documentation/devicetree/bindings/media/nxp,imx7-mipi-csi2.yaml
10859	F: drivers/staging/media/imx/imx7-media-csi.c	10859	F: drivers/staging/media/imx/imx7-media-csi.c
10860	F: drivers/staging/media/imx/imx7-mipi-csis.c	10860	F: drivers/staging/media/imx/imx7-mipi-csis.c
10861		10861
@@ -11418,6 +11418,15 @@ F: Documentation/devicetree/bindings/media/amlogic,meson-gx-ao-cec.yaml · 556 unmodified lines
11418	F: drivers/media/cec/platform/meson/ao-cec-g12a.c	11418	F: drivers/media/cec/platform/meson/ao-cec-g12a.c
11419	F: drivers/media/cec/platform/meson/ao-cec.c	11419	F: drivers/media/cec/platform/meson/ao-cec.c
11420		11420
		11421	MESON GE2D DRIVER FOR AMLOGIC SOCS
		11422	M: Neil Armstrong <narmstrong@baylibre.com>
		11423	L: linux-media@vger.kernel.org
		11424	L: linux-amlogic@lists.infradead.org
		11425	S: Supported
		11426	T: git git://linuxtv.org/media_tree.git
		11427	F: Documentation/devicetree/bindings/media/amlogic,axg-ge2d.yaml
		11428	F: drivers/media/meson/ge2d/
		11429
11421	MESON NAND CONTROLLER DRIVER FOR AMLOGIC SOCS	11430	MESON NAND CONTROLLER DRIVER FOR AMLOGIC SOCS
11422	M: Liang Yang <liang.yang@amlogic.com>	11431	M: Liang Yang <liang.yang@amlogic.com>
11423	L: linux-mtd@lists.infradead.org	11432	L: linux-mtd@lists.infradead.org
@@ -11667,6 +11676,17 @@ M: Oliver Neukum <oliver@neukum.org> · 243 unmodified lines
11667	S: Maintained	11676	S: Maintained
11668	F: drivers/usb/image/microtek.*	11677	F: drivers/usb/image/microtek.*
11669		11678
		11679	MIPI CCS, SMIA AND SMIA++ IMAGE SENSOR DRIVER
		11680	M: Sakari Ailus <sakari.ailus@linux.intel.com>
		11681	L: linux-media@vger.kernel.org
		11682	S: Maintained
		11683	F: Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml
		11684	F: Documentation/driver-api/media/drivers/ccs/
		11685	F: drivers/media/i2c/ccs-pll.c
		11686	F: drivers/media/i2c/ccs-pll.h
		11687	F: drivers/media/i2c/ccs/
		11688	F: include/uapi/linux/smiapp.h
		11689
11670	MIPS	11690	MIPS
11671	M: Thomas Bogendoerfer <tsbogend@alpha.franken.de>	11691	M: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
11672	L: linux-mips@vger.kernel.org	11692	L: linux-mips@vger.kernel.org
@@ -11937,7 +11957,7 @@ M: Jacopo Mondi <jacopo@jmondi.org> · 264 unmodified lines
11937	L: linux-media@vger.kernel.org	11957	L: linux-media@vger.kernel.org
11938	S: Maintained	11958	S: Maintained
11939	T: git git://linuxtv.org/media_tree.git	11959	T: git git://linuxtv.org/media_tree.git
11940	F: Documentation/devicetree/bindings/media/i2c/aptina,mt9v111.txt	11960	F: Documentation/devicetree/bindings/media/i2c/aptina,mt9v111.yaml
11941	F: drivers/media/i2c/mt9v111.c	11961	F: drivers/media/i2c/mt9v111.c
11942		11962
11943	MULTIFUNCTION DEVICES (MFD)	11963	MULTIFUNCTION DEVICES (MFD)
@@ -12882,6 +12902,14 @@ M: Harald Welte <laforge@gnumonks.org> · 938 unmodified lines
12882	S: Maintained	12902	S: Maintained
12883	F: drivers/char/pcmcia/cm4040_cs.*	12903	F: drivers/char/pcmcia/cm4040_cs.*
12884		12904
		12905	OMNIVISION OV02A10 SENSOR DRIVER
		12906	M: Dongchun Zhu <dongchun.zhu@mediatek.com>
		12907	L: linux-media@vger.kernel.org
		12908	S: Maintained
		12909	T: git git://linuxtv.org/media_tree.git
		12910	F: Documentation/devicetree/bindings/media/i2c/ovti,ov02a10.yaml
		12911	F: drivers/media/i2c/ov02a10.c
		12912
12885	OMNIVISION OV13858 SENSOR DRIVER	12913	OMNIVISION OV13858 SENSOR DRIVER
12886	M: Sakari Ailus <sakari.ailus@linux.intel.com>	12914	M: Sakari Ailus <sakari.ailus@linux.intel.com>
12887	L: linux-media@vger.kernel.org	12915	L: linux-media@vger.kernel.org
@@ -12894,7 +12922,7 @@ M: Rui Miguel Silva <rmfrfs@gmail.com> · 6 unmodified lines
12894	L: linux-media@vger.kernel.org	12922	L: linux-media@vger.kernel.org
12895	S: Maintained	12923	S: Maintained
12896	T: git git://linuxtv.org/media_tree.git	12924	T: git git://linuxtv.org/media_tree.git
12897	F: Documentation/devicetree/bindings/media/i2c/ov2680.txt	12925	F: Documentation/devicetree/bindings/media/i2c/ov2680.yaml
12898	F: drivers/media/i2c/ov2680.c	12926	F: drivers/media/i2c/ov2680.c
12899		12927
12900	OMNIVISION OV2685 SENSOR DRIVER	12928	OMNIVISION OV2685 SENSOR DRIVER
@@ -12952,9 +12980,8 @@ T: git git://linuxtv.org/media_tree.git · 51 unmodified lines
12952	F: drivers/media/i2c/ov5695.c	12980	F: drivers/media/i2c/ov5695.c
12953		12981
12954	OMNIVISION OV7670 SENSOR DRIVER	12982	OMNIVISION OV7670 SENSOR DRIVER
12955	M: Jonathan Corbet <corbet@lwn.net>
12956	L: linux-media@vger.kernel.org	12983	L: linux-media@vger.kernel.org
12957	S: Maintained	12984	S: Orphan
12958	T: git git://linuxtv.org/media_tree.git	12985	T: git git://linuxtv.org/media_tree.git
12959	F: Documentation/devicetree/bindings/media/i2c/ov7670.txt	12986	F: Documentation/devicetree/bindings/media/i2c/ov7670.txt
12960	F: drivers/media/i2c/ov7670.c	12987	F: drivers/media/i2c/ov7670.c
@@ -12964,7 +12991,7 @@ M: Jacopo Mondi <jacopo@jmondi.org> · 3 unmodified lines
12964	L: linux-media@vger.kernel.org	12991	L: linux-media@vger.kernel.org
12965	S: Odd fixes	12992	S: Odd fixes
12966	T: git git://linuxtv.org/media_tree.git	12993	T: git git://linuxtv.org/media_tree.git
12967	F: Documentation/devicetree/bindings/media/i2c/ov772x.txt	12994	F: Documentation/devicetree/bindings/media/i2c/ovti,ov772x.yaml
12968	F: drivers/media/i2c/ov772x.c	12995	F: drivers/media/i2c/ov772x.c
12969	F: include/media/i2c/ov772x.h	12996	F: include/media/i2c/ov772x.h
12970		12997
@@ -13000,6 +13027,14 @@ T: git git://linuxtv.org/media_tree.git · 29 unmodified lines
13000	F: Documentation/devicetree/bindings/media/i2c/ov9650.txt	13027	F: Documentation/devicetree/bindings/media/i2c/ov9650.txt
13001	F: drivers/media/i2c/ov9650.c	13028	F: drivers/media/i2c/ov9650.c
13002		13029
		13030	OMNIVISION OV9734 SENSOR DRIVER
		13031	M: Tianshu Qiu <tian.shu.qiu@intel.com>
		13032	R: Bingbu Cao <bingbu.cao@intel.com>
		13033	L: linux-media@vger.kernel.org
		13034	S: Maintained
		13035	T: git git://linuxtv.org/media_tree.git
		13036	F: drivers/media/i2c/ov9734.c
		13037
13003	ONENAND FLASH DRIVER	13038	ONENAND FLASH DRIVER
13004	M: Kyungmin Park <kyungmin.park@samsung.com>	13039	M: Kyungmin Park <kyungmin.park@samsung.com>
13005	L: linux-mtd@lists.infradead.org	13040	L: linux-mtd@lists.infradead.org
@@ -14472,6 +14507,7 @@ W: https://wireless.wiki.kernel.org/en/users/Drivers/ath9k · 1466 unmodified lines
14472	F: drivers/net/wireless/ath/ath9k/	14507	F: drivers/net/wireless/ath/ath9k/
14473		14508
14474	QUALCOMM CAMERA SUBSYSTEM DRIVER	14509	QUALCOMM CAMERA SUBSYSTEM DRIVER
		14510	M: Robert Foss <robert.foss@linaro.org>
14475	M: Todor Tomov <todor.too@gmail.com>	14511	M: Todor Tomov <todor.too@gmail.com>
14476	L: linux-media@vger.kernel.org	14512	L: linux-media@vger.kernel.org
14477	S: Maintained	14513	S: Maintained
@@ -15045,10 +15081,13 @@ ROCKCHIP ISP V1 DRIVER · 567 unmodified lines
15045	M: Helen Koike <helen.koike@collabora.com>	15081	M: Helen Koike <helen.koike@collabora.com>
15046	M: Dafna Hirschfeld <dafna.hirschfeld@collabora.com>	15082	M: Dafna Hirschfeld <dafna.hirschfeld@collabora.com>
15047	L: linux-media@vger.kernel.org	15083	L: linux-media@vger.kernel.org
		15084	L: linux-rockchip@lists.infradead.org
15048	S: Maintained	15085	S: Maintained
15049	F: Documentation/admin-guide/media/rkisp1.rst	15086	F: Documentation/admin-guide/media/rkisp1.rst
		15087	F: Documentation/devicetree/bindings/media/rockchip-isp1.yaml
15050	F: Documentation/userspace-api/media/v4l/pixfmt-meta-rkisp1.rst	15088	F: Documentation/userspace-api/media/v4l/pixfmt-meta-rkisp1.rst
15051	F: drivers/staging/media/rkisp1/	15089	F: drivers/media/platform/rockchip/rkisp1
		15090	F: include/uapi/linux/rkisp1-config.h
15052		15091
15053	ROCKCHIP RASTER 2D GRAPHIC ACCELERATION UNIT DRIVER	15092	ROCKCHIP RASTER 2D GRAPHIC ACCELERATION UNIT DRIVER
15054	M: Jacob Chen <jacob-chen@iotwrt.com>	15093	M: Jacob Chen <jacob-chen@iotwrt.com>
@@ -16127,16 +16166,6 @@ S: Maintained · 1072 unmodified lines
16127	F: drivers/firmware/smccc/	16166	F: drivers/firmware/smccc/
16128	F: include/linux/arm-smccc.h	16167	F: include/linux/arm-smccc.h
16129		16168
16130	SMIA AND SMIA++ IMAGE SENSOR DRIVER
16131	M: Sakari Ailus <sakari.ailus@linux.intel.com>
16132	L: linux-media@vger.kernel.org
16133	S: Maintained
16134	F: Documentation/devicetree/bindings/media/i2c/nokia,smia.txt
16135	F: drivers/media/i2c/smiapp-pll.c
16136	F: drivers/media/i2c/smiapp-pll.h
16137	F: drivers/media/i2c/smiapp/
16138	F: include/uapi/linux/smiapp.h
16139
16140	SMM665 HARDWARE MONITOR DRIVER	16169	SMM665 HARDWARE MONITOR DRIVER
16141	M: Guenter Roeck <linux@roeck-us.net>	16170	M: Guenter Roeck <linux@roeck-us.net>
16142	L: linux-hwmon@vger.kernel.org	16171	L: linux-hwmon@vger.kernel.org
@@ -16299,7 +16328,7 @@ M: Ricardo Ribalda <ribalda@kernel.org> · 156 unmodified lines
16299	L: linux-media@vger.kernel.org	16328	L: linux-media@vger.kernel.org
16300	S: Maintained	16329	S: Maintained
16301	T: git git://linuxtv.org/media_tree.git	16330	T: git git://linuxtv.org/media_tree.git
16302	F: Documentation/devicetree/bindings/media/i2c/sony,imx214.txt	16331	F: Documentation/devicetree/bindings/media/i2c/sony,imx214.yaml
16303	F: drivers/media/i2c/imx214.c	16332	F: drivers/media/i2c/imx214.c
16304		16333
16305	SONY IMX219 SENSOR DRIVER	16334	SONY IMX219 SENSOR DRIVER
@@ -19443,6 +19472,13 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/dlemoal/zonefs.git · 3137 unmodified lines
19443	F: Documentation/filesystems/zonefs.rst	19472	F: Documentation/filesystems/zonefs.rst
19444	F: fs/zonefs/	19473	F: fs/zonefs/
19445		19474
		19475	ZPOOL COMPRESSED PAGE STORAGE API
		19476	M: Dan Streetman <ddstreet@ieee.org>
		19477	L: linux-mm@kvack.org
		19478	S: Maintained
		19479	F: include/linux/zpool.h
		19480	F: mm/zpool.c
		19481
19446	ZR36067 VIDEO FOR LINUX DRIVER	19482	ZR36067 VIDEO FOR LINUX DRIVER
19447	M: Corentin Labbe <clabbe@baylibre.com>	19483	M: Corentin Labbe <clabbe@baylibre.com>
19448	L: mjpeg-users@lists.sourceforge.net	19484	L: mjpeg-users@lists.sourceforge.net
@@ -19453,13 +19489,6 @@ Q: https://patchwork.linuxtv.org/project/linux-media/list/ · 4 unmodified lines
19453	F: Documentation/driver-api/media/drivers/zoran.rst	19489	F: Documentation/driver-api/media/drivers/zoran.rst
19454	F: drivers/staging/media/zoran/	19490	F: drivers/staging/media/zoran/
19455		19491
19456	ZPOOL COMPRESSED PAGE STORAGE API
19457	M: Dan Streetman <ddstreet@ieee.org>
19458	L: linux-mm@kvack.org
19459	S: Maintained
19460	F: include/linux/zpool.h
19461	F: mm/zpool.c
19462
19463	ZRAM COMPRESSED RAM BLOCK DEVICE DRVIER	19492	ZRAM COMPRESSED RAM BLOCK DEVICE DRVIER
19464	M: Minchan Kim <minchan@kernel.org>	19493	M: Minchan Kim <minchan@kernel.org>
19465	M: Nitin Gupta <ngupta@vflare.org>	19494	M: Nitin Gupta <ngupta@vflare.org>

drivers/media/Kconfig+0−1

@@ -24,7 +24,6 @@ if MEDIA_SUPPORT · 23 unmodified lines
24		24
25	config MEDIA_SUPPORT_FILTER	25	config MEDIA_SUPPORT_FILTER
26	bool "Filter media drivers"	26	bool "Filter media drivers"
27	depends on MEDIA_SUPPORT
28	default y if !EMBEDDED && !EXPERT	27	default y if !EMBEDDED && !EXPERT
29	help	28	help
30	Configuring the media subsystem can be complex, as there are	29	Configuring the media subsystem can be complex, as there are

drivers/media/cec/core/cec-core.c+2−2

 		mutex_unlock(&devnode->lock);
 		return;
 	}
+	devnode->registered = false;
+	devnode->unregistered = true;
 	list_for_each_entry(fh, &devnode->fhs, list)
 		wake_up_interruptible(&fh->wait);
-	devnode->registered = false;
-	devnode->unregistered = true;
 	mutex_unlock(&devnode->lock);
 	mutex_lock(&adap->lock);

drivers/media/common/cx2341x.c+2−2

@@ -166,7 +166,7 @@ static void cx2341x_ctrl_fill(u32 id, const char *name, enum v4l2_ctrl_type ty · 165 unmodified lines
166		166
167	/* Must be sorted from low to high control ID! */	167	/* Must be sorted from low to high control ID! */
168	const u32 cx2341x_mpeg_ctrls[] = {	168	const u32 cx2341x_mpeg_ctrls[] = {
169	V4L2_CID_MPEG_CLASS,	169	V4L2_CID_CODEC_CLASS,
170	V4L2_CID_MPEG_STREAM_TYPE,	170	V4L2_CID_MPEG_STREAM_TYPE,
171	V4L2_CID_MPEG_STREAM_VBI_FMT,	171	V4L2_CID_MPEG_STREAM_VBI_FMT,
172	V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,	172	V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
@@ -574,7 +574,7 @@ int cx2341x_ctrl_query(const struct cx2341x_mpeg_params *params, · 401 unmodified lines
574	int err;	574	int err;
575		575
576	switch (qctrl->id) {	576	switch (qctrl->id) {
577	case V4L2_CID_MPEG_CLASS:	577	case V4L2_CID_CODEC_CLASS:
578	return v4l2_ctrl_query_fill(qctrl, 0, 0, 0, 0);	578	return v4l2_ctrl_query_fill(qctrl, 0, 0, 0, 0);
579	case V4L2_CID_MPEG_STREAM_TYPE:	579	case V4L2_CID_MPEG_STREAM_TYPE:
580	return v4l2_ctrl_query_fill(qctrl,	580	return v4l2_ctrl_query_fill(qctrl,

drivers/media/common/saa7146/saa7146_core.c+21−18

 		goto err_free_slist;
 	pt->nents = pages;
-	slen = pci_map_sg(pci,pt->slist,pt->nents,PCI_DMA_FROMDEVICE);
+	slen = dma_map_sg(&pci->dev, pt->slist, pt->nents, DMA_FROM_DEVICE);
 	if (0 == slen)
 		goto err_free_pgtable;
 	return mem;
 err_unmap_sg:
-	pci_unmap_sg(pci, pt->slist, pt->nents, PCI_DMA_FROMDEVICE);
+	dma_unmap_sg(&pci->dev, pt->slist, pt->nents, DMA_FROM_DEVICE);
 err_free_pgtable:
 	saa7146_pgtable_free(pci, pt);
 err_free_slist:
 void saa7146_vfree_destroy_pgtable(struct pci_dev *pci, void *mem, struct saa7146_pgtable *pt)
 {
-	pci_unmap_sg(pci, pt->slist, pt->nents, PCI_DMA_FROMDEVICE);
+	dma_unmap_sg(&pci->dev, pt->slist, pt->nents, DMA_FROM_DEVICE);
 	saa7146_pgtable_free(pci, pt);
 	kfree(pt->slist);
 	pt->slist = NULL;
 {
 	if (NULL == pt->cpu)
 		return;
-	pci_free_consistent(pci, pt->size, pt->cpu, pt->dma);
+	dma_free_coherent(&pci->dev, pt->size, pt->cpu, pt->dma);
 	pt->cpu = NULL;
 }
 	__le32       *cpu;
 	dma_addr_t   dma_addr = 0;
-	cpu = pci_alloc_consistent(pci, PAGE_SIZE, &dma_addr);
+	cpu = dma_alloc_coherent(&pci->dev, PAGE_SIZE, &dma_addr, GFP_KERNEL);
 	if (NULL == cpu) {
 		return -ENOMEM;
 	}
 	err = -ENOMEM;
 	/* get memory for various stuff */
-	dev->d_rps0.cpu_addr = pci_zalloc_consistent(pci, SAA7146_RPS_MEM,
+	dev->d_rps0.cpu_addr = dma_alloc_coherent(&pci->dev, SAA7146_RPS_MEM,
-						     &dev->d_rps0.dma_handle);
+						  &dev->d_rps0.dma_handle,
+						  GFP_KERNEL);
 	if (!dev->d_rps0.cpu_addr)
 		goto err_free_irq;
-	dev->d_rps1.cpu_addr = pci_zalloc_consistent(pci, SAA7146_RPS_MEM,
+	dev->d_rps1.cpu_addr = dma_alloc_coherent(&pci->dev, SAA7146_RPS_MEM,
-						     &dev->d_rps1.dma_handle);
+						  &dev->d_rps1.dma_handle,
+						  GFP_KERNEL);
 	if (!dev->d_rps1.cpu_addr)
 		goto err_free_rps0;
-	dev->d_i2c.cpu_addr = pci_zalloc_consistent(pci, SAA7146_RPS_MEM,
+	dev->d_i2c.cpu_addr = dma_alloc_coherent(&pci->dev, SAA7146_RPS_MEM,
-						    &dev->d_i2c.dma_handle);
+						 &dev->d_i2c.dma_handle, GFP_KERNEL);
 	if (!dev->d_i2c.cpu_addr)
 		goto err_free_rps1;
 	return err;
 err_free_i2c:
-	pci_free_consistent(pci, SAA7146_RPS_MEM, dev->d_i2c.cpu_addr,
+	dma_free_coherent(&pci->dev, SAA7146_RPS_MEM, dev->d_i2c.cpu_addr,
-			    dev->d_i2c.dma_handle);
+			  dev->d_i2c.dma_handle);
 err_free_rps1:
-	pci_free_consistent(pci, SAA7146_RPS_MEM, dev->d_rps1.cpu_addr,
+	dma_free_coherent(&pci->dev, SAA7146_RPS_MEM, dev->d_rps1.cpu_addr,
-			    dev->d_rps1.dma_handle);
+			  dev->d_rps1.dma_handle);
 err_free_rps0:
-	pci_free_consistent(pci, SAA7146_RPS_MEM, dev->d_rps0.cpu_addr,
+	dma_free_coherent(&pci->dev, SAA7146_RPS_MEM, dev->d_rps0.cpu_addr,
-			    dev->d_rps0.dma_handle);
+			  dev->d_rps0.dma_handle);
 err_free_irq:
 	free_irq(pci->irq, (void *)dev);
 err_unmap:
 	free_irq(pdev->irq, dev);
 	for (p = dev_map; p->addr; p++)
-		pci_free_consistent(pdev, SAA7146_RPS_MEM, p->addr, p->dma);
+		dma_free_coherent(&pdev->dev, SAA7146_RPS_MEM, p->addr,
+				  p->dma);
 	iounmap(dev->mem);
 	pci_release_region(pdev, 0);

drivers/media/common/saa7146/saa7146_fops.c+4−5

 	struct videobuf_dmabuf *dma=videobuf_to_dma(&buf->vb);
 	DEB_EE("dev:%p, buf:%p\n", dev, buf);
-	BUG_ON(in_interrupt());
 	videobuf_waiton(q, &buf->vb, 0, 0);
 	videobuf_dma_unmap(q->dev, dma);
 	videobuf_dma_free(dma);
 	dev->ext_vv_data = ext_vv;
 	vv->d_clipping.cpu_addr =
-		pci_zalloc_consistent(dev->pci, SAA7146_CLIPPING_MEM,
+		dma_alloc_coherent(&dev->pci->dev, SAA7146_CLIPPING_MEM,
-				      &vv->d_clipping.dma_handle);
+				   &vv->d_clipping.dma_handle, GFP_KERNEL);
 	if( NULL == vv->d_clipping.cpu_addr ) {
 		ERR("out of memory. aborting.\n");
 		kfree(vv);
 	DEB_EE("dev:%p\n", dev);
 	v4l2_device_unregister(&dev->v4l2_dev);
-	pci_free_consistent(dev->pci, SAA7146_CLIPPING_MEM, vv->d_clipping.cpu_addr, vv->d_clipping.dma_handle);
+	dma_free_coherent(&dev->pci->dev, SAA7146_CLIPPING_MEM,
+			  vv->d_clipping.cpu_addr, vv->d_clipping.dma_handle);
 	v4l2_ctrl_handler_free(&dev->ctrl_handler);
 	kfree(vv);
 	dev->vv_data = NULL;

drivers/media/common/saa7146/saa7146_vbi.c+3−3

@@ -22,7 +22,7 @@ static int vbi_workaround(struct saa7146_dev *dev) · 21 unmodified lines
22	as specified. there is this workaround, but please	22	as specified. there is this workaround, but please
23	don't let me explain it. ;-) */	23	don't let me explain it. ;-) */
24		24
25	cpu = pci_alloc_consistent(dev->pci, 4096, &dma_addr);	25	cpu = dma_alloc_coherent(&dev->pci->dev, 4096, &dma_addr, GFP_KERNEL);
26	if (NULL == cpu)	26	if (NULL == cpu)
27	return -ENOMEM;	27	return -ENOMEM;
28		28
@@ -123,12 +123,12 @@ static int vbi_workaround(struct saa7146_dev *dev) · 94 unmodified lines
123	/* stop rps1 for sure */	123	/* stop rps1 for sure */
124	saa7146_write(dev, MC1, MASK_29);	124	saa7146_write(dev, MC1, MASK_29);
125		125
126	pci_free_consistent(dev->pci, 4096, cpu, dma_addr);	126	dma_free_coherent(&dev->pci->dev, 4096, cpu, dma_addr);
127	return -EINTR;	127	return -EINTR;
128	}	128	}
129	}	129	}
130		130
131	pci_free_consistent(dev->pci, 4096, cpu, dma_addr);	131	dma_free_coherent(&dev->pci->dev, 4096, cpu, dma_addr);
132	return 0;	132	return 0;
133	}	133	}
134		134

drivers/media/common/saa7146/saa7146_video.c+2−4

 	vv->ov.nclips = f->fmt.win.clipcount;
 	if (vv->ov.nclips > 16)
 		vv->ov.nclips = 16;
-	if (copy_from_user(vv->ov.clips, f->fmt.win.clips,
+	memcpy(vv->ov.clips, f->fmt.win.clips,
-				sizeof(struct v4l2_clip) * vv->ov.nclips)) {
+	       sizeof(struct v4l2_clip) * vv->ov.nclips);
-		return -EFAULT;
-	}
 	/* vv->ov.fh is used to indicate that we have valid overlay information, too */
 	vv->ov.fh = fh;

drivers/media/common/siano/smsdvb-main.c+4−1

 	rc = dvb_create_media_graph(&client->adapter, true);
 	if (rc < 0) {
 		pr_err("dvb_create_media_graph failed %d\n", rc);
-		goto client_error;
+		goto media_graph_error;
 	}
 	pr_info("DVB interface registered.\n");
 	return 0;
+media_graph_error:
+	smsdvb_debugfs_release(client);
 client_error:
 	dvb_unregister_frontend(&client->frontend);

drivers/media/dvb-core/dvbdev.c+3−0

 	if (IS_ERR(clsdev)) {
 		pr_err("%s: failed to create device dvb%d.%s%d (%ld)\n",
 		       __func__, adap->num, dnames[type], id, PTR_ERR(clsdev));
+		dvb_media_device_free(dvbdev);
+		kfree(dvbdevfops);
+		kfree(dvbdev);
 		return PTR_ERR(clsdev);
 	}
 	dprintk("DVB: register adapter%d/%s%d @ minor: %i (0x%02x)\n",

drivers/media/dvb-frontends/ascot2e.h+1−1

@@ -33,7 +33,7 @@ struct ascot2e_config { · 32 unmodified lines
33		33
34	#if IS_REACHABLE(CONFIG_DVB_ASCOT2E)	34	#if IS_REACHABLE(CONFIG_DVB_ASCOT2E)
35	/**	35	/**
36	* Attach an ascot2e tuner	36	* ascot2e_attach - Attach an ascot2e tuner
37	*	37	*
38	* @fe: frontend to be attached	38	* @fe: frontend to be attached
39	* @config: pointer to &struct ascot2e_config with tuner configuration.	39	* @config: pointer to &struct ascot2e_config with tuner configuration.

drivers/media/dvb-frontends/cxd2820r.h+1−1

@@ -96,7 +96,7 @@ struct cxd2820r_config { · 95 unmodified lines
96		96
97	#if IS_REACHABLE(CONFIG_DVB_CXD2820R)	97	#if IS_REACHABLE(CONFIG_DVB_CXD2820R)
98	/**	98	/**
99	* Attach a cxd2820r demod	99	* cxd2820r_attach - Attach a cxd2820r demod
100	*	100	*
101	* @config: pointer to &struct cxd2820r_config with demod configuration.	101	* @config: pointer to &struct cxd2820r_config with demod configuration.
102	* @i2c: i2c adapter to use.	102	* @i2c: i2c adapter to use.

drivers/media/dvb-frontends/drx39xyj/drxj.c+0−7

 	default:
 		return -EINVAL;
-		break;
 	}
 	/* Write command */
 			break;
 		default:
 			return -EINVAL;
-			break;
 		}		/* switch ( uio_cfg->mode ) */
 		break;
       /*====================================================================*/
 			break;
 		default:
 			return -EINVAL;
-			break;
 		}		/* switch ( uio_cfg->mode ) */
 		break;
       /*====================================================================*/
 		case DRX_UIO_MODE_FIRMWARE0:
 		default:
 			return -EINVAL;
-			break;
 		}		/* switch ( uio_cfg->mode ) */
 		break;
       /*====================================================================*/
 	default:
 		ext_attr->standard = DRX_STANDARD_UNKNOWN;
 		return -EINVAL;
-		break;
 	}
 	return 0;
 	default:
 		/* Unknow sleep mode */
 		return -EINVAL;
-		break;
 	}
 	/* Check if device needs to be powered up */
 		}
 		default:
 			return -EINVAL;
-			break;
 		}
 		mc_data += mc_block_nr_bytes;

drivers/media/dvb-frontends/drxd_hard.c+0−1

@@ -1622,7 +1622,6 @@ static int CorrectSysClockDeviation(struct drxd_state *state) · 1621 unmodified lines
1622	break;	1622	break;
1623	default:	1623	default:
1624	return -1;	1624	return -1;
1625	break;
1626	}	1625	}
1627		1626
1628	/* Compute new sysclock value	1627	/* Compute new sysclock value

drivers/media/dvb-frontends/drxk.h+1−1

@@ -54,7 +54,7 @@ struct drxk_config { · 53 unmodified lines
54		54
55	#if IS_REACHABLE(CONFIG_DVB_DRXK)	55	#if IS_REACHABLE(CONFIG_DVB_DRXK)
56	/**	56	/**
57	* Attach a drxk demod	57	* drxk_attach - Attach a drxk demod
58	*	58	*
59	* @config: pointer to &struct drxk_config with demod configuration.	59	* @config: pointer to &struct drxk_config with demod configuration.
60	* @i2c: i2c adapter to use.	60	* @i2c: i2c adapter to use.

drivers/media/dvb-frontends/dvb-pll.h+1−1

@@ -38,7 +38,7 @@ struct dvb_pll_config { · 37 unmodified lines
38		38
39	#if IS_REACHABLE(CONFIG_DVB_PLL)	39	#if IS_REACHABLE(CONFIG_DVB_PLL)
40	/**	40	/**
41	* Attach a dvb-pll to the supplied frontend structure.	41	* dvb_pll_attach - Attach a dvb-pll to the supplied frontend structure.
42	*	42	*
43	* @fe: Frontend to attach to.	43	* @fe: Frontend to attach to.
44	* @pll_addr: i2c address of the PLL (if used).	44	* @pll_addr: i2c address of the PLL (if used).

drivers/media/dvb-frontends/helene.h+2−2

@@ -44,7 +44,7 @@ struct helene_config { · 43 unmodified lines
44		44
45	#if IS_REACHABLE(CONFIG_DVB_HELENE)	45	#if IS_REACHABLE(CONFIG_DVB_HELENE)
46	/**	46	/**
47	* Attach a helene tuner (terrestrial and cable standards)	47	* helene_attach - Attach a helene tuner (terrestrial and cable standards)
48	*	48	*
49	* @fe: frontend to be attached	49	* @fe: frontend to be attached
50	* @config: pointer to &struct helene_config with tuner configuration.	50	* @config: pointer to &struct helene_config with tuner configuration.
@@ -57,7 +57,7 @@ extern struct dvb_frontend helene_attach(struct dvb_frontend fe, · 6 unmodified lines
57	struct i2c_adapter *i2c);	57	struct i2c_adapter *i2c);
58		58
59	/**	59	/**
60	* Attach a helene tuner (satellite standards)	60	* helene_attach_s - Attach a helene tuner (satellite standards)
61	*	61	*
62	* @fe: frontend to be attached	62	* @fe: frontend to be attached
63	* @config: pointer to &struct helene_config with tuner configuration.	63	* @config: pointer to &struct helene_config with tuner configuration.

drivers/media/dvb-frontends/horus3a.h+1−1

@@ -33,7 +33,7 @@ struct horus3a_config { · 32 unmodified lines
33		33
34	#if IS_REACHABLE(CONFIG_DVB_HORUS3A)	34	#if IS_REACHABLE(CONFIG_DVB_HORUS3A)
35	/**	35	/**
36	* Attach a horus3a tuner	36	* horus3a_attach - Attach a horus3a tuner
37	*	37	*
38	* @fe: frontend to be attached	38	* @fe: frontend to be attached
39	* @config: pointer to &struct helene_config with tuner configuration.	39	* @config: pointer to &struct helene_config with tuner configuration.

drivers/media/dvb-frontends/ix2505v.h+2−2

@@ -1,5 +1,5 @@
1	/* SPDX-License-Identifier: GPL-2.0-only */	1	/* SPDX-License-Identifier: GPL-2.0-only */
2	/**	2	/*
3	* Driver for Sharp IX2505V (marked B0017) DVB-S silicon tuner	3	* Driver for Sharp IX2505V (marked B0017) DVB-S silicon tuner
4	*	4	*
5	* Copyright (C) 2010 Malcolm Priestley	5	* Copyright (C) 2010 Malcolm Priestley
@@ -31,7 +31,7 @@ struct ix2505v_config { · 25 unmodified lines
31		31
32	#if IS_REACHABLE(CONFIG_DVB_IX2505V)	32	#if IS_REACHABLE(CONFIG_DVB_IX2505V)
33	/**	33	/**
34	* Attach a ix2505v tuner to the supplied frontend structure.	34	* ix2505v_attach - Attach a ix2505v tuner to the supplied frontend structure.
35	*	35	*
36	* @fe: Frontend to attach to.	36	* @fe: Frontend to attach to.
37	* @config: pointer to &struct ix2505v_config	37	* @config: pointer to &struct ix2505v_config

drivers/media/dvb-frontends/m88ds3103.c+3−3

@@ -1793,9 +1793,9 @@ static int m88ds3103_probe(struct i2c_client *client, · 1792 unmodified lines
1793	dev->config.lnb_en_pol = pdata->lnb_en_pol;	1793	dev->config.lnb_en_pol = pdata->lnb_en_pol;
1794	dev->cfg = &dev->config;	1794	dev->cfg = &dev->config;
1795	/* create regmap */	1795	/* create regmap */
1796	dev->regmap_config.reg_bits = 8,	1796	dev->regmap_config.reg_bits = 8;
1797	dev->regmap_config.val_bits = 8,	1797	dev->regmap_config.val_bits = 8;
1798	dev->regmap_config.lock_arg = dev,	1798	dev->regmap_config.lock_arg = dev;
1799	dev->regmap = devm_regmap_init_i2c(client, &dev->regmap_config);	1799	dev->regmap = devm_regmap_init_i2c(client, &dev->regmap_config);
1800	if (IS_ERR(dev->regmap)) {	1800	if (IS_ERR(dev->regmap)) {
1801	ret = PTR_ERR(dev->regmap);	1801	ret = PTR_ERR(dev->regmap);

drivers/media/dvb-frontends/m88ds3103.h+1−1

@@ -128,7 +128,7 @@ struct m88ds3103_config { · 127 unmodified lines
128	#if defined(CONFIG_DVB_M88DS3103) \|\| \	128	#if defined(CONFIG_DVB_M88DS3103) \|\| \
129	(defined(CONFIG_DVB_M88DS3103_MODULE) && defined(MODULE))	129	(defined(CONFIG_DVB_M88DS3103_MODULE) && defined(MODULE))
130	/**	130	/**
131	* Attach a m88ds3103 demod	131	* m88ds3103_attach - Attach a m88ds3103 demod
132	*	132	*
133	* @config: pointer to &struct m88ds3103_config with demod configuration.	133	* @config: pointer to &struct m88ds3103_config with demod configuration.
134	* @i2c: i2c adapter to use.	134	* @i2c: i2c adapter to use.

drivers/media/dvb-frontends/mb86a20s.h+1−1

@@ -26,7 +26,7 @@ struct mb86a20s_config { · 25 unmodified lines
26		26
27	#if IS_REACHABLE(CONFIG_DVB_MB86A20S)	27	#if IS_REACHABLE(CONFIG_DVB_MB86A20S)
28	/**	28	/**
29	* Attach a mb86a20s demod	29	* mb86a20s_attach - Attach a mb86a20s demod
30	*	30	*
31	* @config: pointer to &struct mb86a20s_config with demod configuration.	31	* @config: pointer to &struct mb86a20s_config with demod configuration.
32	* @i2c: i2c adapter to use.	32	* @i2c: i2c adapter to use.

drivers/media/dvb-frontends/nxt200x.c+0−16

 			break;
 		default:
 			return -EINVAL;
-			break;
 	}
 	/* set multi register length */
 			break;
 		default:
 			return -EINVAL;
-			break;
 	}
 	pr_warn("Error writing multireg register 0x%02X\n", reg);
 			/* read the actual data */
 			nxt200x_readbytes(state, reg, data, len);
 			return 0;
-			break;
 		case NXT2004:
 			/* probably not right, but gives correct values */
 			attr = 0x02;
 				nxt200x_readbytes(state, 0x36 + i, &data[i], 1);
 			}
 			return 0;
-			break;
 		default:
 			return -EINVAL;
-			break;
 	}
 }
 			break;
 		default:
 			return -EINVAL;
-			break;
 	}
 	return 0;
 }
 			break;
 		default:
 			return -EINVAL;
-			break;
 	}
 	if (fe->ops.tuner_ops.calc_regs) {
 			break;
 		default:
 			return -EINVAL;
-			break;
 	}
 	nxt200x_writebytes(state, 0x42, buf, 1);
 			break;
 		default:
 			return -EINVAL;
-			break;
 	}
 	nxt200x_writebytes(state, 0x57, buf, 1);
 			break;
 		default:
 			return -EINVAL;
-			break;
 	}
 	/* write sdmx input */
 				break;
 		default:
 				return -EINVAL;
-				break;
 	}
 	buf[1] = 0x00;
 	switch (state->demod_chip) {
 			break;
 		default:
 			return -EINVAL;
-			break;
 	}
 	/* write adc power lpf fc */
 			break;
 		default:
 			return -EINVAL;
-			break;
 	}
 	/* write kg1 */
 				break;
 		default:
 				return -EINVAL;
-				break;
 	}
 	nxt200x_writebytes(state, 0x30, buf, 1);
 			break;
 		default:
 			return -EINVAL;
-			break;
 	}
 	/* write agc control reg */
 				break;
 			default:
 				return -EINVAL;
-				break;
 		}
 		state->initialised = 1;
 	}

drivers/media/dvb-frontends/rtl2832.c+7−7

@@ -1056,13 +1056,13 @@ static int rtl2832_probe(struct i2c_client *client, · 1055 unmodified lines
1056	dev->sleeping = true;	1056	dev->sleeping = true;
1057	INIT_DELAYED_WORK(&dev->i2c_gate_work, rtl2832_i2c_gate_work);	1057	INIT_DELAYED_WORK(&dev->i2c_gate_work, rtl2832_i2c_gate_work);
1058	/* create regmap */	1058	/* create regmap */
1059	dev->regmap_config.reg_bits = 8,	1059	dev->regmap_config.reg_bits = 8;
1060	dev->regmap_config.val_bits = 8,	1060	dev->regmap_config.val_bits = 8;
1061	dev->regmap_config.volatile_reg = rtl2832_volatile_reg,	1061	dev->regmap_config.volatile_reg = rtl2832_volatile_reg;
1062	dev->regmap_config.max_register = 5 * 0x100,	1062	dev->regmap_config.max_register = 5 * 0x100;
1063	dev->regmap_config.ranges = regmap_range_cfg,	1063	dev->regmap_config.ranges = regmap_range_cfg;
1064	dev->regmap_config.num_ranges = ARRAY_SIZE(regmap_range_cfg),	1064	dev->regmap_config.num_ranges = ARRAY_SIZE(regmap_range_cfg);
1065	dev->regmap_config.cache_type = REGCACHE_NONE,	1065	dev->regmap_config.cache_type = REGCACHE_NONE;
1066	dev->regmap = regmap_init_i2c(client, &dev->regmap_config);	1066	dev->regmap = regmap_init_i2c(client, &dev->regmap_config);
1067	if (IS_ERR(dev->regmap)) {	1067	if (IS_ERR(dev->regmap)) {
1068	ret = PTR_ERR(dev->regmap);	1068	ret = PTR_ERR(dev->regmap);

drivers/media/dvb-frontends/si2165.c+1−1

@@ -5,7 +5,7 @@ · 4 unmodified lines
5	* Copyright (C) 2013-2017 Matthias Schwarzott <zzam@gentoo.org>	5	* Copyright (C) 2013-2017 Matthias Schwarzott <zzam@gentoo.org>
6	*	6	*
7	* References:	7	* References:
8	* http://www.silabs.com/Support%20Documents/TechnicalDocs/Si2165-short.pdf	8	* https://www.silabs.com/Support%20Documents/TechnicalDocs/Si2165-short.pdf
9	*/	9	*/
10		10
11	#include <linux/delay.h>	11	#include <linux/delay.h>

drivers/media/dvb-frontends/si2165.h+1−1

@@ -5,7 +5,7 @@ · 4 unmodified lines
5	* Copyright (C) 2013-2017 Matthias Schwarzott <zzam@gentoo.org>	5	* Copyright (C) 2013-2017 Matthias Schwarzott <zzam@gentoo.org>
6	*	6	*
7	* References:	7	* References:
8	* http://www.silabs.com/Support%20Documents/TechnicalDocs/Si2165-short.pdf	8	* https://www.silabs.com/Support%20Documents/TechnicalDocs/Si2165-short.pdf
9	*/	9	*/
10		10
11	#ifndef _DVB_SI2165_H	11	#ifndef _DVB_SI2165_H

drivers/media/dvb-frontends/si21xx.c+0−2

 	switch (volt) {
 	case SEC_VOLTAGE_18:
 		return si21_writereg(state, LNB_CTRL_REG_1, val | 0x40);
-		break;
 	case SEC_VOLTAGE_13:
 		return si21_writereg(state, LNB_CTRL_REG_1, (val & ~0x40));
-		break;
 	default:
 		return -EINVAL;
 	}

drivers/media/dvb-frontends/stb6000.h+1−1

@@ -15,7 +15,7 @@ · 14 unmodified lines
15		15
16	#if IS_REACHABLE(CONFIG_DVB_STB6000)	16	#if IS_REACHABLE(CONFIG_DVB_STB6000)
17	/**	17	/**
18	* Attach a stb6000 tuner to the supplied frontend structure.	18	* stb6000_attach - Attach a stb6000 tuner to the supplied frontend structure.
19	*	19	*
20	* @fe: Frontend to attach to.	20	* @fe: Frontend to attach to.
21	* @addr: i2c address of the tuner.	21	* @addr: i2c address of the tuner.

drivers/media/dvb-frontends/tda826x.h+1−1

@@ -14,7 +14,7 @@ · 13 unmodified lines
14	#include <media/dvb_frontend.h>	14	#include <media/dvb_frontend.h>
15		15
16	/**	16	/**
17	* Attach a tda826x tuner to the supplied frontend structure.	17	* tda826x_attach - Attach a tda826x tuner to the supplied frontend structure.
18	*	18	*
19	* @fe: Frontend to attach to.	19	* @fe: Frontend to attach to.
20	* @addr: i2c address of the tuner.	20	* @addr: i2c address of the tuner.

drivers/media/dvb-frontends/ts2020.c+5−5

@@ -569,11 +569,11 @@ static int ts2020_probe(struct i2c_client *client, · 568 unmodified lines
569		569
570	/* create regmap */	570	/* create regmap */
571	mutex_init(&dev->regmap_mutex);	571	mutex_init(&dev->regmap_mutex);
572	dev->regmap_config.reg_bits = 8,	572	dev->regmap_config.reg_bits = 8;
573	dev->regmap_config.val_bits = 8,	573	dev->regmap_config.val_bits = 8;
574	dev->regmap_config.lock = ts2020_regmap_lock,	574	dev->regmap_config.lock = ts2020_regmap_lock;
575	dev->regmap_config.unlock = ts2020_regmap_unlock,	575	dev->regmap_config.unlock = ts2020_regmap_unlock;
576	dev->regmap_config.lock_arg = dev,	576	dev->regmap_config.lock_arg = dev;
577	dev->regmap = regmap_init_i2c(client, &dev->regmap_config);	577	dev->regmap = regmap_init_i2c(client, &dev->regmap_config);
578	if (IS_ERR(dev->regmap)) {	578	if (IS_ERR(dev->regmap)) {
579	ret = PTR_ERR(dev->regmap);	579	ret = PTR_ERR(dev->regmap);

drivers/media/dvb-frontends/zl10036.h+2−2

@@ -1,5 +1,5 @@
1	/* SPDX-License-Identifier: GPL-2.0-only */	1	/* SPDX-License-Identifier: GPL-2.0-only */
2	/**	2	/*
3	* Driver for Zarlink ZL10036 DVB-S silicon tuner	3	* Driver for Zarlink ZL10036 DVB-S silicon tuner
4	*	4	*
5	* Copyright (C) 2006 Tino Reichardt	5	* Copyright (C) 2006 Tino Reichardt
@@ -19,7 +19,7 @@ struct zl10036_config { · 13 unmodified lines
19		19
20	#if IS_REACHABLE(CONFIG_DVB_ZL10036)	20	#if IS_REACHABLE(CONFIG_DVB_ZL10036)
21	/**	21	/**
22	* Attach a zl10036 tuner to the supplied frontend structure.	22	* zl10036_attach - Attach a zl10036 tuner to the supplied frontend structure.
23	*	23	*
24	* @fe: Frontend to attach to.	24	* @fe: Frontend to attach to.
25	* @config: zl10036_config structure.	25	* @config: zl10036_config structure.

drivers/media/i2c/Kconfig+30−2

 config VIDEO_APTINA_PLL
 	tristate
-config VIDEO_SMIAPP_PLL
+config VIDEO_CCS_PLL
 	tristate
 config VIDEO_HI556
 	  To compile this driver as a module, choose M here: the
 	  module will be called imx355.
+config VIDEO_OV02A10
+	tristate "OmniVision OV02A10 sensor support"
+	depends on VIDEO_V4L2 && I2C
+	select MEDIA_CONTROLLER
+	select VIDEO_V4L2_SUBDEV_API
+	select V4L2_FWNODE
+	help
+	  This is a Video4Linux2 sensor driver for the OmniVision
+	  OV02A10 camera.
+	  To compile this driver as a module, choose M here: the
+	  module will be called ov02a10.
 config VIDEO_OV2640
 	tristate "OmniVision OV2640 sensor support"
 	depends on VIDEO_V4L2 && I2C
 	select MEDIA_CONTROLLER
 	select VIDEO_V4L2_SUBDEV_API
 	select V4L2_FWNODE
+	select REGMAP_I2C
 	help
 	  This is a Video4Linux2 sensor driver for the OmniVision
 	  OV2740 camera.
 	  This is a V4L2 sensor driver for the Omnivision
 	  OV9650 and OV9652 camera sensors.
+config VIDEO_OV9734
+	tristate "OmniVision OV9734 sensor support"
+	depends on VIDEO_V4L2 && I2C
+	depends on ACPI || COMPILE_TEST
+	select MEDIA_CONTROLLER
+	select VIDEO_V4L2_SUBDEV_API
+	select V4L2_FWNODE
+	help
+	  This is a Video4Linux2 sensor driver for the OmniVision
+	  OV9734 camera.
+	  To compile this driver as a module, choose M here: the
+	  module's name is ov9734.
 config VIDEO_OV13858
 	tristate "OmniVision OV13858 sensor support"
 	depends on I2C && VIDEO_V4L2
 	  This is a V4L2 sensor driver for Samsung S5K5BAF 2M
 	  camera sensor with an embedded SoC image signal processor.
-source "drivers/media/i2c/smiapp/Kconfig"
+source "drivers/media/i2c/ccs/Kconfig"
 source "drivers/media/i2c/et8ek8/Kconfig"
 config VIDEO_S5C73M3

drivers/media/i2c/Makefile+4−2

 msp3400-objs	:=	msp3400-driver.o msp3400-kthreads.o
 obj-$(CONFIG_VIDEO_MSP3400) += msp3400.o
-obj-$(CONFIG_VIDEO_SMIAPP)	+= smiapp/
+obj-$(CONFIG_VIDEO_CCS)		+= ccs/
 obj-$(CONFIG_VIDEO_ET8EK8)	+= et8ek8/
 obj-$(CONFIG_VIDEO_CX25840) += cx25840/
 obj-$(CONFIG_VIDEO_M5MOLS)	+= m5mols/
 obj-$(CONFIG_VIDEO_SONY_BTF_MPX) += sony-btf-mpx.o
 obj-$(CONFIG_VIDEO_UPD64031A) += upd64031a.o
 obj-$(CONFIG_VIDEO_UPD64083) += upd64083.o
+obj-$(CONFIG_VIDEO_OV02A10) += ov02a10.o
 obj-$(CONFIG_VIDEO_OV2640) += ov2640.o
 obj-$(CONFIG_VIDEO_OV2680) += ov2680.o
 obj-$(CONFIG_VIDEO_OV2685) += ov2685.o
 obj-$(CONFIG_VIDEO_OV8856) += ov8856.o
 obj-$(CONFIG_VIDEO_OV9640) += ov9640.o
 obj-$(CONFIG_VIDEO_OV9650) += ov9650.o
+obj-$(CONFIG_VIDEO_OV9734) += ov9734.o
 obj-$(CONFIG_VIDEO_OV13858) += ov13858.o
 obj-$(CONFIG_VIDEO_MT9M001) += mt9m001.o
 obj-$(CONFIG_VIDEO_MT9M032) += mt9m032.o
 obj-$(CONFIG_VIDEO_ADP1653)	+= adp1653.o
 obj-$(CONFIG_VIDEO_LM3560)	+= lm3560.o
 obj-$(CONFIG_VIDEO_LM3646)	+= lm3646.o
-obj-$(CONFIG_VIDEO_SMIAPP_PLL)	+= smiapp-pll.o
+obj-$(CONFIG_VIDEO_CCS_PLL)	+= ccs-pll.o
 obj-$(CONFIG_VIDEO_AK881X)		+= ak881x.o
 obj-$(CONFIG_VIDEO_IR_I2C)  += ir-kbd-i2c.o
 obj-$(CONFIG_VIDEO_I2C)		+= video-i2c.o

drivers/media/i2c/ad5820.c+2−4

  */
 static int __maybe_unused ad5820_suspend(struct device *dev)
 {
-	struct i2c_client *client = container_of(dev, struct i2c_client, dev);
+	struct v4l2_subdev *subdev = dev_get_drvdata(dev);
-	struct v4l2_subdev *subdev = i2c_get_clientdata(client);
 	struct ad5820_device *coil = to_ad5820_device(subdev);
 	if (!coil->power_count)
 static int __maybe_unused ad5820_resume(struct device *dev)
 {
-	struct i2c_client *client = container_of(dev, struct i2c_client, dev);
+	struct v4l2_subdev *subdev = dev_get_drvdata(dev);
-	struct v4l2_subdev *subdev = i2c_get_clientdata(client);
 	struct ad5820_device *coil = to_ad5820_device(subdev);
 	if (!coil->power_count)

drivers/media/i2c/adp1653.c+2−4

 static int adp1653_suspend(struct device *dev)
 {
-	struct i2c_client *client = to_i2c_client(dev);
+	struct v4l2_subdev *subdev = dev_get_drvdata(dev);
-	struct v4l2_subdev *subdev = i2c_get_clientdata(client);
 	struct adp1653_flash *flash = to_adp1653_flash(subdev);
 	if (!flash->power_count)
 static int adp1653_resume(struct device *dev)
 {
-	struct i2c_client *client = to_i2c_client(dev);
+	struct v4l2_subdev *subdev = dev_get_drvdata(dev);
-	struct v4l2_subdev *subdev = i2c_get_clientdata(client);
 	struct adp1653_flash *flash = to_adp1653_flash(subdev);
 	if (!flash->power_count)

drivers/media/i2c/adv7180.c+2−4

 #ifdef CONFIG_PM_SLEEP
 static int adv7180_suspend(struct device *dev)
 {
-	struct i2c_client *client = to_i2c_client(dev);
+	struct v4l2_subdev *sd = dev_get_drvdata(dev);
-	struct v4l2_subdev *sd = i2c_get_clientdata(client);
 	struct adv7180_state *state = to_state(sd);
 	return adv7180_set_power(state, false);
 static int adv7180_resume(struct device *dev)
 {
-	struct i2c_client *client = to_i2c_client(dev);
+	struct v4l2_subdev *sd = dev_get_drvdata(dev);
-	struct v4l2_subdev *sd = i2c_get_clientdata(client);
 	struct adv7180_state *state = to_state(sd);
 	int ret;

drivers/media/i2c/adv748x/adv748x-afe.c+1−5

 		   (sdpstd & 0xf) << ADV748X_SDP_VID_SEL_SHIFT);
 }
-static int adv748x_afe_s_input(struct adv748x_afe *afe, unsigned int input)
+int adv748x_afe_s_input(struct adv748x_afe *afe, unsigned int input)
 {
 	struct adv748x_state *state = adv748x_afe_to_state(afe);
 		}
 	}
-	adv748x_afe_s_input(afe, afe->input);
-	adv_dbg(state, "AFE Default input set to %d\n", afe->input);
 	/* Entity pads and sinks are 0-indexed to match the pads */
 	for (i = ADV748X_AFE_SINK_AIN0; i <= ADV748X_AFE_SINK_AIN7; i++)
 		afe->pads[i].flags = MEDIA_PAD_FL_SINK;

drivers/media/i2c/adv748x/adv748x-core.c+29−5

 			return ret;
 	}
-	return adv748x_set_slave_addresses(state);
+	return 0;
 }
 /**
 	if (ret)
 		return ret;
+	adv748x_afe_s_input(&state->afe, state->afe.input);
+	adv_dbg(state, "AFE Default input set to %d\n", state->afe.input);
 	/* Reset TXA and TXB */
 	adv748x_tx_power(&state->txa, 1);
 	adv748x_tx_power(&state->txa, 0);
 	io_write(state, ADV748X_IO_PD, ADV748X_IO_PD_RX_EN);
 	/* Conditionally enable TXa and TXb. */
-	if (is_tx_enabled(&state->txa))
+	if (is_tx_enabled(&state->txa)) {
 		regval |= ADV748X_IO_10_CSI4_EN;
-	if (is_tx_enabled(&state->txb))
+		adv748x_csi2_set_virtual_channel(&state->txa, 0);
+	}
+	if (is_tx_enabled(&state->txb)) {
 		regval |= ADV748X_IO_10_CSI1_EN;
+		adv748x_csi2_set_virtual_channel(&state->txb, 0);
+	}
 	io_write(state, ADV748X_IO_10, regval);
 	/* Use vid_std and v_freq as freerun resolution for CP */
 	return 0;
 }
+/* -----------------------------------------------------------------------------
+ * Suspend / Resume
+ */
+static int __maybe_unused adv748x_resume_early(struct device *dev)
+{
+	struct i2c_client *client = to_i2c_client(dev);
+	struct adv748x_state *state = i2c_get_clientdata(client);
+	return adv748x_reset(state);
+}
 /* -----------------------------------------------------------------------------
  * i2c driver
  */
 				    unsigned int port,
 				    struct device_node *ep)
 {
-	struct v4l2_fwnode_endpoint vep;
+	struct v4l2_fwnode_endpoint vep = { .bus_type = V4L2_MBUS_CSI2_DPHY };
 	unsigned int num_lanes;
 	int ret;
 	if (port != ADV748X_PORT_TXA && port != ADV748X_PORT_TXB)
 		return 0;
-	vep.bus_type = V4L2_MBUS_CSI2_DPHY;
 	ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep), &vep);
 	if (ret)
 		return ret;
 };
 MODULE_DEVICE_TABLE(of, adv748x_of_table);
+static const struct dev_pm_ops adv748x_pm_ops = {
+	SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, adv748x_resume_early)
+};
 static struct i2c_driver adv748x_driver = {
 	.driver = {
 		.name = "adv748x",
 		.of_match_table = adv748x_of_table,
+		.pm = &adv748x_pm_ops,
 	},
 	.probe_new = adv748x_probe,
 	.remove = adv748x_remove,

drivers/media/i2c/adv748x/adv748x-csi2.c+1−5

 #include "adv748x.h"
-static int adv748x_csi2_set_virtual_channel(struct adv748x_csi2 *tx,
+int adv748x_csi2_set_virtual_channel(struct adv748x_csi2 *tx, unsigned int vc)
-					    unsigned int vc)
 {
 	return tx_write(tx, ADV748X_CSI_VC_REF, vc << ADV748X_CSI_VC_REF_SHIFT);
 }
 	if (!is_tx_enabled(tx))
 		return 0;
-	/* Initialise the virtual channel */
-	adv748x_csi2_set_virtual_channel(tx, 0);
 	adv748x_subdev_init(&tx->sd, state, &adv748x_csi2_ops,
 			    MEDIA_ENT_F_VID_IF_BRIDGE,
 			    is_txa(tx) ? "txa" : "txb");

drivers/media/i2c/adv748x/adv748x.h+2−0

 int adv748x_afe_init(struct adv748x_afe *afe);
 void adv748x_afe_cleanup(struct adv748x_afe *afe);
+int adv748x_afe_s_input(struct adv748x_afe *afe, unsigned int input);
 int adv748x_csi2_init(struct adv748x_state *state, struct adv748x_csi2 *tx);
 void adv748x_csi2_cleanup(struct adv748x_csi2 *tx);
+int adv748x_csi2_set_virtual_channel(struct adv748x_csi2 *tx, unsigned int vc);
 int adv748x_csi2_set_pixelrate(struct v4l2_subdev *sd, s64 rate);
 int adv748x_hdmi_init(struct adv748x_hdmi *hdmi);

drivers/media/i2c/ak7375.c+2−5

@@ -196,9 +196,7 @@ static int ak7375_remove(struct i2c_client *client) · 195 unmodified lines
196	*/	196	*/
197	static int __maybe_unused ak7375_vcm_suspend(struct device *dev)	197	static int __maybe_unused ak7375_vcm_suspend(struct device *dev)
198	{	198	{
199		199	struct v4l2_subdev *sd = dev_get_drvdata(dev);
200	struct i2c_client *client = to_i2c_client(dev);
201	struct v4l2_subdev *sd = i2c_get_clientdata(client);
202	struct ak7375_device *ak7375_dev = sd_to_ak7375_vcm(sd);	200	struct ak7375_device *ak7375_dev = sd_to_ak7375_vcm(sd);
203	int ret, val;	201	int ret, val;
204		202
@@ -233,8 +231,7 @@ static int __maybe_unused ak7375_vcm_suspend(struct device *dev) · 28 unmodified lines
233	*/	231	*/
234	static int __maybe_unused ak7375_vcm_resume(struct device *dev)	232	static int __maybe_unused ak7375_vcm_resume(struct device *dev)
235	{	233	{
236	struct i2c_client *client = to_i2c_client(dev);	234	struct v4l2_subdev *sd = dev_get_drvdata(dev);
237	struct v4l2_subdev *sd = i2c_get_clientdata(client);
238	struct ak7375_device *ak7375_dev = sd_to_ak7375_vcm(sd);	235	struct ak7375_device *ak7375_dev = sd_to_ak7375_vcm(sd);
239	int ret, val;	236	int ret, val;
240		237

drivers/media/i2c/ccs-pll.c+886−0

@@ -0,0 +1,886 @@
	1	// SPDX-License-Identifier: GPL-2.0-only
	2	/*
	3	* drivers/media/i2c/ccs-pll.c
	4	*
	5	* Generic MIPI CCS/SMIA/SMIA++ PLL calculator
	6	*
	7	* Copyright (C) 2020 Intel Corporation
	8	* Copyright (C) 2011--2012 Nokia Corporation
	9	* Contact: Sakari Ailus <sakari.ailus@linux.intel.com>
	10	*/
	11
	12	#include <linux/device.h>
	13	#include <linux/gcd.h>
	14	#include <linux/lcm.h>
	15	#include <linux/module.h>
	16
	17	#include "ccs-pll.h"
	18
	19	/* Return an even number or one. */
	20	static inline uint32_t clk_div_even(uint32_t a)
	21	{
	22	return max_t(uint32_t, 1, a & ~1);
	23	}
	24
	25	/* Return an even number or one. */
	26	static inline uint32_t clk_div_even_up(uint32_t a)
	27	{
	28	if (a == 1)
	29	return 1;
	30	return (a + 1) & ~1;
	31	}
	32
	33	static inline uint32_t is_one_or_even(uint32_t a)
	34	{
	35	if (a == 1)
	36	return 1;
	37	if (a & 1)
	38	return 0;
	39
	40	return 1;
	41	}
	42
	43	static inline uint32_t one_or_more(uint32_t a)
	44	{
	45	return a ?: 1;
	46	}
	47
	48	static int bounds_check(struct device *dev, uint32_t val,
	49	uint32_t min, uint32_t max, const char *prefix,
	50	char *str)
	51	{
	52	if (val >= min && val <= max)
	53	return 0;
	54
	55	dev_dbg(dev, "%s_%s out of bounds: %d (%d--%d)\n", prefix,
	56	str, val, min, max);
	57
	58	return -EINVAL;
	59	}
	60
	61	#define PLL_OP 1
	62	#define PLL_VT 2
	63
	64	static const char *pll_string(unsigned int which)
	65	{
	66	switch (which) {
	67	case PLL_OP:
	68	return "op";
	69	case PLL_VT:
	70	return "vt";
	71	}
	72
	73	return NULL;
	74	}
	75
	76	#define PLL_FL(f) CCS_PLL_FLAG_##f
	77
	78	static void print_pll(struct device dev, struct ccs_pll pll)
	79	{
	80	const struct {
	81	struct ccs_pll_branch_fr *fr;
	82	struct ccs_pll_branch_bk *bk;
	83	unsigned int which;
	84	} branches[] = {
	85	{ &pll->vt_fr, &pll->vt_bk, PLL_VT },
	86	{ &pll->op_fr, &pll->op_bk, PLL_OP }
	87	}, *br;
	88	unsigned int i;
	89
	90	dev_dbg(dev, "ext_clk_freq_hz\t\t%u\n", pll->ext_clk_freq_hz);
	91
	92	for (i = 0, br = branches; i < ARRAY_SIZE(branches); i++, br++) {
	93	const char *s = pll_string(br->which);
	94
	95	if (pll->flags & CCS_PLL_FLAG_DUAL_PLL \|\|
	96	br->which == PLL_VT) {
	97	dev_dbg(dev, "%s_pre_pll_clk_div\t\t%u\n", s,
	98	br->fr->pre_pll_clk_div);
	99	dev_dbg(dev, "%s_pll_multiplier\t\t%u\n", s,
	100	br->fr->pll_multiplier);
	101
	102	dev_dbg(dev, "%s_pll_ip_clk_freq_hz\t%u\n", s,
	103	br->fr->pll_ip_clk_freq_hz);
	104	dev_dbg(dev, "%s_pll_op_clk_freq_hz\t%u\n", s,
	105	br->fr->pll_op_clk_freq_hz);
	106	}
	107
	108	if (!(pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) \|\|
	109	br->which == PLL_VT) {
	110	dev_dbg(dev, "%s_sys_clk_div\t\t%u\n", s,
	111	br->bk->sys_clk_div);
	112	dev_dbg(dev, "%s_pix_clk_div\t\t%u\n", s,
	113	br->bk->pix_clk_div);
	114
	115	dev_dbg(dev, "%s_sys_clk_freq_hz\t%u\n", s,
	116	br->bk->sys_clk_freq_hz);
	117	dev_dbg(dev, "%s_pix_clk_freq_hz\t%u\n", s,
	118	br->bk->pix_clk_freq_hz);
	119	}
	120	}
	121
	122	dev_dbg(dev, "pixel rate in pixel array:\t%u\n",
	123	pll->pixel_rate_pixel_array);
	124	dev_dbg(dev, "pixel rate on CSI-2 bus:\t%u\n",
	125	pll->pixel_rate_csi);
	126
	127	dev_dbg(dev, "flags%s%s%s%s%s%s%s%s%s\n",
	128	pll->flags & PLL_FL(LANE_SPEED_MODEL) ? " lane-speed" : "",
	129	pll->flags & PLL_FL(LINK_DECOUPLED) ? " link-decoupled" : "",
	130	pll->flags & PLL_FL(EXT_IP_PLL_DIVIDER) ?
	131	" ext-ip-pll-divider" : "",
	132	pll->flags & PLL_FL(FLEXIBLE_OP_PIX_CLK_DIV) ?
	133	" flexible-op-pix-div" : "",
	134	pll->flags & PLL_FL(FIFO_DERATING) ? " fifo-derating" : "",
	135	pll->flags & PLL_FL(FIFO_OVERRATING) ? " fifo-overrating" : "",
	136	pll->flags & PLL_FL(DUAL_PLL) ? " dual-pll" : "",
	137	pll->flags & PLL_FL(OP_SYS_DDR) ? " op-sys-ddr" : "",
	138	pll->flags & PLL_FL(OP_PIX_DDR) ? " op-pix-ddr" : "");
	139	}
	140
	141	static uint32_t op_sys_ddr(uint32_t flags)
	142	{
	143	return flags & CCS_PLL_FLAG_OP_SYS_DDR ? 1 : 0;
	144	}
	145
	146	static uint32_t op_pix_ddr(uint32_t flags)
	147	{
	148	return flags & CCS_PLL_FLAG_OP_PIX_DDR ? 1 : 0;
	149	}
	150
	151	static int check_fr_bounds(struct device *dev,
	152	const struct ccs_pll_limits *lim,
	153	struct ccs_pll *pll, unsigned int which)
	154	{
	155	const struct ccs_pll_branch_limits_fr *lim_fr;
	156	struct ccs_pll_branch_fr *pll_fr;
	157	const char *s = pll_string(which);
	158	int rval;
	159
	160	if (which == PLL_OP) {
	161	lim_fr = &lim->op_fr;
	162	pll_fr = &pll->op_fr;
	163	} else {
	164	lim_fr = &lim->vt_fr;
	165	pll_fr = &pll->vt_fr;
	166	}
	167
	168	rval = bounds_check(dev, pll_fr->pre_pll_clk_div,
	169	lim_fr->min_pre_pll_clk_div,
	170	lim_fr->max_pre_pll_clk_div, s, "pre_pll_clk_div");
	171
	172	if (!rval)
	173	rval = bounds_check(dev, pll_fr->pll_ip_clk_freq_hz,
	174	lim_fr->min_pll_ip_clk_freq_hz,
	175	lim_fr->max_pll_ip_clk_freq_hz,
	176	s, "pll_ip_clk_freq_hz");
	177	if (!rval)
	178	rval = bounds_check(dev, pll_fr->pll_multiplier,
	179	lim_fr->min_pll_multiplier,
	180	lim_fr->max_pll_multiplier,
	181	s, "pll_multiplier");
	182	if (!rval)
	183	rval = bounds_check(dev, pll_fr->pll_op_clk_freq_hz,
	184	lim_fr->min_pll_op_clk_freq_hz,
	185	lim_fr->max_pll_op_clk_freq_hz,
	186	s, "pll_op_clk_freq_hz");
	187
	188	return rval;
	189	}
	190
	191	static int check_bk_bounds(struct device *dev,
	192	const struct ccs_pll_limits *lim,
	193	struct ccs_pll *pll, unsigned int which)
	194	{
	195	const struct ccs_pll_branch_limits_bk *lim_bk;
	196	struct ccs_pll_branch_bk *pll_bk;
	197	const char *s = pll_string(which);
	198	int rval;
	199
	200	if (which == PLL_OP) {
	201	if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS)
	202	return 0;
	203
	204	lim_bk = &lim->op_bk;
	205	pll_bk = &pll->op_bk;
	206	} else {
	207	lim_bk = &lim->vt_bk;
	208	pll_bk = &pll->vt_bk;
	209	}
	210
	211	rval = bounds_check(dev, pll_bk->sys_clk_div,
	212	lim_bk->min_sys_clk_div,
	213	lim_bk->max_sys_clk_div, s, "op_sys_clk_div");
	214	if (!rval)
	215	rval = bounds_check(dev, pll_bk->sys_clk_freq_hz,
	216	lim_bk->min_sys_clk_freq_hz,
	217	lim_bk->max_sys_clk_freq_hz,
	218	s, "sys_clk_freq_hz");
	219	if (!rval)
	220	rval = bounds_check(dev, pll_bk->sys_clk_div,
	221	lim_bk->min_sys_clk_div,
	222	lim_bk->max_sys_clk_div,
	223	s, "sys_clk_div");
	224	if (!rval)
	225	rval = bounds_check(dev, pll_bk->pix_clk_freq_hz,
	226	lim_bk->min_pix_clk_freq_hz,
	227	lim_bk->max_pix_clk_freq_hz,
	228	s, "pix_clk_freq_hz");
	229
	230	return rval;
	231	}
	232
	233	static int check_ext_bounds(struct device dev, struct ccs_pll pll)
	234	{
	235	if (!(pll->flags & CCS_PLL_FLAG_FIFO_DERATING) &&
	236	pll->pixel_rate_pixel_array > pll->pixel_rate_csi) {
	237	dev_dbg(dev, "device does not support derating\n");
	238	return -EINVAL;
	239	}
	240
	241	if (!(pll->flags & CCS_PLL_FLAG_FIFO_OVERRATING) &&
	242	pll->pixel_rate_pixel_array < pll->pixel_rate_csi) {
	243	dev_dbg(dev, "device does not support overrating\n");
	244	return -EINVAL;
	245	}
	246
	247	return 0;
	248	}
	249
	250	static void
	251	ccs_pll_find_vt_sys_div(struct device dev, const struct ccs_pll_limits lim,
	252	struct ccs_pll pll, struct ccs_pll_branch_fr pll_fr,
	253	uint16_t min_vt_div, uint16_t max_vt_div,
	254	uint16_t min_sys_div, uint16_t max_sys_div)
	255	{
	256	/*
	257	* Find limits for sys_clk_div. Not all values are possible with all
	258	* values of pix_clk_div.
	259	*/
	260	*min_sys_div = lim->vt_bk.min_sys_clk_div;
	261	dev_dbg(dev, "min_sys_div: %u\n", *min_sys_div);
	262	min_sys_div = max_t(uint16_t, min_sys_div,
	263	DIV_ROUND_UP(min_vt_div,
	264	lim->vt_bk.max_pix_clk_div));
	265	dev_dbg(dev, "min_sys_div: max_vt_pix_clk_div: %u\n", *min_sys_div);
	266	min_sys_div = max_t(uint16_t, min_sys_div,
	267	pll_fr->pll_op_clk_freq_hz
	268	/ lim->vt_bk.max_sys_clk_freq_hz);
	269	dev_dbg(dev, "min_sys_div: max_pll_op_clk_freq_hz: %u\n", *min_sys_div);
	270	min_sys_div = clk_div_even_up(min_sys_div);
	271	dev_dbg(dev, "min_sys_div: one or even: %u\n", *min_sys_div);
	272
	273	*max_sys_div = lim->vt_bk.max_sys_clk_div;
	274	dev_dbg(dev, "max_sys_div: %u\n", *max_sys_div);
	275	max_sys_div = min_t(uint16_t, max_sys_div,
	276	DIV_ROUND_UP(max_vt_div,
	277	lim->vt_bk.min_pix_clk_div));
	278	dev_dbg(dev, "max_sys_div: min_vt_pix_clk_div: %u\n", *max_sys_div);
	279	max_sys_div = min_t(uint16_t, max_sys_div,
	280	DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz,
	281	lim->vt_bk.min_pix_clk_freq_hz));
	282	dev_dbg(dev, "max_sys_div: min_vt_pix_clk_freq_hz: %u\n", *max_sys_div);
	283	}
	284
	285	#define CPHY_CONST 7
	286	#define DPHY_CONST 16
	287	#define PHY_CONST_DIV 16
	288
	289	static inline int
	290	__ccs_pll_calculate_vt_tree(struct device *dev,
	291	const struct ccs_pll_limits *lim,
	292	struct ccs_pll *pll, uint32_t mul, uint32_t div)
	293	{
	294	const struct ccs_pll_branch_limits_fr *lim_fr = &lim->vt_fr;
	295	const struct ccs_pll_branch_limits_bk *lim_bk = &lim->vt_bk;
	296	struct ccs_pll_branch_fr *pll_fr = &pll->vt_fr;
	297	struct ccs_pll_branch_bk *pll_bk = &pll->vt_bk;
	298	uint32_t more_mul;
	299	uint16_t best_pix_div = SHRT_MAX >> 1, best_div;
	300	uint16_t vt_div, min_sys_div, max_sys_div, sys_div;
	301
	302	pll_fr->pll_ip_clk_freq_hz =
	303	pll->ext_clk_freq_hz / pll_fr->pre_pll_clk_div;
	304
	305	dev_dbg(dev, "vt_pll_ip_clk_freq_hz %u\n", pll_fr->pll_ip_clk_freq_hz);
	306
	307	more_mul = one_or_more(DIV_ROUND_UP(lim_fr->min_pll_op_clk_freq_hz,
	308	pll_fr->pll_ip_clk_freq_hz * mul));
	309
	310	dev_dbg(dev, "more_mul: %u\n", more_mul);
	311	more_mul = DIV_ROUND_UP(lim_fr->min_pll_multiplier, mul more_mul);
	312	dev_dbg(dev, "more_mul2: %u\n", more_mul);
	313
	314	pll_fr->pll_multiplier = mul * more_mul;
	315
	316	if (pll_fr->pll_multiplier * pll_fr->pll_ip_clk_freq_hz >
	317	lim_fr->max_pll_op_clk_freq_hz)
	318	return -EINVAL;
	319
	320	pll_fr->pll_op_clk_freq_hz =
	321	pll_fr->pll_ip_clk_freq_hz * pll_fr->pll_multiplier;
	322
	323	vt_div = div * more_mul;
	324
	325	ccs_pll_find_vt_sys_div(dev, lim, pll, pll_fr, vt_div, vt_div,
	326	&min_sys_div, &max_sys_div);
	327
	328	max_sys_div = (vt_div & 1) ? 1 : max_sys_div;
	329
	330	dev_dbg(dev, "vt min/max_sys_div: %u,%u\n", min_sys_div, max_sys_div);
	331
	332	for (sys_div = min_sys_div; sys_div <= max_sys_div;
	333	sys_div += 2 - (sys_div & 1)) {
	334	uint16_t pix_div;
	335
	336	if (vt_div % sys_div)
	337	continue;
	338
	339	pix_div = vt_div / sys_div;
	340
	341	if (pix_div < lim_bk->min_pix_clk_div \|\|
	342	pix_div > lim_bk->max_pix_clk_div) {
	343	dev_dbg(dev,
	344	"pix_div %u too small or too big (%u--%u)\n",
	345	pix_div,
	346	lim_bk->min_pix_clk_div,
	347	lim_bk->max_pix_clk_div);
	348	continue;
	349	}
	350
	351	dev_dbg(dev, "sys/pix/best_pix: %u,%u,%u\n", sys_div, pix_div,
	352	best_pix_div);
	353
	354	if (pix_div * sys_div <= best_pix_div) {
	355	best_pix_div = pix_div;
	356	best_div = pix_div * sys_div;
	357	}
	358	}
	359	if (best_pix_div == SHRT_MAX >> 1)
	360	return -EINVAL;
	361
	362	pll_bk->sys_clk_div = best_div / best_pix_div;
	363	pll_bk->pix_clk_div = best_pix_div;
	364
	365	pll_bk->sys_clk_freq_hz =
	366	pll_fr->pll_op_clk_freq_hz / pll_bk->sys_clk_div;
	367	pll_bk->pix_clk_freq_hz =
	368	pll_bk->sys_clk_freq_hz / pll_bk->pix_clk_div;
	369
	370	pll->pixel_rate_pixel_array =
	371	pll_bk->pix_clk_freq_hz * pll->vt_lanes;
	372
	373	return 0;
	374	}
	375
	376	static int ccs_pll_calculate_vt_tree(struct device *dev,
	377	const struct ccs_pll_limits *lim,
	378	struct ccs_pll *pll)
	379	{
	380	const struct ccs_pll_branch_limits_fr *lim_fr = &lim->vt_fr;
	381	struct ccs_pll_branch_fr *pll_fr = &pll->vt_fr;
	382	uint16_t min_pre_pll_clk_div = lim_fr->min_pre_pll_clk_div;
	383	uint16_t max_pre_pll_clk_div = lim_fr->max_pre_pll_clk_div;
	384	uint32_t pre_mul, pre_div;
	385
	386	pre_div = gcd(pll->pixel_rate_csi,
	387	pll->ext_clk_freq_hz * pll->vt_lanes);
	388	pre_mul = pll->pixel_rate_csi / pre_div;
	389	pre_div = pll->ext_clk_freq_hz * pll->vt_lanes / pre_div;
	390
	391	/* Make sure PLL input frequency is within limits */
	392	max_pre_pll_clk_div =
	393	min_t(uint16_t, max_pre_pll_clk_div,
	394	DIV_ROUND_UP(pll->ext_clk_freq_hz,
	395	lim_fr->min_pll_ip_clk_freq_hz));
	396
	397	min_pre_pll_clk_div = max_t(uint16_t, min_pre_pll_clk_div,
	398	pll->ext_clk_freq_hz /
	399	lim_fr->max_pll_ip_clk_freq_hz);
	400
	401	dev_dbg(dev, "vt min/max_pre_pll_clk_div: %u,%u\n",
	402	min_pre_pll_clk_div, max_pre_pll_clk_div);
	403
	404	for (pll_fr->pre_pll_clk_div = min_pre_pll_clk_div;
	405	pll_fr->pre_pll_clk_div <= max_pre_pll_clk_div;
	406	pll_fr->pre_pll_clk_div +=
	407	(pll->flags & CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER) ? 1 :
	408	2 - (pll_fr->pre_pll_clk_div & 1)) {
	409	uint32_t mul, div;
	410	int rval;
	411
	412	div = gcd(pre_mul * pll_fr->pre_pll_clk_div, pre_div);
	413	mul = pre_mul * pll_fr->pre_pll_clk_div / div;
	414	div = pre_div / div;
	415
	416	dev_dbg(dev, "vt pre-div/mul/div: %u,%u,%u\n",
	417	pll_fr->pre_pll_clk_div, mul, div);
	418
	419	rval = __ccs_pll_calculate_vt_tree(dev, lim, pll,
	420	mul, div);
	421	if (rval)
	422	continue;
	423
	424	rval = check_fr_bounds(dev, lim, pll, PLL_VT);
	425	if (rval)
	426	continue;
	427
	428	rval = check_bk_bounds(dev, lim, pll, PLL_VT);
	429	if (rval)
	430	continue;
	431
	432	return 0;
	433	}
	434
	435	return -EINVAL;
	436	}
	437
	438	static void
	439	ccs_pll_calculate_vt(struct device dev, const struct ccs_pll_limits lim,
	440	const struct ccs_pll_branch_limits_bk *op_lim_bk,
	441	struct ccs_pll pll, struct ccs_pll_branch_fr pll_fr,
	442	struct ccs_pll_branch_bk *op_pll_bk, bool cphy,
	443	uint32_t phy_const)
	444	{
	445	uint16_t sys_div;
	446	uint16_t best_pix_div = SHRT_MAX >> 1;
	447	uint16_t vt_op_binning_div;
	448	uint16_t min_vt_div, max_vt_div, vt_div;
	449	uint16_t min_sys_div, max_sys_div;
	450
	451	if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS)
	452	goto out_calc_pixel_rate;
	453
	454	/*
	455	* Find out whether a sensor supports derating. If it does not, VT and
	456	* OP domains are required to run at the same pixel rate.
	457	*/
	458	if (!(pll->flags & CCS_PLL_FLAG_FIFO_DERATING)) {
	459	min_vt_div =
	460	op_pll_bk->sys_clk_div * op_pll_bk->pix_clk_div
	461	* pll->vt_lanes * phy_const / pll->op_lanes
	462	/ (PHY_CONST_DIV << op_pix_ddr(pll->flags));
	463	} else {
	464	/*
	465	* Some sensors perform analogue binning and some do this
	466	* digitally. The ones doing this digitally can be roughly be
	467	* found out using this formula. The ones doing this digitally
	468	* should run at higher clock rate, so smaller divisor is used
	469	* on video timing side.
	470	*/
	471	if (lim->min_line_length_pck_bin > lim->min_line_length_pck
	472	/ pll->binning_horizontal)
	473	vt_op_binning_div = pll->binning_horizontal;
	474	else
	475	vt_op_binning_div = 1;
	476	dev_dbg(dev, "vt_op_binning_div: %u\n", vt_op_binning_div);
	477
	478	/*
	479	* Profile 2 supports vt_pix_clk_div E [4, 10]
	480	*
	481	* Horizontal binning can be used as a base for difference in
	482	* divisors. One must make sure that horizontal blanking is
	483	* enough to accommodate the CSI-2 sync codes.
	484	*
	485	* Take scaling factor and number of VT lanes into account as well.
	486	*
	487	* Find absolute limits for the factor of vt divider.
	488	*/
	489	dev_dbg(dev, "scale_m: %u\n", pll->scale_m);
	490	min_vt_div =
	491	DIV_ROUND_UP(pll->bits_per_pixel
	492	* op_pll_bk->sys_clk_div * pll->scale_n
	493	* pll->vt_lanes * phy_const,
	494	(pll->flags &
	495	CCS_PLL_FLAG_LANE_SPEED_MODEL ?
	496	pll->csi2.lanes : 1)
	497	* vt_op_binning_div * pll->scale_m
	498	* PHY_CONST_DIV << op_pix_ddr(pll->flags));
	499	}
	500
	501	/* Find smallest and biggest allowed vt divisor. */
	502	dev_dbg(dev, "min_vt_div: %u\n", min_vt_div);
	503	min_vt_div = max_t(uint16_t, min_vt_div,
	504	DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz,
	505	lim->vt_bk.max_pix_clk_freq_hz));
	506	dev_dbg(dev, "min_vt_div: max_vt_pix_clk_freq_hz: %u\n",
	507	min_vt_div);
	508	min_vt_div = max_t(uint16_t, min_vt_div, lim->vt_bk.min_pix_clk_div
	509	* lim->vt_bk.min_sys_clk_div);
	510	dev_dbg(dev, "min_vt_div: min_vt_clk_div: %u\n", min_vt_div);
	511
	512	max_vt_div = lim->vt_bk.max_sys_clk_div * lim->vt_bk.max_pix_clk_div;
	513	dev_dbg(dev, "max_vt_div: %u\n", max_vt_div);
	514	max_vt_div = min_t(uint16_t, max_vt_div,
	515	DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz,
	516	lim->vt_bk.min_pix_clk_freq_hz));
	517	dev_dbg(dev, "max_vt_div: min_vt_pix_clk_freq_hz: %u\n",
	518	max_vt_div);
	519
	520	ccs_pll_find_vt_sys_div(dev, lim, pll, pll_fr, min_vt_div,
	521	max_vt_div, &min_sys_div, &max_sys_div);
	522
	523	/*
	524	* Find pix_div such that a legal pix_div * sys_div results
	525	* into a value which is not smaller than div, the desired
	526	* divisor.
	527	*/
	528	for (vt_div = min_vt_div; vt_div <= max_vt_div; vt_div++) {
	529	uint16_t __max_sys_div = vt_div & 1 ? 1 : max_sys_div;
	530
	531	for (sys_div = min_sys_div; sys_div <= __max_sys_div;
	532	sys_div += 2 - (sys_div & 1)) {
	533	uint16_t pix_div;
	534	uint16_t rounded_div;
	535
	536	pix_div = DIV_ROUND_UP(vt_div, sys_div);
	537
	538	if (pix_div < lim->vt_bk.min_pix_clk_div
	539	\|\| pix_div > lim->vt_bk.max_pix_clk_div) {
	540	dev_dbg(dev,
	541	"pix_div %u too small or too big (%u--%u)\n",
	542	pix_div,
	543	lim->vt_bk.min_pix_clk_div,
	544	lim->vt_bk.max_pix_clk_div);
	545	continue;
	546	}
	547
	548	rounded_div = roundup(vt_div, best_pix_div);
	549
	550	/* Check if this one is better. */
	551	if (pix_div * sys_div <= rounded_div)
	552	best_pix_div = pix_div;
	553
	554	/* Bail out if we've already found the best value. */
	555	if (vt_div == rounded_div)
	556	break;
	557	}
	558	if (best_pix_div < SHRT_MAX >> 1)
	559	break;
	560	}
	561
	562	pll->vt_bk.sys_clk_div = DIV_ROUND_UP(vt_div, best_pix_div);
	563	pll->vt_bk.pix_clk_div = best_pix_div;
	564
	565	pll->vt_bk.sys_clk_freq_hz =
	566	pll_fr->pll_op_clk_freq_hz / pll->vt_bk.sys_clk_div;
	567	pll->vt_bk.pix_clk_freq_hz =
	568	pll->vt_bk.sys_clk_freq_hz / pll->vt_bk.pix_clk_div;
	569
	570	out_calc_pixel_rate:
	571	pll->pixel_rate_pixel_array =
	572	pll->vt_bk.pix_clk_freq_hz * pll->vt_lanes;
	573	}
	574
	575	/*
	576	* Heuristically guess the PLL tree for a given common multiplier and
	577	* divisor. Begin with the operational timing and continue to video
	578	* timing once operational timing has been verified.
	579	*
	580	* @mul is the PLL multiplier and @div is the common divisor
	581	* (pre_pll_clk_div and op_sys_clk_div combined). The final PLL
	582	* multiplier will be a multiple of @mul.
	583	*
	584	* @return Zero on success, error code on error.
	585	*/
	586	static int
	587	ccs_pll_calculate_op(struct device dev, const struct ccs_pll_limits lim,
	588	const struct ccs_pll_branch_limits_fr *op_lim_fr,
	589	const struct ccs_pll_branch_limits_bk *op_lim_bk,
	590	struct ccs_pll pll, struct ccs_pll_branch_fr op_pll_fr,
	591	struct ccs_pll_branch_bk *op_pll_bk, uint32_t mul,
	592	uint32_t div, uint32_t op_sys_clk_freq_hz_sdr, uint32_t l,
	593	bool cphy, uint32_t phy_const)
	594	{
	595	/*
	596	* Higher multipliers (and divisors) are often required than
	597	* necessitated by the external clock and the output clocks.
	598	* There are limits for all values in the clock tree. These
	599	* are the minimum and maximum multiplier for mul.
	600	*/
	601	uint32_t more_mul_min, more_mul_max;
	602	uint32_t more_mul_factor;
	603	uint32_t i;
	604
	605	/*
	606	* Get pre_pll_clk_div so that our pll_op_clk_freq_hz won't be
	607	* too high.
	608	*/
	609	dev_dbg(dev, "op_pre_pll_clk_div %u\n", op_pll_fr->pre_pll_clk_div);
	610
	611	/* Don't go above max pll multiplier. */
	612	more_mul_max = op_lim_fr->max_pll_multiplier / mul;
	613	dev_dbg(dev, "more_mul_max: max_op_pll_multiplier check: %u\n",
	614	more_mul_max);
	615	/* Don't go above max pll op frequency. */
	616	more_mul_max =
	617	min_t(uint32_t,
	618	more_mul_max,
	619	op_lim_fr->max_pll_op_clk_freq_hz
	620	/ (pll->ext_clk_freq_hz /
	621	op_pll_fr->pre_pll_clk_div * mul));
	622	dev_dbg(dev, "more_mul_max: max_pll_op_clk_freq_hz check: %u\n",
	623	more_mul_max);
	624	/* Don't go above the division capability of op sys clock divider. */
	625	more_mul_max = min(more_mul_max,
	626	op_lim_bk->max_sys_clk_div * op_pll_fr->pre_pll_clk_div
	627	/ div);
	628	dev_dbg(dev, "more_mul_max: max_op_sys_clk_div check: %u\n",
	629	more_mul_max);
	630	/* Ensure we won't go above max_pll_multiplier. */
	631	more_mul_max = min(more_mul_max, op_lim_fr->max_pll_multiplier / mul);
	632	dev_dbg(dev, "more_mul_max: min_pll_multiplier check: %u\n",
	633	more_mul_max);
	634
	635	/* Ensure we won't go below min_pll_op_clk_freq_hz. */
	636	more_mul_min = DIV_ROUND_UP(op_lim_fr->min_pll_op_clk_freq_hz,
	637	pll->ext_clk_freq_hz /
	638	op_pll_fr->pre_pll_clk_div * mul);
	639	dev_dbg(dev, "more_mul_min: min_op_pll_op_clk_freq_hz check: %u\n",
	640	more_mul_min);
	641	/* Ensure we won't go below min_pll_multiplier. */
	642	more_mul_min = max(more_mul_min,
	643	DIV_ROUND_UP(op_lim_fr->min_pll_multiplier, mul));
	644	dev_dbg(dev, "more_mul_min: min_op_pll_multiplier check: %u\n",
	645	more_mul_min);
	646
	647	if (more_mul_min > more_mul_max) {
	648	dev_dbg(dev,
	649	"unable to compute more_mul_min and more_mul_max\n");
	650	return -EINVAL;
	651	}
	652
	653	more_mul_factor = lcm(div, op_pll_fr->pre_pll_clk_div) / div;
	654	dev_dbg(dev, "more_mul_factor: %u\n", more_mul_factor);
	655	more_mul_factor = lcm(more_mul_factor, op_lim_bk->min_sys_clk_div);
	656	dev_dbg(dev, "more_mul_factor: min_op_sys_clk_div: %d\n",
	657	more_mul_factor);
	658	i = roundup(more_mul_min, more_mul_factor);
	659	if (!is_one_or_even(i))
	660	i <<= 1;
	661
	662	dev_dbg(dev, "final more_mul: %u\n", i);
	663	if (i > more_mul_max) {
	664	dev_dbg(dev, "final more_mul is bad, max %u\n", more_mul_max);
	665	return -EINVAL;
	666	}
	667
	668	op_pll_fr->pll_multiplier = mul * i;
	669	op_pll_bk->sys_clk_div = div * i / op_pll_fr->pre_pll_clk_div;
	670	dev_dbg(dev, "op_sys_clk_div: %u\n", op_pll_bk->sys_clk_div);
	671
	672	op_pll_fr->pll_ip_clk_freq_hz = pll->ext_clk_freq_hz
	673	/ op_pll_fr->pre_pll_clk_div;
	674
	675	op_pll_fr->pll_op_clk_freq_hz = op_pll_fr->pll_ip_clk_freq_hz
	676	* op_pll_fr->pll_multiplier;
	677
	678	if (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL)
	679	op_pll_bk->pix_clk_div =
	680	(pll->bits_per_pixel
	681	* pll->op_lanes * (phy_const << op_sys_ddr(pll->flags))
	682	/ PHY_CONST_DIV / pll->csi2.lanes / l)
	683	>> op_pix_ddr(pll->flags);
	684	else
	685	op_pll_bk->pix_clk_div =
	686	(pll->bits_per_pixel
	687	* (phy_const << op_sys_ddr(pll->flags))
	688	/ PHY_CONST_DIV / l) >> op_pix_ddr(pll->flags);
	689
	690	op_pll_bk->pix_clk_freq_hz =
	691	(op_sys_clk_freq_hz_sdr >> op_pix_ddr(pll->flags))
	692	/ op_pll_bk->pix_clk_div;
	693	op_pll_bk->sys_clk_freq_hz =
	694	op_sys_clk_freq_hz_sdr >> op_sys_ddr(pll->flags);
	695
	696	dev_dbg(dev, "op_pix_clk_div: %u\n", op_pll_bk->pix_clk_div);
	697
	698	return 0;
	699	}
	700
	701	int ccs_pll_calculate(struct device dev, const struct ccs_pll_limits lim,
	702	struct ccs_pll *pll)
	703	{
	704	const struct ccs_pll_branch_limits_fr *op_lim_fr;
	705	const struct ccs_pll_branch_limits_bk *op_lim_bk;
	706	struct ccs_pll_branch_fr *op_pll_fr;
	707	struct ccs_pll_branch_bk *op_pll_bk;
	708	bool cphy = pll->bus_type == CCS_PLL_BUS_TYPE_CSI2_CPHY;
	709	uint32_t phy_const = cphy ? CPHY_CONST : DPHY_CONST;
	710	uint32_t op_sys_clk_freq_hz_sdr;
	711	uint16_t min_op_pre_pll_clk_div;
	712	uint16_t max_op_pre_pll_clk_div;
	713	uint32_t mul, div;
	714	uint32_t l = (!pll->op_bits_per_lane \|\|
	715	pll->op_bits_per_lane >= pll->bits_per_pixel) ? 1 : 2;
	716	uint32_t i;
	717	int rval = -EINVAL;
	718
	719	if (!(pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL)) {
	720	pll->op_lanes = 1;
	721	pll->vt_lanes = 1;
	722	}
	723
	724	if (pll->flags & CCS_PLL_FLAG_DUAL_PLL) {
	725	op_lim_fr = &lim->op_fr;
	726	op_lim_bk = &lim->op_bk;
	727	op_pll_fr = &pll->op_fr;
	728	op_pll_bk = &pll->op_bk;
	729	} else if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) {
	730	/*
	731	* If there's no OP PLL at all, use the VT values
	732	* instead. The OP values are ignored for the rest of
	733	* the PLL calculation.
	734	*/
	735	op_lim_fr = &lim->vt_fr;
	736	op_lim_bk = &lim->vt_bk;
	737	op_pll_fr = &pll->vt_fr;
	738	op_pll_bk = &pll->vt_bk;
	739	} else {
	740	op_lim_fr = &lim->vt_fr;
	741	op_lim_bk = &lim->op_bk;
	742	op_pll_fr = &pll->vt_fr;
	743	op_pll_bk = &pll->op_bk;
	744	}
	745
	746	if (!pll->op_lanes \|\| !pll->vt_lanes \|\| !pll->bits_per_pixel \|\|
	747	!pll->ext_clk_freq_hz \|\| !pll->link_freq \|\| !pll->scale_m \|\|
	748	!op_lim_fr->min_pll_ip_clk_freq_hz \|\|
	749	!op_lim_fr->max_pll_ip_clk_freq_hz \|\|
	750	!op_lim_fr->min_pll_op_clk_freq_hz \|\|
	751	!op_lim_fr->max_pll_op_clk_freq_hz \|\|
	752	!op_lim_bk->max_sys_clk_div \|\| !op_lim_fr->max_pll_multiplier)
	753	return -EINVAL;
	754
	755	/*
	756	* Make sure op_pix_clk_div will be integer --- unless flexible
	757	* op_pix_clk_div is supported
	758	*/
	759	if (!(pll->flags & CCS_PLL_FLAG_FLEXIBLE_OP_PIX_CLK_DIV) &&
	760	(pll->bits_per_pixel * pll->op_lanes) %
	761	(pll->csi2.lanes * l << op_pix_ddr(pll->flags))) {
	762	dev_dbg(dev, "op_pix_clk_div not an integer (bpp %u, op lanes %u, lanes %u, l %u)\n",
	763	pll->bits_per_pixel, pll->op_lanes, pll->csi2.lanes, l);
	764	return -EINVAL;
	765	}
	766
	767	dev_dbg(dev, "vt_lanes: %u\n", pll->vt_lanes);
	768	dev_dbg(dev, "op_lanes: %u\n", pll->op_lanes);
	769
	770	dev_dbg(dev, "binning: %ux%u\n", pll->binning_horizontal,
	771	pll->binning_vertical);
	772
	773	switch (pll->bus_type) {
	774	case CCS_PLL_BUS_TYPE_CSI2_DPHY:
	775	/* CSI transfers 2 bits per clock per lane; thus times 2 */
	776	op_sys_clk_freq_hz_sdr = pll->link_freq * 2
	777	* (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ?
	778	1 : pll->csi2.lanes);
	779	break;
	780	case CCS_PLL_BUS_TYPE_CSI2_CPHY:
	781	op_sys_clk_freq_hz_sdr =
	782	pll->link_freq
	783	* (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ?
	784	1 : pll->csi2.lanes);
	785	break;
	786	default:
	787	return -EINVAL;
	788	}
	789
	790	pll->pixel_rate_csi =
	791	div_u64((uint64_t)op_sys_clk_freq_hz_sdr
	792	* (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ?
	793	pll->csi2.lanes : 1) * PHY_CONST_DIV,
	794	phy_const * pll->bits_per_pixel * l);
	795
	796	/* Figure out limits for OP pre-pll divider based on extclk */
	797	dev_dbg(dev, "min / max op_pre_pll_clk_div: %u / %u\n",
	798	op_lim_fr->min_pre_pll_clk_div, op_lim_fr->max_pre_pll_clk_div);
	799	max_op_pre_pll_clk_div =
	800	min_t(uint16_t, op_lim_fr->max_pre_pll_clk_div,
	801	clk_div_even(pll->ext_clk_freq_hz /
	802	op_lim_fr->min_pll_ip_clk_freq_hz));
	803	min_op_pre_pll_clk_div =
	804	max_t(uint16_t, op_lim_fr->min_pre_pll_clk_div,
	805	clk_div_even_up(
	806	DIV_ROUND_UP(pll->ext_clk_freq_hz,
	807	op_lim_fr->max_pll_ip_clk_freq_hz)));
	808	dev_dbg(dev, "pre-pll check: min / max op_pre_pll_clk_div: %u / %u\n",
	809	min_op_pre_pll_clk_div, max_op_pre_pll_clk_div);
	810
	811	i = gcd(op_sys_clk_freq_hz_sdr,
	812	pll->ext_clk_freq_hz << op_pix_ddr(pll->flags));
	813	mul = op_sys_clk_freq_hz_sdr / i;
	814	div = (pll->ext_clk_freq_hz << op_pix_ddr(pll->flags)) / i;
	815	dev_dbg(dev, "mul %u / div %u\n", mul, div);
	816
	817	min_op_pre_pll_clk_div =
	818	max_t(uint16_t, min_op_pre_pll_clk_div,
	819	clk_div_even_up(
	820	mul /
	821	one_or_more(
	822	DIV_ROUND_UP(op_lim_fr->max_pll_op_clk_freq_hz,
	823	pll->ext_clk_freq_hz))));
	824	dev_dbg(dev, "pll_op check: min / max op_pre_pll_clk_div: %u / %u\n",
	825	min_op_pre_pll_clk_div, max_op_pre_pll_clk_div);
	826
	827	for (op_pll_fr->pre_pll_clk_div = min_op_pre_pll_clk_div;
	828	op_pll_fr->pre_pll_clk_div <= max_op_pre_pll_clk_div;
	829	op_pll_fr->pre_pll_clk_div +=
	830	(pll->flags & CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER) ? 1 :
	831	2 - (op_pll_fr->pre_pll_clk_div & 1)) {
	832	rval = ccs_pll_calculate_op(dev, lim, op_lim_fr, op_lim_bk, pll,
	833	op_pll_fr, op_pll_bk, mul, div,
	834	op_sys_clk_freq_hz_sdr, l, cphy,
	835	phy_const);
	836	if (rval)
	837	continue;
	838
	839	rval = check_fr_bounds(dev, lim, pll,
	840	pll->flags & CCS_PLL_FLAG_DUAL_PLL ?
	841	PLL_OP : PLL_VT);
	842	if (rval)
	843	continue;
	844
	845	rval = check_bk_bounds(dev, lim, pll, PLL_OP);
	846	if (rval)
	847	continue;
	848
	849	if (pll->flags & CCS_PLL_FLAG_DUAL_PLL)
	850	break;
	851
	852	ccs_pll_calculate_vt(dev, lim, op_lim_bk, pll, op_pll_fr,
	853	op_pll_bk, cphy, phy_const);
	854
	855	rval = check_bk_bounds(dev, lim, pll, PLL_VT);
	856	if (rval)
	857	continue;
	858	rval = check_ext_bounds(dev, pll);
	859	if (rval)
	860	continue;
	861
	862	break;
	863	}
	864
	865	if (rval) {
	866	dev_dbg(dev, "unable to compute pre_pll divisor\n");
	867
	868	return rval;
	869	}
	870
	871	if (pll->flags & CCS_PLL_FLAG_DUAL_PLL) {
	872	rval = ccs_pll_calculate_vt_tree(dev, lim, pll);
	873
	874	if (rval)
	875	return rval;
	876	}
	877
	878	print_pll(dev, pll);
	879
	880	return 0;
	881	}
	882	EXPORT_SYMBOL_GPL(ccs_pll_calculate);
	883
	884	MODULE_AUTHOR("Sakari Ailus <sakari.ailus@linux.intel.com>");
	885	MODULE_DESCRIPTION("Generic MIPI CCS/SMIA/SMIA++ PLL calculator");
	886	MODULE_LICENSE("GPL v2");

drivers/media/i2c/ccs-pll.h+214−0

@@ -0,0 +1,214 @@
	1	/* SPDX-License-Identifier: GPL-2.0-only */
	2	/*
	3	* drivers/media/i2c/ccs-pll.h
	4	*
	5	* Generic MIPI CCS/SMIA/SMIA++ PLL calculator
	6	*
	7	* Copyright (C) 2020 Intel Corporation
	8	* Copyright (C) 2012 Nokia Corporation
	9	* Contact: Sakari Ailus <sakari.ailus@linux.intel.com>
	10	*/
	11
	12	#ifndef CCS_PLL_H
	13	#define CCS_PLL_H
	14
	15	#include <linux/bits.h>
	16
	17	/* CSI-2 or CCP-2 */
	18	#define CCS_PLL_BUS_TYPE_CSI2_DPHY 0x00
	19	#define CCS_PLL_BUS_TYPE_CSI2_CPHY 0x01
	20
	21	/* Old SMIA and implementation specific flags */
	22	/* op pix clock is for all lanes in total normally */
	23	#define CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE BIT(0)
	24	#define CCS_PLL_FLAG_NO_OP_CLOCKS BIT(1)
	25	/* CCS PLL flags */
	26	#define CCS_PLL_FLAG_LANE_SPEED_MODEL BIT(2)
	27	#define CCS_PLL_FLAG_LINK_DECOUPLED BIT(3)
	28	#define CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER BIT(4)
	29	#define CCS_PLL_FLAG_FLEXIBLE_OP_PIX_CLK_DIV BIT(5)
	30	#define CCS_PLL_FLAG_FIFO_DERATING BIT(6)
	31	#define CCS_PLL_FLAG_FIFO_OVERRATING BIT(7)
	32	#define CCS_PLL_FLAG_DUAL_PLL BIT(8)
	33	#define CCS_PLL_FLAG_OP_SYS_DDR BIT(9)
	34	#define CCS_PLL_FLAG_OP_PIX_DDR BIT(10)
	35
	36	/**
	37	* struct ccs_pll_branch_fr - CCS PLL configuration (front)
	38	*
	39	* A single branch front-end of the CCS PLL tree.
	40	*
	41	* @pre_pll_clk_div: Pre-PLL clock divisor
	42	* @pll_multiplier: PLL multiplier
	43	* @pll_ip_clk_freq_hz: PLL input clock frequency
	44	* @pll_op_clk_freq_hz: PLL output clock frequency
	45	*/
	46	struct ccs_pll_branch_fr {
	47	uint16_t pre_pll_clk_div;
	48	uint16_t pll_multiplier;
	49	uint32_t pll_ip_clk_freq_hz;
	50	uint32_t pll_op_clk_freq_hz;
	51	};
	52
	53	/**
	54	* struct ccs_pll_branch_bk - CCS PLL configuration (back)
	55	*
	56	* A single branch back-end of the CCS PLL tree.
	57	*
	58	* @sys_clk_div: System clock divider
	59	* @pix_clk_div: Pixel clock divider
	60	* @sys_clk_freq_hz: System clock frequency
	61	* @pix_clk_freq_hz: Pixel clock frequency
	62	*/
	63	struct ccs_pll_branch_bk {
	64	uint16_t sys_clk_div;
	65	uint16_t pix_clk_div;
	66	uint32_t sys_clk_freq_hz;
	67	uint32_t pix_clk_freq_hz;
	68	};
	69
	70	/**
	71	* struct ccs_pll - Full CCS PLL configuration
	72	*
	73	* All information required to calculate CCS PLL configuration.
	74	*
	75	* @bus_type: Type of the data bus, CCS_PLL_BUS_TYPE_* (input)
	76	* @op_lanes: Number of operational lanes (input)
	77	* @vt_lanes: Number of video timing lanes (input)
	78	* @csi2: CSI-2 related parameters
	79	* @csi2.lanes: The number of the CSI-2 data lanes (input)
	80	* @binning_vertical: Vertical binning factor (input)
	81	* @binning_horizontal: Horizontal binning factor (input)
	82	* @scale_m: Downscaling factor, M component, [16, max] (input)
	83	* @scale_n: Downscaling factor, N component, typically 16 (input)
	84	* @bits_per_pixel: Bits per pixel on the output data bus (input)
	85	* @op_bits_per_lane: Number of bits per OP lane (input)
	86	* @flags: CCS_PLL_FLAG_* (input)
	87	* @link_freq: Chosen link frequency (input)
	88	* @ext_clk_freq_hz: External clock frequency, i.e. the sensor's input clock
	89	* (input)
	90	* @vt_fr: Video timing front-end configuration (output)
	91	* @vt_bk: Video timing back-end configuration (output)
	92	* @op_fr: Operational timing front-end configuration (output)
	93	* @op_bk: Operational timing back-end configuration (output)
	94	* @pixel_rate_csi: Pixel rate on the output data bus (output)
	95	* @pixel_rate_pixel_array: Nominal pixel rate in the sensor's pixel array
	96	* (output)
	97	*/
	98	struct ccs_pll {
	99	/* input values */
	100	uint8_t bus_type;
	101	uint8_t op_lanes;
	102	uint8_t vt_lanes;
	103	struct {
	104	uint8_t lanes;
	105	} csi2;
	106	uint8_t binning_horizontal;
	107	uint8_t binning_vertical;
	108	uint8_t scale_m;
	109	uint8_t scale_n;
	110	uint8_t bits_per_pixel;
	111	uint8_t op_bits_per_lane;
	112	uint16_t flags;
	113	uint32_t link_freq;
	114	uint32_t ext_clk_freq_hz;
	115
	116	/* output values */
	117	struct ccs_pll_branch_fr vt_fr;
	118	struct ccs_pll_branch_bk vt_bk;
	119	struct ccs_pll_branch_fr op_fr;
	120	struct ccs_pll_branch_bk op_bk;
	121
	122	uint32_t pixel_rate_csi;
	123	uint32_t pixel_rate_pixel_array;
	124	};
	125
	126	/**
	127	* struct ccs_pll_branch_limits_fr - CCS PLL front-end limits
	128	*
	129	* @min_pre_pll_clk_div: Minimum pre-PLL clock divider
	130	* @max_pre_pll_clk_div: Maximum pre-PLL clock divider
	131	* @min_pll_ip_clk_freq_hz: Minimum PLL input clock frequency
	132	* @max_pll_ip_clk_freq_hz: Maximum PLL input clock frequency
	133	* @min_pll_multiplier: Minimum PLL multiplier
	134	* @max_pll_multiplier: Maximum PLL multiplier
	135	* @min_pll_op_clk_freq_hz: Minimum PLL output clock frequency
	136	* @max_pll_op_clk_freq_hz: Maximum PLL output clock frequency
	137	*/
	138	struct ccs_pll_branch_limits_fr {
	139	uint16_t min_pre_pll_clk_div;
	140	uint16_t max_pre_pll_clk_div;
	141	uint32_t min_pll_ip_clk_freq_hz;
	142	uint32_t max_pll_ip_clk_freq_hz;
	143	uint16_t min_pll_multiplier;
	144	uint16_t max_pll_multiplier;
	145	uint32_t min_pll_op_clk_freq_hz;
	146	uint32_t max_pll_op_clk_freq_hz;
	147	};
	148
	149	/**
	150	* struct ccs_pll_branch_limits_bk - CCS PLL back-end limits
	151	*
	152	* @min_sys_clk_div: Minimum system clock divider
	153	* @max_sys_clk_div: Maximum system clock divider
	154	* @min_sys_clk_freq_hz: Minimum system clock frequency
	155	* @max_sys_clk_freq_hz: Maximum system clock frequency
	156	* @min_pix_clk_div: Minimum pixel clock divider
	157	* @max_pix_clk_div: Maximum pixel clock divider
	158	* @min_pix_clk_freq_hz: Minimum pixel clock frequency
	159	* @max_pix_clk_freq_hz: Maximum pixel clock frequency
	160	*/
	161	struct ccs_pll_branch_limits_bk {
	162	uint16_t min_sys_clk_div;
	163	uint16_t max_sys_clk_div;
	164	uint32_t min_sys_clk_freq_hz;
	165	uint32_t max_sys_clk_freq_hz;
	166	uint16_t min_pix_clk_div;
	167	uint16_t max_pix_clk_div;
	168	uint32_t min_pix_clk_freq_hz;
	169	uint32_t max_pix_clk_freq_hz;
	170	};
	171
	172	/**
	173	* struct ccs_pll_limits - CCS PLL limits
	174	*
	175	* @min_ext_clk_freq_hz: Minimum external clock frequency
	176	* @max_ext_clk_freq_hz: Maximum external clock frequency
	177	* @vt_fr: Video timing front-end limits
	178	* @vt_bk: Video timing back-end limits
	179	* @op_fr: Operational timing front-end limits
	180	* @op_bk: Operational timing back-end limits
	181	* @min_line_length_pck_bin: Minimum line length in pixels, with binning
	182	* @min_line_length_pck: Minimum line length in pixels without binning
	183	*/
	184	struct ccs_pll_limits {
	185	/* Strict PLL limits */
	186	uint32_t min_ext_clk_freq_hz;
	187	uint32_t max_ext_clk_freq_hz;
	188
	189	struct ccs_pll_branch_limits_fr vt_fr;
	190	struct ccs_pll_branch_limits_bk vt_bk;
	191	struct ccs_pll_branch_limits_fr op_fr;
	192	struct ccs_pll_branch_limits_bk op_bk;
	193
	194	/* Other relevant limits */
	195	uint32_t min_line_length_pck_bin;
	196	uint32_t min_line_length_pck;
	197	};
	198
	199	struct device;
	200
	201	/**
	202	* ccs_pll_calculate - Calculate CCS PLL configuration based on input parameters
	203	*
	204	* @dev: Device pointer, used for printing messages
	205	* @limits: Limits specific to the sensor
	206	* @pll: Given PLL configuration
	207	*
	208	* Calculate the CCS PLL configuration based on the limits as well as given
	209	* device specific, system specific or user configured input data.
	210	*/
	211	int ccs_pll_calculate(struct device dev, const struct ccs_pll_limits limits,
	212	struct ccs_pll *pll);
	213
	214	#endif /* CCS_PLL_H */

drivers/media/i2c/ccs/Kconfig+11−0

@@ -0,0 +1,11 @@
	1	# SPDX-License-Identifier: GPL-2.0-only
	2	config VIDEO_CCS
	3	tristate "MIPI CCS/SMIA++/SMIA sensor support"
	4	depends on I2C && VIDEO_V4L2 && HAVE_CLK
	5	select MEDIA_CONTROLLER
	6	select VIDEO_V4L2_SUBDEV_API
	7	select VIDEO_CCS_PLL
	8	select V4L2_FWNODE
	9	help
	10	This is a generic driver for MIPI CCS, SMIA++ and SMIA compliant
	11	camera sensors.

drivers/media/i2c/ccs/Makefile+6−0

@@ -0,0 +1,6 @@
	1	# SPDX-License-Identifier: GPL-2.0-only
	2	ccs-objs += ccs-core.o ccs-reg-access.o \
	3	ccs-quirk.o ccs-limits.o ccs-data.o
	4	obj-$(CONFIG_VIDEO_CCS) += ccs.o
	5
	6	ccflags-y += -I $(srctree)/drivers/media/i2c

drivers/media/i2c/ccs/ccs-core.c+3479−0

@@ -0,0 +1,3479 @@
	1	// SPDX-License-Identifier: GPL-2.0-only
	2	/*
	3	* drivers/media/i2c/ccs/ccs-core.c
	4	*
	5	* Generic driver for MIPI CCS/SMIA/SMIA++ compliant camera sensors
	6	*
	7	* Copyright (C) 2020 Intel Corporation
	8	* Copyright (C) 2010--2012 Nokia Corporation
	9	* Contact: Sakari Ailus <sakari.ailus@linux.intel.com>
	10	*
	11	* Based on smiapp driver by Vimarsh Zutshi
	12	* Based on jt8ev1.c by Vimarsh Zutshi
	13	* Based on smia-sensor.c by Tuukka Toivonen <tuukkat76@gmail.com>
	14	*/
	15
	16	#include <linux/clk.h>
	17	#include <linux/delay.h>
	18	#include <linux/device.h>
	19	#include <linux/firmware.h>
	20	#include <linux/gpio.h>
	21	#include <linux/gpio/consumer.h>
	22	#include <linux/module.h>
	23	#include <linux/pm_runtime.h>
	24	#include <linux/property.h>
	25	#include <linux/regulator/consumer.h>
	26	#include <linux/slab.h>
	27	#include <linux/smiapp.h>
	28	#include <linux/v4l2-mediabus.h>
	29	#include <media/v4l2-fwnode.h>
	30	#include <media/v4l2-device.h>
	31
	32	#include "ccs.h"
	33
	34	#define CCS_ALIGN_DIM(dim, flags) \
	35	((flags) & V4L2_SEL_FLAG_GE \
	36	? ALIGN((dim), 2) \
	37	: (dim) & ~1)
	38
	39	static struct ccs_limit_offset {
	40	u16 lim;
	41	u16 info;
	42	} ccs_limit_offsets[CCS_L_LAST + 1];
	43
	44	/*
	45	* ccs_module_idents - supported camera modules
	46	*/
	47	static const struct ccs_module_ident ccs_module_idents[] = {
	48	CCS_IDENT_L(0x01, 0x022b, -1, "vs6555"),
	49	CCS_IDENT_L(0x01, 0x022e, -1, "vw6558"),
	50	CCS_IDENT_L(0x07, 0x7698, -1, "ovm7698"),
	51	CCS_IDENT_L(0x0b, 0x4242, -1, "smiapp-003"),
	52	CCS_IDENT_L(0x0c, 0x208a, -1, "tcm8330md"),
	53	CCS_IDENT_LQ(0x0c, 0x2134, -1, "tcm8500md", &smiapp_tcm8500md_quirk),
	54	CCS_IDENT_L(0x0c, 0x213e, -1, "et8en2"),
	55	CCS_IDENT_L(0x0c, 0x2184, -1, "tcm8580md"),
	56	CCS_IDENT_LQ(0x0c, 0x560f, -1, "jt8ew9", &smiapp_jt8ew9_quirk),
	57	CCS_IDENT_LQ(0x10, 0x4141, -1, "jt8ev1", &smiapp_jt8ev1_quirk),
	58	CCS_IDENT_LQ(0x10, 0x4241, -1, "imx125es", &smiapp_imx125es_quirk),
	59	};
	60
	61	#define CCS_DEVICE_FLAG_IS_SMIA BIT(0)
	62
	63	struct ccs_device {
	64	unsigned char flags;
	65	};
	66
	67	static const char * const ccs_regulators[] = { "vcore", "vio", "vana" };
	68
	69	/*
	70	*
	71	* Dynamic Capability Identification
	72	*
	73	*/
	74
	75	static void ccs_assign_limit(void *ptr, unsigned int width, u32 val)
	76	{
	77	switch (width) {
	78	case sizeof(u8):
	79	(u8 )ptr = val;
	80	break;
	81	case sizeof(u16):
	82	(u16 )ptr = val;
	83	break;
	84	case sizeof(u32):
	85	(u32 )ptr = val;
	86	break;
	87	}
	88	}
	89
	90	static int ccs_limit_ptr(struct ccs_sensor *sensor, unsigned int limit,
	91	unsigned int offset, void **__ptr)
	92	{
	93	const struct ccs_limit *linfo;
	94
	95	if (WARN_ON(limit >= CCS_L_LAST))
	96	return -EINVAL;
	97
	98	linfo = &ccs_limits[ccs_limit_offsets[limit].info];
	99
	100	if (WARN_ON(!sensor->ccs_limits) \|\|
	101	WARN_ON(offset + ccs_reg_width(linfo->reg) >
	102	ccs_limit_offsets[limit + 1].lim))
	103	return -EINVAL;
	104
	105	*__ptr = sensor->ccs_limits + ccs_limit_offsets[limit].lim + offset;
	106
	107	return 0;
	108	}
	109
	110	void ccs_replace_limit(struct ccs_sensor *sensor,
	111	unsigned int limit, unsigned int offset, u32 val)
	112	{
	113	struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
	114	const struct ccs_limit *linfo;
	115	void *ptr;
	116	int ret;
	117
	118	ret = ccs_limit_ptr(sensor, limit, offset, &ptr);
	119	if (ret)
	120	return;
	121
	122	linfo = &ccs_limits[ccs_limit_offsets[limit].info];
	123
	124	dev_dbg(&client->dev, "quirk: 0x%8.8x \"%s\" %u = %d, 0x%x\n",
	125	linfo->reg, linfo->name, offset, val, val);
	126
	127	ccs_assign_limit(ptr, ccs_reg_width(linfo->reg), val);
	128	}
	129
	130	u32 ccs_get_limit(struct ccs_sensor *sensor, unsigned int limit,
	131	unsigned int offset)
	132	{
	133	void *ptr;
	134	u32 val;
	135	int ret;
	136
	137	ret = ccs_limit_ptr(sensor, limit, offset, &ptr);
	138	if (ret)
	139	return 0;
	140
	141	switch (ccs_reg_width(ccs_limits[ccs_limit_offsets[limit].info].reg)) {
	142	case sizeof(u8):
	143	val = (u8 )ptr;
	144	break;
	145	case sizeof(u16):
	146	val = (u16 )ptr;
	147	break;
	148	case sizeof(u32):
	149	val = (u32 )ptr;
	150	break;
	151	default:
	152	WARN_ON(1);
	153	return 0;
	154	}
	155
	156	return ccs_reg_conv(sensor, ccs_limits[limit].reg, val);
	157	}
	158
	159	static int ccs_read_all_limits(struct ccs_sensor *sensor)
	160	{
	161	struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
	162	void ptr, alloc, *end;
	163	unsigned int i, l;
	164	int ret;
	165
	166	kfree(sensor->ccs_limits);
	167	sensor->ccs_limits = NULL;
	168
	169	alloc = kzalloc(ccs_limit_offsets[CCS_L_LAST].lim, GFP_KERNEL);
	170	if (!alloc)
	171	return -ENOMEM;
	172
	173	end = alloc + ccs_limit_offsets[CCS_L_LAST].lim;
	174
	175	for (i = 0, l = 0, ptr = alloc; ccs_limits[i].size; i++) {
	176	u32 reg = ccs_limits[i].reg;
	177	unsigned int width = ccs_reg_width(reg);
	178	unsigned int j;
	179
	180	if (l == CCS_L_LAST) {
	181	dev_err(&client->dev,
	182	"internal error --- end of limit array\n");
	183	ret = -EINVAL;
	184	goto out_err;
	185	}
	186
	187	for (j = 0; j < ccs_limits[i].size / width;
	188	j++, reg += width, ptr += width) {
	189	u32 val;
	190
	191	ret = ccs_read_addr_noconv(sensor, reg, &val);
	192	if (ret)
	193	goto out_err;
	194
	195	if (ptr + width > end) {
	196	dev_err(&client->dev,
	197	"internal error --- no room for regs\n");
	198	ret = -EINVAL;
	199	goto out_err;
	200	}
	201
	202	if (!val && j)
	203	break;
	204
	205	ccs_assign_limit(ptr, width, val);
	206
	207	dev_dbg(&client->dev, "0x%8.8x \"%s\" = %u, 0x%x\n",
	208	reg, ccs_limits[i].name, val, val);
	209	}
	210
	211	if (ccs_limits[i].flags & CCS_L_FL_SAME_REG)
	212	continue;
	213
	214	l++;
	215	ptr = alloc + ccs_limit_offsets[l].lim;
	216	}
	217
	218	if (l != CCS_L_LAST) {
	219	dev_err(&client->dev,
	220	"internal error --- insufficient limits\n");
	221	ret = -EINVAL;
	222	goto out_err;
	223	}
	224
	225	sensor->ccs_limits = alloc;
	226
	227	if (CCS_LIM(sensor, SCALER_N_MIN) < 16)
	228	ccs_replace_limit(sensor, CCS_L_SCALER_N_MIN, 0, 16);
	229
	230	return 0;
	231
	232	out_err:
	233	kfree(alloc);
	234
	235	return ret;
	236	}
	237
	238	static int ccs_read_frame_fmt(struct ccs_sensor *sensor)
	239	{
	240	struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
	241	u8 fmt_model_type, fmt_model_subtype, ncol_desc, nrow_desc;
	242	unsigned int i;
	243	int pixel_count = 0;
	244	int line_count = 0;
	245
	246	fmt_model_type = CCS_LIM(sensor, FRAME_FORMAT_MODEL_TYPE);
	247	fmt_model_subtype = CCS_LIM(sensor, FRAME_FORMAT_MODEL_SUBTYPE);
	248
	249	ncol_desc = (fmt_model_subtype
	250	& CCS_FRAME_FORMAT_MODEL_SUBTYPE_COLUMNS_MASK)
	251	>> CCS_FRAME_FORMAT_MODEL_SUBTYPE_COLUMNS_SHIFT;
	252	nrow_desc = fmt_model_subtype
	253	& CCS_FRAME_FORMAT_MODEL_SUBTYPE_ROWS_MASK;
	254
	255	dev_dbg(&client->dev, "format_model_type %s\n",
	256	fmt_model_type == CCS_FRAME_FORMAT_MODEL_TYPE_2_BYTE
	257	? "2 byte" :
	258	fmt_model_type == CCS_FRAME_FORMAT_MODEL_TYPE_4_BYTE
	259	? "4 byte" : "is simply bad");
	260
	261	dev_dbg(&client->dev, "%u column and %u row descriptors\n",
	262	ncol_desc, nrow_desc);
	263
	264	for (i = 0; i < ncol_desc + nrow_desc; i++) {
	265	u32 desc;
	266	u32 pixelcode;
	267	u32 pixels;
	268	char *which;
	269	char *what;
	270
	271	if (fmt_model_type == CCS_FRAME_FORMAT_MODEL_TYPE_2_BYTE) {
	272	desc = CCS_LIM_AT(sensor, FRAME_FORMAT_DESCRIPTOR, i);
	273
	274	pixelcode =
	275	(desc
	276	& CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MASK)
	277	>> CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_SHIFT;
	278	pixels = desc & CCS_FRAME_FORMAT_DESCRIPTOR_PIXELS_MASK;
	279	} else if (fmt_model_type
	280	== CCS_FRAME_FORMAT_MODEL_TYPE_4_BYTE) {
	281	desc = CCS_LIM_AT(sensor, FRAME_FORMAT_DESCRIPTOR_4, i);
	282
	283	pixelcode =
	284	(desc
	285	& CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MASK)
	286	>> CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_SHIFT;
	287	pixels = desc &
	288	CCS_FRAME_FORMAT_DESCRIPTOR_4_PIXELS_MASK;
	289	} else {
	290	dev_dbg(&client->dev,
	291	"invalid frame format model type %d\n",
	292	fmt_model_type);
	293	return -EINVAL;
	294	}
	295
	296	if (i < ncol_desc)
	297	which = "columns";
	298	else
	299	which = "rows";
	300
	301	switch (pixelcode) {
	302	case CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_EMBEDDED:
	303	what = "embedded";
	304	break;
	305	case CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_DUMMY_PIXEL:
	306	what = "dummy";
	307	break;
	308	case CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_BLACK_PIXEL:
	309	what = "black";
	310	break;
	311	case CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_DARK_PIXEL:
	312	what = "dark";
	313	break;
	314	case CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_VISIBLE_PIXEL:
	315	what = "visible";
	316	break;
	317	default:
	318	what = "invalid";
	319	break;
	320	}
	321
	322	dev_dbg(&client->dev,
	323	"%s pixels: %d %s (pixelcode %u)\n",
	324	what, pixels, which, pixelcode);
	325
	326	if (i < ncol_desc) {
	327	if (pixelcode ==
	328	CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_VISIBLE_PIXEL)
	329	sensor->visible_pixel_start = pixel_count;
	330	pixel_count += pixels;
	331	continue;
	332	}
	333
	334	/* Handle row descriptors */
	335	switch (pixelcode) {
	336	case CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_EMBEDDED:
	337	if (sensor->embedded_end)
	338	break;
	339	sensor->embedded_start = line_count;
	340	sensor->embedded_end = line_count + pixels;
	341	break;
	342	case CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_VISIBLE_PIXEL:
	343	sensor->image_start = line_count;
	344	break;
	345	}
	346	line_count += pixels;
	347	}
	348
	349	if (sensor->embedded_end > sensor->image_start) {
	350	dev_dbg(&client->dev,
	351	"adjusting image start line to %u (was %u)\n",
	352	sensor->embedded_end, sensor->image_start);
	353	sensor->image_start = sensor->embedded_end;
	354	}
	355
	356	dev_dbg(&client->dev, "embedded data from lines %d to %d\n",
	357	sensor->embedded_start, sensor->embedded_end);
	358	dev_dbg(&client->dev, "image data starts at line %d\n",
	359	sensor->image_start);
	360
	361	return 0;
	362	}
	363
	364	static int ccs_pll_configure(struct ccs_sensor *sensor)
	365	{
	366	struct ccs_pll *pll = &sensor->pll;
	367	int rval;
	368
	369	rval = ccs_write(sensor, VT_PIX_CLK_DIV, pll->vt_bk.pix_clk_div);
	370	if (rval < 0)
	371	return rval;
	372
	373	rval = ccs_write(sensor, VT_SYS_CLK_DIV, pll->vt_bk.sys_clk_div);
	374	if (rval < 0)
	375	return rval;
	376
	377	rval = ccs_write(sensor, PRE_PLL_CLK_DIV, pll->vt_fr.pre_pll_clk_div);
	378	if (rval < 0)
	379	return rval;
	380
	381	rval = ccs_write(sensor, PLL_MULTIPLIER, pll->vt_fr.pll_multiplier);
	382	if (rval < 0)
	383	return rval;
	384
	385	/* Lane op clock ratio does not apply here. */
	386	rval = ccs_write(sensor, REQUESTED_LINK_RATE,
	387	DIV_ROUND_UP(pll->op_bk.sys_clk_freq_hz,
	388	1000000 / 256 / 256) *
	389	(pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ?
	390	sensor->pll.csi2.lanes : 1) <<
	391	(pll->flags & CCS_PLL_FLAG_OP_SYS_DDR ? 1 : 0));
	392	if (rval < 0 \|\| sensor->pll.flags & CCS_PLL_FLAG_NO_OP_CLOCKS)
	393	return rval;
	394
	395	rval = ccs_write(sensor, OP_PIX_CLK_DIV, pll->op_bk.pix_clk_div);
	396	if (rval < 0)
	397	return rval;
	398
	399	rval = ccs_write(sensor, OP_SYS_CLK_DIV, pll->op_bk.sys_clk_div);
	400	if (rval < 0)
	401	return rval;
	402
	403	if (!(pll->flags & CCS_PLL_FLAG_DUAL_PLL))
	404	return 0;
	405
	406	rval = ccs_write(sensor, PLL_MODE, CCS_PLL_MODE_DUAL);
	407	if (rval < 0)
	408	return rval;
	409
	410	rval = ccs_write(sensor, OP_PRE_PLL_CLK_DIV,
	411	pll->op_fr.pre_pll_clk_div);
	412	if (rval < 0)
	413	return rval;
	414
	415	return ccs_write(sensor, OP_PLL_MULTIPLIER, pll->op_fr.pll_multiplier);
	416	}
	417
	418	static int ccs_pll_try(struct ccs_sensor sensor, struct ccs_pll pll)
	419	{
	420	struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
	421	struct ccs_pll_limits lim = {
	422	.vt_fr = {
	423	.min_pre_pll_clk_div = CCS_LIM(sensor, MIN_PRE_PLL_CLK_DIV),
	424	.max_pre_pll_clk_div = CCS_LIM(sensor, MAX_PRE_PLL_CLK_DIV),
	425	.min_pll_ip_clk_freq_hz = CCS_LIM(sensor, MIN_PLL_IP_CLK_FREQ_MHZ),
	426	.max_pll_ip_clk_freq_hz = CCS_LIM(sensor, MAX_PLL_IP_CLK_FREQ_MHZ),
	427	.min_pll_multiplier = CCS_LIM(sensor, MIN_PLL_MULTIPLIER),
	428	.max_pll_multiplier = CCS_LIM(sensor, MAX_PLL_MULTIPLIER),
	429	.min_pll_op_clk_freq_hz = CCS_LIM(sensor, MIN_PLL_OP_CLK_FREQ_MHZ),
	430	.max_pll_op_clk_freq_hz = CCS_LIM(sensor, MAX_PLL_OP_CLK_FREQ_MHZ),
	431	},
	432	.op_fr = {
	433	.min_pre_pll_clk_div = CCS_LIM(sensor, MIN_OP_PRE_PLL_CLK_DIV),
	434	.max_pre_pll_clk_div = CCS_LIM(sensor, MAX_OP_PRE_PLL_CLK_DIV),
	435	.min_pll_ip_clk_freq_hz = CCS_LIM(sensor, MIN_OP_PLL_IP_CLK_FREQ_MHZ),
	436	.max_pll_ip_clk_freq_hz = CCS_LIM(sensor, MAX_OP_PLL_IP_CLK_FREQ_MHZ),
	437	.min_pll_multiplier = CCS_LIM(sensor, MIN_OP_PLL_MULTIPLIER),
	438	.max_pll_multiplier = CCS_LIM(sensor, MAX_OP_PLL_MULTIPLIER),
	439	.min_pll_op_clk_freq_hz = CCS_LIM(sensor, MIN_OP_PLL_OP_CLK_FREQ_MHZ),
	440	.max_pll_op_clk_freq_hz = CCS_LIM(sensor, MAX_OP_PLL_OP_CLK_FREQ_MHZ),
	441	},
	442	.op_bk = {
	443	.min_sys_clk_div = CCS_LIM(sensor, MIN_OP_SYS_CLK_DIV),
	444	.max_sys_clk_div = CCS_LIM(sensor, MAX_OP_SYS_CLK_DIV),
	445	.min_pix_clk_div = CCS_LIM(sensor, MIN_OP_PIX_CLK_DIV),
	446	.max_pix_clk_div = CCS_LIM(sensor, MAX_OP_PIX_CLK_DIV),
	447	.min_sys_clk_freq_hz = CCS_LIM(sensor, MIN_OP_SYS_CLK_FREQ_MHZ),
	448	.max_sys_clk_freq_hz = CCS_LIM(sensor, MAX_OP_SYS_CLK_FREQ_MHZ),
	449	.min_pix_clk_freq_hz = CCS_LIM(sensor, MIN_OP_PIX_CLK_FREQ_MHZ),
	450	.max_pix_clk_freq_hz = CCS_LIM(sensor, MAX_OP_PIX_CLK_FREQ_MHZ),
	451	},
	452	.vt_bk = {
	453	.min_sys_clk_div = CCS_LIM(sensor, MIN_VT_SYS_CLK_DIV),
	454	.max_sys_clk_div = CCS_LIM(sensor, MAX_VT_SYS_CLK_DIV),
	455	.min_pix_clk_div = CCS_LIM(sensor, MIN_VT_PIX_CLK_DIV),
	456	.max_pix_clk_div = CCS_LIM(sensor, MAX_VT_PIX_CLK_DIV),
	457	.min_sys_clk_freq_hz = CCS_LIM(sensor, MIN_VT_SYS_CLK_FREQ_MHZ),
	458	.max_sys_clk_freq_hz = CCS_LIM(sensor, MAX_VT_SYS_CLK_FREQ_MHZ),
	459	.min_pix_clk_freq_hz = CCS_LIM(sensor, MIN_VT_PIX_CLK_FREQ_MHZ),
	460	.max_pix_clk_freq_hz = CCS_LIM(sensor, MAX_VT_PIX_CLK_FREQ_MHZ),
	461	},
	462	.min_line_length_pck_bin = CCS_LIM(sensor, MIN_LINE_LENGTH_PCK_BIN),
	463	.min_line_length_pck = CCS_LIM(sensor, MIN_LINE_LENGTH_PCK),
	464	};
	465
	466	return ccs_pll_calculate(&client->dev, &lim, pll);
	467	}
	468
	469	static int ccs_pll_update(struct ccs_sensor *sensor)
	470	{
	471	struct ccs_pll *pll = &sensor->pll;
	472	int rval;
	473
	474	pll->binning_horizontal = sensor->binning_horizontal;
	475	pll->binning_vertical = sensor->binning_vertical;
	476	pll->link_freq =
	477	sensor->link_freq->qmenu_int[sensor->link_freq->val];
	478	pll->scale_m = sensor->scale_m;
	479	pll->bits_per_pixel = sensor->csi_format->compressed;
	480
	481	rval = ccs_pll_try(sensor, pll);
	482	if (rval < 0)
	483	return rval;
	484
	485	__v4l2_ctrl_s_ctrl_int64(sensor->pixel_rate_parray,
	486	pll->pixel_rate_pixel_array);
	487	__v4l2_ctrl_s_ctrl_int64(sensor->pixel_rate_csi, pll->pixel_rate_csi);
	488
	489	return 0;
	490	}
	491
	492
	493	/*
	494	*
	495	* V4L2 Controls handling
	496	*
	497	*/
	498
	499	static void __ccs_update_exposure_limits(struct ccs_sensor *sensor)
	500	{
	501	struct v4l2_ctrl *ctrl = sensor->exposure;
	502	int max;
	503
	504	max = sensor->pixel_array->crop[CCS_PA_PAD_SRC].height
	505	+ sensor->vblank->val
	506	- CCS_LIM(sensor, COARSE_INTEGRATION_TIME_MAX_MARGIN);
	507
	508	__v4l2_ctrl_modify_range(ctrl, ctrl->minimum, max, ctrl->step, max);
	509	}
	510
	511	/*
	512	* Order matters.
	513	*
	514	* 1. Bits-per-pixel, descending.
	515	* 2. Bits-per-pixel compressed, descending.
	516	* 3. Pixel order, same as in pixel_order_str. Formats for all four pixel
	517	* orders must be defined.
	518	*/
	519	static const struct ccs_csi_data_format ccs_csi_data_formats[] = {
	520	{ MEDIA_BUS_FMT_SGRBG16_1X16, 16, 16, CCS_PIXEL_ORDER_GRBG, },
	521	{ MEDIA_BUS_FMT_SRGGB16_1X16, 16, 16, CCS_PIXEL_ORDER_RGGB, },
	522	{ MEDIA_BUS_FMT_SBGGR16_1X16, 16, 16, CCS_PIXEL_ORDER_BGGR, },
	523	{ MEDIA_BUS_FMT_SGBRG16_1X16, 16, 16, CCS_PIXEL_ORDER_GBRG, },
	524	{ MEDIA_BUS_FMT_SGRBG14_1X14, 14, 14, CCS_PIXEL_ORDER_GRBG, },
	525	{ MEDIA_BUS_FMT_SRGGB14_1X14, 14, 14, CCS_PIXEL_ORDER_RGGB, },
	526	{ MEDIA_BUS_FMT_SBGGR14_1X14, 14, 14, CCS_PIXEL_ORDER_BGGR, },
	527	{ MEDIA_BUS_FMT_SGBRG14_1X14, 14, 14, CCS_PIXEL_ORDER_GBRG, },
	528	{ MEDIA_BUS_FMT_SGRBG12_1X12, 12, 12, CCS_PIXEL_ORDER_GRBG, },
	529	{ MEDIA_BUS_FMT_SRGGB12_1X12, 12, 12, CCS_PIXEL_ORDER_RGGB, },
	530	{ MEDIA_BUS_FMT_SBGGR12_1X12, 12, 12, CCS_PIXEL_ORDER_BGGR, },
	531	{ MEDIA_BUS_FMT_SGBRG12_1X12, 12, 12, CCS_PIXEL_ORDER_GBRG, },
	532	{ MEDIA_BUS_FMT_SGRBG10_1X10, 10, 10, CCS_PIXEL_ORDER_GRBG, },
	533	{ MEDIA_BUS_FMT_SRGGB10_1X10, 10, 10, CCS_PIXEL_ORDER_RGGB, },
	534	{ MEDIA_BUS_FMT_SBGGR10_1X10, 10, 10, CCS_PIXEL_ORDER_BGGR, },
	535	{ MEDIA_BUS_FMT_SGBRG10_1X10, 10, 10, CCS_PIXEL_ORDER_GBRG, },
	536	{ MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8, 10, 8, CCS_PIXEL_ORDER_GRBG, },
	537	{ MEDIA_BUS_FMT_SRGGB10_DPCM8_1X8, 10, 8, CCS_PIXEL_ORDER_RGGB, },
	538	{ MEDIA_BUS_FMT_SBGGR10_DPCM8_1X8, 10, 8, CCS_PIXEL_ORDER_BGGR, },
	539	{ MEDIA_BUS_FMT_SGBRG10_DPCM8_1X8, 10, 8, CCS_PIXEL_ORDER_GBRG, },
	540	{ MEDIA_BUS_FMT_SGRBG8_1X8, 8, 8, CCS_PIXEL_ORDER_GRBG, },
	541	{ MEDIA_BUS_FMT_SRGGB8_1X8, 8, 8, CCS_PIXEL_ORDER_RGGB, },
	542	{ MEDIA_BUS_FMT_SBGGR8_1X8, 8, 8, CCS_PIXEL_ORDER_BGGR, },
	543	{ MEDIA_BUS_FMT_SGBRG8_1X8, 8, 8, CCS_PIXEL_ORDER_GBRG, },
	544	};
	545
	546	static const char *pixel_order_str[] = { "GRBG", "RGGB", "BGGR", "GBRG" };
	547
	548	#define to_csi_format_idx(fmt) (((unsigned long)(fmt) \
	549	- (unsigned long)ccs_csi_data_formats) \
	550	/ sizeof(*ccs_csi_data_formats))
	551
	552	static u32 ccs_pixel_order(struct ccs_sensor *sensor)
	553	{
	554	struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
	555	int flip = 0;
	556
	557	if (sensor->hflip) {
	558	if (sensor->hflip->val)
	559	flip \|= CCS_IMAGE_ORIENTATION_HORIZONTAL_MIRROR;
	560
	561	if (sensor->vflip->val)
	562	flip \|= CCS_IMAGE_ORIENTATION_VERTICAL_FLIP;
	563	}
	564
	565	flip ^= sensor->hvflip_inv_mask;
	566
	567	dev_dbg(&client->dev, "flip %d\n", flip);
	568	return sensor->default_pixel_order ^ flip;
	569	}
	570
	571	static void ccs_update_mbus_formats(struct ccs_sensor *sensor)
	572	{
	573	struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
	574	unsigned int csi_format_idx =
	575	to_csi_format_idx(sensor->csi_format) & ~3;
	576	unsigned int internal_csi_format_idx =
	577	to_csi_format_idx(sensor->internal_csi_format) & ~3;
	578	unsigned int pixel_order = ccs_pixel_order(sensor);
	579
	580	if (WARN_ON_ONCE(max(internal_csi_format_idx, csi_format_idx) +
	581	pixel_order >= ARRAY_SIZE(ccs_csi_data_formats)))
	582	return;
	583
	584	sensor->mbus_frame_fmts =
	585	sensor->default_mbus_frame_fmts << pixel_order;
	586	sensor->csi_format =
	587	&ccs_csi_data_formats[csi_format_idx + pixel_order];
	588	sensor->internal_csi_format =
	589	&ccs_csi_data_formats[internal_csi_format_idx
	590	+ pixel_order];
	591
	592	dev_dbg(&client->dev, "new pixel order %s\n",
	593	pixel_order_str[pixel_order]);
	594	}
	595
	596	static const char * const ccs_test_patterns[] = {
	597	"Disabled",
	598	"Solid Colour",
	599	"Eight Vertical Colour Bars",
	600	"Colour Bars With Fade to Grey",
	601	"Pseudorandom Sequence (PN9)",
	602	};
	603
	604	static int ccs_set_ctrl(struct v4l2_ctrl *ctrl)
	605	{
	606	struct ccs_sensor *sensor =
	607	container_of(ctrl->handler, struct ccs_subdev, ctrl_handler)
	608	->sensor;
	609	struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
	610	int pm_status;
	611	u32 orient = 0;
	612	unsigned int i;
	613	int exposure;
	614	int rval;
	615
	616	switch (ctrl->id) {
	617	case V4L2_CID_HFLIP:
	618	case V4L2_CID_VFLIP:
	619	if (sensor->streaming)
	620	return -EBUSY;
	621
	622	if (sensor->hflip->val)
	623	orient \|= CCS_IMAGE_ORIENTATION_HORIZONTAL_MIRROR;
	624
	625	if (sensor->vflip->val)
	626	orient \|= CCS_IMAGE_ORIENTATION_VERTICAL_FLIP;
	627
	628	orient ^= sensor->hvflip_inv_mask;
	629
	630	ccs_update_mbus_formats(sensor);
	631
	632	break;
	633	case V4L2_CID_VBLANK:
	634	exposure = sensor->exposure->val;
	635
	636	__ccs_update_exposure_limits(sensor);
	637
	638	if (exposure > sensor->exposure->maximum) {
	639	sensor->exposure->val = sensor->exposure->maximum;
	640	rval = ccs_set_ctrl(sensor->exposure);
	641	if (rval < 0)
	642	return rval;
	643	}
	644
	645	break;
	646	case V4L2_CID_LINK_FREQ:
	647	if (sensor->streaming)
	648	return -EBUSY;
	649
	650	rval = ccs_pll_update(sensor);
	651	if (rval)
	652	return rval;
	653
	654	return 0;
	655	case V4L2_CID_TEST_PATTERN:
	656	for (i = 0; i < ARRAY_SIZE(sensor->test_data); i++)
	657	v4l2_ctrl_activate(
	658	sensor->test_data[i],
	659	ctrl->val ==
	660	V4L2_SMIAPP_TEST_PATTERN_MODE_SOLID_COLOUR);
	661
	662	break;
	663	}
	664
	665	pm_status = pm_runtime_get_if_active(&client->dev, true);
	666	if (!pm_status)
	667	return 0;
	668
	669	switch (ctrl->id) {
	670	case V4L2_CID_ANALOGUE_GAIN:
	671	rval = ccs_write(sensor, ANALOG_GAIN_CODE_GLOBAL, ctrl->val);
	672
	673	break;
	674	case V4L2_CID_EXPOSURE:
	675	rval = ccs_write(sensor, COARSE_INTEGRATION_TIME, ctrl->val);
	676
	677	break;
	678	case V4L2_CID_HFLIP:
	679	case V4L2_CID_VFLIP:
	680	rval = ccs_write(sensor, IMAGE_ORIENTATION, orient);
	681
	682	break;
	683	case V4L2_CID_VBLANK:
	684	rval = ccs_write(sensor, FRAME_LENGTH_LINES,
	685	sensor->pixel_array->crop[
	686	CCS_PA_PAD_SRC].height
	687	+ ctrl->val);
	688
	689	break;
	690	case V4L2_CID_HBLANK:
	691	rval = ccs_write(sensor, LINE_LENGTH_PCK,
	692	sensor->pixel_array->crop[CCS_PA_PAD_SRC].width
	693	+ ctrl->val);
	694
	695	break;
	696	case V4L2_CID_TEST_PATTERN:
	697	rval = ccs_write(sensor, TEST_PATTERN_MODE, ctrl->val);
	698
	699	break;
	700	case V4L2_CID_TEST_PATTERN_RED:
	701	rval = ccs_write(sensor, TEST_DATA_RED, ctrl->val);
	702
	703	break;
	704	case V4L2_CID_TEST_PATTERN_GREENR:
	705	rval = ccs_write(sensor, TEST_DATA_GREENR, ctrl->val);
	706
	707	break;
	708	case V4L2_CID_TEST_PATTERN_BLUE:
	709	rval = ccs_write(sensor, TEST_DATA_BLUE, ctrl->val);
	710
	711	break;
	712	case V4L2_CID_TEST_PATTERN_GREENB:
	713	rval = ccs_write(sensor, TEST_DATA_GREENB, ctrl->val);
	714
	715	break;
	716	case V4L2_CID_PIXEL_RATE:
	717	/* For v4l2_ctrl_s_ctrl_int64() used internally. */
	718	rval = 0;
	719
	720	break;
	721	default:
	722	rval = -EINVAL;
	723	}
	724
	725	if (pm_status > 0) {
	726	pm_runtime_mark_last_busy(&client->dev);
	727	pm_runtime_put_autosuspend(&client->dev);
	728	}
	729
	730	return rval;
	731	}
	732
	733	static const struct v4l2_ctrl_ops ccs_ctrl_ops = {
	734	.s_ctrl = ccs_set_ctrl,
	735	};
	736
	737	static int ccs_init_controls(struct ccs_sensor *sensor)
	738	{
	739	struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
	740	int rval;
	741
	742	rval = v4l2_ctrl_handler_init(&sensor->pixel_array->ctrl_handler, 12);
	743	if (rval)
	744	return rval;
	745
	746	sensor->pixel_array->ctrl_handler.lock = &sensor->mutex;
	747
	748	sensor->analog_gain = v4l2_ctrl_new_std(
	749	&sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops,
	750	V4L2_CID_ANALOGUE_GAIN,
	751	CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN),
	752	CCS_LIM(sensor, ANALOG_GAIN_CODE_MAX),
	753	max(CCS_LIM(sensor, ANALOG_GAIN_CODE_STEP), 1U),
	754	CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN));
	755
	756	/* Exposure limits will be updated soon, use just something here. */
	757	sensor->exposure = v4l2_ctrl_new_std(
	758	&sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops,
	759	V4L2_CID_EXPOSURE, 0, 0, 1, 0);
	760
	761	sensor->hflip = v4l2_ctrl_new_std(
	762	&sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops,
	763	V4L2_CID_HFLIP, 0, 1, 1, 0);
	764	sensor->vflip = v4l2_ctrl_new_std(
	765	&sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops,
	766	V4L2_CID_VFLIP, 0, 1, 1, 0);
	767
	768	sensor->vblank = v4l2_ctrl_new_std(
	769	&sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops,
	770	V4L2_CID_VBLANK, 0, 1, 1, 0);
	771
	772	if (sensor->vblank)
	773	sensor->vblank->flags \|= V4L2_CTRL_FLAG_UPDATE;
	774
	775	sensor->hblank = v4l2_ctrl_new_std(
	776	&sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops,
	777	V4L2_CID_HBLANK, 0, 1, 1, 0);
	778
	779	if (sensor->hblank)
	780	sensor->hblank->flags \|= V4L2_CTRL_FLAG_UPDATE;
	781
	782	sensor->pixel_rate_parray = v4l2_ctrl_new_std(
	783	&sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops,
	784	V4L2_CID_PIXEL_RATE, 1, INT_MAX, 1, 1);
	785
	786	v4l2_ctrl_new_std_menu_items(&sensor->pixel_array->ctrl_handler,
	787	&ccs_ctrl_ops, V4L2_CID_TEST_PATTERN,
	788	ARRAY_SIZE(ccs_test_patterns) - 1,
	789	0, 0, ccs_test_patterns);
	790
	791	if (sensor->pixel_array->ctrl_handler.error) {
	792	dev_err(&client->dev,
	793	"pixel array controls initialization failed (%d)\n",
	794	sensor->pixel_array->ctrl_handler.error);
	795	return sensor->pixel_array->ctrl_handler.error;
	796	}
	797
	798	sensor->pixel_array->sd.ctrl_handler =
	799	&sensor->pixel_array->ctrl_handler;
	800
	801	v4l2_ctrl_cluster(2, &sensor->hflip);
	802
	803	rval = v4l2_ctrl_handler_init(&sensor->src->ctrl_handler, 0);
	804	if (rval)
	805	return rval;
	806
	807	sensor->src->ctrl_handler.lock = &sensor->mutex;
	808
	809	sensor->pixel_rate_csi = v4l2_ctrl_new_std(
	810	&sensor->src->ctrl_handler, &ccs_ctrl_ops,
	811	V4L2_CID_PIXEL_RATE, 1, INT_MAX, 1, 1);
	812
	813	if (sensor->src->ctrl_handler.error) {
	814	dev_err(&client->dev,
	815	"src controls initialization failed (%d)\n",
	816	sensor->src->ctrl_handler.error);
	817	return sensor->src->ctrl_handler.error;
	818	}
	819
	820	sensor->src->sd.ctrl_handler = &sensor->src->ctrl_handler;
	821
	822	return 0;
	823	}
	824
	825	/*
	826	* For controls that require information on available media bus codes
	827	* and linke frequencies.
	828	*/
	829	static int ccs_init_late_controls(struct ccs_sensor *sensor)
	830	{
	831	unsigned long *valid_link_freqs = &sensor->valid_link_freqs[
	832	sensor->csi_format->compressed - sensor->compressed_min_bpp];
	833	unsigned int i;
	834
	835	for (i = 0; i < ARRAY_SIZE(sensor->test_data); i++) {
	836	int max_value = (1 << sensor->csi_format->width) - 1;
	837
	838	sensor->test_data[i] = v4l2_ctrl_new_std(
	839	&sensor->pixel_array->ctrl_handler,
	840	&ccs_ctrl_ops, V4L2_CID_TEST_PATTERN_RED + i,
	841	0, max_value, 1, max_value);
	842	}
	843
	844	sensor->link_freq = v4l2_ctrl_new_int_menu(
	845	&sensor->src->ctrl_handler, &ccs_ctrl_ops,
	846	V4L2_CID_LINK_FREQ, __fls(*valid_link_freqs),
	847	__ffs(*valid_link_freqs), sensor->hwcfg.op_sys_clock);
	848
	849	return sensor->src->ctrl_handler.error;
	850	}
	851
	852	static void ccs_free_controls(struct ccs_sensor *sensor)
	853	{
	854	unsigned int i;
	855
	856	for (i = 0; i < sensor->ssds_used; i++)
	857	v4l2_ctrl_handler_free(&sensor->ssds[i].ctrl_handler);
	858	}
	859
	860	static int ccs_get_mbus_formats(struct ccs_sensor *sensor)
	861	{
	862	struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
	863	struct ccs_pll *pll = &sensor->pll;
	864	u8 compressed_max_bpp = 0;
	865	unsigned int type, n;
	866	unsigned int i, pixel_order;
	867	int rval;
	868
	869	type = CCS_LIM(sensor, DATA_FORMAT_MODEL_TYPE);
	870
	871	dev_dbg(&client->dev, "data_format_model_type %d\n", type);
	872
	873	rval = ccs_read(sensor, PIXEL_ORDER, &pixel_order);
	874	if (rval)
	875	return rval;
	876
	877	if (pixel_order >= ARRAY_SIZE(pixel_order_str)) {
	878	dev_dbg(&client->dev, "bad pixel order %d\n", pixel_order);
	879	return -EINVAL;
	880	}
	881
	882	dev_dbg(&client->dev, "pixel order %d (%s)\n", pixel_order,
	883	pixel_order_str[pixel_order]);
	884
	885	switch (type) {
	886	case CCS_DATA_FORMAT_MODEL_TYPE_NORMAL:
	887	n = SMIAPP_DATA_FORMAT_MODEL_TYPE_NORMAL_N;
	888	break;
	889	case CCS_DATA_FORMAT_MODEL_TYPE_EXTENDED:
	890	n = CCS_LIM_DATA_FORMAT_DESCRIPTOR_MAX_N + 1;
	891	break;
	892	default:
	893	return -EINVAL;
	894	}
	895
	896	sensor->default_pixel_order = pixel_order;
	897	sensor->mbus_frame_fmts = 0;
	898
	899	for (i = 0; i < n; i++) {
	900	unsigned int fmt, j;
	901
	902	fmt = CCS_LIM_AT(sensor, DATA_FORMAT_DESCRIPTOR, i);
	903
	904	dev_dbg(&client->dev, "%u: bpp %u, compressed %u\n",
	905	i, fmt >> 8, (u8)fmt);
	906
	907	for (j = 0; j < ARRAY_SIZE(ccs_csi_data_formats); j++) {
	908	const struct ccs_csi_data_format *f =
	909	&ccs_csi_data_formats[j];
	910
	911	if (f->pixel_order != CCS_PIXEL_ORDER_GRBG)
	912	continue;
	913
	914	if (f->width != fmt >>
	915	CCS_DATA_FORMAT_DESCRIPTOR_UNCOMPRESSED_SHIFT \|\|
	916	f->compressed !=
	917	(fmt & CCS_DATA_FORMAT_DESCRIPTOR_COMPRESSED_MASK))
	918	continue;
	919
	920	dev_dbg(&client->dev, "jolly good! %d\n", j);
	921
	922	sensor->default_mbus_frame_fmts \|= 1 << j;
	923	}
	924	}
	925
	926	/* Figure out which BPP values can be used with which formats. */
	927	pll->binning_horizontal = 1;
	928	pll->binning_vertical = 1;
	929	pll->scale_m = sensor->scale_m;
	930
	931	for (i = 0; i < ARRAY_SIZE(ccs_csi_data_formats); i++) {
	932	sensor->compressed_min_bpp =
	933	min(ccs_csi_data_formats[i].compressed,
	934	sensor->compressed_min_bpp);
	935	compressed_max_bpp =
	936	max(ccs_csi_data_formats[i].compressed,
	937	compressed_max_bpp);
	938	}
	939
	940	sensor->valid_link_freqs = devm_kcalloc(
	941	&client->dev,
	942	compressed_max_bpp - sensor->compressed_min_bpp + 1,
	943	sizeof(*sensor->valid_link_freqs), GFP_KERNEL);
	944	if (!sensor->valid_link_freqs)
	945	return -ENOMEM;
	946
	947	for (i = 0; i < ARRAY_SIZE(ccs_csi_data_formats); i++) {
	948	const struct ccs_csi_data_format *f =
	949	&ccs_csi_data_formats[i];
	950	unsigned long *valid_link_freqs =
	951	&sensor->valid_link_freqs[
	952	f->compressed - sensor->compressed_min_bpp];
	953	unsigned int j;
	954
	955	if (!(sensor->default_mbus_frame_fmts & 1 << i))
	956	continue;
	957
	958	pll->bits_per_pixel = f->compressed;
	959
	960	for (j = 0; sensor->hwcfg.op_sys_clock[j]; j++) {
	961	pll->link_freq = sensor->hwcfg.op_sys_clock[j];
	962
	963	rval = ccs_pll_try(sensor, pll);
	964	dev_dbg(&client->dev, "link freq %u Hz, bpp %u %s\n",
	965	pll->link_freq, pll->bits_per_pixel,
	966	rval ? "not ok" : "ok");
	967	if (rval)
	968	continue;
	969
	970	set_bit(j, valid_link_freqs);
	971	}
	972
	973	if (!*valid_link_freqs) {
	974	dev_info(&client->dev,
	975	"no valid link frequencies for %u bpp\n",
	976	f->compressed);
	977	sensor->default_mbus_frame_fmts &= ~BIT(i);
	978	continue;
	979	}
	980
	981	if (!sensor->csi_format
	982	\|\| f->width > sensor->csi_format->width
	983	\|\| (f->width == sensor->csi_format->width
	984	&& f->compressed > sensor->csi_format->compressed)) {
	985	sensor->csi_format = f;
	986	sensor->internal_csi_format = f;
	987	}
	988	}
	989
	990	if (!sensor->csi_format) {
	991	dev_err(&client->dev, "no supported mbus code found\n");
	992	return -EINVAL;
	993	}
	994
	995	ccs_update_mbus_formats(sensor);
	996
	997	return 0;
	998	}
	999
	1000	static void ccs_update_blanking(struct ccs_sensor *sensor)
	1001	{
	1002	struct v4l2_ctrl *vblank = sensor->vblank;
	1003	struct v4l2_ctrl *hblank = sensor->hblank;
	1004	uint16_t min_fll, max_fll, min_llp, max_llp, min_lbp;
	1005	int min, max;
	1006
	1007	if (sensor->binning_vertical > 1 \|\| sensor->binning_horizontal > 1) {
	1008	min_fll = CCS_LIM(sensor, MIN_FRAME_LENGTH_LINES_BIN);
	1009	max_fll = CCS_LIM(sensor, MAX_FRAME_LENGTH_LINES_BIN);
	1010	min_llp = CCS_LIM(sensor, MIN_LINE_LENGTH_PCK_BIN);
	1011	max_llp = CCS_LIM(sensor, MAX_LINE_LENGTH_PCK_BIN);
	1012	min_lbp = CCS_LIM(sensor, MIN_LINE_BLANKING_PCK_BIN);
	1013	} else {
	1014	min_fll = CCS_LIM(sensor, MIN_FRAME_LENGTH_LINES);
	1015	max_fll = CCS_LIM(sensor, MAX_FRAME_LENGTH_LINES);
	1016	min_llp = CCS_LIM(sensor, MIN_LINE_LENGTH_PCK);
	1017	max_llp = CCS_LIM(sensor, MAX_LINE_LENGTH_PCK);
	1018	min_lbp = CCS_LIM(sensor, MIN_LINE_BLANKING_PCK);
	1019	}
	1020
	1021	min = max_t(int,
	1022	CCS_LIM(sensor, MIN_FRAME_BLANKING_LINES),
	1023	min_fll - sensor->pixel_array->crop[CCS_PA_PAD_SRC].height);
	1024	max = max_fll - sensor->pixel_array->crop[CCS_PA_PAD_SRC].height;
	1025
	1026	__v4l2_ctrl_modify_range(vblank, min, max, vblank->step, min);
	1027
	1028	min = max_t(int,
	1029	min_llp - sensor->pixel_array->crop[CCS_PA_PAD_SRC].width,
	1030	min_lbp);
	1031	max = max_llp - sensor->pixel_array->crop[CCS_PA_PAD_SRC].width;
	1032
	1033	__v4l2_ctrl_modify_range(hblank, min, max, hblank->step, min);
	1034
	1035	__ccs_update_exposure_limits(sensor);
	1036	}
	1037
	1038	static int ccs_pll_blanking_update(struct ccs_sensor *sensor)
	1039	{
	1040	struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
	1041	int rval;
	1042
	1043	rval = ccs_pll_update(sensor);
	1044	if (rval < 0)
	1045	return rval;
	1046
	1047	/* Output from pixel array, including blanking */
	1048	ccs_update_blanking(sensor);
	1049
	1050	dev_dbg(&client->dev, "vblank\t\t%d\n", sensor->vblank->val);
	1051	dev_dbg(&client->dev, "hblank\t\t%d\n", sensor->hblank->val);
	1052
	1053	dev_dbg(&client->dev, "real timeperframe\t100/%d\n",
	1054	sensor->pll.pixel_rate_pixel_array /
	1055	((sensor->pixel_array->crop[CCS_PA_PAD_SRC].width
	1056	+ sensor->hblank->val) *
	1057	(sensor->pixel_array->crop[CCS_PA_PAD_SRC].height
	1058	+ sensor->vblank->val) / 100));
	1059
	1060	return 0;
	1061	}
	1062
	1063	/*
	1064	*
	1065	* SMIA++ NVM handling
	1066	*
	1067	*/
	1068
	1069	static int ccs_read_nvm_page(struct ccs_sensor sensor, u32 p, u8 nvm,
	1070	u8 *status)
	1071	{
	1072	unsigned int i;
	1073	int rval;
	1074	u32 s;
	1075
	1076	*status = 0;
	1077
	1078	rval = ccs_write(sensor, DATA_TRANSFER_IF_1_PAGE_SELECT, p);
	1079	if (rval)
	1080	return rval;
	1081
	1082	rval = ccs_write(sensor, DATA_TRANSFER_IF_1_CTRL,
	1083	CCS_DATA_TRANSFER_IF_1_CTRL_ENABLE);
	1084	if (rval)
	1085	return rval;
	1086
	1087	rval = ccs_read(sensor, DATA_TRANSFER_IF_1_STATUS, &s);
	1088	if (rval)
	1089	return rval;
	1090
	1091	if (s & CCS_DATA_TRANSFER_IF_1_STATUS_IMPROPER_IF_USAGE) {
	1092	*status = s;
	1093	return -ENODATA;
	1094	}
	1095
	1096	if (CCS_LIM(sensor, DATA_TRANSFER_IF_CAPABILITY) &
	1097	CCS_DATA_TRANSFER_IF_CAPABILITY_POLLING) {
	1098	for (i = 1000; i > 0; i--) {
	1099	if (s & CCS_DATA_TRANSFER_IF_1_STATUS_READ_IF_READY)
	1100	break;
	1101
	1102	rval = ccs_read(sensor, DATA_TRANSFER_IF_1_STATUS, &s);
	1103	if (rval)
	1104	return rval;
	1105	}
	1106
	1107	if (!i)
	1108	return -ETIMEDOUT;
	1109	}
	1110
	1111	for (i = 0; i <= CCS_LIM_DATA_TRANSFER_IF_1_DATA_MAX_P; i++) {
	1112	u32 v;
	1113
	1114	rval = ccs_read(sensor, DATA_TRANSFER_IF_1_DATA(i), &v);
	1115	if (rval)
	1116	return rval;
	1117
	1118	*nvm++ = v;
	1119	}
	1120
	1121	return 0;
	1122	}
	1123
	1124	static int ccs_read_nvm(struct ccs_sensor sensor, unsigned char nvm,
	1125	size_t nvm_size)
	1126	{
	1127	u8 status = 0;
	1128	u32 p;
	1129	int rval = 0, rval2;
	1130
	1131	for (p = 0; p < nvm_size / (CCS_LIM_DATA_TRANSFER_IF_1_DATA_MAX_P + 1)
	1132	&& !rval; p++) {
	1133	rval = ccs_read_nvm_page(sensor, p, nvm, &status);
	1134	nvm += CCS_LIM_DATA_TRANSFER_IF_1_DATA_MAX_P + 1;
	1135	}
	1136
	1137	if (rval == -ENODATA &&
	1138	status & CCS_DATA_TRANSFER_IF_1_STATUS_IMPROPER_IF_USAGE)
	1139	rval = 0;
	1140
	1141	rval2 = ccs_write(sensor, DATA_TRANSFER_IF_1_CTRL, 0);
	1142	if (rval < 0)
	1143	return rval;
	1144	else
	1145	return rval2 ?: p * (CCS_LIM_DATA_TRANSFER_IF_1_DATA_MAX_P + 1);
	1146	}
	1147
	1148	/*
	1149	*
	1150	* SMIA++ CCI address control
	1151	*
	1152	*/
	1153	static int ccs_change_cci_addr(struct ccs_sensor *sensor)
	1154	{
	1155	struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
	1156	int rval;
	1157	u32 val;
	1158
	1159	client->addr = sensor->hwcfg.i2c_addr_dfl;
	1160
	1161	rval = ccs_write(sensor, CCI_ADDRESS_CTRL,
	1162	sensor->hwcfg.i2c_addr_alt << 1);
	1163	if (rval)
	1164	return rval;
	1165
	1166	client->addr = sensor->hwcfg.i2c_addr_alt;
	1167
	1168	/* verify addr change went ok */
	1169	rval = ccs_read(sensor, CCI_ADDRESS_CTRL, &val);
	1170	if (rval)
	1171	return rval;
	1172
	1173	if (val != sensor->hwcfg.i2c_addr_alt << 1)
	1174	return -ENODEV;
	1175
	1176	return 0;
	1177	}
	1178
	1179	/*
	1180	*
	1181	* SMIA++ Mode Control
	1182	*
	1183	*/
	1184	static int ccs_setup_flash_strobe(struct ccs_sensor *sensor)
	1185	{
	1186	struct ccs_flash_strobe_parms *strobe_setup;
	1187	unsigned int ext_freq = sensor->hwcfg.ext_clk;
	1188	u32 tmp;
	1189	u32 strobe_adjustment;
	1190	u32 strobe_width_high_rs;
	1191	int rval;
	1192
	1193	strobe_setup = sensor->hwcfg.strobe_setup;
	1194
	1195	/*
	1196	* How to calculate registers related to strobe length. Please
	1197	* do not change, or if you do at least know what you're
	1198	* doing. :-)
	1199	*
	1200	* Sakari Ailus <sakari.ailus@linux.intel.com> 2010-10-25
	1201	*
	1202	* flash_strobe_length [us] / 10^6 = (tFlash_strobe_width_ctrl
	1203	* / EXTCLK freq [Hz]) * flash_strobe_adjustment
	1204	*
	1205	* tFlash_strobe_width_ctrl E N, [1 - 0xffff]
	1206	* flash_strobe_adjustment E N, [1 - 0xff]
	1207	*
	1208	* The formula above is written as below to keep it on one
	1209	* line:
	1210	*
	1211	* l / 10^6 = w / e * a
	1212	*
	1213	* Let's mark w * a by x:
	1214	*
	1215	* x = w * a
	1216	*
	1217	* Thus, we get:
	1218	*
	1219	* x = l * e / 10^6
	1220	*
	1221	* The strobe width must be at least as long as requested,
	1222	* thus rounding upwards is needed.
	1223	*
	1224	* x = (l * e + 10^6 - 1) / 10^6
	1225	* -----------------------------
	1226	*
	1227	* Maximum possible accuracy is wanted at all times. Thus keep
	1228	* a as small as possible.
	1229	*
	1230	* Calculate a, assuming maximum w, with rounding upwards:
	1231	*
	1232	* a = (x + (2^16 - 1) - 1) / (2^16 - 1)
	1233	* -------------------------------------
	1234	*
	1235	* Thus, we also get w, with that a, with rounding upwards:
	1236	*
	1237	* w = (x + a - 1) / a
	1238	* -------------------
	1239	*
	1240	* To get limits:
	1241	*
	1242	* x E [1, (2^16 - 1) * (2^8 - 1)]
	1243	*
	1244	* Substituting maximum x to the original formula (with rounding),
	1245	* the maximum l is thus
	1246	*
	1247	* (2^16 - 1) * (2^8 - 1) * 10^6 = l * e + 10^6 - 1
	1248	*
	1249	* l = (10^6 * (2^16 - 1) * (2^8 - 1) - 10^6 + 1) / e
	1250	* --------------------------------------------------
	1251	*
	1252	* flash_strobe_length must be clamped between 1 and
	1253	* (10^6 * (2^16 - 1) * (2^8 - 1) - 10^6 + 1) / EXTCLK freq.
	1254	*
	1255	* Then,
	1256	*
	1257	* flash_strobe_adjustment = ((flash_strobe_length *
	1258	* EXTCLK freq + 10^6 - 1) / 10^6 + (2^16 - 1) - 1) / (2^16 - 1)
	1259	*
	1260	* tFlash_strobe_width_ctrl = ((flash_strobe_length *
	1261	* EXTCLK freq + 10^6 - 1) / 10^6 +
	1262	* flash_strobe_adjustment - 1) / flash_strobe_adjustment
	1263	*/
	1264	tmp = div_u64(1000000ULL * ((1 << 16) - 1) * ((1 << 8) - 1) -
	1265	1000000 + 1, ext_freq);
	1266	strobe_setup->strobe_width_high_us =
	1267	clamp_t(u32, strobe_setup->strobe_width_high_us, 1, tmp);
	1268
	1269	tmp = div_u64(((u64)strobe_setup->strobe_width_high_us * (u64)ext_freq +
	1270	1000000 - 1), 1000000ULL);
	1271	strobe_adjustment = (tmp + (1 << 16) - 1 - 1) / ((1 << 16) - 1);
	1272	strobe_width_high_rs = (tmp + strobe_adjustment - 1) /
	1273	strobe_adjustment;
	1274
	1275	rval = ccs_write(sensor, FLASH_MODE_RS, strobe_setup->mode);
	1276	if (rval < 0)
	1277	goto out;
	1278
	1279	rval = ccs_write(sensor, FLASH_STROBE_ADJUSTMENT, strobe_adjustment);
	1280	if (rval < 0)
	1281	goto out;
	1282
	1283	rval = ccs_write(sensor, TFLASH_STROBE_WIDTH_HIGH_RS_CTRL,
	1284	strobe_width_high_rs);
	1285	if (rval < 0)
	1286	goto out;
	1287
	1288	rval = ccs_write(sensor, TFLASH_STROBE_DELAY_RS_CTRL,
	1289	strobe_setup->strobe_delay);
	1290	if (rval < 0)
	1291	goto out;
	1292
	1293	rval = ccs_write(sensor, FLASH_STROBE_START_POINT,
	1294	strobe_setup->stobe_start_point);
	1295	if (rval < 0)
	1296	goto out;
	1297
	1298	rval = ccs_write(sensor, FLASH_TRIGGER_RS, strobe_setup->trigger);
	1299
	1300	out:
	1301	sensor->hwcfg.strobe_setup->trigger = 0;
	1302
	1303	return rval;
	1304	}
	1305
	1306	/* -----------------------------------------------------------------------------
	1307	* Power management
	1308	*/
	1309
	1310	static int ccs_write_msr_regs(struct ccs_sensor *sensor)
	1311	{
	1312	int rval;
	1313
	1314	rval = ccs_write_data_regs(sensor,
	1315	sensor->sdata.sensor_manufacturer_regs,
	1316	sensor->sdata.num_sensor_manufacturer_regs);
	1317	if (rval)
	1318	return rval;
	1319
	1320	return ccs_write_data_regs(sensor,
	1321	sensor->mdata.module_manufacturer_regs,
	1322	sensor->mdata.num_module_manufacturer_regs);
	1323	}
	1324
	1325	static int ccs_power_on(struct device *dev)
	1326	{
	1327	struct v4l2_subdev *subdev = dev_get_drvdata(dev);
	1328	struct ccs_subdev *ssd = to_ccs_subdev(subdev);
	1329	/*
	1330	* The sub-device related to the I2C device is always the
	1331	* source one, i.e. ssds[0].
	1332	*/
	1333	struct ccs_sensor *sensor =
	1334	container_of(ssd, struct ccs_sensor, ssds[0]);
	1335	const struct ccs_device *ccsdev = device_get_match_data(dev);
	1336	unsigned int sleep;
	1337	int rval;
	1338
	1339	rval = regulator_bulk_enable(ARRAY_SIZE(ccs_regulators),
	1340	sensor->regulators);
	1341	if (rval) {
	1342	dev_err(dev, "failed to enable vana regulator\n");
	1343	return rval;
	1344	}
	1345
	1346	rval = clk_prepare_enable(sensor->ext_clk);
	1347	if (rval < 0) {
	1348	dev_dbg(dev, "failed to enable xclk\n");
	1349	goto out_xclk_fail;
	1350	}
	1351
	1352	gpiod_set_value(sensor->reset, 0);
	1353	gpiod_set_value(sensor->xshutdown, 1);
	1354
	1355	if (ccsdev->flags & CCS_DEVICE_FLAG_IS_SMIA)
	1356	sleep = SMIAPP_RESET_DELAY(sensor->hwcfg.ext_clk);
	1357	else
	1358	sleep = 5000;
	1359
	1360	usleep_range(sleep, sleep);
	1361
	1362	/*
	1363	* Failures to respond to the address change command have been noticed.
	1364	* Those failures seem to be caused by the sensor requiring a longer
	1365	* boot time than advertised. An additional 10ms delay seems to work
	1366	* around the issue, but the SMIA++ I2C write retry hack makes the delay
	1367	* unnecessary. The failures need to be investigated to find a proper
	1368	* fix, and a delay will likely need to be added here if the I2C write
	1369	* retry hack is reverted before the root cause of the boot time issue
	1370	* is found.
	1371	*/
	1372
	1373	if (sensor->hwcfg.i2c_addr_alt) {
	1374	rval = ccs_change_cci_addr(sensor);
	1375	if (rval) {
	1376	dev_err(dev, "cci address change error\n");
	1377	goto out_cci_addr_fail;
	1378	}
	1379	}
	1380
	1381	rval = ccs_write(sensor, SOFTWARE_RESET, CCS_SOFTWARE_RESET_ON);
	1382	if (rval < 0) {
	1383	dev_err(dev, "software reset failed\n");
	1384	goto out_cci_addr_fail;
	1385	}
	1386
	1387	if (sensor->hwcfg.i2c_addr_alt) {
	1388	rval = ccs_change_cci_addr(sensor);
	1389	if (rval) {
	1390	dev_err(dev, "cci address change error\n");
	1391	goto out_cci_addr_fail;
	1392	}
	1393	}
	1394
	1395	rval = ccs_write(sensor, COMPRESSION_MODE,
	1396	CCS_COMPRESSION_MODE_DPCM_PCM_SIMPLE);
	1397	if (rval) {
	1398	dev_err(dev, "compression mode set failed\n");
	1399	goto out_cci_addr_fail;
	1400	}
	1401
	1402	rval = ccs_write(sensor, EXTCLK_FREQUENCY_MHZ,
	1403	sensor->hwcfg.ext_clk / (1000000 / (1 << 8)));
	1404	if (rval) {
	1405	dev_err(dev, "extclk frequency set failed\n");
	1406	goto out_cci_addr_fail;
	1407	}
	1408
	1409	rval = ccs_write(sensor, CSI_LANE_MODE, sensor->hwcfg.lanes - 1);
	1410	if (rval) {
	1411	dev_err(dev, "csi lane mode set failed\n");
	1412	goto out_cci_addr_fail;
	1413	}
	1414
	1415	rval = ccs_write(sensor, FAST_STANDBY_CTRL,
	1416	CCS_FAST_STANDBY_CTRL_FRAME_TRUNCATION);
	1417	if (rval) {
	1418	dev_err(dev, "fast standby set failed\n");
	1419	goto out_cci_addr_fail;
	1420	}
	1421
	1422	rval = ccs_write(sensor, CSI_SIGNALING_MODE,
	1423	sensor->hwcfg.csi_signalling_mode);
	1424	if (rval) {
	1425	dev_err(dev, "csi signalling mode set failed\n");
	1426	goto out_cci_addr_fail;
	1427	}
	1428
	1429	/* DPHY control done by sensor based on requested link rate */
	1430	rval = ccs_write(sensor, PHY_CTRL, CCS_PHY_CTRL_UI);
	1431	if (rval < 0)
	1432	goto out_cci_addr_fail;
	1433
	1434	rval = ccs_write_msr_regs(sensor);
	1435	if (rval)
	1436	goto out_cci_addr_fail;
	1437
	1438	rval = ccs_call_quirk(sensor, post_poweron);
	1439	if (rval) {
	1440	dev_err(dev, "post_poweron quirks failed\n");
	1441	goto out_cci_addr_fail;
	1442	}
	1443
	1444	return 0;
	1445
	1446	out_cci_addr_fail:
	1447	gpiod_set_value(sensor->reset, 1);
	1448	gpiod_set_value(sensor->xshutdown, 0);
	1449	clk_disable_unprepare(sensor->ext_clk);
	1450
	1451	out_xclk_fail:
	1452	regulator_bulk_disable(ARRAY_SIZE(ccs_regulators),
	1453	sensor->regulators);
	1454
	1455	return rval;
	1456	}
	1457
	1458	static int ccs_power_off(struct device *dev)
	1459	{
	1460	struct v4l2_subdev *subdev = dev_get_drvdata(dev);
	1461	struct ccs_subdev *ssd = to_ccs_subdev(subdev);
	1462	struct ccs_sensor *sensor =
	1463	container_of(ssd, struct ccs_sensor, ssds[0]);
	1464
	1465	/*
	1466	* Currently power/clock to lens are enable/disabled separately
	1467	* but they are essentially the same signals. So if the sensor is
	1468	* powered off while the lens is powered on the sensor does not
	1469	* really see a power off and next time the cci address change
	1470	* will fail. So do a soft reset explicitly here.
	1471	*/
	1472	if (sensor->hwcfg.i2c_addr_alt)
	1473	ccs_write(sensor, SOFTWARE_RESET, CCS_SOFTWARE_RESET_ON);
	1474
	1475	gpiod_set_value(sensor->reset, 1);
	1476	gpiod_set_value(sensor->xshutdown, 0);
	1477	clk_disable_unprepare(sensor->ext_clk);
	1478	usleep_range(5000, 5000);
	1479	regulator_bulk_disable(ARRAY_SIZE(ccs_regulators),
	1480	sensor->regulators);
	1481	sensor->streaming = false;
	1482
	1483	return 0;
	1484	}
	1485
	1486	/* -----------------------------------------------------------------------------
	1487	* Video stream management
	1488	*/
	1489
	1490	static int ccs_start_streaming(struct ccs_sensor *sensor)
	1491	{
	1492	struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
	1493	unsigned int binning_mode;
	1494	int rval;
	1495
	1496	mutex_lock(&sensor->mutex);
	1497
	1498	rval = ccs_write(sensor, CSI_DATA_FORMAT,
	1499	(sensor->csi_format->width << 8) \|
	1500	sensor->csi_format->compressed);
	1501	if (rval)
	1502	goto out;
	1503
	1504	/* Binning configuration */
	1505	if (sensor->binning_horizontal == 1 &&
	1506	sensor->binning_vertical == 1) {
	1507	binning_mode = 0;
	1508	} else {
	1509	u8 binning_type =
	1510	(sensor->binning_horizontal << 4)
	1511	\| sensor->binning_vertical;
	1512
	1513	rval = ccs_write(sensor, BINNING_TYPE, binning_type);
	1514	if (rval < 0)
	1515	goto out;
	1516
	1517	binning_mode = 1;
	1518	}
	1519	rval = ccs_write(sensor, BINNING_MODE, binning_mode);
	1520	if (rval < 0)
	1521	goto out;
	1522
	1523	/* Set up PLL */
	1524	rval = ccs_pll_configure(sensor);
	1525	if (rval)
	1526	goto out;
	1527
	1528	/* Analog crop start coordinates */
	1529	rval = ccs_write(sensor, X_ADDR_START,
	1530	sensor->pixel_array->crop[CCS_PA_PAD_SRC].left);
	1531	if (rval < 0)
	1532	goto out;
	1533
	1534	rval = ccs_write(sensor, Y_ADDR_START,
	1535	sensor->pixel_array->crop[CCS_PA_PAD_SRC].top);
	1536	if (rval < 0)
	1537	goto out;
	1538
	1539	/* Analog crop end coordinates */
	1540	rval = ccs_write(
	1541	sensor, X_ADDR_END,
	1542	sensor->pixel_array->crop[CCS_PA_PAD_SRC].left
	1543	+ sensor->pixel_array->crop[CCS_PA_PAD_SRC].width - 1);
	1544	if (rval < 0)
	1545	goto out;
	1546
	1547	rval = ccs_write(
	1548	sensor, Y_ADDR_END,
	1549	sensor->pixel_array->crop[CCS_PA_PAD_SRC].top
	1550	+ sensor->pixel_array->crop[CCS_PA_PAD_SRC].height - 1);
	1551	if (rval < 0)
	1552	goto out;
	1553
	1554	/*
	1555	* Output from pixel array, including blanking, is set using
	1556	* controls below. No need to set here.
	1557	*/
	1558
	1559	/* Digital crop */
	1560	if (CCS_LIM(sensor, DIGITAL_CROP_CAPABILITY)
	1561	== CCS_DIGITAL_CROP_CAPABILITY_INPUT_CROP) {
	1562	rval = ccs_write(
	1563	sensor, DIGITAL_CROP_X_OFFSET,
	1564	sensor->scaler->crop[CCS_PAD_SINK].left);
	1565	if (rval < 0)
	1566	goto out;
	1567
	1568	rval = ccs_write(
	1569	sensor, DIGITAL_CROP_Y_OFFSET,
	1570	sensor->scaler->crop[CCS_PAD_SINK].top);
	1571	if (rval < 0)
	1572	goto out;
	1573
	1574	rval = ccs_write(
	1575	sensor, DIGITAL_CROP_IMAGE_WIDTH,
	1576	sensor->scaler->crop[CCS_PAD_SINK].width);
	1577	if (rval < 0)
	1578	goto out;
	1579
	1580	rval = ccs_write(
	1581	sensor, DIGITAL_CROP_IMAGE_HEIGHT,
	1582	sensor->scaler->crop[CCS_PAD_SINK].height);
	1583	if (rval < 0)
	1584	goto out;
	1585	}
	1586
	1587	/* Scaling */
	1588	if (CCS_LIM(sensor, SCALING_CAPABILITY)
	1589	!= CCS_SCALING_CAPABILITY_NONE) {
	1590	rval = ccs_write(sensor, SCALING_MODE, sensor->scaling_mode);
	1591	if (rval < 0)
	1592	goto out;
	1593
	1594	rval = ccs_write(sensor, SCALE_M, sensor->scale_m);
	1595	if (rval < 0)
	1596	goto out;
	1597	}
	1598
	1599	/* Output size from sensor */
	1600	rval = ccs_write(sensor, X_OUTPUT_SIZE,
	1601	sensor->src->crop[CCS_PAD_SRC].width);
	1602	if (rval < 0)
	1603	goto out;
	1604	rval = ccs_write(sensor, Y_OUTPUT_SIZE,
	1605	sensor->src->crop[CCS_PAD_SRC].height);
	1606	if (rval < 0)
	1607	goto out;
	1608
	1609	if (CCS_LIM(sensor, FLASH_MODE_CAPABILITY) &
	1610	(CCS_FLASH_MODE_CAPABILITY_SINGLE_STROBE \|
	1611	SMIAPP_FLASH_MODE_CAPABILITY_MULTIPLE_STROBE) &&
	1612	sensor->hwcfg.strobe_setup != NULL &&
	1613	sensor->hwcfg.strobe_setup->trigger != 0) {
	1614	rval = ccs_setup_flash_strobe(sensor);
	1615	if (rval)
	1616	goto out;
	1617	}
	1618
	1619	rval = ccs_call_quirk(sensor, pre_streamon);
	1620	if (rval) {
	1621	dev_err(&client->dev, "pre_streamon quirks failed\n");
	1622	goto out;
	1623	}
	1624
	1625	rval = ccs_write(sensor, MODE_SELECT, CCS_MODE_SELECT_STREAMING);
	1626
	1627	out:
	1628	mutex_unlock(&sensor->mutex);
	1629
	1630	return rval;
	1631	}
	1632
	1633	static int ccs_stop_streaming(struct ccs_sensor *sensor)
	1634	{
	1635	struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
	1636	int rval;
	1637
	1638	mutex_lock(&sensor->mutex);
	1639	rval = ccs_write(sensor, MODE_SELECT, CCS_MODE_SELECT_SOFTWARE_STANDBY);
	1640	if (rval)
	1641	goto out;
	1642
	1643	rval = ccs_call_quirk(sensor, post_streamoff);
	1644	if (rval)
	1645	dev_err(&client->dev, "post_streamoff quirks failed\n");
	1646
	1647	out:
	1648	mutex_unlock(&sensor->mutex);
	1649	return rval;
	1650	}
	1651
	1652	/* -----------------------------------------------------------------------------
	1653	* V4L2 subdev video operations
	1654	*/
	1655
	1656	static int ccs_pm_get_init(struct ccs_sensor *sensor)
	1657	{
	1658	struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
	1659	int rval;
	1660
	1661	rval = pm_runtime_get_sync(&client->dev);
	1662	if (rval < 0) {
	1663	pm_runtime_put_noidle(&client->dev);
	1664
	1665	return rval;
	1666	} else if (!rval) {
	1667	rval = v4l2_ctrl_handler_setup(&sensor->pixel_array->
	1668	ctrl_handler);
	1669	if (rval)
	1670	return rval;
	1671
	1672	return v4l2_ctrl_handler_setup(&sensor->src->ctrl_handler);
	1673	}
	1674
	1675	return 0;
	1676	}
	1677
	1678	static int ccs_set_stream(struct v4l2_subdev *subdev, int enable)
	1679	{
	1680	struct ccs_sensor *sensor = to_ccs_sensor(subdev);
	1681	struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
	1682	int rval;
	1683
	1684	if (sensor->streaming == enable)
	1685	return 0;
	1686
	1687	if (!enable) {
	1688	ccs_stop_streaming(sensor);
	1689	sensor->streaming = false;
	1690	pm_runtime_mark_last_busy(&client->dev);
	1691	pm_runtime_put_autosuspend(&client->dev);
	1692
	1693	return 0;
	1694	}
	1695
	1696	rval = ccs_pm_get_init(sensor);
	1697	if (rval)
	1698	return rval;
	1699
	1700	sensor->streaming = true;
	1701
	1702	rval = ccs_start_streaming(sensor);
	1703	if (rval < 0) {
	1704	sensor->streaming = false;
	1705	pm_runtime_mark_last_busy(&client->dev);
	1706	pm_runtime_put_autosuspend(&client->dev);
	1707	}
	1708
	1709	return rval;
	1710	}
	1711
	1712	static int ccs_enum_mbus_code(struct v4l2_subdev *subdev,
	1713	struct v4l2_subdev_pad_config *cfg,
	1714	struct v4l2_subdev_mbus_code_enum *code)
	1715	{
	1716	struct i2c_client *client = v4l2_get_subdevdata(subdev);
	1717	struct ccs_sensor *sensor = to_ccs_sensor(subdev);
	1718	unsigned int i;
	1719	int idx = -1;
	1720	int rval = -EINVAL;
	1721
	1722	mutex_lock(&sensor->mutex);
	1723
	1724	dev_err(&client->dev, "subdev %s, pad %d, index %d\n",
	1725	subdev->name, code->pad, code->index);
	1726
	1727	if (subdev != &sensor->src->sd \|\| code->pad != CCS_PAD_SRC) {
	1728	if (code->index)
	1729	goto out;
	1730
	1731	code->code = sensor->internal_csi_format->code;
	1732	rval = 0;
	1733	goto out;
	1734	}
	1735
	1736	for (i = 0; i < ARRAY_SIZE(ccs_csi_data_formats); i++) {
	1737	if (sensor->mbus_frame_fmts & (1 << i))
	1738	idx++;
	1739
	1740	if (idx == code->index) {
	1741	code->code = ccs_csi_data_formats[i].code;
	1742	dev_err(&client->dev, "found index %d, i %d, code %x\n",
	1743	code->index, i, code->code);
	1744	rval = 0;
	1745	break;
	1746	}
	1747	}
	1748
	1749	out:
	1750	mutex_unlock(&sensor->mutex);
	1751
	1752	return rval;
	1753	}
	1754
	1755	static u32 __ccs_get_mbus_code(struct v4l2_subdev *subdev, unsigned int pad)
	1756	{
	1757	struct ccs_sensor *sensor = to_ccs_sensor(subdev);
	1758
	1759	if (subdev == &sensor->src->sd && pad == CCS_PAD_SRC)
	1760	return sensor->csi_format->code;
	1761	else
	1762	return sensor->internal_csi_format->code;
	1763	}
	1764
	1765	static int __ccs_get_format(struct v4l2_subdev *subdev,
	1766	struct v4l2_subdev_pad_config *cfg,
	1767	struct v4l2_subdev_format *fmt)
	1768	{
	1769	struct ccs_subdev *ssd = to_ccs_subdev(subdev);
	1770
	1771	if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
	1772	fmt->format = *v4l2_subdev_get_try_format(subdev, cfg,
	1773	fmt->pad);
	1774	} else {
	1775	struct v4l2_rect *r;
	1776
	1777	if (fmt->pad == ssd->source_pad)
	1778	r = &ssd->crop[ssd->source_pad];
	1779	else
	1780	r = &ssd->sink_fmt;
	1781
	1782	fmt->format.code = __ccs_get_mbus_code(subdev, fmt->pad);
	1783	fmt->format.width = r->width;
	1784	fmt->format.height = r->height;
	1785	fmt->format.field = V4L2_FIELD_NONE;
	1786	}
	1787
	1788	return 0;
	1789	}
	1790
	1791	static int ccs_get_format(struct v4l2_subdev *subdev,
	1792	struct v4l2_subdev_pad_config *cfg,
	1793	struct v4l2_subdev_format *fmt)
	1794	{
	1795	struct ccs_sensor *sensor = to_ccs_sensor(subdev);
	1796	int rval;
	1797
	1798	mutex_lock(&sensor->mutex);
	1799	rval = __ccs_get_format(subdev, cfg, fmt);
	1800	mutex_unlock(&sensor->mutex);
	1801
	1802	return rval;
	1803	}
	1804
	1805	static void ccs_get_crop_compose(struct v4l2_subdev *subdev,
	1806	struct v4l2_subdev_pad_config *cfg,
	1807	struct v4l2_rect **crops,
	1808	struct v4l2_rect **comps, int which)
	1809	{
	1810	struct ccs_subdev *ssd = to_ccs_subdev(subdev);
	1811	unsigned int i;
	1812
	1813	if (which == V4L2_SUBDEV_FORMAT_ACTIVE) {
	1814	if (crops)
	1815	for (i = 0; i < subdev->entity.num_pads; i++)
	1816	crops[i] = &ssd->crop[i];
	1817	if (comps)
	1818	*comps = &ssd->compose;
	1819	} else {
	1820	if (crops) {
	1821	for (i = 0; i < subdev->entity.num_pads; i++)
	1822	crops[i] = v4l2_subdev_get_try_crop(subdev,
	1823	cfg, i);
	1824	}
	1825	if (comps)
	1826	*comps = v4l2_subdev_get_try_compose(subdev, cfg,
	1827	CCS_PAD_SINK);
	1828	}
	1829	}
	1830
	1831	/* Changes require propagation only on sink pad. */
	1832	static void ccs_propagate(struct v4l2_subdev *subdev,
	1833	struct v4l2_subdev_pad_config *cfg, int which,
	1834	int target)
	1835	{
	1836	struct ccs_sensor *sensor = to_ccs_sensor(subdev);
	1837	struct ccs_subdev *ssd = to_ccs_subdev(subdev);
	1838	struct v4l2_rect comp, crops[CCS_PADS];
	1839
	1840	ccs_get_crop_compose(subdev, cfg, crops, &comp, which);
	1841
	1842	switch (target) {
	1843	case V4L2_SEL_TGT_CROP:
	1844	comp->width = crops[CCS_PAD_SINK]->width;
	1845	comp->height = crops[CCS_PAD_SINK]->height;
	1846	if (which == V4L2_SUBDEV_FORMAT_ACTIVE) {
	1847	if (ssd == sensor->scaler) {
	1848	sensor->scale_m = CCS_LIM(sensor, SCALER_N_MIN);
	1849	sensor->scaling_mode =
	1850	CCS_SCALING_MODE_NO_SCALING;
	1851	} else if (ssd == sensor->binner) {
	1852	sensor->binning_horizontal = 1;
	1853	sensor->binning_vertical = 1;
	1854	}
	1855	}
	1856	fallthrough;
	1857	case V4L2_SEL_TGT_COMPOSE:
	1858	crops[CCS_PAD_SRC] = comp;
	1859	break;
	1860	default:
	1861	WARN_ON_ONCE(1);
	1862	}
	1863	}
	1864
	1865	static const struct ccs_csi_data_format
	1866	ccs_validate_csi_data_format(struct ccs_sensor sensor, u32 code)
	1867	{
	1868	unsigned int i;
	1869
	1870	for (i = 0; i < ARRAY_SIZE(ccs_csi_data_formats); i++) {
	1871	if (sensor->mbus_frame_fmts & (1 << i) &&
	1872	ccs_csi_data_formats[i].code == code)
	1873	return &ccs_csi_data_formats[i];
	1874	}
	1875
	1876	return sensor->csi_format;
	1877	}
	1878
	1879	static int ccs_set_format_source(struct v4l2_subdev *subdev,
	1880	struct v4l2_subdev_pad_config *cfg,
	1881	struct v4l2_subdev_format *fmt)
	1882	{
	1883	struct ccs_sensor *sensor = to_ccs_sensor(subdev);
	1884	const struct ccs_csi_data_format *csi_format,
	1885	*old_csi_format = sensor->csi_format;
	1886	unsigned long *valid_link_freqs;
	1887	u32 code = fmt->format.code;
	1888	unsigned int i;
	1889	int rval;
	1890
	1891	rval = __ccs_get_format(subdev, cfg, fmt);
	1892	if (rval)
	1893	return rval;
	1894
	1895	/*
	1896	* Media bus code is changeable on src subdev's source pad. On
	1897	* other source pads we just get format here.
	1898	*/
	1899	if (subdev != &sensor->src->sd)
	1900	return 0;
	1901
	1902	csi_format = ccs_validate_csi_data_format(sensor, code);
	1903
	1904	fmt->format.code = csi_format->code;
	1905
	1906	if (fmt->which != V4L2_SUBDEV_FORMAT_ACTIVE)
	1907	return 0;
	1908
	1909	sensor->csi_format = csi_format;
	1910
	1911	if (csi_format->width != old_csi_format->width)
	1912	for (i = 0; i < ARRAY_SIZE(sensor->test_data); i++)
	1913	__v4l2_ctrl_modify_range(
	1914	sensor->test_data[i], 0,
	1915	(1 << csi_format->width) - 1, 1, 0);
	1916
	1917	if (csi_format->compressed == old_csi_format->compressed)
	1918	return 0;
	1919
	1920	valid_link_freqs =
	1921	&sensor->valid_link_freqs[sensor->csi_format->compressed
	1922	- sensor->compressed_min_bpp];
	1923
	1924	__v4l2_ctrl_modify_range(
	1925	sensor->link_freq, 0,
	1926	__fls(valid_link_freqs), ~valid_link_freqs,
	1927	__ffs(*valid_link_freqs));
	1928
	1929	return ccs_pll_update(sensor);
	1930	}
	1931
	1932	static int ccs_set_format(struct v4l2_subdev *subdev,
	1933	struct v4l2_subdev_pad_config *cfg,
	1934	struct v4l2_subdev_format *fmt)
	1935	{
	1936	struct ccs_sensor *sensor = to_ccs_sensor(subdev);
	1937	struct ccs_subdev *ssd = to_ccs_subdev(subdev);
	1938	struct v4l2_rect *crops[CCS_PADS];
	1939
	1940	mutex_lock(&sensor->mutex);
	1941
	1942	if (fmt->pad == ssd->source_pad) {
	1943	int rval;
	1944
	1945	rval = ccs_set_format_source(subdev, cfg, fmt);
	1946
	1947	mutex_unlock(&sensor->mutex);
	1948
	1949	return rval;
	1950	}
	1951
	1952	/* Sink pad. Width and height are changeable here. */
	1953	fmt->format.code = __ccs_get_mbus_code(subdev, fmt->pad);
	1954	fmt->format.width &= ~1;
	1955	fmt->format.height &= ~1;
	1956	fmt->format.field = V4L2_FIELD_NONE;
	1957
	1958	fmt->format.width =
	1959	clamp(fmt->format.width,
	1960	CCS_LIM(sensor, MIN_X_OUTPUT_SIZE),
	1961	CCS_LIM(sensor, MAX_X_OUTPUT_SIZE));
	1962	fmt->format.height =
	1963	clamp(fmt->format.height,
	1964	CCS_LIM(sensor, MIN_Y_OUTPUT_SIZE),
	1965	CCS_LIM(sensor, MAX_Y_OUTPUT_SIZE));
	1966
	1967	ccs_get_crop_compose(subdev, cfg, crops, NULL, fmt->which);
	1968
	1969	crops[ssd->sink_pad]->left = 0;
	1970	crops[ssd->sink_pad]->top = 0;
	1971	crops[ssd->sink_pad]->width = fmt->format.width;
	1972	crops[ssd->sink_pad]->height = fmt->format.height;
	1973	if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE)
	1974	ssd->sink_fmt = *crops[ssd->sink_pad];
	1975	ccs_propagate(subdev, cfg, fmt->which, V4L2_SEL_TGT_CROP);
	1976
	1977	mutex_unlock(&sensor->mutex);
	1978
	1979	return 0;
	1980	}
	1981
	1982	/*
	1983	* Calculate goodness of scaled image size compared to expected image
	1984	* size and flags provided.
	1985	*/
	1986	#define SCALING_GOODNESS 100000
	1987	#define SCALING_GOODNESS_EXTREME 100000000
	1988	static int scaling_goodness(struct v4l2_subdev *subdev, int w, int ask_w,
	1989	int h, int ask_h, u32 flags)
	1990	{
	1991	struct ccs_sensor *sensor = to_ccs_sensor(subdev);
	1992	struct i2c_client *client = v4l2_get_subdevdata(subdev);
	1993	int val = 0;
	1994
	1995	w &= ~1;
	1996	ask_w &= ~1;
	1997	h &= ~1;
	1998	ask_h &= ~1;
	1999
	2000	if (flags & V4L2_SEL_FLAG_GE) {
	2001	if (w < ask_w)
	2002	val -= SCALING_GOODNESS;
	2003	if (h < ask_h)
	2004	val -= SCALING_GOODNESS;
	2005	}
	2006
	2007	if (flags & V4L2_SEL_FLAG_LE) {
	2008	if (w > ask_w)
	2009	val -= SCALING_GOODNESS;
	2010	if (h > ask_h)
	2011	val -= SCALING_GOODNESS;
	2012	}
	2013
	2014	val -= abs(w - ask_w);
	2015	val -= abs(h - ask_h);
	2016
	2017	if (w < CCS_LIM(sensor, MIN_X_OUTPUT_SIZE))
	2018	val -= SCALING_GOODNESS_EXTREME;
	2019
	2020	dev_dbg(&client->dev, "w %d ask_w %d h %d ask_h %d goodness %d\n",
	2021	w, ask_w, h, ask_h, val);
	2022
	2023	return val;
	2024	}
	2025
	2026	static void ccs_set_compose_binner(struct v4l2_subdev *subdev,
	2027	struct v4l2_subdev_pad_config *cfg,
	2028	struct v4l2_subdev_selection *sel,
	2029	struct v4l2_rect **crops,
	2030	struct v4l2_rect *comp)
	2031	{
	2032	struct ccs_sensor *sensor = to_ccs_sensor(subdev);
	2033	unsigned int i;
	2034	unsigned int binh = 1, binv = 1;
	2035	int best = scaling_goodness(
	2036	subdev,
	2037	crops[CCS_PAD_SINK]->width, sel->r.width,
	2038	crops[CCS_PAD_SINK]->height, sel->r.height, sel->flags);
	2039
	2040	for (i = 0; i < sensor->nbinning_subtypes; i++) {
	2041	int this = scaling_goodness(
	2042	subdev,
	2043	crops[CCS_PAD_SINK]->width
	2044	/ sensor->binning_subtypes[i].horizontal,
	2045	sel->r.width,
	2046	crops[CCS_PAD_SINK]->height
	2047	/ sensor->binning_subtypes[i].vertical,
	2048	sel->r.height, sel->flags);
	2049
	2050	if (this > best) {
	2051	binh = sensor->binning_subtypes[i].horizontal;
	2052	binv = sensor->binning_subtypes[i].vertical;
	2053	best = this;
	2054	}
	2055	}
	2056	if (sel->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
	2057	sensor->binning_vertical = binv;
	2058	sensor->binning_horizontal = binh;
	2059	}
	2060
	2061	sel->r.width = (crops[CCS_PAD_SINK]->width / binh) & ~1;
	2062	sel->r.height = (crops[CCS_PAD_SINK]->height / binv) & ~1;
	2063	}
	2064
	2065	/*
	2066	* Calculate best scaling ratio and mode for given output resolution.
	2067	*
	2068	* Try all of these: horizontal ratio, vertical ratio and smallest
	2069	* size possible (horizontally).
	2070	*
	2071	* Also try whether horizontal scaler or full scaler gives a better
	2072	* result.
	2073	*/
	2074	static void ccs_set_compose_scaler(struct v4l2_subdev *subdev,
	2075	struct v4l2_subdev_pad_config *cfg,
	2076	struct v4l2_subdev_selection *sel,
	2077	struct v4l2_rect **crops,
	2078	struct v4l2_rect *comp)
	2079	{
	2080	struct i2c_client *client = v4l2_get_subdevdata(subdev);
	2081	struct ccs_sensor *sensor = to_ccs_sensor(subdev);
	2082	u32 min, max, a, b, max_m;
	2083	u32 scale_m = CCS_LIM(sensor, SCALER_N_MIN);
	2084	int mode = CCS_SCALING_MODE_HORIZONTAL;
	2085	u32 try[4];
	2086	u32 ntry = 0;
	2087	unsigned int i;
	2088	int best = INT_MIN;
	2089
	2090	sel->r.width = min_t(unsigned int, sel->r.width,
	2091	crops[CCS_PAD_SINK]->width);
	2092	sel->r.height = min_t(unsigned int, sel->r.height,
	2093	crops[CCS_PAD_SINK]->height);
	2094
	2095	a = crops[CCS_PAD_SINK]->width
	2096	* CCS_LIM(sensor, SCALER_N_MIN) / sel->r.width;
	2097	b = crops[CCS_PAD_SINK]->height
	2098	* CCS_LIM(sensor, SCALER_N_MIN) / sel->r.height;
	2099	max_m = crops[CCS_PAD_SINK]->width
	2100	* CCS_LIM(sensor, SCALER_N_MIN)
	2101	/ CCS_LIM(sensor, MIN_X_OUTPUT_SIZE);
	2102
	2103	a = clamp(a, CCS_LIM(sensor, SCALER_M_MIN),
	2104	CCS_LIM(sensor, SCALER_M_MAX));
	2105	b = clamp(b, CCS_LIM(sensor, SCALER_M_MIN),
	2106	CCS_LIM(sensor, SCALER_M_MAX));
	2107	max_m = clamp(max_m, CCS_LIM(sensor, SCALER_M_MIN),
	2108	CCS_LIM(sensor, SCALER_M_MAX));
	2109
	2110	dev_dbg(&client->dev, "scaling: a %d b %d max_m %d\n", a, b, max_m);
	2111
	2112	min = min(max_m, min(a, b));
	2113	max = min(max_m, max(a, b));
	2114
	2115	try[ntry] = min;
	2116	ntry++;
	2117	if (min != max) {
	2118	try[ntry] = max;
	2119	ntry++;
	2120	}
	2121	if (max != max_m) {
	2122	try[ntry] = min + 1;
	2123	ntry++;
	2124	if (min != max) {
	2125	try[ntry] = max + 1;
	2126	ntry++;
	2127	}
	2128	}
	2129
	2130	for (i = 0; i < ntry; i++) {
	2131	int this = scaling_goodness(
	2132	subdev,
	2133	crops[CCS_PAD_SINK]->width
	2134	/ try[i] * CCS_LIM(sensor, SCALER_N_MIN),
	2135	sel->r.width,
	2136	crops[CCS_PAD_SINK]->height,
	2137	sel->r.height,
	2138	sel->flags);
	2139
	2140	dev_dbg(&client->dev, "trying factor %d (%d)\n", try[i], i);
	2141
	2142	if (this > best) {
	2143	scale_m = try[i];
	2144	mode = CCS_SCALING_MODE_HORIZONTAL;
	2145	best = this;
	2146	}
	2147
	2148	if (CCS_LIM(sensor, SCALING_CAPABILITY)
	2149	== CCS_SCALING_CAPABILITY_HORIZONTAL)
	2150	continue;
	2151
	2152	this = scaling_goodness(
	2153	subdev, crops[CCS_PAD_SINK]->width
	2154	/ try[i]
	2155	* CCS_LIM(sensor, SCALER_N_MIN),
	2156	sel->r.width,
	2157	crops[CCS_PAD_SINK]->height
	2158	/ try[i]
	2159	* CCS_LIM(sensor, SCALER_N_MIN),
	2160	sel->r.height,
	2161	sel->flags);
	2162
	2163	if (this > best) {
	2164	scale_m = try[i];
	2165	mode = SMIAPP_SCALING_MODE_BOTH;
	2166	best = this;
	2167	}
	2168	}
	2169
	2170	sel->r.width =
	2171	(crops[CCS_PAD_SINK]->width
	2172	/ scale_m
	2173	* CCS_LIM(sensor, SCALER_N_MIN)) & ~1;
	2174	if (mode == SMIAPP_SCALING_MODE_BOTH)
	2175	sel->r.height =
	2176	(crops[CCS_PAD_SINK]->height
	2177	/ scale_m
	2178	* CCS_LIM(sensor, SCALER_N_MIN))
	2179	& ~1;
	2180	else
	2181	sel->r.height = crops[CCS_PAD_SINK]->height;
	2182
	2183	if (sel->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
	2184	sensor->scale_m = scale_m;
	2185	sensor->scaling_mode = mode;
	2186	}
	2187	}
	2188	/* We're only called on source pads. This function sets scaling. */
	2189	static int ccs_set_compose(struct v4l2_subdev *subdev,
	2190	struct v4l2_subdev_pad_config *cfg,
	2191	struct v4l2_subdev_selection *sel)
	2192	{
	2193	struct ccs_sensor *sensor = to_ccs_sensor(subdev);
	2194	struct ccs_subdev *ssd = to_ccs_subdev(subdev);
	2195	struct v4l2_rect comp, crops[CCS_PADS];
	2196
	2197	ccs_get_crop_compose(subdev, cfg, crops, &comp, sel->which);
	2198
	2199	sel->r.top = 0;
	2200	sel->r.left = 0;
	2201
	2202	if (ssd == sensor->binner)
	2203	ccs_set_compose_binner(subdev, cfg, sel, crops, comp);
	2204	else
	2205	ccs_set_compose_scaler(subdev, cfg, sel, crops, comp);
	2206
	2207	*comp = sel->r;
	2208	ccs_propagate(subdev, cfg, sel->which, V4L2_SEL_TGT_COMPOSE);
	2209
	2210	if (sel->which == V4L2_SUBDEV_FORMAT_ACTIVE)
	2211	return ccs_pll_blanking_update(sensor);
	2212
	2213	return 0;
	2214	}
	2215
	2216	static int __ccs_sel_supported(struct v4l2_subdev *subdev,
	2217	struct v4l2_subdev_selection *sel)
	2218	{
	2219	struct ccs_sensor *sensor = to_ccs_sensor(subdev);
	2220	struct ccs_subdev *ssd = to_ccs_subdev(subdev);
	2221
	2222	/* We only implement crop in three places. */
	2223	switch (sel->target) {
	2224	case V4L2_SEL_TGT_CROP:
	2225	case V4L2_SEL_TGT_CROP_BOUNDS:
	2226	if (ssd == sensor->pixel_array && sel->pad == CCS_PA_PAD_SRC)
	2227	return 0;
	2228	if (ssd == sensor->src && sel->pad == CCS_PAD_SRC)
	2229	return 0;
	2230	if (ssd == sensor->scaler && sel->pad == CCS_PAD_SINK &&
	2231	CCS_LIM(sensor, DIGITAL_CROP_CAPABILITY)
	2232	== CCS_DIGITAL_CROP_CAPABILITY_INPUT_CROP)
	2233	return 0;
	2234	return -EINVAL;
	2235	case V4L2_SEL_TGT_NATIVE_SIZE:
	2236	if (ssd == sensor->pixel_array && sel->pad == CCS_PA_PAD_SRC)
	2237	return 0;
	2238	return -EINVAL;
	2239	case V4L2_SEL_TGT_COMPOSE:
	2240	case V4L2_SEL_TGT_COMPOSE_BOUNDS:
	2241	if (sel->pad == ssd->source_pad)
	2242	return -EINVAL;
	2243	if (ssd == sensor->binner)
	2244	return 0;
	2245	if (ssd == sensor->scaler && CCS_LIM(sensor, SCALING_CAPABILITY)
	2246	!= CCS_SCALING_CAPABILITY_NONE)
	2247	return 0;
	2248	fallthrough;
	2249	default:
	2250	return -EINVAL;
	2251	}
	2252	}
	2253
	2254	static int ccs_set_crop(struct v4l2_subdev *subdev,
	2255	struct v4l2_subdev_pad_config *cfg,
	2256	struct v4l2_subdev_selection *sel)
	2257	{
	2258	struct ccs_sensor *sensor = to_ccs_sensor(subdev);
	2259	struct ccs_subdev *ssd = to_ccs_subdev(subdev);
	2260	struct v4l2_rect src_size, crops[CCS_PADS];
	2261	struct v4l2_rect _r;
	2262
	2263	ccs_get_crop_compose(subdev, cfg, crops, NULL, sel->which);
	2264
	2265	if (sel->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
	2266	if (sel->pad == ssd->sink_pad)
	2267	src_size = &ssd->sink_fmt;
	2268	else
	2269	src_size = &ssd->compose;
	2270	} else {
	2271	if (sel->pad == ssd->sink_pad) {
	2272	_r.left = 0;
	2273	_r.top = 0;
	2274	_r.width = v4l2_subdev_get_try_format(subdev, cfg,
	2275	sel->pad)
	2276	->width;
	2277	_r.height = v4l2_subdev_get_try_format(subdev, cfg,
	2278	sel->pad)
	2279	->height;
	2280	src_size = &_r;
	2281	} else {
	2282	src_size = v4l2_subdev_get_try_compose(
	2283	subdev, cfg, ssd->sink_pad);
	2284	}
	2285	}
	2286
	2287	if (ssd == sensor->src && sel->pad == CCS_PAD_SRC) {
	2288	sel->r.left = 0;
	2289	sel->r.top = 0;
	2290	}
	2291
	2292	sel->r.width = min(sel->r.width, src_size->width);
	2293	sel->r.height = min(sel->r.height, src_size->height);
	2294
	2295	sel->r.left = min_t(int, sel->r.left, src_size->width - sel->r.width);
	2296	sel->r.top = min_t(int, sel->r.top, src_size->height - sel->r.height);
	2297
	2298	*crops[sel->pad] = sel->r;
	2299
	2300	if (ssd != sensor->pixel_array && sel->pad == CCS_PAD_SINK)
	2301	ccs_propagate(subdev, cfg, sel->which, V4L2_SEL_TGT_CROP);
	2302
	2303	return 0;
	2304	}
	2305
	2306	static void ccs_get_native_size(struct ccs_subdev ssd, struct v4l2_rect r)
	2307	{
	2308	r->top = 0;
	2309	r->left = 0;
	2310	r->width = CCS_LIM(ssd->sensor, X_ADDR_MAX) + 1;
	2311	r->height = CCS_LIM(ssd->sensor, Y_ADDR_MAX) + 1;
	2312	}
	2313
	2314	static int __ccs_get_selection(struct v4l2_subdev *subdev,
	2315	struct v4l2_subdev_pad_config *cfg,
	2316	struct v4l2_subdev_selection *sel)
	2317	{
	2318	struct ccs_sensor *sensor = to_ccs_sensor(subdev);
	2319	struct ccs_subdev *ssd = to_ccs_subdev(subdev);
	2320	struct v4l2_rect comp, crops[CCS_PADS];
	2321	struct v4l2_rect sink_fmt;
	2322	int ret;
	2323
	2324	ret = __ccs_sel_supported(subdev, sel);
	2325	if (ret)
	2326	return ret;
	2327
	2328	ccs_get_crop_compose(subdev, cfg, crops, &comp, sel->which);
	2329
	2330	if (sel->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
	2331	sink_fmt = ssd->sink_fmt;
	2332	} else {
	2333	struct v4l2_mbus_framefmt *fmt =
	2334	v4l2_subdev_get_try_format(subdev, cfg, ssd->sink_pad);
	2335
	2336	sink_fmt.left = 0;
	2337	sink_fmt.top = 0;
	2338	sink_fmt.width = fmt->width;
	2339	sink_fmt.height = fmt->height;
	2340	}
	2341
	2342	switch (sel->target) {
	2343	case V4L2_SEL_TGT_CROP_BOUNDS:
	2344	case V4L2_SEL_TGT_NATIVE_SIZE:
	2345	if (ssd == sensor->pixel_array)
	2346	ccs_get_native_size(ssd, &sel->r);
	2347	else if (sel->pad == ssd->sink_pad)
	2348	sel->r = sink_fmt;
	2349	else
	2350	sel->r = *comp;
	2351	break;
	2352	case V4L2_SEL_TGT_CROP:
	2353	case V4L2_SEL_TGT_COMPOSE_BOUNDS:
	2354	sel->r = *crops[sel->pad];
	2355	break;
	2356	case V4L2_SEL_TGT_COMPOSE:
	2357	sel->r = *comp;
	2358	break;
	2359	}
	2360
	2361	return 0;
	2362	}
	2363
	2364	static int ccs_get_selection(struct v4l2_subdev *subdev,
	2365	struct v4l2_subdev_pad_config *cfg,
	2366	struct v4l2_subdev_selection *sel)
	2367	{
	2368	struct ccs_sensor *sensor = to_ccs_sensor(subdev);
	2369	int rval;
	2370
	2371	mutex_lock(&sensor->mutex);
	2372	rval = __ccs_get_selection(subdev, cfg, sel);
	2373	mutex_unlock(&sensor->mutex);
	2374
	2375	return rval;
	2376	}
	2377
	2378	static int ccs_set_selection(struct v4l2_subdev *subdev,
	2379	struct v4l2_subdev_pad_config *cfg,
	2380	struct v4l2_subdev_selection *sel)
	2381	{
	2382	struct ccs_sensor *sensor = to_ccs_sensor(subdev);
	2383	int ret;
	2384
	2385	ret = __ccs_sel_supported(subdev, sel);
	2386	if (ret)
	2387	return ret;
	2388
	2389	mutex_lock(&sensor->mutex);
	2390
	2391	sel->r.left = max(0, sel->r.left & ~1);
	2392	sel->r.top = max(0, sel->r.top & ~1);
	2393	sel->r.width = CCS_ALIGN_DIM(sel->r.width, sel->flags);
	2394	sel->r.height = CCS_ALIGN_DIM(sel->r.height, sel->flags);
	2395
	2396	sel->r.width = max_t(unsigned int, CCS_LIM(sensor, MIN_X_OUTPUT_SIZE),
	2397	sel->r.width);
	2398	sel->r.height = max_t(unsigned int, CCS_LIM(sensor, MIN_Y_OUTPUT_SIZE),
	2399	sel->r.height);
	2400
	2401	switch (sel->target) {
	2402	case V4L2_SEL_TGT_CROP:
	2403	ret = ccs_set_crop(subdev, cfg, sel);
	2404	break;
	2405	case V4L2_SEL_TGT_COMPOSE:
	2406	ret = ccs_set_compose(subdev, cfg, sel);
	2407	break;
	2408	default:
	2409	ret = -EINVAL;
	2410	}
	2411
	2412	mutex_unlock(&sensor->mutex);
	2413	return ret;
	2414	}
	2415
	2416	static int ccs_get_skip_frames(struct v4l2_subdev subdev, u32 frames)
	2417	{
	2418	struct ccs_sensor *sensor = to_ccs_sensor(subdev);
	2419
	2420	*frames = sensor->frame_skip;
	2421	return 0;
	2422	}
	2423
	2424	static int ccs_get_skip_top_lines(struct v4l2_subdev subdev, u32 lines)
	2425	{
	2426	struct ccs_sensor *sensor = to_ccs_sensor(subdev);
	2427
	2428	*lines = sensor->image_start;
	2429
	2430	return 0;
	2431	}
	2432
	2433	/* -----------------------------------------------------------------------------
	2434	* sysfs attributes
	2435	*/
	2436
	2437	static ssize_t
	2438	ccs_sysfs_nvm_read(struct device dev, struct device_attribute attr,
	2439	char *buf)
	2440	{
	2441	struct v4l2_subdev *subdev = i2c_get_clientdata(to_i2c_client(dev));
	2442	struct i2c_client *client = v4l2_get_subdevdata(subdev);
	2443	struct ccs_sensor *sensor = to_ccs_sensor(subdev);
	2444	int rval;
	2445
	2446	if (!sensor->dev_init_done)
	2447	return -EBUSY;
	2448
	2449	rval = ccs_pm_get_init(sensor);
	2450	if (rval < 0)
	2451	return -ENODEV;
	2452
	2453	rval = ccs_read_nvm(sensor, buf, PAGE_SIZE);
	2454	if (rval < 0) {
	2455	pm_runtime_put(&client->dev);
	2456	dev_err(&client->dev, "nvm read failed\n");
	2457	return -ENODEV;
	2458	}
	2459
	2460	pm_runtime_mark_last_busy(&client->dev);
	2461	pm_runtime_put_autosuspend(&client->dev);
	2462
	2463	/*
	2464	* NVM is still way below a PAGE_SIZE, so we can safely
	2465	* assume this for now.
	2466	*/
	2467	return rval;
	2468	}
	2469	static DEVICE_ATTR(nvm, S_IRUGO, ccs_sysfs_nvm_read, NULL);
	2470
	2471	static ssize_t
	2472	ccs_sysfs_ident_read(struct device dev, struct device_attribute attr,
	2473	char *buf)
	2474	{
	2475	struct v4l2_subdev *subdev = i2c_get_clientdata(to_i2c_client(dev));
	2476	struct ccs_sensor *sensor = to_ccs_sensor(subdev);
	2477	struct ccs_module_info *minfo = &sensor->minfo;
	2478
	2479	if (minfo->mipi_manufacturer_id)
	2480	return snprintf(buf, PAGE_SIZE, "%4.4x%4.4x%2.2x\n",
	2481	minfo->mipi_manufacturer_id, minfo->model_id,
	2482	minfo->revision_number) + 1;
	2483	else
	2484	return snprintf(buf, PAGE_SIZE, "%2.2x%4.4x%2.2x\n",
	2485	minfo->smia_manufacturer_id, minfo->model_id,
	2486	minfo->revision_number) + 1;
	2487	}
	2488
	2489	static DEVICE_ATTR(ident, S_IRUGO, ccs_sysfs_ident_read, NULL);
	2490
	2491	/* -----------------------------------------------------------------------------
	2492	* V4L2 subdev core operations
	2493	*/
	2494
	2495	static int ccs_identify_module(struct ccs_sensor *sensor)
	2496	{
	2497	struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
	2498	struct ccs_module_info *minfo = &sensor->minfo;
	2499	unsigned int i;
	2500	u32 rev;
	2501	int rval = 0;
	2502
	2503	/* Module info */
	2504	rval = ccs_read(sensor, MODULE_MANUFACTURER_ID,
	2505	&minfo->mipi_manufacturer_id);
	2506	if (!rval && !minfo->mipi_manufacturer_id)
	2507	rval = ccs_read_addr_8only(sensor,
	2508	SMIAPP_REG_U8_MANUFACTURER_ID,
	2509	&minfo->smia_manufacturer_id);
	2510	if (!rval)
	2511	rval = ccs_read_addr_8only(sensor, CCS_R_MODULE_MODEL_ID,
	2512	&minfo->model_id);
	2513	if (!rval)
	2514	rval = ccs_read_addr_8only(sensor,
	2515	CCS_R_MODULE_REVISION_NUMBER_MAJOR,
	2516	&rev);
	2517	if (!rval) {
	2518	rval = ccs_read_addr_8only(sensor,
	2519	CCS_R_MODULE_REVISION_NUMBER_MINOR,
	2520	&minfo->revision_number);
	2521	minfo->revision_number \|= rev << 8;
	2522	}
	2523	if (!rval)
	2524	rval = ccs_read_addr_8only(sensor, CCS_R_MODULE_DATE_YEAR,
	2525	&minfo->module_year);
	2526	if (!rval)
	2527	rval = ccs_read_addr_8only(sensor, CCS_R_MODULE_DATE_MONTH,
	2528	&minfo->module_month);
	2529	if (!rval)
	2530	rval = ccs_read_addr_8only(sensor, CCS_R_MODULE_DATE_DAY,
	2531	&minfo->module_day);
	2532
	2533	/* Sensor info */
	2534	if (!rval)
	2535	rval = ccs_read(sensor, SENSOR_MANUFACTURER_ID,
	2536	&minfo->sensor_mipi_manufacturer_id);
	2537	if (!rval && !minfo->sensor_mipi_manufacturer_id)
	2538	rval = ccs_read_addr_8only(sensor,
	2539	CCS_R_SENSOR_MANUFACTURER_ID,
	2540	&minfo->sensor_smia_manufacturer_id);
	2541	if (!rval)
	2542	rval = ccs_read_addr_8only(sensor,
	2543	CCS_R_SENSOR_MODEL_ID,
	2544	&minfo->sensor_model_id);
	2545	if (!rval)
	2546	rval = ccs_read_addr_8only(sensor,
	2547	CCS_R_SENSOR_REVISION_NUMBER,
	2548	&minfo->sensor_revision_number);
	2549	if (!rval)
	2550	rval = ccs_read_addr_8only(sensor,
	2551	CCS_R_SENSOR_FIRMWARE_VERSION,
	2552	&minfo->sensor_firmware_version);
	2553
	2554	/* SMIA */
	2555	if (!rval)
	2556	rval = ccs_read(sensor, MIPI_CCS_VERSION, &minfo->ccs_version);
	2557	if (!rval && !minfo->ccs_version)
	2558	rval = ccs_read_addr_8only(sensor, SMIAPP_REG_U8_SMIA_VERSION,
	2559	&minfo->smia_version);
	2560	if (!rval && !minfo->ccs_version)
	2561	rval = ccs_read_addr_8only(sensor, SMIAPP_REG_U8_SMIAPP_VERSION,
	2562	&minfo->smiapp_version);
	2563
	2564	if (rval) {
	2565	dev_err(&client->dev, "sensor detection failed\n");
	2566	return -ENODEV;
	2567	}
	2568
	2569	if (minfo->mipi_manufacturer_id)
	2570	dev_dbg(&client->dev, "MIPI CCS module 0x%4.4x-0x%4.4x\n",
	2571	minfo->mipi_manufacturer_id, minfo->model_id);
	2572	else
	2573	dev_dbg(&client->dev, "SMIA module 0x%2.2x-0x%4.4x\n",
	2574	minfo->smia_manufacturer_id, minfo->model_id);
	2575
	2576	dev_dbg(&client->dev,
	2577	"module revision 0x%4.4x date %2.2d-%2.2d-%2.2d\n",
	2578	minfo->revision_number, minfo->module_year, minfo->module_month,
	2579	minfo->module_day);
	2580
	2581	if (minfo->sensor_mipi_manufacturer_id)
	2582	dev_dbg(&client->dev, "MIPI CCS sensor 0x%4.4x-0x%4.4x\n",
	2583	minfo->sensor_mipi_manufacturer_id,
	2584	minfo->sensor_model_id);
	2585	else
	2586	dev_dbg(&client->dev, "SMIA sensor 0x%2.2x-0x%4.4x\n",
	2587	minfo->sensor_smia_manufacturer_id,
	2588	minfo->sensor_model_id);
	2589
	2590	dev_dbg(&client->dev,
	2591	"sensor revision 0x%2.2x firmware version 0x%2.2x\n",
	2592	minfo->sensor_revision_number, minfo->sensor_firmware_version);
	2593
	2594	if (minfo->ccs_version) {
	2595	dev_dbg(&client->dev, "MIPI CCS version %u.%u",
	2596	(minfo->ccs_version & CCS_MIPI_CCS_VERSION_MAJOR_MASK)
	2597	>> CCS_MIPI_CCS_VERSION_MAJOR_SHIFT,
	2598	(minfo->ccs_version & CCS_MIPI_CCS_VERSION_MINOR_MASK));
	2599	minfo->name = CCS_NAME;
	2600	} else {
	2601	dev_dbg(&client->dev,
	2602	"smia version %2.2d smiapp version %2.2d\n",
	2603	minfo->smia_version, minfo->smiapp_version);
	2604	minfo->name = SMIAPP_NAME;
	2605	}
	2606
	2607	/*
	2608	* Some modules have bad data in the lvalues below. Hope the
	2609	* rvalues have better stuff. The lvalues are module
	2610	* parameters whereas the rvalues are sensor parameters.
	2611	*/
	2612	if (minfo->sensor_smia_manufacturer_id &&
	2613	!minfo->smia_manufacturer_id && !minfo->model_id) {
	2614	minfo->smia_manufacturer_id =
	2615	minfo->sensor_smia_manufacturer_id;
	2616	minfo->model_id = minfo->sensor_model_id;
	2617	minfo->revision_number = minfo->sensor_revision_number;
	2618	}
	2619
	2620	for (i = 0; i < ARRAY_SIZE(ccs_module_idents); i++) {
	2621	if (ccs_module_idents[i].mipi_manufacturer_id &&
	2622	ccs_module_idents[i].mipi_manufacturer_id
	2623	!= minfo->mipi_manufacturer_id)
	2624	continue;
	2625	if (ccs_module_idents[i].smia_manufacturer_id &&
	2626	ccs_module_idents[i].smia_manufacturer_id
	2627	!= minfo->smia_manufacturer_id)
	2628	continue;
	2629	if (ccs_module_idents[i].model_id != minfo->model_id)
	2630	continue;
	2631	if (ccs_module_idents[i].flags
	2632	& CCS_MODULE_IDENT_FLAG_REV_LE) {
	2633	if (ccs_module_idents[i].revision_number_major
	2634	< (minfo->revision_number >> 8))
	2635	continue;
	2636	} else {
	2637	if (ccs_module_idents[i].revision_number_major
	2638	!= (minfo->revision_number >> 8))
	2639	continue;
	2640	}
	2641
	2642	minfo->name = ccs_module_idents[i].name;
	2643	minfo->quirk = ccs_module_idents[i].quirk;
	2644	break;
	2645	}
	2646
	2647	if (i >= ARRAY_SIZE(ccs_module_idents))
	2648	dev_warn(&client->dev,
	2649	"no quirks for this module; let's hope it's fully compliant\n");
	2650
	2651	dev_dbg(&client->dev, "the sensor is called %s\n", minfo->name);
	2652
	2653	return 0;
	2654	}
	2655
	2656	static const struct v4l2_subdev_ops ccs_ops;
	2657	static const struct v4l2_subdev_internal_ops ccs_internal_ops;
	2658	static const struct media_entity_operations ccs_entity_ops;
	2659
	2660	static int ccs_register_subdev(struct ccs_sensor *sensor,
	2661	struct ccs_subdev *ssd,
	2662	struct ccs_subdev *sink_ssd,
	2663	u16 source_pad, u16 sink_pad, u32 link_flags)
	2664	{
	2665	struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
	2666	int rval;
	2667
	2668	if (!sink_ssd)
	2669	return 0;
	2670
	2671	rval = media_entity_pads_init(&ssd->sd.entity, ssd->npads, ssd->pads);
	2672	if (rval) {
	2673	dev_err(&client->dev, "media_entity_pads_init failed\n");
	2674	return rval;
	2675	}
	2676
	2677	rval = v4l2_device_register_subdev(sensor->src->sd.v4l2_dev, &ssd->sd);
	2678	if (rval) {
	2679	dev_err(&client->dev, "v4l2_device_register_subdev failed\n");
	2680	return rval;
	2681	}
	2682
	2683	rval = media_create_pad_link(&ssd->sd.entity, source_pad,
	2684	&sink_ssd->sd.entity, sink_pad,
	2685	link_flags);
	2686	if (rval) {
	2687	dev_err(&client->dev, "media_create_pad_link failed\n");
	2688	v4l2_device_unregister_subdev(&ssd->sd);
	2689	return rval;
	2690	}
	2691
	2692	return 0;
	2693	}
	2694
	2695	static void ccs_unregistered(struct v4l2_subdev *subdev)
	2696	{
	2697	struct ccs_sensor *sensor = to_ccs_sensor(subdev);
	2698	unsigned int i;
	2699
	2700	for (i = 1; i < sensor->ssds_used; i++)
	2701	v4l2_device_unregister_subdev(&sensor->ssds[i].sd);
	2702	}
	2703
	2704	static int ccs_registered(struct v4l2_subdev *subdev)
	2705	{
	2706	struct ccs_sensor *sensor = to_ccs_sensor(subdev);
	2707	int rval;
	2708
	2709	if (sensor->scaler) {
	2710	rval = ccs_register_subdev(sensor, sensor->binner,
	2711	sensor->scaler,
	2712	CCS_PAD_SRC, CCS_PAD_SINK,
	2713	MEDIA_LNK_FL_ENABLED \|
	2714	MEDIA_LNK_FL_IMMUTABLE);
	2715	if (rval < 0)
	2716	return rval;
	2717	}
	2718
	2719	rval = ccs_register_subdev(sensor, sensor->pixel_array, sensor->binner,
	2720	CCS_PA_PAD_SRC, CCS_PAD_SINK,
	2721	MEDIA_LNK_FL_ENABLED \|
	2722	MEDIA_LNK_FL_IMMUTABLE);
	2723	if (rval)
	2724	goto out_err;
	2725
	2726	return 0;
	2727
	2728	out_err:
	2729	ccs_unregistered(subdev);
	2730
	2731	return rval;
	2732	}
	2733
	2734	static void ccs_cleanup(struct ccs_sensor *sensor)
	2735	{
	2736	struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
	2737
	2738	device_remove_file(&client->dev, &dev_attr_nvm);
	2739	device_remove_file(&client->dev, &dev_attr_ident);
	2740
	2741	ccs_free_controls(sensor);
	2742	}
	2743
	2744	static void ccs_create_subdev(struct ccs_sensor *sensor,
	2745	struct ccs_subdev ssd, const char name,
	2746	unsigned short num_pads, u32 function)
	2747	{
	2748	struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
	2749
	2750	if (!ssd)
	2751	return;
	2752
	2753	if (ssd != sensor->src)
	2754	v4l2_subdev_init(&ssd->sd, &ccs_ops);
	2755
	2756	ssd->sd.flags \|= V4L2_SUBDEV_FL_HAS_DEVNODE;
	2757	ssd->sd.entity.function = function;
	2758	ssd->sensor = sensor;
	2759
	2760	ssd->npads = num_pads;
	2761	ssd->source_pad = num_pads - 1;
	2762
	2763	v4l2_i2c_subdev_set_name(&ssd->sd, client, sensor->minfo.name, name);
	2764
	2765	ccs_get_native_size(ssd, &ssd->sink_fmt);
	2766
	2767	ssd->compose.width = ssd->sink_fmt.width;
	2768	ssd->compose.height = ssd->sink_fmt.height;
	2769	ssd->crop[ssd->source_pad] = ssd->compose;
	2770	ssd->pads[ssd->source_pad].flags = MEDIA_PAD_FL_SOURCE;
	2771	if (ssd != sensor->pixel_array) {
	2772	ssd->crop[ssd->sink_pad] = ssd->compose;
	2773	ssd->pads[ssd->sink_pad].flags = MEDIA_PAD_FL_SINK;
	2774	}
	2775
	2776	ssd->sd.entity.ops = &ccs_entity_ops;
	2777
	2778	if (ssd == sensor->src)
	2779	return;
	2780
	2781	ssd->sd.internal_ops = &ccs_internal_ops;
	2782	ssd->sd.owner = THIS_MODULE;
	2783	ssd->sd.dev = &client->dev;
	2784	v4l2_set_subdevdata(&ssd->sd, client);
	2785	}
	2786
	2787	static int ccs_open(struct v4l2_subdev sd, struct v4l2_subdev_fh fh)
	2788	{
	2789	struct ccs_subdev *ssd = to_ccs_subdev(sd);
	2790	struct ccs_sensor *sensor = ssd->sensor;
	2791	unsigned int i;
	2792
	2793	mutex_lock(&sensor->mutex);
	2794
	2795	for (i = 0; i < ssd->npads; i++) {
	2796	struct v4l2_mbus_framefmt *try_fmt =
	2797	v4l2_subdev_get_try_format(sd, fh->pad, i);
	2798	struct v4l2_rect *try_crop =
	2799	v4l2_subdev_get_try_crop(sd, fh->pad, i);
	2800	struct v4l2_rect *try_comp;
	2801
	2802	ccs_get_native_size(ssd, try_crop);
	2803
	2804	try_fmt->width = try_crop->width;
	2805	try_fmt->height = try_crop->height;
	2806	try_fmt->code = sensor->internal_csi_format->code;
	2807	try_fmt->field = V4L2_FIELD_NONE;
	2808
	2809	if (ssd != sensor->pixel_array)
	2810	continue;
	2811
	2812	try_comp = v4l2_subdev_get_try_compose(sd, fh->pad, i);
	2813	try_comp = try_crop;
	2814	}
	2815
	2816	mutex_unlock(&sensor->mutex);
	2817
	2818	return 0;
	2819	}
	2820
	2821	static const struct v4l2_subdev_video_ops ccs_video_ops = {
	2822	.s_stream = ccs_set_stream,
	2823	};
	2824
	2825	static const struct v4l2_subdev_pad_ops ccs_pad_ops = {
	2826	.enum_mbus_code = ccs_enum_mbus_code,
	2827	.get_fmt = ccs_get_format,
	2828	.set_fmt = ccs_set_format,
	2829	.get_selection = ccs_get_selection,
	2830	.set_selection = ccs_set_selection,
	2831	};
	2832
	2833	static const struct v4l2_subdev_sensor_ops ccs_sensor_ops = {
	2834	.g_skip_frames = ccs_get_skip_frames,
	2835	.g_skip_top_lines = ccs_get_skip_top_lines,
	2836	};
	2837
	2838	static const struct v4l2_subdev_ops ccs_ops = {
	2839	.video = &ccs_video_ops,
	2840	.pad = &ccs_pad_ops,
	2841	.sensor = &ccs_sensor_ops,
	2842	};
	2843
	2844	static const struct media_entity_operations ccs_entity_ops = {
	2845	.link_validate = v4l2_subdev_link_validate,
	2846	};
	2847
	2848	static const struct v4l2_subdev_internal_ops ccs_internal_src_ops = {
	2849	.registered = ccs_registered,
	2850	.unregistered = ccs_unregistered,
	2851	.open = ccs_open,
	2852	};
	2853
	2854	static const struct v4l2_subdev_internal_ops ccs_internal_ops = {
	2855	.open = ccs_open,
	2856	};
	2857
	2858	/* -----------------------------------------------------------------------------
	2859	* I2C Driver
	2860	*/
	2861
	2862	static int __maybe_unused ccs_suspend(struct device *dev)
	2863	{
	2864	struct i2c_client *client = to_i2c_client(dev);
	2865	struct v4l2_subdev *subdev = i2c_get_clientdata(client);
	2866	struct ccs_sensor *sensor = to_ccs_sensor(subdev);
	2867	bool streaming = sensor->streaming;
	2868	int rval;
	2869
	2870	rval = pm_runtime_get_sync(dev);
	2871	if (rval < 0) {
	2872	pm_runtime_put_noidle(dev);
	2873
	2874	return -EAGAIN;
	2875	}
	2876
	2877	if (sensor->streaming)
	2878	ccs_stop_streaming(sensor);
	2879
	2880	/* save state for resume */
	2881	sensor->streaming = streaming;
	2882
	2883	return 0;
	2884	}
	2885
	2886	static int __maybe_unused ccs_resume(struct device *dev)
	2887	{
	2888	struct i2c_client *client = to_i2c_client(dev);
	2889	struct v4l2_subdev *subdev = i2c_get_clientdata(client);
	2890	struct ccs_sensor *sensor = to_ccs_sensor(subdev);
	2891	int rval = 0;
	2892
	2893	pm_runtime_put(dev);
	2894
	2895	if (sensor->streaming)
	2896	rval = ccs_start_streaming(sensor);
	2897
	2898	return rval;
	2899	}
	2900
	2901	static int ccs_get_hwconfig(struct ccs_sensor sensor, struct device dev)
	2902	{
	2903	struct ccs_hwconfig *hwcfg = &sensor->hwcfg;
	2904	struct v4l2_fwnode_endpoint bus_cfg = { .bus_type = V4L2_MBUS_UNKNOWN };
	2905	struct fwnode_handle *ep;
	2906	struct fwnode_handle *fwnode = dev_fwnode(dev);
	2907	u32 rotation;
	2908	int i;
	2909	int rval;
	2910
	2911	ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
	2912	if (!ep)
	2913	return -ENODEV;
	2914
	2915	/*
	2916	* Note that we do need to rely on detecting the bus type between CSI-2
	2917	* D-PHY and CCP2 as the old bindings did not require it.
	2918	*/
	2919	rval = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
	2920	if (rval)
	2921	goto out_err;
	2922
	2923	switch (bus_cfg.bus_type) {
	2924	case V4L2_MBUS_CSI2_DPHY:
	2925	hwcfg->csi_signalling_mode = CCS_CSI_SIGNALING_MODE_CSI_2_DPHY;
	2926	hwcfg->lanes = bus_cfg.bus.mipi_csi2.num_data_lanes;
	2927	break;
	2928	case V4L2_MBUS_CSI2_CPHY:
	2929	hwcfg->csi_signalling_mode = CCS_CSI_SIGNALING_MODE_CSI_2_CPHY;
	2930	hwcfg->lanes = bus_cfg.bus.mipi_csi2.num_data_lanes;
	2931	break;
	2932	case V4L2_MBUS_CSI1:
	2933	case V4L2_MBUS_CCP2:
	2934	hwcfg->csi_signalling_mode = (bus_cfg.bus.mipi_csi1.strobe) ?
	2935	SMIAPP_CSI_SIGNALLING_MODE_CCP2_DATA_STROBE :
	2936	SMIAPP_CSI_SIGNALLING_MODE_CCP2_DATA_CLOCK;
	2937	hwcfg->lanes = 1;
	2938	break;
	2939	default:
	2940	dev_err(dev, "unsupported bus %u\n", bus_cfg.bus_type);
	2941	rval = -EINVAL;
	2942	goto out_err;
	2943	}
	2944
	2945	dev_dbg(dev, "lanes %u\n", hwcfg->lanes);
	2946
	2947	rval = fwnode_property_read_u32(fwnode, "rotation", &rotation);
	2948	if (!rval) {
	2949	switch (rotation) {
	2950	case 180:
	2951	hwcfg->module_board_orient =
	2952	CCS_MODULE_BOARD_ORIENT_180;
	2953	fallthrough;
	2954	case 0:
	2955	break;
	2956	default:
	2957	dev_err(dev, "invalid rotation %u\n", rotation);
	2958	rval = -EINVAL;
	2959	goto out_err;
	2960	}
	2961	}
	2962
	2963	rval = fwnode_property_read_u32(dev_fwnode(dev), "clock-frequency",
	2964	&hwcfg->ext_clk);
	2965	if (rval)
	2966	dev_info(dev, "can't get clock-frequency\n");
	2967
	2968	dev_dbg(dev, "clk %d, mode %d\n", hwcfg->ext_clk,
	2969	hwcfg->csi_signalling_mode);
	2970
	2971	if (!bus_cfg.nr_of_link_frequencies) {
	2972	dev_warn(dev, "no link frequencies defined\n");
	2973	rval = -EINVAL;
	2974	goto out_err;
	2975	}
	2976
	2977	hwcfg->op_sys_clock = devm_kcalloc(
	2978	dev, bus_cfg.nr_of_link_frequencies + 1 /* guardian */,
	2979	sizeof(*hwcfg->op_sys_clock), GFP_KERNEL);
	2980	if (!hwcfg->op_sys_clock) {
	2981	rval = -ENOMEM;
	2982	goto out_err;
	2983	}
	2984
	2985	for (i = 0; i < bus_cfg.nr_of_link_frequencies; i++) {
	2986	hwcfg->op_sys_clock[i] = bus_cfg.link_frequencies[i];
	2987	dev_dbg(dev, "freq %d: %lld\n", i, hwcfg->op_sys_clock[i]);
	2988	}
	2989
	2990	v4l2_fwnode_endpoint_free(&bus_cfg);
	2991	fwnode_handle_put(ep);
	2992
	2993	return 0;
	2994
	2995	out_err:
	2996	v4l2_fwnode_endpoint_free(&bus_cfg);
	2997	fwnode_handle_put(ep);
	2998
	2999	return rval;
	3000	}
	3001
	3002	static int ccs_probe(struct i2c_client *client)
	3003	{
	3004	struct ccs_sensor *sensor;
	3005	const struct firmware *fw;
	3006	char filename[40];
	3007	unsigned int i;
	3008	int rval;
	3009
	3010	sensor = devm_kzalloc(&client->dev, sizeof(*sensor), GFP_KERNEL);
	3011	if (sensor == NULL)
	3012	return -ENOMEM;
	3013
	3014	rval = ccs_get_hwconfig(sensor, &client->dev);
	3015	if (rval)
	3016	return rval;
	3017
	3018	sensor->src = &sensor->ssds[sensor->ssds_used];
	3019
	3020	v4l2_i2c_subdev_init(&sensor->src->sd, client, &ccs_ops);
	3021	sensor->src->sd.internal_ops = &ccs_internal_src_ops;
	3022
	3023	sensor->regulators = devm_kcalloc(&client->dev,
	3024	ARRAY_SIZE(ccs_regulators),
	3025	sizeof(*sensor->regulators),
	3026	GFP_KERNEL);
	3027	if (!sensor->regulators)
	3028	return -ENOMEM;
	3029
	3030	for (i = 0; i < ARRAY_SIZE(ccs_regulators); i++)
	3031	sensor->regulators[i].supply = ccs_regulators[i];
	3032
	3033	rval = devm_regulator_bulk_get(&client->dev, ARRAY_SIZE(ccs_regulators),
	3034	sensor->regulators);
	3035	if (rval) {
	3036	dev_err(&client->dev, "could not get regulators\n");
	3037	return rval;
	3038	}
	3039
	3040	sensor->ext_clk = devm_clk_get(&client->dev, NULL);
	3041	if (PTR_ERR(sensor->ext_clk) == -ENOENT) {
	3042	dev_info(&client->dev, "no clock defined, continuing...\n");
	3043	sensor->ext_clk = NULL;
	3044	} else if (IS_ERR(sensor->ext_clk)) {
	3045	dev_err(&client->dev, "could not get clock (%ld)\n",
	3046	PTR_ERR(sensor->ext_clk));
	3047	return -EPROBE_DEFER;
	3048	}
	3049
	3050	if (sensor->ext_clk) {
	3051	if (sensor->hwcfg.ext_clk) {
	3052	unsigned long rate;
	3053
	3054	rval = clk_set_rate(sensor->ext_clk,
	3055	sensor->hwcfg.ext_clk);
	3056	if (rval < 0) {
	3057	dev_err(&client->dev,
	3058	"unable to set clock freq to %u\n",
	3059	sensor->hwcfg.ext_clk);
	3060	return rval;
	3061	}
	3062
	3063	rate = clk_get_rate(sensor->ext_clk);
	3064	if (rate != sensor->hwcfg.ext_clk) {
	3065	dev_err(&client->dev,
	3066	"can't set clock freq, asked for %u but got %lu\n",
	3067	sensor->hwcfg.ext_clk, rate);
	3068	return -EINVAL;
	3069	}
	3070	} else {
	3071	sensor->hwcfg.ext_clk = clk_get_rate(sensor->ext_clk);
	3072	dev_dbg(&client->dev, "obtained clock freq %u\n",
	3073	sensor->hwcfg.ext_clk);
	3074	}
	3075	} else if (sensor->hwcfg.ext_clk) {
	3076	dev_dbg(&client->dev, "assuming clock freq %u\n",
	3077	sensor->hwcfg.ext_clk);
	3078	} else {
	3079	dev_err(&client->dev, "unable to obtain clock freq\n");
	3080	return -EINVAL;
	3081	}
	3082
	3083	sensor->reset = devm_gpiod_get_optional(&client->dev, "reset",
	3084	GPIOD_OUT_HIGH);
	3085	if (IS_ERR(sensor->reset))
	3086	return PTR_ERR(sensor->reset);
	3087	/* Support old users that may have used "xshutdown" property. */
	3088	if (!sensor->reset)
	3089	sensor->xshutdown = devm_gpiod_get_optional(&client->dev,
	3090	"xshutdown",
	3091	GPIOD_OUT_LOW);
	3092	if (IS_ERR(sensor->xshutdown))
	3093	return PTR_ERR(sensor->xshutdown);
	3094
	3095	rval = ccs_power_on(&client->dev);
	3096	if (rval < 0)
	3097	return rval;
	3098
	3099	mutex_init(&sensor->mutex);
	3100
	3101	rval = ccs_identify_module(sensor);
	3102	if (rval) {
	3103	rval = -ENODEV;
	3104	goto out_power_off;
	3105	}
	3106
	3107	rval = snprintf(filename, sizeof(filename),
	3108	"ccs/ccs-sensor-%4.4x-%4.4x-%4.4x.fw",
	3109	sensor->minfo.sensor_mipi_manufacturer_id,
	3110	sensor->minfo.sensor_model_id,
	3111	sensor->minfo.sensor_revision_number);
	3112	if (rval >= sizeof(filename)) {
	3113	rval = -ENOMEM;
	3114	goto out_power_off;
	3115	}
	3116
	3117	rval = request_firmware(&fw, filename, &client->dev);
	3118	if (!rval) {
	3119	ccs_data_parse(&sensor->sdata, fw->data, fw->size, &client->dev,
	3120	true);
	3121	release_firmware(fw);
	3122	}
	3123
	3124	rval = snprintf(filename, sizeof(filename),
	3125	"ccs/ccs-module-%4.4x-%4.4x-%4.4x.fw",
	3126	sensor->minfo.mipi_manufacturer_id,
	3127	sensor->minfo.model_id,
	3128	sensor->minfo.revision_number);
	3129	if (rval >= sizeof(filename)) {
	3130	rval = -ENOMEM;
	3131	goto out_release_sdata;
	3132	}
	3133
	3134	rval = request_firmware(&fw, filename, &client->dev);
	3135	if (!rval) {
	3136	ccs_data_parse(&sensor->mdata, fw->data, fw->size, &client->dev,
	3137	true);
	3138	release_firmware(fw);
	3139	}
	3140
	3141	rval = ccs_read_all_limits(sensor);
	3142	if (rval)
	3143	goto out_release_mdata;
	3144
	3145	rval = ccs_read_frame_fmt(sensor);
	3146	if (rval) {
	3147	rval = -ENODEV;
	3148	goto out_free_ccs_limits;
	3149	}
	3150
	3151	/*
	3152	* Handle Sensor Module orientation on the board.
	3153	*
	3154	* The application of H-FLIP and V-FLIP on the sensor is modified by
	3155	* the sensor orientation on the board.
	3156	*
	3157	* For CCS_BOARD_SENSOR_ORIENT_180 the default behaviour is to set
	3158	* both H-FLIP and V-FLIP for normal operation which also implies
	3159	* that a set/unset operation for user space HFLIP and VFLIP v4l2
	3160	* controls will need to be internally inverted.
	3161	*
	3162	* Rotation also changes the bayer pattern.
	3163	*/
	3164	if (sensor->hwcfg.module_board_orient ==
	3165	CCS_MODULE_BOARD_ORIENT_180)
	3166	sensor->hvflip_inv_mask =
	3167	CCS_IMAGE_ORIENTATION_HORIZONTAL_MIRROR \|
	3168	CCS_IMAGE_ORIENTATION_VERTICAL_FLIP;
	3169
	3170	rval = ccs_call_quirk(sensor, limits);
	3171	if (rval) {
	3172	dev_err(&client->dev, "limits quirks failed\n");
	3173	goto out_free_ccs_limits;
	3174	}
	3175
	3176	if (CCS_LIM(sensor, BINNING_CAPABILITY)) {
	3177	sensor->nbinning_subtypes =
	3178	min_t(u8, CCS_LIM(sensor, BINNING_SUB_TYPES),
	3179	CCS_LIM_BINNING_SUB_TYPE_MAX_N);
	3180
	3181	for (i = 0; i < sensor->nbinning_subtypes; i++) {
	3182	sensor->binning_subtypes[i].horizontal =
	3183	CCS_LIM_AT(sensor, BINNING_SUB_TYPE, i) >>
	3184	CCS_BINNING_SUB_TYPE_COLUMN_SHIFT;
	3185	sensor->binning_subtypes[i].vertical =
	3186	CCS_LIM_AT(sensor, BINNING_SUB_TYPE, i) &
	3187	CCS_BINNING_SUB_TYPE_ROW_MASK;
	3188
	3189	dev_dbg(&client->dev, "binning %xx%x\n",
	3190	sensor->binning_subtypes[i].horizontal,
	3191	sensor->binning_subtypes[i].vertical);
	3192	}
	3193	}
	3194	sensor->binning_horizontal = 1;
	3195	sensor->binning_vertical = 1;
	3196
	3197	if (device_create_file(&client->dev, &dev_attr_ident) != 0) {
	3198	dev_err(&client->dev, "sysfs ident entry creation failed\n");
	3199	rval = -ENOENT;
	3200	goto out_free_ccs_limits;
	3201	}
	3202
	3203	if (sensor->minfo.smiapp_version &&
	3204	CCS_LIM(sensor, DATA_TRANSFER_IF_CAPABILITY) &
	3205	CCS_DATA_TRANSFER_IF_CAPABILITY_SUPPORTED) {
	3206	if (device_create_file(&client->dev, &dev_attr_nvm) != 0) {
	3207	dev_err(&client->dev, "sysfs nvm entry failed\n");
	3208	rval = -EBUSY;
	3209	goto out_cleanup;
	3210	}
	3211	}
	3212
	3213	if (!CCS_LIM(sensor, MIN_OP_SYS_CLK_DIV) \|\|
	3214	!CCS_LIM(sensor, MAX_OP_SYS_CLK_DIV) \|\|
	3215	!CCS_LIM(sensor, MIN_OP_PIX_CLK_DIV) \|\|
	3216	!CCS_LIM(sensor, MAX_OP_PIX_CLK_DIV)) {
	3217	/* No OP clock branch */
	3218	sensor->pll.flags \|= CCS_PLL_FLAG_NO_OP_CLOCKS;
	3219	} else if (CCS_LIM(sensor, SCALING_CAPABILITY)
	3220	!= CCS_SCALING_CAPABILITY_NONE \|\|
	3221	CCS_LIM(sensor, DIGITAL_CROP_CAPABILITY)
	3222	== CCS_DIGITAL_CROP_CAPABILITY_INPUT_CROP) {
	3223	/* We have a scaler or digital crop. */
	3224	sensor->scaler = &sensor->ssds[sensor->ssds_used];
	3225	sensor->ssds_used++;
	3226	}
	3227	sensor->binner = &sensor->ssds[sensor->ssds_used];
	3228	sensor->ssds_used++;
	3229	sensor->pixel_array = &sensor->ssds[sensor->ssds_used];
	3230	sensor->ssds_used++;
	3231
	3232	sensor->scale_m = CCS_LIM(sensor, SCALER_N_MIN);
	3233
	3234	/* prepare PLL configuration input values */
	3235	sensor->pll.bus_type = CCS_PLL_BUS_TYPE_CSI2_DPHY;
	3236	sensor->pll.csi2.lanes = sensor->hwcfg.lanes;
	3237	if (CCS_LIM(sensor, CLOCK_CALCULATION) &
	3238	CCS_CLOCK_CALCULATION_LANE_SPEED) {
	3239	sensor->pll.flags \|= CCS_PLL_FLAG_LANE_SPEED_MODEL;
	3240	if (CCS_LIM(sensor, CLOCK_CALCULATION) &
	3241	CCS_CLOCK_CALCULATION_LINK_DECOUPLED) {
	3242	sensor->pll.vt_lanes =
	3243	CCS_LIM(sensor, NUM_OF_VT_LANES) + 1;
	3244	sensor->pll.op_lanes =
	3245	CCS_LIM(sensor, NUM_OF_OP_LANES) + 1;
	3246	sensor->pll.flags \|= CCS_PLL_FLAG_LINK_DECOUPLED;
	3247	} else {
	3248	sensor->pll.vt_lanes = sensor->pll.csi2.lanes;
	3249	sensor->pll.op_lanes = sensor->pll.csi2.lanes;
	3250	}
	3251	}
	3252	if (CCS_LIM(sensor, CLOCK_TREE_PLL_CAPABILITY) &
	3253	CCS_CLOCK_TREE_PLL_CAPABILITY_EXT_DIVIDER)
	3254	sensor->pll.flags \|= CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER;
	3255	if (CCS_LIM(sensor, CLOCK_TREE_PLL_CAPABILITY) &
	3256	CCS_CLOCK_TREE_PLL_CAPABILITY_FLEXIBLE_OP_PIX_CLK_DIV)
	3257	sensor->pll.flags \|= CCS_PLL_FLAG_FLEXIBLE_OP_PIX_CLK_DIV;
	3258	if (CCS_LIM(sensor, FIFO_SUPPORT_CAPABILITY) &
	3259	CCS_FIFO_SUPPORT_CAPABILITY_DERATING)
	3260	sensor->pll.flags \|= CCS_PLL_FLAG_FIFO_DERATING;
	3261	if (CCS_LIM(sensor, FIFO_SUPPORT_CAPABILITY) &
	3262	CCS_FIFO_SUPPORT_CAPABILITY_DERATING_OVERRATING)
	3263	sensor->pll.flags \|= CCS_PLL_FLAG_FIFO_DERATING \|
	3264	CCS_PLL_FLAG_FIFO_OVERRATING;
	3265	if (CCS_LIM(sensor, CLOCK_TREE_PLL_CAPABILITY) &
	3266	CCS_CLOCK_TREE_PLL_CAPABILITY_DUAL_PLL) {
	3267	if (CCS_LIM(sensor, CLOCK_TREE_PLL_CAPABILITY) &
	3268	CCS_CLOCK_TREE_PLL_CAPABILITY_SINGLE_PLL) {
	3269	u32 v;
	3270
	3271	/* Use sensor default in PLL mode selection */
	3272	rval = ccs_read(sensor, PLL_MODE, &v);
	3273	if (rval)
	3274	goto out_cleanup;
	3275
	3276	if (v == CCS_PLL_MODE_DUAL)
	3277	sensor->pll.flags \|= CCS_PLL_FLAG_DUAL_PLL;
	3278	} else {
	3279	sensor->pll.flags \|= CCS_PLL_FLAG_DUAL_PLL;
	3280	}
	3281	if (CCS_LIM(sensor, CLOCK_CALCULATION) &
	3282	CCS_CLOCK_CALCULATION_DUAL_PLL_OP_SYS_DDR)
	3283	sensor->pll.flags \|= CCS_PLL_FLAG_OP_SYS_DDR;
	3284	if (CCS_LIM(sensor, CLOCK_CALCULATION) &
	3285	CCS_CLOCK_CALCULATION_DUAL_PLL_OP_PIX_DDR)
	3286	sensor->pll.flags \|= CCS_PLL_FLAG_OP_PIX_DDR;
	3287	}
	3288	sensor->pll.op_bits_per_lane = CCS_LIM(sensor, OP_BITS_PER_LANE);
	3289	sensor->pll.ext_clk_freq_hz = sensor->hwcfg.ext_clk;
	3290	sensor->pll.scale_n = CCS_LIM(sensor, SCALER_N_MIN);
	3291
	3292	ccs_create_subdev(sensor, sensor->scaler, " scaler", 2,
	3293	MEDIA_ENT_F_CAM_SENSOR);
	3294	ccs_create_subdev(sensor, sensor->binner, " binner", 2,
	3295	MEDIA_ENT_F_PROC_VIDEO_SCALER);
	3296	ccs_create_subdev(sensor, sensor->pixel_array, " pixel_array", 1,
	3297	MEDIA_ENT_F_PROC_VIDEO_SCALER);
	3298
	3299	rval = ccs_init_controls(sensor);
	3300	if (rval < 0)
	3301	goto out_cleanup;
	3302
	3303	rval = ccs_call_quirk(sensor, init);
	3304	if (rval)
	3305	goto out_cleanup;
	3306
	3307	rval = ccs_get_mbus_formats(sensor);
	3308	if (rval) {
	3309	rval = -ENODEV;
	3310	goto out_cleanup;
	3311	}
	3312
	3313	rval = ccs_init_late_controls(sensor);
	3314	if (rval) {
	3315	rval = -ENODEV;
	3316	goto out_cleanup;
	3317	}
	3318
	3319	mutex_lock(&sensor->mutex);
	3320	rval = ccs_pll_blanking_update(sensor);
	3321	mutex_unlock(&sensor->mutex);
	3322	if (rval) {
	3323	dev_err(&client->dev, "update mode failed\n");
	3324	goto out_cleanup;
	3325	}
	3326
	3327	sensor->streaming = false;
	3328	sensor->dev_init_done = true;
	3329
	3330	rval = media_entity_pads_init(&sensor->src->sd.entity, 2,
	3331	sensor->src->pads);
	3332	if (rval < 0)
	3333	goto out_media_entity_cleanup;
	3334
	3335	rval = ccs_write_msr_regs(sensor);
	3336	if (rval)
	3337	goto out_media_entity_cleanup;
	3338
	3339	pm_runtime_set_active(&client->dev);
	3340	pm_runtime_get_noresume(&client->dev);
	3341	pm_runtime_enable(&client->dev);
	3342
	3343	rval = v4l2_async_register_subdev_sensor_common(&sensor->src->sd);
	3344	if (rval < 0)
	3345	goto out_disable_runtime_pm;
	3346
	3347	pm_runtime_set_autosuspend_delay(&client->dev, 1000);
	3348	pm_runtime_use_autosuspend(&client->dev);
	3349	pm_runtime_put_autosuspend(&client->dev);
	3350
	3351	return 0;
	3352
	3353	out_disable_runtime_pm:
	3354	pm_runtime_put_noidle(&client->dev);
	3355	pm_runtime_disable(&client->dev);
	3356
	3357	out_media_entity_cleanup:
	3358	media_entity_cleanup(&sensor->src->sd.entity);
	3359
	3360	out_cleanup:
	3361	ccs_cleanup(sensor);
	3362
	3363	out_release_mdata:
	3364	kvfree(sensor->mdata.backing);
	3365
	3366	out_release_sdata:
	3367	kvfree(sensor->sdata.backing);
	3368
	3369	out_free_ccs_limits:
	3370	kfree(sensor->ccs_limits);
	3371
	3372	out_power_off:
	3373	ccs_power_off(&client->dev);
	3374	mutex_destroy(&sensor->mutex);
	3375
	3376	return rval;
	3377	}
	3378
	3379	static int ccs_remove(struct i2c_client *client)
	3380	{
	3381	struct v4l2_subdev *subdev = i2c_get_clientdata(client);
	3382	struct ccs_sensor *sensor = to_ccs_sensor(subdev);
	3383	unsigned int i;
	3384
	3385	v4l2_async_unregister_subdev(subdev);
	3386
	3387	pm_runtime_disable(&client->dev);
	3388	if (!pm_runtime_status_suspended(&client->dev))
	3389	ccs_power_off(&client->dev);
	3390	pm_runtime_set_suspended(&client->dev);
	3391
	3392	for (i = 0; i < sensor->ssds_used; i++) {
	3393	v4l2_device_unregister_subdev(&sensor->ssds[i].sd);
	3394	media_entity_cleanup(&sensor->ssds[i].sd.entity);
	3395	}
	3396	ccs_cleanup(sensor);
	3397	mutex_destroy(&sensor->mutex);
	3398	kfree(sensor->ccs_limits);
	3399	kvfree(sensor->sdata.backing);
	3400	kvfree(sensor->mdata.backing);
	3401
	3402	return 0;
	3403	}
	3404
	3405	static const struct ccs_device smia_device = {
	3406	.flags = CCS_DEVICE_FLAG_IS_SMIA,
	3407	};
	3408
	3409	static const struct ccs_device ccs_device = {};
	3410
	3411	static const struct acpi_device_id ccs_acpi_table[] = {
	3412	{ .id = "MIPI0200", .driver_data = (unsigned long)&ccs_device },
	3413	{ },
	3414	};
	3415	MODULE_DEVICE_TABLE(acpi, ccs_acpi_table);
	3416
	3417	static const struct of_device_id ccs_of_table[] = {
	3418	{ .compatible = "mipi-ccs-1.1", .data = &ccs_device },
	3419	{ .compatible = "mipi-ccs-1.0", .data = &ccs_device },
	3420	{ .compatible = "mipi-ccs", .data = &ccs_device },
	3421	{ .compatible = "nokia,smia", .data = &smia_device },
	3422	{ },
	3423	};
	3424	MODULE_DEVICE_TABLE(of, ccs_of_table);
	3425
	3426	static const struct dev_pm_ops ccs_pm_ops = {
	3427	SET_SYSTEM_SLEEP_PM_OPS(ccs_suspend, ccs_resume)
	3428	SET_RUNTIME_PM_OPS(ccs_power_off, ccs_power_on, NULL)
	3429	};
	3430
	3431	static struct i2c_driver ccs_i2c_driver = {
	3432	.driver = {
	3433	.acpi_match_table = ccs_acpi_table,
	3434	.of_match_table = ccs_of_table,
	3435	.name = CCS_NAME,
	3436	.pm = &ccs_pm_ops,
	3437	},
	3438	.probe_new = ccs_probe,
	3439	.remove = ccs_remove,
	3440	};
	3441
	3442	static int ccs_module_init(void)
	3443	{
	3444	unsigned int i, l;
	3445
	3446	for (i = 0, l = 0; ccs_limits[i].size && l < CCS_L_LAST; i++) {
	3447	if (!(ccs_limits[i].flags & CCS_L_FL_SAME_REG)) {
	3448	ccs_limit_offsets[l + 1].lim =
	3449	ALIGN(ccs_limit_offsets[l].lim +
	3450	ccs_limits[i].size,
	3451	ccs_reg_width(ccs_limits[i + 1].reg));
	3452	ccs_limit_offsets[l].info = i;
	3453	l++;
	3454	} else {
	3455	ccs_limit_offsets[l].lim += ccs_limits[i].size;
	3456	}
	3457	}
	3458
	3459	if (WARN_ON(ccs_limits[i].size))
	3460	return -EINVAL;
	3461
	3462	if (WARN_ON(l != CCS_L_LAST))
	3463	return -EINVAL;
	3464
	3465	return i2c_register_driver(THIS_MODULE, &ccs_i2c_driver);
	3466	}
	3467
	3468	static void ccs_module_cleanup(void)
	3469	{
	3470	i2c_del_driver(&ccs_i2c_driver);
	3471	}
	3472
	3473	module_init(ccs_module_init);
	3474	module_exit(ccs_module_cleanup);
	3475
	3476	MODULE_AUTHOR("Sakari Ailus <sakari.ailus@linux.intel.com>");
	3477	MODULE_DESCRIPTION("Generic MIPI CCS/SMIA/SMIA++ camera sensor driver");
	3478	MODULE_LICENSE("GPL v2");
	3479	MODULE_ALIAS("smiapp");

drivers/media/i2c/ccs/ccs-data-defs.h+221−0

@@ -0,0 +1,221 @@
	1	/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
	2	/*
	3	* CCS static data binary format definitions
	4	*
	5	* Copyright 2019--2020 Intel Corporation
	6	*/
	7
	8	#ifndef __CCS_DATA_DEFS_H__
	9	#define __CCS_DATA_DEFS_H__
	10
	11	#include "ccs-data.h"
	12
	13	#define CCS_STATIC_DATA_VERSION 0
	14
	15	enum __ccs_data_length_specifier_id {
	16	CCS_DATA_LENGTH_SPECIFIER_1 = 0,
	17	CCS_DATA_LENGTH_SPECIFIER_2 = 1,
	18	CCS_DATA_LENGTH_SPECIFIER_3 = 2
	19	};
	20
	21	#define CCS_DATA_LENGTH_SPECIFIER_SIZE_SHIFT 6
	22
	23	struct __ccs_data_length_specifier {
	24	u8 length;
	25	} __packed;
	26
	27	struct __ccs_data_length_specifier2 {
	28	u8 length[2];
	29	} __packed;
	30
	31	struct __ccs_data_length_specifier3 {
	32	u8 length[3];
	33	} __packed;
	34
	35	struct __ccs_data_block {
	36	u8 id;
	37	struct __ccs_data_length_specifier length;
	38	} __packed;
	39
	40	#define CCS_DATA_BLOCK_HEADER_ID_VERSION_SHIFT 5
	41
	42	struct __ccs_data_block3 {
	43	u8 id;
	44	struct __ccs_data_length_specifier2 length;
	45	} __packed;
	46
	47	struct __ccs_data_block4 {
	48	u8 id;
	49	struct __ccs_data_length_specifier3 length;
	50	} __packed;
	51
	52	enum __ccs_data_block_id {
	53	CCS_DATA_BLOCK_ID_DUMMY = 1,
	54	CCS_DATA_BLOCK_ID_DATA_VERSION = 2,
	55	CCS_DATA_BLOCK_ID_SENSOR_READ_ONLY_REGS = 3,
	56	CCS_DATA_BLOCK_ID_MODULE_READ_ONLY_REGS = 4,
	57	CCS_DATA_BLOCK_ID_SENSOR_MANUFACTURER_REGS = 5,
	58	CCS_DATA_BLOCK_ID_MODULE_MANUFACTURER_REGS = 6,
	59	CCS_DATA_BLOCK_ID_SENSOR_RULE_BASED_BLOCK = 32,
	60	CCS_DATA_BLOCK_ID_MODULE_RULE_BASED_BLOCK = 33,
	61	CCS_DATA_BLOCK_ID_SENSOR_PDAF_PIXEL_LOCATION = 36,
	62	CCS_DATA_BLOCK_ID_MODULE_PDAF_PIXEL_LOCATION = 37,
	63	CCS_DATA_BLOCK_ID_LICENSE = 40,
	64	CCS_DATA_BLOCK_ID_END = 127,
	65	};
	66
	67	struct __ccs_data_block_version {
	68	u8 static_data_version_major[2];
	69	u8 static_data_version_minor[2];
	70	u8 year[2];
	71	u8 month;
	72	u8 day;
	73	} __packed;
	74
	75	struct __ccs_data_block_regs {
	76	u8 reg_len;
	77	} __packed;
	78
	79	#define CCS_DATA_BLOCK_REGS_ADDR_MASK 0x07
	80	#define CCS_DATA_BLOCK_REGS_LEN_SHIFT 3
	81	#define CCS_DATA_BLOCK_REGS_LEN_MASK 0x38
	82	#define CCS_DATA_BLOCK_REGS_SEL_SHIFT 6
	83
	84	enum ccs_data_block_regs_sel {
	85	CCS_DATA_BLOCK_REGS_SEL_REGS = 0,
	86	CCS_DATA_BLOCK_REGS_SEL_REGS2 = 1,
	87	CCS_DATA_BLOCK_REGS_SEL_REGS3 = 2,
	88	};
	89
	90	struct __ccs_data_block_regs2 {
	91	u8 reg_len;
	92	u8 addr;
	93	} __packed;
	94
	95	#define CCS_DATA_BLOCK_REGS_2_ADDR_MASK 0x01
	96	#define CCS_DATA_BLOCK_REGS_2_LEN_SHIFT 1
	97	#define CCS_DATA_BLOCK_REGS_2_LEN_MASK 0x3e
	98
	99	struct __ccs_data_block_regs3 {
	100	u8 reg_len;
	101	u8 addr[2];
	102	} __packed;
	103
	104	#define CCS_DATA_BLOCK_REGS_3_LEN_MASK 0x3f
	105
	106	enum __ccs_data_ffd_pixelcode {
	107	CCS_DATA_BLOCK_FFD_PIXELCODE_EMBEDDED = 1,
	108	CCS_DATA_BLOCK_FFD_PIXELCODE_DUMMY = 2,
	109	CCS_DATA_BLOCK_FFD_PIXELCODE_BLACK = 3,
	110	CCS_DATA_BLOCK_FFD_PIXELCODE_DARK = 4,
	111	CCS_DATA_BLOCK_FFD_PIXELCODE_VISIBLE = 5,
	112	CCS_DATA_BLOCK_FFD_PIXELCODE_MS_0 = 8,
	113	CCS_DATA_BLOCK_FFD_PIXELCODE_MS_1 = 9,
	114	CCS_DATA_BLOCK_FFD_PIXELCODE_MS_2 = 10,
	115	CCS_DATA_BLOCK_FFD_PIXELCODE_MS_3 = 11,
	116	CCS_DATA_BLOCK_FFD_PIXELCODE_MS_4 = 12,
	117	CCS_DATA_BLOCK_FFD_PIXELCODE_MS_5 = 13,
	118	CCS_DATA_BLOCK_FFD_PIXELCODE_MS_6 = 14,
	119	CCS_DATA_BLOCK_FFD_PIXELCODE_TOP_OB = 16,
	120	CCS_DATA_BLOCK_FFD_PIXELCODE_BOTTOM_OB = 17,
	121	CCS_DATA_BLOCK_FFD_PIXELCODE_LEFT_OB = 18,
	122	CCS_DATA_BLOCK_FFD_PIXELCODE_RIGHT_OB = 19,
	123	CCS_DATA_BLOCK_FFD_PIXELCODE_TOP_LEFT_OB = 20,
	124	CCS_DATA_BLOCK_FFD_PIXELCODE_TOP_RIGHT_OB = 21,
	125	CCS_DATA_BLOCK_FFD_PIXELCODE_BOTTOM_LEFT_OB = 22,
	126	CCS_DATA_BLOCK_FFD_PIXELCODE_BOTTOM_RIGHT_OB = 23,
	127	CCS_DATA_BLOCK_FFD_PIXELCODE_TOTAL = 24,
	128	CCS_DATA_BLOCK_FFD_PIXELCODE_TOP_PDAF = 32,
	129	CCS_DATA_BLOCK_FFD_PIXELCODE_BOTTOM_PDAF = 33,
	130	CCS_DATA_BLOCK_FFD_PIXELCODE_LEFT_PDAF = 34,
	131	CCS_DATA_BLOCK_FFD_PIXELCODE_RIGHT_PDAF = 35,
	132	CCS_DATA_BLOCK_FFD_PIXELCODE_TOP_LEFT_PDAF = 36,
	133	CCS_DATA_BLOCK_FFD_PIXELCODE_TOP_RIGHT_PDAF = 37,
	134	CCS_DATA_BLOCK_FFD_PIXELCODE_BOTTOM_LEFT_PDAF = 38,
	135	CCS_DATA_BLOCK_FFD_PIXELCODE_BOTTOM_RIGHT_PDAF = 39,
	136	CCS_DATA_BLOCK_FFD_PIXELCODE_SEPARATED_PDAF = 40,
	137	CCS_DATA_BLOCK_FFD_PIXELCODE_ORIGINAL_ORDER_PDAF = 41,
	138	CCS_DATA_BLOCK_FFD_PIXELCODE_VENDOR_PDAF = 41,
	139	};
	140
	141	struct __ccs_data_block_ffd_entry {
	142	u8 pixelcode;
	143	u8 reserved;
	144	u8 value[2];
	145	} __packed;
	146
	147	struct __ccs_data_block_ffd {
	148	u8 num_column_descs;
	149	u8 num_row_descs;
	150	} __packed;
	151
	152	enum __ccs_data_block_rule_id {
	153	CCS_DATA_BLOCK_RULE_ID_IF = 1,
	154	CCS_DATA_BLOCK_RULE_ID_READ_ONLY_REGS = 2,
	155	CCS_DATA_BLOCK_RULE_ID_FFD = 3,
	156	CCS_DATA_BLOCK_RULE_ID_MSR = 4,
	157	CCS_DATA_BLOCK_RULE_ID_PDAF_READOUT = 5,
	158	};
	159
	160	struct __ccs_data_block_rule_if {
	161	u8 addr[2];
	162	u8 value;
	163	u8 mask;
	164	} __packed;
	165
	166	enum __ccs_data_block_pdaf_readout_order {
	167	CCS_DATA_BLOCK_PDAF_READOUT_ORDER_ORIGINAL = 1,
	168	CCS_DATA_BLOCK_PDAF_READOUT_ORDER_SEPARATE_WITHIN_LINE = 2,
	169	CCS_DATA_BLOCK_PDAF_READOUT_ORDER_SEPARATE_TYPES_SEPARATE_LINES = 3,
	170	};
	171
	172	struct __ccs_data_block_pdaf_readout {
	173	u8 pdaf_readout_info_reserved;
	174	u8 pdaf_readout_info_order;
	175	} __packed;
	176
	177	struct __ccs_data_block_pdaf_pix_loc_block_desc {
	178	u8 block_type_id;
	179	u8 repeat_x[2];
	180	} __packed;
	181
	182	struct __ccs_data_block_pdaf_pix_loc_block_desc_group {
	183	u8 num_block_descs[2];
	184	u8 repeat_y;
	185	} __packed;
	186
	187	enum __ccs_data_block_pdaf_pix_loc_pixel_type {
	188	CCS_DATA_PDAF_PIXEL_TYPE_LEFT_SEPARATED = 0,
	189	CCS_DATA_PDAF_PIXEL_TYPE_RIGHT_SEPARATED = 1,
	190	CCS_DATA_PDAF_PIXEL_TYPE_TOP_SEPARATED = 2,
	191	CCS_DATA_PDAF_PIXEL_TYPE_BOTTOM_SEPARATED = 3,
	192	CCS_DATA_PDAF_PIXEL_TYPE_LEFT_SIDE_BY_SIDE = 4,
	193	CCS_DATA_PDAF_PIXEL_TYPE_RIGHT_SIDE_BY_SIDE = 5,
	194	CCS_DATA_PDAF_PIXEL_TYPE_TOP_SIDE_BY_SIDE = 6,
	195	CCS_DATA_PDAF_PIXEL_TYPE_BOTTOM_SIDE_BY_SIDE = 7,
	196	CCS_DATA_PDAF_PIXEL_TYPE_TOP_LEFT = 8,
	197	CCS_DATA_PDAF_PIXEL_TYPE_TOP_RIGHT = 9,
	198	CCS_DATA_PDAF_PIXEL_TYPE_BOTTOM_LEFT = 10,
	199	CCS_DATA_PDAF_PIXEL_TYPE_BOTTOM_RIGHT = 11,
	200	};
	201
	202	struct __ccs_data_block_pdaf_pix_loc_pixel_desc {
	203	u8 pixel_type;
	204	u8 small_offset_x;
	205	u8 small_offset_y;
	206	} __packed;
	207
	208	struct __ccs_data_block_pdaf_pix_loc {
	209	u8 main_offset_x[2];
	210	u8 main_offset_y[2];
	211	u8 global_pdaf_type;
	212	u8 block_width;
	213	u8 block_height;
	214	u8 num_block_desc_groups[2];
	215	} __packed;
	216
	217	struct __ccs_data_block_end {
	218	u8 crc[4];
	219	} __packed;
	220
	221	#endif /* __CCS_DATA_DEFS_H__ */

drivers/media/i2c/ccs/ccs-data.c+953−0

@@ -0,0 +1,953 @@
	1	// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
	2	/*
	3	* CCS static data binary parser library
	4	*
	5	* Copyright 2019--2020 Intel Corporation
	6	*/
	7
	8	#include <linux/device.h>
	9	#include <linux/errno.h>
	10	#include <linux/limits.h>
	11	#include <linux/mm.h>
	12	#include <linux/slab.h>
	13	#include <linux/types.h>
	14
	15	#include "ccs-data-defs.h"
	16
	17	struct bin_container {
	18	void *base;
	19	void *now;
	20	void *end;
	21	size_t size;
	22	};
	23
	24	static void bin_alloc(struct bin_container bin, size_t len)
	25	{
	26	void *ptr;
	27
	28	len = ALIGN(len, 8);
	29
	30	if (bin->end - bin->now < len)
	31	return NULL;
	32
	33	ptr = bin->now;
	34	bin->now += len;
	35
	36	return ptr;
	37	}
	38
	39	static void bin_reserve(struct bin_container *bin, size_t len)
	40	{
	41	bin->size += ALIGN(len, 8);
	42	}
	43
	44	static int bin_backing_alloc(struct bin_container *bin)
	45	{
	46	bin->base = bin->now = kvzalloc(bin->size, GFP_KERNEL);
	47	if (!bin->base)
	48	return -ENOMEM;
	49
	50	bin->end = bin->base + bin->size;
	51
	52	return 0;
	53	}
	54
	55	#define is_contained(var, endp) \
	56	(sizeof(var) <= (endp) - (void )(var))
	57	#define has_headroom(ptr, headroom, endp) \
	58	((headroom) <= (endp) - (void *)(ptr))
	59	#define is_contained_with_headroom(var, headroom, endp) \
	60	(sizeof(var) + (headroom) <= (endp) - (void )(var))
	61
	62	static int
	63	ccs_data_parse_length_specifier(const struct __ccs_data_length_specifier *__len,
	64	size_t __hlen, size_t __plen,
	65	const void *endp)
	66	{
	67	size_t hlen, plen;
	68
	69	if (!is_contained(__len, endp))
	70	return -ENODATA;
	71
	72	switch (__len->length >> CCS_DATA_LENGTH_SPECIFIER_SIZE_SHIFT) {
	73	case CCS_DATA_LENGTH_SPECIFIER_1:
	74	hlen = sizeof(*__len);
	75	plen = __len->length &
	76	((1 << CCS_DATA_LENGTH_SPECIFIER_SIZE_SHIFT) - 1);
	77	break;
	78	case CCS_DATA_LENGTH_SPECIFIER_2: {
	79	struct __ccs_data_length_specifier2 __len2 = (void )__len;
	80
	81	if (!is_contained(__len2, endp))
	82	return -ENODATA;
	83
	84	hlen = sizeof(*__len2);
	85	plen = ((size_t)
	86	(__len2->length[0] &
	87	((1 << CCS_DATA_LENGTH_SPECIFIER_SIZE_SHIFT) - 1))
	88	<< 8) + __len2->length[1];
	89	break;
	90	}
	91	case CCS_DATA_LENGTH_SPECIFIER_3: {
	92	struct __ccs_data_length_specifier3 __len3 = (void )__len;
	93
	94	if (!is_contained(__len3, endp))
	95	return -ENODATA;
	96
	97	hlen = sizeof(*__len3);
	98	plen = ((size_t)
	99	(__len3->length[0] &
	100	((1 << CCS_DATA_LENGTH_SPECIFIER_SIZE_SHIFT) - 1))
	101	<< 16) + (__len3->length[0] << 8) + __len3->length[1];
	102	break;
	103	}
	104	default:
	105	return -EINVAL;
	106	}
	107
	108	if (!has_headroom(__len, hlen + plen, endp))
	109	return -ENODATA;
	110
	111	*__hlen = hlen;
	112	*__plen = plen;
	113
	114	return 0;
	115	}
	116
	117	static u8
	118	ccs_data_parse_format_version(const struct __ccs_data_block *block)
	119	{
	120	return block->id >> CCS_DATA_BLOCK_HEADER_ID_VERSION_SHIFT;
	121	}
	122
	123	static u8 ccs_data_parse_block_id(const struct __ccs_data_block *block,
	124	bool is_first)
	125	{
	126	if (!is_first)
	127	return block->id;
	128
	129	return block->id & ((1 << CCS_DATA_BLOCK_HEADER_ID_VERSION_SHIFT) - 1);
	130	}
	131
	132	static int ccs_data_parse_version(struct bin_container *bin,
	133	struct ccs_data_container *ccsdata,
	134	const void payload, const void endp)
	135	{
	136	const struct __ccs_data_block_version *v = payload;
	137	struct ccs_data_block_version *vv;
	138
	139	if (v + 1 != endp)
	140	return -ENODATA;
	141
	142	if (!bin->base) {
	143	bin_reserve(bin, sizeof(*ccsdata->version));
	144	return 0;
	145	}
	146
	147	ccsdata->version = bin_alloc(bin, sizeof(*ccsdata->version));
	148	if (!ccsdata->version)
	149	return -ENOMEM;
	150
	151	vv = ccsdata->version;
	152	vv->version_major = ((u16)v->static_data_version_major[0] << 8) +
	153	v->static_data_version_major[1];
	154	vv->version_minor = ((u16)v->static_data_version_minor[0] << 8) +
	155	v->static_data_version_major[1];
	156	vv->date_year = ((u16)v->year[0] << 8) + v->year[1];
	157	vv->date_month = v->month;
	158	vv->date_day = v->day;
	159
	160	return 0;
	161	}
	162
	163	static void print_ccs_data_version(struct device *dev,
	164	struct ccs_data_block_version *v)
	165	{
	166	dev_dbg(dev,
	167	"static data version %4.4x.%4.4x, date %4.4u-%2.2u-%2.2u\n",
	168	v->version_major, v->version_minor,
	169	v->date_year, v->date_month, v->date_day);
	170	}
	171
	172	static int ccs_data_block_parse_header(const struct __ccs_data_block *block,
	173	bool is_first, unsigned int *__block_id,
	174	const void **payload,
	175	const struct __ccs_data_block **next_block,
	176	const void endp, struct device dev,
	177	bool verbose)
	178	{
	179	size_t plen, hlen;
	180	u8 block_id;
	181	int rval;
	182
	183	if (!is_contained(block, endp))
	184	return -ENODATA;
	185
	186	rval = ccs_data_parse_length_specifier(&block->length, &hlen, &plen,
	187	endp);
	188	if (rval < 0)
	189	return rval;
	190
	191	block_id = ccs_data_parse_block_id(block, is_first);
	192
	193	if (verbose)
	194	dev_dbg(dev,
	195	"Block ID 0x%2.2x, header length %zu, payload length %zu\n",
	196	block_id, hlen, plen);
	197
	198	if (!has_headroom(&block->length, hlen + plen, endp))
	199	return -ENODATA;
	200
	201	if (__block_id)
	202	*__block_id = block_id;
	203
	204	if (payload)
	205	payload = (void )&block->length + hlen;
	206
	207	if (next_block)
	208	next_block = (void )&block->length + hlen + plen;
	209
	210	return 0;
	211	}
	212
	213	static int ccs_data_parse_regs(struct bin_container *bin,
	214	struct ccs_reg **__regs,
	215	size_t __num_regs, const void payload,
	216	const void endp, struct device dev)
	217	{
	218	struct ccs_reg regs_base, regs;
	219	size_t num_regs = 0;
	220	u16 addr = 0;
	221
	222	if (bin->base && __regs) {
	223	regs = regs_base = bin_alloc(bin, sizeof(regs) *__num_regs);
	224	if (!regs)
	225	return -ENOMEM;
	226	}
	227
	228	while (payload < endp && num_regs < INT_MAX) {
	229	const struct __ccs_data_block_regs *r = payload;
	230	size_t len;
	231	const void *data;
	232
	233	if (!is_contained(r, endp))
	234	return -ENODATA;
	235
	236	switch (r->reg_len >> CCS_DATA_BLOCK_REGS_SEL_SHIFT) {
	237	case CCS_DATA_BLOCK_REGS_SEL_REGS:
	238	addr += r->reg_len & CCS_DATA_BLOCK_REGS_ADDR_MASK;
	239	len = ((r->reg_len & CCS_DATA_BLOCK_REGS_LEN_MASK)
	240	>> CCS_DATA_BLOCK_REGS_LEN_SHIFT) + 1;
	241
	242	if (!is_contained_with_headroom(r, len, endp))
	243	return -ENODATA;
	244
	245	data = r + 1;
	246	break;
	247	case CCS_DATA_BLOCK_REGS_SEL_REGS2: {
	248	const struct __ccs_data_block_regs2 *r2 = payload;
	249
	250	if (!is_contained(r2, endp))
	251	return -ENODATA;
	252
	253	addr += ((u16)(r2->reg_len &
	254	CCS_DATA_BLOCK_REGS_2_ADDR_MASK) << 8)
	255	+ r2->addr;
	256	len = ((r2->reg_len & CCS_DATA_BLOCK_REGS_2_LEN_MASK)
	257	>> CCS_DATA_BLOCK_REGS_2_LEN_SHIFT) + 1;
	258
	259	if (!is_contained_with_headroom(r2, len, endp))
	260	return -ENODATA;
	261
	262	data = r2 + 1;
	263	break;
	264	}
	265	case CCS_DATA_BLOCK_REGS_SEL_REGS3: {
	266	const struct __ccs_data_block_regs3 *r3 = payload;
	267
	268	if (!is_contained(r3, endp))
	269	return -ENODATA;
	270
	271	addr = ((u16)r3->addr[0] << 8) + r3->addr[1];
	272	len = (r3->reg_len & CCS_DATA_BLOCK_REGS_3_LEN_MASK) + 1;
	273
	274	if (!is_contained_with_headroom(r3, len, endp))
	275	return -ENODATA;
	276
	277	data = r3 + 1;
	278	break;
	279	}
	280	default:
	281	return -EINVAL;
	282	}
	283
	284	num_regs++;
	285
	286	if (!bin->base) {
	287	bin_reserve(bin, len);
	288	} else if (__regs) {
	289	regs->addr = addr;
	290	regs->len = len;
	291	regs->value = bin_alloc(bin, len);
	292	if (!regs->value)
	293	return -ENOMEM;
	294
	295	memcpy(regs->value, data, len);
	296	regs++;
	297	}
	298
	299	addr += len;
	300	payload = data + len;
	301	}
	302
	303	if (!bin->base)
	304	bin_reserve(bin, sizeof(regs) num_regs);
	305
	306	if (__num_regs)
	307	*__num_regs = num_regs;
	308
	309	if (bin->base && __regs)
	310	*__regs = regs_base;
	311
	312	return 0;
	313	}
	314
	315	static int ccs_data_parse_reg_rules(struct bin_container *bin,
	316	struct ccs_reg **__regs,
	317	size_t *__num_regs,
	318	const void *payload,
	319	const void endp, struct device dev)
	320	{
	321	int rval;
	322
	323	if (!bin->base)
	324	return ccs_data_parse_regs(bin, NULL, NULL, payload, endp, dev);
	325
	326	rval = ccs_data_parse_regs(bin, NULL, __num_regs, payload, endp, dev);
	327	if (rval)
	328	return rval;
	329
	330	return ccs_data_parse_regs(bin, __regs, __num_regs, payload, endp,
	331	dev);
	332	}
	333
	334	static void assign_ffd_entry(struct ccs_frame_format_desc *desc,
	335	const struct __ccs_data_block_ffd_entry *ent)
	336	{
	337	desc->pixelcode = ent->pixelcode;
	338	desc->value = ((u16)ent->value[0] << 8) + ent->value[1];
	339	}
	340
	341	static int ccs_data_parse_ffd(struct bin_container *bin,
	342	struct ccs_frame_format_descs **ffd,
	343	const void *payload,
	344	const void endp, struct device dev)
	345	{
	346	const struct __ccs_data_block_ffd *__ffd = payload;
	347	const struct __ccs_data_block_ffd_entry *__entry;
	348	unsigned int i;
	349
	350	if (!is_contained(__ffd, endp))
	351	return -ENODATA;
	352
	353	if ((void )__ffd + sizeof(__ffd) +
	354	((u32)__ffd->num_column_descs +
	355	(u32)__ffd->num_row_descs) *
	356	sizeof(struct __ccs_data_block_ffd_entry) != endp)
	357	return -ENODATA;
	358
	359	if (!bin->base) {
	360	bin_reserve(bin, sizeof(**ffd));
	361	bin_reserve(bin, __ffd->num_column_descs *
	362	sizeof(struct ccs_frame_format_desc));
	363	bin_reserve(bin, __ffd->num_row_descs *
	364	sizeof(struct ccs_frame_format_desc));
	365
	366	return 0;
	367	}
	368
	369	ffd = bin_alloc(bin, sizeof(*ffd));
	370	if (!*ffd)
	371	return -ENOMEM;
	372
	373	(*ffd)->num_column_descs = __ffd->num_column_descs;
	374	(*ffd)->num_row_descs = __ffd->num_row_descs;
	375	__entry = (void *)(__ffd + 1);
	376
	377	(ffd)->column_descs = bin_alloc(bin, __ffd->num_column_descs
	378	sizeof((ffd)->column_descs));
	379	if (!(*ffd)->column_descs)
	380	return -ENOMEM;
	381
	382	for (i = 0; i < __ffd->num_column_descs; i++, __entry++)
	383	assign_ffd_entry(&(*ffd)->column_descs[i], __entry);
	384
	385	(ffd)->row_descs = bin_alloc(bin, __ffd->num_row_descs
	386	sizeof((ffd)->row_descs));
	387	if (!(*ffd)->row_descs)
	388	return -ENOMEM;
	389
	390	for (i = 0; i < __ffd->num_row_descs; i++, __entry++)
	391	assign_ffd_entry(&(*ffd)->row_descs[i], __entry);
	392
	393	if (__entry != endp)
	394	return -EPROTO;
	395
	396	return 0;
	397	}
	398
	399	static int ccs_data_parse_pdaf_readout(struct bin_container *bin,
	400	struct ccs_pdaf_readout **pdaf_readout,
	401	const void *payload,
	402	const void endp, struct device dev)
	403	{
	404	const struct __ccs_data_block_pdaf_readout *__pdaf = payload;
	405
	406	if (!is_contained(__pdaf, endp))
	407	return -ENODATA;
	408
	409	if (!bin->base) {
	410	bin_reserve(bin, sizeof(**pdaf_readout));
	411	} else {
	412	pdaf_readout = bin_alloc(bin, sizeof(*pdaf_readout));
	413	if (!*pdaf_readout)
	414	return -ENOMEM;
	415
	416	(*pdaf_readout)->pdaf_readout_info_order =
	417	__pdaf->pdaf_readout_info_order;
	418	}
	419
	420	return ccs_data_parse_ffd(bin, !bin->base ? NULL : &(*pdaf_readout)->ffd,
	421	__pdaf + 1, endp, dev);
	422	}
	423
	424	static int ccs_data_parse_rules(struct bin_container *bin,
	425	struct ccs_rule **__rules,
	426	size_t __num_rules, const void payload,
	427	const void endp, struct device dev)
	428	{
	429	struct ccs_rule rules_base, rules = NULL, *next_rule;
	430	size_t num_rules = 0;
	431	const void *__next_rule = payload;
	432	int rval;
	433
	434	if (bin->base) {
	435	rules_base = next_rule =
	436	bin_alloc(bin, sizeof(rules) *__num_rules);
	437	if (!rules_base)
	438	return -ENOMEM;
	439	}
	440
	441	while (__next_rule < endp) {
	442	size_t rule_hlen, rule_plen, rule_plen2;
	443	const u8 *__rule_type;
	444	const void *rule_payload;
	445
	446	/* Size of a single rule */
	447	rval = ccs_data_parse_length_specifier(__next_rule, &rule_hlen,
	448	&rule_plen, endp);
	449
	450	if (rval < 0)
	451	return rval;
	452
	453	__rule_type = __next_rule + rule_hlen;
	454
	455	if (!is_contained(__rule_type, endp))
	456	return -ENODATA;
	457
	458	rule_payload = __rule_type + 1;
	459	rule_plen2 = rule_plen - sizeof(*__rule_type);
	460
	461	switch (*__rule_type) {
	462	case CCS_DATA_BLOCK_RULE_ID_IF: {
	463	const struct __ccs_data_block_rule_if *__if_rules =
	464	rule_payload;
	465	const size_t __num_if_rules =
	466	rule_plen2 / sizeof(*__if_rules);
	467	struct ccs_if_rule *if_rule;
	468
	469	if (!has_headroom(__if_rules,
	470	sizeof(__if_rules) __num_if_rules,
	471	rule_payload + rule_plen2))
	472	return -ENODATA;
	473
	474	/* Also check there is no extra data */
	475	if (__if_rules + __num_if_rules !=
	476	rule_payload + rule_plen2)
	477	return -EINVAL;
	478
	479	if (!bin->base) {
	480	bin_reserve(bin,
	481	sizeof(if_rule)
	482	__num_if_rules);
	483	num_rules++;
	484	} else {
	485	unsigned int i;
	486
	487	rules = next_rule;
	488	next_rule++;
	489
	490	if_rule = bin_alloc(bin,
	491	sizeof(if_rule)
	492	__num_if_rules);
	493	if (!if_rule)
	494	return -ENOMEM;
	495
	496	for (i = 0; i < __num_if_rules; i++) {
	497	if_rule[i].addr =
	498	((u16)__if_rules[i].addr[0]
	499	<< 8) +
	500	__if_rules[i].addr[1];
	501	if_rule[i].value = __if_rules[i].value;
	502	if_rule[i].mask = __if_rules[i].mask;
	503	}
	504
	505	rules->if_rules = if_rule;
	506	rules->num_if_rules = __num_if_rules;
	507	}
	508	break;
	509	}
	510	case CCS_DATA_BLOCK_RULE_ID_READ_ONLY_REGS:
	511	rval = ccs_data_parse_reg_rules(bin, &rules->read_only_regs,
	512	&rules->num_read_only_regs,
	513	rule_payload,
	514	rule_payload + rule_plen2,
	515	dev);
	516	if (rval)
	517	return rval;
	518	break;
	519	case CCS_DATA_BLOCK_RULE_ID_FFD:
	520	rval = ccs_data_parse_ffd(bin, &rules->frame_format,
	521	rule_payload,
	522	rule_payload + rule_plen2,
	523	dev);
	524	if (rval)
	525	return rval;
	526	break;
	527	case CCS_DATA_BLOCK_RULE_ID_MSR:
	528	rval = ccs_data_parse_reg_rules(bin,
	529	&rules->manufacturer_regs,
	530	&rules->num_manufacturer_regs,
	531	rule_payload,
	532	rule_payload + rule_plen2,
	533	dev);
	534	if (rval)
	535	return rval;
	536	break;
	537	case CCS_DATA_BLOCK_RULE_ID_PDAF_READOUT:
	538	rval = ccs_data_parse_pdaf_readout(bin,
	539	&rules->pdaf_readout,
	540	rule_payload,
	541	rule_payload + rule_plen2,
	542	dev);
	543	if (rval)
	544	return rval;
	545	break;
	546	default:
	547	dev_dbg(dev,
	548	"Don't know how to handle rule type %u!\n",
	549	*__rule_type);
	550	return -EINVAL;
	551	}
	552	__next_rule = __next_rule + rule_hlen + rule_plen;
	553	}
	554
	555	if (!bin->base) {
	556	bin_reserve(bin, sizeof(rules) num_rules);
	557	*__num_rules = num_rules;
	558	} else {
	559	*__rules = rules_base;
	560	}
	561
	562	return 0;
	563	}
	564
	565	static int ccs_data_parse_pdaf(struct bin_container bin, struct ccs_pdaf_pix_loc *pdaf,
	566	const void payload, const void endp,
	567	struct device *dev)
	568	{
	569	const struct __ccs_data_block_pdaf_pix_loc *__pdaf = payload;
	570	const struct __ccs_data_block_pdaf_pix_loc_block_desc_group *__bdesc_group;
	571	const struct __ccs_data_block_pdaf_pix_loc_pixel_desc *__pixel_desc;
	572	unsigned int i;
	573	u16 num_block_desc_groups;
	574	u8 max_block_type_id = 0;
	575	const u8 *__num_pixel_descs;
	576
	577	if (!is_contained(__pdaf, endp))
	578	return -ENODATA;
	579
	580	if (bin->base) {
	581	pdaf = bin_alloc(bin, sizeof(*pdaf));
	582	if (!*pdaf)
	583	return -ENOMEM;
	584	} else {
	585	bin_reserve(bin, sizeof(**pdaf));
	586	}
	587
	588	num_block_desc_groups =
	589	((u16)__pdaf->num_block_desc_groups[0] << 8) +
	590	__pdaf->num_block_desc_groups[1];
	591
	592	if (bin->base) {
	593	(*pdaf)->main_offset_x =
	594	((u16)__pdaf->main_offset_x[0] << 8) +
	595	__pdaf->main_offset_x[1];
	596	(*pdaf)->main_offset_y =
	597	((u16)__pdaf->main_offset_y[0] << 8) +
	598	__pdaf->main_offset_y[1];
	599	(*pdaf)->global_pdaf_type = __pdaf->global_pdaf_type;
	600	(*pdaf)->block_width = __pdaf->block_width;
	601	(*pdaf)->block_height = __pdaf->block_height;
	602	(*pdaf)->num_block_desc_groups = num_block_desc_groups;
	603	}
	604
	605	__bdesc_group = (const void *)(__pdaf + 1);
	606
	607	if (bin->base) {
	608	(*pdaf)->block_desc_groups =
	609	bin_alloc(bin,
	610	sizeof(struct ccs_pdaf_pix_loc_block_desc_group) *
	611	num_block_desc_groups);
	612	if (!(*pdaf)->block_desc_groups)
	613	return -ENOMEM;
	614	} else {
	615	bin_reserve(bin, sizeof(struct ccs_pdaf_pix_loc_block_desc_group) *
	616	num_block_desc_groups);
	617	}
	618
	619	for (i = 0; i < num_block_desc_groups; i++) {
	620	const struct __ccs_data_block_pdaf_pix_loc_block_desc *__bdesc;
	621	u16 num_block_descs;
	622	unsigned int j;
	623
	624	if (!is_contained(__bdesc_group, endp))
	625	return -ENODATA;
	626
	627	num_block_descs =
	628	((u16)__bdesc_group->num_block_descs[0] << 8) +
	629	__bdesc_group->num_block_descs[1];
	630
	631	if (bin->base) {
	632	(*pdaf)->block_desc_groups[i].repeat_y =
	633	__bdesc_group->repeat_y;
	634	(*pdaf)->block_desc_groups[i].num_block_descs =
	635	num_block_descs;
	636	}
	637
	638	__bdesc = (const void *)(__bdesc_group + 1);
	639
	640	if (bin->base) {
	641	(*pdaf)->block_desc_groups[i].block_descs =
	642	bin_alloc(bin,
	643	sizeof(struct ccs_pdaf_pix_loc_block_desc) *
	644	num_block_descs);
	645	if (!(*pdaf)->block_desc_groups[i].block_descs)
	646	return -ENOMEM;
	647	} else {
	648	bin_reserve(bin, sizeof(struct ccs_pdaf_pix_loc_block_desc) *
	649	num_block_descs);
	650	}
	651
	652	for (j = 0; j < num_block_descs; j++, __bdesc++) {
	653	struct ccs_pdaf_pix_loc_block_desc *bdesc;
	654
	655	if (!is_contained(__bdesc, endp))
	656	return -ENODATA;
	657
	658	if (max_block_type_id <= __bdesc->block_type_id)
	659	max_block_type_id = __bdesc->block_type_id + 1;
	660
	661	if (!bin->base)
	662	continue;
	663
	664	bdesc = &(*pdaf)->block_desc_groups[i].block_descs[j];
	665
	666	bdesc->repeat_x = ((u16)__bdesc->repeat_x[0] << 8)
	667	+ __bdesc->repeat_x[1];
	668
	669	if (__bdesc->block_type_id >= num_block_descs)
	670	return -EINVAL;
	671
	672	bdesc->block_type_id = __bdesc->block_type_id;
	673	}
	674
	675	__bdesc_group = (const void *)__bdesc;
	676	}
	677
	678	__num_pixel_descs = (const void *)__bdesc_group;
	679
	680	if (bin->base) {
	681	(*pdaf)->pixel_desc_groups =
	682	bin_alloc(bin,
	683	sizeof(struct ccs_pdaf_pix_loc_pixel_desc_group) *
	684	max_block_type_id);
	685	if (!(*pdaf)->pixel_desc_groups)
	686	return -ENOMEM;
	687	(*pdaf)->num_pixel_desc_grups = max_block_type_id;
	688	} else {
	689	bin_reserve(bin, sizeof(struct ccs_pdaf_pix_loc_pixel_desc_group) *
	690	max_block_type_id);
	691	}
	692
	693	for (i = 0; i < max_block_type_id; i++) {
	694	struct ccs_pdaf_pix_loc_pixel_desc_group *pdgroup;
	695	unsigned int j;
	696
	697	if (!is_contained(__num_pixel_descs, endp))
	698	return -ENODATA;
	699
	700	if (bin->base) {
	701	pdgroup = &(*pdaf)->pixel_desc_groups[i];
	702	pdgroup->descs =
	703	bin_alloc(bin,
	704	sizeof(struct ccs_pdaf_pix_loc_pixel_desc) *
	705	*__num_pixel_descs);
	706	if (!pdgroup->descs)
	707	return -ENOMEM;
	708	pdgroup->num_descs = *__num_pixel_descs;
	709	} else {
	710	bin_reserve(bin, sizeof(struct ccs_pdaf_pix_loc_pixel_desc) *
	711	*__num_pixel_descs);
	712	}
	713
	714	__pixel_desc = (const void *)(__num_pixel_descs + 1);
	715
	716	for (j = 0; j < *__num_pixel_descs; j++, __pixel_desc++) {
	717	struct ccs_pdaf_pix_loc_pixel_desc *pdesc;
	718
	719	if (!is_contained(__pixel_desc, endp))
	720	return -ENODATA;
	721
	722	if (!bin->base)
	723	continue;
	724
	725	pdesc = &pdgroup->descs[j];
	726	pdesc->pixel_type = __pixel_desc->pixel_type;
	727	pdesc->small_offset_x = __pixel_desc->small_offset_x;
	728	pdesc->small_offset_y = __pixel_desc->small_offset_y;
	729	}
	730
	731	__num_pixel_descs = (const void *)(__pixel_desc + 1);
	732	}
	733
	734	return 0;
	735	}
	736
	737	static int ccs_data_parse_license(struct bin_container *bin,
	738	char **__license,
	739	size_t *__license_length,
	740	const void payload, const void endp)
	741	{
	742	size_t size = endp - payload;
	743	char *license;
	744
	745	if (!bin->base) {
	746	bin_reserve(bin, size);
	747	return 0;
	748	}
	749
	750	license = bin_alloc(bin, size);
	751	if (!license)
	752	return -ENOMEM;
	753
	754	memcpy(license, payload, size);
	755
	756	*__license = license;
	757	*__license_length = size;
	758
	759	return 0;
	760	}
	761
	762	static int ccs_data_parse_end(bool end, const void payload, const void *endp,
	763	struct device *dev)
	764	{
	765	const struct __ccs_data_block_end *__end = payload;
	766
	767	if (__end + 1 != endp) {
	768	dev_dbg(dev, "Invalid end block length %u\n",
	769	(unsigned int)(endp - payload));
	770	return -ENODATA;
	771	}
	772
	773	*end = true;
	774
	775	return 0;
	776	}
	777
	778	static int __ccs_data_parse(struct bin_container *bin,
	779	struct ccs_data_container *ccsdata,
	780	const void data, size_t len, struct device dev,
	781	bool verbose)
	782	{
	783	const struct __ccs_data_block *block = data;
	784	const struct __ccs_data_block *endp = data + len;
	785	unsigned int version;
	786	bool is_first = true;
	787	int rval;
	788
	789	version = ccs_data_parse_format_version(block);
	790	if (version != CCS_STATIC_DATA_VERSION) {
	791	dev_dbg(dev, "Don't know how to handle version %u\n", version);
	792	return -EINVAL;
	793	}
	794
	795	if (verbose)
	796	dev_dbg(dev, "Parsing CCS static data version %u\n", version);
	797
	798	if (!bin->base)
	799	*ccsdata = (struct ccs_data_container){ 0 };
	800
	801	while (block < endp) {
	802	const struct __ccs_data_block *next_block;
	803	unsigned int block_id;
	804	const void *payload;
	805
	806	rval = ccs_data_block_parse_header(block, is_first, &block_id,
	807	&payload, &next_block, endp,
	808	dev,
	809	bin->base ? false : verbose);
	810
	811	if (rval < 0)
	812	return rval;
	813
	814	switch (block_id) {
	815	case CCS_DATA_BLOCK_ID_DUMMY:
	816	break;
	817	case CCS_DATA_BLOCK_ID_DATA_VERSION:
	818	rval = ccs_data_parse_version(bin, ccsdata, payload,
	819	next_block);
	820	if (rval < 0)
	821	return rval;
	822	break;
	823	case CCS_DATA_BLOCK_ID_SENSOR_READ_ONLY_REGS:
	824	rval = ccs_data_parse_regs(
	825	bin, &ccsdata->sensor_read_only_regs,
	826	&ccsdata->num_sensor_read_only_regs, payload,
	827	next_block, dev);
	828	if (rval < 0)
	829	return rval;
	830	break;
	831	case CCS_DATA_BLOCK_ID_SENSOR_MANUFACTURER_REGS:
	832	rval = ccs_data_parse_regs(
	833	bin, &ccsdata->sensor_manufacturer_regs,
	834	&ccsdata->num_sensor_manufacturer_regs, payload,
	835	next_block, dev);
	836	if (rval < 0)
	837	return rval;
	838	break;
	839	case CCS_DATA_BLOCK_ID_MODULE_READ_ONLY_REGS:
	840	rval = ccs_data_parse_regs(
	841	bin, &ccsdata->module_read_only_regs,
	842	&ccsdata->num_module_read_only_regs, payload,
	843	next_block, dev);
	844	if (rval < 0)
	845	return rval;
	846	break;
	847	case CCS_DATA_BLOCK_ID_MODULE_MANUFACTURER_REGS:
	848	rval = ccs_data_parse_regs(
	849	bin, &ccsdata->module_manufacturer_regs,
	850	&ccsdata->num_module_manufacturer_regs, payload,
	851	next_block, dev);
	852	if (rval < 0)
	853	return rval;
	854	break;
	855	case CCS_DATA_BLOCK_ID_SENSOR_PDAF_PIXEL_LOCATION:
	856	rval = ccs_data_parse_pdaf(bin, &ccsdata->sensor_pdaf,
	857	payload, next_block, dev);
	858	if (rval < 0)
	859	return rval;
	860	break;
	861	case CCS_DATA_BLOCK_ID_MODULE_PDAF_PIXEL_LOCATION:
	862	rval = ccs_data_parse_pdaf(bin, &ccsdata->module_pdaf,
	863	payload, next_block, dev);
	864	if (rval < 0)
	865	return rval;
	866	break;
	867	case CCS_DATA_BLOCK_ID_SENSOR_RULE_BASED_BLOCK:
	868	rval = ccs_data_parse_rules(
	869	bin, &ccsdata->sensor_rules,
	870	&ccsdata->num_sensor_rules, payload, next_block,
	871	dev);
	872	if (rval < 0)
	873	return rval;
	874	break;
	875	case CCS_DATA_BLOCK_ID_MODULE_RULE_BASED_BLOCK:
	876	rval = ccs_data_parse_rules(
	877	bin, &ccsdata->module_rules,
	878	&ccsdata->num_module_rules, payload, next_block,
	879	dev);
	880	if (rval < 0)
	881	return rval;
	882	break;
	883	case CCS_DATA_BLOCK_ID_LICENSE:
	884	rval = ccs_data_parse_license(bin, &ccsdata->license,
	885	&ccsdata->license_length,
	886	payload, next_block);
	887	if (rval < 0)
	888	return rval;
	889	break;
	890	case CCS_DATA_BLOCK_ID_END:
	891	rval = ccs_data_parse_end(&ccsdata->end, payload,
	892	next_block, dev);
	893	if (rval < 0)
	894	return rval;
	895	break;
	896	default:
	897	dev_dbg(dev, "WARNING: not handling block ID 0x%2.2x\n",
	898	block_id);
	899	}
	900
	901	block = next_block;
	902	is_first = false;
	903	}
	904
	905	return 0;
	906	}
	907
	908	/**
	909	* ccs_data_parse - Parse a CCS static data file into a usable in-memory
	910	* data structure
	911	* @ccsdata: CCS static data in-memory data structure
	912	* @data: CCS static data binary
	913	* @len: Length of @data
	914	* @dev: Device the data is related to (used for printing debug messages)
	915	* @verbose: Whether to be verbose or not
	916	*/
	917	int ccs_data_parse(struct ccs_data_container ccsdata, const void data,
	918	size_t len, struct device *dev, bool verbose)
	919	{
	920	struct bin_container bin = { 0 };
	921	int rval;
	922
	923	rval = __ccs_data_parse(&bin, ccsdata, data, len, dev, verbose);
	924	if (rval)
	925	return rval;
	926
	927	rval = bin_backing_alloc(&bin);
	928	if (rval)
	929	return rval;
	930
	931	rval = __ccs_data_parse(&bin, ccsdata, data, len, dev, false);
	932	if (rval)
	933	goto out_free;
	934
	935	if (verbose && ccsdata->version)
	936	print_ccs_data_version(dev, ccsdata->version);
	937
	938	if (bin.now != bin.end) {
	939	rval = -EPROTO;
	940	dev_dbg(dev, "parsing mismatch; base %p; now %p; end %p\n",
	941	bin.base, bin.now, bin.end);
	942	goto out_free;
	943	}
	944
	945	ccsdata->backing = bin.base;
	946
	947	return 0;
	948
	949	out_free:
	950	kvfree(bin.base);
	951
	952	return rval;
	953	}

drivers/media/i2c/ccs/ccs-data.h+228−0

@@ -0,0 +1,228 @@
	1	/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
	2	/*
	3	* CCS static data in-memory data structure definitions
	4	*
	5	* Copyright 2019--2020 Intel Corporation
	6	*/
	7
	8	#ifndef __CCS_DATA_H__
	9	#define __CCS_DATA_H__
	10
	11	#include <linux/types.h>
	12
	13	/**
	14	* struct ccs_data_block_version - CCS static data version
	15	* @version_major: Major version number
	16	* @version_minor: Minor version number
	17	* @date_year: Year
	18	* @date_month: Month
	19	* @date_day: Day
	20	*/
	21	struct ccs_data_block_version {
	22	u16 version_major;
	23	u16 version_minor;
	24	u16 date_year;
	25	u8 date_month;
	26	u8 date_day;
	27	};
	28
	29	/**
	30	* struct ccs_reg - CCS register value
	31	* @addr: The 16-bit address of the register
	32	* @len: Length of the data
	33	* @value: Data
	34	*/
	35	struct ccs_reg {
	36	u16 addr;
	37	u16 len;
	38	u8 *value;
	39	};
	40
	41	/**
	42	* struct ccs_if_rule - CCS static data if rule
	43	* @addr: Register address
	44	* @value: Register value
	45	* @mask: Value applied to both actual register value and @value
	46	*/
	47	struct ccs_if_rule {
	48	u16 addr;
	49	u8 value;
	50	u8 mask;
	51	};
	52
	53	/**
	54	* struct ccs_frame_format_desc - CCS frame format descriptor
	55	* @pixelcode: The pixelcode; CCS_DATA_BLOCK_FFD_PIXELCODE_*
	56	* @value: Value related to the pixelcode
	57	*/
	58	struct ccs_frame_format_desc {
	59	u8 pixelcode;
	60	u16 value;
	61	};
	62
	63	/**
	64	* struct ccs_frame_format_descs - A series of CCS frame format descriptors
	65	* @num_column_descs: Number of column descriptors
	66	* @num_row_descs: Number of row descriptors
	67	* @column_descs: Column descriptors
	68	* @row_descs: Row descriptors
	69	*/
	70	struct ccs_frame_format_descs {
	71	u8 num_column_descs;
	72	u8 num_row_descs;
	73	struct ccs_frame_format_desc *column_descs;
	74	struct ccs_frame_format_desc *row_descs;
	75	};
	76
	77	/**
	78	* struct ccs_pdaf_readout - CCS PDAF data readout descriptor
	79	* @pdaf_readout_info_order: PDAF readout order
	80	* @ffd: Frame format of PDAF data
	81	*/
	82	struct ccs_pdaf_readout {
	83	u8 pdaf_readout_info_order;
	84	struct ccs_frame_format_descs *ffd;
	85	};
	86
	87	/**
	88	* struct ccs_rule - A CCS static data rule
	89	* @num_if_rules: Number of if rules
	90	* @if_rules: If rules
	91	* @num_read_only_regs: Number of read-only registers
	92	* @read_only_regs: Read-only registers
	93	* @num_manufacturer_regs: Number of manufacturer-specific registers
	94	* @manufacturer_regs: Manufacturer-specific registers
	95	* @frame_format: Frame format
	96	* @pdaf_readout: PDAF readout
	97	*/
	98	struct ccs_rule {
	99	size_t num_if_rules;
	100	struct ccs_if_rule *if_rules;
	101	size_t num_read_only_regs;
	102	struct ccs_reg *read_only_regs;
	103	size_t num_manufacturer_regs;
	104	struct ccs_reg *manufacturer_regs;
	105	struct ccs_frame_format_descs *frame_format;
	106	struct ccs_pdaf_readout *pdaf_readout;
	107	};
	108
	109	/**
	110	* struct ccs_pdaf_pix_loc_block_desc - PDAF pixel location block descriptor
	111	* @block_type_id: Block type identifier, from 0 to n
	112	* @repeat_x: Number of times this block is repeated to right
	113	*/
	114	struct ccs_pdaf_pix_loc_block_desc {
	115	u8 block_type_id;
	116	u16 repeat_x;
	117	};
	118
	119	/**
	120	* struct ccs_pdaf_pix_loc_block_desc_group - PDAF pixel location block
	121	* descriptor group
	122	* @repeat_y: Number of times the group is repeated down
	123	* @num_block_descs: Number of block descriptors in @block_descs
	124	* @block_descs: Block descriptors
	125	*/
	126	struct ccs_pdaf_pix_loc_block_desc_group {
	127	u8 repeat_y;
	128	u16 num_block_descs;
	129	struct ccs_pdaf_pix_loc_block_desc *block_descs;
	130	};
	131
	132	/**
	133	* struct ccs_pdaf_pix_loc_block_desc - PDAF pixel location block descriptor
	134	* @pixel_type: Type of the pixel; CCS_DATA_PDAF_PIXEL_TYPE_*
	135	* @small_offset_x: offset X coordinate
	136	* @small_offset_y: offset Y coordinate
	137	*/
	138	struct ccs_pdaf_pix_loc_pixel_desc {
	139	u8 pixel_type;
	140	u8 small_offset_x;
	141	u8 small_offset_y;
	142	};
	143
	144	/**
	145	* struct ccs_pdaf_pix_loc_pixel_desc_group - PDAF pixel location pixel
	146	* descriptor group
	147	* @num_descs: Number of descriptors in @descs
	148	* @descs: PDAF pixel location pixel descriptors
	149	*/
	150	struct ccs_pdaf_pix_loc_pixel_desc_group {
	151	u8 num_descs;
	152	struct ccs_pdaf_pix_loc_pixel_desc *descs;
	153	};
	154
	155	/**
	156	* struct ccs_pdaf_pix_loc - PDAF pixel locations
	157	* @main_offset_x: Start X coordinate of PDAF pixel blocks
	158	* @main_offset_y: Start Y coordinate of PDAF pixel blocks
	159	* @global_pdaf_type: PDAF pattern type
	160	* @block_width: Width of a block in pixels
	161	* @block_height: Heigth of a block in pixels
	162	* @num_block_desc_groups: Number of block descriptor groups
	163	* @block_desc_groups: Block descriptor groups
	164	* @num_pixel_desc_grups: Number of pixel descriptor groups
	165	* @pixel_desc_groups: Pixel descriptor groups
	166	*/
	167	struct ccs_pdaf_pix_loc {
	168	u16 main_offset_x;
	169	u16 main_offset_y;
	170	u8 global_pdaf_type;
	171	u8 block_width;
	172	u8 block_height;
	173	u16 num_block_desc_groups;
	174	struct ccs_pdaf_pix_loc_block_desc_group *block_desc_groups;
	175	u8 num_pixel_desc_grups;
	176	struct ccs_pdaf_pix_loc_pixel_desc_group *pixel_desc_groups;
	177	};
	178
	179	/**
	180	* struct ccs_data_container - In-memory CCS static data
	181	* @version: CCS static data version
	182	* @num_sensor_read_only_regs: Number of the read-only registers for the sensor
	183	* @sensor_read_only_regs: Read-only registers for the sensor
	184	* @num_sensor_manufacturer_regs: Number of the manufacturer-specific registers
	185	* for the sensor
	186	* @sensor_manufacturer_regs: Manufacturer-specific registers for the sensor
	187	* @num_sensor_rules: Number of rules for the sensor
	188	* @sensor_rules: Rules for the sensor
	189	* @num_module_read_only_regs: Number of the read-only registers for the module
	190	* @module_read_only_regs: Read-only registers for the module
	191	* @num_module_manufacturer_regs: Number of the manufacturer-specific registers
	192	* for the module
	193	* @module_manufacturer_regs: Manufacturer-specific registers for the module
	194	* @num_module_rules: Number of rules for the module
	195	* @module_rules: Rules for the module
	196	* @sensor_pdaf: PDAF data for the sensor
	197	* @module_pdaf: PDAF data for the module
	198	* @license_length: Lenght of the license data
	199	* @license: License data
	200	* @end: Whether or not there's an end block
	201	* @backing: Raw data, pointed to from elsewhere so keep it around
	202	*/
	203	struct ccs_data_container {
	204	struct ccs_data_block_version *version;
	205	size_t num_sensor_read_only_regs;
	206	struct ccs_reg *sensor_read_only_regs;
	207	size_t num_sensor_manufacturer_regs;
	208	struct ccs_reg *sensor_manufacturer_regs;
	209	size_t num_sensor_rules;
	210	struct ccs_rule *sensor_rules;
	211	size_t num_module_read_only_regs;
	212	struct ccs_reg *module_read_only_regs;
	213	size_t num_module_manufacturer_regs;
	214	struct ccs_reg *module_manufacturer_regs;
	215	size_t num_module_rules;
	216	struct ccs_rule *module_rules;
	217	struct ccs_pdaf_pix_loc *sensor_pdaf;
	218	struct ccs_pdaf_pix_loc *module_pdaf;
	219	size_t license_length;
	220	char *license;
	221	bool end;
	222	void *backing;
	223	};
	224
	225	int ccs_data_parse(struct ccs_data_container ccsdata, const void data,
	226	size_t len, struct device *dev, bool verbose);
	227
	228	#endif /* __CCS_DATA_H__ */

drivers/media/i2c/ccs/ccs-limits.c+239−0

@@ -0,0 +1,239 @@
	1	// SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
	2	/* Copyright (C) 2019--2020 Intel Corporation */
	3
	4	#include "ccs-limits.h"
	5	#include "ccs-regs.h"
	6
	7	const struct ccs_limit ccs_limits[] = {
	8	{ CCS_R_FRAME_FORMAT_MODEL_TYPE, 1, 0, "frame_format_model_type" },
	9	{ CCS_R_FRAME_FORMAT_MODEL_SUBTYPE, 1, 0, "frame_format_model_subtype" },
	10	{ CCS_R_FRAME_FORMAT_DESCRIPTOR(0), 30, 0, "frame_format_descriptor" },
	11	{ CCS_R_FRAME_FORMAT_DESCRIPTOR_4(0), 32, 0, "frame_format_descriptor_4" },
	12	{ CCS_R_ANALOG_GAIN_CAPABILITY, 2, 0, "analog_gain_capability" },
	13	{ CCS_R_ANALOG_GAIN_CODE_MIN, 2, 0, "analog_gain_code_min" },
	14	{ CCS_R_ANALOG_GAIN_CODE_MAX, 2, 0, "analog_gain_code_max" },
	15	{ CCS_R_ANALOG_GAIN_CODE_STEP, 2, 0, "analog_gain_code_step" },
	16	{ CCS_R_ANALOG_GAIN_TYPE, 2, 0, "analog_gain_type" },
	17	{ CCS_R_ANALOG_GAIN_M0, 2, 0, "analog_gain_m0" },
	18	{ CCS_R_ANALOG_GAIN_C0, 2, 0, "analog_gain_c0" },
	19	{ CCS_R_ANALOG_GAIN_M1, 2, 0, "analog_gain_m1" },
	20	{ CCS_R_ANALOG_GAIN_C1, 2, 0, "analog_gain_c1" },
	21	{ CCS_R_ANALOG_LINEAR_GAIN_MIN, 2, 0, "analog_linear_gain_min" },
	22	{ CCS_R_ANALOG_LINEAR_GAIN_MAX, 2, 0, "analog_linear_gain_max" },
	23	{ CCS_R_ANALOG_LINEAR_GAIN_STEP_SIZE, 2, 0, "analog_linear_gain_step_size" },
	24	{ CCS_R_ANALOG_EXPONENTIAL_GAIN_MIN, 2, 0, "analog_exponential_gain_min" },
	25	{ CCS_R_ANALOG_EXPONENTIAL_GAIN_MAX, 2, 0, "analog_exponential_gain_max" },
	26	{ CCS_R_ANALOG_EXPONENTIAL_GAIN_STEP_SIZE, 2, 0, "analog_exponential_gain_step_size" },
	27	{ CCS_R_DATA_FORMAT_MODEL_TYPE, 1, 0, "data_format_model_type" },
	28	{ CCS_R_DATA_FORMAT_MODEL_SUBTYPE, 1, 0, "data_format_model_subtype" },
	29	{ CCS_R_DATA_FORMAT_DESCRIPTOR(0), 32, 0, "data_format_descriptor" },
	30	{ CCS_R_INTEGRATION_TIME_CAPABILITY, 2, 0, "integration_time_capability" },
	31	{ CCS_R_COARSE_INTEGRATION_TIME_MIN, 2, 0, "coarse_integration_time_min" },
	32	{ CCS_R_COARSE_INTEGRATION_TIME_MAX_MARGIN, 2, 0, "coarse_integration_time_max_margin" },
	33	{ CCS_R_FINE_INTEGRATION_TIME_MIN, 2, 0, "fine_integration_time_min" },
	34	{ CCS_R_FINE_INTEGRATION_TIME_MAX_MARGIN, 2, 0, "fine_integration_time_max_margin" },
	35	{ CCS_R_DIGITAL_GAIN_CAPABILITY, 1, 0, "digital_gain_capability" },
	36	{ CCS_R_DIGITAL_GAIN_MIN, 2, 0, "digital_gain_min" },
	37	{ CCS_R_DIGITAL_GAIN_MAX, 2, 0, "digital_gain_max" },
	38	{ CCS_R_DIGITAL_GAIN_STEP_SIZE, 2, 0, "digital_gain_step_size" },
	39	{ CCS_R_PEDESTAL_CAPABILITY, 1, 0, "Pedestal_capability" },
	40	{ CCS_R_ADC_CAPABILITY, 1, 0, "ADC_capability" },
	41	{ CCS_R_ADC_BIT_DEPTH_CAPABILITY, 4, 0, "ADC_bit_depth_capability" },
	42	{ CCS_R_MIN_EXT_CLK_FREQ_MHZ, 4, 0, "min_ext_clk_freq_mhz" },
	43	{ CCS_R_MAX_EXT_CLK_FREQ_MHZ, 4, 0, "max_ext_clk_freq_mhz" },
	44	{ CCS_R_MIN_PRE_PLL_CLK_DIV, 2, 0, "min_pre_pll_clk_div" },
	45	{ CCS_R_MAX_PRE_PLL_CLK_DIV, 2, 0, "max_pre_pll_clk_div" },
	46	{ CCS_R_MIN_PLL_IP_CLK_FREQ_MHZ, 4, 0, "min_pll_ip_clk_freq_mhz" },
	47	{ CCS_R_MAX_PLL_IP_CLK_FREQ_MHZ, 4, 0, "max_pll_ip_clk_freq_mhz" },
	48	{ CCS_R_MIN_PLL_MULTIPLIER, 2, 0, "min_pll_multiplier" },
	49	{ CCS_R_MAX_PLL_MULTIPLIER, 2, 0, "max_pll_multiplier" },
	50	{ CCS_R_MIN_PLL_OP_CLK_FREQ_MHZ, 4, 0, "min_pll_op_clk_freq_mhz" },
	51	{ CCS_R_MAX_PLL_OP_CLK_FREQ_MHZ, 4, 0, "max_pll_op_clk_freq_mhz" },
	52	{ CCS_R_MIN_VT_SYS_CLK_DIV, 2, 0, "min_vt_sys_clk_div" },
	53	{ CCS_R_MAX_VT_SYS_CLK_DIV, 2, 0, "max_vt_sys_clk_div" },
	54	{ CCS_R_MIN_VT_SYS_CLK_FREQ_MHZ, 4, 0, "min_vt_sys_clk_freq_mhz" },
	55	{ CCS_R_MAX_VT_SYS_CLK_FREQ_MHZ, 4, 0, "max_vt_sys_clk_freq_mhz" },
	56	{ CCS_R_MIN_VT_PIX_CLK_FREQ_MHZ, 4, 0, "min_vt_pix_clk_freq_mhz" },
	57	{ CCS_R_MAX_VT_PIX_CLK_FREQ_MHZ, 4, 0, "max_vt_pix_clk_freq_mhz" },
	58	{ CCS_R_MIN_VT_PIX_CLK_DIV, 2, 0, "min_vt_pix_clk_div" },
	59	{ CCS_R_MAX_VT_PIX_CLK_DIV, 2, 0, "max_vt_pix_clk_div" },
	60	{ CCS_R_CLOCK_CALCULATION, 1, 0, "clock_calculation" },
	61	{ CCS_R_NUM_OF_VT_LANES, 1, 0, "num_of_vt_lanes" },
	62	{ CCS_R_NUM_OF_OP_LANES, 1, 0, "num_of_op_lanes" },
	63	{ CCS_R_OP_BITS_PER_LANE, 1, 0, "op_bits_per_lane" },
	64	{ CCS_R_MIN_FRAME_LENGTH_LINES, 2, 0, "min_frame_length_lines" },
	65	{ CCS_R_MAX_FRAME_LENGTH_LINES, 2, 0, "max_frame_length_lines" },
	66	{ CCS_R_MIN_LINE_LENGTH_PCK, 2, 0, "min_line_length_pck" },
	67	{ CCS_R_MAX_LINE_LENGTH_PCK, 2, 0, "max_line_length_pck" },
	68	{ CCS_R_MIN_LINE_BLANKING_PCK, 2, 0, "min_line_blanking_pck" },
	69	{ CCS_R_MIN_FRAME_BLANKING_LINES, 2, 0, "min_frame_blanking_lines" },
	70	{ CCS_R_MIN_LINE_LENGTH_PCK_STEP_SIZE, 1, 0, "min_line_length_pck_step_size" },
	71	{ CCS_R_TIMING_MODE_CAPABILITY, 1, 0, "timing_mode_capability" },
	72	{ CCS_R_FRAME_MARGIN_MAX_VALUE, 2, 0, "frame_margin_max_value" },
	73	{ CCS_R_FRAME_MARGIN_MIN_VALUE, 1, 0, "frame_margin_min_value" },
	74	{ CCS_R_GAIN_DELAY_TYPE, 1, 0, "gain_delay_type" },
	75	{ CCS_R_MIN_OP_SYS_CLK_DIV, 2, 0, "min_op_sys_clk_div" },
	76	{ CCS_R_MAX_OP_SYS_CLK_DIV, 2, 0, "max_op_sys_clk_div" },
	77	{ CCS_R_MIN_OP_SYS_CLK_FREQ_MHZ, 4, 0, "min_op_sys_clk_freq_mhz" },
	78	{ CCS_R_MAX_OP_SYS_CLK_FREQ_MHZ, 4, 0, "max_op_sys_clk_freq_mhz" },
	79	{ CCS_R_MIN_OP_PIX_CLK_DIV, 2, 0, "min_op_pix_clk_div" },
	80	{ CCS_R_MAX_OP_PIX_CLK_DIV, 2, 0, "max_op_pix_clk_div" },
	81	{ CCS_R_MIN_OP_PIX_CLK_FREQ_MHZ, 4, 0, "min_op_pix_clk_freq_mhz" },
	82	{ CCS_R_MAX_OP_PIX_CLK_FREQ_MHZ, 4, 0, "max_op_pix_clk_freq_mhz" },
	83	{ CCS_R_X_ADDR_MIN, 2, 0, "x_addr_min" },
	84	{ CCS_R_Y_ADDR_MIN, 2, 0, "y_addr_min" },
	85	{ CCS_R_X_ADDR_MAX, 2, 0, "x_addr_max" },
	86	{ CCS_R_Y_ADDR_MAX, 2, 0, "y_addr_max" },
	87	{ CCS_R_MIN_X_OUTPUT_SIZE, 2, 0, "min_x_output_size" },
	88	{ CCS_R_MIN_Y_OUTPUT_SIZE, 2, 0, "min_y_output_size" },
	89	{ CCS_R_MAX_X_OUTPUT_SIZE, 2, 0, "max_x_output_size" },
	90	{ CCS_R_MAX_Y_OUTPUT_SIZE, 2, 0, "max_y_output_size" },
	91	{ CCS_R_X_ADDR_START_DIV_CONSTANT, 1, 0, "x_addr_start_div_constant" },
	92	{ CCS_R_Y_ADDR_START_DIV_CONSTANT, 1, 0, "y_addr_start_div_constant" },
	93	{ CCS_R_X_ADDR_END_DIV_CONSTANT, 1, 0, "x_addr_end_div_constant" },
	94	{ CCS_R_Y_ADDR_END_DIV_CONSTANT, 1, 0, "y_addr_end_div_constant" },
	95	{ CCS_R_X_SIZE_DIV, 1, 0, "x_size_div" },
	96	{ CCS_R_Y_SIZE_DIV, 1, 0, "y_size_div" },
	97	{ CCS_R_X_OUTPUT_DIV, 1, 0, "x_output_div" },
	98	{ CCS_R_Y_OUTPUT_DIV, 1, 0, "y_output_div" },
	99	{ CCS_R_NON_FLEXIBLE_RESOLUTION_SUPPORT, 1, 0, "non_flexible_resolution_support" },
	100	{ CCS_R_MIN_OP_PRE_PLL_CLK_DIV, 2, 0, "min_op_pre_pll_clk_div" },
	101	{ CCS_R_MAX_OP_PRE_PLL_CLK_DIV, 2, 0, "max_op_pre_pll_clk_div" },
	102	{ CCS_R_MIN_OP_PLL_IP_CLK_FREQ_MHZ, 4, 0, "min_op_pll_ip_clk_freq_mhz" },
	103	{ CCS_R_MAX_OP_PLL_IP_CLK_FREQ_MHZ, 4, 0, "max_op_pll_ip_clk_freq_mhz" },
	104	{ CCS_R_MIN_OP_PLL_MULTIPLIER, 2, 0, "min_op_pll_multiplier" },
	105	{ CCS_R_MAX_OP_PLL_MULTIPLIER, 2, 0, "max_op_pll_multiplier" },
	106	{ CCS_R_MIN_OP_PLL_OP_CLK_FREQ_MHZ, 4, 0, "min_op_pll_op_clk_freq_mhz" },
	107	{ CCS_R_MAX_OP_PLL_OP_CLK_FREQ_MHZ, 4, 0, "max_op_pll_op_clk_freq_mhz" },
	108	{ CCS_R_CLOCK_TREE_PLL_CAPABILITY, 1, 0, "clock_tree_pll_capability" },
	109	{ CCS_R_CLOCK_CAPA_TYPE_CAPABILITY, 1, 0, "clock_capa_type_capability" },
	110	{ CCS_R_MIN_EVEN_INC, 2, 0, "min_even_inc" },
	111	{ CCS_R_MIN_ODD_INC, 2, 0, "min_odd_inc" },
	112	{ CCS_R_MAX_EVEN_INC, 2, 0, "max_even_inc" },
	113	{ CCS_R_MAX_ODD_INC, 2, 0, "max_odd_inc" },
	114	{ CCS_R_AUX_SUBSAMP_CAPABILITY, 1, 0, "aux_subsamp_capability" },
	115	{ CCS_R_AUX_SUBSAMP_MONO_CAPABILITY, 1, 0, "aux_subsamp_mono_capability" },
	116	{ CCS_R_MONOCHROME_CAPABILITY, 1, 0, "monochrome_capability" },
	117	{ CCS_R_PIXEL_READOUT_CAPABILITY, 1, 0, "pixel_readout_capability" },
	118	{ CCS_R_MIN_EVEN_INC_MONO, 2, 0, "min_even_inc_mono" },
	119	{ CCS_R_MAX_EVEN_INC_MONO, 2, 0, "max_even_inc_mono" },
	120	{ CCS_R_MIN_ODD_INC_MONO, 2, 0, "min_odd_inc_mono" },
	121	{ CCS_R_MAX_ODD_INC_MONO, 2, 0, "max_odd_inc_mono" },
	122	{ CCS_R_MIN_EVEN_INC_BC2, 2, 0, "min_even_inc_bc2" },
	123	{ CCS_R_MAX_EVEN_INC_BC2, 2, 0, "max_even_inc_bc2" },
	124	{ CCS_R_MIN_ODD_INC_BC2, 2, 0, "min_odd_inc_bc2" },
	125	{ CCS_R_MAX_ODD_INC_BC2, 2, 0, "max_odd_inc_bc2" },
	126	{ CCS_R_MIN_EVEN_INC_MONO_BC2, 2, 0, "min_even_inc_mono_bc2" },
	127	{ CCS_R_MAX_EVEN_INC_MONO_BC2, 2, 0, "max_even_inc_mono_bc2" },
	128	{ CCS_R_MIN_ODD_INC_MONO_BC2, 2, 0, "min_odd_inc_mono_bc2" },
	129	{ CCS_R_MAX_ODD_INC_MONO_BC2, 2, 0, "max_odd_inc_mono_bc2" },
	130	{ CCS_R_SCALING_CAPABILITY, 2, 0, "scaling_capability" },
	131	{ CCS_R_SCALER_M_MIN, 2, 0, "scaler_m_min" },
	132	{ CCS_R_SCALER_M_MAX, 2, 0, "scaler_m_max" },
	133	{ CCS_R_SCALER_N_MIN, 2, 0, "scaler_n_min" },
	134	{ CCS_R_SCALER_N_MAX, 2, 0, "scaler_n_max" },
	135	{ CCS_R_DIGITAL_CROP_CAPABILITY, 1, 0, "digital_crop_capability" },
	136	{ CCS_R_HDR_CAPABILITY_1, 1, 0, "hdr_capability_1" },
	137	{ CCS_R_MIN_HDR_BIT_DEPTH, 1, 0, "min_hdr_bit_depth" },
	138	{ CCS_R_HDR_RESOLUTION_SUB_TYPES, 1, 0, "hdr_resolution_sub_types" },
	139	{ CCS_R_HDR_RESOLUTION_SUB_TYPE(0), 2, 0, "hdr_resolution_sub_type" },
	140	{ CCS_R_HDR_CAPABILITY_2, 1, 0, "hdr_capability_2" },
	141	{ CCS_R_MAX_HDR_BIT_DEPTH, 1, 0, "max_hdr_bit_depth" },
	142	{ CCS_R_USL_SUPPORT_CAPABILITY, 1, 0, "usl_support_capability" },
	143	{ CCS_R_USL_CLOCK_MODE_D_CAPABILITY, 1, 0, "usl_clock_mode_d_capability" },
	144	{ CCS_R_MIN_OP_SYS_CLK_DIV_REV, 1, 0, "min_op_sys_clk_div_rev" },
	145	{ CCS_R_MAX_OP_SYS_CLK_DIV_REV, 1, 0, "max_op_sys_clk_div_rev" },
	146	{ CCS_R_MIN_OP_PIX_CLK_DIV_REV, 1, 0, "min_op_pix_clk_div_rev" },
	147	{ CCS_R_MAX_OP_PIX_CLK_DIV_REV, 1, 0, "max_op_pix_clk_div_rev" },
	148	{ CCS_R_MIN_OP_SYS_CLK_FREQ_REV_MHZ, 4, 0, "min_op_sys_clk_freq_rev_mhz" },
	149	{ CCS_R_MAX_OP_SYS_CLK_FREQ_REV_MHZ, 4, 0, "max_op_sys_clk_freq_rev_mhz" },
	150	{ CCS_R_MIN_OP_PIX_CLK_FREQ_REV_MHZ, 4, 0, "min_op_pix_clk_freq_rev_mhz" },
	151	{ CCS_R_MAX_OP_PIX_CLK_FREQ_REV_MHZ, 4, 0, "max_op_pix_clk_freq_rev_mhz" },
	152	{ CCS_R_MAX_BITRATE_REV_D_MODE_MBPS, 4, 0, "max_bitrate_rev_d_mode_mbps" },
	153	{ CCS_R_MAX_SYMRATE_REV_C_MODE_MSPS, 4, 0, "max_symrate_rev_c_mode_msps" },
	154	{ CCS_R_COMPRESSION_CAPABILITY, 1, 0, "compression_capability" },
	155	{ CCS_R_TEST_MODE_CAPABILITY, 2, 0, "test_mode_capability" },
	156	{ CCS_R_PN9_DATA_FORMAT1, 1, 0, "pn9_data_format1" },
	157	{ CCS_R_PN9_DATA_FORMAT2, 1, 0, "pn9_data_format2" },
	158	{ CCS_R_PN9_DATA_FORMAT3, 1, 0, "pn9_data_format3" },
	159	{ CCS_R_PN9_DATA_FORMAT4, 1, 0, "pn9_data_format4" },
	160	{ CCS_R_PN9_MISC_CAPABILITY, 1, 0, "pn9_misc_capability" },
	161	{ CCS_R_TEST_PATTERN_CAPABILITY, 1, 0, "test_pattern_capability" },
	162	{ CCS_R_PATTERN_SIZE_DIV_M1, 1, 0, "pattern_size_div_m1" },
	163	{ CCS_R_FIFO_SUPPORT_CAPABILITY, 1, 0, "fifo_support_capability" },
	164	{ CCS_R_PHY_CTRL_CAPABILITY, 1, 0, "phy_ctrl_capability" },
	165	{ CCS_R_CSI_DPHY_LANE_MODE_CAPABILITY, 1, 0, "csi_dphy_lane_mode_capability" },
	166	{ CCS_R_CSI_SIGNALING_MODE_CAPABILITY, 1, 0, "csi_signaling_mode_capability" },
	167	{ CCS_R_FAST_STANDBY_CAPABILITY, 1, 0, "fast_standby_capability" },
	168	{ CCS_R_CSI_ADDRESS_CONTROL_CAPABILITY, 1, 0, "csi_address_control_capability" },
	169	{ CCS_R_DATA_TYPE_CAPABILITY, 1, 0, "data_type_capability" },
	170	{ CCS_R_CSI_CPHY_LANE_MODE_CAPABILITY, 1, 0, "csi_cphy_lane_mode_capability" },
	171	{ CCS_R_EMB_DATA_CAPABILITY, 1, 0, "emb_data_capability" },
	172	{ CCS_R_MAX_PER_LANE_BITRATE_LANE_D_MODE_MBPS(0), 16, 0, "max_per_lane_bitrate_lane_d_mode_mbps 0" },
	173	{ CCS_R_MAX_PER_LANE_BITRATE_LANE_D_MODE_MBPS(4), 16, CCS_L_FL_SAME_REG, "max_per_lane_bitrate_lane_d_mode_mbps 4" },
	174	{ CCS_R_TEMP_SENSOR_CAPABILITY, 1, 0, "temp_sensor_capability" },
	175	{ CCS_R_MAX_PER_LANE_BITRATE_LANE_C_MODE_MBPS(0), 16, 0, "max_per_lane_bitrate_lane_c_mode_mbps 0" },
	176	{ CCS_R_MAX_PER_LANE_BITRATE_LANE_C_MODE_MBPS(4), 16, CCS_L_FL_SAME_REG, "max_per_lane_bitrate_lane_c_mode_mbps 4" },
	177	{ CCS_R_DPHY_EQUALIZATION_CAPABILITY, 1, 0, "dphy_equalization_capability" },
	178	{ CCS_R_CPHY_EQUALIZATION_CAPABILITY, 1, 0, "cphy_equalization_capability" },
	179	{ CCS_R_DPHY_PREAMBLE_CAPABILITY, 1, 0, "dphy_preamble_capability" },
	180	{ CCS_R_DPHY_SSC_CAPABILITY, 1, 0, "dphy_ssc_capability" },
	181	{ CCS_R_CPHY_CALIBRATION_CAPABILITY, 1, 0, "cphy_calibration_capability" },
	182	{ CCS_R_DPHY_CALIBRATION_CAPABILITY, 1, 0, "dphy_calibration_capability" },
	183	{ CCS_R_PHY_CTRL_CAPABILITY_2, 1, 0, "phy_ctrl_capability_2" },
	184	{ CCS_R_LRTE_CPHY_CAPABILITY, 1, 0, "lrte_cphy_capability" },
	185	{ CCS_R_LRTE_DPHY_CAPABILITY, 1, 0, "lrte_dphy_capability" },
	186	{ CCS_R_ALPS_CAPABILITY_DPHY, 1, 0, "alps_capability_dphy" },
	187	{ CCS_R_ALPS_CAPABILITY_CPHY, 1, 0, "alps_capability_cphy" },
	188	{ CCS_R_SCRAMBLING_CAPABILITY, 1, 0, "scrambling_capability" },
	189	{ CCS_R_DPHY_MANUAL_CONSTANT, 1, 0, "dphy_manual_constant" },
	190	{ CCS_R_CPHY_MANUAL_CONSTANT, 1, 0, "cphy_manual_constant" },
	191	{ CCS_R_CSI2_INTERFACE_CAPABILITY_MISC, 1, 0, "CSI2_interface_capability_misc" },
	192	{ CCS_R_PHY_CTRL_CAPABILITY_3, 1, 0, "PHY_ctrl_capability_3" },
	193	{ CCS_R_DPHY_SF, 1, 0, "dphy_sf" },
	194	{ CCS_R_CPHY_SF, 1, 0, "cphy_sf" },
	195	{ CCS_R_DPHY_LIMITS_1, 1, 0, "dphy_limits_1" },
	196	{ CCS_R_DPHY_LIMITS_2, 1, 0, "dphy_limits_2" },
	197	{ CCS_R_DPHY_LIMITS_3, 1, 0, "dphy_limits_3" },
	198	{ CCS_R_DPHY_LIMITS_4, 1, 0, "dphy_limits_4" },
	199	{ CCS_R_DPHY_LIMITS_5, 1, 0, "dphy_limits_5" },
	200	{ CCS_R_DPHY_LIMITS_6, 1, 0, "dphy_limits_6" },
	201	{ CCS_R_CPHY_LIMITS_1, 1, 0, "cphy_limits_1" },
	202	{ CCS_R_CPHY_LIMITS_2, 1, 0, "cphy_limits_2" },
	203	{ CCS_R_CPHY_LIMITS_3, 1, 0, "cphy_limits_3" },
	204	{ CCS_R_MIN_FRAME_LENGTH_LINES_BIN, 2, 0, "min_frame_length_lines_bin" },
	205	{ CCS_R_MAX_FRAME_LENGTH_LINES_BIN, 2, 0, "max_frame_length_lines_bin" },
	206	{ CCS_R_MIN_LINE_LENGTH_PCK_BIN, 2, 0, "min_line_length_pck_bin" },
	207	{ CCS_R_MAX_LINE_LENGTH_PCK_BIN, 2, 0, "max_line_length_pck_bin" },
	208	{ CCS_R_MIN_LINE_BLANKING_PCK_BIN, 2, 0, "min_line_blanking_pck_bin" },
	209	{ CCS_R_FINE_INTEGRATION_TIME_MIN_BIN, 2, 0, "fine_integration_time_min_bin" },
	210	{ CCS_R_FINE_INTEGRATION_TIME_MAX_MARGIN_BIN, 2, 0, "fine_integration_time_max_margin_bin" },
	211	{ CCS_R_BINNING_CAPABILITY, 1, 0, "binning_capability" },
	212	{ CCS_R_BINNING_WEIGHTING_CAPABILITY, 1, 0, "binning_weighting_capability" },
	213	{ CCS_R_BINNING_SUB_TYPES, 1, 0, "binning_sub_types" },
	214	{ CCS_R_BINNING_SUB_TYPE(0), 64, 0, "binning_sub_type" },
	215	{ CCS_R_BINNING_WEIGHTING_MONO_CAPABILITY, 1, 0, "binning_weighting_mono_capability" },
	216	{ CCS_R_BINNING_SUB_TYPES_MONO, 1, 0, "binning_sub_types_mono" },
	217	{ CCS_R_BINNING_SUB_TYPE_MONO(0), 64, 0, "binning_sub_type_mono" },
	218	{ CCS_R_DATA_TRANSFER_IF_CAPABILITY, 1, 0, "data_transfer_if_capability" },
	219	{ CCS_R_SHADING_CORRECTION_CAPABILITY, 1, 0, "shading_correction_capability" },
	220	{ CCS_R_GREEN_IMBALANCE_CAPABILITY, 1, 0, "green_imbalance_capability" },
	221	{ CCS_R_MODULE_SPECIFIC_CORRECTION_CAPABILITY, 1, 0, "module_specific_correction_capability" },
	222	{ CCS_R_DEFECT_CORRECTION_CAPABILITY, 2, 0, "defect_correction_capability" },
	223	{ CCS_R_DEFECT_CORRECTION_CAPABILITY_2, 2, 0, "defect_correction_capability_2" },
	224	{ CCS_R_NF_CAPABILITY, 1, 0, "nf_capability" },
	225	{ CCS_R_OB_READOUT_CAPABILITY, 1, 0, "ob_readout_capability" },
	226	{ CCS_R_COLOR_FEEDBACK_CAPABILITY, 1, 0, "color_feedback_capability" },
	227	{ CCS_R_CFA_PATTERN_CAPABILITY, 1, 0, "CFA_pattern_capability" },
	228	{ CCS_R_CFA_PATTERN_CONVERSION_CAPABILITY, 1, 0, "CFA_pattern_conversion_capability" },
	229	{ CCS_R_FLASH_MODE_CAPABILITY, 1, 0, "flash_mode_capability" },
	230	{ CCS_R_SA_STROBE_MODE_CAPABILITY, 1, 0, "sa_strobe_mode_capability" },
	231	{ CCS_R_RESET_MAX_DELAY, 1, 0, "reset_max_delay" },
	232	{ CCS_R_RESET_MIN_TIME, 1, 0, "reset_min_time" },
	233	{ CCS_R_PDAF_CAPABILITY_1, 1, 0, "pdaf_capability_1" },
	234	{ CCS_R_PDAF_CAPABILITY_2, 1, 0, "pdaf_capability_2" },
	235	{ CCS_R_BRACKETING_LUT_CAPABILITY_1, 1, 0, "bracketing_lut_capability_1" },
	236	{ CCS_R_BRACKETING_LUT_CAPABILITY_2, 1, 0, "bracketing_lut_capability_2" },
	237	{ CCS_R_BRACKETING_LUT_SIZE, 1, 0, "bracketing_lut_size" },
	238	{ 0 } /* Guardian */
	239	};

drivers/media/i2c/ccs/ccs-limits.h+259−0

@@ -0,0 +1,259 @@
	1	/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
	2	/* Copyright (C) 2019--2020 Intel Corporation */
	3
	4	#ifndef __CCS_LIMITS_H__
	5	#define __CCS_LIMITS_H__
	6
	7	#include <linux/bits.h>
	8	#include <linux/types.h>
	9
	10	struct ccs_limit {
	11	u32 reg;
	12	u16 size;
	13	u16 flags;
	14	const char *name;
	15	};
	16
	17	#define CCS_L_FL_SAME_REG BIT(0)
	18
	19	extern const struct ccs_limit ccs_limits[];
	20
	21	#define CCS_L_FRAME_FORMAT_MODEL_TYPE 0
	22	#define CCS_L_FRAME_FORMAT_MODEL_SUBTYPE 1
	23	#define CCS_L_FRAME_FORMAT_DESCRIPTOR 2
	24	#define CCS_L_FRAME_FORMAT_DESCRIPTOR_OFFSET(n) ((n) * 2)
	25	#define CCS_L_FRAME_FORMAT_DESCRIPTOR_4 3
	26	#define CCS_L_FRAME_FORMAT_DESCRIPTOR_4_OFFSET(n) ((n) * 4)
	27	#define CCS_L_ANALOG_GAIN_CAPABILITY 4
	28	#define CCS_L_ANALOG_GAIN_CODE_MIN 5
	29	#define CCS_L_ANALOG_GAIN_CODE_MAX 6
	30	#define CCS_L_ANALOG_GAIN_CODE_STEP 7
	31	#define CCS_L_ANALOG_GAIN_TYPE 8
	32	#define CCS_L_ANALOG_GAIN_M0 9
	33	#define CCS_L_ANALOG_GAIN_C0 10
	34	#define CCS_L_ANALOG_GAIN_M1 11
	35	#define CCS_L_ANALOG_GAIN_C1 12
	36	#define CCS_L_ANALOG_LINEAR_GAIN_MIN 13
	37	#define CCS_L_ANALOG_LINEAR_GAIN_MAX 14
	38	#define CCS_L_ANALOG_LINEAR_GAIN_STEP_SIZE 15
	39	#define CCS_L_ANALOG_EXPONENTIAL_GAIN_MIN 16
	40	#define CCS_L_ANALOG_EXPONENTIAL_GAIN_MAX 17
	41	#define CCS_L_ANALOG_EXPONENTIAL_GAIN_STEP_SIZE 18
	42	#define CCS_L_DATA_FORMAT_MODEL_TYPE 19
	43	#define CCS_L_DATA_FORMAT_MODEL_SUBTYPE 20
	44	#define CCS_L_DATA_FORMAT_DESCRIPTOR 21
	45	#define CCS_L_DATA_FORMAT_DESCRIPTOR_OFFSET(n) ((n) * 2)
	46	#define CCS_L_INTEGRATION_TIME_CAPABILITY 22
	47	#define CCS_L_COARSE_INTEGRATION_TIME_MIN 23
	48	#define CCS_L_COARSE_INTEGRATION_TIME_MAX_MARGIN 24
	49	#define CCS_L_FINE_INTEGRATION_TIME_MIN 25
	50	#define CCS_L_FINE_INTEGRATION_TIME_MAX_MARGIN 26
	51	#define CCS_L_DIGITAL_GAIN_CAPABILITY 27
	52	#define CCS_L_DIGITAL_GAIN_MIN 28
	53	#define CCS_L_DIGITAL_GAIN_MAX 29
	54	#define CCS_L_DIGITAL_GAIN_STEP_SIZE 30
	55	#define CCS_L_PEDESTAL_CAPABILITY 31
	56	#define CCS_L_ADC_CAPABILITY 32
	57	#define CCS_L_ADC_BIT_DEPTH_CAPABILITY 33
	58	#define CCS_L_MIN_EXT_CLK_FREQ_MHZ 34
	59	#define CCS_L_MAX_EXT_CLK_FREQ_MHZ 35
	60	#define CCS_L_MIN_PRE_PLL_CLK_DIV 36
	61	#define CCS_L_MAX_PRE_PLL_CLK_DIV 37
	62	#define CCS_L_MIN_PLL_IP_CLK_FREQ_MHZ 38
	63	#define CCS_L_MAX_PLL_IP_CLK_FREQ_MHZ 39
	64	#define CCS_L_MIN_PLL_MULTIPLIER 40
	65	#define CCS_L_MAX_PLL_MULTIPLIER 41
	66	#define CCS_L_MIN_PLL_OP_CLK_FREQ_MHZ 42
	67	#define CCS_L_MAX_PLL_OP_CLK_FREQ_MHZ 43
	68	#define CCS_L_MIN_VT_SYS_CLK_DIV 44
	69	#define CCS_L_MAX_VT_SYS_CLK_DIV 45
	70	#define CCS_L_MIN_VT_SYS_CLK_FREQ_MHZ 46
	71	#define CCS_L_MAX_VT_SYS_CLK_FREQ_MHZ 47
	72	#define CCS_L_MIN_VT_PIX_CLK_FREQ_MHZ 48
	73	#define CCS_L_MAX_VT_PIX_CLK_FREQ_MHZ 49
	74	#define CCS_L_MIN_VT_PIX_CLK_DIV 50
	75	#define CCS_L_MAX_VT_PIX_CLK_DIV 51
	76	#define CCS_L_CLOCK_CALCULATION 52
	77	#define CCS_L_NUM_OF_VT_LANES 53
	78	#define CCS_L_NUM_OF_OP_LANES 54
	79	#define CCS_L_OP_BITS_PER_LANE 55
	80	#define CCS_L_MIN_FRAME_LENGTH_LINES 56
	81	#define CCS_L_MAX_FRAME_LENGTH_LINES 57
	82	#define CCS_L_MIN_LINE_LENGTH_PCK 58
	83	#define CCS_L_MAX_LINE_LENGTH_PCK 59
	84	#define CCS_L_MIN_LINE_BLANKING_PCK 60
	85	#define CCS_L_MIN_FRAME_BLANKING_LINES 61
	86	#define CCS_L_MIN_LINE_LENGTH_PCK_STEP_SIZE 62
	87	#define CCS_L_TIMING_MODE_CAPABILITY 63
	88	#define CCS_L_FRAME_MARGIN_MAX_VALUE 64
	89	#define CCS_L_FRAME_MARGIN_MIN_VALUE 65
	90	#define CCS_L_GAIN_DELAY_TYPE 66
	91	#define CCS_L_MIN_OP_SYS_CLK_DIV 67
	92	#define CCS_L_MAX_OP_SYS_CLK_DIV 68
	93	#define CCS_L_MIN_OP_SYS_CLK_FREQ_MHZ 69
	94	#define CCS_L_MAX_OP_SYS_CLK_FREQ_MHZ 70
	95	#define CCS_L_MIN_OP_PIX_CLK_DIV 71
	96	#define CCS_L_MAX_OP_PIX_CLK_DIV 72
	97	#define CCS_L_MIN_OP_PIX_CLK_FREQ_MHZ 73
	98	#define CCS_L_MAX_OP_PIX_CLK_FREQ_MHZ 74
	99	#define CCS_L_X_ADDR_MIN 75
	100	#define CCS_L_Y_ADDR_MIN 76
	101	#define CCS_L_X_ADDR_MAX 77
	102	#define CCS_L_Y_ADDR_MAX 78
	103	#define CCS_L_MIN_X_OUTPUT_SIZE 79
	104	#define CCS_L_MIN_Y_OUTPUT_SIZE 80
	105	#define CCS_L_MAX_X_OUTPUT_SIZE 81
	106	#define CCS_L_MAX_Y_OUTPUT_SIZE 82
	107	#define CCS_L_X_ADDR_START_DIV_CONSTANT 83
	108	#define CCS_L_Y_ADDR_START_DIV_CONSTANT 84
	109	#define CCS_L_X_ADDR_END_DIV_CONSTANT 85
	110	#define CCS_L_Y_ADDR_END_DIV_CONSTANT 86
	111	#define CCS_L_X_SIZE_DIV 87
	112	#define CCS_L_Y_SIZE_DIV 88
	113	#define CCS_L_X_OUTPUT_DIV 89
	114	#define CCS_L_Y_OUTPUT_DIV 90
	115	#define CCS_L_NON_FLEXIBLE_RESOLUTION_SUPPORT 91
	116	#define CCS_L_MIN_OP_PRE_PLL_CLK_DIV 92
	117	#define CCS_L_MAX_OP_PRE_PLL_CLK_DIV 93
	118	#define CCS_L_MIN_OP_PLL_IP_CLK_FREQ_MHZ 94
	119	#define CCS_L_MAX_OP_PLL_IP_CLK_FREQ_MHZ 95
	120	#define CCS_L_MIN_OP_PLL_MULTIPLIER 96
	121	#define CCS_L_MAX_OP_PLL_MULTIPLIER 97
	122	#define CCS_L_MIN_OP_PLL_OP_CLK_FREQ_MHZ 98
	123	#define CCS_L_MAX_OP_PLL_OP_CLK_FREQ_MHZ 99
	124	#define CCS_L_CLOCK_TREE_PLL_CAPABILITY 100
	125	#define CCS_L_CLOCK_CAPA_TYPE_CAPABILITY 101
	126	#define CCS_L_MIN_EVEN_INC 102
	127	#define CCS_L_MIN_ODD_INC 103
	128	#define CCS_L_MAX_EVEN_INC 104
	129	#define CCS_L_MAX_ODD_INC 105
	130	#define CCS_L_AUX_SUBSAMP_CAPABILITY 106
	131	#define CCS_L_AUX_SUBSAMP_MONO_CAPABILITY 107
	132	#define CCS_L_MONOCHROME_CAPABILITY 108
	133	#define CCS_L_PIXEL_READOUT_CAPABILITY 109
	134	#define CCS_L_MIN_EVEN_INC_MONO 110
	135	#define CCS_L_MAX_EVEN_INC_MONO 111
	136	#define CCS_L_MIN_ODD_INC_MONO 112
	137	#define CCS_L_MAX_ODD_INC_MONO 113
	138	#define CCS_L_MIN_EVEN_INC_BC2 114
	139	#define CCS_L_MAX_EVEN_INC_BC2 115
	140	#define CCS_L_MIN_ODD_INC_BC2 116
	141	#define CCS_L_MAX_ODD_INC_BC2 117
	142	#define CCS_L_MIN_EVEN_INC_MONO_BC2 118
	143	#define CCS_L_MAX_EVEN_INC_MONO_BC2 119
	144	#define CCS_L_MIN_ODD_INC_MONO_BC2 120
	145	#define CCS_L_MAX_ODD_INC_MONO_BC2 121
	146	#define CCS_L_SCALING_CAPABILITY 122
	147	#define CCS_L_SCALER_M_MIN 123
	148	#define CCS_L_SCALER_M_MAX 124
	149	#define CCS_L_SCALER_N_MIN 125
	150	#define CCS_L_SCALER_N_MAX 126
	151	#define CCS_L_DIGITAL_CROP_CAPABILITY 127
	152	#define CCS_L_HDR_CAPABILITY_1 128
	153	#define CCS_L_MIN_HDR_BIT_DEPTH 129
	154	#define CCS_L_HDR_RESOLUTION_SUB_TYPES 130
	155	#define CCS_L_HDR_RESOLUTION_SUB_TYPE 131
	156	#define CCS_L_HDR_RESOLUTION_SUB_TYPE_OFFSET(n) (n)
	157	#define CCS_L_HDR_CAPABILITY_2 132
	158	#define CCS_L_MAX_HDR_BIT_DEPTH 133
	159	#define CCS_L_USL_SUPPORT_CAPABILITY 134
	160	#define CCS_L_USL_CLOCK_MODE_D_CAPABILITY 135
	161	#define CCS_L_MIN_OP_SYS_CLK_DIV_REV 136
	162	#define CCS_L_MAX_OP_SYS_CLK_DIV_REV 137
	163	#define CCS_L_MIN_OP_PIX_CLK_DIV_REV 138
	164	#define CCS_L_MAX_OP_PIX_CLK_DIV_REV 139
	165	#define CCS_L_MIN_OP_SYS_CLK_FREQ_REV_MHZ 140
	166	#define CCS_L_MAX_OP_SYS_CLK_FREQ_REV_MHZ 141
	167	#define CCS_L_MIN_OP_PIX_CLK_FREQ_REV_MHZ 142
	168	#define CCS_L_MAX_OP_PIX_CLK_FREQ_REV_MHZ 143
	169	#define CCS_L_MAX_BITRATE_REV_D_MODE_MBPS 144
	170	#define CCS_L_MAX_SYMRATE_REV_C_MODE_MSPS 145
	171	#define CCS_L_COMPRESSION_CAPABILITY 146
	172	#define CCS_L_TEST_MODE_CAPABILITY 147
	173	#define CCS_L_PN9_DATA_FORMAT1 148
	174	#define CCS_L_PN9_DATA_FORMAT2 149
	175	#define CCS_L_PN9_DATA_FORMAT3 150
	176	#define CCS_L_PN9_DATA_FORMAT4 151
	177	#define CCS_L_PN9_MISC_CAPABILITY 152
	178	#define CCS_L_TEST_PATTERN_CAPABILITY 153
	179	#define CCS_L_PATTERN_SIZE_DIV_M1 154
	180	#define CCS_L_FIFO_SUPPORT_CAPABILITY 155
	181	#define CCS_L_PHY_CTRL_CAPABILITY 156
	182	#define CCS_L_CSI_DPHY_LANE_MODE_CAPABILITY 157
	183	#define CCS_L_CSI_SIGNALING_MODE_CAPABILITY 158
	184	#define CCS_L_FAST_STANDBY_CAPABILITY 159
	185	#define CCS_L_CSI_ADDRESS_CONTROL_CAPABILITY 160
	186	#define CCS_L_DATA_TYPE_CAPABILITY 161
	187	#define CCS_L_CSI_CPHY_LANE_MODE_CAPABILITY 162
	188	#define CCS_L_EMB_DATA_CAPABILITY 163
	189	#define CCS_L_MAX_PER_LANE_BITRATE_LANE_D_MODE_MBPS 164
	190	#define CCS_L_MAX_PER_LANE_BITRATE_LANE_D_MODE_MBPS_OFFSET(n) ((n) * 4)
	191	#define CCS_L_TEMP_SENSOR_CAPABILITY 165
	192	#define CCS_L_MAX_PER_LANE_BITRATE_LANE_C_MODE_MBPS 166
	193	#define CCS_L_MAX_PER_LANE_BITRATE_LANE_C_MODE_MBPS_OFFSET(n) ((n) * 4)
	194	#define CCS_L_DPHY_EQUALIZATION_CAPABILITY 167
	195	#define CCS_L_CPHY_EQUALIZATION_CAPABILITY 168
	196	#define CCS_L_DPHY_PREAMBLE_CAPABILITY 169
	197	#define CCS_L_DPHY_SSC_CAPABILITY 170
	198	#define CCS_L_CPHY_CALIBRATION_CAPABILITY 171
	199	#define CCS_L_DPHY_CALIBRATION_CAPABILITY 172
	200	#define CCS_L_PHY_CTRL_CAPABILITY_2 173
	201	#define CCS_L_LRTE_CPHY_CAPABILITY 174
	202	#define CCS_L_LRTE_DPHY_CAPABILITY 175
	203	#define CCS_L_ALPS_CAPABILITY_DPHY 176
	204	#define CCS_L_ALPS_CAPABILITY_CPHY 177
	205	#define CCS_L_SCRAMBLING_CAPABILITY 178
	206	#define CCS_L_DPHY_MANUAL_CONSTANT 179
	207	#define CCS_L_CPHY_MANUAL_CONSTANT 180
	208	#define CCS_L_CSI2_INTERFACE_CAPABILITY_MISC 181
	209	#define CCS_L_PHY_CTRL_CAPABILITY_3 182
	210	#define CCS_L_DPHY_SF 183
	211	#define CCS_L_CPHY_SF 184
	212	#define CCS_L_DPHY_LIMITS_1 185
	213	#define CCS_L_DPHY_LIMITS_2 186
	214	#define CCS_L_DPHY_LIMITS_3 187
	215	#define CCS_L_DPHY_LIMITS_4 188
	216	#define CCS_L_DPHY_LIMITS_5 189
	217	#define CCS_L_DPHY_LIMITS_6 190
	218	#define CCS_L_CPHY_LIMITS_1 191
	219	#define CCS_L_CPHY_LIMITS_2 192
	220	#define CCS_L_CPHY_LIMITS_3 193
	221	#define CCS_L_MIN_FRAME_LENGTH_LINES_BIN 194
	222	#define CCS_L_MAX_FRAME_LENGTH_LINES_BIN 195
	223	#define CCS_L_MIN_LINE_LENGTH_PCK_BIN 196
	224	#define CCS_L_MAX_LINE_LENGTH_PCK_BIN 197
	225	#define CCS_L_MIN_LINE_BLANKING_PCK_BIN 198
	226	#define CCS_L_FINE_INTEGRATION_TIME_MIN_BIN 199
	227	#define CCS_L_FINE_INTEGRATION_TIME_MAX_MARGIN_BIN 200
	228	#define CCS_L_BINNING_CAPABILITY 201
	229	#define CCS_L_BINNING_WEIGHTING_CAPABILITY 202
	230	#define CCS_L_BINNING_SUB_TYPES 203
	231	#define CCS_L_BINNING_SUB_TYPE 204
	232	#define CCS_L_BINNING_SUB_TYPE_OFFSET(n) (n)
	233	#define CCS_L_BINNING_WEIGHTING_MONO_CAPABILITY 205
	234	#define CCS_L_BINNING_SUB_TYPES_MONO 206
	235	#define CCS_L_BINNING_SUB_TYPE_MONO 207
	236	#define CCS_L_BINNING_SUB_TYPE_MONO_OFFSET(n) (n)
	237	#define CCS_L_DATA_TRANSFER_IF_CAPABILITY 208
	238	#define CCS_L_SHADING_CORRECTION_CAPABILITY 209
	239	#define CCS_L_GREEN_IMBALANCE_CAPABILITY 210
	240	#define CCS_L_MODULE_SPECIFIC_CORRECTION_CAPABILITY 211
	241	#define CCS_L_DEFECT_CORRECTION_CAPABILITY 212
	242	#define CCS_L_DEFECT_CORRECTION_CAPABILITY_2 213
	243	#define CCS_L_NF_CAPABILITY 214
	244	#define CCS_L_OB_READOUT_CAPABILITY 215
	245	#define CCS_L_COLOR_FEEDBACK_CAPABILITY 216
	246	#define CCS_L_CFA_PATTERN_CAPABILITY 217
	247	#define CCS_L_CFA_PATTERN_CONVERSION_CAPABILITY 218
	248	#define CCS_L_FLASH_MODE_CAPABILITY 219
	249	#define CCS_L_SA_STROBE_MODE_CAPABILITY 220
	250	#define CCS_L_RESET_MAX_DELAY 221
	251	#define CCS_L_RESET_MIN_TIME 222
	252	#define CCS_L_PDAF_CAPABILITY_1 223
	253	#define CCS_L_PDAF_CAPABILITY_2 224
	254	#define CCS_L_BRACKETING_LUT_CAPABILITY_1 225
	255	#define CCS_L_BRACKETING_LUT_CAPABILITY_2 226
	256	#define CCS_L_BRACKETING_LUT_SIZE 227
	257	#define CCS_L_LAST 228
	258
	259	#endif /* __CCS_LIMITS_H__ */

drivers/media/i2c/ccs/ccs-quirk.crenamed from drivers/media/i2c/smiapp/smiapp-quirk.c+46−59

 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * drivers/media/i2c/smiapp/smiapp-quirk.c
+ * drivers/media/i2c/ccs/ccs-quirk.c
  *
- * Generic driver for SMIA/SMIA++ compliant camera modules
+ * Generic driver for MIPI CCS/SMIA/SMIA++ compliant camera sensors
  *
+ * Copyright (C) 2020 Intel Corporation
  * Copyright (C) 2011--2012 Nokia Corporation
- * Contact: Sakari Ailus <sakari.ailus@iki.fi>
+ * Contact: Sakari Ailus <sakari.ailus@linux.intel.com>
  */
 #include <linux/delay.h>
-#include "smiapp.h"
+#include "ccs.h"
+#include "ccs-limits.h"
-static int smiapp_write_8(struct smiapp_sensor *sensor, u16 reg, u8 val)
+static int ccs_write_addr_8s(struct ccs_sensor *sensor,
-{
+			     const struct ccs_reg_8 *regs, int len)
-	return smiapp_write(sensor, SMIAPP_REG_MK_U8(reg), val);
-}
-static int smiapp_write_8s(struct smiapp_sensor *sensor,
-			   const struct smiapp_reg_8 *regs, int len)
 {
 	struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
 	int rval;
 	for (; len > 0; len--, regs++) {
-		rval = smiapp_write_8(sensor, regs->reg, regs->val);
+		rval = ccs_write_addr(sensor, regs->reg, regs->val);
 		if (rval < 0) {
 			dev_err(&client->dev,
 				"error %d writing reg 0x%4.4x, val 0x%2.2x",
 	return 0;
 }
-void smiapp_replace_limit(struct smiapp_sensor *sensor,
+static int jt8ew9_limits(struct ccs_sensor *sensor)
-			  u32 limit, u32 val)
-{
-	struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
-	dev_dbg(&client->dev, "quirk: 0x%8.8x \"%s\" = %d, 0x%x\n",
-		smiapp_reg_limits[limit].addr,
-		smiapp_reg_limits[limit].what, val, val);
-	sensor->limits[limit] = val;
-}
-static int jt8ew9_limits(struct smiapp_sensor *sensor)
 {
-	if (sensor->minfo.revision_number_major < 0x03)
+	if (sensor->minfo.revision_number < 0x0300)
 		sensor->frame_skip = 1;
 	/* Below 24 gain doesn't have effect at all, */
 	/* but ~59 is needed for full dynamic range */
-	smiapp_replace_limit(sensor, SMIAPP_LIMIT_ANALOGUE_GAIN_CODE_MIN, 59);
+	ccs_replace_limit(sensor, CCS_L_ANALOG_GAIN_CODE_MIN, 0, 59);
-	smiapp_replace_limit(
+	ccs_replace_limit(sensor, CCS_L_ANALOG_GAIN_CODE_MAX, 0, 6000);
-		sensor, SMIAPP_LIMIT_ANALOGUE_GAIN_CODE_MAX, 6000);
 	return 0;
 }
-static int jt8ew9_post_poweron(struct smiapp_sensor *sensor)
+static int jt8ew9_post_poweron(struct ccs_sensor *sensor)
 {
-	static const struct smiapp_reg_8 regs[] = {
+	static const struct ccs_reg_8 regs[] = {
 		{ 0x30a3, 0xd8 }, /* Output port control : LVDS ports only */
 		{ 0x30ae, 0x00 }, /* 0x0307 pll_multiplier maximum value on PLL input 9.6MHz ( 19.2MHz is divided on pre_pll_div) */
 		{ 0x30af, 0xd0 }, /* 0x0307 pll_multiplier maximum value on PLL input 9.6MHz ( 19.2MHz is divided on pre_pll_div) */
 	};
-	return smiapp_write_8s(sensor, regs, ARRAY_SIZE(regs));
+	return ccs_write_addr_8s(sensor, regs, ARRAY_SIZE(regs));
 }
-const struct smiapp_quirk smiapp_jt8ew9_quirk = {
+const struct ccs_quirk smiapp_jt8ew9_quirk = {
 	.limits = jt8ew9_limits,
 	.post_poweron = jt8ew9_post_poweron,
 };
-static int imx125es_post_poweron(struct smiapp_sensor *sensor)
+static int imx125es_post_poweron(struct ccs_sensor *sensor)
 {
 	/* Taken from v02. No idea what the other two are. */
-	static const struct smiapp_reg_8 regs[] = {
+	static const struct ccs_reg_8 regs[] = {
 		/*
 		 * 0x3302: clk during frame blanking:
 		 * 0x00 - HS mode, 0x01 - LP11
 		{ 0x3b08, 0x8c },
 	};
-	return smiapp_write_8s(sensor, regs, ARRAY_SIZE(regs));
+	return ccs_write_addr_8s(sensor, regs, ARRAY_SIZE(regs));
 }
-const struct smiapp_quirk smiapp_imx125es_quirk = {
+const struct ccs_quirk smiapp_imx125es_quirk = {
 	.post_poweron = imx125es_post_poweron,
 };
-static int jt8ev1_limits(struct smiapp_sensor *sensor)
+static int jt8ev1_limits(struct ccs_sensor *sensor)
 {
-	smiapp_replace_limit(sensor, SMIAPP_LIMIT_X_ADDR_MAX, 4271);
+	ccs_replace_limit(sensor, CCS_L_X_ADDR_MAX, 0, 4271);
-	smiapp_replace_limit(sensor,
+	ccs_replace_limit(sensor, CCS_L_MIN_LINE_BLANKING_PCK_BIN, 0, 184);
-			     SMIAPP_LIMIT_MIN_LINE_BLANKING_PCK_BIN, 184);
 	return 0;
 }
-static int jt8ev1_post_poweron(struct smiapp_sensor *sensor)
+static int jt8ev1_post_poweron(struct ccs_sensor *sensor)
 {
 	struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
 	int rval;
-	static const struct smiapp_reg_8 regs[] = {
+	static const struct ccs_reg_8 regs[] = {
 		{ 0x3031, 0xcd }, /* For digital binning (EQ_MONI) */
 		{ 0x30a3, 0xd0 }, /* FLASH STROBE enable */
 		{ 0x3237, 0x00 }, /* For control of pulse timing for ADC */
 		{ 0x33cf, 0xec }, /* For Black sun */
 		{ 0x3328, 0x80 }, /* Ugh. No idea what's this. */
 	};
-	static const struct smiapp_reg_8 regs_96[] = {
+	static const struct ccs_reg_8 regs_96[] = {
 		{ 0x30ae, 0x00 }, /* For control of ADC clock */
 		{ 0x30af, 0xd0 },
 		{ 0x30b0, 0x01 },
 	};
-	rval = smiapp_write_8s(sensor, regs, ARRAY_SIZE(regs));
+	rval = ccs_write_addr_8s(sensor, regs, ARRAY_SIZE(regs));
 	if (rval < 0)
 		return rval;
-	switch (sensor->hwcfg->ext_clk) {
+	switch (sensor->hwcfg.ext_clk) {
 	case 9600000:
-		return smiapp_write_8s(sensor, regs_96,
+		return ccs_write_addr_8s(sensor, regs_96,
 				       ARRAY_SIZE(regs_96));
 	default:
 		dev_warn(&client->dev, "no MSRs for %d Hz ext_clk\n",
-			 sensor->hwcfg->ext_clk);
+			 sensor->hwcfg.ext_clk);
 		return 0;
 	}
 }
-static int jt8ev1_pre_streamon(struct smiapp_sensor *sensor)
+static int jt8ev1_pre_streamon(struct ccs_sensor *sensor)
 {
-	return smiapp_write_8(sensor, 0x3328, 0x00);
+	return ccs_write_addr(sensor, 0x3328, 0x00);
 }
-static int jt8ev1_post_streamoff(struct smiapp_sensor *sensor)
+static int jt8ev1_post_streamoff(struct ccs_sensor *sensor)
 {
 	int rval;
 	/* Workaround: allows fast standby to work properly */
-	rval = smiapp_write_8(sensor, 0x3205, 0x04);
+	rval = ccs_write_addr(sensor, 0x3205, 0x04);
 	if (rval < 0)
 		return rval;
 	usleep_range(2000, 2050);
 	/* Restore it */
-	rval = smiapp_write_8(sensor, 0x3205, 0x00);
+	rval = ccs_write_addr(sensor, 0x3205, 0x00);
 	if (rval < 0)
 		return rval;
-	return smiapp_write_8(sensor, 0x3328, 0x80);
+	return ccs_write_addr(sensor, 0x3328, 0x80);
 }
-static int jt8ev1_init(struct smiapp_sensor *sensor)
+static int jt8ev1_init(struct ccs_sensor *sensor)
 {
-	sensor->pll.flags |= SMIAPP_PLL_FLAG_OP_PIX_CLOCK_PER_LANE;
+	sensor->pll.flags |= CCS_PLL_FLAG_LANE_SPEED_MODEL |
+		CCS_PLL_FLAG_LINK_DECOUPLED;
+	sensor->pll.vt_lanes = 1;
+	sensor->pll.op_lanes = sensor->pll.csi2.lanes;
 	return 0;
 }
-const struct smiapp_quirk smiapp_jt8ev1_quirk = {
+const struct ccs_quirk smiapp_jt8ev1_quirk = {
 	.limits = jt8ev1_limits,
 	.post_poweron = jt8ev1_post_poweron,
 	.pre_streamon = jt8ev1_pre_streamon,
 	.init = jt8ev1_init,
 };
-static int tcm8500md_limits(struct smiapp_sensor *sensor)
+static int tcm8500md_limits(struct ccs_sensor *sensor)
 {
-	smiapp_replace_limit(sensor, SMIAPP_LIMIT_MIN_PLL_IP_FREQ_HZ, 2700000);
+	ccs_replace_limit(sensor, CCS_L_MIN_PLL_IP_CLK_FREQ_MHZ, 0, 2700000);
 	return 0;
 }
-const struct smiapp_quirk smiapp_tcm8500md_quirk = {
+const struct ccs_quirk smiapp_tcm8500md_quirk = {
 	.limits = tcm8500md_limits,
 };

drivers/media/i2c/ccs/ccs-quirk.hrenamed from drivers/media/i2c/smiapp/smiapp-quirk.h+26−28

@@ -1,20 +1,21 @@
1	/* SPDX-License-Identifier: GPL-2.0-only */	1	/* SPDX-License-Identifier: GPL-2.0-only */
2	/*	2	/*
3	* drivers/media/i2c/smiapp/smiapp-quirk.h	3	* drivers/media/i2c/ccs/ccs-quirk.h
4	*	4	*
5	* Generic driver for SMIA/SMIA++ compliant camera modules	5	* Generic driver for MIPI CCS/SMIA/SMIA++ compliant camera sensors
6	*	6	*
		7	* Copyright (C) 2020 Intel Corporation
7	* Copyright (C) 2011--2012 Nokia Corporation	8	* Copyright (C) 2011--2012 Nokia Corporation
8	* Contact: Sakari Ailus <sakari.ailus@iki.fi>	9	* Contact: Sakari Ailus <sakari.ailus@linux.intel.com>
9	*/	10	*/
10		11
11	#ifndef __SMIAPP_QUIRK__	12	#ifndef __CCS_QUIRK__
12	#define __SMIAPP_QUIRK__	13	#define __CCS_QUIRK__
13		14
14	struct smiapp_sensor;	15	struct ccs_sensor;
15		16
16	/**	17	/**
17	* struct smiapp_quirk - quirks for sensors that deviate from SMIA++ standard	18	* struct ccs_quirk - quirks for sensors that deviate from SMIA++ standard
18	*	19	*
19	* @limits: Replace sensor->limits with values which can't be read from	20	* @limits: Replace sensor->limits with values which can't be read from
20	* sensor registers. Called the first time the sensor is powered up.	21	* sensor registers. Called the first time the sensor is powered up.
@@ -36,46 +37,43 @@ struct smiapp_sensor; · 15 unmodified lines
36	* access may be done by the caller (default read	37	* access may be done by the caller (default read
37	* value is zero), else negative error code on error	38	* value is zero), else negative error code on error
38	*/	39	*/
39	struct smiapp_quirk {	40	struct ccs_quirk {
40	int (limits)(struct smiapp_sensor sensor);	41	int (limits)(struct ccs_sensor sensor);
41	int (post_poweron)(struct smiapp_sensor sensor);	42	int (post_poweron)(struct ccs_sensor sensor);
42	int (pre_streamon)(struct smiapp_sensor sensor);	43	int (pre_streamon)(struct ccs_sensor sensor);
43	int (post_streamoff)(struct smiapp_sensor sensor);	44	int (post_streamoff)(struct ccs_sensor sensor);
44	unsigned long (pll_flags)(struct smiapp_sensor sensor);	45	unsigned long (pll_flags)(struct ccs_sensor sensor);
45	int (init)(struct smiapp_sensor sensor);	46	int (init)(struct ccs_sensor sensor);
46	int (reg_access)(struct smiapp_sensor sensor, bool write, u32 *reg,	47	int (reg_access)(struct ccs_sensor sensor, bool write, u32 *reg,
47	u32 *val);	48	u32 *val);
48	unsigned long flags;	49	unsigned long flags;
49	};	50	};
50		51
51	#define SMIAPP_QUIRK_FLAG_8BIT_READ_ONLY (1 << 0)	52	#define CCS_QUIRK_FLAG_8BIT_READ_ONLY (1 << 0)
52		53
53	struct smiapp_reg_8 {	54	struct ccs_reg_8 {
54	u16 reg;	55	u16 reg;
55	u8 val;	56	u8 val;
56	};	57	};
57		58
58	void smiapp_replace_limit(struct smiapp_sensor *sensor,	59	#define CCS_MK_QUIRK_REG_8(_reg, _val) \
59	u32 limit, u32 val);
60
61	#define SMIAPP_MK_QUIRK_REG_8(_reg, _val) \
62	{ \	60	{ \
63	.reg = (u16)_reg, \	61	.reg = (u16)_reg, \
64	.val = _val, \	62	.val = _val, \
65	}	63	}
66		64
67	#define smiapp_call_quirk(sensor, _quirk, ...) \	65	#define ccs_call_quirk(sensor, _quirk, ...) \
68	((sensor)->minfo.quirk && \	66	((sensor)->minfo.quirk && \
69	(sensor)->minfo.quirk->_quirk ? \	67	(sensor)->minfo.quirk->_quirk ? \
70	(sensor)->minfo.quirk->_quirk(sensor, ##__VA_ARGS__) : 0)	68	(sensor)->minfo.quirk->_quirk(sensor, ##__VA_ARGS__) : 0)
71		69
72	#define smiapp_needs_quirk(sensor, _quirk) \	70	#define ccs_needs_quirk(sensor, _quirk) \
73	((sensor)->minfo.quirk ? \	71	((sensor)->minfo.quirk ? \
74	(sensor)->minfo.quirk->flags & _quirk : 0)	72	(sensor)->minfo.quirk->flags & _quirk : 0)
75		73
76	extern const struct smiapp_quirk smiapp_jt8ev1_quirk;	74	extern const struct ccs_quirk smiapp_jt8ev1_quirk;
77	extern const struct smiapp_quirk smiapp_imx125es_quirk;	75	extern const struct ccs_quirk smiapp_imx125es_quirk;
78	extern const struct smiapp_quirk smiapp_jt8ew9_quirk;	76	extern const struct ccs_quirk smiapp_jt8ew9_quirk;
79	extern const struct smiapp_quirk smiapp_tcm8500md_quirk;	77	extern const struct ccs_quirk smiapp_tcm8500md_quirk;
80		78
81	#endif /* __SMIAPP_QUIRK__ */	79	#endif /* __CCS_QUIRK__ */

drivers/media/i2c/ccs/ccs-reg-access.c+409−0

@@ -0,0 +1,409 @@
	1	// SPDX-License-Identifier: GPL-2.0-only
	2	/*
	3	* drivers/media/i2c/ccs/ccs-reg-access.c
	4	*
	5	* Generic driver for MIPI CCS/SMIA/SMIA++ compliant camera sensors
	6	*
	7	* Copyright (C) 2020 Intel Corporation
	8	* Copyright (C) 2011--2012 Nokia Corporation
	9	* Contact: Sakari Ailus <sakari.ailus@linux.intel.com>
	10	*/
	11
	12	#include <asm/unaligned.h>
	13
	14	#include <linux/delay.h>
	15	#include <linux/i2c.h>
	16
	17	#include "ccs.h"
	18	#include "ccs-limits.h"
	19
	20	static uint32_t float_to_u32_mul_1000000(struct i2c_client *client,
	21	uint32_t phloat)
	22	{
	23	int32_t exp;
	24	uint64_t man;
	25
	26	if (phloat >= 0x80000000) {
	27	dev_err(&client->dev, "this is a negative number\n");
	28	return 0;
	29	}
	30
	31	if (phloat == 0x7f800000)
	32	return ~0; /* Inf. */
	33
	34	if ((phloat & 0x7f800000) == 0x7f800000) {
	35	dev_err(&client->dev, "NaN or other special number\n");
	36	return 0;
	37	}
	38
	39	/* Valid cases begin here */
	40	if (phloat == 0)
	41	return 0; /* Valid zero */
	42
	43	if (phloat > 0x4f800000)
	44	return ~0; /* larger than 4294967295 */
	45
	46	/*
	47	* Unbias exponent (note how phloat is now guaranteed to
	48	* have 0 in the high bit)
	49	*/
	50	exp = ((int32_t)phloat >> 23) - 127;
	51
	52	/* Extract mantissa, add missing '1' bit and it's in MHz */
	53	man = ((phloat & 0x7fffff) \| 0x800000) * 1000000ULL;
	54
	55	if (exp < 0)
	56	man >>= -exp;
	57	else
	58	man <<= exp;
	59
	60	man >>= 23; /* Remove mantissa bias */
	61
	62	return man & 0xffffffff;
	63	}
	64
	65
	66	/*
	67	* Read a 8/16/32-bit i2c register. The value is returned in 'val'.
	68	* Returns zero if successful, or non-zero otherwise.
	69	*/
	70	static int ____ccs_read_addr(struct ccs_sensor *sensor, u16 reg, u16 len,
	71	u32 *val)
	72	{
	73	struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
	74	struct i2c_msg msg;
	75	unsigned char data_buf[sizeof(u32)] = { 0 };
	76	unsigned char offset_buf[sizeof(u16)];
	77	int r;
	78
	79	if (len > sizeof(data_buf))
	80	return -EINVAL;
	81
	82	msg.addr = client->addr;
	83	msg.flags = 0;
	84	msg.len = sizeof(offset_buf);
	85	msg.buf = offset_buf;
	86	put_unaligned_be16(reg, offset_buf);
	87
	88	r = i2c_transfer(client->adapter, &msg, 1);
	89	if (r != 1) {
	90	if (r >= 0)
	91	r = -EBUSY;
	92	goto err;
	93	}
	94
	95	msg.len = len;
	96	msg.flags = I2C_M_RD;
	97	msg.buf = &data_buf[sizeof(data_buf) - len];
	98
	99	r = i2c_transfer(client->adapter, &msg, 1);
	100	if (r != 1) {
	101	if (r >= 0)
	102	r = -EBUSY;
	103	goto err;
	104	}
	105
	106	*val = get_unaligned_be32(data_buf);
	107
	108	return 0;
	109
	110	err:
	111	dev_err(&client->dev, "read from offset 0x%x error %d\n", reg, r);
	112
	113	return r;
	114	}
	115
	116	/* Read a register using 8-bit access only. */
	117	static int ____ccs_read_addr_8only(struct ccs_sensor *sensor, u16 reg,
	118	u16 len, u32 *val)
	119	{
	120	unsigned int i;
	121	int rval;
	122
	123	*val = 0;
	124
	125	for (i = 0; i < len; i++) {
	126	u32 val8;
	127
	128	rval = ____ccs_read_addr(sensor, reg + i, 1, &val8);
	129	if (rval < 0)
	130	return rval;
	131	*val \|= val8 << ((len - i - 1) << 3);
	132	}
	133
	134	return 0;
	135	}
	136
	137	unsigned int ccs_reg_width(u32 reg)
	138	{
	139	if (reg & CCS_FL_16BIT)
	140	return sizeof(uint16_t);
	141	if (reg & CCS_FL_32BIT)
	142	return sizeof(uint32_t);
	143
	144	return sizeof(uint8_t);
	145	}
	146
	147	static u32 ireal32_to_u32_mul_1000000(struct i2c_client *client, u32 val)
	148	{
	149	if (val >> 10 > U32_MAX / 15625) {
	150	dev_warn(&client->dev, "value %u overflows!\n", val);
	151	return U32_MAX;
	152	}
	153
	154	return ((val >> 10) * 15625) +
	155	(val & GENMASK(9, 0)) * 15625 / 1024;
	156	}
	157
	158	u32 ccs_reg_conv(struct ccs_sensor *sensor, u32 reg, u32 val)
	159	{
	160	struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
	161
	162	if (reg & CCS_FL_FLOAT_IREAL) {
	163	if (CCS_LIM(sensor, CLOCK_CAPA_TYPE_CAPABILITY) &
	164	CCS_CLOCK_CAPA_TYPE_CAPABILITY_IREAL)
	165	val = ireal32_to_u32_mul_1000000(client, val);
	166	else
	167	val = float_to_u32_mul_1000000(client, val);
	168	} else if (reg & CCS_FL_IREAL) {
	169	val = ireal32_to_u32_mul_1000000(client, val);
	170	}
	171
	172	return val;
	173	}
	174
	175	/*
	176	* Read a 8/16/32-bit i2c register. The value is returned in 'val'.
	177	* Returns zero if successful, or non-zero otherwise.
	178	*/
	179	static int __ccs_read_addr(struct ccs_sensor sensor, u32 reg, u32 val,
	180	bool only8, bool conv)
	181	{
	182	unsigned int len = ccs_reg_width(reg);
	183	int rval;
	184
	185	if (!only8)
	186	rval = ____ccs_read_addr(sensor, CCS_REG_ADDR(reg), len, val);
	187	else
	188	rval = ____ccs_read_addr_8only(sensor, CCS_REG_ADDR(reg), len,
	189	val);
	190	if (rval < 0)
	191	return rval;
	192
	193	if (!conv)
	194	return 0;
	195
	196	val = ccs_reg_conv(sensor, reg, val);
	197
	198	return 0;
	199	}
	200
	201	static int __ccs_read_data(struct ccs_reg *regs, size_t num_regs,
	202	u32 reg, u32 *val)
	203	{
	204	unsigned int width = ccs_reg_width(reg);
	205	size_t i;
	206
	207	for (i = 0; i < num_regs; i++, regs++) {
	208	uint8_t *data;
	209
	210	if (regs->addr + regs->len < CCS_REG_ADDR(reg) + width)
	211	continue;
	212
	213	if (regs->addr > CCS_REG_ADDR(reg))
	214	break;
	215
	216	data = &regs->value[CCS_REG_ADDR(reg) - regs->addr];
	217
	218	switch (width) {
	219	case sizeof(uint8_t):
	220	val = data;
	221	break;
	222	case sizeof(uint16_t):
	223	*val = get_unaligned_be16(data);
	224	break;
	225	case sizeof(uint32_t):
	226	*val = get_unaligned_be32(data);
	227	break;
	228	default:
	229	WARN_ON(1);
	230	return -EINVAL;
	231	}
	232
	233	return 0;
	234	}
	235
	236	return -ENOENT;
	237	}
	238
	239	static int ccs_read_data(struct ccs_sensor sensor, u32 reg, u32 val)
	240	{
	241	if (!__ccs_read_data(sensor->sdata.sensor_read_only_regs,
	242	sensor->sdata.num_sensor_read_only_regs,
	243	reg, val))
	244	return 0;
	245
	246	return __ccs_read_data(sensor->mdata.module_read_only_regs,
	247	sensor->mdata.num_module_read_only_regs,
	248	reg, val);
	249	}
	250
	251	static int ccs_read_addr_raw(struct ccs_sensor sensor, u32 reg, u32 val,
	252	bool force8, bool quirk, bool conv, bool data)
	253	{
	254	int rval;
	255
	256	if (data) {
	257	rval = ccs_read_data(sensor, reg, val);
	258	if (!rval)
	259	return 0;
	260	}
	261
	262	if (quirk) {
	263	*val = 0;
	264	rval = ccs_call_quirk(sensor, reg_access, false, &reg, val);
	265	if (rval == -ENOIOCTLCMD)
	266	return 0;
	267	if (rval < 0)
	268	return rval;
	269
	270	if (force8)
	271	return __ccs_read_addr(sensor, reg, val, true, conv);
	272	}
	273
	274	return __ccs_read_addr(sensor, reg, val,
	275	ccs_needs_quirk(sensor,
	276	CCS_QUIRK_FLAG_8BIT_READ_ONLY),
	277	conv);
	278	}
	279
	280	int ccs_read_addr(struct ccs_sensor sensor, u32 reg, u32 val)
	281	{
	282	return ccs_read_addr_raw(sensor, reg, val, false, true, true, true);
	283	}
	284
	285	int ccs_read_addr_8only(struct ccs_sensor sensor, u32 reg, u32 val)
	286	{
	287	return ccs_read_addr_raw(sensor, reg, val, true, true, true, true);
	288	}
	289
	290	int ccs_read_addr_noconv(struct ccs_sensor sensor, u32 reg, u32 val)
	291	{
	292	return ccs_read_addr_raw(sensor, reg, val, false, true, false, true);
	293	}
	294
	295	static int ccs_write_retry(struct i2c_client client, struct i2c_msg msg)
	296	{
	297	unsigned int retries;
	298	int r;
	299
	300	for (retries = 0; retries < 10; retries++) {
	301	/*
	302	* Due to unknown reason sensor stops responding. This
	303	* loop is a temporaty solution until the root cause
	304	* is found.
	305	*/
	306	r = i2c_transfer(client->adapter, msg, 1);
	307	if (r != 1) {
	308	usleep_range(1000, 2000);
	309	continue;
	310	}
	311
	312	if (retries)
	313	dev_err(&client->dev,
	314	"sensor i2c stall encountered. retries: %d\n",
	315	retries);
	316	return 0;
	317	}
	318
	319	return r;
	320	}
	321
	322	int ccs_write_addr_no_quirk(struct ccs_sensor *sensor, u32 reg, u32 val)
	323	{
	324	struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
	325	struct i2c_msg msg;
	326	unsigned char data[6];
	327	unsigned int len = ccs_reg_width(reg);
	328	int r;
	329
	330	if (len > sizeof(data) - 2)
	331	return -EINVAL;
	332
	333	msg.addr = client->addr;
	334	msg.flags = 0; /* Write */
	335	msg.len = 2 + len;
	336	msg.buf = data;
	337
	338	put_unaligned_be16(CCS_REG_ADDR(reg), data);
	339	put_unaligned_be32(val << (8 * (sizeof(val) - len)), data + 2);
	340
	341	dev_dbg(&client->dev, "writing reg 0x%4.4x value 0x%.x (%u)\n",
	342	CCS_REG_ADDR(reg), ccs_reg_width(reg) << 1,
	343	ccs_reg_width(reg) << 1, val, val);
	344
	345	r = ccs_write_retry(client, &msg);
	346	if (r)
	347	dev_err(&client->dev,
	348	"wrote 0x%x to offset 0x%x error %d\n", val,
	349	CCS_REG_ADDR(reg), r);
	350
	351	return r;
	352	}
	353
	354	/*
	355	* Write to a 8/16-bit register.
	356	* Returns zero if successful, or non-zero otherwise.
	357	*/
	358	int ccs_write_addr(struct ccs_sensor *sensor, u32 reg, u32 val)
	359	{
	360	int rval;
	361
	362	rval = ccs_call_quirk(sensor, reg_access, true, &reg, &val);
	363	if (rval == -ENOIOCTLCMD)
	364	return 0;
	365	if (rval < 0)
	366	return rval;
	367
	368	return ccs_write_addr_no_quirk(sensor, reg, val);
	369	}
	370
	371	#define MAX_WRITE_LEN 32U
	372
	373	int ccs_write_data_regs(struct ccs_sensor sensor, struct ccs_reg regs,
	374	size_t num_regs)
	375	{
	376	struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
	377	unsigned char buf[2 + MAX_WRITE_LEN];
	378	struct i2c_msg msg = {
	379	.addr = client->addr,
	380	.buf = buf,
	381	};
	382	size_t i;
	383
	384	for (i = 0; i < num_regs; i++, regs++) {
	385	unsigned char *regdata = regs->value;
	386	unsigned int j;
	387
	388	for (j = 0; j < regs->len;
	389	j += msg.len - 2, regdata += msg.len - 2) {
	390	int rval;
	391
	392	msg.len = min(regs->len - j, MAX_WRITE_LEN);
	393
	394	put_unaligned_be16(regs->addr + j, buf);
	395	memcpy(buf + 2, regdata, msg.len);
	396	msg.len += 2;
	397
	398	rval = ccs_write_retry(client, &msg);
	399	if (rval) {
	400	dev_err(&client->dev,
	401	"error writing %u octets to address 0x%4.4x\n",
	402	msg.len, regs->addr + j);
	403	return rval;
	404	}
	405	}
	406	}
	407
	408	return 0;
	409	}

drivers/media/i2c/ccs/ccs-reg-access.h+42−0

@@ -0,0 +1,42 @@
	1	/* SPDX-License-Identifier: GPL-2.0-only */
	2	/*
	3	* include/media/ccs/ccs-reg-access.h
	4	*
	5	* Generic driver for MIPI CCS/SMIA/SMIA++ compliant camera sensors
	6	*
	7	* Copyright (C) 2020 Intel Corporation
	8	* Copyright (C) 2011--2012 Nokia Corporation
	9	* Contact: Sakari Ailus <sakari.ailus@linux.intel.com>
	10	*/
	11
	12	#ifndef SMIAPP_REGS_H
	13	#define SMIAPP_REGS_H
	14
	15	#include <linux/i2c.h>
	16	#include <linux/types.h>
	17

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@@ -244,7 +244,7 @@ Carrier Signal to Noise ratio (:ref:`DTV-STAT-CNR`) · 243 unmodified lines
244	Having it available after inner FEC is more common.	244	Having it available after inner FEC is more common.
245		245
246	Bit counts post-FEC (:ref:`DTV-STAT-POST-ERROR-BIT-COUNT` and :ref:`DTV-STAT-POST-TOTAL-BIT-COUNT`)	246	Bit counts post-FEC (:ref:`DTV-STAT-POST-ERROR-BIT-COUNT` and :ref:`DTV-STAT-POST-TOTAL-BIT-COUNT`)
247	- Those counters measure the number of bits and bit errors errors after	247	- Those counters measure the number of bits and bit errors after
248	the forward error correction (FEC) on the inner coding block	248	the forward error correction (FEC) on the inner coding block
249	(after Viterbi, LDPC or other inner code).	249	(after Viterbi, LDPC or other inner code).
250		250
@@ -253,7 +253,7 @@ Bit counts post-FEC (:ref:`DTV-STAT-POST-ERROR-BIT-COUNT` and :ref:`DTV-STAT-POS · 2 unmodified lines
253	see :c:type:`fe_status`).	253	see :c:type:`fe_status`).
254		254
255	Bit counts pre-FEC (:ref:`DTV-STAT-PRE-ERROR-BIT-COUNT` and :ref:`DTV-STAT-PRE-TOTAL-BIT-COUNT`)	255	Bit counts pre-FEC (:ref:`DTV-STAT-PRE-ERROR-BIT-COUNT` and :ref:`DTV-STAT-PRE-TOTAL-BIT-COUNT`)
256	- Those counters measure the number of bits and bit errors errors before	256	- Those counters measure the number of bits and bit errors before
257	the forward error correction (FEC) on the inner coding block	257	the forward error correction (FEC) on the inner coding block
258	(before Viterbi, LDPC or other inner code).	258	(before Viterbi, LDPC or other inner code).
259		259
@@ -263,7 +263,7 @@ Bit counts pre-FEC (:ref:`DTV-STAT-PRE-ERROR-BIT-COUNT` and :ref:`DTV-STAT-PRE-T · 3 unmodified lines
263	after ``FE_HAS_VITERBI``, see :c:type:`fe_status`).	263	after ``FE_HAS_VITERBI``, see :c:type:`fe_status`).
264		264
265	Block counts (:ref:`DTV-STAT-ERROR-BLOCK-COUNT` and :ref:`DTV-STAT-TOTAL-BLOCK-COUNT`)	265	Block counts (:ref:`DTV-STAT-ERROR-BLOCK-COUNT` and :ref:`DTV-STAT-TOTAL-BLOCK-COUNT`)
266	- Those counters measure the number of blocks and block errors errors after	266	- Those counters measure the number of blocks and block errors after
267	the forward error correction (FEC) on the inner coding block	267	the forward error correction (FEC) on the inner coding block
268	(before Viterbi, LDPC or other inner code).	268	(before Viterbi, LDPC or other inner code).
269		269