spi: Support for DTR ops Merge the SPIMEM DTR bits in spi-nor/next so that we can continue the development on top of them.
Unified · Split
| @@ -285,6 +285,12 @@ static bool atmel_qspi_supports_op(struct spi_mem *mem, · 284 unmodified lines | ||
| 285 | 285 | op->dummy.nbytes == 0) |
| 286 | 286 | return false; |
| 287 | 287 | |
| 288 | + /* DTR ops not supported. */ | |
| 289 | + if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr) | |
| 290 | + return false; | |
| 291 | + if (op->cmd.nbytes != 1) | |
| 292 | + return false; | |
| 293 | + | |
| 288 | 294 | return true; |
| 289 | 295 | } |
| 290 | 296 | |
| @@ -156,6 +156,12 @@ bool spi_mem_default_supports_op(struct spi_mem *mem, · 155 unmodified lines | ||
| 156 | 156 | op->data.dir == SPI_MEM_DATA_OUT)) |
| 157 | 157 | return false; |
| 158 | 158 | |
| 159 | + if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr) | |
| 160 | + return false; | |
| 161 | + | |
| 162 | + if (op->cmd.nbytes != 1) | |
| 163 | + return false; | |
| 164 | + | |
| 159 | 165 | return true; |
| 160 | 166 | } |
| 161 | 167 | EXPORT_SYMBOL_GPL(spi_mem_default_supports_op); |
| @@ -170,7 +176,7 @@ static bool spi_mem_buswidth_is_valid(u8 buswidth) · 8 unmodified lines | ||
| 170 | 176 | |
| 171 | 177 | static int spi_mem_check_op(const struct spi_mem_op *op) |
| 172 | 178 | { |
| 173 | − if (!op->cmd.buswidth) | |
| 179 | + if (!op->cmd.buswidth || !op->cmd.nbytes) | |
| 174 | 180 | return -EINVAL; |
| 175 | 181 | |
| 176 | 182 | if ((op->addr.nbytes && !op->addr.buswidth) || |
| @@ -306,8 +312,7 @@ int spi_mem_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) · 129 unmodified lines | ||
| 306 | 312 | return ret; |
| 307 | 313 | } |
| 308 | 314 | |
| 309 | − tmpbufsize = sizeof(op->cmd.opcode) + op->addr.nbytes + | |
| 310 | − op->dummy.nbytes; | |
| 315 | + tmpbufsize = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes; | |
| 311 | 316 | |
| 312 | 317 | /* |
| 313 | 318 | * Allocate a buffer to transmit the CMD, ADDR cycles with kmalloc() so |
| @@ -322,7 +327,7 @@ int spi_mem_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) · 8 unmodified lines | ||
| 322 | 327 | |
| 323 | 328 | tmpbuf[0] = op->cmd.opcode; |
| 324 | 329 | xfers[xferpos].tx_buf = tmpbuf; |
| 325 | − xfers[xferpos].len = sizeof(op->cmd.opcode); | |
| 330 | + xfers[xferpos].len = op->cmd.nbytes; | |
| 326 | 331 | xfers[xferpos].tx_nbits = op->cmd.buswidth; |
| 327 | 332 | spi_message_add_tail(&xfers[xferpos], &msg); |
| 328 | 333 | xferpos++; |
| @@ -424,8 +429,7 @@ int spi_mem_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) · 95 unmodified lines | ||
| 424 | 429 | return ctlr->mem_ops->adjust_op_size(mem, op); |
| 425 | 430 | |
| 426 | 431 | if (!ctlr->mem_ops || !ctlr->mem_ops->exec_op) { |
| 427 | − len = sizeof(op->cmd.opcode) + op->addr.nbytes + | |
| 428 | − op->dummy.nbytes; | |
| 432 | + len = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes; | |
| 429 | 433 | |
| 430 | 434 | if (len > spi_max_transfer_size(mem->spi)) |
| 431 | 435 | return -EINVAL; |
| @@ -195,7 +195,7 @@ static int mtk_nor_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) · 194 unmodified lines | ||
| 195 | 195 | } |
| 196 | 196 | } |
| 197 | 197 | |
| 198 | − len = MTK_NOR_PRG_MAX_SIZE - sizeof(op->cmd.opcode) - op->addr.nbytes - | |
| 198 | + len = MTK_NOR_PRG_MAX_SIZE - op->cmd.nbytes - op->addr.nbytes - | |
| 199 | 199 | op->dummy.nbytes; |
| 200 | 200 | if (op->data.nbytes > len) |
| 201 | 201 | op->data.nbytes = len; |
| @@ -211,6 +211,12 @@ static bool mtk_nor_supports_op(struct spi_mem *mem, · 9 unmodified lines | ||
| 211 | 211 | if (op->cmd.buswidth != 1) |
| 212 | 212 | return false; |
| 213 | 213 | |
| 214 | + /* DTR ops not supported. */ | |
| 215 | + if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr) | |
| 216 | + return false; | |
| 217 | + if (op->cmd.nbytes != 1) | |
| 218 | + return false; | |
| 219 | + | |
| 214 | 220 | if ((op->addr.nbytes == 3) || (op->addr.nbytes == 4)) { |
| 215 | 221 | if ((op->data.dir == SPI_MEM_DATA_IN) && mtk_nor_match_read(op)) |
| 216 | 222 | return true; |
| @@ -219,7 +225,7 @@ static bool mtk_nor_supports_op(struct spi_mem *mem, · 2 unmodified lines | ||
| 219 | 225 | (op->dummy.buswidth == 0) && |
| 220 | 226 | (op->data.buswidth == 1); |
| 221 | 227 | } |
| 222 | − len = sizeof(op->cmd.opcode) + op->addr.nbytes + op->dummy.nbytes; | |
| 228 | + len = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes; | |
| 223 | 229 | if ((len > MTK_NOR_PRG_MAX_SIZE) || |
| 224 | 230 | ((op->data.nbytes) && (len == MTK_NOR_PRG_MAX_SIZE))) |
| 225 | 231 | return false; |
| @@ -356,6 +356,7 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem, · 355 unmodified lines | ||
| 356 | 356 | int nio = 1, i, ret; |
| 357 | 357 | u32 ss_ctrl; |
| 358 | 358 | u8 addr[8]; |
| 359 | + u8 opcode = op->cmd.opcode; | |
| 359 | 360 | |
| 360 | 361 | ret = mxic_spi_set_freq(mxic, mem->spi->max_speed_hz); |
| 361 | 362 | if (ret) |
| @@ -393,7 +394,7 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem, · 31 unmodified lines | ||
| 393 | 394 | writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT, |
| 394 | 395 | mxic->regs + HC_CFG); |
| 395 | 396 | |
| 396 | − ret = mxic_spi_data_xfer(mxic, &op->cmd.opcode, NULL, 1); | |
| 397 | + ret = mxic_spi_data_xfer(mxic, &opcode, NULL, 1); | |
| 397 | 398 | if (ret) |
| 398 | 399 | goto out; |
| 399 | 400 | |
| @@ -527,20 +527,21 @@ static int zynq_qspi_exec_mem_op(struct spi_mem *mem, · 526 unmodified lines | ||
| 527 | 527 | struct zynq_qspi *xqspi = spi_controller_get_devdata(mem->spi->master); |
| 528 | 528 | int err = 0, i; |
| 529 | 529 | u8 *tmpbuf; |
| 530 | + u8 opcode = op->cmd.opcode; | |
| 530 | 531 | |
| 531 | 532 | dev_dbg(xqspi->dev, "cmd:%#x mode:%d.%d.%d.%d\n", |
| 532 | − op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth, | |
| 533 | + opcode, op->cmd.buswidth, op->addr.buswidth, | |
| 533 | 534 | op->dummy.buswidth, op->data.buswidth); |
| 534 | 535 | |
| 535 | 536 | zynq_qspi_chipselect(mem->spi, true); |
| 536 | 537 | zynq_qspi_config_op(xqspi, mem->spi); |
| 537 | 538 | |
| 538 | − if (op->cmd.opcode) { | |
| 539 | + if (op->cmd.nbytes) { | |
| 539 | 540 | reinit_completion(&xqspi->data_completion); |
| 540 | − xqspi->txbuf = (u8 *)&op->cmd.opcode; | |
| 541 | + xqspi->txbuf = &opcode; | |
| 541 | 542 | xqspi->rxbuf = NULL; |
| 542 | − xqspi->tx_bytes = sizeof(op->cmd.opcode); | |
| 543 | − xqspi->rx_bytes = sizeof(op->cmd.opcode); | |
| 543 | + xqspi->tx_bytes = op->cmd.nbytes; | |
| 544 | + xqspi->rx_bytes = op->cmd.nbytes; | |
| 544 | 545 | zynq_qspi_write_op(xqspi, ZYNQ_QSPI_FIFO_DEPTH, true); |
| 545 | 546 | zynq_qspi_write(xqspi, ZYNQ_QSPI_IEN_OFFSET, |
| 546 | 547 | ZYNQ_QSPI_IXR_RXTX_MASK); |
| @@ -17,6 +17,7 @@ · 16 unmodified lines | ||
| 17 | 17 | { \ |
| 18 | 18 | .buswidth = __buswidth, \ |
| 19 | 19 | .opcode = __opcode, \ |
| 20 | + .nbytes = 1, \ | |
| 20 | 21 | } |
| 21 | 22 | |
| 22 | 23 | #define SPI_MEM_OP_ADDR(__nbytes, __val, __buswidth) \ |
| @@ -69,11 +70,15 @@ enum spi_mem_data_dir { · 46 unmodified lines | ||
| 69 | 70 | |
| 70 | 71 | /** |
| 71 | 72 | * struct spi_mem_op - describes a SPI memory operation |
| 73 | + * @cmd.nbytes: number of opcode bytes (only 1 or 2 are valid). The opcode is | |
| 74 | + * sent MSB-first. | |
| 72 | 75 | * @cmd.buswidth: number of IO lines used to transmit the command |
| 73 | 76 | * @cmd.opcode: operation opcode |
| 77 | + * @cmd.dtr: whether the command opcode should be sent in DTR mode or not | |
| 74 | 78 | * @addr.nbytes: number of address bytes to send. Can be zero if the operation |
| 75 | 79 | * does not need to send an address |
| 76 | 80 | * @addr.buswidth: number of IO lines used to transmit the address cycles |
| 81 | + * @addr.dtr: whether the address should be sent in DTR mode or not | |
| 77 | 82 | * @addr.val: address value. This value is always sent MSB first on the bus. |
| 78 | 83 | * Note that only @addr.nbytes are taken into account in this |
| 79 | 84 | * address value, so users should make sure the value fits in the |
| @@ -81,7 +86,9 @@ enum spi_mem_data_dir { · 1 unmodified line | ||
| 81 | 86 | * @dummy.nbytes: number of dummy bytes to send after an opcode or address. Can |
| 82 | 87 | * be zero if the operation does not require dummy bytes |
| 83 | 88 | * @dummy.buswidth: number of IO lanes used to transmit the dummy bytes |
| 89 | + * @dummy.dtr: whether the dummy bytes should be sent in DTR mode or not | |
| 84 | 90 | * @data.buswidth: number of IO lanes used to send/receive the data |
| 91 | + * @data.dtr: whether the data should be sent in DTR mode or not | |
| 85 | 92 | * @data.dir: direction of the transfer |
| 86 | 93 | * @data.nbytes: number of data bytes to send/receive. Can be zero if the |
| 87 | 94 | * operation does not involve transferring data |
| @@ -90,23 +97,28 @@ enum spi_mem_data_dir { · 2 unmodified lines | ||
| 90 | 97 | */ |
| 91 | 98 | struct spi_mem_op { |
| 92 | 99 | struct { |
| 100 | + u8 nbytes; | |
| 93 | 101 | u8 buswidth; |
| 94 | − u8 opcode; | |
| 102 | + u8 dtr : 1; | |
| 103 | + u16 opcode; | |
| 95 | 104 | } cmd; |
| 96 | 105 | |
| 97 | 106 | struct { |
| 98 | 107 | u8 nbytes; |
| 99 | 108 | u8 buswidth; |
| 109 | + u8 dtr : 1; | |
| 100 | 110 | u64 val; |
| 101 | 111 | } addr; |
| 102 | 112 | |
| 103 | 113 | struct { |
| 104 | 114 | u8 nbytes; |
| 105 | 115 | u8 buswidth; |
| 116 | + u8 dtr : 1; | |
| 106 | 117 | } dummy; |
| 107 | 118 | |
| 108 | 119 | struct { |
| 109 | 120 | u8 buswidth; |
| 121 | + u8 dtr : 1; | |
| 110 | 122 | enum spi_mem_data_dir dir; |
| 111 | 123 | unsigned int nbytes; |
| 112 | 124 | union { |