| @@ -47,6 +47,9 @@ enum { · 46 unmodified lines |
| 47 | * @muxval: a number usually used to poke into some mux regiser to | 47 | * @muxval: a number usually used to poke into some mux regiser to |
| 48 | * mux in the signal to this channel | 48 | * mux in the signal to this channel |
| 49 | * @cctl_opt: default options for the channel control register | 49 | * @cctl_opt: default options for the channel control register |
| | 50 | * @device_fc: Flow Controller Settings for ccfg register. Only valid for slave |
| | 51 | * channels. Fill with 'true' if peripheral should be flow controller. Direction |
| | 52 | * will be selected at Runtime. |
| 50 | * @addr: source/target address in physical memory for this DMA channel, | 53 | * @addr: source/target address in physical memory for this DMA channel, |
| 51 | * can be the address of a FIFO register for burst requests for example. | 54 | * can be the address of a FIFO register for burst requests for example. |
| 52 | * This can be left undefined if the PrimeCell API is used for configuring | 55 | * This can be left undefined if the PrimeCell API is used for configuring |
| @@ -65,6 +68,7 @@ struct pl08x_channel_data { · 12 unmodified lines |
| 65 | int max_signal; | 68 | int max_signal; |
| 66 | u32 muxval; | 69 | u32 muxval; |
| 67 | u32 cctl; | 70 | u32 cctl; |
| | 71 | bool device_fc; |
| 68 | dma_addr_t addr; | 72 | dma_addr_t addr; |
| 69 | bool circular_buffer; | 73 | bool circular_buffer; |
| 70 | bool single; | 74 | bool single; |
| @@ -77,13 +81,11 @@ struct pl08x_channel_data { · 6 unmodified lines |
| 77 | * @addr: current address | 81 | * @addr: current address |
| 78 | * @maxwidth: the maximum width of a transfer on this bus | 82 | * @maxwidth: the maximum width of a transfer on this bus |
| 79 | * @buswidth: the width of this bus in bytes: 1, 2 or 4 | 83 | * @buswidth: the width of this bus in bytes: 1, 2 or 4 |
| 80 | * @fill_bytes: bytes required to fill to the next bus memory boundary | | |
| 81 | */ | 84 | */ |
| 82 | struct pl08x_bus_data { | 85 | struct pl08x_bus_data { |
| 83 | dma_addr_t addr; | 86 | dma_addr_t addr; |
| 84 | u8 maxwidth; | 87 | u8 maxwidth; |
| 85 | u8 buswidth; | 88 | u8 buswidth; |
| 86 | size_t fill_bytes; | | |
| 87 | }; | 89 | }; |
| 88 | | 90 | |
| 89 | /** | 91 | /** |
| @@ -103,18 +105,36 @@ struct pl08x_phy_chan { · 13 unmodified lines |
| 103 | struct pl08x_dma_chan *serving; | 105 | struct pl08x_dma_chan *serving; |
| 104 | }; | 106 | }; |
| 105 | | 107 | |
| | 108 | /** |
| | 109 | * struct pl08x_sg - structure containing data per sg |
| | 110 | * @src_addr: src address of sg |
| | 111 | * @dst_addr: dst address of sg |
| | 112 | * @len: transfer len in bytes |
| | 113 | * @node: node for txd's dsg_list |
| | 114 | */ |
| | 115 | struct pl08x_sg { |
| | 116 | dma_addr_t src_addr; |
| | 117 | dma_addr_t dst_addr; |
| | 118 | size_t len; |
| | 119 | struct list_head node; |
| | 120 | }; |
| | 121 | |
| 106 | /** | 122 | /** |
| 107 | * struct pl08x_txd - wrapper for struct dma_async_tx_descriptor | 123 | * struct pl08x_txd - wrapper for struct dma_async_tx_descriptor |
| | 124 | * @tx: async tx descriptor |
| | 125 | * @node: node for txd list for channels |
| | 126 | * @dsg_list: list of children sg's |
| | 127 | * @direction: direction of transfer |
| 108 | * @llis_bus: DMA memory address (physical) start for the LLIs | 128 | * @llis_bus: DMA memory address (physical) start for the LLIs |
| 109 | * @llis_va: virtual memory address start for the LLIs | 129 | * @llis_va: virtual memory address start for the LLIs |
| | 130 | * @cctl: control reg values for current txd |
| | 131 | * @ccfg: config reg values for current txd |
| 110 | */ | 132 | */ |
| 111 | struct pl08x_txd { | 133 | struct pl08x_txd { |
| 112 | struct dma_async_tx_descriptor tx; | 134 | struct dma_async_tx_descriptor tx; |
| 113 | struct list_head node; | 135 | struct list_head node; |
| | 136 | struct list_head dsg_list; |
| 114 | enum dma_data_direction direction; | 137 | enum dma_data_direction direction; |
| 115 | dma_addr_t src_addr; | | |
| 116 | dma_addr_t dst_addr; | | |
| 117 | size_t len; | | |
| 118 | dma_addr_t llis_bus; | 138 | dma_addr_t llis_bus; |
| 119 | struct pl08x_lli *llis_va; | 139 | struct pl08x_lli *llis_va; |
| 120 | /* Default cctl value for LLIs */ | 140 | /* Default cctl value for LLIs */ |