Bring changes from drm-misc-next that got merged in drm-next back to drm-xe so they can be used for additional features.
Unified · Split
| @@ -2161,6 +2161,19 @@ N: Mike Kravetz · 2160 unmodified lines | ||
| 2161 | 2161 | E: mike.kravetz@oracle.com |
| 2162 | 2162 | D: Maintenance and development of the hugetlb subsystem |
| 2163 | 2163 | |
| 2164 | +N: Seth Jennings | |
| 2165 | +E: sjenning@redhat.com | |
| 2166 | +D: Creation and maintenance of zswap | |
| 2167 | + | |
| 2168 | +N: Dan Streetman | |
| 2169 | +E: ddstreet@ieee.org | |
| 2170 | +D: Maintenance and development of zswap | |
| 2171 | +D: Creation and maintenance of the zpool API | |
| 2172 | + | |
| 2173 | +N: Vitaly Wool | |
| 2174 | +E: vitaly.wool@konsulko.com | |
| 2175 | +D: Maintenance and development of zswap | |
| 2176 | + | |
| 2164 | 2177 | N: Andreas S. Krebs |
| 2165 | 2178 | E: akrebs@altavista.net |
| 2166 | 2179 | D: CYPRESS CY82C693 chipset IDE, Digital's PC-Alpha 164SX boards |
| @@ -1,4 +1,4 @@ | ||
| 1 | −What: /sys/class/<iface>/queues/rx-<queue>/rps_cpus | |
| 1 | +What: /sys/class/net/<iface>/queues/rx-<queue>/rps_cpus | |
| 2 | 2 | Date: March 2010 |
| 3 | 3 | KernelVersion: 2.6.35 |
| 4 | 4 | Contact: netdev@vger.kernel.org |
| @@ -8,7 +8,7 @@ Description: · 3 unmodified lines | ||
| 8 | 8 | network device queue. Possible values depend on the number |
| 9 | 9 | of available CPU(s) in the system. |
| 10 | 10 | |
| 11 | −What: /sys/class/<iface>/queues/rx-<queue>/rps_flow_cnt | |
| 11 | +What: /sys/class/net/<iface>/queues/rx-<queue>/rps_flow_cnt | |
| 12 | 12 | Date: April 2010 |
| 13 | 13 | KernelVersion: 2.6.35 |
| 14 | 14 | Contact: netdev@vger.kernel.org |
| @@ -16,7 +16,7 @@ Description: · 1 unmodified line | ||
| 16 | 16 | Number of Receive Packet Steering flows being currently |
| 17 | 17 | processed by this particular network device receive queue. |
| 18 | 18 | |
| 19 | −What: /sys/class/<iface>/queues/tx-<queue>/tx_timeout | |
| 19 | +What: /sys/class/net/<iface>/queues/tx-<queue>/tx_timeout | |
| 20 | 20 | Date: November 2011 |
| 21 | 21 | KernelVersion: 3.3 |
| 22 | 22 | Contact: netdev@vger.kernel.org |
| @@ -24,7 +24,7 @@ Description: · 1 unmodified line | ||
| 24 | 24 | Indicates the number of transmit timeout events seen by this |
| 25 | 25 | network interface transmit queue. |
| 26 | 26 | |
| 27 | −What: /sys/class/<iface>/queues/tx-<queue>/tx_maxrate | |
| 27 | +What: /sys/class/net/<iface>/queues/tx-<queue>/tx_maxrate | |
| 28 | 28 | Date: March 2015 |
| 29 | 29 | KernelVersion: 4.1 |
| 30 | 30 | Contact: netdev@vger.kernel.org |
| @@ -32,7 +32,7 @@ Description: · 1 unmodified line | ||
| 32 | 32 | A Mbps max-rate set for the queue, a value of zero means disabled, |
| 33 | 33 | default is disabled. |
| 34 | 34 | |
| 35 | −What: /sys/class/<iface>/queues/tx-<queue>/xps_cpus | |
| 35 | +What: /sys/class/net/<iface>/queues/tx-<queue>/xps_cpus | |
| 36 | 36 | Date: November 2010 |
| 37 | 37 | KernelVersion: 2.6.38 |
| 38 | 38 | Contact: netdev@vger.kernel.org |
| @@ -42,7 +42,7 @@ Description: · 3 unmodified lines | ||
| 42 | 42 | network device transmit queue. Possible values depend on the |
| 43 | 43 | number of available CPU(s) in the system. |
| 44 | 44 | |
| 45 | −What: /sys/class/<iface>/queues/tx-<queue>/xps_rxqs | |
| 45 | +What: /sys/class/net/<iface>/queues/tx-<queue>/xps_rxqs | |
| 46 | 46 | Date: June 2018 |
| 47 | 47 | KernelVersion: 4.18.0 |
| 48 | 48 | Contact: netdev@vger.kernel.org |
| @@ -53,7 +53,7 @@ Description: · 4 unmodified lines | ||
| 53 | 53 | number of available receive queue(s) in the network device. |
| 54 | 54 | Default is disabled. |
| 55 | 55 | |
| 56 | −What: /sys/class/<iface>/queues/tx-<queue>/byte_queue_limits/hold_time | |
| 56 | +What: /sys/class/net/<iface>/queues/tx-<queue>/byte_queue_limits/hold_time | |
| 57 | 57 | Date: November 2011 |
| 58 | 58 | KernelVersion: 3.3 |
| 59 | 59 | Contact: netdev@vger.kernel.org |
| @@ -62,7 +62,7 @@ Description: · 2 unmodified lines | ||
| 62 | 62 | of this particular network device transmit queue. |
| 63 | 63 | Default value is 1000. |
| 64 | 64 | |
| 65 | −What: /sys/class/<iface>/queues/tx-<queue>/byte_queue_limits/inflight | |
| 65 | +What: /sys/class/net/<iface>/queues/tx-<queue>/byte_queue_limits/inflight | |
| 66 | 66 | Date: November 2011 |
| 67 | 67 | KernelVersion: 3.3 |
| 68 | 68 | Contact: netdev@vger.kernel.org |
| @@ -70,7 +70,7 @@ Description: · 1 unmodified line | ||
| 70 | 70 | Indicates the number of bytes (objects) in flight on this |
| 71 | 71 | network device transmit queue. |
| 72 | 72 | |
| 73 | −What: /sys/class/<iface>/queues/tx-<queue>/byte_queue_limits/limit | |
| 73 | +What: /sys/class/net/<iface>/queues/tx-<queue>/byte_queue_limits/limit | |
| 74 | 74 | Date: November 2011 |
| 75 | 75 | KernelVersion: 3.3 |
| 76 | 76 | Contact: netdev@vger.kernel.org |
| @@ -79,7 +79,7 @@ Description: · 2 unmodified lines | ||
| 79 | 79 | on this network device transmit queue. This value is clamped |
| 80 | 80 | to be within the bounds defined by limit_max and limit_min. |
| 81 | 81 | |
| 82 | −What: /sys/class/<iface>/queues/tx-<queue>/byte_queue_limits/limit_max | |
| 82 | +What: /sys/class/net/<iface>/queues/tx-<queue>/byte_queue_limits/limit_max | |
| 83 | 83 | Date: November 2011 |
| 84 | 84 | KernelVersion: 3.3 |
| 85 | 85 | Contact: netdev@vger.kernel.org |
| @@ -88,7 +88,7 @@ Description: · 2 unmodified lines | ||
| 88 | 88 | queued on this network device transmit queue. See |
| 89 | 89 | include/linux/dynamic_queue_limits.h for the default value. |
| 90 | 90 | |
| 91 | −What: /sys/class/<iface>/queues/tx-<queue>/byte_queue_limits/limit_min | |
| 91 | +What: /sys/class/net/<iface>/queues/tx-<queue>/byte_queue_limits/limit_min | |
| 92 | 92 | Date: November 2011 |
| 93 | 93 | KernelVersion: 3.3 |
| 94 | 94 | Contact: netdev@vger.kernel.org |
| @@ -10,6 +10,7 @@ What: /sys/devices/platform/silicom-platform/power_cycle · 9 unmodified lines | ||
| 10 | 10 | Date: November 2023 |
| 11 | 11 | KernelVersion: 6.7 |
| 12 | 12 | Contact: Henry Shi <henrys@silicom-usa.com> |
| 13 | +Description: | |
| 13 | 14 | This file allow user to power cycle the platform. |
| 14 | 15 | Default value is 0; when set to 1, it powers down |
| 15 | 16 | the platform, waits 5 seconds, then powers on the |
| @@ -101,8 +101,8 @@ External References · 100 unmodified lines | ||
| 101 | 101 | email threads |
| 102 | 102 | ------------- |
| 103 | 103 | |
| 104 | −* `Initial discussion on the New subsystem for acceleration devices <https://lkml.org/lkml/2022/7/31/83>`_ - Oded Gabbay (2022) | |
| 105 | −* `patch-set to add the new subsystem <https://lkml.org/lkml/2022/10/22/544>`_ - Oded Gabbay (2022) | |
| 104 | +* `Initial discussion on the New subsystem for acceleration devices <https://lore.kernel.org/lkml/CAFCwf11=9qpNAepL7NL+YAV_QO=Wv6pnWPhKHKAepK3fNn+2Dg@mail.gmail.com/>`_ - Oded Gabbay (2022) | |
| 105 | +* `patch-set to add the new subsystem <https://lore.kernel.org/lkml/20221022214622.18042-1-ogabbay@kernel.org/>`_ - Oded Gabbay (2022) | |
| 106 | 106 | |
| 107 | 107 | Conference talks |
| 108 | 108 | ---------------- |
| @@ -218,8 +218,3 @@ bytes respectively. Such letter suffixes can also be entirely omitted: · 217 unmodified lines | ||
| 218 | 218 | |
| 219 | 219 | .. include:: kernel-parameters.txt |
| 220 | 220 | :literal: |
| 221 | − | |
| 222 | −Todo | |
| 223 | −---- | |
| 224 | − | |
| 225 | − Add more DRM drivers. | |
| @@ -243,13 +243,9 @@ To reduce its OS jitter, do any of the following: · 242 unmodified lines | ||
| 243 | 243 | 3. Do any of the following needed to avoid jitter that your |
| 244 | 244 | application cannot tolerate: |
| 245 | 245 | |
| 246 | − a. Build your kernel with CONFIG_SLUB=y rather than | |
| 247 | − CONFIG_SLAB=y, thus avoiding the slab allocator's periodic | |
| 248 | − use of each CPU's workqueues to run its cache_reap() | |
| 249 | − function. | |
| 250 | − b. Avoid using oprofile, thus avoiding OS jitter from | |
| 246 | + a. Avoid using oprofile, thus avoiding OS jitter from | |
| 251 | 247 | wq_sync_buffer(). |
| 252 | − c. Limit your CPU frequency so that a CPU-frequency | |
| 248 | + b. Limit your CPU frequency so that a CPU-frequency | |
| 253 | 249 | governor is not required, possibly enlisting the aid of |
| 254 | 250 | special heatsinks or other cooling technologies. If done |
| 255 | 251 | correctly, and if you CPU architecture permits, you should |
| @@ -259,7 +255,7 @@ To reduce its OS jitter, do any of the following: · 3 unmodified lines | ||
| 259 | 255 | |
| 260 | 256 | WARNING: Please check your CPU specifications to |
| 261 | 257 | make sure that this is safe on your particular system. |
| 262 | − d. As of v3.18, Christoph Lameter's on-demand vmstat workers | |
| 258 | + c. As of v3.18, Christoph Lameter's on-demand vmstat workers | |
| 263 | 259 | commit prevents OS jitter due to vmstat_update() on |
| 264 | 260 | CONFIG_SMP=y systems. Before v3.18, is not possible |
| 265 | 261 | to entirely get rid of the OS jitter, but you can |
| @@ -274,7 +270,7 @@ To reduce its OS jitter, do any of the following: · 8 unmodified lines | ||
| 274 | 270 | (based on an earlier one from Gilad Ben-Yossef) that |
| 275 | 271 | reduces or even eliminates vmstat overhead for some |
| 276 | 272 | workloads at https://lore.kernel.org/r/00000140e9dfd6bd-40db3d4f-c1be-434f-8132-7820f81bb586-000000@email.amazonses.com. |
| 277 | − e. If running on high-end powerpc servers, build with | |
| 273 | + d. If running on high-end powerpc servers, build with | |
| 278 | 274 | CONFIG_PPC_RTAS_DAEMON=n. This prevents the RTAS |
| 279 | 275 | daemon from running on each CPU every second or so. |
| 280 | 276 | (This will require editing Kconfig files and will defeat |
| @@ -282,12 +278,12 @@ To reduce its OS jitter, do any of the following: · 1 unmodified line | ||
| 282 | 278 | due to the rtas_event_scan() function. |
| 283 | 279 | WARNING: Please check your CPU specifications to |
| 284 | 280 | make sure that this is safe on your particular system. |
| 285 | − f. If running on Cell Processor, build your kernel with | |
| 281 | + e. If running on Cell Processor, build your kernel with | |
| 286 | 282 | CBE_CPUFREQ_SPU_GOVERNOR=n to avoid OS jitter from |
| 287 | 283 | spu_gov_work(). |
| 288 | 284 | WARNING: Please check your CPU specifications to |
| 289 | 285 | make sure that this is safe on your particular system. |
| 290 | − g. If running on PowerMAC, build your kernel with | |
| 286 | + f. If running on PowerMAC, build your kernel with | |
| 291 | 287 | CONFIG_PMAC_RACKMETER=n to disable the CPU-meter, |
| 292 | 288 | avoiding OS jitter from rackmeter_do_timer(). |
| 293 | 289 | |
| @@ -671,8 +671,23 @@ Testing Static Functions · 670 unmodified lines | ||
| 671 | 671 | ------------------------ |
| 672 | 672 | |
| 673 | 673 | If we do not want to expose functions or variables for testing, one option is to |
| 674 | −conditionally ``#include`` the test file at the end of your .c file. For | |
| 675 | −example: | |
| 674 | +conditionally export the used symbol. For example: | |
| 675 | + | |
| 676 | +.. code-block:: c | |
| 677 | + | |
| 678 | + /* In my_file.c */ | |
| 679 | + | |
| 680 | + VISIBLE_IF_KUNIT int do_interesting_thing(); | |
| 681 | + EXPORT_SYMBOL_IF_KUNIT(do_interesting_thing); | |
| 682 | + | |
| 683 | + /* In my_file.h */ | |
| 684 | + | |
| 685 | + #if IS_ENABLED(CONFIG_KUNIT) | |
| 686 | + int do_interesting_thing(void); | |
| 687 | + #endif | |
| 688 | + | |
| 689 | +Alternatively, you could conditionally ``#include`` the test file at the end of | |
| 690 | +your .c file. For example: | |
| 676 | 691 | |
| 677 | 692 | .. code-block:: c |
| 678 | 693 | |
| @@ -0,0 +1,102 @@ | ||
| 1 | +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | |
| 2 | +%YAML 1.2 | |
| 3 | +--- | |
| 4 | +$id: http://devicetree.org/schemas/display/bridge/fsl,imx8mp-hdmi-tx.yaml# | |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# | |
| 6 | + | |
| 7 | +title: Freescale i.MX8MP DWC HDMI TX Encoder | |
| 8 | + | |
| 9 | +maintainers: | |
| 10 | + - Lucas Stach <l.stach@pengutronix.de> | |
| 11 | + | |
| 12 | +description: | |
| 13 | + The i.MX8MP HDMI transmitter is a Synopsys DesignWare | |
| 14 | + HDMI 2.0a TX controller IP. | |
| 15 | + | |
| 16 | +allOf: | |
| 17 | + - $ref: /schemas/display/bridge/synopsys,dw-hdmi.yaml# | |
| 18 | + | |
| 19 | +properties: | |
| 20 | + compatible: | |
| 21 | + enum: | |
| 22 | + - fsl,imx8mp-hdmi-tx | |
| 23 | + | |
| 24 | + reg-io-width: | |
| 25 | + const: 1 | |
| 26 | + | |
| 27 | + clocks: | |
| 28 | + maxItems: 4 | |
| 29 | + | |
| 30 | + clock-names: | |
| 31 | + items: | |
| 32 | + - const: iahb | |
| 33 | + - const: isfr | |
| 34 | + - const: cec | |
| 35 | + - const: pix | |
| 36 | + | |
| 37 | + power-domains: | |
| 38 | + maxItems: 1 | |
| 39 | + | |
| 40 | + ports: | |
| 41 | + $ref: /schemas/graph.yaml#/properties/ports | |
| 42 | + | |
| 43 | + properties: | |
| 44 | + port@0: | |
| 45 | + $ref: /schemas/graph.yaml#/properties/port | |
| 46 | + description: Parallel RGB input port | |
| 47 | + | |
| 48 | + port@1: | |
| 49 | + $ref: /schemas/graph.yaml#/properties/port | |
| 50 | + description: HDMI output port | |
| 51 | + | |
| 52 | + required: | |
| 53 | + - port@0 | |
| 54 | + - port@1 | |
| 55 | + | |
| 56 | +required: | |
| 57 | + - compatible | |
| 58 | + - reg | |
| 59 | + - clocks | |
| 60 | + - clock-names | |
| 61 | + - interrupts | |
| 62 | + - power-domains | |
| 63 | + - ports | |
| 64 | + | |
| 65 | +unevaluatedProperties: false | |
| 66 | + | |
| 67 | +examples: | |
| 68 | + - | | |
| 69 | + #include <dt-bindings/clock/imx8mp-clock.h> | |
| 70 | + #include <dt-bindings/interrupt-controller/irq.h> | |
| 71 | + #include <dt-bindings/power/imx8mp-power.h> | |
| 72 | + | |
| 73 | + hdmi@32fd8000 { | |
| 74 | + compatible = "fsl,imx8mp-hdmi-tx"; | |
| 75 | + reg = <0x32fd8000 0x7eff>; | |
| 76 | + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; | |
| 77 | + clocks = <&clk IMX8MP_CLK_HDMI_APB>, | |
| 78 | + <&clk IMX8MP_CLK_HDMI_REF_266M>, | |
| 79 | + <&clk IMX8MP_CLK_32K>, | |
| 80 | + <&hdmi_tx_phy>; | |
| 81 | + clock-names = "iahb", "isfr", "cec", "pix"; | |
| 82 | + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX>; | |
| 83 | + reg-io-width = <1>; | |
| 84 | + ports { | |
| 85 | + #address-cells = <1>; | |
| 86 | + #size-cells = <0>; | |
| 87 | + port@0 { | |
| 88 | + reg = <0>; | |
| 89 | + | |
| 90 | + hdmi_tx_from_pvi: endpoint { | |
| 91 | + remote-endpoint = <&pvi_to_hdmi_tx>; | |
| 92 | + }; | |
| 93 | + }; | |
| 94 | + | |
| 95 | + port@1 { | |
| 96 | + reg = <1>; | |
| 97 | + hdmi_tx_out: endpoint { | |
| 98 | + remote-endpoint = <&hdmi0_con>; | |
| 99 | + }; | |
| 100 | + }; | |
| 101 | + }; | |
| 102 | + }; | |
| @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# · 6 unmodified lines | ||
| 7 | 7 | title: SN65DSI86 DSI to eDP bridge chip |
| 8 | 8 | |
| 9 | 9 | maintainers: |
| 10 | − - Sandeep Panda <spanda@codeaurora.org> | |
| 10 | + - Douglas Anderson <dianders@chromium.org> | |
| 11 | 11 | |
| 12 | 12 | description: | |
| 13 | 13 | The Texas Instruments SN65DSI86 bridge takes MIPI DSI in and outputs eDP. |
| @@ -0,0 +1,84 @@ | ||
| 1 | +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | |
| 2 | +%YAML 1.2 | |
| 3 | +--- | |
| 4 | +$id: http://devicetree.org/schemas/display/imx/fsl,imx8mp-hdmi-pvi.yaml# | |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# | |
| 6 | + | |
| 7 | +title: Freescale i.MX8MP HDMI Parallel Video Interface | |
| 8 | + | |
| 9 | +maintainers: | |
| 10 | + - Lucas Stach <l.stach@pengutronix.de> | |
| 11 | + | |
| 12 | +description: | |
| 13 | + The HDMI parallel video interface is a timing and sync generator block in the | |
| 14 | + i.MX8MP SoC, that sits between the video source and the HDMI TX controller. | |
| 15 | + | |
| 16 | +properties: | |
| 17 | + compatible: | |
| 18 | + const: fsl,imx8mp-hdmi-pvi | |
| 19 | + | |
| 20 | + reg: | |
| 21 | + maxItems: 1 | |
| 22 | + | |
| 23 | + interrupts: | |
| 24 | + maxItems: 1 | |
| 25 | + | |
| 26 | + power-domains: | |
| 27 | + maxItems: 1 | |
| 28 | + | |
| 29 | + ports: | |
| 30 | + $ref: /schemas/graph.yaml#/properties/ports | |
| 31 | + | |
| 32 | + properties: | |
| 33 | + port@0: | |
| 34 | + $ref: /schemas/graph.yaml#/properties/port | |
| 35 | + description: Input from the LCDIF controller. | |
| 36 | + | |
| 37 | + port@1: | |
| 38 | + $ref: /schemas/graph.yaml#/properties/port | |
| 39 | + description: Output to the HDMI TX controller. | |
| 40 | + | |
| 41 | + required: | |
| 42 | + - port@0 | |
| 43 | + - port@1 | |
| 44 | + | |
| 45 | +required: | |
| 46 | + - compatible | |
| 47 | + - reg | |
| 48 | + - interrupts | |
| 49 | + - power-domains | |
| 50 | + - ports | |
| 51 | + | |
| 52 | +additionalProperties: false | |
| 53 | + | |
| 54 | +examples: | |
| 55 | + - | | |
| 56 | + #include <dt-bindings/interrupt-controller/irq.h> | |
| 57 | + #include <dt-bindings/power/imx8mp-power.h> | |
| 58 | + | |
| 59 | + display-bridge@32fc4000 { | |
| 60 | + compatible = "fsl,imx8mp-hdmi-pvi"; | |
| 61 | + reg = <0x32fc4000 0x44>; | |
| 62 | + interrupt-parent = <&irqsteer_hdmi>; | |
| 63 | + interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; | |
| 64 | + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_PVI>; | |
| 65 | + | |
| 66 | + ports { | |
| 67 | + #address-cells = <1>; | |
| 68 | + #size-cells = <0>; | |
| 69 | + | |
| 70 | + port@0 { | |
| 71 | + reg = <0>; | |
| 72 | + pvi_from_lcdif3: endpoint { | |
| 73 | + remote-endpoint = <&lcdif3_to_pvi>; | |
| 74 | + }; | |
| 75 | + }; | |
| 76 | + | |
| 77 | + port@1 { | |
| 78 | + reg = <1>; | |
| 79 | + pvi_to_hdmi_tx: endpoint { | |
| 80 | + remote-endpoint = <&hdmi_tx_from_pvi>; | |
| 81 | + }; | |
| 82 | + }; | |
| 83 | + }; | |
| 84 | + }; | |
| @@ -0,0 +1,58 @@ | ||
| 1 | +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | |
| 2 | +%YAML 1.2 | |
| 3 | +--- | |
| 4 | +$id: http://devicetree.org/schemas/display/panel/boe,th101mb31ig002-28a.yaml# | |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# | |
| 6 | + | |
| 7 | +title: BOE TH101MB31IG002-28A WXGA DSI Display Panel | |
| 8 | + | |
| 9 | +maintainers: | |
| 10 | + - Manuel Traut <manut@mecka.net> | |
| 11 | + | |
| 12 | +allOf: | |
| 13 | + - $ref: panel-common.yaml# | |
| 14 | + | |
| 15 | +properties: | |
| 16 | + compatible: | |
| 17 | + enum: | |
| 18 | + # BOE TH101MB31IG002-28A 10.1" WXGA TFT LCD panel | |
| 19 | + - boe,th101mb31ig002-28a | |
| 20 | + | |
| 21 | + reg: true | |
| 22 | + backlight: true | |
| 23 | + enable-gpios: true | |
| 24 | + power-supply: true | |
| 25 | + port: true | |
| 26 | + rotation: true | |
| 27 | + | |
| 28 | +required: | |
| 29 | + - compatible | |
| 30 | + - reg | |
| 31 | + - enable-gpios | |
| 32 | + - power-supply | |
| 33 | + | |
| 34 | +additionalProperties: false | |
| 35 | + | |
| 36 | +examples: | |
| 37 | + - | | |
| 38 | + #include <dt-bindings/gpio/gpio.h> | |
| 39 | + | |
| 40 | + dsi { | |
| 41 | + #address-cells = <1>; | |
| 42 | + #size-cells = <0>; | |
| 43 | + panel@0 { | |
| 44 | + compatible = "boe,th101mb31ig002-28a"; | |
| 45 | + reg = <0>; | |
| 46 | + backlight = <&backlight_lcd0>; | |
| 47 | + enable-gpios = <&gpio 45 GPIO_ACTIVE_HIGH>; | |
| 48 | + rotation = <90>; | |
| 49 | + power-supply = <&vcc_3v3>; | |
| 50 | + port { | |
| 51 | + panel_in_dsi: endpoint { | |
| 52 | + remote-endpoint = <&dsi_out_con>; | |
| 53 | + }; | |
| 54 | + }; | |
| 55 | + }; | |
| 56 | + }; | |
| 57 | + | |
| 58 | +... | |
| @@ -15,7 +15,9 @@ allOf: · 14 unmodified lines | ||
| 15 | 15 | properties: |
| 16 | 16 | compatible: |
| 17 | 17 | items: |
| 18 | − - const: hydis,hva40wv1 | |
| 18 | + - enum: | |
| 19 | + - frida,frd400b25025 | |
| 20 | + - hydis,hva40wv1 | |
| 19 | 21 | - const: novatek,nt35510 |
| 20 | 22 | description: This indicates the panel manufacturer of the panel |
| 21 | 23 | that is in turn using the NT35510 panel driver. The compatible |
| @@ -0,0 +1,66 @@ | ||
| 1 | +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause | |
| 2 | +%YAML 1.2 | |
| 3 | +--- | |
| 4 | +$id: http://devicetree.org/schemas/display/panel/novatek,nt36672e.yaml# | |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# | |
| 6 | + | |
| 7 | +title: Novatek NT36672E LCD DSI Panel | |
| 8 | + | |
| 9 | +maintainers: | |
| 10 | + - Ritesh Kumar <quic_riteshk@quicinc.com> | |
| 11 | + | |
| 12 | +allOf: | |
| 13 | + - $ref: panel-common.yaml# | |
| 14 | + | |
| 15 | +properties: | |
| 16 | + compatible: | |
| 17 | + const: novatek,nt36672e | |
| 18 | + | |
| 19 | + reg: | |
| 20 | + maxItems: 1 | |
| 21 | + description: DSI virtual channel | |
| 22 | + | |
| 23 | + vddi-supply: true | |
| 24 | + avdd-supply: true | |
| 25 | + avee-supply: true | |
| 26 | + port: true | |
| 27 | + reset-gpios: true | |
| 28 | + backlight: true | |
| 29 | + | |
| 30 | +required: | |
| 31 | + - compatible | |
| 32 | + - reg | |
| 33 | + - vddi-supply | |
| 34 | + - avdd-supply | |
| 35 | + - avee-supply | |
| 36 | + - reset-gpios | |
| 37 | + - port | |
| 38 | + | |
| 39 | +additionalProperties: false | |
| 40 | + | |
| 41 | +examples: | |
| 42 | + - | | |
| 43 | + #include <dt-bindings/gpio/gpio.h> | |
| 44 | + dsi { | |
| 45 | + #address-cells = <1>; | |
| 46 | + #size-cells = <0>; | |
| 47 | + panel@0 { | |
| 48 | + compatible = "novatek,nt36672e"; | |
| 49 | + reg = <0>; | |
| 50 | + | |
| 51 | + reset-gpios = <&tlmm 44 GPIO_ACTIVE_HIGH>; | |
| 52 | + | |
| 53 | + vddi-supply = <&vreg_l8c_1p8>; | |
| 54 | + avdd-supply = <&disp_avdd>; | |
| 55 | + avee-supply = <&disp_avee>; | |
| 56 | + | |
| 57 | + backlight = <&pwm_backlight>; | |
| 58 | + | |
| 59 | + port { | |
| 60 | + panel0_in: endpoint { | |
| 61 | + remote-endpoint = <&dsi0_out>; | |
| 62 | + }; | |
| 63 | + }; | |
| 64 | + }; | |
| 65 | + }; | |
| 66 | +... | |
| @@ -42,6 +42,8 @@ properties: · 41 unmodified lines | ||
| 42 | 42 | - auo,b101ew05 |
| 43 | 43 | # Chunghwa Picture Tubes Ltd. 7" WXGA (800x1280) TFT LCD LVDS panel |
| 44 | 44 | - chunghwa,claa070wp03xg |
| 45 | + # EDT ETML0700Z9NDHA 7.0" WSVGA (1024x600) color TFT LCD LVDS panel | |
| 46 | + - edt,etml0700z9ndha | |
| 45 | 47 | # HannStar Display Corp. HSD101PWW2 10.1" WXGA (1280x800) LVDS panel |
| 46 | 48 | - hannstar,hsd101pww2 |
| 47 | 49 | # Hydis Technologies 7" WXGA (800x1280) TFT LCD LVDS panel |
| @@ -141,6 +141,8 @@ properties: · 140 unmodified lines | ||
| 141 | 141 | - edt,etm0700g0edh6 |
| 142 | 142 | # Emerging Display Technology Corp. LVDS WSVGA TFT Display with capacitive touch |
| 143 | 143 | - edt,etml0700y5dha |
| 144 | + # Emerging Display Technology Corp. 10.1" LVDS WXGA TFT Display with capacitive touch | |
| 145 | + - edt,etml1010g3dra | |
| 144 | 146 | # Emerging Display Technology Corp. 5.7" VGA TFT LCD panel with |
| 145 | 147 | # capacitive touch |
| 146 | 148 | - edt,etmv570g2dhu |
| @@ -22,6 +22,8 @@ properties: · 21 unmodified lines | ||
| 22 | 22 | enum: |
| 23 | 23 | # Anberic RG353V-V2 5.0" 640x480 TFT LCD panel |
| 24 | 24 | - anbernic,rg353v-panel-v2 |
| 25 | + # Powkiddy RGB10MAX3 5.0" 720x1280 TFT LCD panel | |
| 26 | + - powkiddy,rgb10max3-panel | |
| 25 | 27 | # Powkiddy RGB30 3.0" 720x720 TFT LCD panel |
| 26 | 28 | - powkiddy,rgb30-panel |
| 27 | 29 | # Rocktech JH057N00900 5.5" 720x1440 TFT LCD panel |
| @@ -43,6 +45,7 @@ properties: · 15 unmodified lines | ||
| 43 | 45 | reset-gpios: true |
| 44 | 46 | |
| 45 | 47 | backlight: true |
| 48 | + rotation: true | |
| 46 | 49 | |
| 47 | 50 | required: |
| 48 | 51 | - compatible |
| @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# · 6 unmodified lines | ||
| 7 | 7 | title: Visionox model RM69299 Panels |
| 8 | 8 | |
| 9 | 9 | maintainers: |
| 10 | − - Harigovindan P <harigovi@codeaurora.org> | |
| 10 | + - Abhinav Kumar <quic_abhinavk@quicinc.com> | |
| 11 | + - Jessica Zhang <quic_jesszhan@quicinc.com> | |
| 11 | 12 | |
| 12 | 13 | description: | |
| 13 | 14 | This binding is for display panels using a Visionox RM692999 panel. |
| @@ -94,11 +94,14 @@ properties: · 93 unmodified lines | ||
| 94 | 94 | - const: default |
| 95 | 95 | - const: unwedge |
| 96 | 96 | |
| 97 | + power-domains: | |
| 98 | + maxItems: 1 | |
| 99 | + | |
| 97 | 100 | ports: |
| 98 | 101 | $ref: /schemas/graph.yaml#/properties/ports |
| 99 | 102 | |
| 100 | − patternProperties: | |
| 101 | − "^port(@0)?$": | |
| 103 | + properties: | |
| 104 | + port@0: | |
| 102 | 105 | $ref: /schemas/graph.yaml#/properties/port |
| 103 | 106 | description: Input of the DWC HDMI TX |
| 104 | 107 | properties: |
| @@ -108,11 +111,14 @@ properties: · 3 unmodified lines | ||
| 108 | 111 | description: Connection to the VOPB |
| 109 | 112 | endpoint@1: |
| 110 | 113 | description: Connection to the VOPL |
| 111 | − properties: | |
| 112 | 114 | port@1: |
| 113 | 115 | $ref: /schemas/graph.yaml#/properties/port |
| 114 | 116 | description: Output of the DWC HDMI TX |
| 115 | 117 | |
| 118 | + required: | |
| 119 | + - port@0 | |
| 120 | + - port@1 | |
| 121 | + | |
| 116 | 122 | rockchip,grf: |
| 117 | 123 | $ref: /schemas/types.yaml#/definitions/phandle |
| 118 | 124 | description: |
| @@ -135,19 +141,25 @@ examples: · 16 unmodified lines | ||
| 135 | 141 | #include <dt-bindings/clock/rk3288-cru.h> |
| 136 | 142 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 137 | 143 | #include <dt-bindings/interrupt-controller/irq.h> |
| 144 | + #include <dt-bindings/power/rk3288-power.h> | |
| 138 | 145 | |
| 139 | 146 | hdmi: hdmi@ff980000 { |
| 140 | 147 | compatible = "rockchip,rk3288-dw-hdmi"; |
| 141 | 148 | reg = <0xff980000 0x20000>; |
| 142 | 149 | reg-io-width = <4>; |
| 143 | − ddc-i2c-bus = <&i2c5>; | |
| 144 | − rockchip,grf = <&grf>; | |
| 145 | 150 | interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; |
| 146 | 151 | clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>; |
| 147 | 152 | clock-names = "iahb", "isfr"; |
| 153 | + ddc-i2c-bus = <&i2c5>; | |
| 154 | + power-domains = <&power RK3288_PD_VIO>; | |
| 155 | + rockchip,grf = <&grf>; | |
| 148 | 156 | |
| 149 | 157 | ports { |
| 150 | − port { | |
| 158 | + #address-cells = <1>; | |
| 159 | + #size-cells = <0>; | |
| 160 | + | |
| 161 | + port@0 { | |
| 162 | + reg = <0>; | |
| 151 | 163 | #address-cells = <1>; |
| 152 | 164 | #size-cells = <0>; |
| 153 | 165 | |
| @@ -155,11 +167,20 @@ examples: · 1 unmodified line | ||
| 155 | 167 | reg = <0>; |
| 156 | 168 | remote-endpoint = <&vopb_out_hdmi>; |
| 157 | 169 | }; |
| 170 | + | |
| 158 | 171 | hdmi_in_vopl: endpoint@1 { |
| 159 | 172 | reg = <1>; |
| 160 | 173 | remote-endpoint = <&vopl_out_hdmi>; |
| 161 | 174 | }; |
| 162 | 175 | }; |
| 176 | + | |
| 177 | + port@1 { | |
| 178 | + reg = <1>; | |
| 179 | + | |
| 180 | + hdmi_out_con: endpoint { | |
| 181 | + remote-endpoint = <&hdmi_con_in>; | |
| 182 | + }; | |
| 183 | + }; | |
| 163 | 184 | }; |
| 164 | 185 | }; |
| 165 | 186 | |
| @@ -85,7 +85,7 @@ allOf: · 84 unmodified lines | ||
| 85 | 85 | clocks: |
| 86 | 86 | minItems: 6 |
| 87 | 87 | maxItems: 6 |
| 88 | − regs: | |
| 88 | + reg: | |
| 89 | 89 | minItems: 2 |
| 90 | 90 | maxItems: 2 |
| 91 | 91 | |
| @@ -99,7 +99,7 @@ allOf: · 7 unmodified lines | ||
| 99 | 99 | clocks: |
| 100 | 100 | minItems: 4 |
| 101 | 101 | maxItems: 4 |
| 102 | − regs: | |
| 102 | + reg: | |
| 103 | 103 | minItems: 2 |
| 104 | 104 | maxItems: 2 |
| 105 | 105 | |
| @@ -116,7 +116,7 @@ allOf: · 10 unmodified lines | ||
| 116 | 116 | clocks: |
| 117 | 117 | minItems: 3 |
| 118 | 118 | maxItems: 3 |
| 119 | − regs: | |
| 119 | + reg: | |
| 120 | 120 | minItems: 1 |
| 121 | 121 | maxItems: 1 |
| 122 | 122 | |
| @@ -131,9 +131,9 @@ allOf: · 130 unmodified lines | ||
| 131 | 131 | const: sinowealth,sh1106 |
| 132 | 132 | then: |
| 133 | 133 | properties: |
| 134 | − width: | |
| 134 | + solomon,width: | |
| 135 | 135 | default: 132 |
| 136 | − height: | |
| 136 | + solomon,height: | |
| 137 | 137 | default: 64 |
| 138 | 138 | solomon,dclk-div: |
| 139 | 139 | default: 1 |
| @@ -149,9 +149,9 @@ allOf: · 9 unmodified lines | ||
| 149 | 149 | - solomon,ssd1305 |
| 150 | 150 | then: |
| 151 | 151 | properties: |
| 152 | − width: | |
| 152 | + solomon,width: | |
| 153 | 153 | default: 132 |
| 154 | − height: | |
| 154 | + solomon,height: | |
| 155 | 155 | default: 64 |
| 156 | 156 | solomon,dclk-div: |
| 157 | 157 | default: 1 |
| @@ -167,9 +167,9 @@ allOf: · 9 unmodified lines | ||
| 167 | 167 | - solomon,ssd1306 |
| 168 | 168 | then: |
| 169 | 169 | properties: |
| 170 | − width: | |
| 170 | + solomon,width: | |
| 171 | 171 | default: 128 |
| 172 | − height: | |
| 172 | + solomon,height: | |
| 173 | 173 | default: 64 |
| 174 | 174 | solomon,dclk-div: |
| 175 | 175 | default: 1 |
| @@ -185,9 +185,9 @@ allOf: · 9 unmodified lines | ||
| 185 | 185 | - solomon,ssd1307 |
| 186 | 186 | then: |
| 187 | 187 | properties: |
| 188 | − width: | |
| 188 | + solomon,width: | |
| 189 | 189 | default: 128 |
| 190 | − height: | |
| 190 | + solomon,height: | |
| 191 | 191 | default: 39 |
| 192 | 192 | solomon,dclk-div: |
| 193 | 193 | default: 2 |
| @@ -205,9 +205,9 @@ allOf: · 11 unmodified lines | ||
| 205 | 205 | - solomon,ssd1309 |
| 206 | 206 | then: |
| 207 | 207 | properties: |
| 208 | − width: | |
| 208 | + solomon,width: | |
| 209 | 209 | default: 128 |
| 210 | − height: | |
| 210 | + solomon,height: | |
| 211 | 211 | default: 64 |
| 212 | 212 | solomon,dclk-div: |
| 213 | 213 | default: 1 |
| @@ -30,9 +30,9 @@ allOf: · 29 unmodified lines | ||
| 30 | 30 | const: solomon,ssd1322 |
| 31 | 31 | then: |
| 32 | 32 | properties: |
| 33 | − width: | |
| 33 | + solomon,width: | |
| 34 | 34 | default: 480 |
| 35 | − height: | |
| 35 | + solomon,height: | |
| 36 | 36 | default: 128 |
| 37 | 37 | |
| 38 | 38 | - if: |
| @@ -42,9 +42,9 @@ allOf: · 3 unmodified lines | ||
| 42 | 42 | const: solomon,ssd1325 |
| 43 | 43 | then: |
| 44 | 44 | properties: |
| 45 | − width: | |
| 45 | + solomon,width: | |
| 46 | 46 | default: 128 |
| 47 | − height: | |
| 47 | + solomon,height: | |
| 48 | 48 | default: 80 |
| 49 | 49 | |
| 50 | 50 | - if: |
| @@ -54,9 +54,9 @@ allOf: · 3 unmodified lines | ||
| 54 | 54 | const: solomon,ssd1327 |
| 55 | 55 | then: |
| 56 | 56 | properties: |
| 57 | − width: | |
| 57 | + solomon,width: | |
| 58 | 58 | default: 128 |
| 59 | − height: | |
| 59 | + solomon,height: | |
| 60 | 60 | default: 128 |
| 61 | 61 | |
| 62 | 62 | unevaluatedProperties: false |
| @@ -0,0 +1,45 @@ | ||
| 1 | +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | |
| 2 | +%YAML 1.2 | |
| 3 | +--- | |
| 4 | +$id: http://devicetree.org/schemas/display/solomon,ssd133x.yaml# | |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# | |
| 6 | + | |
| 7 | +title: Solomon SSD133x OLED Display Controllers | |
| 8 | + | |
| 9 | +maintainers: | |
| 10 | + - Javier Martinez Canillas <javierm@redhat.com> | |
| 11 | + | |
| 12 | +allOf: | |
| 13 | + - $ref: solomon,ssd-common.yaml# | |
| 14 | + | |
| 15 | +properties: | |
| 16 | + compatible: | |
| 17 | + enum: | |
| 18 | + - solomon,ssd1331 | |
| 19 | + | |
| 20 | + solomon,width: | |
| 21 | + default: 96 | |
| 22 | + | |
| 23 | + solomon,height: | |
| 24 | + default: 64 | |
| 25 | + | |
| 26 | +required: | |
| 27 | + - compatible | |
| 28 | + - reg | |
| 29 | + | |
| 30 | +unevaluatedProperties: false | |
| 31 | + | |
| 32 | +examples: | |
| 33 | + - | | |
| 34 | + spi { | |
| 35 | + #address-cells = <1>; | |
| 36 | + #size-cells = <0>; | |
| 37 | + | |
| 38 | + oled@0 { | |
| 39 | + compatible = "solomon,ssd1331"; | |
| 40 | + reg = <0x0>; | |
| 41 | + reset-gpios = <&gpio2 7>; | |
| 42 | + dc-gpios = <&gpio2 8>; | |
| 43 | + spi-max-frequency = <10000000>; | |
| 44 | + }; | |
| 45 | + }; | |
| @@ -17,7 +17,7 @@ properties: · 16 unmodified lines | ||
| 17 | 17 | compatible: |
| 18 | 18 | items: |
| 19 | 19 | - enum: |
| 20 | − - ti,k3-j721s2-wave521c | |
| 20 | + - ti,j721s2-wave521c | |
| 21 | 21 | - const: cnm,wave521c |
| 22 | 22 | |
| 23 | 23 | reg: |
| @@ -53,7 +53,7 @@ additionalProperties: false · 29 unmodified lines | ||
| 53 | 53 | examples: |
| 54 | 54 | - | |
| 55 | 55 | vpu: video-codec@12345678 { |
| 56 | − compatible = "ti,k3-j721s2-wave521c", "cnm,wave521c"; | |
| 56 | + compatible = "ti,j721s2-wave521c", "cnm,wave521c"; | |
| 57 | 57 | reg = <0x12345678 0x1000>; |
| 58 | 58 | clocks = <&clks 42>; |
| 59 | 59 | interrupts = <42>; |
| @@ -22,6 +22,7 @@ properties: · 21 unmodified lines | ||
| 22 | 22 | - const: allwinner,sun6i-a31-spdif |
| 23 | 23 | - const: allwinner,sun8i-h3-spdif |
| 24 | 24 | - const: allwinner,sun50i-h6-spdif |
| 25 | + - const: allwinner,sun50i-h616-spdif | |
| 25 | 26 | - items: |
| 26 | 27 | - const: allwinner,sun8i-a83t-spdif |
| 27 | 28 | - const: allwinner,sun8i-h3-spdif |
| @@ -62,6 +63,8 @@ allOf: · 34 unmodified lines | ||
| 62 | 63 | enum: |
| 63 | 64 | - allwinner,sun6i-a31-spdif |
| 64 | 65 | - allwinner,sun8i-h3-spdif |
| 66 | + - allwinner,sun50i-h6-spdif | |
| 67 | + - allwinner,sun50i-h616-spdif | |
| 65 | 68 | |
| 66 | 69 | then: |
| 67 | 70 | required: |
| @@ -73,7 +76,7 @@ allOf: · 5 unmodified lines | ||
| 73 | 76 | contains: |
| 74 | 77 | enum: |
| 75 | 78 | - allwinner,sun8i-h3-spdif |
| 76 | − - allwinner,sun50i-h6-spdif | |
| 79 | + - allwinner,sun50i-h616-spdif | |
| 77 | 80 | |
| 78 | 81 | then: |
| 79 | 82 | properties: |
| @@ -145,7 +145,9 @@ filesystem, an overlay filesystem needs to record in the upper filesystem · 144 unmodified lines | ||
| 145 | 145 | that files have been removed. This is done using whiteouts and opaque |
| 146 | 146 | directories (non-directories are always opaque). |
| 147 | 147 | |
| 148 | −A whiteout is created as a character device with 0/0 device number. | |
| 148 | +A whiteout is created as a character device with 0/0 device number or | |
| 149 | +as a zero-size regular file with the xattr "trusted.overlay.whiteout". | |
| 150 | + | |
| 149 | 151 | When a whiteout is found in the upper level of a merged directory, any |
| 150 | 152 | matching name in the lower level is ignored, and the whiteout itself |
| 151 | 153 | is also hidden. |
| @@ -154,6 +156,13 @@ A directory is made opaque by setting the xattr "trusted.overlay.opaque" · 2 unmodified lines | ||
| 154 | 156 | to "y". Where the upper filesystem contains an opaque directory, any |
| 155 | 157 | directory in the lower filesystem with the same name is ignored. |
| 156 | 158 | |
| 159 | +An opaque directory should not conntain any whiteouts, because they do not | |
| 160 | +serve any purpose. A merge directory containing regular files with the xattr | |
| 161 | +"trusted.overlay.whiteout", should be additionally marked by setting the xattr | |
| 162 | +"trusted.overlay.opaque" to "x" on the merge directory itself. | |
| 163 | +This is needed to avoid the overhead of checking the "trusted.overlay.whiteout" | |
| 164 | +on all entries during readdir in the common case. | |
| 165 | + | |
| 157 | 166 | readdir |
| 158 | 167 | ------- |
| 159 | 168 | |
| @@ -534,8 +543,9 @@ A lower dir with a regular whiteout will always be handled by the overlayfs · 374 unmodified lines | ||
| 534 | 543 | mount, so to support storing an effective whiteout file in an overlayfs mount an |
| 535 | 544 | alternative form of whiteout is supported. This form is a regular, zero-size |
| 536 | 545 | file with the "overlay.whiteout" xattr set, inside a directory with the |
| 537 | −"overlay.whiteouts" xattr set. Such whiteouts are never created by overlayfs, | |
| 538 | −but can be used by userspace tools (like containers) that generate lower layers. | |
| 546 | +"overlay.opaque" xattr set to "x" (see `whiteouts and opaque directories`_). | |
| 547 | +These alternative whiteouts are never created by overlayfs, but can be used by | |
| 548 | +userspace tools (like containers) that generate lower layers. | |
| 539 | 549 | These alternative whiteouts can be escaped using the standard xattr escape |
| 540 | 550 | mechanism in order to properly nest to any depth. |
| 541 | 551 | |
| @@ -16,6 +16,7 @@ Radeon (RX|TM) (PRO|WX) Vega /MI25 /V320 /V340L /8200 /9100 /SSG MxGPU, VEGA10, · 15 unmodified lines | ||
| 16 | 16 | AMD Radeon (Pro) VII /MI50 /MI60, VEGA20, DCE 12, 9.4.0, VCE 4.1.0 / UVD 7.2.0, 4.2.0 |
| 17 | 17 | MI100, ARCTURUS, *, 9.4.1, VCN 2.5.0, 4.2.2 |
| 18 | 18 | MI200, ALDEBARAN, *, 9.4.2, VCN 2.6.0, 4.4.0 |
| 19 | +MI300, AQUA_VANGARAM, *, 9.4.3, VCN 4.0.3, 4.4.2 | |
| 19 | 20 | AMD Radeon (RX|Pro) 5600(M|XT) /5700 (M|XT|XTB) /W5700, NAVI10, DCN 2.0.0, 10.1.10, VCN 2.0.0, 5.0.0 |
| 20 | 21 | AMD Radeon (Pro) 5300 /5500XTB/5500(XT|M) /W5500M /W5500, NAVI14, DCN 2.0.0, 10.1.1, VCN 2.0.2, 5.0.2 |
| 21 | 22 | AMD Radeon RX 6800(XT) /6900(XT) /W6800, SIENNA_CICHLID, DCN 3.0.0, 10.3.0, VCN 3.0.0, 5.2.0 |
| @@ -23,4 +24,5 @@ AMD Radeon RX 6700 XT / 6800M / 6700M, NAVY_FLOUNDER, DCN 3.0.0, 10.3.2, VCN 3.0 · 1 unmodified line | ||
| 23 | 24 | AMD Radeon RX 6600(XT) /6600M /W6600 /W6600M, DIMGREY_CAVEFISH, DCN 3.0.2, 10.3.4, VCN 3.0.16, 5.2.4 |
| 24 | 25 | AMD Radeon RX 6500M /6300M /W6500M /W6300M, BEIGE_GOBY, DCN 3.0.3, 10.3.5, VCN 3.0.33, 5.2.5 |
| 25 | 26 | AMD Radeon RX 7900 XT /XTX, , DCN 3.2.0, 11.0.0, VCN 4.0.0, 6.0.0 |
| 27 | +AMD Radeon RX 7800 XT, , DCN 3.2.0, 11.0.3, VCN 4.0.0, 6.0.3 | |
| 26 | 28 | AMD Radeon RX 7600M (XT) /7700S /7600S, , DCN 3.2.1, 11.0.2, VCN 4.0.4, 6.0.2 |
| @@ -0,0 +1,78 @@ | ||
| 1 | +========== | |
| 2 | +DCN Blocks | |
| 3 | +========== | |
| 4 | + | |
| 5 | +In this section, you will find some extra details about some of the DCN blocks | |
| 6 | +and the code documentation when it is automatically generated. | |
| 7 | + | |
| 8 | +DCHUBBUB | |
| 9 | +-------- | |
| 10 | + | |
| 11 | +.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | |
| 12 | + :doc: overview | |
| 13 | + | |
| 14 | +.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | |
| 15 | + :export: | |
| 16 | + | |
| 17 | +.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | |
| 18 | + :internal: | |
| 19 | + | |
| 20 | +HUBP | |
| 21 | +---- | |
| 22 | + | |
| 23 | +.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | |
| 24 | + :doc: overview | |
| 25 | + | |
| 26 | +.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | |
| 27 | + :export: | |
| 28 | + | |
| 29 | +.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | |
| 30 | + :internal: | |
| 31 | + | |
| 32 | +DPP | |
| 33 | +--- | |
| 34 | + | |
| 35 | +.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | |
| 36 | + :doc: overview | |
| 37 | + | |
| 38 | +.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | |
| 39 | + :export: | |
| 40 | + | |
| 41 | +.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | |
| 42 | + :internal: | |
| 43 | + | |
| 44 | +MPC | |
| 45 | +--- | |
| 46 | + | |
| 47 | +.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | |
| 48 | + :doc: overview | |
| 49 | + | |
| 50 | +.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | |
| 51 | + :export: | |
| 52 | + | |
| 53 | +.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | |
| 54 | + :internal: | |
| 55 | + | |
| 56 | +OPP | |
| 57 | +--- | |
| 58 | + | |
| 59 | +.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | |
| 60 | + :doc: overview | |
| 61 | + | |
| 62 | +.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | |
| 63 | + :export: | |
| 64 | + | |
| 65 | +.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | |
| 66 | + :internal: | |
| 67 | + | |
| 68 | +DIO | |
| 69 | +--- | |
| 70 | + | |
| 71 | +.. kernel-doc:: drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h | |
| 72 | + :doc: overview | |
| 73 | + | |
| 74 | +.. kernel-doc:: drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h | |
| 75 | + :export: | |
| 76 | + | |
| 77 | +.. kernel-doc:: drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h | |
| 78 | + :internal: | |
| @@ -0,0 +1,168 @@ | ||
| 1 | +.. _display_todos: | |
| 2 | + | |
| 3 | +============================== | |
| 4 | +AMDGPU - Display Contributions | |
| 5 | +============================== | |
| 6 | + | |
| 7 | +First of all, if you are here, you probably want to give some technical | |
| 8 | +contribution to the display code, and for that, we say thank you :) | |
| 9 | + | |
| 10 | +This page summarizes some of the issues you can help with; keep in mind that | |
| 11 | +this is a static page, and it is always a good idea to try to reach developers | |
| 12 | +in the amdgfx or some of the maintainers. Finally, this page follows the DRM | |
| 13 | +way of creating a TODO list; for more information, check | |
| 14 | +'Documentation/gpu/todo.rst'. | |
| 15 | + | |
| 16 | +Gitlab issues | |
| 17 | +============= | |
| 18 | + | |
| 19 | +Users can report issues associated with AMD GPUs at: | |
| 20 | + | |
| 21 | +- https://gitlab.freedesktop.org/drm/amd | |
| 22 | + | |
| 23 | +Usually, we try to add a proper label to all new tickets to make it easy to | |
| 24 | +filter issues. If you can reproduce any problem, you could help by adding more | |
| 25 | +information or fixing the issue. | |
| 26 | + | |
| 27 | +Level: diverse | |
| 28 | + | |
| 29 | +IGT | |
| 30 | +=== | |
| 31 | + | |
| 32 | +`IGT`_ provides many integration tests that can be run on your GPU. We always | |
| 33 | +want to pass a large set of tests to increase the test coverage in our CI. If | |
| 34 | +you wish to contribute to the display code but are unsure where a good place | |
| 35 | +is, we recommend you run all IGT tests and try to fix any failure you see in | |
| 36 | +your hardware. Keep in mind that this failure can be an IGT problem or a kernel | |
| 37 | +issue; it is necessary to analyze case-by-case. | |
| 38 | + | |
| 39 | +Level: diverse | |
| 40 | + | |
| 41 | +.. _IGT: https://gitlab.freedesktop.org/drm/igt-gpu-tools | |
| 42 | + | |
| 43 | +Compilation | |
| 44 | +=========== | |
| 45 | + | |
| 46 | +Fix compilation warnings | |
| 47 | +------------------------ | |
| 48 | + | |
| 49 | +Enable the W1 or W2 warning level in the kernel compilation and try to fix the | |
| 50 | +issues on the display side. | |
| 51 | + | |
| 52 | +Level: Starter | |
| 53 | + | |
| 54 | +Fix compilation issues when using um architecture | |
| 55 | +------------------------------------------------- | |
| 56 | + | |
| 57 | +Linux has a User-mode Linux (UML) feature, and the kernel can be compiled to | |
| 58 | +the **um** architecture. Compiling for **um** can bring multiple advantages | |
| 59 | +from the test perspective. We currently have some compilation issues in this | |
| 60 | +area that we need to fix. | |
| 61 | + | |
| 62 | +Level: Intermediate | |
| 63 | + | |
| 64 | +Code Refactor | |
| 65 | +============= | |
| 66 | + | |
| 67 | +Add prefix to DC functions to improve the debug with ftrace | |
| 68 | +----------------------------------------------------------- | |
| 69 | + | |
| 70 | +The Ftrace debug feature (check 'Documentation/trace/ftrace.rst') is a | |
| 71 | +fantastic way to check the code path when developers try to make sense of a | |
| 72 | +bug. Ftrace provides a filter mechanism that can be useful when the developer | |
| 73 | +has some hunch of which part of the code can cause the issue; for this reason, | |
| 74 | +if a set of functions has a proper prefix, it becomes easy to create a good | |
| 75 | +filter. Additionally, prefixes can improve stack trace readability. | |
| 76 | + | |
| 77 | +The DC code does not follow some prefix rules, which makes the Ftrace filter | |
| 78 | +more complicated and reduces the readability of the stack trace. If you want | |
| 79 | +something simple to start contributing to the display, you can make patches for | |
| 80 | +adding prefixes to DC functions. To create those prefixes, use part of the file | |
| 81 | +name as a prefix for all functions in the target file. Check the | |
| 82 | +'amdgpu_dm_crtc.c` and `amdgpu_dm_plane.c` for some references. However, we | |
| 83 | +strongly advise not to send huge patches changing these prefixes; otherwise, it | |
| 84 | +will be hard to review and test, which can generate second thoughts from | |
| 85 | +maintainers. Try small steps; in case of double, you can ask before you put in | |
| 86 | +effort. We recommend first looking at folders like dceXYZ, dcnXYZ, basics, | |
| 87 | +bios, core, clk_mgr, hwss, resource, and irq. | |
| 88 | + | |
| 89 | +Level: Starter | |
| 90 | + | |
| 91 | +Reduce code duplication | |
| 92 | +----------------------- | |
| 93 | + | |
| 94 | +AMD has an extensive portfolio with various dGPUs and APUs that amdgpu | |
| 95 | +supports. To maintain the new hardware release cadence, DCE/DCN was designed in | |
| 96 | +a modular design, making the bring-up for new hardware fast. Over the years, | |
| 97 | +amdgpu accumulated some technical debt in the code duplication area. For this | |
| 98 | +task, it would be a good idea to find a tool that can discover code duplication | |
| 99 | +(including patterns) and use it as guidance to reduce duplications. | |
| 100 | + | |
| 101 | +Level: Intermediate | |
| 102 | + | |
| 103 | +Make atomic_commit_[check|tail] more readable | |
| 104 | +--------------------------------------------- | |
| 105 | + | |
| 106 | +The functions responsible for atomic commit and tail are intricate and | |
| 107 | +extensive. In particular `amdgpu_dm_atomic_commit_tail` is a long function and | |
| 108 | +could benefit from being split into smaller helpers. Improvements in this area | |
| 109 | +are more than welcome, but keep in mind that changes in this area will affect | |
| 110 | +all ASICs, meaning that refactoring requires a comprehensive verification; in | |
| 111 | +other words, this effort can take some time for validation. | |
| 112 | + | |
| 113 | +Level: Advanced | |
| 114 | + | |
| 115 | +Documentation | |
| 116 | +============= | |
| 117 | + | |
| 118 | +Expand kernel-doc | |
| 119 | +----------------- | |
| 120 | + | |
| 121 | +Many DC functions do not have a proper kernel-doc; understanding a function and | |
| 122 | +adding documentation is a great way to learn more about the amdgpu driver and | |
| 123 | +also leave an outstanding contribution to the entire community. | |
| 124 | + | |
| 125 | +Level: Starter | |
| 126 | + | |
| 127 | +Beyond AMDGPU | |
| 128 | +============= | |
| 129 | + | |
| 130 | +AMDGPU provides features that are not yet enabled in the userspace. This | |
| 131 | +section highlights some of the coolest display features, which could be enabled | |
| 132 | +with the userspace developer helper. | |
| 133 | + | |
| 134 | +Enable underlay | |
| 135 | +--------------- | |
| 136 | + | |
| 137 | +AMD display has this feature called underlay (which you can read more about at | |
| 138 | +'Documentation/GPU/amdgpu/display/mpo-overview.rst') which is intended to | |
| 139 | +save power when playing a video. The basic idea is to put a video in the | |
| 140 | +underlay plane at the bottom and the desktop in the plane above it with a hole | |
| 141 | +in the video area. This feature is enabled in ChromeOS, and from our data | |
| 142 | +measurement, it can save power. | |
| 143 | + | |
| 144 | +Level: Unknown | |
| 145 | + | |
| 146 | +Adaptive Backlight Modulation (ABM) | |
| 147 | +----------------------------------- | |
| 148 | + | |
| 149 | +ABM is a feature that adjusts the display panel's backlight level and pixel | |
| 150 | +values depending on the displayed image. This power-saving feature can be very | |
| 151 | +useful when the system starts to run off battery; since this will impact the | |
| 152 | +display output fidelity, it would be good if this option was something that | |
| 153 | +users could turn on or off. | |
| 154 | + | |
| 155 | +Level: Unknown | |
| 156 | + | |
| 157 | + | |
| 158 | +HDR & Color management & VRR | |
| 159 | +---------------------------- | |
| 160 | + | |
| 161 | +HDR, Color Management, and VRR are huge topics and it's hard to put these into | |
| 162 | +concise ToDos. If you are interested in this topic, we recommend checking some | |
| 163 | +blog posts from the community developers to better understand some of the | |
| 164 | +specific challenges and people working on the subject. If anyone wants to work | |
| 165 | +on some particular part, we can try to help with some basic guidance. Finally, | |
| 166 | +keep in mind that we already have some kernel-doc in place for those areas. | |
| 167 | + | |
| 168 | +Level: Unknown | |
| @@ -131,9 +131,6 @@ The DRM blend mode and its elements are then mapped by AMDGPU display manager · 130 unmodified lines | ||
| 131 | 131 | (DM) to program the blending configuration of the Multiple Pipe/Plane Combined |
| 132 | 132 | (MPC), as follows: |
| 133 | 133 | |
| 134 | −.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | |
| 135 | − :doc: mpc-overview | |
| 136 | − | |
| 137 | 134 | .. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h |
| 138 | 135 | :functions: mpcc_blnd_cfg |
| 139 | 136 | |
| @@ -7,18 +7,80 @@ drm/amd/display - Display Core (DC) · 6 unmodified lines | ||
| 7 | 7 | AMD display engine is partially shared with other operating systems; for this |
| 8 | 8 | reason, our Display Core Driver is divided into two pieces: |
| 9 | 9 | |
| 10 | −1. **Display Core (DC)** contains the OS-agnostic components. Things like | |
| 10 | +#. **Display Core (DC)** contains the OS-agnostic components. Things like | |
| 11 | 11 | hardware programming and resource management are handled here. |
| 12 | −2. **Display Manager (DM)** contains the OS-dependent components. Hooks to the | |
| 13 | − amdgpu base driver and DRM are implemented here. | |
| 12 | +#. **Display Manager (DM)** contains the OS-dependent components. Hooks to the | |
| 13 | + amdgpu base driver and DRM are implemented here. For example, you can check | |
| 14 | + display/amdgpu_dm/ folder. | |
| 15 | + | |
| 16 | +------------------ | |
| 17 | +DC Code validation | |
| 18 | +------------------ | |
| 19 | + | |
| 20 | +Maintaining the same code base across multiple OSes requires a lot of | |
| 21 | +synchronization effort between repositories and exhaustive validation. In the | |
| 22 | +DC case, we maintain a tree to centralize code from different parts. The shared | |
| 23 | +repository has integration tests with our Internal Linux CI farm, and we run a | |
| 24 | +comprehensive set of IGT tests in various AMD GPUs/APUs (mostly recent dGPUs | |
| 25 | +and APUs). Our CI also checks ARM64/32, PPC64/32, and x86_64/32 compilation | |
| 26 | +with DCN enabled and disabled. | |
| 27 | + | |
| 28 | +When we upstream a new feature or some patches, we pack them in a patchset with | |
| 29 | +the prefix **DC Patches for <DATE>**, which is created based on the latest | |
| 30 | +`amd-staging-drm-next <https://gitlab.freedesktop.org/agd5f/linux>`_. All of | |
| 31 | +those patches are under a DC version tested as follows: | |
| 32 | + | |
| 33 | +* Ensure that every patch compiles and the entire series pass our set of IGT | |
| 34 | + test in different hardware. | |
| 35 | +* Prepare a branch with those patches for our validation team. If there is an | |
| 36 | + error, a developer will debug as fast as possible; usually, a simple bisect | |
| 37 | + in the series is enough to point to a bad change, and two possible actions | |
| 38 | + emerge: fix the issue or drop the patch. If it is not an easy fix, the bad | |
| 39 | + patch is dropped. | |
| 40 | +* Finally, developers wait a few days for community feedback before we merge | |
| 41 | + the series. | |
| 42 | + | |
| 43 | +It is good to stress that the test phase is something that we take extremely | |
| 44 | +seriously, and we never merge anything that fails our validation. Follows an | |
| 45 | +overview of our test set: | |
| 46 | + | |
| 47 | +#. Manual test | |
| 48 | + * Multiple Hotplugs with DP and HDMI. | |
| 49 | + * Stress test with multiple display configuration changes via the user interface. | |
| 50 | + * Validate VRR behaviour. | |
| 51 | + * Check PSR. | |
| 52 | + * Validate MPO when playing video. | |
| 53 | + * Test more than two displays connected at the same time. | |
| 54 | + * Check suspend/resume. | |
| 55 | + * Validate FPO. | |
| 56 | + * Check MST. | |
| 57 | +#. Automated test | |
| 58 | + * IGT tests in a farm with GPUs and APUs that support DCN and DCE. | |
| 59 | + * Compilation validation with the latest GCC and Clang from LTS distro. | |
| 60 | + * Cross-compilation for PowerPC 64/32, ARM 64/32, and x86 32. | |
| 61 | + | |
| 62 | +In terms of test setup for CI and manual tests, we usually use: | |
| 63 | + | |
| 64 | +#. The latest Ubuntu LTS. | |
| 65 | +#. In terms of userspace, we only use fully updated open-source components | |
| 66 | + provided by the distribution official package manager. | |
| 67 | +#. Regarding IGT, we use the latest code from the upstream. | |
| 68 | +#. Most of the manual tests are conducted in the GNome but we also use KDE. | |
| 69 | + | |
| 70 | +Notice that someone from our test team will always reply to the cover letter | |
| 71 | +with the test report. | |
| 72 | + | |
| 73 | +-------------- | |
| 74 | +DC Information | |
| 75 | +-------------- | |
| 14 | 76 | |
| 15 | 77 | The display pipe is responsible for "scanning out" a rendered frame from the |
| 16 | 78 | GPU memory (also called VRAM, FrameBuffer, etc.) to a display. In other words, |
| 17 | 79 | it would: |
| 18 | 80 | |
| 19 | −1. Read frame information from memory; | |
| 20 | −2. Perform required transformation; | |
| 21 | −3. Send pixel data to sink devices. | |
| 81 | +#. Read frame information from memory; | |
| 82 | +#. Perform required transformation; | |
| 83 | +#. Send pixel data to sink devices. | |
| 22 | 84 | |
| 23 | 85 | If you want to learn more about our driver details, take a look at the below |
| 24 | 86 | table of content: |
| @@ -26,7 +88,9 @@ table of content: · 1 unmodified line | ||
| 26 | 88 | .. toctree:: |
| 27 | 89 | |
| 28 | 90 | display-manager.rst |
| 29 | − dc-debug.rst | |
| 30 | 91 | dcn-overview.rst |
| 92 | + dcn-blocks.rst | |
| 31 | 93 | mpo-overview.rst |
| 94 | + dc-debug.rst | |
| 95 | + display-contributing.rst | |
| 32 | 96 | dc-glossary.rst |
| @@ -153,18 +153,6 @@ Managed Resources · 152 unmodified lines | ||
| 153 | 153 | .. kernel-doc:: include/drm/drm_managed.h |
| 154 | 154 | :internal: |
| 155 | 155 | |
| 156 | −Bus-specific Device Registration and PCI Support | |
| 157 | −------------------------------------------------ | |
| 158 | − | |
| 159 | −A number of functions are provided to help with device registration. The | |
| 160 | −functions deal with PCI and platform devices respectively and are only | |
| 161 | −provided for historical reasons. These are all deprecated and shouldn't | |
| 162 | −be used in new drivers. Besides that there's a few helpers for pci | |
| 163 | −drivers. | |
| 164 | − | |
| 165 | −.. kernel-doc:: drivers/gpu/drm/drm_pci.c | |
| 166 | − :export: | |
| 167 | − | |
| 168 | 156 | Open/Close, File Operations and IOCTLs |
| 169 | 157 | ====================================== |
| 170 | 158 | |
| @@ -164,6 +164,8 @@ Conference talks · 163 unmodified lines | ||
| 164 | 164 | Slides and articles |
| 165 | 165 | ------------------- |
| 166 | 166 | |
| 167 | +* `The Linux graphics stack in a nutshell, part 1 <https://lwn.net/Articles/955376/>`_ - Thomas Zimmermann (2023) | |
| 168 | +* `The Linux graphics stack in a nutshell, part 2 <https://lwn.net/Articles/955708/>`_ - Thomas Zimmermann (2023) | |
| 167 | 169 | * `Understanding the Linux Graphics Stack <https://bootlin.com/doc/training/graphics/graphics-slides.pdf>`_ - Bootlin (2022) |
| 168 | 170 | * `DRM KMS overview <https://wiki.st.com/stm32mpu/wiki/DRM_KMS_overview>`_ - STMicroelectronics (2021) |
| 169 | 171 | * `Linux graphic stack <https://studiopixl.com/2017-05-13/linux-graphic-stack-an-overview>`_ - Nathan Gauër (2017) |
| @@ -31,7 +31,3 @@ host such documentation: · 30 unmodified lines | ||
| 31 | 31 | .. toctree:: |
| 32 | 32 | |
| 33 | 33 | i915_vm_bind.rst |
| 34 | − | |
| 35 | −.. toctree:: | |
| 36 | − | |
| 37 | − xe.rst | |
| @@ -1,234 +0,0 @@ | ||
| 1 | −========================== | |
| 2 | −Xe – Merge Acceptance Plan | |
| 3 | −========================== | |
| 4 | −Xe is a new driver for Intel GPUs that supports both integrated and | |
| 5 | −discrete platforms starting with Tiger Lake (first Intel Xe Architecture). | |
| 6 | − | |
| 7 | −This document aims to establish a merge plan for the Xe, by writing down clear | |
| 8 | −pre-merge goals, in order to avoid unnecessary delays. | |
| 9 | − | |
| 10 | −Xe – Overview | |
| 11 | −============= | |
| 12 | −The main motivation of Xe is to have a fresh base to work from that is | |
| 13 | −unencumbered by older platforms, whilst also taking the opportunity to | |
| 14 | −rearchitect our driver to increase sharing across the drm subsystem, both | |
| 15 | −leveraging and allowing us to contribute more towards other shared components | |
| 16 | −like TTM and drm/scheduler. | |
| 17 | − | |
| 18 | −This is also an opportunity to start from the beginning with a clean uAPI that is | |
| 19 | −extensible by design and already aligned with the modern userspace needs. For | |
| 20 | −this reason, the memory model is solely based on GPU Virtual Address space | |
| 21 | −bind/unbind (‘VM_BIND’) of GEM buffer objects (BOs) and execution only supporting | |
| 22 | −explicit synchronization. With persistent mapping across the execution, the | |
| 23 | −userspace does not need to provide a list of all required mappings during each | |
| 24 | −submission. | |
| 25 | − | |
| 26 | −The new driver leverages a lot from i915. As for display, the intent is to share | |
| 27 | −the display code with the i915 driver so that there is maximum reuse there. | |
| 28 | − | |
| 29 | −As for the power management area, the goal is to have a much-simplified support | |
| 30 | −for the system suspend states (S-states), PCI device suspend states (D-states), | |
| 31 | −GPU/Render suspend states (R-states) and frequency management. It should leverage | |
| 32 | −as much as possible all the existent PCI-subsystem infrastructure (pm and | |
| 33 | −runtime_pm) and underlying firmware components such PCODE and GuC for the power | |
| 34 | −states and frequency decisions. | |
| 35 | − | |
| 36 | −Repository: | |
| 37 | − | |
| 38 | −https://gitlab.freedesktop.org/drm/xe/kernel (branch drm-xe-next) | |
| 39 | − | |
| 40 | −Xe – Platforms | |
| 41 | −============== | |
| 42 | −Currently, Xe is already functional and has experimental support for multiple | |
| 43 | −platforms starting from Tiger Lake, with initial support in userspace implemented | |
| 44 | −in Mesa (for Iris and Anv, our OpenGL and Vulkan drivers), as well as in NEO | |
| 45 | −(for OpenCL and Level0). | |
| 46 | − | |
| 47 | −During a transition period, platforms will be supported by both Xe and i915. | |
| 48 | −However, the force_probe mechanism existent in both drivers will allow only one | |
| 49 | −official and by-default probe at a given time. | |
| 50 | − | |
| 51 | −For instance, in order to probe a DG2 which PCI ID is 0x5690 by Xe instead of | |
| 52 | −i915, the following set of parameters need to be used: | |
| 53 | − | |
| 54 | −``` | |
| 55 | −i915.force_probe=!5690 xe.force_probe=5690 | |
| 56 | −``` | |
| 57 | − | |
| 58 | −In both drivers, the ‘.require_force_probe’ protection forces the user to use the | |
| 59 | −force_probe parameter while the driver is under development. This protection is | |
| 60 | −only removed when the support for the platform and the uAPI are stable. Stability | |
| 61 | −which needs to be demonstrated by CI results. | |
| 62 | − | |
| 63 | −In order to avoid user space regressions, i915 will continue to support all the | |
| 64 | −current platforms that are already out of this protection. Xe support will be | |
| 65 | −forever experimental and dependent on the usage of force_probe for these | |
| 66 | −platforms. | |
| 67 | − | |
| 68 | −When the time comes for Xe, the protection will be lifted on Xe and kept in i915. | |
| 69 | − | |
| 70 | −Xe – Pre-Merge Goals - Work-in-Progress | |
| 71 | −======================================= | |
| 72 | − | |
| 73 | −Display integration with i915 | |
| 74 | −----------------------------- | |
| 75 | −In order to share the display code with the i915 driver so that there is maximum | |
| 76 | −reuse, the i915/display/ code is built twice, once for i915.ko and then for | |
| 77 | −xe.ko. Currently, the i915/display code in Xe tree is polluted with many 'ifdefs' | |
| 78 | −depending on the build target. The goal is to refactor both Xe and i915/display | |
| 79 | −code simultaneously in order to get a clean result before they land upstream, so | |
| 80 | −that display can already be part of the initial pull request towards drm-next. | |
| 81 | − | |
| 82 | −However, display code should not gate the acceptance of Xe in upstream. Xe | |
| 83 | −patches will be refactored in a way that display code can be removed, if needed, | |
| 84 | −from the first pull request of Xe towards drm-next. The expectation is that when | |
| 85 | −both drivers are part of the drm-tip, the introduction of cleaner patches will be | |
| 86 | −easier and speed up. | |
| 87 | − | |
| 88 | −Xe – uAPI high level overview | |
| 89 | −============================= | |
| 90 | − | |
| 91 | −...Warning: To be done in follow up patches after/when/where the main consensus in various items are individually reached. | |
| 92 | − | |
| 93 | −Xe – Pre-Merge Goals - Completed | |
| 94 | −================================ | |
| 95 | − | |
| 96 | −Drm_exec | |
| 97 | −-------- | |
| 98 | −Helper to make dma_resv locking for a big number of buffers is getting removed in | |
| 99 | −the drm_exec series proposed in https://patchwork.freedesktop.org/patch/524376/ | |
| 100 | −If that happens, Xe needs to change and incorporate the changes in the driver. | |
| 101 | −The goal is to engage with the Community to understand if the best approach is to | |
| 102 | −move that to the drivers that are using it or if we should keep the helpers in | |
| 103 | −place waiting for Xe to get merged. | |
| 104 | − | |
| 105 | −This item ties into the GPUVA, VM_BIND, and even long-running compute support. | |
| 106 | − | |
| 107 | −As a key measurable result, we need to have a community consensus documented in | |
| 108 | −this document and the Xe driver prepared for the changes, if necessary. | |
| 109 | − | |
| 110 | −Userptr integration and vm_bind | |
| 111 | −------------------------------- | |
| 112 | −Different drivers implement different ways of dealing with execution of userptr. | |
| 113 | −With multiple drivers currently introducing support to VM_BIND, the goal is to | |
| 114 | −aim for a DRM consensus on what’s the best way to have that support. To some | |
| 115 | −extent this is already getting addressed itself with the GPUVA where likely the | |
| 116 | −userptr will be a GPUVA with a NULL GEM call VM bind directly on the userptr. | |
| 117 | −However, there are more aspects around the rules for that and the usage of | |
| 118 | −mmu_notifiers, locking and other aspects. | |
| 119 | − | |
| 120 | −This task here has the goal of introducing a documentation of the basic rules. | |
| 121 | − | |
| 122 | −The documentation *needs* to first live in this document (API session below) and | |
| 123 | −then moved to another more specific document or at Xe level or at DRM level. | |
| 124 | − | |
| 125 | −Documentation should include: | |
| 126 | − | |
| 127 | − * The userptr part of the VM_BIND api. | |
| 128 | − | |
| 129 | − * Locking, including the page-faulting case. | |
| 130 | − | |
| 131 | − * O(1) complexity under VM_BIND. | |
| 132 | − | |
| 133 | −The document is now included in the drm documentation :doc:`here </gpu/drm-vm-bind-async>`. | |
| 134 | − | |
| 135 | −Some parts of userptr like mmu_notifiers should become GPUVA or DRM helpers when | |
| 136 | −the second driver supporting VM_BIND+userptr appears. Details to be defined when | |
| 137 | −the time comes. | |
| 138 | − | |
| 139 | −The DRM GPUVM helpers do not yet include the userptr parts, but discussions | |
| 140 | −about implementing them are ongoing. | |
| 141 | − | |
| 142 | −ASYNC VM_BIND | |
| 143 | −------------- | |
| 144 | −Although having a common DRM level IOCTL for VM_BIND is not a requirement to get | |
| 145 | −Xe merged, it is mandatory to have a consensus with other drivers and Mesa. | |
| 146 | −It needs to be clear how to handle async VM_BIND and interactions with userspace | |
| 147 | −memory fences. Ideally with helper support so people don't get it wrong in all | |
| 148 | −possible ways. | |
| 149 | − | |
| 150 | −As a key measurable result, the benefits of ASYNC VM_BIND and a discussion of | |
| 151 | −various flavors, error handling and sample API suggestions are documented in | |
| 152 | −:doc:`The ASYNC VM_BIND document </gpu/drm-vm-bind-async>`. | |
| 153 | − | |
| 154 | −Drm_scheduler | |
| 155 | −------------- | |
| 156 | −Xe primarily uses Firmware based scheduling (GuC FW). However, it will use | |
| 157 | −drm_scheduler as the scheduler ‘frontend’ for userspace submission in order to | |
| 158 | −resolve syncobj and dma-buf implicit sync dependencies. However, drm_scheduler is | |
| 159 | −not yet prepared to handle the 1-to-1 relationship between drm_gpu_scheduler and | |
| 160 | −drm_sched_entity. | |
| 161 | − | |
| 162 | −Deeper changes to drm_scheduler should *not* be required to get Xe accepted, but | |
| 163 | −some consensus needs to be reached between Xe and other community drivers that | |
| 164 | −could also benefit from this work, for coupling FW based/assisted submission such | |
| 165 | −as the ARM’s new Mali GPU driver, and others. | |
| 166 | − | |
| 167 | −As a key measurable result, the patch series introducing Xe itself shall not | |
| 168 | −depend on any other patch touching drm_scheduler itself that was not yet merged | |
| 169 | −through drm-misc. This, by itself, already includes the reach of an agreement for | |
| 170 | −uniform 1 to 1 relationship implementation / usage across drivers. | |
| 171 | − | |
| 172 | −Long running compute: minimal data structure/scaffolding | |
| 173 | −-------------------------------------------------------- | |
| 174 | −The generic scheduler code needs to include the handling of endless compute | |
| 175 | −contexts, with the minimal scaffolding for preempt-ctx fences (probably on the | |
| 176 | −drm_sched_entity) and making sure drm_scheduler can cope with the lack of job | |
| 177 | −completion fence. | |
| 178 | − | |
| 179 | −The goal is to achieve a consensus ahead of Xe initial pull-request, ideally with | |
| 180 | −this minimal drm/scheduler work, if needed, merged to drm-misc in a way that any | |
| 181 | −drm driver, including Xe, could re-use and add their own individual needs on top | |
| 182 | −in a next stage. However, this should not block the initial merge. | |
| 183 | − | |
| 184 | −Dev_coredump | |
| 185 | −------------ | |
| 186 | − | |
| 187 | −Xe needs to align with other drivers on the way that the error states are | |
| 188 | −dumped, avoiding a Xe only error_state solution. The goal is to use devcoredump | |
| 189 | −infrastructure to report error states, since it produces a standardized way | |
| 190 | −by exposing a virtual and temporary /sys/class/devcoredump device. | |
| 191 | − | |
| 192 | −As the key measurable result, Xe driver needs to provide GPU snapshots captured | |
| 193 | −at hang time through devcoredump, but without depending on any core modification | |
| 194 | −of devcoredump infrastructure itself. | |
| 195 | − | |
| 196 | −Later, when we are in-tree, the goal is to collaborate with devcoredump | |
| 197 | −infrastructure with overall possible improvements, like multiple file support | |
| 198 | −for better organization of the dumps, snapshot support, dmesg extra print, | |
| 199 | −and whatever may make sense and help the overall infrastructure. | |
| 200 | − | |
| 201 | −DRM_VM_BIND | |
| 202 | −----------- | |
| 203 | −Nouveau, and Xe are all implementing ‘VM_BIND’ and new ‘Exec’ uAPIs in order to | |
| 204 | −fulfill the needs of the modern uAPI. Xe merge should *not* be blocked on the | |
| 205 | −development of a common new drm_infrastructure. However, the Xe team needs to | |
| 206 | −engage with the community to explore the options of a common API. | |
| 207 | − | |
| 208 | −As a key measurable result, the DRM_VM_BIND needs to be documented in this file | |
| 209 | −below, or this entire block deleted if the consensus is for independent drivers | |
| 210 | −vm_bind ioctls. | |
| 211 | − | |
| 212 | −Although having a common DRM level IOCTL for VM_BIND is not a requirement to get | |
| 213 | −Xe merged, it is mandatory to enforce the overall locking scheme for all major | |
| 214 | −structs and list (so vm and vma). So, a consensus is needed, and possibly some | |
| 215 | −common helpers. If helpers are needed, they should be also documented in this | |
| 216 | −document. | |
| 217 | − | |
| 218 | −GPU VA | |
| 219 | −------ | |
| 220 | −Two main goals of Xe are meeting together here: | |
| 221 | − | |
| 222 | −1) Have an uAPI that aligns with modern UMD needs. | |
| 223 | − | |
| 224 | −2) Early upstream engagement. | |
| 225 | − | |
| 226 | −RedHat engineers working on Nouveau proposed a new DRM feature to handle keeping | |
| 227 | −track of GPU virtual address mappings. This is still not merged upstream, but | |
| 228 | −this aligns very well with our goals and with our VM_BIND. The engagement with | |
| 229 | −upstream and the port of Xe towards GPUVA is already ongoing. | |
| 230 | − | |
| 231 | −As a key measurable result, Xe needs to be aligned with the GPU VA and working in | |
| 232 | −our tree. Missing Nouveau patches should *not* block Xe and any needed GPUVA | |
| 233 | −related patch should be independent and present on dri-devel or acked by | |
| 234 | −maintainers to go along with the first Xe pull request towards drm-next. | |
| @@ -120,6 +120,29 @@ Contact: Daniel Vetter, respective driver maintainers · 119 unmodified lines | ||
| 120 | 120 | |
| 121 | 121 | Level: Advanced |
| 122 | 122 | |
| 123 | +Rename drm_atomic_state | |
| 124 | +----------------------- | |
| 125 | + | |
| 126 | +The KMS framework uses two slightly different definitions for the ``state`` | |
| 127 | +concept. For a given object (plane, CRTC, encoder, etc., so | |
| 128 | +``drm_$OBJECT_state``), the state is the entire state of that object. However, | |
| 129 | +at the device level, ``drm_atomic_state`` refers to a state update for a | |
| 130 | +limited number of objects. | |
| 131 | + | |
| 132 | +The state isn't the entire device state, but only the full state of some | |
| 133 | +objects in that device. This is confusing to newcomers, and | |
| 134 | +``drm_atomic_state`` should be renamed to something clearer like | |
| 135 | +``drm_atomic_commit``. | |
| 136 | + | |
| 137 | +In addition to renaming the structure itself, it would also imply renaming some | |
| 138 | +related functions (``drm_atomic_state_alloc``, ``drm_atomic_state_get``, | |
| 139 | +``drm_atomic_state_put``, ``drm_atomic_state_init``, | |
| 140 | +``__drm_atomic_state_free``, etc.). | |
| 141 | + | |
| 142 | +Contact: Maxime Ripard <mripard@kernel.org> | |
| 143 | + | |
| 144 | +Level: Advanced | |
| 145 | + | |
| 123 | 146 | Fallout from atomic KMS |
| 124 | 147 | ----------------------- |
| 125 | 148 | |
| @@ -942,6 +942,10 @@ attribute-sets: · 941 unmodified lines | ||
| 942 | 942 | - |
| 943 | 943 | name: gro-ipv4-max-size |
| 944 | 944 | type: u32 |
| 945 | + - | |
| 946 | + name: dpll-pin | |
| 947 | + type: nest | |
| 948 | + nested-attributes: link-dpll-pin-attrs | |
| 945 | 949 | - |
| 946 | 950 | name: af-spec-attrs |
| 947 | 951 | attributes: |
| @@ -1627,6 +1631,12 @@ attribute-sets: · 679 unmodified lines | ||
| 1627 | 1631 | - |
| 1628 | 1632 | name: used |
| 1629 | 1633 | type: u8 |
| 1634 | + - | |
| 1635 | + name: link-dpll-pin-attrs | |
| 1636 | + attributes: | |
| 1637 | + - | |
| 1638 | + name: id | |
| 1639 | + type: u32 | |
| 1630 | 1640 | |
| 1631 | 1641 | sub-messages: |
| 1632 | 1642 | - |
| @@ -12,5 +12,7 @@ · 11 unmodified lines | ||
| 12 | 12 | <script type="text/javascript"> <!-- |
| 13 | 13 | var sbar = document.getElementsByClassName("sphinxsidebar")[0]; |
| 14 | 14 | let currents = document.getElementsByClassName("current") |
| 15 | − sbar.scrollTop = currents[currents.length - 1].offsetTop; | |
| 15 | + if (currents.length) { | |
| 16 | + sbar.scrollTop = currents[currents.length - 1].offsetTop; | |
| 17 | + } | |
| 16 | 18 | --> </script> |
| @@ -448,17 +448,17 @@ Function-specific configfs interface · 447 unmodified lines | ||
| 448 | 448 | The function name to use when creating the function directory is "ncm". |
| 449 | 449 | The NCM function provides these attributes in its function directory: |
| 450 | 450 | |
| 451 | − =============== ================================================== | |
| 452 | − ifname network device interface name associated with this | |
| 453 | − function instance | |
| 454 | − qmult queue length multiplier for high and super speed | |
| 455 | − host_addr MAC address of host's end of this | |
| 456 | − Ethernet over USB link | |
| 457 | − dev_addr MAC address of device's end of this | |
| 458 | − Ethernet over USB link | |
| 459 | − max_segment_size Segment size required for P2P connections. This | |
| 460 | − will set MTU to (max_segment_size - 14 bytes) | |
| 461 | − =============== ================================================== | |
| 451 | + ======================= ================================================== | |
| 452 | + ifname network device interface name associated with this | |
| 453 | + function instance | |
| 454 | + qmult queue length multiplier for high and super speed | |
| 455 | + host_addr MAC address of host's end of this | |
| 456 | + Ethernet over USB link | |
| 457 | + dev_addr MAC address of device's end of this | |
| 458 | + Ethernet over USB link | |
| 459 | + max_segment_size Segment size required for P2P connections. This | |
| 460 | + will set MTU to 14 bytes | |
| 461 | + ======================= ================================================== | |
| 462 | 462 | |
| 463 | 463 | and after creating the functions/ncm.<instance name> they contain default |
| 464 | 464 | values: qmult is 5, dev_addr and host_addr are randomly selected. |
| @@ -3168,10 +3168,10 @@ F: drivers/hwmon/asus-ec-sensors.c · 3167 unmodified lines | ||
| 3168 | 3168 | |
| 3169 | 3169 | ASUS NOTEBOOKS AND EEEPC ACPI/WMI EXTRAS DRIVERS |
| 3170 | 3170 | M: Corentin Chary <corentin.chary@gmail.com> |
| 3171 | −L: acpi4asus-user@lists.sourceforge.net | |
| 3171 | +M: Luke D. Jones <luke@ljones.dev> | |
| 3172 | 3172 | L: platform-driver-x86@vger.kernel.org |
| 3173 | 3173 | S: Maintained |
| 3174 | −W: http://acpi4asus.sf.net | |
| 3174 | +W: https://asus-linux.org/ | |
| 3175 | 3175 | F: drivers/platform/x86/asus*.c |
| 3176 | 3176 | F: drivers/platform/x86/eeepc*.c |
| 3177 | 3177 | |
| @@ -4547,7 +4547,7 @@ F: drivers/net/ieee802154/ca8210.c · 1369 unmodified lines | ||
| 4547 | 4547 | |
| 4548 | 4548 | CACHEFILES: FS-CACHE BACKEND FOR CACHING ON MOUNTED FILESYSTEMS |
| 4549 | 4549 | M: David Howells <dhowells@redhat.com> |
| 4550 | −L: linux-cachefs@redhat.com (moderated for non-subscribers) | |
| 4550 | +L: netfs@lists.linux.dev | |
| 4551 | 4551 | S: Supported |
| 4552 | 4552 | F: Documentation/filesystems/caching/cachefiles.rst |
| 4553 | 4553 | F: fs/cachefiles/ |
| @@ -5958,7 +5958,6 @@ S: Maintained · 1404 unmodified lines | ||
| 5958 | 5958 | F: drivers/platform/x86/dell/dell-wmi-descriptor.c |
| 5959 | 5959 | |
| 5960 | 5960 | DELL WMI HARDWARE PRIVACY SUPPORT |
| 5961 | −M: Perry Yuan <Perry.Yuan@dell.com> | |
| 5962 | 5961 | L: Dell.Client.Kernel@dell.com |
| 5963 | 5962 | L: platform-driver-x86@vger.kernel.org |
| 5964 | 5963 | S: Maintained |
| @@ -7309,6 +7308,7 @@ F: drivers/gpu/drm/xlnx/ · 1344 unmodified lines | ||
| 7309 | 7308 | |
| 7310 | 7309 | DRM GPU SCHEDULER |
| 7311 | 7310 | M: Luben Tuikov <ltuikov89@gmail.com> |
| 7311 | +M: Matthew Brost <matthew.brost@intel.com> | |
| 7312 | 7312 | L: dri-devel@lists.freedesktop.org |
| 7313 | 7313 | S: Maintained |
| 7314 | 7314 | T: git git://anongit.freedesktop.org/drm/drm-misc |
| @@ -7955,12 +7955,13 @@ L: rust-for-linux@vger.kernel.org · 640 unmodified lines | ||
| 7955 | 7955 | S: Maintained |
| 7956 | 7956 | F: rust/kernel/net/phy.rs |
| 7957 | 7957 | |
| 7958 | −EXEC & BINFMT API | |
| 7958 | +EXEC & BINFMT API, ELF | |
| 7959 | 7959 | R: Eric Biederman <ebiederm@xmission.com> |
| 7960 | 7960 | R: Kees Cook <keescook@chromium.org> |
| 7961 | 7961 | L: linux-mm@kvack.org |
| 7962 | 7962 | S: Supported |
| 7963 | 7963 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux.git for-next/execve |
| 7964 | +F: Documentation/userspace-api/ELF.rst | |
| 7964 | 7965 | F: fs/*binfmt_*.c |
| 7965 | 7966 | F: fs/exec.c |
| 7966 | 7967 | F: include/linux/binfmts.h |
| @@ -8223,7 +8224,8 @@ F: include/linux/iomap.h · 256 unmodified lines | ||
| 8223 | 8224 | |
| 8224 | 8225 | FILESYSTEMS [NETFS LIBRARY] |
| 8225 | 8226 | M: David Howells <dhowells@redhat.com> |
| 8226 | −L: linux-cachefs@redhat.com (moderated for non-subscribers) | |
| 8227 | +R: Jeff Layton <jlayton@kernel.org> | |
| 8228 | +L: netfs@lists.linux.dev | |
| 8227 | 8229 | L: linux-fsdevel@vger.kernel.org |
| 8228 | 8230 | S: Supported |
| 8229 | 8231 | F: Documentation/filesystems/caching/ |
| @@ -10090,7 +10092,7 @@ L: linux-i2c@vger.kernel.org · 1860 unmodified lines | ||
| 10090 | 10092 | S: Maintained |
| 10091 | 10093 | W: https://i2c.wiki.kernel.org/ |
| 10092 | 10094 | Q: https://patchwork.ozlabs.org/project/linux-i2c/list/ |
| 10093 | −T: git git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux.git | |
| 10095 | +T: git git://git.kernel.org/pub/scm/linux/kernel/git/andi.shyti/linux.git | |
| 10094 | 10096 | F: Documentation/devicetree/bindings/i2c/ |
| 10095 | 10097 | F: drivers/i2c/algos/ |
| 10096 | 10098 | F: drivers/i2c/busses/ |
| @@ -10282,7 +10284,7 @@ F: drivers/scsi/ibmvscsi/ibmvscsi* · 185 unmodified lines | ||
| 10282 | 10284 | F: include/scsi/viosrp.h |
| 10283 | 10285 | |
| 10284 | 10286 | IBM Power Virtual SCSI Device Target Driver |
| 10285 | −M: Michael Cyr <mikecyr@linux.ibm.com> | |
| 10287 | +M: Tyrel Datwyler <tyreld@linux.ibm.com> | |
| 10286 | 10288 | L: linux-scsi@vger.kernel.org |
| 10287 | 10289 | L: target-devel@vger.kernel.org |
| 10288 | 10290 | S: Supported |
| @@ -10466,7 +10468,6 @@ F: drivers/media/rc/img-ir/ · 177 unmodified lines | ||
| 10466 | 10468 | |
| 10467 | 10469 | IMGTEC POWERVR DRM DRIVER |
| 10468 | 10470 | M: Frank Binns <frank.binns@imgtec.com> |
| 10469 | −M: Donald Robson <donald.robson@imgtec.com> | |
| 10470 | 10471 | M: Matt Coster <matt.coster@imgtec.com> |
| 10471 | 10472 | S: Supported |
| 10472 | 10473 | T: git git://anongit.freedesktop.org/drm/drm-misc |
| @@ -11724,6 +11725,7 @@ F: fs/smb/server/ · 1251 unmodified lines | ||
| 11724 | 11725 | KERNEL UNIT TESTING FRAMEWORK (KUnit) |
| 11725 | 11726 | M: Brendan Higgins <brendanhiggins@google.com> |
| 11726 | 11727 | M: David Gow <davidgow@google.com> |
| 11728 | +R: Rae Moar <rmoar@google.com> | |
| 11727 | 11729 | L: linux-kselftest@vger.kernel.org |
| 11728 | 11730 | L: kunit-dev@googlegroups.com |
| 11729 | 11731 | S: Maintained |
| @@ -12902,6 +12904,8 @@ M: Alejandro Colomar <alx@kernel.org> · 1172 unmodified lines | ||
| 12902 | 12904 | L: linux-man@vger.kernel.org |
| 12903 | 12905 | S: Maintained |
| 12904 | 12906 | W: http://www.kernel.org/doc/man-pages |
| 12907 | +T: git git://git.kernel.org/pub/scm/docs/man-pages/man-pages.git | |
| 12908 | +T: git git://www.alejandro-colomar.es/src/alx/linux/man-pages/man-pages.git | |
| 12905 | 12909 | |
| 12906 | 12910 | MANAGEMENT COMPONENT TRANSPORT PROTOCOL (MCTP) |
| 12907 | 12911 | M: Jeremy Kerr <jk@codeconstruct.com.au> |
| @@ -15177,6 +15181,7 @@ F: Documentation/networking/net_cachelines/net_device.rst · 2269 unmodified lines | ||
| 15177 | 15181 | F: drivers/connector/ |
| 15178 | 15182 | F: drivers/net/ |
| 15179 | 15183 | F: include/dt-bindings/net/ |
| 15184 | +F: include/linux/cn_proc.h | |
| 15180 | 15185 | F: include/linux/etherdevice.h |
| 15181 | 15186 | F: include/linux/fcdevice.h |
| 15182 | 15187 | F: include/linux/fddidevice.h |
| @@ -15184,6 +15189,7 @@ F: include/linux/hippidevice.h · 1 unmodified line | ||
| 15184 | 15189 | F: include/linux/if_* |
| 15185 | 15190 | F: include/linux/inetdevice.h |
| 15186 | 15191 | F: include/linux/netdevice.h |
| 15192 | +F: include/uapi/linux/cn_proc.h | |
| 15187 | 15193 | F: include/uapi/linux/if_* |
| 15188 | 15194 | F: include/uapi/linux/netdevice.h |
| 15189 | 15195 | X: drivers/net/wireless/ |
| @@ -16856,9 +16862,8 @@ F: Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml · 1666 unmodified lines | ||
| 16856 | 16862 | F: drivers/pci/controller/pcie-xilinx-cpm.c |
| 16857 | 16863 | |
| 16858 | 16864 | PCI ENDPOINT SUBSYSTEM |
| 16859 | −M: Lorenzo Pieralisi <lpieralisi@kernel.org> | |
| 16865 | +M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> | |
| 16860 | 16866 | M: Krzysztof Wilczyński <kw@linux.com> |
| 16861 | −R: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> | |
| 16862 | 16867 | R: Kishon Vijay Abraham I <kishon@kernel.org> |
| 16863 | 16868 | L: linux-pci@vger.kernel.org |
| 16864 | 16869 | S: Supported |
| @@ -18081,7 +18086,6 @@ F: drivers/net/ethernet/qualcomm/emac/ · 1216 unmodified lines | ||
| 18081 | 18086 | |
| 18082 | 18087 | QUALCOMM ETHQOS ETHERNET DRIVER |
| 18083 | 18088 | M: Vinod Koul <vkoul@kernel.org> |
| 18084 | −R: Bhupesh Sharma <bhupesh.sharma@linaro.org> | |
| 18085 | 18089 | L: netdev@vger.kernel.org |
| 18086 | 18090 | L: linux-arm-msm@vger.kernel.org |
| 18087 | 18091 | S: Maintained |
| @@ -20549,6 +20553,7 @@ F: Documentation/translations/sp_SP/ · 2461 unmodified lines | ||
| 20549 | 20553 | |
| 20550 | 20554 | SPARC + UltraSPARC (sparc/sparc64) |
| 20551 | 20555 | M: "David S. Miller" <davem@davemloft.net> |
| 20556 | +M: Andreas Larsson <andreas@gaisler.com> | |
| 20552 | 20557 | L: sparclinux@vger.kernel.org |
| 20553 | 20558 | S: Maintained |
| 20554 | 20559 | Q: http://patchwork.ozlabs.org/project/sparclinux/list/ |
| @@ -24339,13 +24344,6 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/dlemoal/zonefs.git · 3784 unmodified lines | ||
| 24339 | 24344 | F: Documentation/filesystems/zonefs.rst |
| 24340 | 24345 | F: fs/zonefs/ |
| 24341 | 24346 | |
| 24342 | −ZPOOL COMPRESSED PAGE STORAGE API | |
| 24343 | −M: Dan Streetman <ddstreet@ieee.org> | |
| 24344 | −L: linux-mm@kvack.org | |
| 24345 | −S: Maintained | |
| 24346 | −F: include/linux/zpool.h | |
| 24347 | −F: mm/zpool.c | |
| 24348 | − | |
| 24349 | 24347 | ZR36067 VIDEO FOR LINUX DRIVER |
| 24350 | 24348 | M: Corentin Labbe <clabbe@baylibre.com> |
| 24351 | 24349 | L: mjpeg-users@lists.sourceforge.net |
| @@ -24397,7 +24395,9 @@ M: Nhat Pham <nphamcs@gmail.com> · 45 unmodified lines | ||
| 24397 | 24395 | L: linux-mm@kvack.org |
| 24398 | 24396 | S: Maintained |
| 24399 | 24397 | F: Documentation/admin-guide/mm/zswap.rst |
| 24398 | +F: include/linux/zpool.h | |
| 24400 | 24399 | F: include/linux/zswap.h |
| 24400 | +F: mm/zpool.c | |
| 24401 | 24401 | F: mm/zswap.c |
| 24402 | 24402 | |
| 24403 | 24403 | THE REST |
| @@ -2,7 +2,7 @@ · 1 unmodified line | ||
| 2 | 2 | VERSION = 6 |
| 3 | 3 | PATCHLEVEL = 8 |
| 4 | 4 | SUBLEVEL = 0 |
| 5 | −EXTRAVERSION = -rc1 | |
| 5 | +EXTRAVERSION = -rc3 | |
| 6 | 6 | NAME = Hurr durr I'ma ninja sloth |
| 7 | 7 | |
| 8 | 8 | # *DOCUMENTATION* |
| @@ -294,15 +294,15 @@ may-sync-config := 1 · 285 unmodified lines | ||
| 294 | 294 | single-build := |
| 295 | 295 | |
| 296 | 296 | ifneq ($(filter $(no-dot-config-targets), $(MAKECMDGOALS)),) |
| 297 | − ifeq ($(filter-out $(no-dot-config-targets), $(MAKECMDGOALS)),) | |
| 297 | + ifeq ($(filter-out $(no-dot-config-targets), $(MAKECMDGOALS)),) | |
| 298 | 298 | need-config := |
| 299 | − endif | |
| 299 | + endif | |
| 300 | 300 | endif |
| 301 | 301 | |
| 302 | 302 | ifneq ($(filter $(no-sync-config-targets), $(MAKECMDGOALS)),) |
| 303 | − ifeq ($(filter-out $(no-sync-config-targets), $(MAKECMDGOALS)),) | |
| 303 | + ifeq ($(filter-out $(no-sync-config-targets), $(MAKECMDGOALS)),) | |
| 304 | 304 | may-sync-config := |
| 305 | − endif | |
| 305 | + endif | |
| 306 | 306 | endif |
| 307 | 307 | |
| 308 | 308 | need-compiler := $(may-sync-config) |
| @@ -323,9 +323,9 @@ endif · 14 unmodified lines | ||
| 323 | 323 | # We cannot build single targets and the others at the same time |
| 324 | 324 | ifneq ($(filter $(single-targets), $(MAKECMDGOALS)),) |
| 325 | 325 | single-build := 1 |
| 326 | − ifneq ($(filter-out $(single-targets), $(MAKECMDGOALS)),) | |
| 326 | + ifneq ($(filter-out $(single-targets), $(MAKECMDGOALS)),) | |
| 327 | 327 | mixed-build := 1 |
| 328 | − endif | |
| 328 | + endif | |
| 329 | 329 | endif |
| 330 | 330 | |
| 331 | 331 | # For "make -j clean all", "make -j mrproper defconfig all", etc. |
| @@ -986,6 +986,10 @@ NOSTDINC_FLAGS += -nostdinc · 654 unmodified lines | ||
| 986 | 986 | # perform bounds checking. |
| 987 | 987 | KBUILD_CFLAGS += $(call cc-option, -fstrict-flex-arrays=3) |
| 988 | 988 | |
| 989 | +#Currently, disable -Wstringop-overflow for GCC 11, globally. | |
| 990 | +KBUILD_CFLAGS-$(CONFIG_CC_NO_STRINGOP_OVERFLOW) += $(call cc-option, -Wno-stringop-overflow) | |
| 991 | +KBUILD_CFLAGS-$(CONFIG_CC_STRINGOP_OVERFLOW) += $(call cc-option, -Wstringop-overflow) | |
| 992 | + | |
| 989 | 993 | # disable invalid "can't wrap" optimizations for signed / pointers |
| 990 | 994 | KBUILD_CFLAGS += -fno-strict-overflow |
| 991 | 995 | |
| @@ -1662,7 +1666,7 @@ help: · 670 unmodified lines | ||
| 1662 | 1666 | @echo ' (sparse by default)' |
| 1663 | 1667 | @echo ' make C=2 [targets] Force check of all c source with $$CHECK' |
| 1664 | 1668 | @echo ' make RECORDMCOUNT_WARN=1 [targets] Warn about ignored mcount sections' |
| 1665 | − @echo ' make W=n [targets] Enable extra build checks, n=1,2,3 where' | |
| 1669 | + @echo ' make W=n [targets] Enable extra build checks, n=1,2,3,c,e where' | |
| 1666 | 1670 | @echo ' 1: warnings which may be relevant and do not occur too often' |
| 1667 | 1671 | @echo ' 2: warnings which occur quite often but may still be relevant' |
| 1668 | 1672 | @echo ' 3: more obscure warnings, can most likely be ignored' |
| @@ -673,6 +673,7 @@ config SHADOW_CALL_STACK · 672 unmodified lines | ||
| 673 | 673 | bool "Shadow Call Stack" |
| 674 | 674 | depends on ARCH_SUPPORTS_SHADOW_CALL_STACK |
| 675 | 675 | depends on DYNAMIC_FTRACE_WITH_ARGS || DYNAMIC_FTRACE_WITH_REGS || !FUNCTION_GRAPH_TRACER |
| 676 | + depends on MMU | |
| 676 | 677 | help |
| 677 | 678 | This option enables the compiler's Shadow Call Stack, which |
| 678 | 679 | uses a shadow stack to protect function return addresses from |
| @@ -45,8 +45,8 @@ · 44 unmodified lines | ||
| 45 | 45 | num-chipselects = <1>; |
| 46 | 46 | cs-gpios = <&gpio0 ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>; |
| 47 | 47 | |
| 48 | − tpmdev@0 { | |
| 49 | − compatible = "tcg,tpm_tis-spi"; | |
| 48 | + tpm@0 { | |
| 49 | + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; | |
| 50 | 50 | spi-max-frequency = <33000000>; |
| 51 | 51 | reg = <0>; |
| 52 | 52 | }; |
| @@ -80,8 +80,8 @@ · 79 unmodified lines | ||
| 80 | 80 | gpio-miso = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_HIGH>; |
| 81 | 81 | num-chipselects = <1>; |
| 82 | 82 | |
| 83 | − tpmdev@0 { | |
| 84 | − compatible = "tcg,tpm_tis-spi"; | |
| 83 | + tpm@0 { | |
| 84 | + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; | |
| 85 | 85 | spi-max-frequency = <33000000>; |
| 86 | 86 | reg = <0>; |
| 87 | 87 | }; |
| @@ -456,7 +456,7 @@ · 455 unmodified lines | ||
| 456 | 456 | status = "okay"; |
| 457 | 457 | |
| 458 | 458 | tpm: tpm@2e { |
| 459 | − compatible = "tcg,tpm-tis-i2c"; | |
| 459 | + compatible = "nuvoton,npct75x", "tcg,tpm-tis-i2c"; | |
| 460 | 460 | reg = <0x2e>; |
| 461 | 461 | }; |
| 462 | 462 | }; |
| @@ -35,8 +35,8 @@ · 34 unmodified lines | ||
| 35 | 35 | gpio-mosi = <&gpio0 ASPEED_GPIO(X, 4) GPIO_ACTIVE_HIGH>; |
| 36 | 36 | gpio-miso = <&gpio0 ASPEED_GPIO(X, 5) GPIO_ACTIVE_HIGH>; |
| 37 | 37 | |
| 38 | − tpmdev@0 { | |
| 39 | − compatible = "tcg,tpm_tis-spi"; | |
| 38 | + tpm@0 { | |
| 39 | + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; | |
| 40 | 40 | spi-max-frequency = <33000000>; |
| 41 | 41 | reg = <0>; |
| 42 | 42 | }; |
| @@ -116,7 +116,7 @@ · 115 unmodified lines | ||
| 116 | 116 | tpm_tis: tpm@1 { |
| 117 | 117 | pinctrl-names = "default"; |
| 118 | 118 | pinctrl-0 = <&pinctrl_tpm>; |
| 119 | − compatible = "tcg,tpm_tis-spi"; | |
| 119 | + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; | |
| 120 | 120 | reg = <1>; |
| 121 | 121 | spi-max-frequency = <20000000>; |
| 122 | 122 | interrupt-parent = <&gpio5>; |
| @@ -130,7 +130,7 @@ · 129 unmodified lines | ||
| 130 | 130 | * TCG specification - Section 6.4.1 Clocking: |
| 131 | 131 | * TPM shall support a SPI clock frequency range of 10-24 MHz. |
| 132 | 132 | */ |
| 133 | − st33htph: tpm-tis@0 { | |
| 133 | + st33htph: tpm@0 { | |
| 134 | 134 | compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi"; |
| 135 | 135 | reg = <0>; |
| 136 | 136 | spi-max-frequency = <24000000>; |
| @@ -434,6 +434,7 @@ · 433 unmodified lines | ||
| 434 | 434 | }; |
| 435 | 435 | |
| 436 | 436 | &fimd { |
| 437 | + samsung,invert-vclk; | |
| 437 | 438 | status = "okay"; |
| 438 | 439 | }; |
| 439 | 440 | |
| @@ -217,7 +217,7 @@ · 216 unmodified lines | ||
| 217 | 217 | pinctrl-names = "default"; |
| 218 | 218 | pinctrl-0 = <&spi1_pins>; |
| 219 | 219 | |
| 220 | − tpm_spi_tis@0 { | |
| 220 | + tpm@0 { | |
| 221 | 221 | compatible = "tcg,tpm_tis-spi"; |
| 222 | 222 | reg = <0>; |
| 223 | 223 | spi-max-frequency = <500000>; |
| @@ -195,7 +195,7 @@ vdso_prepare: prepare0 · 194 unmodified lines | ||
| 195 | 195 | include/generated/vdso-offsets.h arch/arm64/kernel/vdso/vdso.so |
| 196 | 196 | ifdef CONFIG_COMPAT_VDSO |
| 197 | 197 | $(Q)$(MAKE) $(build)=arch/arm64/kernel/vdso32 \ |
| 198 | − include/generated/vdso32-offsets.h arch/arm64/kernel/vdso32/vdso.so | |
| 198 | + arch/arm64/kernel/vdso32/vdso.so | |
| 199 | 199 | endif |
| 200 | 200 | endif |
| 201 | 201 | |
| @@ -289,7 +289,7 @@ · 288 unmodified lines | ||
| 289 | 289 | #clock-cells = <1>; |
| 290 | 290 | clocks = <&cmu_top CLK_DOUT_CMU_MISC_BUS>, |
| 291 | 291 | <&cmu_top CLK_DOUT_CMU_MISC_SSS>; |
| 292 | − clock-names = "dout_cmu_misc_bus", "dout_cmu_misc_sss"; | |
| 292 | + clock-names = "bus", "sss"; | |
| 293 | 293 | }; |
| 294 | 294 | |
| 295 | 295 | watchdog_cl0: watchdog@10060000 { |
| @@ -120,7 +120,7 @@ · 119 unmodified lines | ||
| 120 | 120 | }; |
| 121 | 121 | |
| 122 | 122 | tpm: tpm@1 { |
| 123 | − compatible = "tcg,tpm_tis-spi"; | |
| 123 | + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; | |
| 124 | 124 | interrupts = <11 IRQ_TYPE_LEVEL_LOW>; |
| 125 | 125 | interrupt-parent = <&gpio2>; |
| 126 | 126 | pinctrl-names = "default"; |
| @@ -89,7 +89,7 @@ · 88 unmodified lines | ||
| 89 | 89 | status = "okay"; |
| 90 | 90 | |
| 91 | 91 | tpm@1 { |
| 92 | − compatible = "tcg,tpm_tis-spi"; | |
| 92 | + compatible = "atmel,attpm20p", "tcg,tpm_tis-spi"; | |
| 93 | 93 | reg = <0x1>; |
| 94 | 94 | spi-max-frequency = <36000000>; |
| 95 | 95 | }; |
| @@ -109,7 +109,7 @@ · 108 unmodified lines | ||
| 109 | 109 | status = "okay"; |
| 110 | 110 | |
| 111 | 111 | tpm@1 { |
| 112 | − compatible = "tcg,tpm_tis-spi"; | |
| 112 | + compatible = "atmel,attpm20p", "tcg,tpm_tis-spi"; | |
| 113 | 113 | reg = <0x1>; |
| 114 | 114 | spi-max-frequency = <36000000>; |
| 115 | 115 | }; |
| @@ -234,7 +234,7 @@ · 233 unmodified lines | ||
| 234 | 234 | status = "okay"; |
| 235 | 235 | |
| 236 | 236 | tpm: tpm@0 { |
| 237 | − compatible = "infineon,slb9670"; | |
| 237 | + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; | |
| 238 | 238 | reg = <0>; |
| 239 | 239 | pinctrl-names = "default"; |
| 240 | 240 | pinctrl-0 = <&pinctrl_tpm>; |
| @@ -103,7 +103,7 @@ · 102 unmodified lines | ||
| 103 | 103 | status = "okay"; |
| 104 | 104 | |
| 105 | 105 | tpm@1 { |
| 106 | − compatible = "tcg,tpm_tis-spi"; | |
| 106 | + compatible = "atmel,attpm20p", "tcg,tpm_tis-spi"; | |
| 107 | 107 | reg = <0x1>; |
| 108 | 108 | spi-max-frequency = <36000000>; |
| 109 | 109 | }; |
| @@ -115,7 +115,7 @@ · 114 unmodified lines | ||
| 115 | 115 | status = "okay"; |
| 116 | 116 | |
| 117 | 117 | tpm@1 { |
| 118 | − compatible = "tcg,tpm_tis-spi"; | |
| 118 | + compatible = "atmel,attpm20p", "tcg,tpm_tis-spi"; | |
| 119 | 119 | reg = <0x1>; |
| 120 | 120 | spi-max-frequency = <36000000>; |
| 121 | 121 | }; |
| @@ -196,7 +196,7 @@ · 195 unmodified lines | ||
| 196 | 196 | status = "okay"; |
| 197 | 197 | |
| 198 | 198 | tpm@0 { |
| 199 | − compatible = "tcg,tpm_tis-spi"; | |
| 199 | + compatible = "atmel,attpm20p", "tcg,tpm_tis-spi"; | |
| 200 | 200 | reg = <0x0>; |
| 201 | 201 | spi-max-frequency = <36000000>; |
| 202 | 202 | }; |
| @@ -65,7 +65,7 @@ · 64 unmodified lines | ||
| 65 | 65 | status = "okay"; |
| 66 | 66 | |
| 67 | 67 | tpm@0 { |
| 68 | − compatible = "infineon,slb9670"; | |
| 68 | + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; | |
| 69 | 69 | reg = <0>; |
| 70 | 70 | spi-max-frequency = <43000000>; |
| 71 | 71 | }; |
| @@ -888,7 +888,7 @@ · 887 unmodified lines | ||
| 888 | 888 | status = "okay"; |
| 889 | 889 | cs-gpios = <&pio 86 GPIO_ACTIVE_LOW>; |
| 890 | 890 | |
| 891 | − cr50@0 { | |
| 891 | + tpm@0 { | |
| 892 | 892 | compatible = "google,cr50"; |
| 893 | 893 | reg = <0>; |
| 894 | 894 | spi-max-frequency = <1000000>; |
| @@ -1402,7 +1402,7 @@ · 1401 unmodified lines | ||
| 1402 | 1402 | pinctrl-names = "default"; |
| 1403 | 1403 | pinctrl-0 = <&spi5_pins>; |
| 1404 | 1404 | |
| 1405 | − cr50@0 { | |
| 1405 | + tpm@0 { | |
| 1406 | 1406 | compatible = "google,cr50"; |
| 1407 | 1407 | reg = <0>; |
| 1408 | 1408 | interrupts-extended = <&pio 171 IRQ_TYPE_EDGE_RISING>; |
| @@ -70,7 +70,7 @@ · 69 unmodified lines | ||
| 70 | 70 | &spi0 { |
| 71 | 71 | status = "okay"; |
| 72 | 72 | |
| 73 | − cr50@0 { | |
| 73 | + tpm@0 { | |
| 74 | 74 | compatible = "google,cr50"; |
| 75 | 75 | reg = <0>; |
| 76 | 76 | interrupt-parent = <&gpio0>; |
| @@ -706,7 +706,7 @@ camera: &i2c7 { · 705 unmodified lines | ||
| 706 | 706 | &spi2 { |
| 707 | 707 | status = "okay"; |
| 708 | 708 | |
| 709 | − cr50@0 { | |
| 709 | + tpm@0 { | |
| 710 | 710 | compatible = "google,cr50"; |
| 711 | 711 | reg = <0>; |
| 712 | 712 | interrupt-parent = <&gpio1>; |
| @@ -17,9 +17,6 @@ · 16 unmodified lines | ||
| 17 | 17 | #ifndef __ASSEMBLY__ |
| 18 | 18 | |
| 19 | 19 | #include <generated/vdso-offsets.h> |
| 20 | −#ifdef CONFIG_COMPAT_VDSO | |
| 21 | −#include <generated/vdso32-offsets.h> | |
| 22 | −#endif | |
| 23 | 20 | |
| 24 | 21 | #define VDSO_SYMBOL(base, name) \ |
| 25 | 22 | ({ \ |
| @@ -77,9 +77,9 @@ obj-$(CONFIG_UNWIND_PATCH_PAC_INTO_SCS) += patch-scs.o · 76 unmodified lines | ||
| 77 | 77 | # We need to prevent the SCS patching code from patching itself. Using |
| 78 | 78 | # -mbranch-protection=none here to avoid the patchable PAC opcodes from being |
| 79 | 79 | # generated triggers an issue with full LTO on Clang, which stops emitting PAC |
| 80 | −# instructions altogether. So instead, omit the unwind tables used by the | |
| 81 | −# patching code, so it will not be able to locate its own PAC instructions. | |
| 82 | −CFLAGS_patch-scs.o += -fno-asynchronous-unwind-tables -fno-unwind-tables | |
| 80 | +# instructions altogether. So disable LTO as well for the compilation unit. | |
| 81 | +CFLAGS_patch-scs.o += -mbranch-protection=none | |
| 82 | +CFLAGS_REMOVE_patch-scs.o += $(CC_FLAGS_LTO) | |
| 83 | 83 | |
| 84 | 84 | # Force dependency (vdso*-wrap.S includes vdso.so through incbin) |
| 85 | 85 | $(obj)/vdso-wrap.o: $(obj)/vdso/vdso.so |
| @@ -127,9 +127,6 @@ obj-vdso := $(c-obj-vdso) $(c-obj-vdso-gettimeofday) $(asm-obj-vdso) · 126 unmodified lines | ||
| 127 | 127 | targets += vdso.lds |
| 128 | 128 | CPPFLAGS_vdso.lds += -P -C -U$(ARCH) |
| 129 | 129 | |
| 130 | −include/generated/vdso32-offsets.h: $(obj)/vdso32.so.dbg FORCE | |
| 131 | − $(call if_changed,vdsosym) | |
| 132 | − | |
| 133 | 130 | # Strip rule for vdso.so |
| 134 | 131 | $(obj)/vdso.so: OBJCOPYFLAGS := -S |
| 135 | 132 | $(obj)/vdso.so: $(obj)/vdso32.so.dbg FORCE |
| @@ -166,9 +163,3 @@ quiet_cmd_vdsoas = AS32 $@ · 30 unmodified lines | ||
| 166 | 163 | |
| 167 | 164 | quiet_cmd_vdsomunge = MUNGE $@ |
| 168 | 165 | cmd_vdsomunge = $(obj)/$(munge) $< $@ |
| 169 | − | |
| 170 | −# Generate vDSO offsets using helper script (borrowed from the 64-bit vDSO) | |
| 171 | −gen-vdsosym := $(srctree)/$(src)/../vdso/gen_vdso_offsets.sh | |
| 172 | −quiet_cmd_vdsosym = VDSOSYM $@ | |
| 173 | −# The AArch64 nm should be able to read an AArch32 binary | |
| 174 | − cmd_vdsosym = $(NM) $< | $(gen-vdsosym) | LC_ALL=C sort > $@ | |
| @@ -60,7 +60,7 @@ int kvm_own_lsx(struct kvm_vcpu *vcpu); · 59 unmodified lines | ||
| 60 | 60 | void kvm_save_lsx(struct loongarch_fpu *fpu); |
| 61 | 61 | void kvm_restore_lsx(struct loongarch_fpu *fpu); |
| 62 | 62 | #else |
| 63 | −static inline int kvm_own_lsx(struct kvm_vcpu *vcpu) { } | |
| 63 | +static inline int kvm_own_lsx(struct kvm_vcpu *vcpu) { return -EINVAL; } | |
| 64 | 64 | static inline void kvm_save_lsx(struct loongarch_fpu *fpu) { } |
| 65 | 65 | static inline void kvm_restore_lsx(struct loongarch_fpu *fpu) { } |
| 66 | 66 | #endif |
| @@ -70,7 +70,7 @@ int kvm_own_lasx(struct kvm_vcpu *vcpu); · 3 unmodified lines | ||
| 70 | 70 | void kvm_save_lasx(struct loongarch_fpu *fpu); |
| 71 | 71 | void kvm_restore_lasx(struct loongarch_fpu *fpu); |
| 72 | 72 | #else |
| 73 | −static inline int kvm_own_lasx(struct kvm_vcpu *vcpu) { } | |
| 73 | +static inline int kvm_own_lasx(struct kvm_vcpu *vcpu) { return -EINVAL; } | |
| 74 | 74 | static inline void kvm_save_lasx(struct loongarch_fpu *fpu) { } |
| 75 | 75 | static inline void kvm_restore_lasx(struct loongarch_fpu *fpu) { } |
| 76 | 76 | #endif |
| @@ -509,7 +509,6 @@ asmlinkage void start_secondary(void) · 508 unmodified lines | ||
| 509 | 509 | sync_counter(); |
| 510 | 510 | cpu = raw_smp_processor_id(); |
| 511 | 511 | set_my_cpu_offset(per_cpu_offset(cpu)); |
| 512 | − rcutree_report_cpu_starting(cpu); | |
| 513 | 512 | |
| 514 | 513 | cpu_probe(); |
| 515 | 514 | constant_clockevent_init(); |
| @@ -675,7 +675,7 @@ static bool fault_supports_huge_mapping(struct kvm_memory_slot *memslot, · 674 unmodified lines | ||
| 675 | 675 | * |
| 676 | 676 | * There are several ways to safely use this helper: |
| 677 | 677 | * |
| 678 | − * - Check mmu_invalidate_retry_hva() after grabbing the mapping level, before | |
| 678 | + * - Check mmu_invalidate_retry_gfn() after grabbing the mapping level, before | |
| 679 | 679 | * consuming it. In this case, mmu_lock doesn't need to be held during the |
| 680 | 680 | * lookup, but it does need to be held while checking the MMU notifier. |
| 681 | 681 | * |
| @@ -855,7 +855,7 @@ retry: · 173 unmodified lines | ||
| 855 | 855 | |
| 856 | 856 | /* Check if an invalidation has taken place since we got pfn */ |
| 857 | 857 | spin_lock(&kvm->mmu_lock); |
| 858 | − if (mmu_invalidate_retry_hva(kvm, mmu_seq, hva)) { | |
| 858 | + if (mmu_invalidate_retry_gfn(kvm, mmu_seq, gfn)) { | |
| 859 | 859 | /* |
| 860 | 860 | * This can happen when mappings are changed asynchronously, but |
| 861 | 861 | * also synchronously if a COW is triggered by |
| @@ -284,12 +284,16 @@ static void setup_tlb_handler(int cpu) · 283 unmodified lines | ||
| 284 | 284 | set_handler(EXCCODE_TLBNR * VECSIZE, handle_tlb_protect, VECSIZE); |
| 285 | 285 | set_handler(EXCCODE_TLBNX * VECSIZE, handle_tlb_protect, VECSIZE); |
| 286 | 286 | set_handler(EXCCODE_TLBPE * VECSIZE, handle_tlb_protect, VECSIZE); |
| 287 | − } | |
| 287 | + } else { | |
| 288 | + int vec_sz __maybe_unused; | |
| 289 | + void *addr __maybe_unused; | |
| 290 | + struct page *page __maybe_unused; | |
| 291 | + | |
| 292 | + /* Avoid lockdep warning */ | |
| 293 | + rcutree_report_cpu_starting(cpu); | |
| 294 | + | |
| 288 | 295 | #ifdef CONFIG_NUMA |
| 289 | − else { | |
| 290 | − void *addr; | |
| 291 | − struct page *page; | |
| 292 | − const int vec_sz = sizeof(exception_handlers); | |
| 296 | + vec_sz = sizeof(exception_handlers); | |
| 293 | 297 | |
| 294 | 298 | if (pcpu_handlers[cpu]) |
| 295 | 299 | return; |
| @@ -305,8 +309,8 @@ static void setup_tlb_handler(int cpu) · 9 unmodified lines | ||
| 305 | 309 | csr_write64(pcpu_handlers[cpu], LOONGARCH_CSR_EENTRY); |
| 306 | 310 | csr_write64(pcpu_handlers[cpu], LOONGARCH_CSR_MERRENTRY); |
| 307 | 311 | csr_write64(pcpu_handlers[cpu] + 80*VECSIZE, LOONGARCH_CSR_TLBRENTRY); |
| 308 | − } | |
| 309 | 312 | #endif |
| 313 | + } | |
| 310 | 314 | } |
| 311 | 315 | |
| 312 | 316 | void tlb_init(int cpu) |
| @@ -15,10 +15,10 @@ · 14 unmodified lines | ||
| 15 | 15 | KBUILD_DEFCONFIG := multi_defconfig |
| 16 | 16 | |
| 17 | 17 | ifdef cross_compiling |
| 18 | − ifeq ($(CROSS_COMPILE),) | |
| 18 | + ifeq ($(CROSS_COMPILE),) | |
| 19 | 19 | CROSS_COMPILE := $(call cc-cross-prefix, \ |
| 20 | 20 | m68k-linux-gnu- m68k-linux- m68k-unknown-linux-gnu-) |
| 21 | − endif | |
| 21 | + endif | |
| 22 | 22 | endif |
| 23 | 23 | |
| 24 | 24 | # |
| @@ -40,6 +40,7 @@ · 39 unmodified lines | ||
| 40 | 40 | #include <linux/string.h> |
| 41 | 41 | |
| 42 | 42 | #include <asm/bootinfo.h> |
| 43 | +#include <prom.h> | |
| 43 | 44 | |
| 44 | 45 | int prom_argc; |
| 45 | 46 | char **prom_argv; |
| @@ -30,13 +30,11 @@ · 29 unmodified lines | ||
| 30 | 30 | #include <linux/mm.h> |
| 31 | 31 | #include <linux/dma-map-ops.h> /* for dma_default_coherent */ |
| 32 | 32 | |
| 33 | +#include <asm/bootinfo.h> | |
| 33 | 34 | #include <asm/mipsregs.h> |
| 34 | 35 | |
| 35 | 36 | #include <au1000.h> |
| 36 | 37 | |
| 37 | −extern void __init board_setup(void); | |
| 38 | −extern void __init alchemy_set_lpj(void); | |
| 39 | − | |
| 40 | 38 | static bool alchemy_dma_coherent(void) |
| 41 | 39 | { |
| 42 | 40 | switch (alchemy_get_cputype()) { |
| @@ -702,7 +702,7 @@ static struct ssb_sprom bcm63xx_sprom = { · 701 unmodified lines | ||
| 702 | 702 | .boardflags_hi = 0x0000, |
| 703 | 703 | }; |
| 704 | 704 | |
| 705 | −int bcm63xx_get_fallback_sprom(struct ssb_bus *bus, struct ssb_sprom *out) | |
| 705 | +static int bcm63xx_get_fallback_sprom(struct ssb_bus *bus, struct ssb_sprom *out) | |
| 706 | 706 | { |
| 707 | 707 | if (bus->bustype == SSB_BUSTYPE_PCI) { |
| 708 | 708 | memcpy(out, &bcm63xx_sprom, sizeof(struct ssb_sprom)); |
| @@ -26,7 +26,7 @@ static struct platform_device bcm63xx_rng_device = { · 25 unmodified lines | ||
| 26 | 26 | .resource = rng_resources, |
| 27 | 27 | }; |
| 28 | 28 | |
| 29 | −int __init bcm63xx_rng_register(void) | |
| 29 | +static int __init bcm63xx_rng_register(void) | |
| 30 | 30 | { |
| 31 | 31 | if (!BCMCPU_IS_6368()) |
| 32 | 32 | return -ENODEV; |
| @@ -10,6 +10,7 @@ · 9 unmodified lines | ||
| 10 | 10 | #include <linux/kernel.h> |
| 11 | 11 | #include <linux/platform_device.h> |
| 12 | 12 | #include <bcm63xx_cpu.h> |
| 13 | +#include <bcm63xx_dev_uart.h> | |
| 13 | 14 | |
| 14 | 15 | static struct resource uart0_resources[] = { |
| 15 | 16 | { |
| @@ -34,7 +34,7 @@ static struct platform_device bcm63xx_wdt_device = { · 33 unmodified lines | ||
| 34 | 34 | }, |
| 35 | 35 | }; |
| 36 | 36 | |
| 37 | −int __init bcm63xx_wdt_register(void) | |
| 37 | +static int __init bcm63xx_wdt_register(void) | |
| 38 | 38 | { |
| 39 | 39 | wdt_resources[0].start = bcm63xx_regset_address(RSET_WDT); |
| 40 | 40 | wdt_resources[0].end = wdt_resources[0].start; |
| @@ -72,7 +72,7 @@ static inline int enable_irq_for_cpu(int cpu, struct irq_data *d, · 71 unmodified lines | ||
| 72 | 72 | */ |
| 73 | 73 | |
| 74 | 74 | #define BUILD_IPIC_INTERNAL(width) \ |
| 75 | −void __dispatch_internal_##width(int cpu) \ | |
| 75 | +static void __dispatch_internal_##width(int cpu) \ | |
| 76 | 76 | { \ |
| 77 | 77 | u32 pending[width / 32]; \ |
| 78 | 78 | unsigned int src, tgt; \ |
| @@ -159,7 +159,7 @@ void __init plat_mem_setup(void) · 158 unmodified lines | ||
| 159 | 159 | board_setup(); |
| 160 | 160 | } |
| 161 | 161 | |
| 162 | −int __init bcm63xx_register_devices(void) | |
| 162 | +static int __init bcm63xx_register_devices(void) | |
| 163 | 163 | { |
| 164 | 164 | /* register gpiochip */ |
| 165 | 165 | bcm63xx_gpio_init(); |
| @@ -178,7 +178,7 @@ int bcm63xx_timer_set(int id, int monotonic, unsigned int countdown_us) · 177 unmodified lines | ||
| 178 | 178 | |
| 179 | 179 | EXPORT_SYMBOL(bcm63xx_timer_set); |
| 180 | 180 | |
| 181 | −int bcm63xx_timer_init(void) | |
| 181 | +static int bcm63xx_timer_init(void) | |
| 182 | 182 | { |
| 183 | 183 | int ret, irq; |
| 184 | 184 | u32 reg; |
| @@ -23,9 +23,6 @@ · 22 unmodified lines | ||
| 23 | 23 | |
| 24 | 24 | #include <cobalt.h> |
| 25 | 25 | |
| 26 | −extern void cobalt_machine_restart(char *command); | |
| 27 | −extern void cobalt_machine_halt(void); | |
| 28 | − | |
| 29 | 26 | const char *get_system_type(void) |
| 30 | 27 | { |
| 31 | 28 | switch (cobalt_board_id) { |
| @@ -37,7 +37,7 @@ static unsigned int nr_prom_mem __initdata; · 36 unmodified lines | ||
| 37 | 37 | */ |
| 38 | 38 | #define ARC_PAGE_SHIFT 12 |
| 39 | 39 | |
| 40 | −struct linux_mdesc * __init ArcGetMemoryDescriptor(struct linux_mdesc *Current) | |
| 40 | +static struct linux_mdesc * __init ArcGetMemoryDescriptor(struct linux_mdesc *Current) | |
| 41 | 41 | { |
| 42 | 42 | return (struct linux_mdesc *) ARC_CALL1(get_mdesc, Current); |
| 43 | 43 | } |
| @@ -597,6 +597,9 @@ · 596 unmodified lines | ||
| 597 | 597 | |
| 598 | 598 | #include <asm/cpu.h> |
| 599 | 599 | |
| 600 | +void alchemy_set_lpj(void); | |
| 601 | +void board_setup(void); | |
| 602 | + | |
| 600 | 603 | /* helpers to access the SYS_* registers */ |
| 601 | 604 | static inline unsigned long alchemy_rdsys(int regofs) |
| 602 | 605 | { |
| @@ -19,4 +19,7 @@ extern int cobalt_board_id; · 18 unmodified lines | ||
| 19 | 19 | #define COBALT_BRD_ID_QUBE2 0x5 |
| 20 | 20 | #define COBALT_BRD_ID_RAQ2 0x6 |
| 21 | 21 | |
| 22 | +void cobalt_machine_halt(void); | |
| 23 | +void cobalt_machine_restart(char *command); | |
| 24 | + | |
| 22 | 25 | #endif /* __ASM_COBALT_H */ |
| @@ -11,6 +11,7 @@ · 10 unmodified lines | ||
| 11 | 11 | |
| 12 | 12 | #include <asm/cpu-features.h> |
| 13 | 13 | #include <asm/cpu-info.h> |
| 14 | +#include <asm/fpu.h> | |
| 14 | 15 | |
| 15 | 16 | #ifdef CONFIG_MIPS_FP_SUPPORT |
| 16 | 17 | |
| @@ -309,6 +310,11 @@ void mips_set_personality_nan(struct arch_elf_state *state) · 292 unmodified lines | ||
| 309 | 310 | struct cpuinfo_mips *c = &boot_cpu_data; |
| 310 | 311 | struct task_struct *t = current; |
| 311 | 312 | |
| 313 | + /* Do this early so t->thread.fpu.fcr31 won't be clobbered in case | |
| 314 | + * we are preempted before the lose_fpu(0) in start_thread. | |
| 315 | + */ | |
| 316 | + lose_fpu(0); | |
| 317 | + | |
| 312 | 318 | t->thread.fpu.fcr31 = c->fpu_csr31; |
| 313 | 319 | switch (state->nan_2008) { |
| 314 | 320 | case 0: |
| @@ -2007,7 +2007,13 @@ unsigned long vi_handlers[64]; · 2006 unmodified lines | ||
| 2007 | 2007 | |
| 2008 | 2008 | void reserve_exception_space(phys_addr_t addr, unsigned long size) |
| 2009 | 2009 | { |
| 2010 | − memblock_reserve(addr, size); | |
| 2010 | + /* | |
| 2011 | + * reserve exception space on CPUs other than CPU0 | |
| 2012 | + * is too late, since memblock is unavailable when APs | |
| 2013 | + * up | |
| 2014 | + */ | |
| 2015 | + if (smp_processor_id() == 0) | |
| 2016 | + memblock_reserve(addr, size); | |
| 2011 | 2017 | } |
| 2012 | 2018 | |
| 2013 | 2019 | void __init *set_except_vector(int n, void *addr) |
| @@ -108,10 +108,9 @@ void __init prom_init(void) · 107 unmodified lines | ||
| 108 | 108 | prom_init_cmdline(); |
| 109 | 109 | |
| 110 | 110 | #if defined(CONFIG_MIPS_MT_SMP) |
| 111 | − if (cpu_has_mipsmt) { | |
| 112 | − lantiq_smp_ops = vsmp_smp_ops; | |
| 111 | + lantiq_smp_ops = vsmp_smp_ops; | |
| 112 | + if (cpu_has_mipsmt) | |
| 113 | 113 | lantiq_smp_ops.init_secondary = lantiq_init_secondary; |
| 114 | − register_smp_ops(&lantiq_smp_ops); | |
| 115 | − } | |
| 114 | + register_smp_ops(&lantiq_smp_ops); | |
| 116 | 115 | #endif |
| 117 | 116 | } |
| @@ -103,6 +103,9 @@ void __init szmem(unsigned int node) · 102 unmodified lines | ||
| 103 | 103 | if (loongson_sysconf.vgabios_addr) |
| 104 | 104 | memblock_reserve(virt_to_phys((void *)loongson_sysconf.vgabios_addr), |
| 105 | 105 | SZ_256K); |
| 106 | + /* set nid for reserved memory */ | |
| 107 | + memblock_set_node((u64)node << 44, (u64)(node + 1) << 44, | |
| 108 | + &memblock.reserved, node); | |
| 106 | 109 | } |
| 107 | 110 | |
| 108 | 111 | #ifndef CONFIG_NUMA |
| @@ -132,6 +132,8 @@ static void __init node_mem_init(unsigned int node) · 131 unmodified lines | ||
| 132 | 132 | |
| 133 | 133 | /* Reserve pfn range 0~node[0]->node_start_pfn */ |
| 134 | 134 | memblock_reserve(0, PAGE_SIZE * start_pfn); |
| 135 | + /* set nid for reserved memory on node 0 */ | |
| 136 | + memblock_set_node(0, 1ULL << 44, &memblock.reserved, 0); | |
| 135 | 137 | } |
| 136 | 138 | } |
| 137 | 139 | |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | |
| 6 | 6 | obj-y := ip27-berr.o ip27-irq.o ip27-init.o ip27-klconfig.o \ |
| 7 | 7 | ip27-klnuma.o ip27-memory.o ip27-nmi.o ip27-reset.o ip27-timer.o \ |
| 8 | − ip27-hubio.o ip27-xtalk.o | |
| 8 | + ip27-xtalk.o | |
| 9 | 9 | |
| 10 | 10 | obj-$(CONFIG_EARLY_PRINTK) += ip27-console.o |
| 11 | 11 | obj-$(CONFIG_SMP) += ip27-smp.o |
| @@ -22,6 +22,8 @@ · 21 unmodified lines | ||
| 22 | 22 | #include <asm/traps.h> |
| 23 | 23 | #include <linux/uaccess.h> |
| 24 | 24 | |
| 25 | +#include "ip27-common.h" | |
| 26 | + | |
| 25 | 27 | static void dump_hub_information(unsigned long errst0, unsigned long errst1) |
| 26 | 28 | { |
| 27 | 29 | static char *err_type[2][8] = { |
| @@ -57,7 +59,7 @@ static void dump_hub_information(unsigned long errst0, unsigned long errst1) · 29 unmodified lines | ||
| 57 | 59 | [st0.pi_stat0_fmt.s0_err_type] ? : "invalid"); |
| 58 | 60 | } |
| 59 | 61 | |
| 60 | −int ip27_be_handler(struct pt_regs *regs, int is_fixup) | |
| 62 | +static int ip27_be_handler(struct pt_regs *regs, int is_fixup) | |
| 61 | 63 | { |
| 62 | 64 | unsigned long errst0, errst1; |
| 63 | 65 | int data = regs->cp0_cause & 4; |
| @@ -10,6 +10,7 @@ extern void hub_rt_clock_event_init(void); · 9 unmodified lines | ||
| 10 | 10 | extern void hub_rtc_init(nasid_t nasid); |
| 11 | 11 | extern void install_cpu_nmi_handler(int slice); |
| 12 | 12 | extern void install_ipi(void); |
| 13 | +extern void ip27_be_init(void); | |
| 13 | 14 | extern void ip27_reboot_setup(void); |
| 14 | 15 | extern const struct plat_smp_ops ip27_smp_ops; |
| 15 | 16 | extern unsigned long node_getfirstfree(nasid_t nasid); |
| @@ -17,4 +18,5 @@ extern void per_cpu_init(void); · 1 unmodified line | ||
| 17 | 18 | extern void replicate_kernel_text(void); |
| 18 | 19 | extern void setup_replication_mask(void); |
| 19 | 20 | |
| 21 | + | |
| 20 | 22 | #endif /* __IP27_COMMON_H */ |
| @@ -1,185 +0,0 @@ | ||
| 1 | −// SPDX-License-Identifier: GPL-2.0-only | |
| 2 | −/* | |
| 3 | − * Copyright (C) 1992-1997, 2000-2003 Silicon Graphics, Inc. | |
| 4 | − * Copyright (C) 2004 Christoph Hellwig. | |
| 5 | − * | |
| 6 | − * Support functions for the HUB ASIC - mostly PIO mapping related. | |
| 7 | − */ | |
| 8 | − | |
| 9 | −#include <linux/bitops.h> | |
| 10 | −#include <linux/string.h> | |
| 11 | −#include <linux/mmzone.h> | |
| 12 | −#include <asm/sn/addrs.h> | |
| 13 | −#include <asm/sn/arch.h> | |
| 14 | −#include <asm/sn/agent.h> | |
| 15 | −#include <asm/sn/io.h> | |
| 16 | −#include <asm/xtalk/xtalk.h> | |
| 17 | − | |
| 18 | − | |
| 19 | −static int force_fire_and_forget = 1; | |
| 20 | − | |
| 21 | −/** | |
| 22 | − * hub_pio_map - establish a HUB PIO mapping | |
| 23 | − * | |
| 24 | − * @nasid: nasid to perform PIO mapping on | |
| 25 | − * @widget: widget ID to perform PIO mapping for | |
| 26 | − * @xtalk_addr: xtalk_address that needs to be mapped | |
| 27 | − * @size: size of the PIO mapping | |
| 28 | − * | |
| 29 | − **/ | |
| 30 | −unsigned long hub_pio_map(nasid_t nasid, xwidgetnum_t widget, | |
| 31 | − unsigned long xtalk_addr, size_t size) | |
| 32 | −{ | |
| 33 | − unsigned i; | |
| 34 | − | |
| 35 | − /* use small-window mapping if possible */ | |
| 36 | − if ((xtalk_addr % SWIN_SIZE) + size <= SWIN_SIZE) | |
| 37 | − return NODE_SWIN_BASE(nasid, widget) + (xtalk_addr % SWIN_SIZE); | |
| 38 | − | |
| 39 | − if ((xtalk_addr % BWIN_SIZE) + size > BWIN_SIZE) { | |
| 40 | − printk(KERN_WARNING "PIO mapping at hub %d widget %d addr 0x%lx" | |
| 41 | − " too big (%ld)\n", | |
| 42 | − nasid, widget, xtalk_addr, size); | |
| 43 | − return 0; | |
| 44 | − } | |
| 45 | − | |
| 46 | − xtalk_addr &= ~(BWIN_SIZE-1); | |
| 47 | − for (i = 0; i < HUB_NUM_BIG_WINDOW; i++) { | |
| 48 | − if (test_and_set_bit(i, hub_data(nasid)->h_bigwin_used)) | |
| 49 | − continue; | |
| 50 | − | |
| 51 | − /* | |
| 52 | − * The code below does a PIO write to setup an ITTE entry. | |
| 53 | − * | |
| 54 | − * We need to prevent other CPUs from seeing our updated | |
| 55 | − * memory shadow of the ITTE (in the piomap) until the ITTE | |
| 56 | − * entry is actually set up; otherwise, another CPU might | |
| 57 | − * attempt a PIO prematurely. | |
| 58 | − * | |
| 59 | − * Also, the only way we can know that an entry has been | |
| 60 | − * received by the hub and can be used by future PIO reads/ | |
| 61 | − * writes is by reading back the ITTE entry after writing it. | |
| 62 | − * | |
| 63 | − * For these two reasons, we PIO read back the ITTE entry | |
| 64 | − * after we write it. | |
| 65 | − */ | |
| 66 | − IIO_ITTE_PUT(nasid, i, HUB_PIO_MAP_TO_MEM, widget, xtalk_addr); | |
| 67 | − __raw_readq(IIO_ITTE_GET(nasid, i)); | |
| 68 | − | |
| 69 | − return NODE_BWIN_BASE(nasid, widget) + (xtalk_addr % BWIN_SIZE); | |
| 70 | − } | |
| 71 | − | |
| 72 | − printk(KERN_WARNING "unable to establish PIO mapping for at" | |
| 73 | − " hub %d widget %d addr 0x%lx\n", | |
| 74 | − nasid, widget, xtalk_addr); | |
| 75 | − return 0; | |
| 76 | −} | |
| 77 | − | |
| 78 | − | |
| 79 | −/* | |
| 80 | − * hub_setup_prb(nasid, prbnum, credits, conveyor) | |
| 81 | − * | |
| 82 | − * Put a PRB into fire-and-forget mode if conveyor isn't set. Otherwise, | |
| 83 | − * put it into conveyor belt mode with the specified number of credits. | |
| 84 | − */ | |
| 85 | −static void hub_setup_prb(nasid_t nasid, int prbnum, int credits) | |
| 86 | −{ | |
| 87 | − union iprb_u prb; | |
| 88 | − int prb_offset; | |
| 89 | − | |
| 90 | − /* | |
| 91 | − * Get the current register value. | |
| 92 | − */ | |
| 93 | − prb_offset = IIO_IOPRB(prbnum); | |
| 94 | − prb.iprb_regval = REMOTE_HUB_L(nasid, prb_offset); | |
| 95 | − | |
| 96 | − /* | |
| 97 | − * Clear out some fields. | |
| 98 | − */ | |
| 99 | − prb.iprb_ovflow = 1; | |
| 100 | − prb.iprb_bnakctr = 0; | |
| 101 | − prb.iprb_anakctr = 0; | |
| 102 | − | |
| 103 | − /* | |
| 104 | − * Enable or disable fire-and-forget mode. | |
| 105 | − */ | |
| 106 | − prb.iprb_ff = force_fire_and_forget ? 1 : 0; | |
| 107 | − | |
| 108 | − /* | |
| 109 | − * Set the appropriate number of PIO credits for the widget. | |
| 110 | − */ | |
| 111 | − prb.iprb_xtalkctr = credits; | |
| 112 | − | |
| 113 | − /* | |
| 114 | − * Store the new value to the register. | |
| 115 | − */ | |
| 116 | − REMOTE_HUB_S(nasid, prb_offset, prb.iprb_regval); | |
| 117 | −} | |
| 118 | − | |
| 119 | −/** | |
| 120 | − * hub_set_piomode - set pio mode for a given hub | |
| 121 | − * | |
| 122 | − * @nasid: physical node ID for the hub in question | |
| 123 | − * | |
| 124 | − * Put the hub into either "PIO conveyor belt" mode or "fire-and-forget" mode. | |
| 125 | − * To do this, we have to make absolutely sure that no PIOs are in progress | |
| 126 | − * so we turn off access to all widgets for the duration of the function. | |
| 127 | − * | |
| 128 | − * XXX - This code should really check what kind of widget we're talking | |
| 129 | − * to. Bridges can only handle three requests, but XG will do more. | |
| 130 | − * How many can crossbow handle to widget 0? We're assuming 1. | |
| 131 | − * | |
| 132 | − * XXX - There is a bug in the crossbow that link reset PIOs do not | |
| 133 | − * return write responses. The easiest solution to this problem is to | |
| 134 | − * leave widget 0 (xbow) in fire-and-forget mode at all times. This | |
| 135 | − * only affects pio's to xbow registers, which should be rare. | |
| 136 | − **/ | |
| 137 | −static void hub_set_piomode(nasid_t nasid) | |
| 138 | −{ | |
| 139 | − u64 ii_iowa; | |
| 140 | − union hubii_wcr_u ii_wcr; | |
| 141 | − unsigned i; | |
| 142 | − | |
| 143 | − ii_iowa = REMOTE_HUB_L(nasid, IIO_OUTWIDGET_ACCESS); | |
| 144 | − REMOTE_HUB_S(nasid, IIO_OUTWIDGET_ACCESS, 0); | |
| 145 | − | |
| 146 | − ii_wcr.wcr_reg_value = REMOTE_HUB_L(nasid, IIO_WCR); | |
| 147 | − | |
| 148 | − if (ii_wcr.iwcr_dir_con) { | |
| 149 | − /* | |
| 150 | − * Assume a bridge here. | |
| 151 | − */ | |
| 152 | − hub_setup_prb(nasid, 0, 3); | |
| 153 | − } else { | |
| 154 | − /* | |
| 155 | − * Assume a crossbow here. | |
| 156 | − */ | |
| 157 | − hub_setup_prb(nasid, 0, 1); | |
| 158 | − } | |
| 159 | − | |
| 160 | − /* | |
| 161 | − * XXX - Here's where we should take the widget type into | |
| 162 | − * when account assigning credits. | |
| 163 | − */ | |
| 164 | − for (i = HUB_WIDGET_ID_MIN; i <= HUB_WIDGET_ID_MAX; i++) | |
| 165 | − hub_setup_prb(nasid, i, 3); | |
| 166 | − | |
| 167 | − REMOTE_HUB_S(nasid, IIO_OUTWIDGET_ACCESS, ii_iowa); | |
| 168 | −} | |
| 169 | − | |
| 170 | −/* | |
| 171 | − * hub_pio_init - PIO-related hub initialization | |
| 172 | − * | |
| 173 | − * @hub: hubinfo structure for our hub | |
| 174 | − */ | |
| 175 | −void hub_pio_init(nasid_t nasid) | |
| 176 | −{ | |
| 177 | − unsigned i; | |
| 178 | − | |
| 179 | − /* initialize big window piomaps for this hub */ | |
| 180 | − bitmap_zero(hub_data(nasid)->h_bigwin_used, HUB_NUM_BIG_WINDOW); | |
| 181 | − for (i = 0; i < HUB_NUM_BIG_WINDOW; i++) | |
| 182 | − IIO_ITTE_DISABLE(nasid, i); | |
| 183 | − | |
| 184 | − hub_set_piomode(nasid); | |
| 185 | −} | |
| @@ -23,6 +23,8 @@ · 22 unmodified lines | ||
| 23 | 23 | #include <asm/sn/intr.h> |
| 24 | 24 | #include <asm/sn/irq_alloc.h> |
| 25 | 25 | |
| 26 | +#include "ip27-common.h" | |
| 27 | + | |
| 26 | 28 | struct hub_irq_data { |
| 27 | 29 | u64 *irq_mask[2]; |
| 28 | 30 | cpuid_t cpu; |
| @@ -23,6 +23,7 @@ · 22 unmodified lines | ||
| 23 | 23 | #include <asm/page.h> |
| 24 | 24 | #include <asm/pgalloc.h> |
| 25 | 25 | #include <asm/sections.h> |
| 26 | +#include <asm/sgialib.h> | |
| 26 | 27 | |
| 27 | 28 | #include <asm/sn/arch.h> |
| 28 | 29 | #include <asm/sn/agent.h> |
| @@ -11,6 +11,8 @@ · 10 unmodified lines | ||
| 11 | 11 | #include <asm/sn/arch.h> |
| 12 | 12 | #include <asm/sn/agent.h> |
| 13 | 13 | |
| 14 | +#include "ip27-common.h" | |
| 15 | + | |
| 14 | 16 | #if 0 |
| 15 | 17 | #define NODE_NUM_CPUS(n) CNODE_NUM_CPUS(n) |
| 16 | 18 | #else |
| @@ -23,16 +25,7 @@ · 6 unmodified lines | ||
| 23 | 25 | typedef unsigned long machreg_t; |
| 24 | 26 | |
| 25 | 27 | static arch_spinlock_t nmi_lock = __ARCH_SPIN_LOCK_UNLOCKED; |
| 26 | − | |
| 27 | −/* | |
| 28 | − * Let's see what else we need to do here. Set up sp, gp? | |
| 29 | − */ | |
| 30 | −void nmi_dump(void) | |
| 31 | −{ | |
| 32 | − void cont_nmi_dump(void); | |
| 33 | − | |
| 34 | − cont_nmi_dump(); | |
| 35 | −} | |
| 28 | +static void nmi_dump(void); | |
| 36 | 29 | |
| 37 | 30 | void install_cpu_nmi_handler(int slice) |
| 38 | 31 | { |
| @@ -53,7 +46,7 @@ void install_cpu_nmi_handler(int slice) · 14 unmodified lines | ||
| 53 | 46 | * into the eframe format for the node under consideration. |
| 54 | 47 | */ |
| 55 | 48 | |
| 56 | −void nmi_cpu_eframe_save(nasid_t nasid, int slice) | |
| 49 | +static void nmi_cpu_eframe_save(nasid_t nasid, int slice) | |
| 57 | 50 | { |
| 58 | 51 | struct reg_struct *nr; |
| 59 | 52 | int i; |
| @@ -129,7 +122,7 @@ void nmi_cpu_eframe_save(nasid_t nasid, int slice) · 69 unmodified lines | ||
| 129 | 122 | pr_emerg("\n"); |
| 130 | 123 | } |
| 131 | 124 | |
| 132 | −void nmi_dump_hub_irq(nasid_t nasid, int slice) | |
| 125 | +static void nmi_dump_hub_irq(nasid_t nasid, int slice) | |
| 133 | 126 | { |
| 134 | 127 | u64 mask0, mask1, pend0, pend1; |
| 135 | 128 | |
| @@ -153,7 +146,7 @@ void nmi_dump_hub_irq(nasid_t nasid, int slice) · 17 unmodified lines | ||
| 153 | 146 | * Copy the cpu registers which have been saved in the IP27prom format |
| 154 | 147 | * into the eframe format for the node under consideration. |
| 155 | 148 | */ |
| 156 | −void nmi_node_eframe_save(nasid_t nasid) | |
| 149 | +static void nmi_node_eframe_save(nasid_t nasid) | |
| 157 | 150 | { |
| 158 | 151 | int slice; |
| 159 | 152 | |
| @@ -170,8 +163,7 @@ void nmi_node_eframe_save(nasid_t nasid) · 10 unmodified lines | ||
| 170 | 163 | /* |
| 171 | 164 | * Save the nmi cpu registers for all cpus in the system. |
| 172 | 165 | */ |
| 173 | −void | |
| 174 | −nmi_eframes_save(void) | |
| 166 | +static void nmi_eframes_save(void) | |
| 175 | 167 | { |
| 176 | 168 | nasid_t nasid; |
| 177 | 169 | |
| @@ -179,8 +171,7 @@ nmi_eframes_save(void) · 1 unmodified line | ||
| 179 | 171 | nmi_node_eframe_save(nasid); |
| 180 | 172 | } |
| 181 | 173 | |
| 182 | −void | |
| 183 | −cont_nmi_dump(void) | |
| 174 | +static void nmi_dump(void) | |
| 184 | 175 | { |
| 185 | 176 | #ifndef REAL_NMI_SIGNAL |
| 186 | 177 | static atomic_t nmied_cpus = ATOMIC_INIT(0); |
| @@ -3,6 +3,7 @@ · 2 unmodified lines | ||
| 3 | 3 | #include <linux/io.h> |
| 4 | 4 | |
| 5 | 5 | #include <asm/sn/ioc3.h> |
| 6 | +#include <asm/setup.h> | |
| 6 | 7 | |
| 7 | 8 | static inline struct ioc3_uartregs *console_uart(void) |
| 8 | 9 | { |
| @@ -14,6 +14,7 @@ · 13 unmodified lines | ||
| 14 | 14 | #include <linux/percpu.h> |
| 15 | 15 | #include <linux/memblock.h> |
| 16 | 16 | |
| 17 | +#include <asm/bootinfo.h> | |
| 17 | 18 | #include <asm/smp-ops.h> |
| 18 | 19 | #include <asm/sgialib.h> |
| 19 | 20 | #include <asm/time.h> |
| @@ -18,6 +18,8 @@ · 17 unmodified lines | ||
| 18 | 18 | #include <asm/ip32/crime.h> |
| 19 | 19 | #include <asm/ip32/mace.h> |
| 20 | 20 | |
| 21 | +#include "ip32-common.h" | |
| 22 | + | |
| 21 | 23 | struct sgi_crime __iomem *crime; |
| 22 | 24 | struct sgi_mace __iomem *mace; |
| 23 | 25 | |
| @@ -39,7 +41,7 @@ void __init crime_init(void) · 15 unmodified lines | ||
| 39 | 41 | id, rev, field, (unsigned long) CRIME_BASE); |
| 40 | 42 | } |
| 41 | 43 | |
| 42 | −irqreturn_t crime_memerr_intr(unsigned int irq, void *dev_id) | |
| 44 | +irqreturn_t crime_memerr_intr(int irq, void *dev_id) | |
| 43 | 45 | { |
| 44 | 46 | unsigned long stat, addr; |
| 45 | 47 | int fatal = 0; |
| @@ -90,7 +92,7 @@ irqreturn_t crime_memerr_intr(unsigned int irq, void *dev_id) · 44 unmodified lines | ||
| 90 | 92 | return IRQ_HANDLED; |
| 91 | 93 | } |
| 92 | 94 | |
| 93 | −irqreturn_t crime_cpuerr_intr(unsigned int irq, void *dev_id) | |
| 95 | +irqreturn_t crime_cpuerr_intr(int irq, void *dev_id) | |
| 94 | 96 | { |
| 95 | 97 | unsigned long stat = crime->cpu_error_stat & CRIME_CPU_ERROR_MASK; |
| 96 | 98 | unsigned long addr = crime->cpu_error_addr & CRIME_CPU_ERROR_ADDR_MASK; |
| @@ -18,6 +18,8 @@ · 17 unmodified lines | ||
| 18 | 18 | #include <asm/ptrace.h> |
| 19 | 19 | #include <asm/tlbdebug.h> |
| 20 | 20 | |
| 21 | +#include "ip32-common.h" | |
| 22 | + | |
| 21 | 23 | static int ip32_be_handler(struct pt_regs *regs, int is_fixup) |
| 22 | 24 | { |
| 23 | 25 | int data = regs->cp0_cause & 4; |
| @@ -0,0 +1,15 @@ | ||
| 1 | +/* SPDX-License-Identifier: GPL-2.0-only */ | |
| 2 | + | |
| 3 | +#ifndef __IP32_COMMON_H | |
| 4 | +#define __IP32_COMMON_H | |
| 5 | + | |
| 6 | +#include <linux/init.h> | |
| 7 | +#include <linux/interrupt.h> | |
| 8 | + | |
| 9 | +void __init crime_init(void); | |
| 10 | +irqreturn_t crime_memerr_intr(int irq, void *dev_id); | |
| 11 | +irqreturn_t crime_cpuerr_intr(int irq, void *dev_id); | |
| 12 | +void __init ip32_be_init(void); | |
| 13 | +void ip32_prepare_poweroff(void); | |
| 14 | + | |
| 15 | +#endif /* __IP32_COMMON_H */ | |
| @@ -28,6 +28,8 @@ · 27 unmodified lines | ||
| 28 | 28 | #include <asm/ip32/mace.h> |
| 29 | 29 | #include <asm/ip32/ip32_ints.h> |
| 30 | 30 | |
| 31 | +#include "ip32-common.h" | |
| 32 | + | |
| 31 | 33 | /* issue a PIO read to make sure no PIO writes are pending */ |
| 32 | 34 | static inline void flush_crime_bus(void) |
| 33 | 35 | { |
| @@ -107,10 +109,6 @@ static inline void flush_mace_bus(void) · 73 unmodified lines | ||
| 107 | 109 | * is quite different anyway. |
| 108 | 110 | */ |
| 109 | 111 | |
| 110 | −/* Some initial interrupts to set up */ | |
| 111 | −extern irqreturn_t crime_memerr_intr(int irq, void *dev_id); | |
| 112 | −extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id); | |
| 113 | − | |
| 114 | 112 | /* |
| 115 | 113 | * This is for pure CRIME interrupts - ie not MACE. The advantage? |
| 116 | 114 | * We get to split the register in half and do faster lookups. |
| @@ -15,6 +15,7 @@ · 14 unmodified lines | ||
| 15 | 15 | #include <asm/ip32/crime.h> |
| 16 | 16 | #include <asm/bootinfo.h> |
| 17 | 17 | #include <asm/page.h> |
| 18 | +#include <asm/sgialib.h> | |
| 18 | 19 | |
| 19 | 20 | extern void crime_init(void); |
| 20 | 21 | |
| @@ -29,6 +29,8 @@ · 28 unmodified lines | ||
| 29 | 29 | #include <asm/ip32/crime.h> |
| 30 | 30 | #include <asm/ip32/ip32_ints.h> |
| 31 | 31 | |
| 32 | +#include "ip32-common.h" | |
| 33 | + | |
| 32 | 34 | #define POWERDOWN_TIMEOUT 120 |
| 33 | 35 | /* |
| 34 | 36 | * Blink frequency during reboot grace period and when panicked. |
| @@ -26,8 +26,7 @@ · 25 unmodified lines | ||
| 26 | 26 | #include <asm/ip32/mace.h> |
| 27 | 27 | #include <asm/ip32/ip32_ints.h> |
| 28 | 28 | |
| 29 | −extern void ip32_be_init(void); | |
| 30 | −extern void crime_init(void); | |
| 29 | +#include "ip32-common.h" | |
| 31 | 30 | |
| 32 | 31 | #ifdef CONFIG_SGI_O2MACE_ETH |
| 33 | 32 | /* |
| @@ -25,7 +25,6 @@ config PARISC · 24 unmodified lines | ||
| 25 | 25 | select RTC_DRV_GENERIC |
| 26 | 26 | select INIT_ALL_POSSIBLE |
| 27 | 27 | select BUG |
| 28 | − select BUILDTIME_TABLE_SORT | |
| 29 | 28 | select HAVE_KERNEL_UNCOMPRESSED |
| 30 | 29 | select HAVE_PCI |
| 31 | 30 | select HAVE_PERF_EVENTS |
| @@ -50,12 +50,12 @@ export CROSS32CC · 49 unmodified lines | ||
| 50 | 50 | |
| 51 | 51 | # Set default cross compiler for kernel build |
| 52 | 52 | ifdef cross_compiling |
| 53 | − ifeq ($(CROSS_COMPILE),) | |
| 53 | + ifeq ($(CROSS_COMPILE),) | |
| 54 | 54 | CC_SUFFIXES = linux linux-gnu unknown-linux-gnu suse-linux |
| 55 | 55 | CROSS_COMPILE := $(call cc-cross-prefix, \ |
| 56 | 56 | $(foreach a,$(CC_ARCHES), \ |
| 57 | 57 | $(foreach s,$(CC_SUFFIXES),$(a)-$(s)-))) |
| 58 | − endif | |
| 58 | + endif | |
| 59 | 59 | endif |
| 60 | 60 | |
| 61 | 61 | ifdef CONFIG_DYNAMIC_FTRACE |
| @@ -576,6 +576,7 @@ · 575 unmodified lines | ||
| 576 | 576 | .section __ex_table,"aw" ! \ |
| 577 | 577 | .align 4 ! \ |
| 578 | 578 | .word (fault_addr - .), (except_addr - .) ! \ |
| 579 | + or %r0,%r0,%r0 ! \ | |
| 579 | 580 | .previous |
| 580 | 581 | |
| 581 | 582 | |
| @@ -0,0 +1,64 @@ | ||
| 1 | +/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | +#ifndef __PARISC_EXTABLE_H | |
| 3 | +#define __PARISC_EXTABLE_H | |
| 4 | + | |
| 5 | +#include <asm/ptrace.h> | |
| 6 | +#include <linux/compiler.h> | |
| 7 | + | |
| 8 | +/* | |
| 9 | + * The exception table consists of three addresses: | |
| 10 | + * | |
| 11 | + * - A relative address to the instruction that is allowed to fault. | |
| 12 | + * - A relative address at which the program should continue (fixup routine) | |
| 13 | + * - An asm statement which specifies which CPU register will | |
| 14 | + * receive -EFAULT when an exception happens if the lowest bit in | |
| 15 | + * the fixup address is set. | |
| 16 | + * | |
| 17 | + * Note: The register specified in the err_opcode instruction will be | |
| 18 | + * modified at runtime if a fault happens. Register %r0 will be ignored. | |
| 19 | + * | |
| 20 | + * Since relative addresses are used, 32bit values are sufficient even on | |
| 21 | + * 64bit kernel. | |
| 22 | + */ | |
| 23 | + | |
| 24 | +struct pt_regs; | |
| 25 | +int fixup_exception(struct pt_regs *regs); | |
| 26 | + | |
| 27 | +#define ARCH_HAS_RELATIVE_EXTABLE | |
| 28 | +struct exception_table_entry { | |
| 29 | + int insn; /* relative address of insn that is allowed to fault. */ | |
| 30 | + int fixup; /* relative address of fixup routine */ | |
| 31 | + int err_opcode; /* sample opcode with register which holds error code */ | |
| 32 | +}; | |
| 33 | + | |
| 34 | +#define ASM_EXCEPTIONTABLE_ENTRY( fault_addr, except_addr, opcode )\ | |
| 35 | + ".section __ex_table,\"aw\"\n" \ | |
| 36 | + ".align 4\n" \ | |
| 37 | + ".word (" #fault_addr " - .), (" #except_addr " - .)\n" \ | |
| 38 | + opcode "\n" \ | |
| 39 | + ".previous\n" | |
| 40 | + | |
| 41 | +/* | |
| 42 | + * ASM_EXCEPTIONTABLE_ENTRY_EFAULT() creates a special exception table entry | |
| 43 | + * (with lowest bit set) for which the fault handler in fixup_exception() will | |
| 44 | + * load -EFAULT on fault into the register specified by the err_opcode instruction, | |
| 45 | + * and zeroes the target register in case of a read fault in get_user(). | |
| 46 | + */ | |
| 47 | +#define ASM_EXCEPTIONTABLE_VAR(__err_var) \ | |
| 48 | + int __err_var = 0 | |
| 49 | +#define ASM_EXCEPTIONTABLE_ENTRY_EFAULT( fault_addr, except_addr, register )\ | |
| 50 | + ASM_EXCEPTIONTABLE_ENTRY( fault_addr, except_addr + 1, "or %%r0,%%r0," register) | |
| 51 | + | |
| 52 | +static inline void swap_ex_entry_fixup(struct exception_table_entry *a, | |
| 53 | + struct exception_table_entry *b, | |
| 54 | + struct exception_table_entry tmp, | |
| 55 | + int delta) | |
| 56 | +{ | |
| 57 | + a->fixup = b->fixup + delta; | |
| 58 | + b->fixup = tmp.fixup - delta; | |
| 59 | + a->err_opcode = b->err_opcode; | |
| 60 | + b->err_opcode = tmp.err_opcode; | |
| 61 | +} | |
| 62 | +#define swap_ex_entry_fixup swap_ex_entry_fixup | |
| 63 | + | |
| 64 | +#endif | |
| @@ -8,7 +8,8 @@ · 7 unmodified lines | ||
| 8 | 8 | "copy %%r0,%0\n" \ |
| 9 | 9 | "8:\tlpa %%r0(%1),%0\n" \ |
| 10 | 10 | "9:\n" \ |
| 11 | − ASM_EXCEPTIONTABLE_ENTRY(8b, 9b) \ | |
| 11 | + ASM_EXCEPTIONTABLE_ENTRY(8b, 9b, \ | |
| 12 | + "or %%r0,%%r0,%%r0") \ | |
| 12 | 13 | : "=&r" (pa) \ |
| 13 | 14 | : "r" (va) \ |
| 14 | 15 | : "memory" \ |
| @@ -22,7 +23,8 @@ · 7 unmodified lines | ||
| 22 | 23 | "copy %%r0,%0\n" \ |
| 23 | 24 | "8:\tlpa %%r0(%%sr3,%1),%0\n" \ |
| 24 | 25 | "9:\n" \ |
| 25 | − ASM_EXCEPTIONTABLE_ENTRY(8b, 9b) \ | |
| 26 | + ASM_EXCEPTIONTABLE_ENTRY(8b, 9b, \ | |
| 27 | + "or %%r0,%%r0,%%r0") \ | |
| 26 | 28 | : "=&r" (pa) \ |
| 27 | 29 | : "r" (va) \ |
| 28 | 30 | : "memory" \ |
| @@ -7,6 +7,7 @@ · 6 unmodified lines | ||
| 7 | 7 | */ |
| 8 | 8 | #include <asm/page.h> |
| 9 | 9 | #include <asm/cache.h> |
| 10 | +#include <asm/extable.h> | |
| 10 | 11 | |
| 11 | 12 | #include <linux/bug.h> |
| 12 | 13 | #include <linux/string.h> |
| @@ -26,37 +27,6 @@ · 13 unmodified lines | ||
| 26 | 27 | #define STD_USER(sr, x, ptr) __put_user_asm(sr, "std", x, ptr) |
| 27 | 28 | #endif |
| 28 | 29 | |
| 29 | −/* | |
| 30 | − * The exception table contains two values: the first is the relative offset to | |
| 31 | − * the address of the instruction that is allowed to fault, and the second is | |
| 32 | − * the relative offset to the address of the fixup routine. Since relative | |
| 33 | − * addresses are used, 32bit values are sufficient even on 64bit kernel. | |
| 34 | − */ | |
| 35 | − | |
| 36 | −#define ARCH_HAS_RELATIVE_EXTABLE | |
| 37 | −struct exception_table_entry { | |
| 38 | − int insn; /* relative address of insn that is allowed to fault. */ | |
| 39 | − int fixup; /* relative address of fixup routine */ | |
| 40 | −}; | |
| 41 | − | |
| 42 | −#define ASM_EXCEPTIONTABLE_ENTRY( fault_addr, except_addr )\ | |
| 43 | − ".section __ex_table,\"aw\"\n" \ | |
| 44 | − ".align 4\n" \ | |
| 45 | − ".word (" #fault_addr " - .), (" #except_addr " - .)\n\t" \ | |
| 46 | − ".previous\n" | |
| 47 | − | |
| 48 | −/* | |
| 49 | − * ASM_EXCEPTIONTABLE_ENTRY_EFAULT() creates a special exception table entry | |
| 50 | − * (with lowest bit set) for which the fault handler in fixup_exception() will | |
| 51 | − * load -EFAULT into %r29 for a read or write fault, and zeroes the target | |
| 52 | − * register in case of a read fault in get_user(). | |
| 53 | − */ | |
| 54 | −#define ASM_EXCEPTIONTABLE_REG 29 | |
| 55 | −#define ASM_EXCEPTIONTABLE_VAR(__variable) \ | |
| 56 | − register long __variable __asm__ ("r29") = 0 | |
| 57 | −#define ASM_EXCEPTIONTABLE_ENTRY_EFAULT( fault_addr, except_addr )\ | |
| 58 | − ASM_EXCEPTIONTABLE_ENTRY( fault_addr, except_addr + 1) | |
| 59 | − | |
| 60 | 30 | #define __get_user_internal(sr, val, ptr) \ |
| 61 | 31 | ({ \ |
| 62 | 32 | ASM_EXCEPTIONTABLE_VAR(__gu_err); \ |
| @@ -83,7 +53,7 @@ struct exception_table_entry { · 20 unmodified lines | ||
| 83 | 53 | \ |
| 84 | 54 | __asm__("1: " ldx " 0(%%sr%2,%3),%0\n" \ |
| 85 | 55 | "9:\n" \ |
| 86 | − ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 9b) \ | |
| 56 | + ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 9b, "%1") \ | |
| 87 | 57 | : "=r"(__gu_val), "+r"(__gu_err) \ |
| 88 | 58 | : "i"(sr), "r"(ptr)); \ |
| 89 | 59 | \ |
| @@ -115,8 +85,8 @@ struct exception_table_entry { · 25 unmodified lines | ||
| 115 | 85 | "1: ldw 0(%%sr%2,%3),%0\n" \ |
| 116 | 86 | "2: ldw 4(%%sr%2,%3),%R0\n" \ |
| 117 | 87 | "9:\n" \ |
| 118 | − ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 9b) \ | |
| 119 | − ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 9b) \ | |
| 88 | + ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 9b, "%1") \ | |
| 89 | + ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 9b, "%1") \ | |
| 120 | 90 | : "=&r"(__gu_tmp.l), "+r"(__gu_err) \ |
| 121 | 91 | : "i"(sr), "r"(ptr)); \ |
| 122 | 92 | \ |
| @@ -174,7 +144,7 @@ struct exception_table_entry { · 51 unmodified lines | ||
| 174 | 144 | __asm__ __volatile__ ( \ |
| 175 | 145 | "1: " stx " %1,0(%%sr%2,%3)\n" \ |
| 176 | 146 | "9:\n" \ |
| 177 | − ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 9b) \ | |
| 147 | + ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 9b, "%0") \ | |
| 178 | 148 | : "+r"(__pu_err) \ |
| 179 | 149 | : "r"(x), "i"(sr), "r"(ptr)) |
| 180 | 150 | |
| @@ -186,15 +156,14 @@ struct exception_table_entry { · 5 unmodified lines | ||
| 186 | 156 | "1: stw %1,0(%%sr%2,%3)\n" \ |
| 187 | 157 | "2: stw %R1,4(%%sr%2,%3)\n" \ |
| 188 | 158 | "9:\n" \ |
| 189 | − ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 9b) \ | |
| 190 | − ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 9b) \ | |
| 159 | + ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 9b, "%0") \ | |
| 160 | + ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 9b, "%0") \ | |
| 191 | 161 | : "+r"(__pu_err) \ |
| 192 | 162 | : "r"(__val), "i"(sr), "r"(ptr)); \ |
| 193 | 163 | } while (0) |
| 194 | 164 | |
| 195 | 165 | #endif /* !defined(CONFIG_64BIT) */ |
| 196 | 166 | |
| 197 | − | |
| 198 | 167 | /* |
| 199 | 168 | * Complex access routines -- external declarations |
| 200 | 169 | */ |
| @@ -216,7 +185,4 @@ unsigned long __must_check raw_copy_from_user(void *dst, const void __user *src, · 15 unmodified lines | ||
| 216 | 185 | #define INLINE_COPY_TO_USER |
| 217 | 186 | #define INLINE_COPY_FROM_USER |
| 218 | 187 | |
| 219 | −struct pt_regs; | |
| 220 | −int fixup_exception(struct pt_regs *regs); | |
| 221 | − | |
| 222 | 188 | #endif /* __PARISC_UACCESS_H */ |
| @@ -58,7 +58,7 @@ int pa_serialize_tlb_flushes __ro_after_init; · 57 unmodified lines | ||
| 58 | 58 | |
| 59 | 59 | struct pdc_cache_info cache_info __ro_after_init; |
| 60 | 60 | #ifndef CONFIG_PA20 |
| 61 | −struct pdc_btlb_info btlb_info __ro_after_init; | |
| 61 | +struct pdc_btlb_info btlb_info; | |
| 62 | 62 | #endif |
| 63 | 63 | |
| 64 | 64 | DEFINE_STATIC_KEY_TRUE(parisc_has_cache); |
| @@ -264,6 +264,10 @@ parisc_cache_init(void) · 199 unmodified lines | ||
| 264 | 264 | icache_stride = CAFL_STRIDE(cache_info.ic_conf); |
| 265 | 265 | #undef CAFL_STRIDE |
| 266 | 266 | |
| 267 | + /* stride needs to be non-zero, otherwise cache flushes will not work */ | |
| 268 | + WARN_ON(cache_info.dc_size && dcache_stride == 0); | |
| 269 | + WARN_ON(cache_info.ic_size && icache_stride == 0); | |
| 270 | + | |
| 267 | 271 | if ((boot_cpu_data.pdc.capabilities & PDC_MODEL_NVA_MASK) == |
| 268 | 272 | PDC_MODEL_NVA_UNSUPPORTED) { |
| 269 | 273 | printk(KERN_WARNING "parisc_cache_init: Only equivalent aliasing supported!\n"); |
| @@ -850,7 +854,7 @@ SYSCALL_DEFINE3(cacheflush, unsigned long, addr, unsigned long, bytes, · 580 unmodified lines | ||
| 850 | 854 | #endif |
| 851 | 855 | " fic,m %3(%4,%0)\n" |
| 852 | 856 | "2: sync\n" |
| 853 | − ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 2b) | |
| 857 | + ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 2b, "%1") | |
| 854 | 858 | : "+r" (start), "+r" (error) |
| 855 | 859 | : "r" (end), "r" (dcache_stride), "i" (SR_USER)); |
| 856 | 860 | } |
| @@ -865,7 +869,7 @@ SYSCALL_DEFINE3(cacheflush, unsigned long, addr, unsigned long, bytes, · 8 unmodified lines | ||
| 865 | 869 | #endif |
| 866 | 870 | " fdc,m %3(%4,%0)\n" |
| 867 | 871 | "2: sync\n" |
| 868 | − ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 2b) | |
| 872 | + ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 2b, "%1") | |
| 869 | 873 | : "+r" (start), "+r" (error) |
| 870 | 874 | : "r" (end), "r" (icache_stride), "i" (SR_USER)); |
| 871 | 875 | } |
| @@ -742,7 +742,7 @@ parse_tree_node(struct device *parent, int index, struct hardware_path *modpath) · 741 unmodified lines | ||
| 742 | 742 | }; |
| 743 | 743 | |
| 744 | 744 | if (device_for_each_child(parent, &recurse_data, descend_children)) |
| 745 | − { /* nothing */ }; | |
| 745 | + { /* nothing */ } | |
| 746 | 746 | |
| 747 | 747 | return d.dev; |
| 748 | 748 | } |
| @@ -1004,6 +1004,9 @@ static __init int qemu_print_iodc_data(struct device *lin_dev, void *data) · 255 unmodified lines | ||
| 1004 | 1004 | |
| 1005 | 1005 | pr_info("\n"); |
| 1006 | 1006 | |
| 1007 | + /* Prevent hung task messages when printing on serial console */ | |
| 1008 | + cond_resched(); | |
| 1009 | + | |
| 1007 | 1010 | pr_info("#define HPA_%08lx_DESCRIPTION \"%s\"\n", |
| 1008 | 1011 | hpa, parisc_hardware_description(&dev->id)); |
| 1009 | 1012 | |
| @@ -120,8 +120,8 @@ static int emulate_ldh(struct pt_regs *regs, int toreg) · 119 unmodified lines | ||
| 120 | 120 | "2: ldbs 1(%%sr1,%3), %0\n" |
| 121 | 121 | " depw %2, 23, 24, %0\n" |
| 122 | 122 | "3: \n" |
| 123 | − ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b) | |
| 124 | − ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b) | |
| 123 | + ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%1") | |
| 124 | + ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%1") | |
| 125 | 125 | : "+r" (val), "+r" (ret), "=&r" (temp1) |
| 126 | 126 | : "r" (saddr), "r" (regs->isr) ); |
| 127 | 127 | |
| @@ -152,8 +152,8 @@ static int emulate_ldw(struct pt_regs *regs, int toreg, int flop) · 24 unmodified lines | ||
| 152 | 152 | " mtctl %2,11\n" |
| 153 | 153 | " vshd %0,%3,%0\n" |
| 154 | 154 | "3: \n" |
| 155 | − ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b) | |
| 156 | − ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b) | |
| 155 | + ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%1") | |
| 156 | + ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%1") | |
| 157 | 157 | : "+r" (val), "+r" (ret), "=&r" (temp1), "=&r" (temp2) |
| 158 | 158 | : "r" (saddr), "r" (regs->isr) ); |
| 159 | 159 | |
| @@ -189,8 +189,8 @@ static int emulate_ldd(struct pt_regs *regs, int toreg, int flop) · 29 unmodified lines | ||
| 189 | 189 | " mtsar %%r19\n" |
| 190 | 190 | " shrpd %0,%%r20,%%sar,%0\n" |
| 191 | 191 | "3: \n" |
| 192 | − ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b) | |
| 193 | − ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b) | |
| 192 | + ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%1") | |
| 193 | + ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%1") | |
| 194 | 194 | : "=r" (val), "+r" (ret) |
| 195 | 195 | : "0" (val), "r" (saddr), "r" (regs->isr) |
| 196 | 196 | : "r19", "r20" ); |
| @@ -209,9 +209,9 @@ static int emulate_ldd(struct pt_regs *regs, int toreg, int flop) · 12 unmodified lines | ||
| 209 | 209 | " vshd %0,%R0,%0\n" |
| 210 | 210 | " vshd %R0,%4,%R0\n" |
| 211 | 211 | "4: \n" |
| 212 | − ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 4b) | |
| 213 | − ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 4b) | |
| 214 | − ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 4b) | |
| 212 | + ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 4b, "%1") | |
| 213 | + ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 4b, "%1") | |
| 214 | + ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 4b, "%1") | |
| 215 | 215 | : "+r" (val), "+r" (ret), "+r" (saddr), "=&r" (shift), "=&r" (temp1) |
| 216 | 216 | : "r" (regs->isr) ); |
| 217 | 217 | } |
| @@ -244,8 +244,8 @@ static int emulate_sth(struct pt_regs *regs, int frreg) · 26 unmodified lines | ||
| 244 | 244 | "1: stb %1, 0(%%sr1, %3)\n" |
| 245 | 245 | "2: stb %2, 1(%%sr1, %3)\n" |
| 246 | 246 | "3: \n" |
| 247 | − ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b) | |
| 248 | − ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b) | |
| 247 | + ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%0") | |
| 248 | + ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%0") | |
| 249 | 249 | : "+r" (ret), "=&r" (temp1) |
| 250 | 250 | : "r" (val), "r" (regs->ior), "r" (regs->isr) ); |
| 251 | 251 | |
| @@ -285,8 +285,8 @@ static int emulate_stw(struct pt_regs *regs, int frreg, int flop) · 33 unmodified lines | ||
| 285 | 285 | " stw %%r20,0(%%sr1,%2)\n" |
| 286 | 286 | " stw %%r21,4(%%sr1,%2)\n" |
| 287 | 287 | "3: \n" |
| 288 | − ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b) | |
| 289 | − ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b) | |
| 288 | + ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%0") | |
| 289 | + ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%0") | |
| 290 | 290 | : "+r" (ret) |
| 291 | 291 | : "r" (val), "r" (regs->ior), "r" (regs->isr) |
| 292 | 292 | : "r19", "r20", "r21", "r22", "r1" ); |
| @@ -329,10 +329,10 @@ static int emulate_std(struct pt_regs *regs, int frreg, int flop) · 36 unmodified lines | ||
| 329 | 329 | "3: std %%r20,0(%%sr1,%2)\n" |
| 330 | 330 | "4: std %%r21,8(%%sr1,%2)\n" |
| 331 | 331 | "5: \n" |
| 332 | − ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 5b) | |
| 333 | − ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 5b) | |
| 334 | − ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 5b) | |
| 335 | − ASM_EXCEPTIONTABLE_ENTRY_EFAULT(4b, 5b) | |
| 332 | + ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 5b, "%0") | |
| 333 | + ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 5b, "%0") | |
| 334 | + ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 5b, "%0") | |
| 335 | + ASM_EXCEPTIONTABLE_ENTRY_EFAULT(4b, 5b, "%0") | |
| 336 | 336 | : "+r" (ret) |
| 337 | 337 | : "r" (val), "r" (regs->ior), "r" (regs->isr) |
| 338 | 338 | : "r19", "r20", "r21", "r22", "r1" ); |
| @@ -357,11 +357,11 @@ static int emulate_std(struct pt_regs *regs, int frreg, int flop) · 18 unmodified lines | ||
| 357 | 357 | "4: stw %%r1,4(%%sr1,%2)\n" |
| 358 | 358 | "5: stw %R1,8(%%sr1,%2)\n" |
| 359 | 359 | "6: \n" |
| 360 | − ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 6b) | |
| 361 | − ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 6b) | |
| 362 | − ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 6b) | |
| 363 | − ASM_EXCEPTIONTABLE_ENTRY_EFAULT(4b, 6b) | |
| 364 | − ASM_EXCEPTIONTABLE_ENTRY_EFAULT(5b, 6b) | |
| 360 | + ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 6b, "%0") | |
| 361 | + ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 6b, "%0") | |
| 362 | + ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 6b, "%0") | |
| 363 | + ASM_EXCEPTIONTABLE_ENTRY_EFAULT(4b, 6b, "%0") | |
| 364 | + ASM_EXCEPTIONTABLE_ENTRY_EFAULT(5b, 6b, "%0") | |
| 365 | 365 | : "+r" (ret) |
| 366 | 366 | : "r" (val), "r" (regs->ior), "r" (regs->isr) |
| 367 | 367 | : "r19", "r20", "r21", "r1" ); |
| @@ -127,7 +127,7 @@ SECTIONS · 126 unmodified lines | ||
| 127 | 127 | } |
| 128 | 128 | #endif |
| 129 | 129 | |
| 130 | − RO_DATA(8) | |
| 130 | + RO_DATA(PAGE_SIZE) | |
| 131 | 131 | |
| 132 | 132 | /* unwind info */ |
| 133 | 133 | . = ALIGN(4); |
| @@ -150,11 +150,16 @@ int fixup_exception(struct pt_regs *regs) · 149 unmodified lines | ||
| 150 | 150 | * Fix up get_user() and put_user(). |
| 151 | 151 | * ASM_EXCEPTIONTABLE_ENTRY_EFAULT() sets the least-significant |
| 152 | 152 | * bit in the relative address of the fixup routine to indicate |
| 153 | − * that gr[ASM_EXCEPTIONTABLE_REG] should be loaded with | |
| 154 | − * -EFAULT to report a userspace access error. | |
| 153 | + * that the register encoded in the "or %r0,%r0,register" | |
| 154 | + * opcode should be loaded with -EFAULT to report a userspace | |
| 155 | + * access error. | |
| 155 | 156 | */ |
| 156 | 157 | if (fix->fixup & 1) { |
| 157 | − regs->gr[ASM_EXCEPTIONTABLE_REG] = -EFAULT; | |
| 158 | + int fault_error_reg = fix->err_opcode & 0x1f; | |
| 159 | + if (!WARN_ON(!fault_error_reg)) | |
| 160 | + regs->gr[fault_error_reg] = -EFAULT; | |
| 161 | + pr_debug("Unalignment fixup of register %d at %pS\n", | |
| 162 | + fault_error_reg, (void*)regs->iaoq[0]); | |
| 158 | 163 | |
| 159 | 164 | /* zero target register for get_user() */ |
| 160 | 165 | if (parisc_acctyp(0, regs->iir) == VM_READ) { |
| @@ -1287,20 +1287,20 @@ spapr_tce_platform_iommu_attach_dev(struct iommu_domain *platform_domain, · 1286 unmodified lines | ||
| 1287 | 1287 | struct iommu_domain *domain = iommu_get_domain_for_dev(dev); |
| 1288 | 1288 | struct iommu_group *grp = iommu_group_get(dev); |
| 1289 | 1289 | struct iommu_table_group *table_group; |
| 1290 | − int ret = -EINVAL; | |
| 1291 | 1290 | |
| 1292 | 1291 | /* At first attach the ownership is already set */ |
| 1293 | 1292 | if (!domain) |
| 1294 | 1293 | return 0; |
| 1295 | 1294 | |
| 1296 | − if (!grp) | |
| 1297 | − return -ENODEV; | |
| 1298 | − | |
| 1299 | 1295 | table_group = iommu_group_get_iommudata(grp); |
| 1300 | − ret = table_group->ops->take_ownership(table_group); | |
| 1296 | + /* | |
| 1297 | + * The domain being set to PLATFORM from earlier | |
| 1298 | + * BLOCKED. The table_group ownership has to be released. | |
| 1299 | + */ | |
| 1300 | + table_group->ops->release_ownership(table_group); | |
| 1301 | 1301 | iommu_group_put(grp); |
| 1302 | 1302 | |
| 1303 | − return ret; | |
| 1303 | + return 0; | |
| 1304 | 1304 | } |
| 1305 | 1305 | |
| 1306 | 1306 | static const struct iommu_domain_ops spapr_tce_platform_domain_ops = { |
| @@ -1312,13 +1312,32 @@ static struct iommu_domain spapr_tce_platform_domain = { · 5 unmodified lines | ||
| 1312 | 1312 | .ops = &spapr_tce_platform_domain_ops, |
| 1313 | 1313 | }; |
| 1314 | 1314 | |
| 1315 | −static struct iommu_domain spapr_tce_blocked_domain = { | |
| 1316 | − .type = IOMMU_DOMAIN_BLOCKED, | |
| 1315 | +static int | |
| 1316 | +spapr_tce_blocked_iommu_attach_dev(struct iommu_domain *platform_domain, | |
| 1317 | + struct device *dev) | |
| 1318 | +{ | |
| 1319 | + struct iommu_group *grp = iommu_group_get(dev); | |
| 1320 | + struct iommu_table_group *table_group; | |
| 1321 | + int ret = -EINVAL; | |
| 1322 | + | |
| 1317 | 1323 | /* |
| 1318 | 1324 | * FIXME: SPAPR mixes blocked and platform behaviors, the blocked domain |
| 1319 | 1325 | * also sets the dma_api ops |
| 1320 | 1326 | */ |
| 1321 | − .ops = &spapr_tce_platform_domain_ops, | |
| 1327 | + table_group = iommu_group_get_iommudata(grp); | |
| 1328 | + ret = table_group->ops->take_ownership(table_group); | |
| 1329 | + iommu_group_put(grp); | |
| 1330 | + | |
| 1331 | + return ret; | |
| 1332 | +} | |
| 1333 | + | |
| 1334 | +static const struct iommu_domain_ops spapr_tce_blocked_domain_ops = { | |
| 1335 | + .attach_dev = spapr_tce_blocked_iommu_attach_dev, | |
| 1336 | +}; | |
| 1337 | + | |
| 1338 | +static struct iommu_domain spapr_tce_blocked_domain = { | |
| 1339 | + .type = IOMMU_DOMAIN_BLOCKED, | |
| 1340 | + .ops = &spapr_tce_blocked_domain_ops, | |
| 1322 | 1341 | }; |
| 1323 | 1342 | |
| 1324 | 1343 | static bool spapr_tce_iommu_capable(struct device *dev, enum iommu_cap cap) |
| @@ -67,6 +67,7 @@ config PS3_VUART · 66 unmodified lines | ||
| 67 | 67 | config PS3_PS3AV |
| 68 | 68 | depends on PPC_PS3 |
| 69 | 69 | tristate "PS3 AV settings driver" if PS3_ADVANCED |
| 70 | + select VIDEO | |
| 70 | 71 | select PS3_VUART |
| 71 | 72 | default y |
| 72 | 73 | help |
| @@ -93,144 +93,160 @@ · 92 unmodified lines | ||
| 93 | 93 | <&cpu63_intc 3>; |
| 94 | 94 | }; |
| 95 | 95 | |
| 96 | − clint_mtimer0: timer@70ac000000 { | |
| 96 | + clint_mtimer0: timer@70ac004000 { | |
| 97 | 97 | compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; |
| 98 | − reg = <0x00000070 0xac000000 0x00000000 0x00007ff8>; | |
| 98 | + reg = <0x00000070 0xac004000 0x00000000 0x0000c000>; | |
| 99 | + reg-names = "mtimecmp"; | |
| 99 | 100 | interrupts-extended = <&cpu0_intc 7>, |
| 100 | 101 | <&cpu1_intc 7>, |
| 101 | 102 | <&cpu2_intc 7>, |
| 102 | 103 | <&cpu3_intc 7>; |
| 103 | 104 | }; |
| 104 | 105 | |
| 105 | − clint_mtimer1: timer@70ac010000 { | |
| 106 | + clint_mtimer1: timer@70ac014000 { | |
| 106 | 107 | compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; |
| 107 | − reg = <0x00000070 0xac010000 0x00000000 0x00007ff8>; | |
| 108 | + reg = <0x00000070 0xac014000 0x00000000 0x0000c000>; | |
| 109 | + reg-names = "mtimecmp"; | |
| 108 | 110 | interrupts-extended = <&cpu4_intc 7>, |
| 109 | 111 | <&cpu5_intc 7>, |
| 110 | 112 | <&cpu6_intc 7>, |
| 111 | 113 | <&cpu7_intc 7>; |
| 112 | 114 | }; |
| 113 | 115 | |
| 114 | − clint_mtimer2: timer@70ac020000 { | |
| 116 | + clint_mtimer2: timer@70ac024000 { | |
| 115 | 117 | compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; |
| 116 | − reg = <0x00000070 0xac020000 0x00000000 0x00007ff8>; | |
| 118 | + reg = <0x00000070 0xac024000 0x00000000 0x0000c000>; | |
| 119 | + reg-names = "mtimecmp"; | |
| 117 | 120 | interrupts-extended = <&cpu8_intc 7>, |
| 118 | 121 | <&cpu9_intc 7>, |
| 119 | 122 | <&cpu10_intc 7>, |
| 120 | 123 | <&cpu11_intc 7>; |
| 121 | 124 | }; |
| 122 | 125 | |
| 123 | − clint_mtimer3: timer@70ac030000 { | |
| 126 | + clint_mtimer3: timer@70ac034000 { | |
| 124 | 127 | compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; |
| 125 | − reg = <0x00000070 0xac030000 0x00000000 0x00007ff8>; | |
| 128 | + reg = <0x00000070 0xac034000 0x00000000 0x0000c000>; | |
| 129 | + reg-names = "mtimecmp"; | |
| 126 | 130 | interrupts-extended = <&cpu12_intc 7>, |
| 127 | 131 | <&cpu13_intc 7>, |
| 128 | 132 | <&cpu14_intc 7>, |
| 129 | 133 | <&cpu15_intc 7>; |
| 130 | 134 | }; |
| 131 | 135 | |
| 132 | − clint_mtimer4: timer@70ac040000 { | |
| 136 | + clint_mtimer4: timer@70ac044000 { | |
| 133 | 137 | compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; |
| 134 | − reg = <0x00000070 0xac040000 0x00000000 0x00007ff8>; | |
| 138 | + reg = <0x00000070 0xac044000 0x00000000 0x0000c000>; | |
| 139 | + reg-names = "mtimecmp"; | |
| 135 | 140 | interrupts-extended = <&cpu16_intc 7>, |
| 136 | 141 | <&cpu17_intc 7>, |
| 137 | 142 | <&cpu18_intc 7>, |
| 138 | 143 | <&cpu19_intc 7>; |
| 139 | 144 | }; |
| 140 | 145 | |
| 141 | − clint_mtimer5: timer@70ac050000 { | |
| 146 | + clint_mtimer5: timer@70ac054000 { | |
| 142 | 147 | compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; |
| 143 | − reg = <0x00000070 0xac050000 0x00000000 0x00007ff8>; | |
| 148 | + reg = <0x00000070 0xac054000 0x00000000 0x0000c000>; | |
| 149 | + reg-names = "mtimecmp"; | |
| 144 | 150 | interrupts-extended = <&cpu20_intc 7>, |
| 145 | 151 | <&cpu21_intc 7>, |
| 146 | 152 | <&cpu22_intc 7>, |
| 147 | 153 | <&cpu23_intc 7>; |
| 148 | 154 | }; |
| 149 | 155 | |
| 150 | − clint_mtimer6: timer@70ac060000 { | |
| 156 | + clint_mtimer6: timer@70ac064000 { | |
| 151 | 157 | compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; |
| 152 | − reg = <0x00000070 0xac060000 0x00000000 0x00007ff8>; | |
| 158 | + reg = <0x00000070 0xac064000 0x00000000 0x0000c000>; | |
| 159 | + reg-names = "mtimecmp"; | |
| 153 | 160 | interrupts-extended = <&cpu24_intc 7>, |
| 154 | 161 | <&cpu25_intc 7>, |
| 155 | 162 | <&cpu26_intc 7>, |
| 156 | 163 | <&cpu27_intc 7>; |
| 157 | 164 | }; |
| 158 | 165 | |
| 159 | − clint_mtimer7: timer@70ac070000 { | |
| 166 | + clint_mtimer7: timer@70ac074000 { | |
| 160 | 167 | compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; |
| 161 | − reg = <0x00000070 0xac070000 0x00000000 0x00007ff8>; | |
| 168 | + reg = <0x00000070 0xac074000 0x00000000 0x0000c000>; | |
| 169 | + reg-names = "mtimecmp"; | |
| 162 | 170 | interrupts-extended = <&cpu28_intc 7>, |
| 163 | 171 | <&cpu29_intc 7>, |
| 164 | 172 | <&cpu30_intc 7>, |
| 165 | 173 | <&cpu31_intc 7>; |
| 166 | 174 | }; |
| 167 | 175 | |
| 168 | − clint_mtimer8: timer@70ac080000 { | |
| 176 | + clint_mtimer8: timer@70ac084000 { | |
| 169 | 177 | compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; |
| 170 | − reg = <0x00000070 0xac080000 0x00000000 0x00007ff8>; | |
| 178 | + reg = <0x00000070 0xac084000 0x00000000 0x0000c000>; | |
| 179 | + reg-names = "mtimecmp"; | |
| 171 | 180 | interrupts-extended = <&cpu32_intc 7>, |
| 172 | 181 | <&cpu33_intc 7>, |
| 173 | 182 | <&cpu34_intc 7>, |
| 174 | 183 | <&cpu35_intc 7>; |
| 175 | 184 | }; |
| 176 | 185 | |
| 177 | − clint_mtimer9: timer@70ac090000 { | |
| 186 | + clint_mtimer9: timer@70ac094000 { | |
| 178 | 187 | compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; |
| 179 | − reg = <0x00000070 0xac090000 0x00000000 0x00007ff8>; | |
| 188 | + reg = <0x00000070 0xac094000 0x00000000 0x0000c000>; | |
| 189 | + reg-names = "mtimecmp"; | |
| 180 | 190 | interrupts-extended = <&cpu36_intc 7>, |
| 181 | 191 | <&cpu37_intc 7>, |
| 182 | 192 | <&cpu38_intc 7>, |
| 183 | 193 | <&cpu39_intc 7>; |
| 184 | 194 | }; |
| 185 | 195 | |
| 186 | − clint_mtimer10: timer@70ac0a0000 { | |
| 196 | + clint_mtimer10: timer@70ac0a4000 { | |
| 187 | 197 | compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; |
| 188 | − reg = <0x00000070 0xac0a0000 0x00000000 0x00007ff8>; | |
| 198 | + reg = <0x00000070 0xac0a4000 0x00000000 0x0000c000>; | |
| 199 | + reg-names = "mtimecmp"; | |
| 189 | 200 | interrupts-extended = <&cpu40_intc 7>, |
| 190 | 201 | <&cpu41_intc 7>, |
| 191 | 202 | <&cpu42_intc 7>, |
| 192 | 203 | <&cpu43_intc 7>; |
| 193 | 204 | }; |
| 194 | 205 | |
| 195 | − clint_mtimer11: timer@70ac0b0000 { | |
| 206 | + clint_mtimer11: timer@70ac0b4000 { | |
| 196 | 207 | compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; |
| 197 | − reg = <0x00000070 0xac0b0000 0x00000000 0x00007ff8>; | |
| 208 | + reg = <0x00000070 0xac0b4000 0x00000000 0x0000c000>; | |
| 209 | + reg-names = "mtimecmp"; | |
| 198 | 210 | interrupts-extended = <&cpu44_intc 7>, |
| 199 | 211 | <&cpu45_intc 7>, |
| 200 | 212 | <&cpu46_intc 7>, |
| 201 | 213 | <&cpu47_intc 7>; |
| 202 | 214 | }; |
| 203 | 215 | |
| 204 | − clint_mtimer12: timer@70ac0c0000 { | |
| 216 | + clint_mtimer12: timer@70ac0c4000 { | |
| 205 | 217 | compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; |
| 206 | − reg = <0x00000070 0xac0c0000 0x00000000 0x00007ff8>; | |
| 218 | + reg = <0x00000070 0xac0c4000 0x00000000 0x0000c000>; | |
| 219 | + reg-names = "mtimecmp"; | |
| 207 | 220 | interrupts-extended = <&cpu48_intc 7>, |
| 208 | 221 | <&cpu49_intc 7>, |
| 209 | 222 | <&cpu50_intc 7>, |
| 210 | 223 | <&cpu51_intc 7>; |
| 211 | 224 | }; |
| 212 | 225 | |
| 213 | − clint_mtimer13: timer@70ac0d0000 { | |
| 226 | + clint_mtimer13: timer@70ac0d4000 { | |
| 214 | 227 | compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; |
| 215 | − reg = <0x00000070 0xac0d0000 0x00000000 0x00007ff8>; | |
| 228 | + reg = <0x00000070 0xac0d4000 0x00000000 0x0000c000>; | |
| 229 | + reg-names = "mtimecmp"; | |
| 216 | 230 | interrupts-extended = <&cpu52_intc 7>, |
| 217 | 231 | <&cpu53_intc 7>, |
| 218 | 232 | <&cpu54_intc 7>, |
| 219 | 233 | <&cpu55_intc 7>; |
| 220 | 234 | }; |
| 221 | 235 | |
| 222 | − clint_mtimer14: timer@70ac0e0000 { | |
| 236 | + clint_mtimer14: timer@70ac0e4000 { | |
| 223 | 237 | compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; |
| 224 | − reg = <0x00000070 0xac0e0000 0x00000000 0x00007ff8>; | |
| 238 | + reg = <0x00000070 0xac0e4000 0x00000000 0x0000c000>; | |
| 239 | + reg-names = "mtimecmp"; | |
| 225 | 240 | interrupts-extended = <&cpu56_intc 7>, |
| 226 | 241 | <&cpu57_intc 7>, |
| 227 | 242 | <&cpu58_intc 7>, |
| 228 | 243 | <&cpu59_intc 7>; |
| 229 | 244 | }; |
| 230 | 245 | |
| 231 | − clint_mtimer15: timer@70ac0f0000 { | |
| 246 | + clint_mtimer15: timer@70ac0f4000 { | |
| 232 | 247 | compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; |
| 233 | − reg = <0x00000070 0xac0f0000 0x00000000 0x00007ff8>; | |
| 248 | + reg = <0x00000070 0xac0f4000 0x00000000 0x0000c000>; | |
| 249 | + reg-names = "mtimecmp"; | |
| 234 | 250 | interrupts-extended = <&cpu60_intc 7>, |
| 235 | 251 | <&cpu61_intc 7>, |
| 236 | 252 | <&cpu62_intc 7>, |
| @@ -795,6 +795,7 @@ static int __arch_prepare_bpf_trampoline(struct bpf_tramp_image *im, · 794 unmodified lines | ||
| 795 | 795 | struct bpf_tramp_links *fentry = &tlinks[BPF_TRAMP_FENTRY]; |
| 796 | 796 | struct bpf_tramp_links *fexit = &tlinks[BPF_TRAMP_FEXIT]; |
| 797 | 797 | struct bpf_tramp_links *fmod_ret = &tlinks[BPF_TRAMP_MODIFY_RETURN]; |
| 798 | + bool is_struct_ops = flags & BPF_TRAMP_F_INDIRECT; | |
| 798 | 799 | void *orig_call = func_addr; |
| 799 | 800 | bool save_ret; |
| 800 | 801 | u32 insn; |
| @@ -878,7 +879,7 @@ static int __arch_prepare_bpf_trampoline(struct bpf_tramp_image *im, · 77 unmodified lines | ||
| 878 | 879 | |
| 879 | 880 | stack_size = round_up(stack_size, 16); |
| 880 | 881 | |
| 881 | − if (func_addr) { | |
| 882 | + if (!is_struct_ops) { | |
| 882 | 883 | /* For the trampoline called from function entry, |
| 883 | 884 | * the frame of traced function and the frame of |
| 884 | 885 | * trampoline need to be considered. |
| @@ -998,7 +999,7 @@ static int __arch_prepare_bpf_trampoline(struct bpf_tramp_image *im, · 113 unmodified lines | ||
| 998 | 999 | |
| 999 | 1000 | emit_ld(RV_REG_S1, -sreg_off, RV_REG_FP, ctx); |
| 1000 | 1001 | |
| 1001 | − if (func_addr) { | |
| 1002 | + if (!is_struct_ops) { | |
| 1002 | 1003 | /* trampoline called from function entry */ |
| 1003 | 1004 | emit_ld(RV_REG_T0, stack_size - 8, RV_REG_SP, ctx); |
| 1004 | 1005 | emit_ld(RV_REG_FP, stack_size - 16, RV_REG_SP, ctx); |
| @@ -115,7 +115,9 @@ archprepare: · 114 unmodified lines | ||
| 115 | 115 | $(Q)$(MAKE) $(build)=$(HOST_DIR)/um include/generated/user_constants.h |
| 116 | 116 | |
| 117 | 117 | LINK-$(CONFIG_LD_SCRIPT_STATIC) += -static |
| 118 | −LINK-$(CONFIG_LD_SCRIPT_DYN) += $(call cc-option, -no-pie) | |
| 118 | +ifdef CONFIG_LD_SCRIPT_DYN | |
| 119 | +LINK-$(call gcc-min-version, 60100)$(CONFIG_CC_IS_CLANG) += -no-pie | |
| 120 | +endif | |
| 119 | 121 | LINK-$(CONFIG_LD_SCRIPT_DYN_RPATH) += -Wl,-rpath,/lib |
| 120 | 122 | |
| 121 | 123 | CFLAGS_NO_HARDENING := $(call cc-option, -fno-PIC,) $(call cc-option, -fno-pic,) \ |
| @@ -112,13 +112,13 @@ ifeq ($(CONFIG_X86_32),y) · 111 unmodified lines | ||
| 112 | 112 | # temporary until string.h is fixed |
| 113 | 113 | KBUILD_CFLAGS += -ffreestanding |
| 114 | 114 | |
| 115 | − ifeq ($(CONFIG_STACKPROTECTOR),y) | |
| 116 | − ifeq ($(CONFIG_SMP),y) | |
| 115 | + ifeq ($(CONFIG_STACKPROTECTOR),y) | |
| 116 | + ifeq ($(CONFIG_SMP),y) | |
| 117 | 117 | KBUILD_CFLAGS += -mstack-protector-guard-reg=fs -mstack-protector-guard-symbol=__stack_chk_guard |
| 118 | − else | |
| 118 | + else | |
| 119 | 119 | KBUILD_CFLAGS += -mstack-protector-guard=global |
| 120 | − endif | |
| 121 | − endif | |
| 120 | + endif | |
| 121 | + endif | |
| 122 | 122 | else |
| 123 | 123 | BITS := 64 |
| 124 | 124 | UTS_MACHINE := x86_64 |
| @@ -81,10 +81,8 @@ · 80 unmodified lines | ||
| 81 | 81 | #define X86_FEATURE_K6_MTRR ( 3*32+ 1) /* AMD K6 nonstandard MTRRs */ |
| 82 | 82 | #define X86_FEATURE_CYRIX_ARR ( 3*32+ 2) /* Cyrix ARRs (= MTRRs) */ |
| 83 | 83 | #define X86_FEATURE_CENTAUR_MCR ( 3*32+ 3) /* Centaur MCRs (= MTRRs) */ |
| 84 | − | |
| 85 | −/* CPU types for specific tunings: */ | |
| 86 | 84 | #define X86_FEATURE_K8 ( 3*32+ 4) /* "" Opteron, Athlon64 */ |
| 87 | −/* FREE, was #define X86_FEATURE_K7 ( 3*32+ 5) "" Athlon */ | |
| 85 | +#define X86_FEATURE_ZEN5 ( 3*32+ 5) /* "" CPU based on Zen5 microarchitecture */ | |
| 88 | 86 | #define X86_FEATURE_P3 ( 3*32+ 6) /* "" P3 */ |
| 89 | 87 | #define X86_FEATURE_P4 ( 3*32+ 7) /* "" P4 */ |
| 90 | 88 | #define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* TSC ticks at a constant rate */ |
| @@ -162,6 +162,8 @@ · 161 unmodified lines | ||
| 162 | 162 | #define INTEL_FAM6_ATOM_CRESTMONT_X 0xAF /* Sierra Forest */ |
| 163 | 163 | #define INTEL_FAM6_ATOM_CRESTMONT 0xB6 /* Grand Ridge */ |
| 164 | 164 | |
| 165 | +#define INTEL_FAM6_ATOM_DARKMONT_X 0xDD /* Clearwater Forest */ | |
| 166 | + | |
| 165 | 167 | /* Xeon Phi */ |
| 166 | 168 | |
| 167 | 169 | #define INTEL_FAM6_XEON_PHI_KNL 0x57 /* Knights Landing */ |
| @@ -64,6 +64,7 @@ static inline bool kmsan_virt_addr_valid(void *addr) · 63 unmodified lines | ||
| 64 | 64 | { |
| 65 | 65 | unsigned long x = (unsigned long)addr; |
| 66 | 66 | unsigned long y = x - __START_KERNEL_map; |
| 67 | + bool ret; | |
| 67 | 68 | |
| 68 | 69 | /* use the carry flag to determine if x was < __START_KERNEL_map */ |
| 69 | 70 | if (unlikely(x > y)) { |
| @@ -79,7 +80,21 @@ static inline bool kmsan_virt_addr_valid(void *addr) · 9 unmodified lines | ||
| 79 | 80 | return false; |
| 80 | 81 | } |
| 81 | 82 | |
| 82 | − return pfn_valid(x >> PAGE_SHIFT); | |
| 83 | + /* | |
| 84 | + * pfn_valid() relies on RCU, and may call into the scheduler on exiting | |
| 85 | + * the critical section. However, this would result in recursion with | |
| 86 | + * KMSAN. Therefore, disable preemption here, and re-enable preemption | |
| 87 | + * below while suppressing reschedules to avoid recursion. | |
| 88 | + * | |
| 89 | + * Note, this sacrifices occasionally breaking scheduling guarantees. | |
| 90 | + * Although, a kernel compiled with KMSAN has already given up on any | |
| 91 | + * performance guarantees due to being heavily instrumented. | |
| 92 | + */ | |
| 93 | + preempt_disable(); | |
| 94 | + ret = pfn_valid(x >> PAGE_SHIFT); | |
| 95 | + preempt_enable_no_resched(); | |
| 96 | + | |
| 97 | + return ret; | |
| 83 | 98 | } |
| 84 | 99 | |
| 85 | 100 | #endif /* !MODULE */ |
| @@ -58,12 +58,29 @@ extern long __ia32_sys_ni_syscall(const struct pt_regs *regs); · 57 unmodified lines | ||
| 58 | 58 | ,,regs->di,,regs->si,,regs->dx \ |
| 59 | 59 | ,,regs->r10,,regs->r8,,regs->r9) \ |
| 60 | 60 | |
| 61 | + | |
| 62 | +/* SYSCALL_PT_ARGS is Adapted from s390x */ | |
| 63 | +#define SYSCALL_PT_ARG6(m, t1, t2, t3, t4, t5, t6) \ | |
| 64 | + SYSCALL_PT_ARG5(m, t1, t2, t3, t4, t5), m(t6, (regs->bp)) | |
| 65 | +#define SYSCALL_PT_ARG5(m, t1, t2, t3, t4, t5) \ | |
| 66 | + SYSCALL_PT_ARG4(m, t1, t2, t3, t4), m(t5, (regs->di)) | |
| 67 | +#define SYSCALL_PT_ARG4(m, t1, t2, t3, t4) \ | |
| 68 | + SYSCALL_PT_ARG3(m, t1, t2, t3), m(t4, (regs->si)) | |
| 69 | +#define SYSCALL_PT_ARG3(m, t1, t2, t3) \ | |
| 70 | + SYSCALL_PT_ARG2(m, t1, t2), m(t3, (regs->dx)) | |
| 71 | +#define SYSCALL_PT_ARG2(m, t1, t2) \ | |
| 72 | + SYSCALL_PT_ARG1(m, t1), m(t2, (regs->cx)) | |
| 73 | +#define SYSCALL_PT_ARG1(m, t1) m(t1, (regs->bx)) | |
| 74 | +#define SYSCALL_PT_ARGS(x, ...) SYSCALL_PT_ARG##x(__VA_ARGS__) | |
| 75 | + | |
| 76 | +#define __SC_COMPAT_CAST(t, a) \ | |
| 77 | + (__typeof(__builtin_choose_expr(__TYPE_IS_L(t), 0, 0U))) \ | |
| 78 | + (unsigned int)a | |
| 79 | + | |
| 61 | 80 | /* Mapping of registers to parameters for syscalls on i386 */ |
| 62 | 81 | #define SC_IA32_REGS_TO_ARGS(x, ...) \ |
| 63 | − __MAP(x,__SC_ARGS \ | |
| 64 | − ,,(unsigned int)regs->bx,,(unsigned int)regs->cx \ | |
| 65 | − ,,(unsigned int)regs->dx,,(unsigned int)regs->si \ | |
| 66 | − ,,(unsigned int)regs->di,,(unsigned int)regs->bp) | |
| 82 | + SYSCALL_PT_ARGS(x, __SC_COMPAT_CAST, \ | |
| 83 | + __MAP(x, __SC_TYPE, __VA_ARGS__)) \ | |
| 67 | 84 | |
| 68 | 85 | #define __SYS_STUB0(abi, name) \ |
| 69 | 86 | long __##abi##_##name(const struct pt_regs *regs); \ |
| @@ -403,7 +403,7 @@ noinstr void BUG_func(void) · 402 unmodified lines | ||
| 403 | 403 | { |
| 404 | 404 | BUG(); |
| 405 | 405 | } |
| 406 | −EXPORT_SYMBOL_GPL(BUG_func); | |
| 406 | +EXPORT_SYMBOL(BUG_func); | |
| 407 | 407 | |
| 408 | 408 | #define CALL_RIP_REL_OPCODE 0xff |
| 409 | 409 | #define CALL_RIP_REL_MODRM 0x15 |
| @@ -538,7 +538,7 @@ static void bsp_init_amd(struct cpuinfo_x86 *c) · 537 unmodified lines | ||
| 538 | 538 | |
| 539 | 539 | /* Figure out Zen generations: */ |
| 540 | 540 | switch (c->x86) { |
| 541 | − case 0x17: { | |
| 541 | + case 0x17: | |
| 542 | 542 | switch (c->x86_model) { |
| 543 | 543 | case 0x00 ... 0x2f: |
| 544 | 544 | case 0x50 ... 0x5f: |
| @@ -554,8 +554,8 @@ static void bsp_init_amd(struct cpuinfo_x86 *c) · 9 unmodified lines | ||
| 554 | 554 | goto warn; |
| 555 | 555 | } |
| 556 | 556 | break; |
| 557 | − } | |
| 558 | − case 0x19: { | |
| 557 | + | |
| 558 | + case 0x19: | |
| 559 | 559 | switch (c->x86_model) { |
| 560 | 560 | case 0x00 ... 0x0f: |
| 561 | 561 | case 0x20 ... 0x5f: |
| @@ -569,7 +569,20 @@ static void bsp_init_amd(struct cpuinfo_x86 *c) · 7 unmodified lines | ||
| 569 | 569 | goto warn; |
| 570 | 570 | } |
| 571 | 571 | break; |
| 572 | − } | |
| 572 | + | |
| 573 | + case 0x1a: | |
| 574 | + switch (c->x86_model) { | |
| 575 | + case 0x00 ... 0x0f: | |
| 576 | + case 0x20 ... 0x2f: | |
| 577 | + case 0x40 ... 0x4f: | |
| 578 | + case 0x70 ... 0x7f: | |
| 579 | + setup_force_cpu_cap(X86_FEATURE_ZEN5); | |
| 580 | + break; | |
| 581 | + default: | |
| 582 | + goto warn; | |
| 583 | + } | |
| 584 | + break; | |
| 585 | + | |
| 573 | 586 | default: |
| 574 | 587 | break; |
| 575 | 588 | } |
| @@ -1039,6 +1052,11 @@ static void init_amd_zen4(struct cpuinfo_x86 *c) · 463 unmodified lines | ||
| 1039 | 1052 | msr_set_bit(MSR_ZEN4_BP_CFG, MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT); |
| 1040 | 1053 | } |
| 1041 | 1054 | |
| 1055 | +static void init_amd_zen5(struct cpuinfo_x86 *c) | |
| 1056 | +{ | |
| 1057 | + init_amd_zen_common(); | |
| 1058 | +} | |
| 1059 | + | |
| 1042 | 1060 | static void init_amd(struct cpuinfo_x86 *c) |
| 1043 | 1061 | { |
| 1044 | 1062 | u64 vm_cr; |
| @@ -1084,6 +1102,8 @@ static void init_amd(struct cpuinfo_x86 *c) · 39 unmodified lines | ||
| 1084 | 1102 | init_amd_zen3(c); |
| 1085 | 1103 | else if (boot_cpu_has(X86_FEATURE_ZEN4)) |
| 1086 | 1104 | init_amd_zen4(c); |
| 1105 | + else if (boot_cpu_has(X86_FEATURE_ZEN5)) | |
| 1106 | + init_amd_zen5(c); | |
| 1087 | 1107 | |
| 1088 | 1108 | /* |
| 1089 | 1109 | * Enable workaround for FXSAVE leak on CPUs |
| @@ -49,6 +49,7 @@ · 48 unmodified lines | ||
| 49 | 49 | #include "blk-pm.h" |
| 50 | 50 | #include "blk-cgroup.h" |
| 51 | 51 | #include "blk-throttle.h" |
| 52 | +#include "blk-ioprio.h" | |
| 52 | 53 | |
| 53 | 54 | struct dentry *blk_debugfs_root; |
| 54 | 55 | |
| @@ -833,6 +834,14 @@ end_io: · 778 unmodified lines | ||
| 833 | 834 | } |
| 834 | 835 | EXPORT_SYMBOL(submit_bio_noacct); |
| 835 | 836 | |
| 837 | +static void bio_set_ioprio(struct bio *bio) | |
| 838 | +{ | |
| 839 | + /* Nobody set ioprio so far? Initialize it based on task's nice value */ | |
| 840 | + if (IOPRIO_PRIO_CLASS(bio->bi_ioprio) == IOPRIO_CLASS_NONE) | |
| 841 | + bio->bi_ioprio = get_current_ioprio(); | |
| 842 | + blkcg_set_ioprio(bio); | |
| 843 | +} | |
| 844 | + | |
| 836 | 845 | /** |
| 837 | 846 | * submit_bio - submit a bio to the block device layer for I/O |
| 838 | 847 | * @bio: The &struct bio which describes the I/O |
| @@ -855,6 +864,7 @@ void submit_bio(struct bio *bio) · 16 unmodified lines | ||
| 855 | 864 | count_vm_events(PGPGOUT, bio_sectors(bio)); |
| 856 | 865 | } |
| 857 | 866 | |
| 867 | + bio_set_ioprio(bio); | |
| 858 | 868 | submit_bio_noacct(bio); |
| 859 | 869 | } |
| 860 | 870 | EXPORT_SYMBOL(submit_bio); |
| @@ -205,12 +205,19 @@ static int bio_copy_user_iov(struct request *rq, struct rq_map_data *map_data, · 204 unmodified lines | ||
| 205 | 205 | /* |
| 206 | 206 | * success |
| 207 | 207 | */ |
| 208 | − if ((iov_iter_rw(iter) == WRITE && | |
| 209 | − (!map_data || !map_data->null_mapped)) || | |
| 210 | − (map_data && map_data->from_user)) { | |
| 208 | + if (iov_iter_rw(iter) == WRITE && | |
| 209 | + (!map_data || !map_data->null_mapped)) { | |
| 211 | 210 | ret = bio_copy_from_iter(bio, iter); |
| 212 | 211 | if (ret) |
| 213 | 212 | goto cleanup; |
| 213 | + } else if (map_data && map_data->from_user) { | |
| 214 | + struct iov_iter iter2 = *iter; | |
| 215 | + | |
| 216 | + /* This is the copy-in part of SG_DXFER_TO_FROM_DEV. */ | |
| 217 | + iter2.data_source = ITER_SOURCE; | |
| 218 | + ret = bio_copy_from_iter(bio, &iter2); | |
| 219 | + if (ret) | |
| 220 | + goto cleanup; | |
| 214 | 221 | } else { |
| 215 | 222 | if (bmd->is_our_pages) |
| 216 | 223 | zero_fill_bio(bio); |
| @@ -40,7 +40,6 @@ · 39 unmodified lines | ||
| 40 | 40 | #include "blk-stat.h" |
| 41 | 41 | #include "blk-mq-sched.h" |
| 42 | 42 | #include "blk-rq-qos.h" |
| 43 | −#include "blk-ioprio.h" | |
| 44 | 43 | |
| 45 | 44 | static DEFINE_PER_CPU(struct llist_head, blk_cpu_done); |
| 46 | 45 | static DEFINE_PER_CPU(call_single_data_t, blk_cpu_csd); |
| @@ -2944,14 +2943,6 @@ static bool blk_mq_use_cached_rq(struct request *rq, struct blk_plug *plug, · 2897 unmodified lines | ||
| 2944 | 2943 | return true; |
| 2945 | 2944 | } |
| 2946 | 2945 | |
| 2947 | −static void bio_set_ioprio(struct bio *bio) | |
| 2948 | −{ | |
| 2949 | − /* Nobody set ioprio so far? Initialize it based on task's nice value */ | |
| 2950 | − if (IOPRIO_PRIO_CLASS(bio->bi_ioprio) == IOPRIO_CLASS_NONE) | |
| 2951 | − bio->bi_ioprio = get_current_ioprio(); | |
| 2952 | − blkcg_set_ioprio(bio); | |
| 2953 | −} | |
| 2954 | − | |
| 2955 | 2946 | /** |
| 2956 | 2947 | * blk_mq_submit_bio - Create and send a request to block device. |
| 2957 | 2948 | * @bio: Bio pointer. |
| @@ -2976,7 +2967,6 @@ void blk_mq_submit_bio(struct bio *bio) · 18 unmodified lines | ||
| 2976 | 2967 | blk_status_t ret; |
| 2977 | 2968 | |
| 2978 | 2969 | bio = blk_queue_bounce(bio, q); |
| 2979 | − bio_set_ioprio(bio); | |
| 2980 | 2970 | |
| 2981 | 2971 | if (plug) { |
| 2982 | 2972 | rq = rq_list_peek(&plug->cached_rq); |
| @@ -20,8 +20,6 @@ static int blkpg_do_ioctl(struct block_device *bdev, · 19 unmodified lines | ||
| 20 | 20 | struct blkpg_partition p; |
| 21 | 21 | sector_t start, length; |
| 22 | 22 | |
| 23 | − if (disk->flags & GENHD_FL_NO_PART) | |
| 24 | − return -EINVAL; | |
| 25 | 23 | if (!capable(CAP_SYS_ADMIN)) |
| 26 | 24 | return -EACCES; |
| 27 | 25 | if (copy_from_user(&p, upart, sizeof(struct blkpg_partition))) |
| @@ -439,6 +439,11 @@ int bdev_add_partition(struct gendisk *disk, int partno, sector_t start, · 438 unmodified lines | ||
| 439 | 439 | goto out; |
| 440 | 440 | } |
| 441 | 441 | |
| 442 | + if (disk->flags & GENHD_FL_NO_PART) { | |
| 443 | + ret = -EINVAL; | |
| 444 | + goto out; | |
| 445 | + } | |
| 446 | + | |
| 442 | 447 | if (partition_overlaps(disk, start, length, -1)) { |
| 443 | 448 | ret = -EBUSY; |
| 444 | 449 | goto out; |
| @@ -102,7 +102,7 @@ static int reset_pending_show(struct seq_file *s, void *v) · 101 unmodified lines | ||
| 102 | 102 | { |
| 103 | 103 | struct ivpu_device *vdev = seq_to_ivpu(s); |
| 104 | 104 | |
| 105 | − seq_printf(s, "%d\n", atomic_read(&vdev->pm->in_reset)); | |
| 105 | + seq_printf(s, "%d\n", atomic_read(&vdev->pm->reset_pending)); | |
| 106 | 106 | return 0; |
| 107 | 107 | } |
| 108 | 108 | |
| @@ -130,7 +130,9 @@ dvfs_mode_fops_write(struct file *file, const char __user *user_buf, size_t size · 21 unmodified lines | ||
| 130 | 130 | |
| 131 | 131 | fw->dvfs_mode = dvfs_mode; |
| 132 | 132 | |
| 133 | − ivpu_pm_schedule_recovery(vdev); | |
| 133 | + ret = pci_try_reset_function(to_pci_dev(vdev->drm.dev)); | |
| 134 | + if (ret) | |
| 135 | + return ret; | |
| 134 | 136 | |
| 135 | 137 | return size; |
| 136 | 138 | } |
| @@ -190,7 +192,10 @@ fw_profiling_freq_fops_write(struct file *file, const char __user *user_buf, · 53 unmodified lines | ||
| 190 | 192 | return ret; |
| 191 | 193 | |
| 192 | 194 | ivpu_hw_profiling_freq_drive(vdev, enable); |
| 193 | − ivpu_pm_schedule_recovery(vdev); | |
| 195 | + | |
| 196 | + ret = pci_try_reset_function(to_pci_dev(vdev->drm.dev)); | |
| 197 | + if (ret) | |
| 198 | + return ret; | |
| 194 | 199 | |
| 195 | 200 | return size; |
| 196 | 201 | } |
| @@ -301,11 +306,18 @@ static ssize_t · 104 unmodified lines | ||
| 301 | 306 | ivpu_force_recovery_fn(struct file *file, const char __user *user_buf, size_t size, loff_t *pos) |
| 302 | 307 | { |
| 303 | 308 | struct ivpu_device *vdev = file->private_data; |
| 309 | + int ret; | |
| 304 | 310 | |
| 305 | 311 | if (!size) |
| 306 | 312 | return -EINVAL; |
| 307 | 313 | |
| 308 | − ivpu_pm_schedule_recovery(vdev); | |
| 314 | + ret = ivpu_rpm_get(vdev); | |
| 315 | + if (ret) | |
| 316 | + return ret; | |
| 317 | + | |
| 318 | + ivpu_pm_trigger_recovery(vdev, "debugfs"); | |
| 319 | + flush_work(&vdev->pm->recovery_work); | |
| 320 | + ivpu_rpm_put(vdev); | |
| 309 | 321 | return size; |
| 310 | 322 | } |
| 311 | 323 | |
| @@ -6,6 +6,7 @@ · 5 unmodified lines | ||
| 6 | 6 | #include <linux/firmware.h> |
| 7 | 7 | #include <linux/module.h> |
| 8 | 8 | #include <linux/pci.h> |
| 9 | +#include <linux/pm_runtime.h> | |
| 9 | 10 | |
| 10 | 11 | #include <drm/drm_accel.h> |
| 11 | 12 | #include <drm/drm_file.h> |
| @@ -17,6 +18,7 @@ · 5 unmodified lines | ||
| 17 | 18 | #include "ivpu_debugfs.h" |
| 18 | 19 | #include "ivpu_drv.h" |
| 19 | 20 | #include "ivpu_fw.h" |
| 21 | +#include "ivpu_fw_log.h" | |
| 20 | 22 | #include "ivpu_gem.h" |
| 21 | 23 | #include "ivpu_hw.h" |
| 22 | 24 | #include "ivpu_ipc.h" |
| @@ -65,22 +67,20 @@ struct ivpu_file_priv *ivpu_file_priv_get(struct ivpu_file_priv *file_priv) · 42 unmodified lines | ||
| 65 | 67 | return file_priv; |
| 66 | 68 | } |
| 67 | 69 | |
| 68 | −struct ivpu_file_priv *ivpu_file_priv_get_by_ctx_id(struct ivpu_device *vdev, unsigned long id) | |
| 70 | +static void file_priv_unbind(struct ivpu_device *vdev, struct ivpu_file_priv *file_priv) | |
| 69 | 71 | { |
| 70 | − struct ivpu_file_priv *file_priv; | |
| 71 | − | |
| 72 | − xa_lock_irq(&vdev->context_xa); | |
| 73 | − file_priv = xa_load(&vdev->context_xa, id); | |
| 74 | − /* file_priv may still be in context_xa during file_priv_release() */ | |
| 75 | − if (file_priv && !kref_get_unless_zero(&file_priv->ref)) | |
| 76 | − file_priv = NULL; | |
| 77 | − xa_unlock_irq(&vdev->context_xa); | |
| 78 | − | |
| 79 | − if (file_priv) | |
| 80 | − ivpu_dbg(vdev, KREF, "file_priv get by id: ctx %u refcount %u\n", | |
| 81 | − file_priv->ctx.id, kref_read(&file_priv->ref)); | |
| 82 | − | |
| 83 | − return file_priv; | |
| 72 | + mutex_lock(&file_priv->lock); | |
| 73 | + if (file_priv->bound) { | |
| 74 | + ivpu_dbg(vdev, FILE, "file_priv unbind: ctx %u\n", file_priv->ctx.id); | |
| 75 | + | |
| 76 | + ivpu_cmdq_release_all_locked(file_priv); | |
| 77 | + ivpu_jsm_context_release(vdev, file_priv->ctx.id); | |
| 78 | + ivpu_bo_unbind_all_bos_from_context(vdev, &file_priv->ctx); | |
| 79 | + ivpu_mmu_user_context_fini(vdev, &file_priv->ctx); | |
| 80 | + file_priv->bound = false; | |
| 81 | + drm_WARN_ON(&vdev->drm, !xa_erase_irq(&vdev->context_xa, file_priv->ctx.id)); | |
| 82 | + } | |
| 83 | + mutex_unlock(&file_priv->lock); | |
| 84 | 84 | } |
| 85 | 85 | |
| 86 | 86 | static void file_priv_release(struct kref *ref) |
| @@ -88,13 +88,15 @@ static void file_priv_release(struct kref *ref) · 1 unmodified line | ||
| 88 | 88 | struct ivpu_file_priv *file_priv = container_of(ref, struct ivpu_file_priv, ref); |
| 89 | 89 | struct ivpu_device *vdev = file_priv->vdev; |
| 90 | 90 | |
| 91 | − ivpu_dbg(vdev, FILE, "file_priv release: ctx %u\n", file_priv->ctx.id); | |
| 91 | + ivpu_dbg(vdev, FILE, "file_priv release: ctx %u bound %d\n", | |
| 92 | + file_priv->ctx.id, (bool)file_priv->bound); | |
| 93 | + | |
| 94 | + pm_runtime_get_sync(vdev->drm.dev); | |
| 95 | + mutex_lock(&vdev->context_list_lock); | |
| 96 | + file_priv_unbind(vdev, file_priv); | |
| 97 | + mutex_unlock(&vdev->context_list_lock); | |
| 98 | + pm_runtime_put_autosuspend(vdev->drm.dev); | |
| 92 | 99 | |
| 93 | − ivpu_cmdq_release_all(file_priv); | |
| 94 | − ivpu_jsm_context_release(vdev, file_priv->ctx.id); | |
| 95 | − ivpu_bo_remove_all_bos_from_context(vdev, &file_priv->ctx); | |
| 96 | − ivpu_mmu_user_context_fini(vdev, &file_priv->ctx); | |
| 97 | − drm_WARN_ON(&vdev->drm, xa_erase_irq(&vdev->context_xa, file_priv->ctx.id) != file_priv); | |
| 98 | 100 | mutex_destroy(&file_priv->lock); |
| 99 | 101 | kfree(file_priv); |
| 100 | 102 | } |
| @@ -176,9 +178,6 @@ static int ivpu_get_param_ioctl(struct drm_device *dev, void *data, struct drm_f · 75 unmodified lines | ||
| 176 | 178 | case DRM_IVPU_PARAM_CONTEXT_BASE_ADDRESS: |
| 177 | 179 | args->value = vdev->hw->ranges.user.start; |
| 178 | 180 | break; |
| 179 | − case DRM_IVPU_PARAM_CONTEXT_PRIORITY: | |
| 180 | − args->value = file_priv->priority; | |
| 181 | − break; | |
| 182 | 181 | case DRM_IVPU_PARAM_CONTEXT_ID: |
| 183 | 182 | args->value = file_priv->ctx.id; |
| 184 | 183 | break; |
| @@ -218,17 +217,10 @@ static int ivpu_get_param_ioctl(struct drm_device *dev, void *data, struct drm_f · 33 unmodified lines | ||
| 218 | 217 | |
| 219 | 218 | static int ivpu_set_param_ioctl(struct drm_device *dev, void *data, struct drm_file *file) |
| 220 | 219 | { |
| 221 | − struct ivpu_file_priv *file_priv = file->driver_priv; | |
| 222 | 220 | struct drm_ivpu_param *args = data; |
| 223 | 221 | int ret = 0; |
| 224 | 222 | |
| 225 | 223 | switch (args->param) { |
| 226 | − case DRM_IVPU_PARAM_CONTEXT_PRIORITY: | |
| 227 | − if (args->value <= DRM_IVPU_CONTEXT_PRIORITY_REALTIME) | |
| 228 | − file_priv->priority = args->value; | |
| 229 | − else | |
| 230 | − ret = -EINVAL; | |
| 231 | − break; | |
| 232 | 224 | default: |
| 233 | 225 | ret = -EINVAL; |
| 234 | 226 | } |
| @@ -241,50 +233,53 @@ static int ivpu_open(struct drm_device *dev, struct drm_file *file) · 6 unmodified lines | ||
| 241 | 233 | struct ivpu_device *vdev = to_ivpu_device(dev); |
| 242 | 234 | struct ivpu_file_priv *file_priv; |
| 243 | 235 | u32 ctx_id; |
| 244 | − void *old; | |
| 245 | − int ret; | |
| 236 | + int idx, ret; | |
| 246 | 237 | |
| 247 | − ret = xa_alloc_irq(&vdev->context_xa, &ctx_id, NULL, vdev->context_xa_limit, GFP_KERNEL); | |
| 248 | − if (ret) { | |
| 249 | − ivpu_err(vdev, "Failed to allocate context id: %d\n", ret); | |
| 250 | − return ret; | |
| 251 | − } | |
| 238 | + if (!drm_dev_enter(dev, &idx)) | |
| 239 | + return -ENODEV; | |
| 252 | 240 | |
| 253 | 241 | file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); |
| 254 | 242 | if (!file_priv) { |
| 255 | 243 | ret = -ENOMEM; |
| 256 | − goto err_xa_erase; | |
| 244 | + goto err_dev_exit; | |
| 257 | 245 | } |
| 258 | 246 | |
| 259 | 247 | file_priv->vdev = vdev; |
| 260 | − file_priv->priority = DRM_IVPU_CONTEXT_PRIORITY_NORMAL; | |
| 248 | + file_priv->bound = true; | |
| 261 | 249 | kref_init(&file_priv->ref); |
| 262 | 250 | mutex_init(&file_priv->lock); |
| 263 | 251 | |
| 252 | + mutex_lock(&vdev->context_list_lock); | |
| 253 | + | |
| 254 | + ret = xa_alloc_irq(&vdev->context_xa, &ctx_id, file_priv, | |
| 255 | + vdev->context_xa_limit, GFP_KERNEL); | |
| 256 | + if (ret) { | |
| 257 | + ivpu_err(vdev, "Failed to allocate context id: %d\n", ret); | |
| 258 | + goto err_unlock; | |
| 259 | + } | |
| 260 | + | |
| 264 | 261 | ret = ivpu_mmu_user_context_init(vdev, &file_priv->ctx, ctx_id); |
| 265 | 262 | if (ret) |
| 266 | − goto err_mutex_destroy; | |
| 263 | + goto err_xa_erase; | |
| 267 | 264 | |
| 268 | − old = xa_store_irq(&vdev->context_xa, ctx_id, file_priv, GFP_KERNEL); | |
| 269 | − if (xa_is_err(old)) { | |
| 270 | − ret = xa_err(old); | |
| 271 | − ivpu_err(vdev, "Failed to store context %u: %d\n", ctx_id, ret); | |
| 272 | − goto err_ctx_fini; | |
| 273 | − } | |
| 265 | + mutex_unlock(&vdev->context_list_lock); | |
| 266 | + drm_dev_exit(idx); | |
| 267 | + | |
| 268 | + file->driver_priv = file_priv; | |
| 274 | 269 | |
| 275 | 270 | ivpu_dbg(vdev, FILE, "file_priv create: ctx %u process %s pid %d\n", |
| 276 | 271 | ctx_id, current->comm, task_pid_nr(current)); |
| 277 | 272 | |
| 278 | − file->driver_priv = file_priv; | |
| 279 | 273 | return 0; |
| 280 | 274 | |
| 281 | −err_ctx_fini: | |
| 282 | − ivpu_mmu_user_context_fini(vdev, &file_priv->ctx); | |
| 283 | −err_mutex_destroy: | |
| 284 | − mutex_destroy(&file_priv->lock); | |
| 285 | − kfree(file_priv); | |
| 286 | 275 | err_xa_erase: |
| 287 | 276 | xa_erase_irq(&vdev->context_xa, ctx_id); |
| 277 | +err_unlock: | |
| 278 | + mutex_unlock(&vdev->context_list_lock); | |
| 279 | + mutex_destroy(&file_priv->lock); | |
| 280 | + kfree(file_priv); | |
| 281 | +err_dev_exit: | |
| 282 | + drm_dev_exit(idx); | |
| 288 | 283 | return ret; |
| 289 | 284 | } |
| 290 | 285 | |
| @@ -340,8 +335,6 @@ static int ivpu_wait_for_ready(struct ivpu_device *vdev) · 49 unmodified lines | ||
| 340 | 335 | |
| 341 | 336 | if (!ret) |
| 342 | 337 | ivpu_dbg(vdev, PM, "VPU ready message received successfully\n"); |
| 343 | − else | |
| 344 | − ivpu_hw_diagnose_failure(vdev); | |
| 345 | 338 | |
| 346 | 339 | return ret; |
| 347 | 340 | } |
| @@ -369,6 +362,9 @@ int ivpu_boot(struct ivpu_device *vdev) · 21 unmodified lines | ||
| 369 | 362 | ret = ivpu_wait_for_ready(vdev); |
| 370 | 363 | if (ret) { |
| 371 | 364 | ivpu_err(vdev, "Failed to boot the firmware: %d\n", ret); |
| 365 | + ivpu_hw_diagnose_failure(vdev); | |
| 366 | + ivpu_mmu_evtq_dump(vdev); | |
| 367 | + ivpu_fw_log_dump(vdev); | |
| 372 | 368 | return ret; |
| 373 | 369 | } |
| 374 | 370 | |
| @@ -540,6 +536,10 @@ static int ivpu_dev_init(struct ivpu_device *vdev) · 165 unmodified lines | ||
| 540 | 536 | lockdep_set_class(&vdev->submitted_jobs_xa.xa_lock, &submitted_jobs_xa_lock_class_key); |
| 541 | 537 | INIT_LIST_HEAD(&vdev->bo_list); |
| 542 | 538 | |
| 539 | + ret = drmm_mutex_init(&vdev->drm, &vdev->context_list_lock); | |
| 540 | + if (ret) | |
| 541 | + goto err_xa_destroy; | |
| 542 | + | |
| 543 | 543 | ret = drmm_mutex_init(&vdev->drm, &vdev->bo_list_lock); |
| 544 | 544 | if (ret) |
| 545 | 545 | goto err_xa_destroy; |
| @@ -611,14 +611,30 @@ err_xa_destroy: · 65 unmodified lines | ||
| 611 | 611 | return ret; |
| 612 | 612 | } |
| 613 | 613 | |
| 614 | +static void ivpu_bo_unbind_all_user_contexts(struct ivpu_device *vdev) | |
| 615 | +{ | |
| 616 | + struct ivpu_file_priv *file_priv; | |
| 617 | + unsigned long ctx_id; | |
| 618 | + | |
| 619 | + mutex_lock(&vdev->context_list_lock); | |
| 620 | + | |
| 621 | + xa_for_each(&vdev->context_xa, ctx_id, file_priv) | |
| 622 | + file_priv_unbind(vdev, file_priv); | |
| 623 | + | |
| 624 | + mutex_unlock(&vdev->context_list_lock); | |
| 625 | +} | |
| 626 | + | |
| 614 | 627 | static void ivpu_dev_fini(struct ivpu_device *vdev) |
| 615 | 628 | { |
| 616 | 629 | ivpu_pm_disable(vdev); |
| 617 | 630 | ivpu_shutdown(vdev); |
| 618 | 631 | if (IVPU_WA(d3hot_after_power_off)) |
| 619 | 632 | pci_set_power_state(to_pci_dev(vdev->drm.dev), PCI_D3hot); |
| 633 | + | |
| 634 | + ivpu_jobs_abort_all(vdev); | |
| 620 | 635 | ivpu_job_done_consumer_fini(vdev); |
| 621 | 636 | ivpu_pm_cancel_recovery(vdev); |
| 637 | + ivpu_bo_unbind_all_user_contexts(vdev); | |
| 622 | 638 | |
| 623 | 639 | ivpu_ipc_fini(vdev); |
| 624 | 640 | ivpu_fw_fini(vdev); |
| @@ -56,6 +56,7 @@ · 55 unmodified lines | ||
| 56 | 56 | #define IVPU_DBG_JSM BIT(10) |
| 57 | 57 | #define IVPU_DBG_KREF BIT(11) |
| 58 | 58 | #define IVPU_DBG_RPM BIT(12) |
| 59 | +#define IVPU_DBG_MMU_MAP BIT(13) | |
| 59 | 60 | |
| 60 | 61 | #define ivpu_err(vdev, fmt, ...) \ |
| 61 | 62 | drm_err(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__) |
| @@ -114,6 +115,7 @@ struct ivpu_device { · 52 unmodified lines | ||
| 114 | 115 | |
| 115 | 116 | struct ivpu_mmu_context gctx; |
| 116 | 117 | struct ivpu_mmu_context rctx; |
| 118 | + struct mutex context_list_lock; /* Protects user context addition/removal */ | |
| 117 | 119 | struct xarray context_xa; |
| 118 | 120 | struct xa_limit context_xa_limit; |
| 119 | 121 | |
| @@ -145,8 +147,8 @@ struct ivpu_file_priv { · 25 unmodified lines | ||
| 145 | 147 | struct mutex lock; /* Protects cmdq */ |
| 146 | 148 | struct ivpu_cmdq *cmdq[IVPU_NUM_ENGINES]; |
| 147 | 149 | struct ivpu_mmu_context ctx; |
| 148 | − u32 priority; | |
| 149 | 150 | bool has_mmu_faults; |
| 151 | + bool bound; | |
| 150 | 152 | }; |
| 151 | 153 | |
| 152 | 154 | extern int ivpu_dbg_mask; |
| @@ -162,7 +164,6 @@ extern bool ivpu_disable_mmu_cont_pages; · 9 unmodified lines | ||
| 162 | 164 | extern int ivpu_test_mode; |
| 163 | 165 | |
| 164 | 166 | struct ivpu_file_priv *ivpu_file_priv_get(struct ivpu_file_priv *file_priv); |
| 165 | −struct ivpu_file_priv *ivpu_file_priv_get_by_ctx_id(struct ivpu_device *vdev, unsigned long id); | |
| 166 | 167 | void ivpu_file_priv_put(struct ivpu_file_priv **link); |
| 167 | 168 | |
| 168 | 169 | int ivpu_boot(struct ivpu_device *vdev); |
| @@ -24,14 +24,11 @@ static const struct drm_gem_object_funcs ivpu_gem_funcs; · 23 unmodified lines | ||
| 24 | 24 | |
| 25 | 25 | static inline void ivpu_dbg_bo(struct ivpu_device *vdev, struct ivpu_bo *bo, const char *action) |
| 26 | 26 | { |
| 27 | − if (bo->ctx) | |
| 28 | − ivpu_dbg(vdev, BO, "%6s: size %zu has_pages %d dma_mapped %d handle %u ctx %d vpu_addr 0x%llx mmu_mapped %d\n", | |
| 29 | − action, ivpu_bo_size(bo), (bool)bo->base.pages, (bool)bo->base.sgt, | |
| 30 | − bo->handle, bo->ctx->id, bo->vpu_addr, bo->mmu_mapped); | |
| 31 | − else | |
| 32 | − ivpu_dbg(vdev, BO, "%6s: size %zu has_pages %d dma_mapped %d handle %u (not added to context)\n", | |
| 33 | − action, ivpu_bo_size(bo), (bool)bo->base.pages, (bool)bo->base.sgt, | |
| 34 | − bo->handle); | |
| 27 | + ivpu_dbg(vdev, BO, | |
| 28 | + "%6s: bo %8p vpu_addr %9llx size %8zu ctx %d has_pages %d dma_mapped %d mmu_mapped %d wc %d imported %d\n", | |
| 29 | + action, bo, bo->vpu_addr, ivpu_bo_size(bo), bo->ctx ? bo->ctx->id : 0, | |
| 30 | + (bool)bo->base.pages, (bool)bo->base.sgt, bo->mmu_mapped, bo->base.map_wc, | |
| 31 | + (bool)bo->base.base.import_attach); | |
| 35 | 32 | } |
| 36 | 33 | |
| 37 | 34 | /* |
| @@ -49,12 +46,7 @@ int __must_check ivpu_bo_pin(struct ivpu_bo *bo) · 11 unmodified lines | ||
| 49 | 46 | mutex_lock(&bo->lock); |
| 50 | 47 | |
| 51 | 48 | ivpu_dbg_bo(vdev, bo, "pin"); |
| 52 | − | |
| 53 | − if (!bo->ctx) { | |
| 54 | − ivpu_err(vdev, "vpu_addr not allocated for BO %d\n", bo->handle); | |
| 55 | − ret = -EINVAL; | |
| 56 | − goto unlock; | |
| 57 | − } | |
| 49 | + drm_WARN_ON(&vdev->drm, !bo->ctx); | |
| 58 | 50 | |
| 59 | 51 | if (!bo->mmu_mapped) { |
| 60 | 52 | struct sg_table *sgt = drm_gem_shmem_get_pages_sgt(&bo->base); |
| @@ -85,7 +77,10 @@ ivpu_bo_alloc_vpu_addr(struct ivpu_bo *bo, struct ivpu_mmu_context *ctx, · 24 unmodified lines | ||
| 85 | 77 | const struct ivpu_addr_range *range) |
| 86 | 78 | { |
| 87 | 79 | struct ivpu_device *vdev = ivpu_bo_to_vdev(bo); |
| 88 | − int ret; | |
| 80 | + int idx, ret; | |
| 81 | + | |
| 82 | + if (!drm_dev_enter(&vdev->drm, &idx)) | |
| 83 | + return -ENODEV; | |
| 89 | 84 | |
| 90 | 85 | mutex_lock(&bo->lock); |
| 91 | 86 | |
| @@ -101,6 +96,8 @@ ivpu_bo_alloc_vpu_addr(struct ivpu_bo *bo, struct ivpu_mmu_context *ctx, · 9 unmodified lines | ||
| 101 | 96 | |
| 102 | 97 | mutex_unlock(&bo->lock); |
| 103 | 98 | |
| 99 | + drm_dev_exit(idx); | |
| 100 | + | |
| 104 | 101 | return ret; |
| 105 | 102 | } |
| 106 | 103 | |
| @@ -108,11 +105,7 @@ static void ivpu_bo_unbind_locked(struct ivpu_bo *bo) · 1 unmodified line | ||
| 108 | 105 | { |
| 109 | 106 | struct ivpu_device *vdev = ivpu_bo_to_vdev(bo); |
| 110 | 107 | |
| 111 | − lockdep_assert_held(&bo->lock); | |
| 112 | − | |
| 113 | − ivpu_dbg_bo(vdev, bo, "unbind"); | |
| 114 | − | |
| 115 | − /* TODO: dma_unmap */ | |
| 108 | + lockdep_assert(lockdep_is_held(&bo->lock) || !kref_read(&bo->base.base.refcount)); | |
| 116 | 109 | |
| 117 | 110 | if (bo->mmu_mapped) { |
| 118 | 111 | drm_WARN_ON(&vdev->drm, !bo->ctx); |
| @@ -124,19 +117,23 @@ static void ivpu_bo_unbind_locked(struct ivpu_bo *bo) · 5 unmodified lines | ||
| 124 | 117 | |
| 125 | 118 | if (bo->ctx) { |
| 126 | 119 | ivpu_mmu_context_remove_node(bo->ctx, &bo->mm_node); |
| 127 | − bo->vpu_addr = 0; | |
| 128 | 120 | bo->ctx = NULL; |
| 129 | 121 | } |
| 130 | −} | |
| 131 | 122 | |
| 132 | −static void ivpu_bo_unbind(struct ivpu_bo *bo) | |
| 133 | −{ | |
| 134 | − mutex_lock(&bo->lock); | |
| 135 | − ivpu_bo_unbind_locked(bo); | |
| 136 | − mutex_unlock(&bo->lock); | |
| 123 | + if (bo->base.base.import_attach) | |
| 124 | + return; | |
| 125 | + | |
| 126 | + dma_resv_lock(bo->base.base.resv, NULL); | |
| 127 | + if (bo->base.sgt) { | |
| 128 | + dma_unmap_sgtable(vdev->drm.dev, bo->base.sgt, DMA_BIDIRECTIONAL, 0); | |
| 129 | + sg_free_table(bo->base.sgt); | |
| 130 | + kfree(bo->base.sgt); | |
| 131 | + bo->base.sgt = NULL; | |
| 132 | + } | |
| 133 | + dma_resv_unlock(bo->base.base.resv); | |
| 137 | 134 | } |
| 138 | 135 | |
| 139 | −void ivpu_bo_remove_all_bos_from_context(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx) | |
| 136 | +void ivpu_bo_unbind_all_bos_from_context(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx) | |
| 140 | 137 | { |
| 141 | 138 | struct ivpu_bo *bo; |
| 142 | 139 | |
| @@ -146,8 +143,10 @@ void ivpu_bo_remove_all_bos_from_context(struct ivpu_device *vdev, struct ivpu_m · 3 unmodified lines | ||
| 146 | 143 | mutex_lock(&vdev->bo_list_lock); |
| 147 | 144 | list_for_each_entry(bo, &vdev->bo_list, bo_list_node) { |
| 148 | 145 | mutex_lock(&bo->lock); |
| 149 | − if (bo->ctx == ctx) | |
| 146 | + if (bo->ctx == ctx) { | |
| 147 | + ivpu_dbg_bo(vdev, bo, "unbind"); | |
| 150 | 148 | ivpu_bo_unbind_locked(bo); |
| 149 | + } | |
| 151 | 150 | mutex_unlock(&bo->lock); |
| 152 | 151 | } |
| 153 | 152 | mutex_unlock(&vdev->bo_list_lock); |
| @@ -199,9 +198,6 @@ ivpu_bo_create(struct ivpu_device *vdev, u64 size, u32 flags) · 45 unmodified lines | ||
| 199 | 198 | list_add_tail(&bo->bo_list_node, &vdev->bo_list); |
| 200 | 199 | mutex_unlock(&vdev->bo_list_lock); |
| 201 | 200 | |
| 202 | − ivpu_dbg(vdev, BO, "create: vpu_addr 0x%llx size %zu flags 0x%x\n", | |
| 203 | − bo->vpu_addr, bo->base.base.size, flags); | |
| 204 | − | |
| 205 | 201 | return bo; |
| 206 | 202 | } |
| 207 | 203 | |
| @@ -212,6 +208,12 @@ static int ivpu_bo_open(struct drm_gem_object *obj, struct drm_file *file) · 4 unmodified lines | ||
| 212 | 208 | struct ivpu_bo *bo = to_ivpu_bo(obj); |
| 213 | 209 | struct ivpu_addr_range *range; |
| 214 | 210 | |
| 211 | + if (bo->ctx) { | |
| 212 | + ivpu_warn(vdev, "Can't add BO to ctx %u: already in ctx %u\n", | |
| 213 | + file_priv->ctx.id, bo->ctx->id); | |
| 214 | + return -EALREADY; | |
| 215 | + } | |
| 216 | + | |
| 215 | 217 | if (bo->flags & DRM_IVPU_BO_SHAVE_MEM) |
| 216 | 218 | range = &vdev->hw->ranges.shave; |
| 217 | 219 | else if (bo->flags & DRM_IVPU_BO_DMA_MEM) |
| @@ -227,62 +229,24 @@ static void ivpu_bo_free(struct drm_gem_object *obj) · 9 unmodified lines | ||
| 227 | 229 | struct ivpu_device *vdev = to_ivpu_device(obj->dev); |
| 228 | 230 | struct ivpu_bo *bo = to_ivpu_bo(obj); |
| 229 | 231 | |
| 232 | + ivpu_dbg_bo(vdev, bo, "free"); | |
| 233 | + | |
| 230 | 234 | mutex_lock(&vdev->bo_list_lock); |
| 231 | 235 | list_del(&bo->bo_list_node); |
| 232 | 236 | mutex_unlock(&vdev->bo_list_lock); |
| 233 | 237 | |
| 234 | 238 | drm_WARN_ON(&vdev->drm, !dma_resv_test_signaled(obj->resv, DMA_RESV_USAGE_READ)); |
| 235 | 239 | |
| 236 | − ivpu_dbg_bo(vdev, bo, "free"); | |
| 237 | − | |
| 238 | − ivpu_bo_unbind(bo); | |
| 240 | + ivpu_bo_unbind_locked(bo); | |
| 239 | 241 | mutex_destroy(&bo->lock); |
| 240 | 242 | |
| 241 | 243 | drm_WARN_ON(obj->dev, bo->base.pages_use_count > 1); |
| 242 | 244 | drm_gem_shmem_free(&bo->base); |
| 243 | 245 | } |
| 244 | 246 | |
| 245 | −static const struct dma_buf_ops ivpu_bo_dmabuf_ops = { | |
| 246 | − .cache_sgt_mapping = true, | |
| 247 | − .attach = drm_gem_map_attach, | |
| 248 | − .detach = drm_gem_map_detach, | |
| 249 | − .map_dma_buf = drm_gem_map_dma_buf, | |
| 250 | − .unmap_dma_buf = drm_gem_unmap_dma_buf, | |
| 251 | − .release = drm_gem_dmabuf_release, | |
| 252 | − .mmap = drm_gem_dmabuf_mmap, | |
| 253 | − .vmap = drm_gem_dmabuf_vmap, | |
| 254 | − .vunmap = drm_gem_dmabuf_vunmap, | |
| 255 | −}; | |
| 256 | − | |
| 257 | −static struct dma_buf *ivpu_bo_export(struct drm_gem_object *obj, int flags) | |
| 258 | −{ | |
| 259 | − struct drm_device *dev = obj->dev; | |
| 260 | − struct dma_buf_export_info exp_info = { | |
| 261 | − .exp_name = KBUILD_MODNAME, | |
| 262 | − .owner = dev->driver->fops->owner, | |
| 263 | − .ops = &ivpu_bo_dmabuf_ops, | |
| 264 | − .size = obj->size, | |
| 265 | − .flags = flags, | |
| 266 | − .priv = obj, | |
| 267 | − .resv = obj->resv, | |
| 268 | − }; | |
| 269 | − void *sgt; | |
| 270 | − | |
| 271 | − /* | |
| 272 | − * Make sure that pages are allocated and dma-mapped before exporting the bo. | |
| 273 | − * DMA-mapping is required if the bo will be imported to the same device. | |
| 274 | − */ | |
| 275 | − sgt = drm_gem_shmem_get_pages_sgt(to_drm_gem_shmem_obj(obj)); | |
| 276 | − if (IS_ERR(sgt)) | |
| 277 | − return sgt; | |
| 278 | − | |
| 279 | − return drm_gem_dmabuf_export(dev, &exp_info); | |
| 280 | −} | |
| 281 | − | |
| 282 | 247 | static const struct drm_gem_object_funcs ivpu_gem_funcs = { |
| 283 | 248 | .free = ivpu_bo_free, |
| 284 | 249 | .open = ivpu_bo_open, |
| 285 | − .export = ivpu_bo_export, | |
| 286 | 250 | .print_info = drm_gem_shmem_object_print_info, |
| 287 | 251 | .pin = drm_gem_shmem_object_pin, |
| 288 | 252 | .unpin = drm_gem_shmem_object_unpin, |
| @@ -315,11 +279,9 @@ int ivpu_bo_create_ioctl(struct drm_device *dev, void *data, struct drm_file *fi · 26 unmodified lines | ||
| 315 | 279 | return PTR_ERR(bo); |
| 316 | 280 | } |
| 317 | 281 | |
| 318 | − ret = drm_gem_handle_create(file, &bo->base.base, &bo->handle); | |
| 319 | − if (!ret) { | |
| 282 | + ret = drm_gem_handle_create(file, &bo->base.base, &args->handle); | |
| 283 | + if (!ret) | |
| 320 | 284 | args->vpu_addr = bo->vpu_addr; |
| 321 | − args->handle = bo->handle; | |
| 322 | − } | |
| 323 | 285 | |
| 324 | 286 | drm_gem_object_put(&bo->base.base); |
| 325 | 287 | |
| @@ -361,7 +323,9 @@ ivpu_bo_alloc_internal(struct ivpu_device *vdev, u64 vpu_addr, u64 size, u32 fla · 35 unmodified lines | ||
| 361 | 323 | if (ret) |
| 362 | 324 | goto err_put; |
| 363 | 325 | |
| 326 | + dma_resv_lock(bo->base.base.resv, NULL); | |
| 364 | 327 | ret = drm_gem_shmem_vmap(&bo->base, &map); |
| 328 | + dma_resv_unlock(bo->base.base.resv); | |
| 365 | 329 | if (ret) |
| 366 | 330 | goto err_put; |
| 367 | 331 | |
| @@ -376,7 +340,10 @@ void ivpu_bo_free_internal(struct ivpu_bo *bo) · 8 unmodified lines | ||
| 376 | 340 | { |
| 377 | 341 | struct iosys_map map = IOSYS_MAP_INIT_VADDR(bo->base.vaddr); |
| 378 | 342 | |
| 343 | + dma_resv_lock(bo->base.base.resv, NULL); | |
| 379 | 344 | drm_gem_shmem_vunmap(&bo->base, &map); |
| 345 | + dma_resv_unlock(bo->base.base.resv); | |
| 346 | + | |
| 380 | 347 | drm_gem_object_put(&bo->base.base); |
| 381 | 348 | } |
| 382 | 349 | |
| @@ -432,19 +399,11 @@ int ivpu_bo_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file · 49 unmodified lines | ||
| 432 | 399 | |
| 433 | 400 | static void ivpu_bo_print_info(struct ivpu_bo *bo, struct drm_printer *p) |
| 434 | 401 | { |
| 435 | − unsigned long dma_refcount = 0; | |
| 436 | − | |
| 437 | 402 | mutex_lock(&bo->lock); |
| 438 | 403 | |
| 439 | − if (bo->base.base.dma_buf && bo->base.base.dma_buf->file) | |
| 440 | − dma_refcount = atomic_long_read(&bo->base.base.dma_buf->file->f_count); | |
| 441 | − | |
| 442 | − drm_printf(p, "%-3u %-6d 0x%-12llx %-10lu 0x%-8x %-4u %-8lu", | |
| 443 | − bo->ctx->id, bo->handle, bo->vpu_addr, bo->base.base.size, | |
| 444 | − bo->flags, kref_read(&bo->base.base.refcount), dma_refcount); | |
| 445 | − | |
| 446 | − if (bo->base.base.import_attach) | |
| 447 | − drm_printf(p, " imported"); | |
| 404 | + drm_printf(p, "%-9p %-3u 0x%-12llx %-10lu 0x%-8x %-4u", | |
| 405 | + bo, bo->ctx->id, bo->vpu_addr, bo->base.base.size, | |
| 406 | + bo->flags, kref_read(&bo->base.base.refcount)); | |
| 448 | 407 | |
| 449 | 408 | if (bo->base.pages) |
| 450 | 409 | drm_printf(p, " has_pages"); |
| @@ -452,6 +411,9 @@ static void ivpu_bo_print_info(struct ivpu_bo *bo, struct drm_printer *p) · 1 unmodified line | ||
| 452 | 411 | if (bo->mmu_mapped) |
| 453 | 412 | drm_printf(p, " mmu_mapped"); |
| 454 | 413 | |
| 414 | + if (bo->base.base.import_attach) | |
| 415 | + drm_printf(p, " imported"); | |
| 416 | + | |
| 455 | 417 | drm_printf(p, "\n"); |
| 456 | 418 | |
| 457 | 419 | mutex_unlock(&bo->lock); |
| @@ -462,8 +424,8 @@ void ivpu_bo_list(struct drm_device *dev, struct drm_printer *p) · 4 unmodified lines | ||
| 462 | 424 | struct ivpu_device *vdev = to_ivpu_device(dev); |
| 463 | 425 | struct ivpu_bo *bo; |
| 464 | 426 | |
| 465 | − drm_printf(p, "%-3s %-6s %-14s %-10s %-10s %-4s %-8s %s\n", | |
| 466 | − "ctx", "handle", "vpu_addr", "size", "flags", "refs", "dma_refs", "attribs"); | |
| 427 | + drm_printf(p, "%-9s %-3s %-14s %-10s %-10s %-4s %s\n", | |
| 428 | + "bo", "ctx", "vpu_addr", "size", "flags", "refs", "attribs"); | |
| 467 | 429 | |
| 468 | 430 | mutex_lock(&vdev->bo_list_lock); |
| 469 | 431 | list_for_each_entry(bo, &vdev->bo_list, bo_list_node) |
| @@ -19,14 +19,13 @@ struct ivpu_bo { · 18 unmodified lines | ||
| 19 | 19 | |
| 20 | 20 | struct mutex lock; /* Protects: ctx, mmu_mapped, vpu_addr */ |
| 21 | 21 | u64 vpu_addr; |
| 22 | − u32 handle; | |
| 23 | 22 | u32 flags; |
| 24 | 23 | u32 job_status; /* Valid only for command buffer */ |
| 25 | 24 | bool mmu_mapped; |
| 26 | 25 | }; |
| 27 | 26 | |
| 28 | 27 | int ivpu_bo_pin(struct ivpu_bo *bo); |
| 29 | −void ivpu_bo_remove_all_bos_from_context(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx); | |
| 28 | +void ivpu_bo_unbind_all_bos_from_context(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx); | |
| 30 | 29 | |
| 31 | 30 | struct drm_gem_object *ivpu_gem_create_object(struct drm_device *dev, size_t size); |
| 32 | 31 | struct ivpu_bo *ivpu_bo_alloc_internal(struct ivpu_device *vdev, u64 vpu_addr, u64 size, u32 flags); |
| @@ -875,24 +875,18 @@ static void ivpu_hw_37xx_irq_disable(struct ivpu_device *vdev) · 874 unmodified lines | ||
| 875 | 875 | |
| 876 | 876 | static void ivpu_hw_37xx_irq_wdt_nce_handler(struct ivpu_device *vdev) |
| 877 | 877 | { |
| 878 | − ivpu_err_ratelimited(vdev, "WDT NCE irq\n"); | |
| 879 | − | |
| 880 | − ivpu_pm_schedule_recovery(vdev); | |
| 878 | + ivpu_pm_trigger_recovery(vdev, "WDT NCE IRQ"); | |
| 881 | 879 | } |
| 882 | 880 | |
| 883 | 881 | static void ivpu_hw_37xx_irq_wdt_mss_handler(struct ivpu_device *vdev) |
| 884 | 882 | { |
| 885 | − ivpu_err_ratelimited(vdev, "WDT MSS irq\n"); | |
| 886 | − | |
| 887 | 883 | ivpu_hw_wdt_disable(vdev); |
| 888 | − ivpu_pm_schedule_recovery(vdev); | |
| 884 | + ivpu_pm_trigger_recovery(vdev, "WDT MSS IRQ"); | |
| 889 | 885 | } |
| 890 | 886 | |
| 891 | 887 | static void ivpu_hw_37xx_irq_noc_firewall_handler(struct ivpu_device *vdev) |
| 892 | 888 | { |
| 893 | − ivpu_err_ratelimited(vdev, "NOC Firewall irq\n"); | |
| 894 | − | |
| 895 | − ivpu_pm_schedule_recovery(vdev); | |
| 889 | + ivpu_pm_trigger_recovery(vdev, "NOC Firewall IRQ"); | |
| 896 | 890 | } |
| 897 | 891 | |
| 898 | 892 | /* Handler for IRQs from VPU core (irqV) */ |
| @@ -970,7 +964,7 @@ static bool ivpu_hw_37xx_irqb_handler(struct ivpu_device *vdev, int irq) · 71 unmodified lines | ||
| 970 | 964 | REGB_WR32(VPU_37XX_BUTTRESS_INTERRUPT_STAT, status); |
| 971 | 965 | |
| 972 | 966 | if (schedule_recovery) |
| 973 | − ivpu_pm_schedule_recovery(vdev); | |
| 967 | + ivpu_pm_trigger_recovery(vdev, "Buttress IRQ"); | |
| 974 | 968 | |
| 975 | 969 | return true; |
| 976 | 970 | } |
| @@ -746,7 +746,7 @@ static int ivpu_hw_40xx_info_init(struct ivpu_device *vdev) · 745 unmodified lines | ||
| 746 | 746 | return 0; |
| 747 | 747 | } |
| 748 | 748 | |
| 749 | −static int ivpu_hw_40xx_reset(struct ivpu_device *vdev) | |
| 749 | +static int ivpu_hw_40xx_ip_reset(struct ivpu_device *vdev) | |
| 750 | 750 | { |
| 751 | 751 | int ret; |
| 752 | 752 | u32 val; |
| @@ -768,6 +768,23 @@ static int ivpu_hw_40xx_reset(struct ivpu_device *vdev) · 15 unmodified lines | ||
| 768 | 768 | return ret; |
| 769 | 769 | } |
| 770 | 770 | |
| 771 | +static int ivpu_hw_40xx_reset(struct ivpu_device *vdev) | |
| 772 | +{ | |
| 773 | + int ret = 0; | |
| 774 | + | |
| 775 | + if (ivpu_hw_40xx_ip_reset(vdev)) { | |
| 776 | + ivpu_err(vdev, "Failed to reset VPU IP\n"); | |
| 777 | + ret = -EIO; | |
| 778 | + } | |
| 779 | + | |
| 780 | + if (ivpu_pll_disable(vdev)) { | |
| 781 | + ivpu_err(vdev, "Failed to disable PLL\n"); | |
| 782 | + ret = -EIO; | |
| 783 | + } | |
| 784 | + | |
| 785 | + return ret; | |
| 786 | +} | |
| 787 | + | |
| 771 | 788 | static int ivpu_hw_40xx_d0i3_enable(struct ivpu_device *vdev) |
| 772 | 789 | { |
| 773 | 790 | int ret; |
| @@ -913,7 +930,7 @@ static int ivpu_hw_40xx_power_down(struct ivpu_device *vdev) · 139 unmodified lines | ||
| 913 | 930 | |
| 914 | 931 | ivpu_hw_40xx_save_d0i3_entry_timestamp(vdev); |
| 915 | 932 | |
| 916 | − if (!ivpu_hw_40xx_is_idle(vdev) && ivpu_hw_40xx_reset(vdev)) | |
| 933 | + if (!ivpu_hw_40xx_is_idle(vdev) && ivpu_hw_40xx_ip_reset(vdev)) | |
| 917 | 934 | ivpu_warn(vdev, "Failed to reset the VPU\n"); |
| 918 | 935 | |
| 919 | 936 | if (ivpu_pll_disable(vdev)) { |
| @@ -1032,18 +1049,18 @@ static void ivpu_hw_40xx_irq_disable(struct ivpu_device *vdev) · 112 unmodified lines | ||
| 1032 | 1049 | static void ivpu_hw_40xx_irq_wdt_nce_handler(struct ivpu_device *vdev) |
| 1033 | 1050 | { |
| 1034 | 1051 | /* TODO: For LNN hang consider engine reset instead of full recovery */ |
| 1035 | − ivpu_pm_schedule_recovery(vdev); | |
| 1052 | + ivpu_pm_trigger_recovery(vdev, "WDT NCE IRQ"); | |
| 1036 | 1053 | } |
| 1037 | 1054 | |
| 1038 | 1055 | static void ivpu_hw_40xx_irq_wdt_mss_handler(struct ivpu_device *vdev) |
| 1039 | 1056 | { |
| 1040 | 1057 | ivpu_hw_wdt_disable(vdev); |
| 1041 | − ivpu_pm_schedule_recovery(vdev); | |
| 1058 | + ivpu_pm_trigger_recovery(vdev, "WDT MSS IRQ"); | |
| 1042 | 1059 | } |
| 1043 | 1060 | |
| 1044 | 1061 | static void ivpu_hw_40xx_irq_noc_firewall_handler(struct ivpu_device *vdev) |
| 1045 | 1062 | { |
| 1046 | − ivpu_pm_schedule_recovery(vdev); | |
| 1063 | + ivpu_pm_trigger_recovery(vdev, "NOC Firewall IRQ"); | |
| 1047 | 1064 | } |
| 1048 | 1065 | |
| 1049 | 1066 | /* Handler for IRQs from VPU core (irqV) */ |
| @@ -1137,7 +1154,7 @@ static bool ivpu_hw_40xx_irqb_handler(struct ivpu_device *vdev, int irq) · 87 unmodified lines | ||
| 1137 | 1154 | REGB_WR32(VPU_40XX_BUTTRESS_INTERRUPT_STAT, status); |
| 1138 | 1155 | |
| 1139 | 1156 | if (schedule_recovery) |
| 1140 | − ivpu_pm_schedule_recovery(vdev); | |
| 1157 | + ivpu_pm_trigger_recovery(vdev, "Buttress IRQ"); | |
| 1141 | 1158 | |
| 1142 | 1159 | return true; |
| 1143 | 1160 | } |
| @@ -343,10 +343,8 @@ int ivpu_ipc_send_receive_active(struct ivpu_device *vdev, struct vpu_jsm_msg *r · 342 unmodified lines | ||
| 343 | 343 | hb_ret = ivpu_ipc_send_receive_internal(vdev, &hb_req, VPU_JSM_MSG_QUERY_ENGINE_HB_DONE, |
| 344 | 344 | &hb_resp, VPU_IPC_CHAN_ASYNC_CMD, |
| 345 | 345 | vdev->timeout.jsm); |
| 346 | − if (hb_ret == -ETIMEDOUT) { | |
| 347 | − ivpu_hw_diagnose_failure(vdev); | |
| 348 | − ivpu_pm_schedule_recovery(vdev); | |
| 349 | − } | |
| 346 | + if (hb_ret == -ETIMEDOUT) | |
| 347 | + ivpu_pm_trigger_recovery(vdev, "IPC timeout"); | |
| 350 | 348 | |
| 351 | 349 | return ret; |
| 352 | 350 | } |
| @@ -112,22 +112,20 @@ static void ivpu_cmdq_release_locked(struct ivpu_file_priv *file_priv, u16 engin · 111 unmodified lines | ||
| 112 | 112 | } |
| 113 | 113 | } |
| 114 | 114 | |
| 115 | −void ivpu_cmdq_release_all(struct ivpu_file_priv *file_priv) | |
| 115 | +void ivpu_cmdq_release_all_locked(struct ivpu_file_priv *file_priv) | |
| 116 | 116 | { |
| 117 | 117 | int i; |
| 118 | 118 | |
| 119 | − mutex_lock(&file_priv->lock); | |
| 119 | + lockdep_assert_held(&file_priv->lock); | |
| 120 | 120 | |
| 121 | 121 | for (i = 0; i < IVPU_NUM_ENGINES; i++) |
| 122 | 122 | ivpu_cmdq_release_locked(file_priv, i); |
| 123 | − | |
| 124 | − mutex_unlock(&file_priv->lock); | |
| 125 | 123 | } |
| 126 | 124 | |
| 127 | 125 | /* |
| 128 | 126 | * Mark the doorbell as unregistered and reset job queue pointers. |
| 129 | 127 | * This function needs to be called when the VPU hardware is restarted |
| 130 | − * and FW looses job queue state. The next time job queue is used it | |
| 128 | + * and FW loses job queue state. The next time job queue is used it | |
| 131 | 129 | * will be registered again. |
| 132 | 130 | */ |
| 133 | 131 | static void ivpu_cmdq_reset_locked(struct ivpu_file_priv *file_priv, u16 engine) |
| @@ -161,15 +159,13 @@ void ivpu_cmdq_reset_all_contexts(struct ivpu_device *vdev) · 27 unmodified lines | ||
| 161 | 159 | struct ivpu_file_priv *file_priv; |
| 162 | 160 | unsigned long ctx_id; |
| 163 | 161 | |
| 164 | − xa_for_each(&vdev->context_xa, ctx_id, file_priv) { | |
| 165 | − file_priv = ivpu_file_priv_get_by_ctx_id(vdev, ctx_id); | |
| 166 | − if (!file_priv) | |
| 167 | − continue; | |
| 162 | + mutex_lock(&vdev->context_list_lock); | |
| 168 | 163 | |
| 164 | + xa_for_each(&vdev->context_xa, ctx_id, file_priv) | |
| 169 | 165 | ivpu_cmdq_reset_all(file_priv); |
| 170 | 166 | |
| 171 | − ivpu_file_priv_put(&file_priv); | |
| 172 | − } | |
| 167 | + mutex_unlock(&vdev->context_list_lock); | |
| 168 | + | |
| 173 | 169 | } |
| 174 | 170 | |
| 175 | 171 | static int ivpu_cmdq_push_job(struct ivpu_cmdq *cmdq, struct ivpu_job *job) |
| @@ -243,60 +239,32 @@ static struct dma_fence *ivpu_fence_create(struct ivpu_device *vdev) · 67 unmodified lines | ||
| 243 | 239 | return &fence->base; |
| 244 | 240 | } |
| 245 | 241 | |
| 246 | −static void job_get(struct ivpu_job *job, struct ivpu_job **link) | |
| 242 | +static void ivpu_job_destroy(struct ivpu_job *job) | |
| 247 | 243 | { |
| 248 | 244 | struct ivpu_device *vdev = job->vdev; |
| 249 | − | |
| 250 | − kref_get(&job->ref); | |
| 251 | − *link = job; | |
| 252 | − | |
| 253 | − ivpu_dbg(vdev, KREF, "Job get: id %u refcount %u\n", job->job_id, kref_read(&job->ref)); | |
| 254 | −} | |
| 255 | − | |
| 256 | −static void job_release(struct kref *ref) | |
| 257 | −{ | |
| 258 | − struct ivpu_job *job = container_of(ref, struct ivpu_job, ref); | |
| 259 | − struct ivpu_device *vdev = job->vdev; | |
| 260 | 245 | u32 i; |
| 261 | 246 | |
| 247 | + ivpu_dbg(vdev, JOB, "Job destroyed: id %3u ctx %2d engine %d", | |
| 248 | + job->job_id, job->file_priv->ctx.id, job->engine_idx); | |
| 249 | + | |
| 262 | 250 | for (i = 0; i < job->bo_count; i++) |
| 263 | 251 | if (job->bos[i]) |
| 264 | 252 | drm_gem_object_put(&job->bos[i]->base.base); |
| 265 | 253 | |
| 266 | 254 | dma_fence_put(job->done_fence); |
| 267 | 255 | ivpu_file_priv_put(&job->file_priv); |
| 268 | − | |
| 269 | − ivpu_dbg(vdev, KREF, "Job released: id %u\n", job->job_id); | |
| 270 | 256 | kfree(job); |
| 271 | − | |
| 272 | − /* Allow the VPU to get suspended, must be called after ivpu_file_priv_put() */ | |
| 273 | − ivpu_rpm_put(vdev); | |
| 274 | −} | |
| 275 | − | |
| 276 | −static void job_put(struct ivpu_job *job) | |
| 277 | −{ | |
| 278 | − struct ivpu_device *vdev = job->vdev; | |
| 279 | − | |
| 280 | − ivpu_dbg(vdev, KREF, "Job put: id %u refcount %u\n", job->job_id, kref_read(&job->ref)); | |
| 281 | − kref_put(&job->ref, job_release); | |
| 282 | 257 | } |
| 283 | 258 | |
| 284 | 259 | static struct ivpu_job * |
| 285 | −ivpu_create_job(struct ivpu_file_priv *file_priv, u32 engine_idx, u32 bo_count) | |
| 260 | +ivpu_job_create(struct ivpu_file_priv *file_priv, u32 engine_idx, u32 bo_count) | |
| 286 | 261 | { |
| 287 | 262 | struct ivpu_device *vdev = file_priv->vdev; |
| 288 | 263 | struct ivpu_job *job; |
| 289 | − int ret; | |
| 290 | − | |
| 291 | − ret = ivpu_rpm_get(vdev); | |
| 292 | − if (ret < 0) | |
| 293 | − return NULL; | |
| 294 | 264 | |
| 295 | 265 | job = kzalloc(struct_size(job, bos, bo_count), GFP_KERNEL); |
| 296 | 266 | if (!job) |
| 297 | − goto err_rpm_put; | |
| 298 | − | |
| 299 | − kref_init(&job->ref); | |
| 267 | + return NULL; | |
| 300 | 268 | |
| 301 | 269 | job->vdev = vdev; |
| 302 | 270 | job->engine_idx = engine_idx; |
| @@ -310,17 +278,14 @@ ivpu_create_job(struct ivpu_file_priv *file_priv, u32 engine_idx, u32 bo_count) · 7 unmodified lines | ||
| 310 | 278 | job->file_priv = ivpu_file_priv_get(file_priv); |
| 311 | 279 | |
| 312 | 280 | ivpu_dbg(vdev, JOB, "Job created: ctx %2d engine %d", file_priv->ctx.id, job->engine_idx); |
| 313 | − | |
| 314 | 281 | return job; |
| 315 | 282 | |
| 316 | 283 | err_free_job: |
| 317 | 284 | kfree(job); |
| 318 | −err_rpm_put: | |
| 319 | − ivpu_rpm_put(vdev); | |
| 320 | 285 | return NULL; |
| 321 | 286 | } |
| 322 | 287 | |
| 323 | −static int ivpu_job_done(struct ivpu_device *vdev, u32 job_id, u32 job_status) | |
| 288 | +static int ivpu_job_signal_and_destroy(struct ivpu_device *vdev, u32 job_id, u32 job_status) | |
| 324 | 289 | { |
| 325 | 290 | struct ivpu_job *job; |
| 326 | 291 | |
| @@ -337,9 +302,10 @@ static int ivpu_job_done(struct ivpu_device *vdev, u32 job_id, u32 job_status) · 10 unmodified lines | ||
| 337 | 302 | ivpu_dbg(vdev, JOB, "Job complete: id %3u ctx %2d engine %d status 0x%x\n", |
| 338 | 303 | job->job_id, job->file_priv->ctx.id, job->engine_idx, job_status); |
| 339 | 304 | |
| 305 | + ivpu_job_destroy(job); | |
| 340 | 306 | ivpu_stop_job_timeout_detection(vdev); |
| 341 | 307 | |
| 342 | − job_put(job); | |
| 308 | + ivpu_rpm_put(vdev); | |
| 343 | 309 | return 0; |
| 344 | 310 | } |
| 345 | 311 | |
| @@ -349,10 +315,10 @@ void ivpu_jobs_abort_all(struct ivpu_device *vdev) · 3 unmodified lines | ||
| 349 | 315 | unsigned long id; |
| 350 | 316 | |
| 351 | 317 | xa_for_each(&vdev->submitted_jobs_xa, id, job) |
| 352 | − ivpu_job_done(vdev, id, VPU_JSM_STATUS_ABORTED); | |
| 318 | + ivpu_job_signal_and_destroy(vdev, id, VPU_JSM_STATUS_ABORTED); | |
| 353 | 319 | } |
| 354 | 320 | |
| 355 | −static int ivpu_direct_job_submission(struct ivpu_job *job) | |
| 321 | +static int ivpu_job_submit(struct ivpu_job *job) | |
| 356 | 322 | { |
| 357 | 323 | struct ivpu_file_priv *file_priv = job->file_priv; |
| 358 | 324 | struct ivpu_device *vdev = job->vdev; |
| @@ -360,53 +326,65 @@ static int ivpu_direct_job_submission(struct ivpu_job *job) · 1 unmodified line | ||
| 360 | 326 | struct ivpu_cmdq *cmdq; |
| 361 | 327 | int ret; |
| 362 | 328 | |
| 329 | + ret = ivpu_rpm_get(vdev); | |
| 330 | + if (ret < 0) | |
| 331 | + return ret; | |
| 332 | + | |
| 363 | 333 | mutex_lock(&file_priv->lock); |
| 364 | 334 | |
| 365 | 335 | cmdq = ivpu_cmdq_acquire(job->file_priv, job->engine_idx); |
| 366 | 336 | if (!cmdq) { |
| 367 | − ivpu_warn(vdev, "Failed get job queue, ctx %d engine %d\n", | |
| 368 | − file_priv->ctx.id, job->engine_idx); | |
| 337 | + ivpu_warn_ratelimited(vdev, "Failed get job queue, ctx %d engine %d\n", | |
| 338 | + file_priv->ctx.id, job->engine_idx); | |
| 369 | 339 | ret = -EINVAL; |
| 370 | − goto err_unlock; | |
| 340 | + goto err_unlock_file_priv; | |
| 371 | 341 | } |
| 372 | 342 | |
| 373 | 343 | job_id_range.min = FIELD_PREP(JOB_ID_CONTEXT_MASK, (file_priv->ctx.id - 1)); |
| 374 | 344 | job_id_range.max = job_id_range.min | JOB_ID_JOB_MASK; |
| 375 | 345 | |
| 376 | − job_get(job, &job); | |
| 377 | − ret = xa_alloc(&vdev->submitted_jobs_xa, &job->job_id, job, job_id_range, GFP_KERNEL); | |
| 346 | + xa_lock(&vdev->submitted_jobs_xa); | |
| 347 | + ret = __xa_alloc(&vdev->submitted_jobs_xa, &job->job_id, job, job_id_range, GFP_KERNEL); | |
| 378 | 348 | if (ret) { |
| 379 | − ivpu_warn_ratelimited(vdev, "Failed to allocate job id: %d\n", ret); | |
| 380 | − goto err_job_put; | |
| 349 | + ivpu_dbg(vdev, JOB, "Too many active jobs in ctx %d\n", | |
| 350 | + file_priv->ctx.id); | |
| 351 | + ret = -EBUSY; | |
| 352 | + goto err_unlock_submitted_jobs_xa; | |
| 381 | 353 | } |
| 382 | 354 | |
| 383 | 355 | ret = ivpu_cmdq_push_job(cmdq, job); |
| 384 | 356 | if (ret) |
| 385 | − goto err_xa_erase; | |
| 357 | + goto err_erase_xa; | |
| 386 | 358 | |
| 387 | 359 | ivpu_start_job_timeout_detection(vdev); |
| 388 | 360 | |
| 389 | − ivpu_dbg(vdev, JOB, "Job submitted: id %3u addr 0x%llx ctx %2d engine %d next %d\n", | |
| 390 | − job->job_id, job->cmd_buf_vpu_addr, file_priv->ctx.id, | |
| 391 | − job->engine_idx, cmdq->jobq->header.tail); | |
| 392 | − | |
| 393 | − if (ivpu_test_mode & IVPU_TEST_MODE_NULL_HW) { | |
| 394 | − ivpu_job_done(vdev, job->job_id, VPU_JSM_STATUS_SUCCESS); | |
| 361 | + if (unlikely(ivpu_test_mode & IVPU_TEST_MODE_NULL_HW)) { | |
| 395 | 362 | cmdq->jobq->header.head = cmdq->jobq->header.tail; |
| 396 | 363 | wmb(); /* Flush WC buffer for jobq header */ |
| 397 | 364 | } else { |
| 398 | 365 | ivpu_cmdq_ring_db(vdev, cmdq); |
| 399 | 366 | } |
| 400 | 367 | |
| 368 | + ivpu_dbg(vdev, JOB, "Job submitted: id %3u ctx %2d engine %d addr 0x%llx next %d\n", | |
| 369 | + job->job_id, file_priv->ctx.id, job->engine_idx, | |
| 370 | + job->cmd_buf_vpu_addr, cmdq->jobq->header.tail); | |
| 371 | + | |
| 372 | + xa_unlock(&vdev->submitted_jobs_xa); | |
| 373 | + | |
| 401 | 374 | mutex_unlock(&file_priv->lock); |
| 375 | + | |
| 376 | + if (unlikely(ivpu_test_mode & IVPU_TEST_MODE_NULL_HW)) | |
| 377 | + ivpu_job_signal_and_destroy(vdev, job->job_id, VPU_JSM_STATUS_SUCCESS); | |
| 378 | + | |
| 402 | 379 | return 0; |
| 403 | 380 | |
| 404 | −err_xa_erase: | |
| 405 | − xa_erase(&vdev->submitted_jobs_xa, job->job_id); | |
| 406 | −err_job_put: | |
| 407 | − job_put(job); | |
| 408 | −err_unlock: | |
| 381 | +err_erase_xa: | |
| 382 | + __xa_erase(&vdev->submitted_jobs_xa, job->job_id); | |
| 383 | +err_unlock_submitted_jobs_xa: | |
| 384 | + xa_unlock(&vdev->submitted_jobs_xa); | |
| 385 | +err_unlock_file_priv: | |
| 409 | 386 | mutex_unlock(&file_priv->lock); |
| 387 | + ivpu_rpm_put(vdev); | |
| 410 | 388 | return ret; |
| 411 | 389 | } |
| 412 | 390 | |
| @@ -488,6 +466,9 @@ int ivpu_submit_ioctl(struct drm_device *dev, void *data, struct drm_file *file) · 75 unmodified lines | ||
| 488 | 466 | if (params->engine > DRM_IVPU_ENGINE_COPY) |
| 489 | 467 | return -EINVAL; |
| 490 | 468 | |
| 469 | + if (params->priority > DRM_IVPU_JOB_PRIORITY_REALTIME) | |
| 470 | + return -EINVAL; | |
| 471 | + | |
| 491 | 472 | if (params->buffer_count == 0 || params->buffer_count > JOB_MAX_BUFFER_COUNT) |
| 492 | 473 | return -EINVAL; |
| 493 | 474 | |
| @@ -509,44 +490,49 @@ int ivpu_submit_ioctl(struct drm_device *dev, void *data, struct drm_file *file) · 15 unmodified lines | ||
| 509 | 490 | params->buffer_count * sizeof(u32)); |
| 510 | 491 | if (ret) { |
| 511 | 492 | ret = -EFAULT; |
| 512 | − goto free_handles; | |
| 493 | + goto err_free_handles; | |
| 513 | 494 | } |
| 514 | 495 | |
| 515 | 496 | if (!drm_dev_enter(&vdev->drm, &idx)) { |
| 516 | 497 | ret = -ENODEV; |
| 517 | − goto free_handles; | |
| 498 | + goto err_free_handles; | |
| 518 | 499 | } |
| 519 | 500 | |
| 520 | 501 | ivpu_dbg(vdev, JOB, "Submit ioctl: ctx %u buf_count %u\n", |
| 521 | 502 | file_priv->ctx.id, params->buffer_count); |
| 522 | 503 | |
| 523 | − job = ivpu_create_job(file_priv, params->engine, params->buffer_count); | |
| 504 | + job = ivpu_job_create(file_priv, params->engine, params->buffer_count); | |
| 524 | 505 | if (!job) { |
| 525 | 506 | ivpu_err(vdev, "Failed to create job\n"); |
| 526 | 507 | ret = -ENOMEM; |
| 527 | − goto dev_exit; | |
| 508 | + goto err_exit_dev; | |
| 528 | 509 | } |
| 529 | 510 | |
| 530 | 511 | ret = ivpu_job_prepare_bos_for_submit(file, job, buf_handles, params->buffer_count, |
| 531 | 512 | params->commands_offset); |
| 532 | 513 | if (ret) { |
| 533 | − ivpu_err(vdev, "Failed to prepare job, ret %d\n", ret); | |
| 534 | − goto job_put; | |
| 514 | + ivpu_err(vdev, "Failed to prepare job: %d\n", ret); | |
| 515 | + goto err_destroy_job; | |
| 535 | 516 | } |
| 536 | 517 | |
| 537 | − ret = ivpu_direct_job_submission(job); | |
| 538 | − if (ret) { | |
| 539 | − dma_fence_signal(job->done_fence); | |
| 540 | − ivpu_err(vdev, "Failed to submit job to the HW, ret %d\n", ret); | |
| 541 | − } | |
| 518 | + down_read(&vdev->pm->reset_lock); | |
| 519 | + ret = ivpu_job_submit(job); | |
| 520 | + up_read(&vdev->pm->reset_lock); | |
| 521 | + if (ret) | |
| 522 | + goto err_signal_fence; | |
| 542 | 523 | |
| 543 | −job_put: | |
| 544 | − job_put(job); | |
| 545 | −dev_exit: | |
| 546 | 524 | drm_dev_exit(idx); |
| 547 | −free_handles: | |
| 548 | 525 | kfree(buf_handles); |
| 526 | + return ret; | |
| 549 | 527 | |
| 528 | +err_signal_fence: | |
| 529 | + dma_fence_signal(job->done_fence); | |
| 530 | +err_destroy_job: | |
| 531 | + ivpu_job_destroy(job); | |
| 532 | +err_exit_dev: | |
| 533 | + drm_dev_exit(idx); | |
| 534 | +err_free_handles: | |
| 535 | + kfree(buf_handles); | |
| 550 | 536 | return ret; |
| 551 | 537 | } |
| 552 | 538 | |
| @@ -568,7 +554,7 @@ ivpu_job_done_callback(struct ivpu_device *vdev, struct ivpu_ipc_hdr *ipc_hdr, · 15 unmodified lines | ||
| 568 | 554 | } |
| 569 | 555 | |
| 570 | 556 | payload = (struct vpu_ipc_msg_payload_job_done *)&jsm_msg->payload; |
| 571 | − ret = ivpu_job_done(vdev, payload->job_id, payload->job_status); | |
| 557 | + ret = ivpu_job_signal_and_destroy(vdev, payload->job_id, payload->job_status); | |
| 572 | 558 | if (!ret && !xa_empty(&vdev->submitted_jobs_xa)) |
| 573 | 559 | ivpu_start_job_timeout_detection(vdev); |
| 574 | 560 | } |
| @@ -43,7 +43,6 @@ struct ivpu_cmdq { · 42 unmodified lines | ||
| 43 | 43 | will update the job status |
| 44 | 44 | */ |
| 45 | 45 | struct ivpu_job { |
| 46 | − struct kref ref; | |
| 47 | 46 | struct ivpu_device *vdev; |
| 48 | 47 | struct ivpu_file_priv *file_priv; |
| 49 | 48 | struct dma_fence *done_fence; |
| @@ -56,7 +55,7 @@ struct ivpu_job { · 6 unmodified lines | ||
| 56 | 55 | |
| 57 | 56 | int ivpu_submit_ioctl(struct drm_device *dev, void *data, struct drm_file *file); |
| 58 | 57 | |
| 59 | −void ivpu_cmdq_release_all(struct ivpu_file_priv *file_priv); | |
| 58 | +void ivpu_cmdq_release_all_locked(struct ivpu_file_priv *file_priv); | |
| 60 | 59 | void ivpu_cmdq_reset_all_contexts(struct ivpu_device *vdev); |
| 61 | 60 | |
| 62 | 61 | void ivpu_job_done_consumer_init(struct ivpu_device *vdev); |
| @@ -7,6 +7,7 @@ · 6 unmodified lines | ||
| 7 | 7 | #include <linux/highmem.h> |
| 8 | 8 | |
| 9 | 9 | #include "ivpu_drv.h" |
| 10 | +#include "ivpu_hw.h" | |
| 10 | 11 | #include "ivpu_hw_reg_io.h" |
| 11 | 12 | #include "ivpu_mmu.h" |
| 12 | 13 | #include "ivpu_mmu_context.h" |
| @@ -518,6 +519,7 @@ static int ivpu_mmu_cmdq_sync(struct ivpu_device *vdev) · 505 unmodified lines | ||
| 518 | 519 | |
| 519 | 520 | ivpu_err(vdev, "Timed out waiting for MMU consumer: %d, error: %s\n", ret, |
| 520 | 521 | ivpu_mmu_cmdq_err_to_str(err)); |
| 522 | + ivpu_hw_diagnose_failure(vdev); | |
| 521 | 523 | } |
| 522 | 524 | |
| 523 | 525 | return ret; |
| @@ -885,7 +887,6 @@ static u32 *ivpu_mmu_get_event(struct ivpu_device *vdev) · 361 unmodified lines | ||
| 885 | 887 | |
| 886 | 888 | void ivpu_mmu_irq_evtq_handler(struct ivpu_device *vdev) |
| 887 | 889 | { |
| 888 | − bool schedule_recovery = false; | |
| 889 | 890 | u32 *event; |
| 890 | 891 | u32 ssid; |
| 891 | 892 | |
| @@ -895,14 +896,21 @@ void ivpu_mmu_irq_evtq_handler(struct ivpu_device *vdev) · 3 unmodified lines | ||
| 895 | 896 | ivpu_mmu_dump_event(vdev, event); |
| 896 | 897 | |
| 897 | 898 | ssid = FIELD_GET(IVPU_MMU_EVT_SSID_MASK, event[0]); |
| 898 | − if (ssid == IVPU_GLOBAL_CONTEXT_MMU_SSID) | |
| 899 | − schedule_recovery = true; | |
| 900 | − else | |
| 901 | − ivpu_mmu_user_context_mark_invalid(vdev, ssid); | |
| 899 | + if (ssid == IVPU_GLOBAL_CONTEXT_MMU_SSID) { | |
| 900 | + ivpu_pm_trigger_recovery(vdev, "MMU event"); | |
| 901 | + return; | |
| 902 | + } | |
| 903 | + | |
| 904 | + ivpu_mmu_user_context_mark_invalid(vdev, ssid); | |
| 902 | 905 | } |
| 906 | +} | |
| 903 | 907 | |
| 904 | − if (schedule_recovery) | |
| 905 | − ivpu_pm_schedule_recovery(vdev); | |
| 908 | +void ivpu_mmu_evtq_dump(struct ivpu_device *vdev) | |
| 909 | +{ | |
| 910 | + u32 *event; | |
| 911 | + | |
| 912 | + while ((event = ivpu_mmu_get_event(vdev)) != NULL) | |
| 913 | + ivpu_mmu_dump_event(vdev, event); | |
| 906 | 914 | } |
| 907 | 915 | |
| 908 | 916 | void ivpu_mmu_irq_gerr_handler(struct ivpu_device *vdev) |
| @@ -46,5 +46,6 @@ int ivpu_mmu_invalidate_tlb(struct ivpu_device *vdev, u16 ssid); · 45 unmodified lines | ||
| 46 | 46 | |
| 47 | 47 | void ivpu_mmu_irq_evtq_handler(struct ivpu_device *vdev); |
| 48 | 48 | void ivpu_mmu_irq_gerr_handler(struct ivpu_device *vdev); |
| 49 | +void ivpu_mmu_evtq_dump(struct ivpu_device *vdev); | |
| 49 | 50 | |
| 50 | 51 | #endif /* __IVPU_MMU_H__ */ |
| @@ -355,6 +355,9 @@ ivpu_mmu_context_map_sgt(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx, · 354 unmodified lines | ||
| 355 | 355 | dma_addr_t dma_addr = sg_dma_address(sg) - sg->offset; |
| 356 | 356 | size_t size = sg_dma_len(sg) + sg->offset; |
| 357 | 357 | |
| 358 | + ivpu_dbg(vdev, MMU_MAP, "Map ctx: %u dma_addr: 0x%llx vpu_addr: 0x%llx size: %lu\n", | |
| 359 | + ctx->id, dma_addr, vpu_addr, size); | |
| 360 | + | |
| 358 | 361 | ret = ivpu_mmu_context_map_pages(vdev, ctx, vpu_addr, dma_addr, size, prot); |
| 359 | 362 | if (ret) { |
| 360 | 363 | ivpu_err(vdev, "Failed to map context pages\n"); |
| @@ -366,6 +369,7 @@ ivpu_mmu_context_map_sgt(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx, · 5 unmodified lines | ||
| 366 | 369 | |
| 367 | 370 | /* Ensure page table modifications are flushed from wc buffers to memory */ |
| 368 | 371 | wmb(); |
| 372 | + | |
| 369 | 373 | mutex_unlock(&ctx->lock); |
| 370 | 374 | |
| 371 | 375 | ret = ivpu_mmu_invalidate_tlb(vdev, ctx->id); |
| @@ -388,14 +392,19 @@ ivpu_mmu_context_unmap_sgt(struct ivpu_device *vdev, struct ivpu_mmu_context *ct · 16 unmodified lines | ||
| 388 | 392 | mutex_lock(&ctx->lock); |
| 389 | 393 | |
| 390 | 394 | for_each_sgtable_dma_sg(sgt, sg, i) { |
| 395 | + dma_addr_t dma_addr = sg_dma_address(sg) - sg->offset; | |
| 391 | 396 | size_t size = sg_dma_len(sg) + sg->offset; |
| 392 | 397 | |
| 398 | + ivpu_dbg(vdev, MMU_MAP, "Unmap ctx: %u dma_addr: 0x%llx vpu_addr: 0x%llx size: %lu\n", | |
| 399 | + ctx->id, dma_addr, vpu_addr, size); | |
| 400 | + | |
| 393 | 401 | ivpu_mmu_context_unmap_pages(ctx, vpu_addr, size); |
| 394 | 402 | vpu_addr += size; |
| 395 | 403 | } |
| 396 | 404 | |
| 397 | 405 | /* Ensure page table modifications are flushed from wc buffers to memory */ |
| 398 | 406 | wmb(); |
| 407 | + | |
| 399 | 408 | mutex_unlock(&ctx->lock); |
| 400 | 409 | |
| 401 | 410 | ret = ivpu_mmu_invalidate_tlb(vdev, ctx->id); |
| @@ -13,6 +13,7 @@ · 12 unmodified lines | ||
| 13 | 13 | #include "ivpu_drv.h" |
| 14 | 14 | #include "ivpu_hw.h" |
| 15 | 15 | #include "ivpu_fw.h" |
| 16 | +#include "ivpu_fw_log.h" | |
| 16 | 17 | #include "ivpu_ipc.h" |
| 17 | 18 | #include "ivpu_job.h" |
| 18 | 19 | #include "ivpu_jsm_msg.h" |
| @@ -111,6 +112,14 @@ static void ivpu_pm_recovery_work(struct work_struct *work) · 92 unmodified lines | ||
| 111 | 112 | char *evt[2] = {"IVPU_PM_EVENT=IVPU_RECOVER", NULL}; |
| 112 | 113 | int ret; |
| 113 | 114 | |
| 115 | + ivpu_err(vdev, "Recovering the VPU (reset #%d)\n", atomic_read(&vdev->pm->reset_counter)); | |
| 116 | + | |
| 117 | + ret = pm_runtime_resume_and_get(vdev->drm.dev); | |
| 118 | + if (ret) | |
| 119 | + ivpu_err(vdev, "Failed to resume VPU: %d\n", ret); | |
| 120 | + | |
| 121 | + ivpu_fw_log_dump(vdev); | |
| 122 | + | |
| 114 | 123 | retry: |
| 115 | 124 | ret = pci_try_reset_function(to_pci_dev(vdev->drm.dev)); |
| 116 | 125 | if (ret == -EAGAIN && !drm_dev_is_unplugged(&vdev->drm)) { |
| @@ -122,11 +131,13 @@ retry: · 5 unmodified lines | ||
| 122 | 131 | ivpu_err(vdev, "Failed to reset VPU: %d\n", ret); |
| 123 | 132 | |
| 124 | 133 | kobject_uevent_env(&vdev->drm.dev->kobj, KOBJ_CHANGE, evt); |
| 134 | + pm_runtime_mark_last_busy(vdev->drm.dev); | |
| 135 | + pm_runtime_put_autosuspend(vdev->drm.dev); | |
| 125 | 136 | } |
| 126 | 137 | |
| 127 | −void ivpu_pm_schedule_recovery(struct ivpu_device *vdev) | |
| 138 | +void ivpu_pm_trigger_recovery(struct ivpu_device *vdev, const char *reason) | |
| 128 | 139 | { |
| 129 | − struct ivpu_pm_info *pm = vdev->pm; | |
| 140 | + ivpu_err(vdev, "Recovery triggered by %s\n", reason); | |
| 130 | 141 | |
| 131 | 142 | if (ivpu_disable_recovery) { |
| 132 | 143 | ivpu_err(vdev, "Recovery not available when disable_recovery param is set\n"); |
| @@ -138,10 +149,11 @@ void ivpu_pm_schedule_recovery(struct ivpu_device *vdev) · 5 unmodified lines | ||
| 138 | 149 | return; |
| 139 | 150 | } |
| 140 | 151 | |
| 141 | − /* Schedule recovery if it's not in progress */ | |
| 142 | − if (atomic_cmpxchg(&pm->in_reset, 0, 1) == 0) { | |
| 143 | − ivpu_hw_irq_disable(vdev); | |
| 144 | − queue_work(system_long_wq, &pm->recovery_work); | |
| 152 | + /* Trigger recovery if it's not in progress */ | |
| 153 | + if (atomic_cmpxchg(&vdev->pm->reset_pending, 0, 1) == 0) { | |
| 154 | + ivpu_hw_diagnose_failure(vdev); | |
| 155 | + ivpu_hw_irq_disable(vdev); /* Disable IRQ early to protect from IRQ storm */ | |
| 156 | + queue_work(system_long_wq, &vdev->pm->recovery_work); | |
| 145 | 157 | } |
| 146 | 158 | } |
| 147 | 159 | |
| @@ -149,12 +161,8 @@ static void ivpu_job_timeout_work(struct work_struct *work) · 1 unmodified line | ||
| 149 | 161 | { |
| 150 | 162 | struct ivpu_pm_info *pm = container_of(work, struct ivpu_pm_info, job_timeout_work.work); |
| 151 | 163 | struct ivpu_device *vdev = pm->vdev; |
| 152 | − unsigned long timeout_ms = ivpu_tdr_timeout_ms ? ivpu_tdr_timeout_ms : vdev->timeout.tdr; | |
| 153 | 164 | |
| 154 | − ivpu_err(vdev, "TDR detected, timeout %lu ms", timeout_ms); | |
| 155 | − ivpu_hw_diagnose_failure(vdev); | |
| 156 | − | |
| 157 | − ivpu_pm_schedule_recovery(vdev); | |
| 165 | + ivpu_pm_trigger_recovery(vdev, "TDR"); | |
| 158 | 166 | } |
| 159 | 167 | |
| 160 | 168 | void ivpu_start_job_timeout_detection(struct ivpu_device *vdev) |
| @@ -227,6 +235,9 @@ int ivpu_pm_runtime_suspend_cb(struct device *dev) · 66 unmodified lines | ||
| 227 | 235 | bool hw_is_idle = true; |
| 228 | 236 | int ret; |
| 229 | 237 | |
| 238 | + drm_WARN_ON(&vdev->drm, !xa_empty(&vdev->submitted_jobs_xa)); | |
| 239 | + drm_WARN_ON(&vdev->drm, work_pending(&vdev->pm->recovery_work)); | |
| 240 | + | |
| 230 | 241 | ivpu_dbg(vdev, PM, "Runtime suspend..\n"); |
| 231 | 242 | |
| 232 | 243 | if (!ivpu_hw_is_idle(vdev) && vdev->pm->suspend_reschedule_counter) { |
| @@ -247,7 +258,8 @@ int ivpu_pm_runtime_suspend_cb(struct device *dev) · 14 unmodified lines | ||
| 247 | 258 | ivpu_err(vdev, "Failed to set suspend VPU: %d\n", ret); |
| 248 | 259 | |
| 249 | 260 | if (!hw_is_idle) { |
| 250 | − ivpu_warn(vdev, "VPU failed to enter idle, force suspended.\n"); | |
| 261 | + ivpu_err(vdev, "VPU failed to enter idle, force suspended.\n"); | |
| 262 | + ivpu_fw_log_dump(vdev); | |
| 251 | 263 | ivpu_pm_prepare_cold_boot(vdev); |
| 252 | 264 | } else { |
| 253 | 265 | ivpu_pm_prepare_warm_boot(vdev); |
| @@ -308,11 +320,12 @@ void ivpu_pm_reset_prepare_cb(struct pci_dev *pdev) · 54 unmodified lines | ||
| 308 | 320 | { |
| 309 | 321 | struct ivpu_device *vdev = pci_get_drvdata(pdev); |
| 310 | 322 | |
| 311 | − pm_runtime_get_sync(vdev->drm.dev); | |
| 312 | − | |
| 313 | 323 | ivpu_dbg(vdev, PM, "Pre-reset..\n"); |
| 314 | 324 | atomic_inc(&vdev->pm->reset_counter); |
| 315 | − atomic_set(&vdev->pm->in_reset, 1); | |
| 325 | + atomic_set(&vdev->pm->reset_pending, 1); | |
| 326 | + | |
| 327 | + pm_runtime_get_sync(vdev->drm.dev); | |
| 328 | + down_write(&vdev->pm->reset_lock); | |
| 316 | 329 | ivpu_prepare_for_reset(vdev); |
| 317 | 330 | ivpu_hw_reset(vdev); |
| 318 | 331 | ivpu_pm_prepare_cold_boot(vdev); |
| @@ -329,9 +342,11 @@ void ivpu_pm_reset_done_cb(struct pci_dev *pdev) · 10 unmodified lines | ||
| 329 | 342 | ret = ivpu_resume(vdev); |
| 330 | 343 | if (ret) |
| 331 | 344 | ivpu_err(vdev, "Failed to set RESUME state: %d\n", ret); |
| 332 | − atomic_set(&vdev->pm->in_reset, 0); | |
| 345 | + up_write(&vdev->pm->reset_lock); | |
| 346 | + atomic_set(&vdev->pm->reset_pending, 0); | |
| 333 | 347 | ivpu_dbg(vdev, PM, "Post-reset done.\n"); |
| 334 | 348 | |
| 349 | + pm_runtime_mark_last_busy(vdev->drm.dev); | |
| 335 | 350 | pm_runtime_put_autosuspend(vdev->drm.dev); |
| 336 | 351 | } |
| 337 | 352 | |
| @@ -344,7 +359,10 @@ void ivpu_pm_init(struct ivpu_device *vdev) · 6 unmodified lines | ||
| 344 | 359 | pm->vdev = vdev; |
| 345 | 360 | pm->suspend_reschedule_counter = PM_RESCHEDULE_LIMIT; |
| 346 | 361 | |
| 347 | − atomic_set(&pm->in_reset, 0); | |
| 362 | + init_rwsem(&pm->reset_lock); | |
| 363 | + atomic_set(&pm->reset_pending, 0); | |
| 364 | + atomic_set(&pm->reset_counter, 0); | |
| 365 | + | |
| 348 | 366 | INIT_WORK(&pm->recovery_work, ivpu_pm_recovery_work); |
| 349 | 367 | INIT_DELAYED_WORK(&pm->job_timeout_work, ivpu_job_timeout_work); |
| 350 | 368 | |
| @@ -6,6 +6,7 @@ · 5 unmodified lines | ||
| 6 | 6 | #ifndef __IVPU_PM_H__ |
| 7 | 7 | #define __IVPU_PM_H__ |
| 8 | 8 | |
| 9 | +#include <linux/rwsem.h> | |
| 9 | 10 | #include <linux/types.h> |
| 10 | 11 | |
| 11 | 12 | struct ivpu_device; |
| @@ -14,8 +15,9 @@ struct ivpu_pm_info { · 2 unmodified lines | ||
| 14 | 15 | struct ivpu_device *vdev; |
| 15 | 16 | struct delayed_work job_timeout_work; |
| 16 | 17 | struct work_struct recovery_work; |
| 17 | − atomic_t in_reset; | |
| 18 | + struct rw_semaphore reset_lock; | |
| 18 | 19 | atomic_t reset_counter; |
| 20 | + atomic_t reset_pending; | |
| 19 | 21 | bool is_warmboot; |
| 20 | 22 | u32 suspend_reschedule_counter; |
| 21 | 23 | }; |
| @@ -37,7 +39,7 @@ int __must_check ivpu_rpm_get(struct ivpu_device *vdev); · 15 unmodified lines | ||
| 37 | 39 | int __must_check ivpu_rpm_get_if_active(struct ivpu_device *vdev); |
| 38 | 40 | void ivpu_rpm_put(struct ivpu_device *vdev); |
| 39 | 41 | |
| 40 | −void ivpu_pm_schedule_recovery(struct ivpu_device *vdev); | |
| 42 | +void ivpu_pm_trigger_recovery(struct ivpu_device *vdev, const char *reason); | |
| 41 | 43 | void ivpu_start_job_timeout_detection(struct ivpu_device *vdev); |
| 42 | 44 | void ivpu_stop_job_timeout_detection(struct ivpu_device *vdev); |
| 43 | 45 | |
| @@ -358,8 +358,8 @@ static struct mhi_channel_config aic100_channels[] = { · 357 unmodified lines | ||
| 358 | 358 | .wake_capable = false, |
| 359 | 359 | }, |
| 360 | 360 | { |
| 361 | − .num = 21, | |
| 362 | 361 | .name = "QAIC_TIMESYNC", |
| 362 | + .num = 21, | |
| 363 | 363 | .num_elements = 32, |
| 364 | 364 | .local_elements = 0, |
| 365 | 365 | .event_ring = 0, |
| @@ -390,8 +390,8 @@ static struct mhi_channel_config aic100_channels[] = { · 24 unmodified lines | ||
| 390 | 390 | .wake_capable = false, |
| 391 | 391 | }, |
| 392 | 392 | { |
| 393 | − .num = 23, | |
| 394 | 393 | .name = "QAIC_TIMESYNC_PERIODIC", |
| 394 | + .num = 23, | |
| 395 | 395 | .num_elements = 32, |
| 396 | 396 | .local_elements = 0, |
| 397 | 397 | .event_ring = 0, |
| @@ -30,6 +30,7 @@ · 29 unmodified lines | ||
| 30 | 30 | #define to_qaic_drm_device(dev) container_of(dev, struct qaic_drm_device, drm) |
| 31 | 31 | #define to_drm(qddev) (&(qddev)->drm) |
| 32 | 32 | #define to_accel_kdev(qddev) (to_drm(qddev)->accel->kdev) /* Return Linux device of accel node */ |
| 33 | +#define to_qaic_device(dev) (to_qaic_drm_device((dev))->qdev) | |
| 33 | 34 | |
| 34 | 35 | enum __packed dev_states { |
| 35 | 36 | /* Device is offline or will be very soon */ |
| @@ -191,8 +192,6 @@ struct qaic_bo { · 155 unmodified lines | ||
| 191 | 192 | u32 nr_slice; |
| 192 | 193 | /* Number of slice that have been transferred by DMA engine */ |
| 193 | 194 | u32 nr_slice_xfer_done; |
| 194 | − /* true = BO is queued for execution, true = BO is not queued */ | |
| 195 | − bool queued; | |
| 196 | 195 | /* |
| 197 | 196 | * If true then user has attached slicing information to this BO by |
| 198 | 197 | * calling DRM_IOCTL_QAIC_ATTACH_SLICE_BO ioctl. |
| @@ -141,6 +141,11 @@ struct dbc_rsp { · 140 unmodified lines | ||
| 141 | 141 | __le16 status; |
| 142 | 142 | } __packed; |
| 143 | 143 | |
| 144 | +static inline bool bo_queued(struct qaic_bo *bo) | |
| 145 | +{ | |
| 146 | + return !list_empty(&bo->xfer_list); | |
| 147 | +} | |
| 148 | + | |
| 144 | 149 | inline int get_dbc_req_elem_size(void) |
| 145 | 150 | { |
| 146 | 151 | return sizeof(struct dbc_req); |
| @@ -569,6 +574,9 @@ static void qaic_free_sgt(struct sg_table *sgt) · 422 unmodified lines | ||
| 569 | 574 | { |
| 570 | 575 | struct scatterlist *sg; |
| 571 | 576 | |
| 577 | + if (!sgt) | |
| 578 | + return; | |
| 579 | + | |
| 572 | 580 | for (sg = sgt->sgl; sg; sg = sg_next(sg)) |
| 573 | 581 | if (sg_page(sg)) |
| 574 | 582 | __free_pages(sg_page(sg), get_order(sg->length)); |
| @@ -648,6 +656,7 @@ static void qaic_init_bo(struct qaic_bo *bo, bool reinit) · 73 unmodified lines | ||
| 648 | 656 | } |
| 649 | 657 | complete_all(&bo->xfer_done); |
| 650 | 658 | INIT_LIST_HEAD(&bo->slices); |
| 659 | + INIT_LIST_HEAD(&bo->xfer_list); | |
| 651 | 660 | } |
| 652 | 661 | |
| 653 | 662 | static struct qaic_bo *qaic_alloc_init_bo(void) |
| @@ -709,9 +718,13 @@ int qaic_create_bo_ioctl(struct drm_device *dev, void *data, struct drm_file *fi · 55 unmodified lines | ||
| 709 | 718 | if (ret) |
| 710 | 719 | goto free_bo; |
| 711 | 720 | |
| 721 | + ret = drm_gem_create_mmap_offset(obj); | |
| 722 | + if (ret) | |
| 723 | + goto free_bo; | |
| 724 | + | |
| 712 | 725 | ret = drm_gem_handle_create(file_priv, obj, &args->handle); |
| 713 | 726 | if (ret) |
| 714 | − goto free_sgt; | |
| 727 | + goto free_bo; | |
| 715 | 728 | |
| 716 | 729 | bo->handle = args->handle; |
| 717 | 730 | drm_gem_object_put(obj); |
| @@ -720,10 +733,8 @@ int qaic_create_bo_ioctl(struct drm_device *dev, void *data, struct drm_file *fi · 2 unmodified lines | ||
| 720 | 733 | |
| 721 | 734 | return 0; |
| 722 | 735 | |
| 723 | −free_sgt: | |
| 724 | − qaic_free_sgt(bo->sgt); | |
| 725 | 736 | free_bo: |
| 726 | − kfree(bo); | |
| 737 | + drm_gem_object_put(obj); | |
| 727 | 738 | unlock_dev_srcu: |
| 728 | 739 | srcu_read_unlock(&qdev->dev_lock, qdev_rcu_id); |
| 729 | 740 | unlock_usr_srcu: |
| @@ -738,7 +749,7 @@ int qaic_mmap_bo_ioctl(struct drm_device *dev, void *data, struct drm_file *file · 8 unmodified lines | ||
| 738 | 749 | struct drm_gem_object *obj; |
| 739 | 750 | struct qaic_device *qdev; |
| 740 | 751 | struct qaic_user *usr; |
| 741 | − int ret; | |
| 752 | + int ret = 0; | |
| 742 | 753 | |
| 743 | 754 | usr = file_priv->driver_priv; |
| 744 | 755 | usr_rcu_id = srcu_read_lock(&usr->qddev_lock); |
| @@ -760,9 +771,7 @@ int qaic_mmap_bo_ioctl(struct drm_device *dev, void *data, struct drm_file *file · 15 unmodified lines | ||
| 760 | 771 | goto unlock_dev_srcu; |
| 761 | 772 | } |
| 762 | 773 | |
| 763 | − ret = drm_gem_create_mmap_offset(obj); | |
| 764 | − if (ret == 0) | |
| 765 | − args->offset = drm_vma_node_offset_addr(&obj->vma_node); | |
| 774 | + args->offset = drm_vma_node_offset_addr(&obj->vma_node); | |
| 766 | 775 | |
| 767 | 776 | drm_gem_object_put(obj); |
| 768 | 777 | |
| @@ -828,9 +837,6 @@ static int qaic_prepare_import_bo(struct qaic_bo *bo, struct qaic_attach_slice_h · 59 unmodified lines | ||
| 828 | 837 | struct sg_table *sgt; |
| 829 | 838 | int ret; |
| 830 | 839 | |
| 831 | − if (obj->import_attach->dmabuf->size < hdr->size) | |
| 832 | − return -EINVAL; | |
| 833 | − | |
| 834 | 840 | sgt = dma_buf_map_attachment(obj->import_attach, hdr->dir); |
| 835 | 841 | if (IS_ERR(sgt)) { |
| 836 | 842 | ret = PTR_ERR(sgt); |
| @@ -847,9 +853,6 @@ static int qaic_prepare_export_bo(struct qaic_device *qdev, struct qaic_bo *bo, · 10 unmodified lines | ||
| 847 | 853 | { |
| 848 | 854 | int ret; |
| 849 | 855 | |
| 850 | − if (bo->base.size < hdr->size) | |
| 851 | − return -EINVAL; | |
| 852 | − | |
| 853 | 856 | ret = dma_map_sgtable(&qdev->pdev->dev, bo->sgt, hdr->dir, 0); |
| 854 | 857 | if (ret) |
| 855 | 858 | return -EFAULT; |
| @@ -950,9 +953,6 @@ int qaic_attach_slice_bo_ioctl(struct drm_device *dev, void *data, struct drm_fi · 94 unmodified lines | ||
| 950 | 953 | if (arg_size / args->hdr.count != sizeof(*slice_ent)) |
| 951 | 954 | return -EINVAL; |
| 952 | 955 | |
| 953 | − if (args->hdr.size == 0) | |
| 954 | − return -EINVAL; | |
| 955 | − | |
| 956 | 956 | if (!(args->hdr.dir == DMA_TO_DEVICE || args->hdr.dir == DMA_FROM_DEVICE)) |
| 957 | 957 | return -EINVAL; |
| 958 | 958 | |
| @@ -992,16 +992,16 @@ int qaic_attach_slice_bo_ioctl(struct drm_device *dev, void *data, struct drm_fi · 33 unmodified lines | ||
| 992 | 992 | goto free_slice_ent; |
| 993 | 993 | } |
| 994 | 994 | |
| 995 | − ret = qaic_validate_req(qdev, slice_ent, args->hdr.count, args->hdr.size); | |
| 996 | − if (ret) | |
| 997 | − goto free_slice_ent; | |
| 998 | − | |
| 999 | 995 | obj = drm_gem_object_lookup(file_priv, args->hdr.handle); |
| 1000 | 996 | if (!obj) { |
| 1001 | 997 | ret = -ENOENT; |
| 1002 | 998 | goto free_slice_ent; |
| 1003 | 999 | } |
| 1004 | 1000 | |
| 1001 | + ret = qaic_validate_req(qdev, slice_ent, args->hdr.count, obj->size); | |
| 1002 | + if (ret) | |
| 1003 | + goto put_bo; | |
| 1004 | + | |
| 1005 | 1005 | bo = to_qaic_bo(obj); |
| 1006 | 1006 | ret = mutex_lock_interruptible(&bo->lock); |
| 1007 | 1007 | if (ret) |
| @@ -1173,7 +1173,6 @@ static int send_bo_list_to_device(struct qaic_device *qdev, struct drm_file *fil · 165 unmodified lines | ||
| 1173 | 1173 | struct bo_slice *slice; |
| 1174 | 1174 | unsigned long flags; |
| 1175 | 1175 | struct qaic_bo *bo; |
| 1176 | − bool queued; | |
| 1177 | 1176 | int i, j; |
| 1178 | 1177 | int ret; |
| 1179 | 1178 | |
| @@ -1205,9 +1204,7 @@ static int send_bo_list_to_device(struct qaic_device *qdev, struct drm_file *fil · 25 unmodified lines | ||
| 1205 | 1204 | } |
| 1206 | 1205 | |
| 1207 | 1206 | spin_lock_irqsave(&dbc->xfer_lock, flags); |
| 1208 | − queued = bo->queued; | |
| 1209 | − bo->queued = true; | |
| 1210 | − if (queued) { | |
| 1207 | + if (bo_queued(bo)) { | |
| 1211 | 1208 | spin_unlock_irqrestore(&dbc->xfer_lock, flags); |
| 1212 | 1209 | ret = -EINVAL; |
| 1213 | 1210 | goto unlock_bo; |
| @@ -1230,7 +1227,6 @@ static int send_bo_list_to_device(struct qaic_device *qdev, struct drm_file *fil · 16 unmodified lines | ||
| 1230 | 1227 | else |
| 1231 | 1228 | ret = copy_exec_reqs(qdev, slice, dbc->id, head, tail); |
| 1232 | 1229 | if (ret) { |
| 1233 | − bo->queued = false; | |
| 1234 | 1230 | spin_unlock_irqrestore(&dbc->xfer_lock, flags); |
| 1235 | 1231 | goto unlock_bo; |
| 1236 | 1232 | } |
| @@ -1253,8 +1249,7 @@ failed_to_send_bo: · 16 unmodified lines | ||
| 1253 | 1249 | spin_lock_irqsave(&dbc->xfer_lock, flags); |
| 1254 | 1250 | bo = list_last_entry(&dbc->xfer_list, struct qaic_bo, xfer_list); |
| 1255 | 1251 | obj = &bo->base; |
| 1256 | − bo->queued = false; | |
| 1257 | − list_del(&bo->xfer_list); | |
| 1252 | + list_del_init(&bo->xfer_list); | |
| 1258 | 1253 | spin_unlock_irqrestore(&dbc->xfer_lock, flags); |
| 1259 | 1254 | dma_sync_sgtable_for_cpu(&qdev->pdev->dev, bo->sgt, bo->dir); |
| 1260 | 1255 | drm_gem_object_put(obj); |
| @@ -1615,8 +1610,7 @@ read_fifo: · 354 unmodified lines | ||
| 1615 | 1610 | */ |
| 1616 | 1611 | dma_sync_sgtable_for_cpu(&qdev->pdev->dev, bo->sgt, bo->dir); |
| 1617 | 1612 | bo->nr_slice_xfer_done = 0; |
| 1618 | − bo->queued = false; | |
| 1619 | − list_del(&bo->xfer_list); | |
| 1613 | + list_del_init(&bo->xfer_list); | |
| 1620 | 1614 | bo->perf_stats.req_processed_ts = ktime_get_ns(); |
| 1621 | 1615 | complete_all(&bo->xfer_done); |
| 1622 | 1616 | drm_gem_object_put(&bo->base); |
| @@ -1875,7 +1869,7 @@ int qaic_detach_slice_bo_ioctl(struct drm_device *dev, void *data, struct drm_fi · 252 unmodified lines | ||
| 1875 | 1869 | |
| 1876 | 1870 | /* Check if BO is committed to H/W for DMA */ |
| 1877 | 1871 | spin_lock_irqsave(&dbc->xfer_lock, flags); |
| 1878 | − if (bo->queued) { | |
| 1872 | + if (bo_queued(bo)) { | |
| 1879 | 1873 | spin_unlock_irqrestore(&dbc->xfer_lock, flags); |
| 1880 | 1874 | ret = -EBUSY; |
| 1881 | 1875 | goto unlock_ch_srcu; |
| @@ -1905,8 +1899,7 @@ static void empty_xfer_list(struct qaic_device *qdev, struct dma_bridge_chan *db · 23 unmodified lines | ||
| 1905 | 1899 | spin_lock_irqsave(&dbc->xfer_lock, flags); |
| 1906 | 1900 | while (!list_empty(&dbc->xfer_list)) { |
| 1907 | 1901 | bo = list_first_entry(&dbc->xfer_list, typeof(*bo), xfer_list); |
| 1908 | − bo->queued = false; | |
| 1909 | − list_del(&bo->xfer_list); | |
| 1902 | + list_del_init(&bo->xfer_list); | |
| 1910 | 1903 | spin_unlock_irqrestore(&dbc->xfer_lock, flags); |
| 1911 | 1904 | bo->nr_slice_xfer_done = 0; |
| 1912 | 1905 | bo->req_id = 0; |
| @@ -44,6 +44,53 @@ MODULE_PARM_DESC(datapath_polling, "Operate the datapath in polling mode"); · 43 unmodified lines | ||
| 44 | 44 | static bool link_up; |
| 45 | 45 | static DEFINE_IDA(qaic_usrs); |
| 46 | 46 | |
| 47 | +static void qaicm_wq_release(struct drm_device *dev, void *res) | |
| 48 | +{ | |
| 49 | + struct workqueue_struct *wq = res; | |
| 50 | + | |
| 51 | + destroy_workqueue(wq); | |
| 52 | +} | |
| 53 | + | |
| 54 | +static struct workqueue_struct *qaicm_wq_init(struct drm_device *dev, const char *fmt) | |
| 55 | +{ | |
| 56 | + struct workqueue_struct *wq; | |
| 57 | + int ret; | |
| 58 | + | |
| 59 | + wq = alloc_workqueue(fmt, WQ_UNBOUND, 0); | |
| 60 | + if (!wq) | |
| 61 | + return ERR_PTR(-ENOMEM); | |
| 62 | + ret = drmm_add_action_or_reset(dev, qaicm_wq_release, wq); | |
| 63 | + if (ret) | |
| 64 | + return ERR_PTR(ret); | |
| 65 | + | |
| 66 | + return wq; | |
| 67 | +} | |
| 68 | + | |
| 69 | +static void qaicm_srcu_release(struct drm_device *dev, void *res) | |
| 70 | +{ | |
| 71 | + struct srcu_struct *lock = res; | |
| 72 | + | |
| 73 | + cleanup_srcu_struct(lock); | |
| 74 | +} | |
| 75 | + | |
| 76 | +static int qaicm_srcu_init(struct drm_device *dev, struct srcu_struct *lock) | |
| 77 | +{ | |
| 78 | + int ret; | |
| 79 | + | |
| 80 | + ret = init_srcu_struct(lock); | |
| 81 | + if (ret) | |
| 82 | + return ret; | |
| 83 | + | |
| 84 | + return drmm_add_action_or_reset(dev, qaicm_srcu_release, lock); | |
| 85 | +} | |
| 86 | + | |
| 87 | +static void qaicm_pci_release(struct drm_device *dev, void *res) | |
| 88 | +{ | |
| 89 | + struct qaic_device *qdev = to_qaic_device(dev); | |
| 90 | + | |
| 91 | + pci_set_drvdata(qdev->pdev, NULL); | |
| 92 | +} | |
| 93 | + | |
| 47 | 94 | static void free_usr(struct kref *kref) |
| 48 | 95 | { |
| 49 | 96 | struct qaic_user *usr = container_of(kref, struct qaic_user, ref_count); |
| @@ -299,74 +346,73 @@ void qaic_dev_reset_clean_local_state(struct qaic_device *qdev) · 249 unmodified lines | ||
| 299 | 346 | release_dbc(qdev, i); |
| 300 | 347 | } |
| 301 | 348 | |
| 302 | −static void cleanup_qdev(struct qaic_device *qdev) | |
| 303 | −{ | |
| 304 | − int i; | |
| 305 | − | |
| 306 | − for (i = 0; i < qdev->num_dbc; ++i) | |
| 307 | − cleanup_srcu_struct(&qdev->dbc[i].ch_lock); | |
| 308 | − cleanup_srcu_struct(&qdev->dev_lock); | |
| 309 | − pci_set_drvdata(qdev->pdev, NULL); | |
| 310 | − destroy_workqueue(qdev->cntl_wq); | |
| 311 | − destroy_workqueue(qdev->qts_wq); | |
| 312 | −} | |
| 313 | − | |
| 314 | 349 | static struct qaic_device *create_qdev(struct pci_dev *pdev, const struct pci_device_id *id) |
| 315 | 350 | { |
| 351 | + struct device *dev = &pdev->dev; | |
| 316 | 352 | struct qaic_drm_device *qddev; |
| 317 | 353 | struct qaic_device *qdev; |
| 318 | − int i; | |
| 354 | + struct drm_device *drm; | |
| 355 | + int i, ret; | |
| 319 | 356 | |
| 320 | − qdev = devm_kzalloc(&pdev->dev, sizeof(*qdev), GFP_KERNEL); | |
| 357 | + qdev = devm_kzalloc(dev, sizeof(*qdev), GFP_KERNEL); | |
| 321 | 358 | if (!qdev) |
| 322 | 359 | return NULL; |
| 323 | 360 | |
| 324 | 361 | qdev->dev_state = QAIC_OFFLINE; |
| 325 | 362 | if (id->device == PCI_DEV_AIC100) { |
| 326 | 363 | qdev->num_dbc = 16; |
| 327 | − qdev->dbc = devm_kcalloc(&pdev->dev, qdev->num_dbc, sizeof(*qdev->dbc), GFP_KERNEL); | |
| 364 | + qdev->dbc = devm_kcalloc(dev, qdev->num_dbc, sizeof(*qdev->dbc), GFP_KERNEL); | |
| 328 | 365 | if (!qdev->dbc) |
| 329 | 366 | return NULL; |
| 330 | 367 | } |
| 331 | 368 | |
| 332 | − qdev->cntl_wq = alloc_workqueue("qaic_cntl", WQ_UNBOUND, 0); | |
| 333 | − if (!qdev->cntl_wq) | |
| 369 | + qddev = devm_drm_dev_alloc(&pdev->dev, &qaic_accel_driver, struct qaic_drm_device, drm); | |
| 370 | + if (IS_ERR(qddev)) | |
| 371 | + return NULL; | |
| 372 | + | |
| 373 | + drm = to_drm(qddev); | |
| 374 | + pci_set_drvdata(pdev, qdev); | |
| 375 | + | |
| 376 | + ret = drmm_mutex_init(drm, &qddev->users_mutex); | |
| 377 | + if (ret) | |
| 378 | + return NULL; | |
| 379 | + ret = drmm_add_action_or_reset(drm, qaicm_pci_release, NULL); | |
| 380 | + if (ret) | |
| 381 | + return NULL; | |
| 382 | + ret = drmm_mutex_init(drm, &qdev->cntl_mutex); | |
| 383 | + if (ret) | |
| 334 | 384 | return NULL; |
| 335 | 385 | |
| 336 | − qdev->qts_wq = alloc_workqueue("qaic_ts", WQ_UNBOUND, 0); | |
| 337 | − if (!qdev->qts_wq) { | |
| 338 | − destroy_workqueue(qdev->cntl_wq); | |
| 386 | + qdev->cntl_wq = qaicm_wq_init(drm, "qaic_cntl"); | |
| 387 | + if (IS_ERR(qdev->cntl_wq)) | |
| 388 | + return NULL; | |
| 389 | + qdev->qts_wq = qaicm_wq_init(drm, "qaic_ts"); | |
| 390 | + if (IS_ERR(qdev->qts_wq)) | |
| 339 | 391 | return NULL; |
| 340 | − } | |
| 341 | 392 | |
| 342 | − pci_set_drvdata(pdev, qdev); | |
| 393 | + ret = qaicm_srcu_init(drm, &qdev->dev_lock); | |
| 394 | + if (ret) | |
| 395 | + return NULL; | |
| 396 | + | |
| 397 | + qdev->qddev = qddev; | |
| 343 | 398 | qdev->pdev = pdev; |
| 399 | + qddev->qdev = qdev; | |
| 344 | 400 | |
| 345 | − mutex_init(&qdev->cntl_mutex); | |
| 346 | 401 | INIT_LIST_HEAD(&qdev->cntl_xfer_list); |
| 347 | − init_srcu_struct(&qdev->dev_lock); | |
| 402 | + INIT_LIST_HEAD(&qddev->users); | |
| 348 | 403 | |
| 349 | 404 | for (i = 0; i < qdev->num_dbc; ++i) { |
| 350 | 405 | spin_lock_init(&qdev->dbc[i].xfer_lock); |
| 351 | 406 | qdev->dbc[i].qdev = qdev; |
| 352 | 407 | qdev->dbc[i].id = i; |
| 353 | 408 | INIT_LIST_HEAD(&qdev->dbc[i].xfer_list); |
| 354 | − init_srcu_struct(&qdev->dbc[i].ch_lock); | |
| 409 | + ret = qaicm_srcu_init(drm, &qdev->dbc[i].ch_lock); | |
| 410 | + if (ret) | |
| 411 | + return NULL; | |
| 355 | 412 | init_waitqueue_head(&qdev->dbc[i].dbc_release); |
| 356 | 413 | INIT_LIST_HEAD(&qdev->dbc[i].bo_lists); |
| 357 | 414 | } |
| 358 | 415 | |
| 359 | − qddev = devm_drm_dev_alloc(&pdev->dev, &qaic_accel_driver, struct qaic_drm_device, drm); | |
| 360 | − if (IS_ERR(qddev)) { | |
| 361 | − cleanup_qdev(qdev); | |
| 362 | − return NULL; | |
| 363 | − } | |
| 364 | − | |
| 365 | − drmm_mutex_init(to_drm(qddev), &qddev->users_mutex); | |
| 366 | − INIT_LIST_HEAD(&qddev->users); | |
| 367 | − qddev->qdev = qdev; | |
| 368 | − qdev->qddev = qddev; | |
| 369 | − | |
| 370 | 416 | return qdev; |
| 371 | 417 | } |
| 372 | 418 | |
| @@ -472,35 +518,28 @@ static int qaic_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) · 99 unmodified lines | ||
| 472 | 518 | |
| 473 | 519 | ret = init_pci(qdev, pdev); |
| 474 | 520 | if (ret) |
| 475 | − goto cleanup_qdev; | |
| 521 | + return ret; | |
| 476 | 522 | |
| 477 | 523 | for (i = 0; i < qdev->num_dbc; ++i) |
| 478 | 524 | qdev->dbc[i].dbc_base = qdev->bar_2 + QAIC_DBC_OFF(i); |
| 479 | 525 | |
| 480 | 526 | mhi_irq = init_msi(qdev, pdev); |
| 481 | − if (mhi_irq < 0) { | |
| 482 | − ret = mhi_irq; | |
| 483 | − goto cleanup_qdev; | |
| 484 | − } | |
| 527 | + if (mhi_irq < 0) | |
| 528 | + return mhi_irq; | |
| 485 | 529 | |
| 486 | 530 | ret = qaic_create_drm_device(qdev, QAIC_NO_PARTITION); |
| 487 | 531 | if (ret) |
| 488 | − goto cleanup_qdev; | |
| 532 | + return ret; | |
| 489 | 533 | |
| 490 | 534 | qdev->mhi_cntrl = qaic_mhi_register_controller(pdev, qdev->bar_0, mhi_irq, |
| 491 | 535 | qdev->single_msi); |
| 492 | 536 | if (IS_ERR(qdev->mhi_cntrl)) { |
| 493 | 537 | ret = PTR_ERR(qdev->mhi_cntrl); |
| 494 | − goto cleanup_drm_dev; | |
| 538 | + qaic_destroy_drm_device(qdev, QAIC_NO_PARTITION); | |
| 539 | + return ret; | |
| 495 | 540 | } |
| 496 | 541 | |
| 497 | 542 | return 0; |
| 498 | − | |
| 499 | −cleanup_drm_dev: | |
| 500 | − qaic_destroy_drm_device(qdev, QAIC_NO_PARTITION); | |
| 501 | −cleanup_qdev: | |
| 502 | − cleanup_qdev(qdev); | |
| 503 | − return ret; | |
| 504 | 543 | } |
| 505 | 544 | |
| 506 | 545 | static void qaic_pci_remove(struct pci_dev *pdev) |
| @@ -511,9 +550,8 @@ static void qaic_pci_remove(struct pci_dev *pdev) · 4 unmodified lines | ||
| 511 | 550 | return; |
| 512 | 551 | |
| 513 | 552 | qaic_dev_reset_clean_local_state(qdev); |
| 514 | − qaic_destroy_drm_device(qdev, QAIC_NO_PARTITION); | |
| 515 | 553 | qaic_mhi_free_controller(qdev->mhi_cntrl, link_up); |
| 516 | − cleanup_qdev(qdev); | |
| 554 | + qaic_destroy_drm_device(qdev, QAIC_NO_PARTITION); | |
| 517 | 555 | } |
| 518 | 556 | |
| 519 | 557 | static void qaic_pci_shutdown(struct pci_dev *pdev) |
| @@ -478,6 +478,16 @@ binder_enqueue_thread_work_ilocked(struct binder_thread *thread, · 477 unmodified lines | ||
| 478 | 478 | { |
| 479 | 479 | WARN_ON(!list_empty(&thread->waiting_thread_node)); |
| 480 | 480 | binder_enqueue_work_ilocked(work, &thread->todo); |
| 481 | + | |
| 482 | + /* (e)poll-based threads require an explicit wakeup signal when | |
| 483 | + * queuing their own work; they rely on these events to consume | |
| 484 | + * messages without I/O block. Without it, threads risk waiting | |
| 485 | + * indefinitely without handling the work. | |
| 486 | + */ | |
| 487 | + if (thread->looper & BINDER_LOOPER_STATE_POLL && | |
| 488 | + thread->pid == current->pid && !thread->process_todo) | |
| 489 | + wake_up_interruptible_sync(&thread->wait); | |
| 490 | + | |
| 481 | 491 | thread->process_todo = true; |
| 482 | 492 | } |
| 483 | 493 | |
| @@ -48,6 +48,7 @@ enum { · 47 unmodified lines | ||
| 48 | 48 | enum board_ids { |
| 49 | 49 | /* board IDs by feature in alphabetical order */ |
| 50 | 50 | board_ahci, |
| 51 | + board_ahci_43bit_dma, | |
| 51 | 52 | board_ahci_ign_iferr, |
| 52 | 53 | board_ahci_low_power, |
| 53 | 54 | board_ahci_no_debounce_delay, |
| @@ -128,6 +129,13 @@ static const struct ata_port_info ahci_port_info[] = { · 74 unmodified lines | ||
| 128 | 129 | .udma_mask = ATA_UDMA6, |
| 129 | 130 | .port_ops = &ahci_ops, |
| 130 | 131 | }, |
| 132 | + [board_ahci_43bit_dma] = { | |
| 133 | + AHCI_HFLAGS (AHCI_HFLAG_43BIT_ONLY), | |
| 134 | + .flags = AHCI_FLAG_COMMON, | |
| 135 | + .pio_mask = ATA_PIO4, | |
| 136 | + .udma_mask = ATA_UDMA6, | |
| 137 | + .port_ops = &ahci_ops, | |
| 138 | + }, | |
| 131 | 139 | [board_ahci_ign_iferr] = { |
| 132 | 140 | AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR), |
| 133 | 141 | .flags = AHCI_FLAG_COMMON, |
| @@ -597,14 +605,14 @@ static const struct pci_device_id ahci_pci_tbl[] = { · 463 unmodified lines | ||
| 597 | 605 | { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */ |
| 598 | 606 | { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */ |
| 599 | 607 | |
| 600 | − /* Asmedia */ | |
| 601 | − { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */ | |
| 602 | − { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */ | |
| 603 | − { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */ | |
| 604 | − { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */ | |
| 605 | − { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci }, /* ASM1061R */ | |
| 606 | − { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci }, /* ASM1062R */ | |
| 607 | − { PCI_VDEVICE(ASMEDIA, 0x0624), board_ahci }, /* ASM1062+JMB575 */ | |
| 608 | + /* ASMedia */ | |
| 609 | + { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci_43bit_dma }, /* ASM1060 */ | |
| 610 | + { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci_43bit_dma }, /* ASM1060 */ | |
| 611 | + { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci_43bit_dma }, /* ASM1061 */ | |
| 612 | + { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci_43bit_dma }, /* ASM1061/1062 */ | |
| 613 | + { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci_43bit_dma }, /* ASM1061R */ | |
| 614 | + { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci_43bit_dma }, /* ASM1062R */ | |
| 615 | + { PCI_VDEVICE(ASMEDIA, 0x0624), board_ahci_43bit_dma }, /* ASM1062+JMB575 */ | |
| 608 | 616 | { PCI_VDEVICE(ASMEDIA, 0x1062), board_ahci }, /* ASM1062A */ |
| 609 | 617 | { PCI_VDEVICE(ASMEDIA, 0x1064), board_ahci }, /* ASM1064 */ |
| 610 | 618 | { PCI_VDEVICE(ASMEDIA, 0x1164), board_ahci }, /* ASM1164 */ |
| @@ -663,6 +671,11 @@ MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets"); · 52 unmodified lines | ||
| 663 | 671 | static void ahci_pci_save_initial_config(struct pci_dev *pdev, |
| 664 | 672 | struct ahci_host_priv *hpriv) |
| 665 | 673 | { |
| 674 | + if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && pdev->device == 0x1166) { | |
| 675 | + dev_info(&pdev->dev, "ASM1166 has only six ports\n"); | |
| 676 | + hpriv->saved_port_map = 0x3f; | |
| 677 | + } | |
| 678 | + | |
| 666 | 679 | if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) { |
| 667 | 680 | dev_info(&pdev->dev, "JMB361 has only one port\n"); |
| 668 | 681 | hpriv->saved_port_map = 1; |
| @@ -949,11 +962,20 @@ static int ahci_pci_device_resume(struct device *dev) · 280 unmodified lines | ||
| 949 | 962 | |
| 950 | 963 | #endif /* CONFIG_PM */ |
| 951 | 964 | |
| 952 | −static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac) | |
| 965 | +static int ahci_configure_dma_masks(struct pci_dev *pdev, | |
| 966 | + struct ahci_host_priv *hpriv) | |
| 953 | 967 | { |
| 954 | − const int dma_bits = using_dac ? 64 : 32; | |
| 968 | + int dma_bits; | |
| 955 | 969 | int rc; |
| 956 | 970 | |
| 971 | + if (hpriv->cap & HOST_CAP_64) { | |
| 972 | + dma_bits = 64; | |
| 973 | + if (hpriv->flags & AHCI_HFLAG_43BIT_ONLY) | |
| 974 | + dma_bits = 43; | |
| 975 | + } else { | |
| 976 | + dma_bits = 32; | |
| 977 | + } | |
| 978 | + | |
| 957 | 979 | /* |
| 958 | 980 | * If the device fixup already set the dma_mask to some non-standard |
| 959 | 981 | * value, don't extend it here. This happens on STA2X11, for example. |
| @@ -1926,7 +1948,7 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) · 966 unmodified lines | ||
| 1926 | 1948 | ahci_gtf_filter_workaround(host); |
| 1927 | 1949 | |
| 1928 | 1950 | /* initialize adapter */ |
| 1929 | − rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64); | |
| 1951 | + rc = ahci_configure_dma_masks(pdev, hpriv); | |
| 1930 | 1952 | if (rc) |
| 1931 | 1953 | return rc; |
| 1932 | 1954 | |
| @@ -247,6 +247,7 @@ enum { · 246 unmodified lines | ||
| 247 | 247 | AHCI_HFLAG_SUSPEND_PHYS = BIT(26), /* handle PHYs during |
| 248 | 248 | suspend/resume */ |
| 249 | 249 | AHCI_HFLAG_NO_SXS = BIT(28), /* SXS not supported */ |
| 250 | + AHCI_HFLAG_43BIT_ONLY = BIT(29), /* 43bit DMA addr limit */ | |
| 250 | 251 | |
| 251 | 252 | /* ap->flags bits */ |
| 252 | 253 | |
| @@ -784,7 +784,7 @@ bool sata_lpm_ignore_phy_events(struct ata_link *link) · 783 unmodified lines | ||
| 784 | 784 | EXPORT_SYMBOL_GPL(sata_lpm_ignore_phy_events); |
| 785 | 785 | |
| 786 | 786 | static const char *ata_lpm_policy_names[] = { |
| 787 | − [ATA_LPM_UNKNOWN] = "max_performance", | |
| 787 | + [ATA_LPM_UNKNOWN] = "keep_firmware_settings", | |
| 788 | 788 | [ATA_LPM_MAX_POWER] = "max_performance", |
| 789 | 789 | [ATA_LPM_MED_POWER] = "medium_power", |
| 790 | 790 | [ATA_LPM_MED_POWER_WITH_DIPM] = "med_power_with_dipm", |
| @@ -333,6 +333,7 @@ aoeblk_gdalloc(void *vp) · 332 unmodified lines | ||
| 333 | 333 | struct gendisk *gd; |
| 334 | 334 | mempool_t *mp; |
| 335 | 335 | struct blk_mq_tag_set *set; |
| 336 | + sector_t ssize; | |
| 336 | 337 | ulong flags; |
| 337 | 338 | int late = 0; |
| 338 | 339 | int err; |
| @@ -396,7 +397,7 @@ aoeblk_gdalloc(void *vp) · 57 unmodified lines | ||
| 396 | 397 | gd->minors = AOE_PARTITIONS; |
| 397 | 398 | gd->fops = &aoe_bdops; |
| 398 | 399 | gd->private_data = d; |
| 399 | − set_capacity(gd, d->ssize); | |
| 400 | + ssize = d->ssize; | |
| 400 | 401 | snprintf(gd->disk_name, sizeof gd->disk_name, "etherd/e%ld.%d", |
| 401 | 402 | d->aoemajor, d->aoeminor); |
| 402 | 403 | |
| @@ -405,6 +406,8 @@ aoeblk_gdalloc(void *vp) · 2 unmodified lines | ||
| 405 | 406 | |
| 406 | 407 | spin_unlock_irqrestore(&d->lock, flags); |
| 407 | 408 | |
| 409 | + set_capacity(gd, ssize); | |
| 410 | + | |
| 408 | 411 | err = device_add_disk(NULL, gd, aoe_attr_groups); |
| 409 | 412 | if (err) |
| 410 | 413 | goto out_disk_cleanup; |
| @@ -3452,14 +3452,15 @@ static bool rbd_lock_add_request(struct rbd_img_request *img_req) · 3451 unmodified lines | ||
| 3452 | 3452 | static void rbd_lock_del_request(struct rbd_img_request *img_req) |
| 3453 | 3453 | { |
| 3454 | 3454 | struct rbd_device *rbd_dev = img_req->rbd_dev; |
| 3455 | − bool need_wakeup; | |
| 3455 | + bool need_wakeup = false; | |
| 3456 | 3456 | |
| 3457 | 3457 | lockdep_assert_held(&rbd_dev->lock_rwsem); |
| 3458 | 3458 | spin_lock(&rbd_dev->lock_lists_lock); |
| 3459 | − rbd_assert(!list_empty(&img_req->lock_item)); | |
| 3460 | − list_del_init(&img_req->lock_item); | |
| 3461 | − need_wakeup = (rbd_dev->lock_state == RBD_LOCK_STATE_RELEASING && | |
| 3462 | − list_empty(&rbd_dev->running_list)); | |
| 3459 | + if (!list_empty(&img_req->lock_item)) { | |
| 3460 | + list_del_init(&img_req->lock_item); | |
| 3461 | + need_wakeup = (rbd_dev->lock_state == RBD_LOCK_STATE_RELEASING && | |
| 3462 | + list_empty(&rbd_dev->running_list)); | |
| 3463 | + } | |
| 3463 | 3464 | spin_unlock(&rbd_dev->lock_lists_lock); |
| 3464 | 3465 | if (need_wakeup) |
| 3465 | 3466 | complete(&rbd_dev->releasing_wait); |
| @@ -3842,14 +3843,19 @@ static void wake_lock_waiters(struct rbd_device *rbd_dev, int result) · 376 unmodified lines | ||
| 3842 | 3843 | return; |
| 3843 | 3844 | } |
| 3844 | 3845 | |
| 3845 | − list_for_each_entry(img_req, &rbd_dev->acquiring_list, lock_item) { | |
| 3846 | + while (!list_empty(&rbd_dev->acquiring_list)) { | |
| 3847 | + img_req = list_first_entry(&rbd_dev->acquiring_list, | |
| 3848 | + struct rbd_img_request, lock_item); | |
| 3846 | 3849 | mutex_lock(&img_req->state_mutex); |
| 3847 | 3850 | rbd_assert(img_req->state == RBD_IMG_EXCLUSIVE_LOCK); |
| 3851 | + if (!result) | |
| 3852 | + list_move_tail(&img_req->lock_item, | |
| 3853 | + &rbd_dev->running_list); | |
| 3854 | + else | |
| 3855 | + list_del_init(&img_req->lock_item); | |
| 3848 | 3856 | rbd_img_schedule(img_req, result); |
| 3849 | 3857 | mutex_unlock(&img_req->state_mutex); |
| 3850 | 3858 | } |
| 3851 | − | |
| 3852 | − list_splice_tail_init(&rbd_dev->acquiring_list, &rbd_dev->running_list); | |
| 3853 | 3859 | } |
| 3854 | 3860 | |
| 3855 | 3861 | static bool locker_equal(const struct ceph_locker *lhs, |
| @@ -5326,7 +5332,7 @@ static void rbd_dev_release(struct device *dev) · 1470 unmodified lines | ||
| 5326 | 5332 | |
| 5327 | 5333 | if (need_put) { |
| 5328 | 5334 | destroy_workqueue(rbd_dev->task_wq); |
| 5329 | − ida_simple_remove(&rbd_dev_id_ida, rbd_dev->dev_id); | |
| 5335 | + ida_free(&rbd_dev_id_ida, rbd_dev->dev_id); | |
| 5330 | 5336 | } |
| 5331 | 5337 | |
| 5332 | 5338 | rbd_dev_free(rbd_dev); |
| @@ -5402,9 +5408,9 @@ static struct rbd_device *rbd_dev_create(struct rbd_client *rbdc, · 69 unmodified lines | ||
| 5402 | 5408 | return NULL; |
| 5403 | 5409 | |
| 5404 | 5410 | /* get an id and fill in device name */ |
| 5405 | − rbd_dev->dev_id = ida_simple_get(&rbd_dev_id_ida, 0, | |
| 5406 | − minor_to_rbd_dev_id(1 << MINORBITS), | |
| 5407 | − GFP_KERNEL); | |
| 5411 | + rbd_dev->dev_id = ida_alloc_max(&rbd_dev_id_ida, | |
| 5412 | + minor_to_rbd_dev_id(1 << MINORBITS) - 1, | |
| 5413 | + GFP_KERNEL); | |
| 5408 | 5414 | if (rbd_dev->dev_id < 0) |
| 5409 | 5415 | goto fail_rbd_dev; |
| 5410 | 5416 | |
| @@ -5425,7 +5431,7 @@ static struct rbd_device *rbd_dev_create(struct rbd_client *rbdc, · 14 unmodified lines | ||
| 5425 | 5431 | return rbd_dev; |
| 5426 | 5432 | |
| 5427 | 5433 | fail_dev_id: |
| 5428 | − ida_simple_remove(&rbd_dev_id_ida, rbd_dev->dev_id); | |
| 5434 | + ida_free(&rbd_dev_id_ida, rbd_dev->dev_id); | |
| 5429 | 5435 | fail_rbd_dev: |
| 5430 | 5436 | rbd_dev_free(rbd_dev); |
| 5431 | 5437 | return NULL; |
| @@ -1232,14 +1232,13 @@ static void amd_pstate_epp_update_limit(struct cpufreq_policy *policy) · 1231 unmodified lines | ||
| 1232 | 1232 | max_limit_perf = div_u64(policy->max * cpudata->highest_perf, cpudata->max_freq); |
| 1233 | 1233 | min_limit_perf = div_u64(policy->min * cpudata->highest_perf, cpudata->max_freq); |
| 1234 | 1234 | |
| 1235 | + WRITE_ONCE(cpudata->max_limit_perf, max_limit_perf); | |
| 1236 | + WRITE_ONCE(cpudata->min_limit_perf, min_limit_perf); | |
| 1237 | + | |
| 1235 | 1238 | max_perf = clamp_t(unsigned long, max_perf, cpudata->min_limit_perf, |
| 1236 | 1239 | cpudata->max_limit_perf); |
| 1237 | 1240 | min_perf = clamp_t(unsigned long, min_perf, cpudata->min_limit_perf, |
| 1238 | 1241 | cpudata->max_limit_perf); |
| 1239 | − | |
| 1240 | − WRITE_ONCE(cpudata->max_limit_perf, max_limit_perf); | |
| 1241 | − WRITE_ONCE(cpudata->min_limit_perf, min_limit_perf); | |
| 1242 | − | |
| 1243 | 1242 | value = READ_ONCE(cpudata->cppc_req_cached); |
| 1244 | 1243 | |
| 1245 | 1244 | if (cpudata->policy == CPUFREQ_POLICY_PERFORMANCE) |
| @@ -529,6 +529,30 @@ static int intel_pstate_cppc_get_scaling(int cpu) · 528 unmodified lines | ||
| 529 | 529 | } |
| 530 | 530 | #endif /* CONFIG_ACPI_CPPC_LIB */ |
| 531 | 531 | |
| 532 | +static int intel_pstate_freq_to_hwp_rel(struct cpudata *cpu, int freq, | |
| 533 | + unsigned int relation) | |
| 534 | +{ | |
| 535 | + if (freq == cpu->pstate.turbo_freq) | |
| 536 | + return cpu->pstate.turbo_pstate; | |
| 537 | + | |
| 538 | + if (freq == cpu->pstate.max_freq) | |
| 539 | + return cpu->pstate.max_pstate; | |
| 540 | + | |
| 541 | + switch (relation) { | |
| 542 | + case CPUFREQ_RELATION_H: | |
| 543 | + return freq / cpu->pstate.scaling; | |
| 544 | + case CPUFREQ_RELATION_C: | |
| 545 | + return DIV_ROUND_CLOSEST(freq, cpu->pstate.scaling); | |
| 546 | + } | |
| 547 | + | |
| 548 | + return DIV_ROUND_UP(freq, cpu->pstate.scaling); | |
| 549 | +} | |
| 550 | + | |
| 551 | +static int intel_pstate_freq_to_hwp(struct cpudata *cpu, int freq) | |
| 552 | +{ | |
| 553 | + return intel_pstate_freq_to_hwp_rel(cpu, freq, CPUFREQ_RELATION_L); | |
| 554 | +} | |
| 555 | + | |
| 532 | 556 | /** |
| 533 | 557 | * intel_pstate_hybrid_hwp_adjust - Calibrate HWP performance levels. |
| 534 | 558 | * @cpu: Target CPU. |
| @@ -546,6 +570,7 @@ static void intel_pstate_hybrid_hwp_adjust(struct cpudata *cpu) · 11 unmodified lines | ||
| 546 | 570 | int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling; |
| 547 | 571 | int perf_ctl_turbo = pstate_funcs.get_turbo(cpu->cpu); |
| 548 | 572 | int scaling = cpu->pstate.scaling; |
| 573 | + int freq; | |
| 549 | 574 | |
| 550 | 575 | pr_debug("CPU%d: perf_ctl_max_phys = %d\n", cpu->cpu, perf_ctl_max_phys); |
| 551 | 576 | pr_debug("CPU%d: perf_ctl_turbo = %d\n", cpu->cpu, perf_ctl_turbo); |
| @@ -559,16 +584,16 @@ static void intel_pstate_hybrid_hwp_adjust(struct cpudata *cpu) · 7 unmodified lines | ||
| 559 | 584 | cpu->pstate.max_freq = rounddown(cpu->pstate.max_pstate * scaling, |
| 560 | 585 | perf_ctl_scaling); |
| 561 | 586 | |
| 562 | − cpu->pstate.max_pstate_physical = | |
| 563 | − DIV_ROUND_UP(perf_ctl_max_phys * perf_ctl_scaling, | |
| 564 | − scaling); | |
| 587 | + freq = perf_ctl_max_phys * perf_ctl_scaling; | |
| 588 | + cpu->pstate.max_pstate_physical = intel_pstate_freq_to_hwp(cpu, freq); | |
| 565 | 589 | |
| 566 | − cpu->pstate.min_freq = cpu->pstate.min_pstate * perf_ctl_scaling; | |
| 590 | + freq = cpu->pstate.min_pstate * perf_ctl_scaling; | |
| 591 | + cpu->pstate.min_freq = freq; | |
| 567 | 592 | /* |
| 568 | 593 | * Cast the min P-state value retrieved via pstate_funcs.get_min() to |
| 569 | 594 | * the effective range of HWP performance levels. |
| 570 | 595 | */ |
| 571 | − cpu->pstate.min_pstate = DIV_ROUND_UP(cpu->pstate.min_freq, scaling); | |
| 596 | + cpu->pstate.min_pstate = intel_pstate_freq_to_hwp(cpu, freq); | |
| 572 | 597 | } |
| 573 | 598 | |
| 574 | 599 | static inline void update_turbo_state(void) |
| @@ -2528,13 +2553,12 @@ static void intel_pstate_update_perf_limits(struct cpudata *cpu, · 1953 unmodified lines | ||
| 2528 | 2553 | * abstract values to represent performance rather than pure ratios. |
| 2529 | 2554 | */ |
| 2530 | 2555 | if (hwp_active && cpu->pstate.scaling != perf_ctl_scaling) { |
| 2531 | − int scaling = cpu->pstate.scaling; | |
| 2532 | 2556 | int freq; |
| 2533 | 2557 | |
| 2534 | 2558 | freq = max_policy_perf * perf_ctl_scaling; |
| 2535 | − max_policy_perf = DIV_ROUND_UP(freq, scaling); | |
| 2559 | + max_policy_perf = intel_pstate_freq_to_hwp(cpu, freq); | |
| 2536 | 2560 | freq = min_policy_perf * perf_ctl_scaling; |
| 2537 | − min_policy_perf = DIV_ROUND_UP(freq, scaling); | |
| 2561 | + min_policy_perf = intel_pstate_freq_to_hwp(cpu, freq); | |
| 2538 | 2562 | } |
| 2539 | 2563 | |
| 2540 | 2564 | pr_debug("cpu:%d min_policy_perf:%d max_policy_perf:%d\n", |
| @@ -2908,18 +2932,7 @@ static int intel_cpufreq_target(struct cpufreq_policy *policy, · 367 unmodified lines | ||
| 2908 | 2932 | |
| 2909 | 2933 | cpufreq_freq_transition_begin(policy, &freqs); |
| 2910 | 2934 | |
| 2911 | − switch (relation) { | |
| 2912 | − case CPUFREQ_RELATION_L: | |
| 2913 | − target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling); | |
| 2914 | − break; | |
| 2915 | − case CPUFREQ_RELATION_H: | |
| 2916 | − target_pstate = freqs.new / cpu->pstate.scaling; | |
| 2917 | − break; | |
| 2918 | − default: | |
| 2919 | − target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling); | |
| 2920 | − break; | |
| 2921 | − } | |
| 2922 | − | |
| 2935 | + target_pstate = intel_pstate_freq_to_hwp_rel(cpu, freqs.new, relation); | |
| 2923 | 2936 | target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, false); |
| 2924 | 2937 | |
| 2925 | 2938 | freqs.new = target_pstate * cpu->pstate.scaling; |
| @@ -2937,7 +2950,7 @@ static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy, · 11 unmodified lines | ||
| 2937 | 2950 | |
| 2938 | 2951 | update_turbo_state(); |
| 2939 | 2952 | |
| 2940 | − target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling); | |
| 2953 | + target_pstate = intel_pstate_freq_to_hwp(cpu, target_freq); | |
| 2941 | 2954 | |
| 2942 | 2955 | target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, true); |
| 2943 | 2956 | |
| @@ -4545,6 +4545,7 @@ struct caam_hash_alg { · 4544 unmodified lines | ||
| 4545 | 4545 | struct list_head entry; |
| 4546 | 4546 | struct device *dev; |
| 4547 | 4547 | int alg_type; |
| 4548 | + bool is_hmac; | |
| 4548 | 4549 | struct ahash_alg ahash_alg; |
| 4549 | 4550 | }; |
| 4550 | 4551 | |
| @@ -4571,7 +4572,7 @@ static int caam_hash_cra_init(struct crypto_tfm *tfm) · 20 unmodified lines | ||
| 4571 | 4572 | |
| 4572 | 4573 | ctx->dev = caam_hash->dev; |
| 4573 | 4574 | |
| 4574 | − if (alg->setkey) { | |
| 4575 | + if (caam_hash->is_hmac) { | |
| 4575 | 4576 | ctx->adata.key_dma = dma_map_single_attrs(ctx->dev, ctx->key, |
| 4576 | 4577 | ARRAY_SIZE(ctx->key), |
| 4577 | 4578 | DMA_TO_DEVICE, |
| @@ -4611,7 +4612,7 @@ static int caam_hash_cra_init(struct crypto_tfm *tfm) · 33 unmodified lines | ||
| 4611 | 4612 | * For keyed hash algorithms shared descriptors |
| 4612 | 4613 | * will be created later in setkey() callback |
| 4613 | 4614 | */ |
| 4614 | − return alg->setkey ? 0 : ahash_set_sh_desc(ahash); | |
| 4615 | + return caam_hash->is_hmac ? 0 : ahash_set_sh_desc(ahash); | |
| 4615 | 4616 | } |
| 4616 | 4617 | |
| 4617 | 4618 | static void caam_hash_cra_exit(struct crypto_tfm *tfm) |
| @@ -4646,12 +4647,14 @@ static struct caam_hash_alg *caam_hash_alloc(struct device *dev, · 28 unmodified lines | ||
| 4646 | 4647 | template->hmac_name); |
| 4647 | 4648 | snprintf(alg->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s", |
| 4648 | 4649 | template->hmac_driver_name); |
| 4650 | + t_alg->is_hmac = true; | |
| 4649 | 4651 | } else { |
| 4650 | 4652 | snprintf(alg->cra_name, CRYPTO_MAX_ALG_NAME, "%s", |
| 4651 | 4653 | template->name); |
| 4652 | 4654 | snprintf(alg->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s", |
| 4653 | 4655 | template->driver_name); |
| 4654 | 4656 | t_alg->ahash_alg.setkey = NULL; |
| 4657 | + t_alg->is_hmac = false; | |
| 4655 | 4658 | } |
| 4656 | 4659 | alg->cra_module = THIS_MODULE; |
| 4657 | 4660 | alg->cra_init = caam_hash_cra_init; |
| @@ -1753,6 +1753,7 @@ static struct caam_hash_template driver_hash[] = { · 1752 unmodified lines | ||
| 1753 | 1753 | struct caam_hash_alg { |
| 1754 | 1754 | struct list_head entry; |
| 1755 | 1755 | int alg_type; |
| 1756 | + bool is_hmac; | |
| 1756 | 1757 | struct ahash_engine_alg ahash_alg; |
| 1757 | 1758 | }; |
| 1758 | 1759 | |
| @@ -1804,7 +1805,7 @@ static int caam_hash_cra_init(struct crypto_tfm *tfm) · 45 unmodified lines | ||
| 1804 | 1805 | } else { |
| 1805 | 1806 | if (priv->era >= 6) { |
| 1806 | 1807 | ctx->dir = DMA_BIDIRECTIONAL; |
| 1807 | − ctx->key_dir = alg->setkey ? DMA_TO_DEVICE : DMA_NONE; | |
| 1808 | + ctx->key_dir = caam_hash->is_hmac ? DMA_TO_DEVICE : DMA_NONE; | |
| 1808 | 1809 | } else { |
| 1809 | 1810 | ctx->dir = DMA_TO_DEVICE; |
| 1810 | 1811 | ctx->key_dir = DMA_NONE; |
| @@ -1862,7 +1863,7 @@ static int caam_hash_cra_init(struct crypto_tfm *tfm) · 51 unmodified lines | ||
| 1862 | 1863 | * For keyed hash algorithms shared descriptors |
| 1863 | 1864 | * will be created later in setkey() callback |
| 1864 | 1865 | */ |
| 1865 | − return alg->setkey ? 0 : ahash_set_sh_desc(ahash); | |
| 1866 | + return caam_hash->is_hmac ? 0 : ahash_set_sh_desc(ahash); | |
| 1866 | 1867 | } |
| 1867 | 1868 | |
| 1868 | 1869 | static void caam_hash_cra_exit(struct crypto_tfm *tfm) |
| @@ -1915,12 +1916,14 @@ caam_hash_alloc(struct caam_hash_template *template, · 46 unmodified lines | ||
| 1915 | 1916 | template->hmac_name); |
| 1916 | 1917 | snprintf(alg->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s", |
| 1917 | 1918 | template->hmac_driver_name); |
| 1919 | + t_alg->is_hmac = true; | |
| 1918 | 1920 | } else { |
| 1919 | 1921 | snprintf(alg->cra_name, CRYPTO_MAX_ALG_NAME, "%s", |
| 1920 | 1922 | template->name); |
| 1921 | 1923 | snprintf(alg->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s", |
| 1922 | 1924 | template->driver_name); |
| 1923 | 1925 | halg->setkey = NULL; |
| 1926 | + t_alg->is_hmac = false; | |
| 1924 | 1927 | } |
| 1925 | 1928 | alg->cra_module = THIS_MODULE; |
| 1926 | 1929 | alg->cra_init = caam_hash_cra_init; |
| @@ -463,6 +463,7 @@ void adf_init_hw_data_4xxx(struct adf_hw_device_data *hw_data, u32 dev_id) · 462 unmodified lines | ||
| 463 | 463 | hw_data->fw_name = ADF_402XX_FW; |
| 464 | 464 | hw_data->fw_mmp_name = ADF_402XX_MMP; |
| 465 | 465 | hw_data->uof_get_name = uof_get_name_402xx; |
| 466 | + hw_data->get_ena_thd_mask = get_ena_thd_mask; | |
| 466 | 467 | break; |
| 467 | 468 | case ADF_401XX_PCI_DEVICE_ID: |
| 468 | 469 | hw_data->fw_name = ADF_4XXX_FW; |
| @@ -525,7 +525,7 @@ static int alloc_hpa(struct cxl_region *cxlr, resource_size_t size) · 524 unmodified lines | ||
| 525 | 525 | struct cxl_root_decoder *cxlrd = to_cxl_root_decoder(cxlr->dev.parent); |
| 526 | 526 | struct cxl_region_params *p = &cxlr->params; |
| 527 | 527 | struct resource *res; |
| 528 | − u32 remainder = 0; | |
| 528 | + u64 remainder = 0; | |
| 529 | 529 | |
| 530 | 530 | lockdep_assert_held_write(&cxl_region_rwsem); |
| 531 | 531 | |
| @@ -545,7 +545,7 @@ static int alloc_hpa(struct cxl_region *cxlr, resource_size_t size) · 13 unmodified lines | ||
| 545 | 545 | (cxlr->mode == CXL_DECODER_PMEM && uuid_is_null(&p->uuid))) |
| 546 | 546 | return -ENXIO; |
| 547 | 547 | |
| 548 | − div_u64_rem(size, SZ_256M * p->interleave_ways, &remainder); | |
| 548 | + div64_u64_rem(size, (u64)SZ_256M * p->interleave_ways, &remainder); | |
| 549 | 549 | if (remainder) |
| 550 | 550 | return -EINVAL; |
| 551 | 551 | |
| @@ -382,7 +382,7 @@ static int cxl_pci_mbox_send(struct cxl_memdev_state *mds, · 381 unmodified lines | ||
| 382 | 382 | return rc; |
| 383 | 383 | } |
| 384 | 384 | |
| 385 | −static int cxl_pci_setup_mailbox(struct cxl_memdev_state *mds) | |
| 385 | +static int cxl_pci_setup_mailbox(struct cxl_memdev_state *mds, bool irq_avail) | |
| 386 | 386 | { |
| 387 | 387 | struct cxl_dev_state *cxlds = &mds->cxlds; |
| 388 | 388 | const int cap = readl(cxlds->regs.mbox + CXLDEV_MBOX_CAPS_OFFSET); |
| @@ -441,7 +441,7 @@ static int cxl_pci_setup_mailbox(struct cxl_memdev_state *mds) · 52 unmodified lines | ||
| 441 | 441 | INIT_DELAYED_WORK(&mds->security.poll_dwork, cxl_mbox_sanitize_work); |
| 442 | 442 | |
| 443 | 443 | /* background command interrupts are optional */ |
| 444 | − if (!(cap & CXLDEV_MBOX_CAP_BG_CMD_IRQ)) | |
| 444 | + if (!(cap & CXLDEV_MBOX_CAP_BG_CMD_IRQ) || !irq_avail) | |
| 445 | 445 | return 0; |
| 446 | 446 | |
| 447 | 447 | msgnum = FIELD_GET(CXLDEV_MBOX_CAP_IRQ_MSGNUM_MASK, cap); |
| @@ -588,7 +588,7 @@ static int cxl_mem_alloc_event_buf(struct cxl_memdev_state *mds) · 140 unmodified lines | ||
| 588 | 588 | return devm_add_action_or_reset(mds->cxlds.dev, free_event_buf, buf); |
| 589 | 589 | } |
| 590 | 590 | |
| 591 | −static int cxl_alloc_irq_vectors(struct pci_dev *pdev) | |
| 591 | +static bool cxl_alloc_irq_vectors(struct pci_dev *pdev) | |
| 592 | 592 | { |
| 593 | 593 | int nvecs; |
| 594 | 594 | |
| @@ -605,9 +605,9 @@ static int cxl_alloc_irq_vectors(struct pci_dev *pdev) · 10 unmodified lines | ||
| 605 | 605 | PCI_IRQ_MSIX | PCI_IRQ_MSI); |
| 606 | 606 | if (nvecs < 1) { |
| 607 | 607 | dev_dbg(&pdev->dev, "Failed to alloc irq vectors: %d\n", nvecs); |
| 608 | − return -ENXIO; | |
| 608 | + return false; | |
| 609 | 609 | } |
| 610 | − return 0; | |
| 610 | + return true; | |
| 611 | 611 | } |
| 612 | 612 | |
| 613 | 613 | static irqreturn_t cxl_event_thread(int irq, void *id) |
| @@ -743,7 +743,7 @@ static bool cxl_event_int_is_fw(u8 setting) · 129 unmodified lines | ||
| 743 | 743 | } |
| 744 | 744 | |
| 745 | 745 | static int cxl_event_config(struct pci_host_bridge *host_bridge, |
| 746 | − struct cxl_memdev_state *mds) | |
| 746 | + struct cxl_memdev_state *mds, bool irq_avail) | |
| 747 | 747 | { |
| 748 | 748 | struct cxl_event_interrupt_policy policy; |
| 749 | 749 | int rc; |
| @@ -755,6 +755,11 @@ static int cxl_event_config(struct pci_host_bridge *host_bridge, · 5 unmodified lines | ||
| 755 | 755 | if (!host_bridge->native_cxl_error) |
| 756 | 756 | return 0; |
| 757 | 757 | |
| 758 | + if (!irq_avail) { | |
| 759 | + dev_info(mds->cxlds.dev, "No interrupt support, disable event processing.\n"); | |
| 760 | + return 0; | |
| 761 | + } | |
| 762 | + | |
| 758 | 763 | rc = cxl_mem_alloc_event_buf(mds); |
| 759 | 764 | if (rc) |
| 760 | 765 | return rc; |
| @@ -789,6 +794,7 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) · 28 unmodified lines | ||
| 789 | 794 | struct cxl_register_map map; |
| 790 | 795 | struct cxl_memdev *cxlmd; |
| 791 | 796 | int i, rc, pmu_count; |
| 797 | + bool irq_avail; | |
| 792 | 798 | |
| 793 | 799 | /* |
| 794 | 800 | * Double check the anonymous union trickery in struct cxl_regs |
| @@ -846,11 +852,9 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) · 51 unmodified lines | ||
| 846 | 852 | else |
| 847 | 853 | dev_warn(&pdev->dev, "Media not active (%d)\n", rc); |
| 848 | 854 | |
| 849 | − rc = cxl_alloc_irq_vectors(pdev); | |
| 850 | − if (rc) | |
| 851 | − return rc; | |
| 855 | + irq_avail = cxl_alloc_irq_vectors(pdev); | |
| 852 | 856 | |
| 853 | − rc = cxl_pci_setup_mailbox(mds); | |
| 857 | + rc = cxl_pci_setup_mailbox(mds, irq_avail); | |
| 854 | 858 | if (rc) |
| 855 | 859 | return rc; |
| 856 | 860 | |
| @@ -909,7 +913,7 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) · 52 unmodified lines | ||
| 909 | 913 | } |
| 910 | 914 | } |
| 911 | 915 | |
| 912 | − rc = cxl_event_config(host_bridge, mds); | |
| 916 | + rc = cxl_event_config(host_bridge, mds, irq_avail); | |
| 913 | 917 | if (rc) |
| 914 | 918 | return rc; |
| 915 | 919 | |
| @@ -102,7 +102,7 @@ static atomic64_t dma_fence_context_counter = ATOMIC64_INIT(1); · 101 unmodified lines | ||
| 102 | 102 | * |
| 103 | 103 | * * Drivers are allowed to call dma_fence_wait() from their &mmu_notifier |
| 104 | 104 | * respectively &mmu_interval_notifier callbacks. This means any code required |
| 105 | − * for fence completeion cannot allocate memory with GFP_NOFS or GFP_NOIO. | |
| 105 | + * for fence completion cannot allocate memory with GFP_NOFS or GFP_NOIO. | |
| 106 | 106 | * Only GFP_ATOMIC is permissible, which might fail. |
| 107 | 107 | * |
| 108 | 108 | * Note that only GPU drivers have a reasonable excuse for both requiring |
| @@ -522,7 +522,7 @@ dma_fence_wait_timeout(struct dma_fence *fence, bool intr, signed long timeout) · 413 unmodified lines | ||
| 522 | 522 | EXPORT_SYMBOL(dma_fence_wait_timeout); |
| 523 | 523 | |
| 524 | 524 | /** |
| 525 | − * dma_fence_release - default relese function for fences | |
| 525 | + * dma_fence_release - default release function for fences | |
| 526 | 526 | * @kref: &dma_fence.recfount |
| 527 | 527 | * |
| 528 | 528 | * This is the default release functions for &dma_fence. Drivers shouldn't call |
| @@ -974,8 +974,8 @@ void dma_fence_set_deadline(struct dma_fence *fence, ktime_t deadline) · 445 unmodified lines | ||
| 974 | 974 | EXPORT_SYMBOL(dma_fence_set_deadline); |
| 975 | 975 | |
| 976 | 976 | /** |
| 977 | − * dma_fence_describe - Dump fence describtion into seq_file | |
| 978 | − * @fence: the 6fence to describe | |
| 977 | + * dma_fence_describe - Dump fence description into seq_file | |
| 978 | + * @fence: the fence to describe | |
| 979 | 979 | * @seq: the seq_file to put the textual description into |
| 980 | 980 | * |
| 981 | 981 | * Dump a textual description of the fence and it's state into the seq_file. |
| @@ -405,7 +405,7 @@ static void dma_resv_iter_walk_unlocked(struct dma_resv_iter *cursor) · 404 unmodified lines | ||
| 405 | 405 | * |
| 406 | 406 | * Beware that the iterator can be restarted. Code which accumulates statistics |
| 407 | 407 | * or similar needs to check for this with dma_resv_iter_is_restarted(). For |
| 408 | − * this reason prefer the locked dma_resv_iter_first() whenver possible. | |
| 408 | + * this reason prefer the locked dma_resv_iter_first() whenever possible. | |
| 409 | 409 | * |
| 410 | 410 | * Returns the first fence from an unlocked dma_resv obj. |
| 411 | 411 | */ |
| @@ -428,7 +428,7 @@ EXPORT_SYMBOL(dma_resv_iter_first_unlocked); · 16 unmodified lines | ||
| 428 | 428 | * |
| 429 | 429 | * Beware that the iterator can be restarted. Code which accumulates statistics |
| 430 | 430 | * or similar needs to check for this with dma_resv_iter_is_restarted(). For |
| 431 | − * this reason prefer the locked dma_resv_iter_next() whenver possible. | |
| 431 | + * this reason prefer the locked dma_resv_iter_next() whenever possible. | |
| 432 | 432 | * |
| 433 | 433 | * Returns the next fence from an unlocked dma_resv obj. |
| 434 | 434 | */ |
| @@ -168,10 +168,7 @@ static vm_fault_t cma_heap_vm_fault(struct vm_fault *vmf) · 167 unmodified lines | ||
| 168 | 168 | if (vmf->pgoff > buffer->pagecount) |
| 169 | 169 | return VM_FAULT_SIGBUS; |
| 170 | 170 | |
| 171 | − vmf->page = buffer->pages[vmf->pgoff]; | |
| 172 | − get_page(vmf->page); | |
| 173 | − | |
| 174 | − return 0; | |
| 171 | + return vmf_insert_pfn(vma, vmf->address, page_to_pfn(buffer->pages[vmf->pgoff])); | |
| 175 | 172 | } |
| 176 | 173 | |
| 177 | 174 | static const struct vm_operations_struct dma_heap_vm_ops = { |
| @@ -185,6 +182,8 @@ static int cma_heap_mmap(struct dma_buf *dmabuf, struct vm_area_struct *vma) · 7 unmodified lines | ||
| 185 | 182 | if ((vma->vm_flags & (VM_SHARED | VM_MAYSHARE)) == 0) |
| 186 | 183 | return -EINVAL; |
| 187 | 184 | |
| 185 | + vm_flags_set(vma, VM_IO | VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP); | |
| 186 | + | |
| 188 | 187 | vma->vm_ops = &dma_heap_vm_ops; |
| 189 | 188 | vma->vm_private_data = buffer; |
| 190 | 189 | |
| @@ -222,8 +222,14 @@ struct atdma_sg { · 221 unmodified lines | ||
| 222 | 222 | * @vd: pointer to the virtual dma descriptor. |
| 223 | 223 | * @atchan: pointer to the atmel dma channel. |
| 224 | 224 | * @total_len: total transaction byte count |
| 225 | − * @sg_len: number of sg entries. | |
| 225 | + * @sglen: number of sg entries. | |
| 226 | 226 | * @sg: array of sgs. |
| 227 | + * @boundary: number of transfers to perform before the automatic address increment operation | |
| 228 | + * @dst_hole: value to add to the destination address when the boundary has been reached | |
| 229 | + * @src_hole: value to add to the source address when the boundary has been reached | |
| 230 | + * @memset_buffer: buffer used for the memset operation | |
| 231 | + * @memset_paddr: physical address of the buffer used for the memset operation | |
| 232 | + * @memset_vaddr: virtual address of the buffer used for the memset operation | |
| 227 | 233 | */ |
| 228 | 234 | struct at_desc { |
| 229 | 235 | struct virt_dma_desc vd; |
| @@ -245,7 +251,10 @@ struct at_desc { · 15 unmodified lines | ||
| 245 | 251 | /*-- Channels --------------------------------------------------------*/ |
| 246 | 252 | |
| 247 | 253 | /** |
| 248 | − * atc_status - information bits stored in channel status flag | |
| 254 | + * enum atc_status - information bits stored in channel status flag | |
| 255 | + * | |
| 256 | + * @ATC_IS_PAUSED: If channel is pauses | |
| 257 | + * @ATC_IS_CYCLIC: If channel is cyclic | |
| 249 | 258 | * |
| 250 | 259 | * Manipulated with atomic operations. |
| 251 | 260 | */ |
| @@ -282,7 +291,6 @@ struct at_dma_chan { · 30 unmodified lines | ||
| 282 | 291 | u32 save_cfg; |
| 283 | 292 | u32 save_dscr; |
| 284 | 293 | struct dma_slave_config dma_sconfig; |
| 285 | − bool cyclic; | |
| 286 | 294 | struct at_desc *desc; |
| 287 | 295 | }; |
| 288 | 296 | |
| @@ -328,12 +336,12 @@ static inline u8 convert_buswidth(enum dma_slave_buswidth addr_width) · 39 unmodified lines | ||
| 328 | 336 | /** |
| 329 | 337 | * struct at_dma - internal representation of an Atmel HDMA Controller |
| 330 | 338 | * @dma_device: dmaengine dma_device object members |
| 331 | − * @atdma_devtype: identifier of DMA controller compatibility | |
| 332 | − * @ch_regs: memory mapped register base | |
| 339 | + * @regs: memory mapped register base | |
| 333 | 340 | * @clk: dma controller clock |
| 334 | 341 | * @save_imr: interrupt mask register that is saved on suspend/resume cycle |
| 335 | 342 | * @all_chan_mask: all channels availlable in a mask |
| 336 | 343 | * @lli_pool: hw lli table |
| 344 | + * @memset_pool: hw memset pool | |
| 337 | 345 | * @chan: channels table to store at_dma_chan structures |
| 338 | 346 | */ |
| 339 | 347 | struct at_dma { |
| @@ -626,6 +634,9 @@ static inline u32 atc_calc_bytes_left(u32 current_len, u32 ctrla) · 286 unmodified lines | ||
| 626 | 634 | |
| 627 | 635 | /** |
| 628 | 636 | * atc_get_llis_residue - Get residue for a hardware linked list transfer |
| 637 | + * @atchan: pointer to an atmel hdmac channel. | |
| 638 | + * @desc: pointer to the descriptor for which the residue is calculated. | |
| 639 | + * @residue: residue to be set to dma_tx_state. | |
| 629 | 640 | * |
| 630 | 641 | * Calculate the residue by removing the length of the Linked List Item (LLI) |
| 631 | 642 | * already transferred from the total length. To get the current LLI we can use |
| @@ -661,10 +672,8 @@ static inline u32 atc_calc_bytes_left(u32 current_len, u32 ctrla) · 29 unmodified lines | ||
| 661 | 672 | * two DSCR values are different, we read again the CTRLA then the DSCR till two |
| 662 | 673 | * consecutive read values from DSCR are equal or till the maximum trials is |
| 663 | 674 | * reach. This algorithm is very unlikely not to find a stable value for DSCR. |
| 664 | − * @atchan: pointer to an atmel hdmac channel. | |
| 665 | − * @desc: pointer to the descriptor for which the residue is calculated. | |
| 666 | − * @residue: residue to be set to dma_tx_state. | |
| 667 | − * Returns 0 on success, -errno otherwise. | |
| 675 | + * | |
| 676 | + * Returns: %0 on success, -errno otherwise. | |
| 668 | 677 | */ |
| 669 | 678 | static int atc_get_llis_residue(struct at_dma_chan *atchan, |
| 670 | 679 | struct at_desc *desc, u32 *residue) |
| @@ -731,7 +740,8 @@ static int atc_get_llis_residue(struct at_dma_chan *atchan, · 60 unmodified lines | ||
| 731 | 740 | * @chan: DMA channel |
| 732 | 741 | * @cookie: transaction identifier to check status of |
| 733 | 742 | * @residue: residue to be updated. |
| 734 | − * Return 0 on success, -errono otherwise. | |
| 743 | + * | |
| 744 | + * Return: %0 on success, -errno otherwise. | |
| 735 | 745 | */ |
| 736 | 746 | static int atc_get_residue(struct dma_chan *chan, dma_cookie_t cookie, |
| 737 | 747 | u32 *residue) |
| @@ -1710,7 +1720,7 @@ static void atc_issue_pending(struct dma_chan *chan) · 972 unmodified lines | ||
| 1710 | 1720 | * atc_alloc_chan_resources - allocate resources for DMA channel |
| 1711 | 1721 | * @chan: allocate descriptor resources for this channel |
| 1712 | 1722 | * |
| 1713 | − * return - the number of allocated descriptors | |
| 1723 | + * Return: the number of allocated descriptors | |
| 1714 | 1724 | */ |
| 1715 | 1725 | static int atc_alloc_chan_resources(struct dma_chan *chan) |
| 1716 | 1726 | { |
| @@ -38,15 +38,17 @@ static int dpaa2_qdma_alloc_chan_resources(struct dma_chan *chan) · 37 unmodified lines | ||
| 38 | 38 | if (!dpaa2_chan->fd_pool) |
| 39 | 39 | goto err; |
| 40 | 40 | |
| 41 | − dpaa2_chan->fl_pool = dma_pool_create("fl_pool", dev, | |
| 42 | − sizeof(struct dpaa2_fl_entry), | |
| 43 | − sizeof(struct dpaa2_fl_entry), 0); | |
| 41 | + dpaa2_chan->fl_pool = | |
| 42 | + dma_pool_create("fl_pool", dev, | |
| 43 | + sizeof(struct dpaa2_fl_entry) * 3, | |
| 44 | + sizeof(struct dpaa2_fl_entry), 0); | |
| 45 | + | |
| 44 | 46 | if (!dpaa2_chan->fl_pool) |
| 45 | 47 | goto err_fd; |
| 46 | 48 | |
| 47 | 49 | dpaa2_chan->sdd_pool = |
| 48 | 50 | dma_pool_create("sdd_pool", dev, |
| 49 | − sizeof(struct dpaa2_qdma_sd_d), | |
| 51 | + sizeof(struct dpaa2_qdma_sd_d) * 2, | |
| 50 | 52 | sizeof(struct dpaa2_qdma_sd_d), 0); |
| 51 | 53 | if (!dpaa2_chan->sdd_pool) |
| 52 | 54 | goto err_fl; |
| @@ -514,11 +514,11 @@ static struct fsl_qdma_queue · 513 unmodified lines | ||
| 514 | 514 | queue_temp = queue_head + i + (j * queue_num); |
| 515 | 515 | |
| 516 | 516 | queue_temp->cq = |
| 517 | − dma_alloc_coherent(&pdev->dev, | |
| 518 | − sizeof(struct fsl_qdma_format) * | |
| 519 | − queue_size[i], | |
| 520 | − &queue_temp->bus_addr, | |
| 521 | − GFP_KERNEL); | |
| 517 | + dmam_alloc_coherent(&pdev->dev, | |
| 518 | + sizeof(struct fsl_qdma_format) * | |
| 519 | + queue_size[i], | |
| 520 | + &queue_temp->bus_addr, | |
| 521 | + GFP_KERNEL); | |
| 522 | 522 | if (!queue_temp->cq) |
| 523 | 523 | return NULL; |
| 524 | 524 | queue_temp->block_base = fsl_qdma->block_base + |
| @@ -563,15 +563,14 @@ static struct fsl_qdma_queue · 38 unmodified lines | ||
| 563 | 563 | /* |
| 564 | 564 | * Buffer for queue command |
| 565 | 565 | */ |
| 566 | − status_head->cq = dma_alloc_coherent(&pdev->dev, | |
| 567 | − sizeof(struct fsl_qdma_format) * | |
| 568 | − status_size, | |
| 569 | − &status_head->bus_addr, | |
| 570 | − GFP_KERNEL); | |
| 571 | − if (!status_head->cq) { | |
| 572 | − devm_kfree(&pdev->dev, status_head); | |
| 566 | + status_head->cq = dmam_alloc_coherent(&pdev->dev, | |
| 567 | + sizeof(struct fsl_qdma_format) * | |
| 568 | + status_size, | |
| 569 | + &status_head->bus_addr, | |
| 570 | + GFP_KERNEL); | |
| 571 | + if (!status_head->cq) | |
| 573 | 572 | return NULL; |
| 574 | − } | |
| 573 | + | |
| 575 | 574 | status_head->n_cq = status_size; |
| 576 | 575 | status_head->virt_head = status_head->cq; |
| 577 | 576 | status_head->virt_tail = status_head->cq; |
| @@ -1268,8 +1267,6 @@ static void fsl_qdma_cleanup_vchan(struct dma_device *dmadev) · 690 unmodified lines | ||
| 1268 | 1267 | |
| 1269 | 1268 | static void fsl_qdma_remove(struct platform_device *pdev) |
| 1270 | 1269 | { |
| 1271 | − int i; | |
| 1272 | − struct fsl_qdma_queue *status; | |
| 1273 | 1270 | struct device_node *np = pdev->dev.of_node; |
| 1274 | 1271 | struct fsl_qdma_engine *fsl_qdma = platform_get_drvdata(pdev); |
| 1275 | 1272 | |
| @@ -1277,12 +1274,6 @@ static void fsl_qdma_remove(struct platform_device *pdev) · 1 unmodified line | ||
| 1277 | 1274 | fsl_qdma_cleanup_vchan(&fsl_qdma->dma_dev); |
| 1278 | 1275 | of_dma_controller_free(np); |
| 1279 | 1276 | dma_async_device_unregister(&fsl_qdma->dma_dev); |
| 1280 | − | |
| 1281 | − for (i = 0; i < fsl_qdma->block_number; i++) { | |
| 1282 | − status = fsl_qdma->status[i]; | |
| 1283 | − dma_free_coherent(&pdev->dev, sizeof(struct fsl_qdma_format) * | |
| 1284 | − status->n_cq, status->cq, status->bus_addr); | |
| 1285 | − } | |
| 1286 | 1277 | } |
| 1287 | 1278 | |
| 1288 | 1279 | static const struct of_device_id fsl_qdma_dt_ids[] = { |
| @@ -2404,6 +2404,11 @@ static int edma_probe(struct platform_device *pdev) · 2403 unmodified lines | ||
| 2404 | 2404 | if (irq > 0) { |
| 2405 | 2405 | irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_ccint", |
| 2406 | 2406 | dev_name(dev)); |
| 2407 | + if (!irq_name) { | |
| 2408 | + ret = -ENOMEM; | |
| 2409 | + goto err_disable_pm; | |
| 2410 | + } | |
| 2411 | + | |
| 2407 | 2412 | ret = devm_request_irq(dev, irq, dma_irq_handler, 0, irq_name, |
| 2408 | 2413 | ecc); |
| 2409 | 2414 | if (ret) { |
| @@ -2420,6 +2425,11 @@ static int edma_probe(struct platform_device *pdev) · 10 unmodified lines | ||
| 2420 | 2425 | if (irq > 0) { |
| 2421 | 2426 | irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_ccerrint", |
| 2422 | 2427 | dev_name(dev)); |
| 2428 | + if (!irq_name) { | |
| 2429 | + ret = -ENOMEM; | |
| 2430 | + goto err_disable_pm; | |
| 2431 | + } | |
| 2432 | + | |
| 2423 | 2433 | ret = devm_request_irq(dev, irq, dma_ccerr_handler, 0, irq_name, |
| 2424 | 2434 | ecc); |
| 2425 | 2435 | if (ret) { |
| @@ -3968,6 +3968,7 @@ static void udma_desc_pre_callback(struct virt_dma_chan *vc, · 3967 unmodified lines | ||
| 3968 | 3968 | { |
| 3969 | 3969 | struct udma_chan *uc = to_udma_chan(&vc->chan); |
| 3970 | 3970 | struct udma_desc *d; |
| 3971 | + u8 status; | |
| 3971 | 3972 | |
| 3972 | 3973 | if (!vd) |
| 3973 | 3974 | return; |
| @@ -3977,12 +3978,12 @@ static void udma_desc_pre_callback(struct virt_dma_chan *vc, · 3 unmodified lines | ||
| 3977 | 3978 | if (d->metadata_size) |
| 3978 | 3979 | udma_fetch_epib(uc, d); |
| 3979 | 3980 | |
| 3980 | − /* Provide residue information for the client */ | |
| 3981 | 3981 | if (result) { |
| 3982 | 3982 | void *desc_vaddr = udma_curr_cppi5_desc_vaddr(d, d->desc_idx); |
| 3983 | 3983 | |
| 3984 | 3984 | if (cppi5_desc_get_type(desc_vaddr) == |
| 3985 | 3985 | CPPI5_INFO0_DESC_TYPE_VAL_HOST) { |
| 3986 | + /* Provide residue information for the client */ | |
| 3986 | 3987 | result->residue = d->residue - |
| 3987 | 3988 | cppi5_hdesc_get_pktlen(desc_vaddr); |
| 3988 | 3989 | if (result->residue) |
| @@ -3991,7 +3992,12 @@ static void udma_desc_pre_callback(struct virt_dma_chan *vc, · 2 unmodified lines | ||
| 3991 | 3992 | result->result = DMA_TRANS_NOERROR; |
| 3992 | 3993 | } else { |
| 3993 | 3994 | result->residue = 0; |
| 3994 | − result->result = DMA_TRANS_NOERROR; | |
| 3995 | + /* Propagate TR Response errors to the client */ | |
| 3996 | + status = d->hwdesc[0].tr_resp_base->status; | |
| 3997 | + if (status) | |
| 3998 | + result->result = DMA_TRANS_ABORTED; | |
| 3999 | + else | |
| 4000 | + result->result = DMA_TRANS_NOERROR; | |
| 3995 | 4001 | } |
| 3996 | 4002 | } |
| 3997 | 4003 | } |
| @@ -29,8 +29,6 @@ static u32 dpll_pin_xa_id; · 28 unmodified lines | ||
| 29 | 29 | WARN_ON_ONCE(!xa_get_mark(&dpll_device_xa, (d)->id, DPLL_REGISTERED)) |
| 30 | 30 | #define ASSERT_DPLL_NOT_REGISTERED(d) \ |
| 31 | 31 | WARN_ON_ONCE(xa_get_mark(&dpll_device_xa, (d)->id, DPLL_REGISTERED)) |
| 32 | −#define ASSERT_PIN_REGISTERED(p) \ | |
| 33 | − WARN_ON_ONCE(!xa_get_mark(&dpll_pin_xa, (p)->id, DPLL_REGISTERED)) | |
| 34 | 32 | |
| 35 | 33 | struct dpll_device_registration { |
| 36 | 34 | struct list_head list; |
| @@ -425,6 +423,53 @@ void dpll_device_unregister(struct dpll_device *dpll, · 388 unmodified lines | ||
| 425 | 423 | } |
| 426 | 424 | EXPORT_SYMBOL_GPL(dpll_device_unregister); |
| 427 | 425 | |
| 426 | +static void dpll_pin_prop_free(struct dpll_pin_properties *prop) | |
| 427 | +{ | |
| 428 | + kfree(prop->package_label); | |
| 429 | + kfree(prop->panel_label); | |
| 430 | + kfree(prop->board_label); | |
| 431 | + kfree(prop->freq_supported); | |
| 432 | +} | |
| 433 | + | |
| 434 | +static int dpll_pin_prop_dup(const struct dpll_pin_properties *src, | |
| 435 | + struct dpll_pin_properties *dst) | |
| 436 | +{ | |
| 437 | + memcpy(dst, src, sizeof(*dst)); | |
| 438 | + if (src->freq_supported && src->freq_supported_num) { | |
| 439 | + size_t freq_size = src->freq_supported_num * | |
| 440 | + sizeof(*src->freq_supported); | |
| 441 | + dst->freq_supported = kmemdup(src->freq_supported, | |
| 442 | + freq_size, GFP_KERNEL); | |
| 443 | + if (!src->freq_supported) | |
| 444 | + return -ENOMEM; | |
| 445 | + } | |
| 446 | + if (src->board_label) { | |
| 447 | + dst->board_label = kstrdup(src->board_label, GFP_KERNEL); | |
| 448 | + if (!dst->board_label) | |
| 449 | + goto err_board_label; | |
| 450 | + } | |
| 451 | + if (src->panel_label) { | |
| 452 | + dst->panel_label = kstrdup(src->panel_label, GFP_KERNEL); | |
| 453 | + if (!dst->panel_label) | |
| 454 | + goto err_panel_label; | |
| 455 | + } | |
| 456 | + if (src->package_label) { | |
| 457 | + dst->package_label = kstrdup(src->package_label, GFP_KERNEL); | |
| 458 | + if (!dst->package_label) | |
| 459 | + goto err_package_label; | |
| 460 | + } | |
| 461 | + | |
| 462 | + return 0; | |
| 463 | + | |
| 464 | +err_package_label: | |
| 465 | + kfree(dst->panel_label); | |
| 466 | +err_panel_label: | |
| 467 | + kfree(dst->board_label); | |
| 468 | +err_board_label: | |
| 469 | + kfree(dst->freq_supported); | |
| 470 | + return -ENOMEM; | |
| 471 | +} | |
| 472 | + | |
| 428 | 473 | static struct dpll_pin * |
| 429 | 474 | dpll_pin_alloc(u64 clock_id, u32 pin_idx, struct module *module, |
| 430 | 475 | const struct dpll_pin_properties *prop) |
| @@ -441,20 +486,24 @@ dpll_pin_alloc(u64 clock_id, u32 pin_idx, struct module *module, · 10 unmodified lines | ||
| 441 | 486 | if (WARN_ON(prop->type < DPLL_PIN_TYPE_MUX || |
| 442 | 487 | prop->type > DPLL_PIN_TYPE_MAX)) { |
| 443 | 488 | ret = -EINVAL; |
| 444 | − goto err; | |
| 489 | + goto err_pin_prop; | |
| 445 | 490 | } |
| 446 | − pin->prop = prop; | |
| 491 | + ret = dpll_pin_prop_dup(prop, &pin->prop); | |
| 492 | + if (ret) | |
| 493 | + goto err_pin_prop; | |
| 447 | 494 | refcount_set(&pin->refcount, 1); |
| 448 | 495 | xa_init_flags(&pin->dpll_refs, XA_FLAGS_ALLOC); |
| 449 | 496 | xa_init_flags(&pin->parent_refs, XA_FLAGS_ALLOC); |
| 450 | 497 | ret = xa_alloc_cyclic(&dpll_pin_xa, &pin->id, pin, xa_limit_32b, |
| 451 | 498 | &dpll_pin_xa_id, GFP_KERNEL); |
| 452 | 499 | if (ret) |
| 453 | − goto err; | |
| 500 | + goto err_xa_alloc; | |
| 454 | 501 | return pin; |
| 455 | −err: | |
| 502 | +err_xa_alloc: | |
| 456 | 503 | xa_destroy(&pin->dpll_refs); |
| 457 | 504 | xa_destroy(&pin->parent_refs); |
| 505 | + dpll_pin_prop_free(&pin->prop); | |
| 506 | +err_pin_prop: | |
| 458 | 507 | kfree(pin); |
| 459 | 508 | return ERR_PTR(ret); |
| 460 | 509 | } |
| @@ -514,6 +563,7 @@ void dpll_pin_put(struct dpll_pin *pin) · 53 unmodified lines | ||
| 514 | 563 | xa_destroy(&pin->dpll_refs); |
| 515 | 564 | xa_destroy(&pin->parent_refs); |
| 516 | 565 | xa_erase(&dpll_pin_xa, pin->id); |
| 566 | + dpll_pin_prop_free(&pin->prop); | |
| 517 | 567 | kfree(pin); |
| 518 | 568 | } |
| 519 | 569 | mutex_unlock(&dpll_lock); |
| @@ -564,8 +614,6 @@ dpll_pin_register(struct dpll_device *dpll, struct dpll_pin *pin, · 44 unmodified lines | ||
| 564 | 614 | WARN_ON(!ops->state_on_dpll_get) || |
| 565 | 615 | WARN_ON(!ops->direction_get)) |
| 566 | 616 | return -EINVAL; |
| 567 | − if (ASSERT_DPLL_REGISTERED(dpll)) | |
| 568 | − return -EINVAL; | |
| 569 | 617 | |
| 570 | 618 | mutex_lock(&dpll_lock); |
| 571 | 619 | if (WARN_ON(!(dpll->module == pin->module && |
| @@ -636,15 +684,13 @@ int dpll_pin_on_pin_register(struct dpll_pin *parent, struct dpll_pin *pin, · 64 unmodified lines | ||
| 636 | 684 | unsigned long i, stop; |
| 637 | 685 | int ret; |
| 638 | 686 | |
| 639 | − if (WARN_ON(parent->prop->type != DPLL_PIN_TYPE_MUX)) | |
| 687 | + if (WARN_ON(parent->prop.type != DPLL_PIN_TYPE_MUX)) | |
| 640 | 688 | return -EINVAL; |
| 641 | 689 | |
| 642 | 690 | if (WARN_ON(!ops) || |
| 643 | 691 | WARN_ON(!ops->state_on_pin_get) || |
| 644 | 692 | WARN_ON(!ops->direction_get)) |
| 645 | 693 | return -EINVAL; |
| 646 | − if (ASSERT_PIN_REGISTERED(parent)) | |
| 647 | − return -EINVAL; | |
| 648 | 694 | |
| 649 | 695 | mutex_lock(&dpll_lock); |
| 650 | 696 | ret = dpll_xa_ref_pin_add(&pin->parent_refs, parent, ops, priv); |
| @@ -44,7 +44,7 @@ struct dpll_device { · 43 unmodified lines | ||
| 44 | 44 | * @module: module of creator |
| 45 | 45 | * @dpll_refs: hold referencees to dplls pin was registered with |
| 46 | 46 | * @parent_refs: hold references to parent pins pin was registered with |
| 47 | − * @prop: pointer to pin properties given by registerer | |
| 47 | + * @prop: pin properties copied from the registerer | |
| 48 | 48 | * @rclk_dev_name: holds name of device when pin can recover clock from it |
| 49 | 49 | * @refcount: refcount |
| 50 | 50 | **/ |
| @@ -55,7 +55,7 @@ struct dpll_pin { · 4 unmodified lines | ||
| 55 | 55 | struct module *module; |
| 56 | 56 | struct xarray dpll_refs; |
| 57 | 57 | struct xarray parent_refs; |
| 58 | − const struct dpll_pin_properties *prop; | |
| 58 | + struct dpll_pin_properties prop; | |
| 59 | 59 | refcount_t refcount; |
| 60 | 60 | }; |
| 61 | 61 | |
| @@ -303,17 +303,17 @@ dpll_msg_add_pin_freq(struct sk_buff *msg, struct dpll_pin *pin, · 302 unmodified lines | ||
| 303 | 303 | if (nla_put_64bit(msg, DPLL_A_PIN_FREQUENCY, sizeof(freq), &freq, |
| 304 | 304 | DPLL_A_PIN_PAD)) |
| 305 | 305 | return -EMSGSIZE; |
| 306 | − for (fs = 0; fs < pin->prop->freq_supported_num; fs++) { | |
| 306 | + for (fs = 0; fs < pin->prop.freq_supported_num; fs++) { | |
| 307 | 307 | nest = nla_nest_start(msg, DPLL_A_PIN_FREQUENCY_SUPPORTED); |
| 308 | 308 | if (!nest) |
| 309 | 309 | return -EMSGSIZE; |
| 310 | − freq = pin->prop->freq_supported[fs].min; | |
| 310 | + freq = pin->prop.freq_supported[fs].min; | |
| 311 | 311 | if (nla_put_64bit(msg, DPLL_A_PIN_FREQUENCY_MIN, sizeof(freq), |
| 312 | 312 | &freq, DPLL_A_PIN_PAD)) { |
| 313 | 313 | nla_nest_cancel(msg, nest); |
| 314 | 314 | return -EMSGSIZE; |
| 315 | 315 | } |
| 316 | − freq = pin->prop->freq_supported[fs].max; | |
| 316 | + freq = pin->prop.freq_supported[fs].max; | |
| 317 | 317 | if (nla_put_64bit(msg, DPLL_A_PIN_FREQUENCY_MAX, sizeof(freq), |
| 318 | 318 | &freq, DPLL_A_PIN_PAD)) { |
| 319 | 319 | nla_nest_cancel(msg, nest); |
| @@ -329,9 +329,9 @@ static bool dpll_pin_is_freq_supported(struct dpll_pin *pin, u32 freq) · 9 unmodified lines | ||
| 329 | 329 | { |
| 330 | 330 | int fs; |
| 331 | 331 | |
| 332 | − for (fs = 0; fs < pin->prop->freq_supported_num; fs++) | |
| 333 | − if (freq >= pin->prop->freq_supported[fs].min && | |
| 334 | − freq <= pin->prop->freq_supported[fs].max) | |
| 332 | + for (fs = 0; fs < pin->prop.freq_supported_num; fs++) | |
| 333 | + if (freq >= pin->prop.freq_supported[fs].min && | |
| 334 | + freq <= pin->prop.freq_supported[fs].max) | |
| 335 | 335 | return true; |
| 336 | 336 | return false; |
| 337 | 337 | } |
| @@ -421,7 +421,7 @@ static int · 83 unmodified lines | ||
| 421 | 421 | dpll_cmd_pin_get_one(struct sk_buff *msg, struct dpll_pin *pin, |
| 422 | 422 | struct netlink_ext_ack *extack) |
| 423 | 423 | { |
| 424 | − const struct dpll_pin_properties *prop = pin->prop; | |
| 424 | + const struct dpll_pin_properties *prop = &pin->prop; | |
| 425 | 425 | struct dpll_pin_ref *ref; |
| 426 | 426 | int ret; |
| 427 | 427 | |
| @@ -553,6 +553,24 @@ __dpll_device_change_ntf(struct dpll_device *dpll) · 125 unmodified lines | ||
| 553 | 553 | return dpll_device_event_send(DPLL_CMD_DEVICE_CHANGE_NTF, dpll); |
| 554 | 554 | } |
| 555 | 555 | |
| 556 | +static bool dpll_pin_available(struct dpll_pin *pin) | |
| 557 | +{ | |
| 558 | + struct dpll_pin_ref *par_ref; | |
| 559 | + unsigned long i; | |
| 560 | + | |
| 561 | + if (!xa_get_mark(&dpll_pin_xa, pin->id, DPLL_REGISTERED)) | |
| 562 | + return false; | |
| 563 | + xa_for_each(&pin->parent_refs, i, par_ref) | |
| 564 | + if (xa_get_mark(&dpll_pin_xa, par_ref->pin->id, | |
| 565 | + DPLL_REGISTERED)) | |
| 566 | + return true; | |
| 567 | + xa_for_each(&pin->dpll_refs, i, par_ref) | |
| 568 | + if (xa_get_mark(&dpll_device_xa, par_ref->dpll->id, | |
| 569 | + DPLL_REGISTERED)) | |
| 570 | + return true; | |
| 571 | + return false; | |
| 572 | +} | |
| 573 | + | |
| 556 | 574 | /** |
| 557 | 575 | * dpll_device_change_ntf - notify that the dpll device has been changed |
| 558 | 576 | * @dpll: registered dpll pointer |
| @@ -579,7 +597,7 @@ dpll_pin_event_send(enum dpll_cmd event, struct dpll_pin *pin) · 20 unmodified lines | ||
| 579 | 597 | int ret = -ENOMEM; |
| 580 | 598 | void *hdr; |
| 581 | 599 | |
| 582 | − if (WARN_ON(!xa_get_mark(&dpll_pin_xa, pin->id, DPLL_REGISTERED))) | |
| 600 | + if (!dpll_pin_available(pin)) | |
| 583 | 601 | return -ENODEV; |
| 584 | 602 | |
| 585 | 603 | msg = genlmsg_new(NLMSG_GOODSIZE, GFP_KERNEL); |
| @@ -717,7 +735,7 @@ dpll_pin_on_pin_state_set(struct dpll_pin *pin, u32 parent_idx, · 131 unmodified lines | ||
| 717 | 735 | int ret; |
| 718 | 736 | |
| 719 | 737 | if (!(DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE & |
| 720 | − pin->prop->capabilities)) { | |
| 738 | + pin->prop.capabilities)) { | |
| 721 | 739 | NL_SET_ERR_MSG(extack, "state changing is not allowed"); |
| 722 | 740 | return -EOPNOTSUPP; |
| 723 | 741 | } |
| @@ -753,7 +771,7 @@ dpll_pin_state_set(struct dpll_device *dpll, struct dpll_pin *pin, · 29 unmodified lines | ||
| 753 | 771 | int ret; |
| 754 | 772 | |
| 755 | 773 | if (!(DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE & |
| 756 | − pin->prop->capabilities)) { | |
| 774 | + pin->prop.capabilities)) { | |
| 757 | 775 | NL_SET_ERR_MSG(extack, "state changing is not allowed"); |
| 758 | 776 | return -EOPNOTSUPP; |
| 759 | 777 | } |
| @@ -780,7 +798,7 @@ dpll_pin_prio_set(struct dpll_device *dpll, struct dpll_pin *pin, · 20 unmodified lines | ||
| 780 | 798 | int ret; |
| 781 | 799 | |
| 782 | 800 | if (!(DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE & |
| 783 | − pin->prop->capabilities)) { | |
| 801 | + pin->prop.capabilities)) { | |
| 784 | 802 | NL_SET_ERR_MSG(extack, "prio changing is not allowed"); |
| 785 | 803 | return -EOPNOTSUPP; |
| 786 | 804 | } |
| @@ -808,7 +826,7 @@ dpll_pin_direction_set(struct dpll_pin *pin, struct dpll_device *dpll, · 21 unmodified lines | ||
| 808 | 826 | int ret; |
| 809 | 827 | |
| 810 | 828 | if (!(DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE & |
| 811 | − pin->prop->capabilities)) { | |
| 829 | + pin->prop.capabilities)) { | |
| 812 | 830 | NL_SET_ERR_MSG(extack, "direction changing is not allowed"); |
| 813 | 831 | return -EOPNOTSUPP; |
| 814 | 832 | } |
| @@ -838,8 +856,8 @@ dpll_pin_phase_adj_set(struct dpll_pin *pin, struct nlattr *phase_adj_attr, · 23 unmodified lines | ||
| 838 | 856 | int ret; |
| 839 | 857 | |
| 840 | 858 | phase_adj = nla_get_s32(phase_adj_attr); |
| 841 | − if (phase_adj > pin->prop->phase_range.max || | |
| 842 | − phase_adj < pin->prop->phase_range.min) { | |
| 859 | + if (phase_adj > pin->prop.phase_range.max || | |
| 860 | + phase_adj < pin->prop.phase_range.min) { | |
| 843 | 861 | NL_SET_ERR_MSG_ATTR(extack, phase_adj_attr, |
| 844 | 862 | "phase adjust value not supported"); |
| 845 | 863 | return -EINVAL; |
| @@ -1023,7 +1041,7 @@ dpll_pin_find(u64 clock_id, struct nlattr *mod_name_attr, · 177 unmodified lines | ||
| 1023 | 1041 | unsigned long i; |
| 1024 | 1042 | |
| 1025 | 1043 | xa_for_each_marked(&dpll_pin_xa, i, pin, DPLL_REGISTERED) { |
| 1026 | − prop = pin->prop; | |
| 1044 | + prop = &pin->prop; | |
| 1027 | 1045 | cid_match = clock_id ? pin->clock_id == clock_id : true; |
| 1028 | 1046 | mod_match = mod_name_attr && module_name(pin->module) ? |
| 1029 | 1047 | !nla_strcmp(mod_name_attr, |
| @@ -1130,6 +1148,10 @@ int dpll_nl_pin_id_get_doit(struct sk_buff *skb, struct genl_info *info) · 100 unmodified lines | ||
| 1130 | 1148 | } |
| 1131 | 1149 | pin = dpll_pin_find_from_nlattr(info); |
| 1132 | 1150 | if (!IS_ERR(pin)) { |
| 1151 | + if (!dpll_pin_available(pin)) { | |
| 1152 | + nlmsg_free(msg); | |
| 1153 | + return -ENODEV; | |
| 1154 | + } | |
| 1133 | 1155 | ret = dpll_msg_add_pin_handle(msg, pin); |
| 1134 | 1156 | if (ret) { |
| 1135 | 1157 | nlmsg_free(msg); |
| @@ -1179,6 +1201,8 @@ int dpll_nl_pin_get_dumpit(struct sk_buff *skb, struct netlink_callback *cb) · 43 unmodified lines | ||
| 1179 | 1201 | |
| 1180 | 1202 | xa_for_each_marked_start(&dpll_pin_xa, i, pin, DPLL_REGISTERED, |
| 1181 | 1203 | ctx->idx) { |
| 1204 | + if (!dpll_pin_available(pin)) | |
| 1205 | + continue; | |
| 1182 | 1206 | hdr = genlmsg_put(skb, NETLINK_CB(cb->skb).portid, |
| 1183 | 1207 | cb->nlh->nlmsg_seq, |
| 1184 | 1208 | &dpll_nl_family, NLM_F_MULTI, |
| @@ -1441,7 +1465,8 @@ int dpll_pin_pre_doit(const struct genl_split_ops *ops, struct sk_buff *skb, · 256 unmodified lines | ||
| 1441 | 1465 | } |
| 1442 | 1466 | info->user_ptr[0] = xa_load(&dpll_pin_xa, |
| 1443 | 1467 | nla_get_u32(info->attrs[DPLL_A_PIN_ID])); |
| 1444 | − if (!info->user_ptr[0]) { | |
| 1468 | + if (!info->user_ptr[0] || | |
| 1469 | + !dpll_pin_available(info->user_ptr[0])) { | |
| 1445 | 1470 | NL_SET_ERR_MSG(info->extack, "pin not found"); |
| 1446 | 1471 | ret = -ENODEV; |
| 1447 | 1472 | goto unlock_dev; |
| @@ -118,10 +118,9 @@ static int textual_leaf_to_string(const u32 *block, char *buf, size_t size) · 117 unmodified lines | ||
| 118 | 118 | * @buf: where to put the string |
| 119 | 119 | * @size: size of @buf, in bytes |
| 120 | 120 | * |
| 121 | − * The string is taken from a minimal ASCII text descriptor leaf after | |
| 122 | − * the immediate entry with @key. The string is zero-terminated. | |
| 123 | − * An overlong string is silently truncated such that it and the | |
| 124 | − * zero byte fit into @size. | |
| 121 | + * The string is taken from a minimal ASCII text descriptor leaf just after the entry with the | |
| 122 | + * @key. The string is zero-terminated. An overlong string is silently truncated such that it | |
| 123 | + * and the zero byte fit into @size. | |
| 125 | 124 | * |
| 126 | 125 | * Returns strlen(buf) or a negative error code. |
| 127 | 126 | */ |
| @@ -368,8 +367,17 @@ static ssize_t show_text_leaf(struct device *dev, · 240 unmodified lines | ||
| 368 | 367 | for (i = 0; i < ARRAY_SIZE(directories) && !!directories[i]; ++i) { |
| 369 | 368 | int result = fw_csr_string(directories[i], attr->key, buf, bufsize); |
| 370 | 369 | // Detected. |
| 371 | − if (result >= 0) | |
| 370 | + if (result >= 0) { | |
| 372 | 371 | ret = result; |
| 372 | + } else if (i == 0 && attr->key == CSR_VENDOR) { | |
| 373 | + // Sony DVMC-DA1 has configuration ROM such that the descriptor leaf entry | |
| 374 | + // in the root directory follows to the directory entry for vendor ID | |
| 375 | + // instead of the immediate value for vendor ID. | |
| 376 | + result = fw_csr_string(directories[i], CSR_DIRECTORY | attr->key, buf, | |
| 377 | + bufsize); | |
| 378 | + if (result >= 0) | |
| 379 | + ret = result; | |
| 380 | + } | |
| 373 | 381 | } |
| 374 | 382 | |
| 375 | 383 | if (ret >= 0) { |
| @@ -182,6 +182,7 @@ config MTK_ADSP_IPC · 181 unmodified lines | ||
| 182 | 182 | config SYSFB |
| 183 | 183 | bool |
| 184 | 184 | select BOOT_VESA_SUPPORT |
| 185 | + select SCREEN_INFO | |
| 185 | 186 | |
| 186 | 187 | config SYSFB_SIMPLEFB |
| 187 | 188 | bool "Mark VGA/VBE/EFI FB as generic system framebuffer" |
| @@ -107,12 +107,12 @@ struct ffa_drv_info { · 106 unmodified lines | ||
| 107 | 107 | struct work_struct notif_pcpu_work; |
| 108 | 108 | struct work_struct irq_work; |
| 109 | 109 | struct xarray partition_info; |
| 110 | − unsigned int partition_count; | |
| 111 | 110 | DECLARE_HASHTABLE(notifier_hash, ilog2(FFA_MAX_NOTIFICATIONS)); |
| 112 | 111 | struct mutex notify_lock; /* lock to protect notifier hashtable */ |
| 113 | 112 | }; |
| 114 | 113 | |
| 115 | 114 | static struct ffa_drv_info *drv_info; |
| 115 | +static void ffa_partitions_cleanup(void); | |
| 116 | 116 | |
| 117 | 117 | /* |
| 118 | 118 | * The driver must be able to support all the versions from the earliest |
| @@ -733,6 +733,11 @@ static void __do_sched_recv_cb(u16 part_id, u16 vcpu, bool is_per_vcpu) · 614 unmodified lines | ||
| 733 | 733 | void *cb_data; |
| 734 | 734 | |
| 735 | 735 | partition = xa_load(&drv_info->partition_info, part_id); |
| 736 | + if (!partition) { | |
| 737 | + pr_err("%s: Invalid partition ID 0x%x\n", __func__, part_id); | |
| 738 | + return; | |
| 739 | + } | |
| 740 | + | |
| 736 | 741 | read_lock(&partition->rw_lock); |
| 737 | 742 | callback = partition->callback; |
| 738 | 743 | cb_data = partition->cb_data; |
| @@ -915,6 +920,11 @@ static int ffa_sched_recv_cb_update(u16 part_id, ffa_sched_recv_cb callback, · 176 unmodified lines | ||
| 915 | 920 | return -EOPNOTSUPP; |
| 916 | 921 | |
| 917 | 922 | partition = xa_load(&drv_info->partition_info, part_id); |
| 923 | + if (!partition) { | |
| 924 | + pr_err("%s: Invalid partition ID 0x%x\n", __func__, part_id); | |
| 925 | + return -EINVAL; | |
| 926 | + } | |
| 927 | + | |
| 918 | 928 | write_lock(&partition->rw_lock); |
| 919 | 929 | |
| 920 | 930 | cb_valid = !!partition->callback; |
| @@ -1186,9 +1196,9 @@ void ffa_device_match_uuid(struct ffa_device *ffa_dev, const uuid_t *uuid) · 265 unmodified lines | ||
| 1186 | 1196 | kfree(pbuf); |
| 1187 | 1197 | } |
| 1188 | 1198 | |
| 1189 | −static void ffa_setup_partitions(void) | |
| 1199 | +static int ffa_setup_partitions(void) | |
| 1190 | 1200 | { |
| 1191 | − int count, idx; | |
| 1201 | + int count, idx, ret; | |
| 1192 | 1202 | uuid_t uuid; |
| 1193 | 1203 | struct ffa_device *ffa_dev; |
| 1194 | 1204 | struct ffa_dev_part_info *info; |
| @@ -1197,7 +1207,7 @@ static void ffa_setup_partitions(void) · 2 unmodified lines | ||
| 1197 | 1207 | count = ffa_partition_probe(&uuid_null, &pbuf); |
| 1198 | 1208 | if (count <= 0) { |
| 1199 | 1209 | pr_info("%s: No partitions found, error %d\n", __func__, count); |
| 1200 | − return; | |
| 1210 | + return -EINVAL; | |
| 1201 | 1211 | } |
| 1202 | 1212 | |
| 1203 | 1213 | xa_init(&drv_info->partition_info); |
| @@ -1226,40 +1236,53 @@ static void ffa_setup_partitions(void) · 22 unmodified lines | ||
| 1226 | 1236 | ffa_device_unregister(ffa_dev); |
| 1227 | 1237 | continue; |
| 1228 | 1238 | } |
| 1229 | − xa_store(&drv_info->partition_info, tpbuf->id, info, GFP_KERNEL); | |
| 1239 | + rwlock_init(&info->rw_lock); | |
| 1240 | + ret = xa_insert(&drv_info->partition_info, tpbuf->id, | |
| 1241 | + info, GFP_KERNEL); | |
| 1242 | + if (ret) { | |
| 1243 | + pr_err("%s: failed to save partition ID 0x%x - ret:%d\n", | |
| 1244 | + __func__, tpbuf->id, ret); | |
| 1245 | + ffa_device_unregister(ffa_dev); | |
| 1246 | + kfree(info); | |
| 1247 | + } | |
| 1230 | 1248 | } |
| 1231 | − drv_info->partition_count = count; | |
| 1232 | 1249 | |
| 1233 | 1250 | kfree(pbuf); |
| 1234 | 1251 | |
| 1235 | 1252 | /* Allocate for the host */ |
| 1236 | 1253 | info = kzalloc(sizeof(*info), GFP_KERNEL); |
| 1237 | − if (!info) | |
| 1238 | − return; | |
| 1239 | − xa_store(&drv_info->partition_info, drv_info->vm_id, info, GFP_KERNEL); | |
| 1240 | − drv_info->partition_count++; | |
| 1254 | + if (!info) { | |
| 1255 | + pr_err("%s: failed to alloc Host partition ID 0x%x. Abort.\n", | |
| 1256 | + __func__, drv_info->vm_id); | |
| 1257 | + /* Already registered devices are freed on bus_exit */ | |
| 1258 | + ffa_partitions_cleanup(); | |
| 1259 | + return -ENOMEM; | |
| 1260 | + } | |
| 1261 | + | |
| 1262 | + rwlock_init(&info->rw_lock); | |
| 1263 | + ret = xa_insert(&drv_info->partition_info, drv_info->vm_id, | |
| 1264 | + info, GFP_KERNEL); | |
| 1265 | + if (ret) { | |
| 1266 | + pr_err("%s: failed to save Host partition ID 0x%x - ret:%d. Abort.\n", | |
| 1267 | + __func__, drv_info->vm_id, ret); | |
| 1268 | + kfree(info); | |
| 1269 | + /* Already registered devices are freed on bus_exit */ | |
| 1270 | + ffa_partitions_cleanup(); | |
| 1271 | + } | |
| 1272 | + | |
| 1273 | + return ret; | |
| 1241 | 1274 | } |
| 1242 | 1275 | |
| 1243 | 1276 | static void ffa_partitions_cleanup(void) |
| 1244 | 1277 | { |
| 1245 | − struct ffa_dev_part_info **info; | |
| 1246 | − int idx, count = drv_info->partition_count; | |
| 1247 | − | |
| 1248 | − if (!count) | |
| 1249 | − return; | |
| 1250 | − | |
| 1251 | − info = kcalloc(count, sizeof(*info), GFP_KERNEL); | |
| 1252 | − if (!info) | |
| 1253 | − return; | |
| 1254 | − | |
| 1255 | − xa_extract(&drv_info->partition_info, (void **)info, 0, VM_ID_MASK, | |
| 1256 | − count, XA_PRESENT); | |
| 1278 | + struct ffa_dev_part_info *info; | |
| 1279 | + unsigned long idx; | |
| 1257 | 1280 | |
| 1258 | − for (idx = 0; idx < count; idx++) | |
| 1259 | − kfree(info[idx]); | |
| 1260 | − kfree(info); | |
| 1281 | + xa_for_each(&drv_info->partition_info, idx, info) { | |
| 1282 | + xa_erase(&drv_info->partition_info, idx); | |
| 1283 | + kfree(info); | |
| 1284 | + } | |
| 1261 | 1285 | |
| 1262 | − drv_info->partition_count = 0; | |
| 1263 | 1286 | xa_destroy(&drv_info->partition_info); |
| 1264 | 1287 | } |
| 1265 | 1288 | |
| @@ -1508,7 +1531,11 @@ static int __init ffa_init(void) · 242 unmodified lines | ||
| 1508 | 1531 | |
| 1509 | 1532 | ffa_notifications_setup(); |
| 1510 | 1533 | |
| 1511 | − ffa_setup_partitions(); | |
| 1534 | + ret = ffa_setup_partitions(); | |
| 1535 | + if (ret) { | |
| 1536 | + pr_err("failed to setup partitions\n"); | |
| 1537 | + goto cleanup_notifs; | |
| 1538 | + } | |
| 1512 | 1539 | |
| 1513 | 1540 | ret = ffa_sched_recv_cb_update(drv_info->vm_id, ffa_self_notif_handle, |
| 1514 | 1541 | drv_info, true); |
| @@ -1516,6 +1543,9 @@ static int __init ffa_init(void) · 1 unmodified line | ||
| 1516 | 1543 | pr_info("Failed to register driver sched callback %d\n", ret); |
| 1517 | 1544 | |
| 1518 | 1545 | return 0; |
| 1546 | + | |
| 1547 | +cleanup_notifs: | |
| 1548 | + ffa_notifications_cleanup(); | |
| 1519 | 1549 | free_pages: |
| 1520 | 1550 | if (drv_info->tx_buffer) |
| 1521 | 1551 | free_pages_exact(drv_info->tx_buffer, RXTX_BUFFER_SIZE); |
| @@ -1535,7 +1565,6 @@ static void __exit ffa_exit(void) · 13 unmodified lines | ||
| 1535 | 1565 | ffa_rxtx_unmap(drv_info->vm_id); |
| 1536 | 1566 | free_pages_exact(drv_info->tx_buffer, RXTX_BUFFER_SIZE); |
| 1537 | 1567 | free_pages_exact(drv_info->rx_buffer, RXTX_BUFFER_SIZE); |
| 1538 | − xa_destroy(&drv_info->partition_info); | |
| 1539 | 1568 | kfree(drv_info); |
| 1540 | 1569 | arm_ffa_bus_exit(); |
| 1541 | 1570 | } |
| @@ -13,7 +13,7 @@ · 12 unmodified lines | ||
| 13 | 13 | #include "notify.h" |
| 14 | 14 | |
| 15 | 15 | /* Updated only after ALL the mandatory features for that version are merged */ |
| 16 | −#define SCMI_PROTOCOL_SUPPORTED_VERSION 0x20001 | |
| 16 | +#define SCMI_PROTOCOL_SUPPORTED_VERSION 0x20000 | |
| 17 | 17 | |
| 18 | 18 | enum scmi_clock_protocol_cmd { |
| 19 | 19 | CLOCK_ATTRIBUTES = 0x3, |
| @@ -954,8 +954,7 @@ static int scmi_clock_protocol_init(const struct scmi_protocol_handle *ph) · 934 unmodified lines | ||
| 954 | 954 | scmi_clock_describe_rates_get(ph, clkid, clk); |
| 955 | 955 | } |
| 956 | 956 | |
| 957 | − if (PROTOCOL_REV_MAJOR(version) >= 0x2 && | |
| 958 | − PROTOCOL_REV_MINOR(version) >= 0x1) { | |
| 957 | + if (PROTOCOL_REV_MAJOR(version) >= 0x3) { | |
| 959 | 958 | cinfo->clock_config_set = scmi_clock_config_set_v2; |
| 960 | 959 | cinfo->clock_config_get = scmi_clock_config_get_v2; |
| 961 | 960 | } else { |
| @@ -314,6 +314,7 @@ void shmem_fetch_notification(struct scmi_shared_mem __iomem *shmem, · 313 unmodified lines | ||
| 314 | 314 | void shmem_clear_channel(struct scmi_shared_mem __iomem *shmem); |
| 315 | 315 | bool shmem_poll_done(struct scmi_shared_mem __iomem *shmem, |
| 316 | 316 | struct scmi_xfer *xfer); |
| 317 | +bool shmem_channel_free(struct scmi_shared_mem __iomem *shmem); | |
| 317 | 318 | |
| 318 | 319 | /* declarations for message passing transports */ |
| 319 | 320 | struct scmi_msg_payld; |
| @@ -45,6 +45,20 @@ static void rx_callback(struct mbox_client *cl, void *m) · 44 unmodified lines | ||
| 45 | 45 | { |
| 46 | 46 | struct scmi_mailbox *smbox = client_to_scmi_mailbox(cl); |
| 47 | 47 | |
| 48 | + /* | |
| 49 | + * An A2P IRQ is NOT valid when received while the platform still has | |
| 50 | + * the ownership of the channel, because the platform at first releases | |
| 51 | + * the SMT channel and then sends the completion interrupt. | |
| 52 | + * | |
| 53 | + * This addresses a possible race condition in which a spurious IRQ from | |
| 54 | + * a previous timed-out reply which arrived late could be wrongly | |
| 55 | + * associated with the next pending transaction. | |
| 56 | + */ | |
| 57 | + if (cl->knows_txdone && !shmem_channel_free(smbox->shmem)) { | |
| 58 | + dev_warn(smbox->cinfo->dev, "Ignoring spurious A2P IRQ !\n"); | |
| 59 | + return; | |
| 60 | + } | |
| 61 | + | |
| 48 | 62 | scmi_rx_callback(smbox->cinfo, shmem_read_header(smbox->shmem), NULL); |
| 49 | 63 | } |
| 50 | 64 | |
| @@ -350,8 +350,8 @@ process_response_opp(struct scmi_opp *opp, unsigned int loop_idx, · 349 unmodified lines | ||
| 350 | 350 | } |
| 351 | 351 | |
| 352 | 352 | static inline void |
| 353 | −process_response_opp_v4(struct perf_dom_info *dom, struct scmi_opp *opp, | |
| 354 | − unsigned int loop_idx, | |
| 353 | +process_response_opp_v4(struct device *dev, struct perf_dom_info *dom, | |
| 354 | + struct scmi_opp *opp, unsigned int loop_idx, | |
| 355 | 355 | const struct scmi_msg_resp_perf_describe_levels_v4 *r) |
| 356 | 356 | { |
| 357 | 357 | opp->perf = le32_to_cpu(r->opp[loop_idx].perf_val); |
| @@ -362,10 +362,23 @@ process_response_opp_v4(struct perf_dom_info *dom, struct scmi_opp *opp, · 4 unmodified lines | ||
| 362 | 362 | /* Note that PERF v4 reports always five 32-bit words */ |
| 363 | 363 | opp->indicative_freq = le32_to_cpu(r->opp[loop_idx].indicative_freq); |
| 364 | 364 | if (dom->level_indexing_mode) { |
| 365 | + int ret; | |
| 366 | + | |
| 365 | 367 | opp->level_index = le32_to_cpu(r->opp[loop_idx].level_index); |
| 366 | 368 | |
| 367 | − xa_store(&dom->opps_by_idx, opp->level_index, opp, GFP_KERNEL); | |
| 368 | − xa_store(&dom->opps_by_lvl, opp->perf, opp, GFP_KERNEL); | |
| 369 | + ret = xa_insert(&dom->opps_by_idx, opp->level_index, opp, | |
| 370 | + GFP_KERNEL); | |
| 371 | + if (ret) | |
| 372 | + dev_warn(dev, | |
| 373 | + "Failed to add opps_by_idx at %d - ret:%d\n", | |
| 374 | + opp->level_index, ret); | |
| 375 | + | |
| 376 | + ret = xa_insert(&dom->opps_by_lvl, opp->perf, opp, GFP_KERNEL); | |
| 377 | + if (ret) | |
| 378 | + dev_warn(dev, | |
| 379 | + "Failed to add opps_by_lvl at %d - ret:%d\n", | |
| 380 | + opp->perf, ret); | |
| 381 | + | |
| 369 | 382 | hash_add(dom->opps_by_freq, &opp->hash, opp->indicative_freq); |
| 370 | 383 | } |
| 371 | 384 | } |
| @@ -382,7 +395,7 @@ iter_perf_levels_process_response(const struct scmi_protocol_handle *ph, · 10 unmodified lines | ||
| 382 | 395 | if (PROTOCOL_REV_MAJOR(p->version) <= 0x3) |
| 383 | 396 | process_response_opp(opp, st->loop_idx, response); |
| 384 | 397 | else |
| 385 | − process_response_opp_v4(p->perf_dom, opp, st->loop_idx, | |
| 398 | + process_response_opp_v4(ph->dev, p->perf_dom, opp, st->loop_idx, | |
| 386 | 399 | response); |
| 387 | 400 | p->perf_dom->opp_count++; |
| 388 | 401 | |
| @@ -1111,7 +1111,6 @@ static int scmi_raw_mode_setup(struct scmi_raw_mode_info *raw, · 1110 unmodified lines | ||
| 1111 | 1111 | int i; |
| 1112 | 1112 | |
| 1113 | 1113 | for (i = 0; i < num_chans; i++) { |
| 1114 | − void *xret; | |
| 1115 | 1114 | struct scmi_raw_queue *q; |
| 1116 | 1115 | |
| 1117 | 1116 | q = scmi_raw_queue_init(raw); |
| @@ -1120,13 +1119,12 @@ static int scmi_raw_mode_setup(struct scmi_raw_mode_info *raw, · 2 unmodified lines | ||
| 1120 | 1119 | goto err_xa; |
| 1121 | 1120 | } |
| 1122 | 1121 | |
| 1123 | − xret = xa_store(&raw->chans_q, channels[i], q, | |
| 1122 | + ret = xa_insert(&raw->chans_q, channels[i], q, | |
| 1124 | 1123 | GFP_KERNEL); |
| 1125 | − if (xa_err(xret)) { | |
| 1124 | + if (ret) { | |
| 1126 | 1125 | dev_err(dev, |
| 1127 | 1126 | "Fail to allocate Raw queue 0x%02X\n", |
| 1128 | 1127 | channels[i]); |
| 1129 | − ret = xa_err(xret); | |
| 1130 | 1128 | goto err_xa; |
| 1131 | 1129 | } |
| 1132 | 1130 | } |
| @@ -1322,6 +1320,12 @@ void scmi_raw_message_report(void *r, struct scmi_xfer *xfer, · 189 unmodified lines | ||
| 1322 | 1320 | dev = raw->handle->dev; |
| 1323 | 1321 | q = scmi_raw_queue_select(raw, idx, |
| 1324 | 1322 | SCMI_XFER_IS_CHAN_SET(xfer) ? chan_id : 0); |
| 1323 | + if (!q) { | |
| 1324 | + dev_warn(dev, | |
| 1325 | + "RAW[%d] - NO queue for chan 0x%X. Dropping report.\n", | |
| 1326 | + idx, chan_id); | |
| 1327 | + return; | |
| 1328 | + } | |
| 1325 | 1329 | |
| 1326 | 1330 | /* |
| 1327 | 1331 | * Grab the msg_q_lock upfront to avoid a possible race between |
| @@ -10,7 +10,7 @@ · 9 unmodified lines | ||
| 10 | 10 | #include <linux/processor.h> |
| 11 | 11 | #include <linux/types.h> |
| 12 | 12 | |
| 13 | −#include <asm-generic/bug.h> | |
| 13 | +#include <linux/bug.h> | |
| 14 | 14 | |
| 15 | 15 | #include "common.h" |
| 16 | 16 | |
| @@ -122,3 +122,9 @@ bool shmem_poll_done(struct scmi_shared_mem __iomem *shmem, · 105 unmodified lines | ||
| 122 | 122 | (SCMI_SHMEM_CHAN_STAT_CHANNEL_ERROR | |
| 123 | 123 | SCMI_SHMEM_CHAN_STAT_CHANNEL_FREE); |
| 124 | 124 | } |
| 125 | + | |
| 126 | +bool shmem_channel_free(struct scmi_shared_mem __iomem *shmem) | |
| 127 | +{ | |
| 128 | + return (ioread32(&shmem->channel_status) & | |
| 129 | + SCMI_SHMEM_CHAN_STAT_CHANNEL_FREE); | |
| 130 | +} | |
| @@ -29,6 +29,7 @@ · 28 unmodified lines | ||
| 29 | 29 | #include <linux/init.h> |
| 30 | 30 | #include <linux/kernel.h> |
| 31 | 31 | #include <linux/mm.h> |
| 32 | +#include <linux/pci.h> | |
| 32 | 33 | #include <linux/platform_data/simplefb.h> |
| 33 | 34 | #include <linux/platform_device.h> |
| 34 | 35 | #include <linux/screen_info.h> |
| @@ -69,24 +70,70 @@ void sysfb_disable(void) · 34 unmodified lines | ||
| 69 | 70 | } |
| 70 | 71 | EXPORT_SYMBOL_GPL(sysfb_disable); |
| 71 | 72 | |
| 73 | +#if defined(CONFIG_PCI) | |
| 74 | +static __init bool sysfb_pci_dev_is_enabled(struct pci_dev *pdev) | |
| 75 | +{ | |
| 76 | + /* | |
| 77 | + * TODO: Try to integrate this code into the PCI subsystem | |
| 78 | + */ | |
| 79 | + int ret; | |
| 80 | + u16 command; | |
| 81 | + | |
| 82 | + ret = pci_read_config_word(pdev, PCI_COMMAND, &command); | |
| 83 | + if (ret != PCIBIOS_SUCCESSFUL) | |
| 84 | + return false; | |
| 85 | + if (!(command & PCI_COMMAND_MEMORY)) | |
| 86 | + return false; | |
| 87 | + return true; | |
| 88 | +} | |
| 89 | +#else | |
| 90 | +static __init bool sysfb_pci_dev_is_enabled(struct pci_dev *pdev) | |
| 91 | +{ | |
| 92 | + return false; | |
| 93 | +} | |
| 94 | +#endif | |
| 95 | + | |
| 96 | +static __init struct device *sysfb_parent_dev(const struct screen_info *si) | |
| 97 | +{ | |
| 98 | + struct pci_dev *pdev; | |
| 99 | + | |
| 100 | + pdev = screen_info_pci_dev(si); | |
| 101 | + if (IS_ERR(pdev)) { | |
| 102 | + return ERR_CAST(pdev); | |
| 103 | + } else if (pdev) { | |
| 104 | + if (!sysfb_pci_dev_is_enabled(pdev)) | |
| 105 | + return ERR_PTR(-ENODEV); | |
| 106 | + return &pdev->dev; | |
| 107 | + } | |
| 108 | + | |
| 109 | + return NULL; | |
| 110 | +} | |
| 111 | + | |
| 72 | 112 | static __init int sysfb_init(void) |
| 73 | 113 | { |
| 74 | 114 | struct screen_info *si = &screen_info; |
| 115 | + struct device *parent; | |
| 75 | 116 | struct simplefb_platform_data mode; |
| 76 | 117 | const char *name; |
| 77 | 118 | bool compatible; |
| 78 | 119 | int ret = 0; |
| 79 | 120 | |
| 121 | + screen_info_apply_fixups(); | |
| 122 | + | |
| 80 | 123 | mutex_lock(&disable_lock); |
| 81 | 124 | if (disabled) |
| 82 | 125 | goto unlock_mutex; |
| 83 | 126 | |
| 84 | 127 | sysfb_apply_efi_quirks(); |
| 85 | 128 | |
| 129 | + parent = sysfb_parent_dev(si); | |
| 130 | + if (IS_ERR(parent)) | |
| 131 | + goto unlock_mutex; | |
| 132 | + | |
| 86 | 133 | /* try to create a simple-framebuffer device */ |
| 87 | 134 | compatible = sysfb_parse_mode(si, &mode); |
| 88 | 135 | if (compatible) { |
| 89 | − pd = sysfb_create_simplefb(si, &mode); | |
| 136 | + pd = sysfb_create_simplefb(si, &mode, parent); | |
| 90 | 137 | if (!IS_ERR(pd)) |
| 91 | 138 | goto unlock_mutex; |
| 92 | 139 | } |
| @@ -109,6 +156,8 @@ static __init int sysfb_init(void) · 16 unmodified lines | ||
| 109 | 156 | goto unlock_mutex; |
| 110 | 157 | } |
| 111 | 158 | |
| 159 | + pd->dev.parent = parent; | |
| 160 | + | |
| 112 | 161 | sysfb_set_efifb_fwnode(pd); |
| 113 | 162 | |
| 114 | 163 | ret = platform_device_add_data(pd, si, sizeof(*si)); |
| @@ -128,4 +177,4 @@ unlock_mutex: · 13 unmodified lines | ||
| 128 | 177 | } |
| 129 | 178 | |
| 130 | 179 | /* must execute after PCI subsystem for EFI quirks */ |
| 131 | −subsys_initcall_sync(sysfb_init); | |
| 180 | +device_initcall(sysfb_init); | |
| @@ -91,7 +91,8 @@ __init bool sysfb_parse_mode(const struct screen_info *si, · 90 unmodified lines | ||
| 91 | 91 | } |
| 92 | 92 | |
| 93 | 93 | __init struct platform_device *sysfb_create_simplefb(const struct screen_info *si, |
| 94 | − const struct simplefb_platform_data *mode) | |
| 94 | + const struct simplefb_platform_data *mode, | |
| 95 | + struct device *parent) | |
| 95 | 96 | { |
| 96 | 97 | struct platform_device *pd; |
| 97 | 98 | struct resource res; |
| @@ -143,6 +144,8 @@ __init struct platform_device *sysfb_create_simplefb(const struct screen_info *s · 45 unmodified lines | ||
| 143 | 144 | if (!pd) |
| 144 | 145 | return ERR_PTR(-ENOMEM); |
| 145 | 146 | |
| 147 | + pd->dev.parent = parent; | |
| 148 | + | |
| 146 | 149 | sysfb_set_efifb_fwnode(pd); |
| 147 | 150 | |
| 148 | 151 | ret = platform_device_add_resources(pd, &res, 1); |
| @@ -330,20 +330,27 @@ static int sprd_eic_irq_set_type(struct irq_data *data, unsigned int flow_type) · 329 unmodified lines | ||
| 330 | 330 | switch (flow_type) { |
| 331 | 331 | case IRQ_TYPE_LEVEL_HIGH: |
| 332 | 332 | sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 1); |
| 333 | + sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IC, 1); | |
| 333 | 334 | break; |
| 334 | 335 | case IRQ_TYPE_LEVEL_LOW: |
| 335 | 336 | sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 0); |
| 337 | + sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IC, 1); | |
| 336 | 338 | break; |
| 337 | 339 | case IRQ_TYPE_EDGE_RISING: |
| 338 | 340 | case IRQ_TYPE_EDGE_FALLING: |
| 339 | 341 | case IRQ_TYPE_EDGE_BOTH: |
| 340 | 342 | state = sprd_eic_get(chip, offset); |
| 341 | − if (state) | |
| 343 | + if (state) { | |
| 342 | 344 | sprd_eic_update(chip, offset, |
| 343 | 345 | SPRD_EIC_DBNC_IEV, 0); |
| 344 | − else | |
| 346 | + sprd_eic_update(chip, offset, | |
| 347 | + SPRD_EIC_DBNC_IC, 1); | |
| 348 | + } else { | |
| 345 | 349 | sprd_eic_update(chip, offset, |
| 346 | 350 | SPRD_EIC_DBNC_IEV, 1); |
| 351 | + sprd_eic_update(chip, offset, | |
| 352 | + SPRD_EIC_DBNC_IC, 1); | |
| 353 | + } | |
| 347 | 354 | break; |
| 348 | 355 | default: |
| 349 | 356 | return -ENOTSUPP; |
| @@ -355,20 +362,27 @@ static int sprd_eic_irq_set_type(struct irq_data *data, unsigned int flow_type) · 5 unmodified lines | ||
| 355 | 362 | switch (flow_type) { |
| 356 | 363 | case IRQ_TYPE_LEVEL_HIGH: |
| 357 | 364 | sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 0); |
| 365 | + sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTCLR, 1); | |
| 358 | 366 | break; |
| 359 | 367 | case IRQ_TYPE_LEVEL_LOW: |
| 360 | 368 | sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 1); |
| 369 | + sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTCLR, 1); | |
| 361 | 370 | break; |
| 362 | 371 | case IRQ_TYPE_EDGE_RISING: |
| 363 | 372 | case IRQ_TYPE_EDGE_FALLING: |
| 364 | 373 | case IRQ_TYPE_EDGE_BOTH: |
| 365 | 374 | state = sprd_eic_get(chip, offset); |
| 366 | − if (state) | |
| 375 | + if (state) { | |
| 367 | 376 | sprd_eic_update(chip, offset, |
| 368 | 377 | SPRD_EIC_LATCH_INTPOL, 0); |
| 369 | − else | |
| 378 | + sprd_eic_update(chip, offset, | |
| 379 | + SPRD_EIC_LATCH_INTCLR, 1); | |
| 380 | + } else { | |
| 370 | 381 | sprd_eic_update(chip, offset, |
| 371 | 382 | SPRD_EIC_LATCH_INTPOL, 1); |
| 383 | + sprd_eic_update(chip, offset, | |
| 384 | + SPRD_EIC_LATCH_INTCLR, 1); | |
| 385 | + } | |
| 372 | 386 | break; |
| 373 | 387 | default: |
| 374 | 388 | return -ENOTSUPP; |
| @@ -382,29 +396,34 @@ static int sprd_eic_irq_set_type(struct irq_data *data, unsigned int flow_type) · 7 unmodified lines | ||
| 382 | 396 | sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0); |
| 383 | 397 | sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0); |
| 384 | 398 | sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 1); |
| 399 | + sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1); | |
| 385 | 400 | irq_set_handler_locked(data, handle_edge_irq); |
| 386 | 401 | break; |
| 387 | 402 | case IRQ_TYPE_EDGE_FALLING: |
| 388 | 403 | sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0); |
| 389 | 404 | sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0); |
| 390 | 405 | sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 0); |
| 406 | + sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1); | |
| 391 | 407 | irq_set_handler_locked(data, handle_edge_irq); |
| 392 | 408 | break; |
| 393 | 409 | case IRQ_TYPE_EDGE_BOTH: |
| 394 | 410 | sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0); |
| 395 | 411 | sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 1); |
| 412 | + sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1); | |
| 396 | 413 | irq_set_handler_locked(data, handle_edge_irq); |
| 397 | 414 | break; |
| 398 | 415 | case IRQ_TYPE_LEVEL_HIGH: |
| 399 | 416 | sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0); |
| 400 | 417 | sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 1); |
| 401 | 418 | sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 1); |
| 419 | + sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1); | |
| 402 | 420 | irq_set_handler_locked(data, handle_level_irq); |
| 403 | 421 | break; |
| 404 | 422 | case IRQ_TYPE_LEVEL_LOW: |
| 405 | 423 | sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0); |
| 406 | 424 | sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 1); |
| 407 | 425 | sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 0); |
| 426 | + sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1); | |
| 408 | 427 | irq_set_handler_locked(data, handle_level_irq); |
| 409 | 428 | break; |
| 410 | 429 | default: |
| @@ -417,29 +436,34 @@ static int sprd_eic_irq_set_type(struct irq_data *data, unsigned int flow_type) · 6 unmodified lines | ||
| 417 | 436 | sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0); |
| 418 | 437 | sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0); |
| 419 | 438 | sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 1); |
| 439 | + sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1); | |
| 420 | 440 | irq_set_handler_locked(data, handle_edge_irq); |
| 421 | 441 | break; |
| 422 | 442 | case IRQ_TYPE_EDGE_FALLING: |
| 423 | 443 | sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0); |
| 424 | 444 | sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0); |
| 425 | 445 | sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 0); |
| 446 | + sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1); | |
| 426 | 447 | irq_set_handler_locked(data, handle_edge_irq); |
| 427 | 448 | break; |
| 428 | 449 | case IRQ_TYPE_EDGE_BOTH: |
| 429 | 450 | sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0); |
| 430 | 451 | sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 1); |
| 452 | + sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1); | |
| 431 | 453 | irq_set_handler_locked(data, handle_edge_irq); |
| 432 | 454 | break; |
| 433 | 455 | case IRQ_TYPE_LEVEL_HIGH: |
| 434 | 456 | sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0); |
| 435 | 457 | sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 1); |
| 436 | 458 | sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 1); |
| 459 | + sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1); | |
| 437 | 460 | irq_set_handler_locked(data, handle_level_irq); |
| 438 | 461 | break; |
| 439 | 462 | case IRQ_TYPE_LEVEL_LOW: |
| 440 | 463 | sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0); |
| 441 | 464 | sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 1); |
| 442 | 465 | sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 0); |
| 466 | + sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1); | |
| 443 | 467 | irq_set_handler_locked(data, handle_level_irq); |
| 444 | 468 | break; |
| 445 | 469 | default: |
| @@ -1651,6 +1651,20 @@ static const struct dmi_system_id gpiolib_acpi_quirks[] __initconst = { · 1650 unmodified lines | ||
| 1651 | 1651 | .ignore_interrupt = "INT33FC:00@3", |
| 1652 | 1652 | }, |
| 1653 | 1653 | }, |
| 1654 | + { | |
| 1655 | + /* | |
| 1656 | + * Spurious wakeups from TP_ATTN# pin | |
| 1657 | + * Found in BIOS 0.35 | |
| 1658 | + * https://gitlab.freedesktop.org/drm/amd/-/issues/3073 | |
| 1659 | + */ | |
| 1660 | + .matches = { | |
| 1661 | + DMI_MATCH(DMI_SYS_VENDOR, "GPD"), | |
| 1662 | + DMI_MATCH(DMI_PRODUCT_NAME, "G1619-04"), | |
| 1663 | + }, | |
| 1664 | + .driver_data = &(struct acpi_gpiolib_dmi_quirk) { | |
| 1665 | + .ignore_wake = "PNP0C50:00@8", | |
| 1666 | + }, | |
| 1667 | + }, | |
| 1654 | 1668 | {} /* Terminating entry */ |
| 1655 | 1669 | }; |
| 1656 | 1670 | |
| @@ -19,8 +19,7 @@ menuconfig DRM · 18 unmodified lines | ||
| 19 | 19 | # gallium uses SYS_kcmp for os_same_file_description() to de-duplicate |
| 20 | 20 | # device and dmabuf fd. Let's make sure that is available for our userspace. |
| 21 | 21 | select KCMP |
| 22 | − select VIDEO_CMDLINE | |
| 23 | − select VIDEO_NOMODESET | |
| 22 | + select VIDEO | |
| 24 | 23 | help |
| 25 | 24 | Kernel-level support for the Direct Rendering Infrastructure (DRI) |
| 26 | 25 | introduced in XFree86 4.0. If you say Y here, you need to select |
| @@ -42,7 +41,7 @@ config DRM_MIPI_DSI · 15 unmodified lines | ||
| 42 | 41 | config DRM_DEBUG_MM |
| 43 | 42 | bool "Insert extra checks and debug info into the DRM range managers" |
| 44 | 43 | default n |
| 45 | − depends on DRM=y | |
| 44 | + depends on DRM | |
| 46 | 45 | depends on STACKTRACE_SUPPORT |
| 47 | 46 | select STACKDEPOT |
| 48 | 47 | help |
| @@ -289,19 +288,7 @@ config DRM_VGEM · 240 unmodified lines | ||
| 289 | 288 | as used by Mesa's software renderer for enhanced performance. |
| 290 | 289 | If M is selected the module will be called vgem. |
| 291 | 290 | |
| 292 | −config DRM_VKMS | |
| 293 | − tristate "Virtual KMS (EXPERIMENTAL)" | |
| 294 | − depends on DRM && MMU | |
| 295 | − select DRM_KMS_HELPER | |
| 296 | − select DRM_GEM_SHMEM_HELPER | |
| 297 | − select CRC32 | |
| 298 | − default n | |
| 299 | − help | |
| 300 | − Virtual Kernel Mode-Setting (VKMS) is used for testing or for | |
| 301 | − running GPU in a headless machines. Choose this option to get | |
| 302 | − a VKMS. | |
| 303 | − | |
| 304 | − If M is selected the module will be called vkms. | |
| 291 | +source "drivers/gpu/drm/vkms/Kconfig" | |
| 305 | 292 | |
| 306 | 293 | source "drivers/gpu/drm/exynos/Kconfig" |
| 307 | 294 | |
| @@ -80,7 +80,7 @@ amdgpu-y += amdgpu_device.o amdgpu_doorbell_mgr.o amdgpu_kms.o \ · 79 unmodified lines | ||
| 80 | 80 | amdgpu_umc.o smu_v11_0_i2c.o amdgpu_fru_eeprom.o amdgpu_rap.o \ |
| 81 | 81 | amdgpu_fw_attestation.o amdgpu_securedisplay.o \ |
| 82 | 82 | amdgpu_eeprom.o amdgpu_mca.o amdgpu_psp_ta.o amdgpu_lsdma.o \ |
| 83 | − amdgpu_ring_mux.o amdgpu_xcp.o amdgpu_seq64.o | |
| 83 | + amdgpu_ring_mux.o amdgpu_xcp.o amdgpu_seq64.o amdgpu_aca.o | |
| 84 | 84 | |
| 85 | 85 | amdgpu-$(CONFIG_PROC_FS) += amdgpu_fdinfo.o |
| 86 | 86 | |
| @@ -107,6 +107,7 @@ · 106 unmodified lines | ||
| 107 | 107 | #include "amdgpu_smuio.h" |
| 108 | 108 | #include "amdgpu_fdinfo.h" |
| 109 | 109 | #include "amdgpu_mca.h" |
| 110 | +#include "amdgpu_aca.h" | |
| 110 | 111 | #include "amdgpu_ras.h" |
| 111 | 112 | #include "amdgpu_xcp.h" |
| 112 | 113 | #include "amdgpu_seq64.h" |
| @@ -114,14 +115,12 @@ · 1 unmodified line | ||
| 114 | 115 | |
| 115 | 116 | #define MAX_GPU_INSTANCE 64 |
| 116 | 117 | |
| 117 | −struct amdgpu_gpu_instance | |
| 118 | −{ | |
| 118 | +struct amdgpu_gpu_instance { | |
| 119 | 119 | struct amdgpu_device *adev; |
| 120 | 120 | int mgpu_fan_enabled; |
| 121 | 121 | }; |
| 122 | 122 | |
| 123 | −struct amdgpu_mgpu_info | |
| 124 | −{ | |
| 123 | +struct amdgpu_mgpu_info { | |
| 125 | 124 | struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; |
| 126 | 125 | struct mutex mutex; |
| 127 | 126 | uint32_t num_gpu; |
| @@ -140,8 +139,7 @@ enum amdgpu_ss { · 12 unmodified lines | ||
| 140 | 139 | AMDGPU_SS_DRV_UNLOAD |
| 141 | 140 | }; |
| 142 | 141 | |
| 143 | −struct amdgpu_watchdog_timer | |
| 144 | −{ | |
| 142 | +struct amdgpu_watchdog_timer { | |
| 145 | 143 | bool timeout_fatal_disable; |
| 146 | 144 | uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */ |
| 147 | 145 | }; |
| @@ -1045,6 +1043,9 @@ struct amdgpu_device { · 897 unmodified lines | ||
| 1045 | 1043 | /* MCA */ |
| 1046 | 1044 | struct amdgpu_mca mca; |
| 1047 | 1045 | |
| 1046 | + /* ACA */ | |
| 1047 | + struct amdgpu_aca aca; | |
| 1048 | + | |
| 1048 | 1049 | struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; |
| 1049 | 1050 | uint32_t harvest_ip_mask; |
| 1050 | 1051 | int num_ip_blocks; |
| @@ -1078,6 +1079,8 @@ struct amdgpu_device { · 27 unmodified lines | ||
| 1078 | 1079 | bool in_s3; |
| 1079 | 1080 | bool in_s4; |
| 1080 | 1081 | bool in_s0ix; |
| 1082 | + /* indicate amdgpu suspension status */ | |
| 1083 | + bool suspend_complete; | |
| 1081 | 1084 | |
| 1082 | 1085 | enum pp_mp1_state mp1_state; |
| 1083 | 1086 | struct amdgpu_doorbell_index doorbell_index; |
| @@ -1329,6 +1332,7 @@ int emu_soc_asic_init(struct amdgpu_device *adev); · 245 unmodified lines | ||
| 1329 | 1332 | #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ |
| 1330 | 1333 | WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) |
| 1331 | 1334 | |
| 1335 | +#define AMDGPU_GET_REG_FIELD(x, h, l) (((x) & GENMASK_ULL(h, l)) >> (l)) | |
| 1332 | 1336 | /* |
| 1333 | 1337 | * BIOS helpers. |
| 1334 | 1338 | */ |
| @@ -0,0 +1,879 @@ | ||
| 1 | +/* | |
| 2 | + * Copyright 2023 Advanced Micro Devices, Inc. | |
| 3 | + * | |
| 4 | + * Permission is hereby granted, free of charge, to any person obtaining a | |
| 5 | + * copy of this software and associated documentation files (the "Software"), | |
| 6 | + * to deal in the Software without restriction, including without limitation | |
| 7 | + * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 8 | + * and/or sell copies of the Software, and to permit persons to whom the | |
| 9 | + * Software is furnished to do so, subject to the following conditions: | |
| 10 | + * | |
| 11 | + * The above copyright notice and this permission notice shall be included in | |
| 12 | + * all copies or substantial portions of the Software. | |
| 13 | + * | |
| 14 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
| 15 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 16 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 17 | + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 18 | + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 19 | + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 20 | + * OTHER DEALINGS IN THE SOFTWARE. | |
| 21 | + * | |
| 22 | + */ | |
| 23 | + | |
| 24 | +#include <linux/list.h> | |
| 25 | +#include "amdgpu.h" | |
| 26 | +#include "amdgpu_aca.h" | |
| 27 | +#include "amdgpu_ras.h" | |
| 28 | + | |
| 29 | +#define ACA_BANK_HWID(type, hwid, mcatype) [ACA_HWIP_TYPE_##type] = {hwid, mcatype} | |
| 30 | + | |
| 31 | +typedef int bank_handler_t(struct aca_handle *handle, struct aca_bank *bank, enum aca_error_type type, void *data); | |
| 32 | + | |
| 33 | +struct aca_banks { | |
| 34 | + int nr_banks; | |
| 35 | + struct list_head list; | |
| 36 | +}; | |
| 37 | + | |
| 38 | +struct aca_hwip { | |
| 39 | + int hwid; | |
| 40 | + int mcatype; | |
| 41 | +}; | |
| 42 | + | |
| 43 | +static struct aca_hwip aca_hwid_mcatypes[ACA_HWIP_TYPE_COUNT] = { | |
| 44 | + ACA_BANK_HWID(SMU, 0x01, 0x01), | |
| 45 | + ACA_BANK_HWID(PCS_XGMI, 0x50, 0x00), | |
| 46 | + ACA_BANK_HWID(UMC, 0x96, 0x00), | |
| 47 | +}; | |
| 48 | + | |
| 49 | +static void aca_banks_init(struct aca_banks *banks) | |
| 50 | +{ | |
| 51 | + if (!banks) | |
| 52 | + return; | |
| 53 | + | |
| 54 | + memset(banks, 0, sizeof(*banks)); | |
| 55 | + INIT_LIST_HEAD(&banks->list); | |
| 56 | +} | |
| 57 | + | |
| 58 | +static int aca_banks_add_bank(struct aca_banks *banks, struct aca_bank *bank) | |
| 59 | +{ | |
| 60 | + struct aca_bank_node *node; | |
| 61 | + | |
| 62 | + if (!bank) | |
| 63 | + return -EINVAL; | |
| 64 | + | |
| 65 | + node = kvzalloc(sizeof(*node), GFP_KERNEL); | |
| 66 | + if (!node) | |
| 67 | + return -ENOMEM; | |
| 68 | + | |
| 69 | + memcpy(&node->bank, bank, sizeof(*bank)); | |
| 70 | + | |
| 71 | + INIT_LIST_HEAD(&node->node); | |
| 72 | + list_add_tail(&node->node, &banks->list); | |
| 73 | + | |
| 74 | + banks->nr_banks++; | |
| 75 | + | |
| 76 | + return 0; | |
| 77 | +} | |
| 78 | + | |
| 79 | +static void aca_banks_release(struct aca_banks *banks) | |
| 80 | +{ | |
| 81 | + struct aca_bank_node *node, *tmp; | |
| 82 | + | |
| 83 | + list_for_each_entry_safe(node, tmp, &banks->list, node) { | |
| 84 | + list_del(&node->node); | |
| 85 | + kvfree(node); | |
| 86 | + } | |
| 87 | +} | |
| 88 | + | |
| 89 | +static int aca_smu_get_valid_aca_count(struct amdgpu_device *adev, enum aca_error_type type, u32 *count) | |
| 90 | +{ | |
| 91 | + struct amdgpu_aca *aca = &adev->aca; | |
| 92 | + const struct aca_smu_funcs *smu_funcs = aca->smu_funcs; | |
| 93 | + | |
| 94 | + if (!count) | |
| 95 | + return -EINVAL; | |
| 96 | + | |
| 97 | + if (!smu_funcs || !smu_funcs->get_valid_aca_count) | |
| 98 | + return -EOPNOTSUPP; | |
| 99 | + | |
| 100 | + return smu_funcs->get_valid_aca_count(adev, type, count); | |
| 101 | +} | |
| 102 | + | |
| 103 | +static struct aca_regs_dump { | |
| 104 | + const char *name; | |
| 105 | + int reg_idx; | |
| 106 | +} aca_regs[] = { | |
| 107 | + {"CONTROL", ACA_REG_IDX_CTL}, | |
| 108 | + {"STATUS", ACA_REG_IDX_STATUS}, | |
| 109 | + {"ADDR", ACA_REG_IDX_ADDR}, | |
| 110 | + {"MISC", ACA_REG_IDX_MISC0}, | |
| 111 | + {"CONFIG", ACA_REG_IDX_CONFG}, | |
| 112 | + {"IPID", ACA_REG_IDX_IPID}, | |
| 113 | + {"SYND", ACA_REG_IDX_SYND}, | |
| 114 | + {"DESTAT", ACA_REG_IDX_DESTAT}, | |
| 115 | + {"DEADDR", ACA_REG_IDX_DEADDR}, | |
| 116 | + {"CONTROL_MASK", ACA_REG_IDX_CTL_MASK}, | |
| 117 | +}; | |
| 118 | + | |
| 119 | +static void aca_smu_bank_dump(struct amdgpu_device *adev, int idx, int total, struct aca_bank *bank) | |
| 120 | +{ | |
| 121 | + int i; | |
| 122 | + | |
| 123 | + dev_info(adev->dev, HW_ERR "Accelerator Check Architecture events logged\n"); | |
| 124 | + /* plus 1 for output format, e.g: ACA[08/08]: xxxx */ | |
| 125 | + for (i = 0; i < ARRAY_SIZE(aca_regs); i++) | |
| 126 | + dev_info(adev->dev, HW_ERR "ACA[%02d/%02d].%s=0x%016llx\n", | |
| 127 | + idx + 1, total, aca_regs[i].name, bank->regs[aca_regs[i].reg_idx]); | |
| 128 | +} | |
| 129 | + | |
| 130 | +static int aca_smu_get_valid_aca_banks(struct amdgpu_device *adev, enum aca_error_type type, | |
| 131 | + int start, int count, | |
| 132 | + struct aca_banks *banks) | |
| 133 | +{ | |
| 134 | + struct amdgpu_aca *aca = &adev->aca; | |
| 135 | + const struct aca_smu_funcs *smu_funcs = aca->smu_funcs; | |
| 136 | + struct aca_bank bank; | |
| 137 | + int i, max_count, ret; | |
| 138 | + | |
| 139 | + if (!count) | |
| 140 | + return 0; | |
| 141 | + | |
| 142 | + if (!smu_funcs || !smu_funcs->get_valid_aca_bank) | |
| 143 | + return -EOPNOTSUPP; | |
| 144 | + | |
| 145 | + switch (type) { | |
| 146 | + case ACA_ERROR_TYPE_UE: | |
| 147 | + max_count = smu_funcs->max_ue_bank_count; | |
| 148 | + break; | |
| 149 | + case ACA_ERROR_TYPE_CE: | |
| 150 | + max_count = smu_funcs->max_ce_bank_count; | |
| 151 | + break; | |
| 152 | + case ACA_ERROR_TYPE_DEFERRED: | |
| 153 | + default: | |
| 154 | + return -EINVAL; | |
| 155 | + } | |
| 156 | + | |
| 157 | + if (start + count >= max_count) | |
| 158 | + return -EINVAL; | |
| 159 | + | |
| 160 | + count = min_t(int, count, max_count); | |
| 161 | + for (i = 0; i < count; i++) { | |
| 162 | + memset(&bank, 0, sizeof(bank)); | |
| 163 | + ret = smu_funcs->get_valid_aca_bank(adev, type, start + i, &bank); | |
| 164 | + if (ret) | |
| 165 | + return ret; | |
| 166 | + | |
| 167 | + aca_smu_bank_dump(adev, i, count, &bank); | |
| 168 | + | |
| 169 | + ret = aca_banks_add_bank(banks, &bank); | |
| 170 | + if (ret) | |
| 171 | + return ret; | |
| 172 | + } | |
| 173 | + | |
| 174 | + return 0; | |
| 175 | +} | |
| 176 | + | |
| 177 | +static bool aca_bank_hwip_is_matched(struct aca_bank *bank, enum aca_hwip_type type) | |
| 178 | +{ | |
| 179 | + | |
| 180 | + struct aca_hwip *hwip; | |
| 181 | + int hwid, mcatype; | |
| 182 | + u64 ipid; | |
| 183 | + | |
| 184 | + if (!bank || type == ACA_HWIP_TYPE_UNKNOW) | |
| 185 | + return false; | |
| 186 | + | |
| 187 | + hwip = &aca_hwid_mcatypes[type]; | |
| 188 | + if (!hwip->hwid) | |
| 189 | + return false; | |
| 190 | + | |
| 191 | + ipid = bank->regs[ACA_REG_IDX_IPID]; | |
| 192 | + hwid = ACA_REG__IPID__HARDWAREID(ipid); | |
| 193 | + mcatype = ACA_REG__IPID__MCATYPE(ipid); | |
| 194 | + | |
| 195 | + return hwip->hwid == hwid && hwip->mcatype == mcatype; | |
| 196 | +} | |
| 197 | + | |
| 198 | +static bool aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, enum aca_error_type type) | |
| 199 | +{ | |
| 200 | + const struct aca_bank_ops *bank_ops = handle->bank_ops; | |
| 201 | + | |
| 202 | + if (!aca_bank_hwip_is_matched(bank, handle->hwip)) | |
| 203 | + return false; | |
| 204 | + | |
| 205 | + if (!bank_ops->aca_bank_is_valid) | |
| 206 | + return true; | |
| 207 | + | |
| 208 | + return bank_ops->aca_bank_is_valid(handle, bank, type, handle->data); | |
| 209 | +} | |
| 210 | + | |
| 211 | +static struct aca_bank_error *new_bank_error(struct aca_error *aerr, struct aca_bank_info *info) | |
| 212 | +{ | |
| 213 | + struct aca_bank_error *bank_error; | |
| 214 | + | |
| 215 | + bank_error = kvzalloc(sizeof(*bank_error), GFP_KERNEL); | |
| 216 | + if (!bank_error) | |
| 217 | + return NULL; | |
| 218 | + | |
| 219 | + INIT_LIST_HEAD(&bank_error->node); | |
| 220 | + memcpy(&bank_error->info, info, sizeof(*info)); | |
| 221 | + | |
| 222 | + mutex_lock(&aerr->lock); | |
| 223 | + list_add_tail(&bank_error->node, &aerr->list); | |
| 224 | + mutex_unlock(&aerr->lock); | |
| 225 | + | |
| 226 | + return bank_error; | |
| 227 | +} | |
| 228 | + | |
| 229 | +static struct aca_bank_error *find_bank_error(struct aca_error *aerr, struct aca_bank_info *info) | |
| 230 | +{ | |
| 231 | + struct aca_bank_error *bank_error = NULL; | |
| 232 | + struct aca_bank_info *tmp_info; | |
| 233 | + bool found = false; | |
| 234 | + | |
| 235 | + mutex_lock(&aerr->lock); | |
| 236 | + list_for_each_entry(bank_error, &aerr->list, node) { | |
| 237 | + tmp_info = &bank_error->info; | |
| 238 | + if (tmp_info->socket_id == info->socket_id && | |
| 239 | + tmp_info->die_id == info->die_id) { | |
| 240 | + found = true; | |
| 241 | + goto out_unlock; | |
| 242 | + } | |
| 243 | + } | |
| 244 | + | |
| 245 | +out_unlock: | |
| 246 | + mutex_unlock(&aerr->lock); | |
| 247 | + | |
| 248 | + return found ? bank_error : NULL; | |
| 249 | +} | |
| 250 | + | |
| 251 | +static void aca_bank_error_remove(struct aca_error *aerr, struct aca_bank_error *bank_error) | |
| 252 | +{ | |
| 253 | + if (!aerr || !bank_error) | |
| 254 | + return; | |
| 255 | + | |
| 256 | + list_del(&bank_error->node); | |
| 257 | + aerr->nr_errors--; | |
| 258 | + | |
| 259 | + kvfree(bank_error); | |
| 260 | +} | |
| 261 | + | |
| 262 | +static struct aca_bank_error *get_bank_error(struct aca_error *aerr, struct aca_bank_info *info) | |
| 263 | +{ | |
| 264 | + struct aca_bank_error *bank_error; | |
| 265 | + | |
| 266 | + if (!aerr || !info) | |
| 267 | + return NULL; | |
| 268 | + | |
| 269 | + bank_error = find_bank_error(aerr, info); | |
| 270 | + if (bank_error) | |
| 271 | + return bank_error; | |
| 272 | + | |
| 273 | + return new_bank_error(aerr, info); | |
| 274 | +} | |
| 275 | + | |
| 276 | +static int aca_log_errors(struct aca_handle *handle, enum aca_error_type type, | |
| 277 | + struct aca_bank_report *report) | |
| 278 | +{ | |
| 279 | + struct aca_error_cache *error_cache = &handle->error_cache; | |
| 280 | + struct aca_bank_error *bank_error; | |
| 281 | + struct aca_error *aerr; | |
| 282 | + | |
| 283 | + if (!handle || !report) | |
| 284 | + return -EINVAL; | |
| 285 | + | |
| 286 | + if (!report->count[type]) | |
| 287 | + return 0; | |
| 288 | + | |
| 289 | + aerr = &error_cache->errors[type]; | |
| 290 | + bank_error = get_bank_error(aerr, &report->info); | |
| 291 | + if (!bank_error) | |
| 292 | + return -ENOMEM; | |
| 293 | + | |
| 294 | + bank_error->count[type] += report->count[type]; | |
| 295 | + | |
| 296 | + return 0; | |
| 297 | +} | |
| 298 | + | |
| 299 | +static int aca_generate_bank_report(struct aca_handle *handle, struct aca_bank *bank, | |
| 300 | + enum aca_error_type type, struct aca_bank_report *report) | |
| 301 | +{ | |
| 302 | + const struct aca_bank_ops *bank_ops = handle->bank_ops; | |
| 303 | + | |
| 304 | + if (!bank || !report) | |
| 305 | + return -EINVAL; | |
| 306 | + | |
| 307 | + if (!bank_ops->aca_bank_generate_report) | |
| 308 | + return -EOPNOTSUPP; | |
| 309 | + | |
| 310 | + memset(report, 0, sizeof(*report)); | |
| 311 | + return bank_ops->aca_bank_generate_report(handle, bank, type, | |
| 312 | + report, handle->data); | |
| 313 | +} | |
| 314 | + | |
| 315 | +static int handler_aca_log_bank_error(struct aca_handle *handle, struct aca_bank *bank, | |
| 316 | + enum aca_error_type type, void *data) | |
| 317 | +{ | |
| 318 | + struct aca_bank_report report; | |
| 319 | + int ret; | |
| 320 | + | |
| 321 | + ret = aca_generate_bank_report(handle, bank, type, &report); | |
| 322 | + if (ret) | |
| 323 | + return ret; | |
| 324 | + | |
| 325 | + if (!report.count[type]) | |
| 326 | + return 0; | |
| 327 | + | |
| 328 | + ret = aca_log_errors(handle, type, &report); | |
| 329 | + if (ret) | |
| 330 | + return ret; | |
| 331 | + | |
| 332 | + return 0; | |
| 333 | +} | |
| 334 | + | |
| 335 | +static int aca_dispatch_bank(struct aca_handle_manager *mgr, struct aca_bank *bank, | |
| 336 | + enum aca_error_type type, bank_handler_t handler, void *data) | |
| 337 | +{ | |
| 338 | + struct aca_handle *handle; | |
| 339 | + int ret; | |
| 340 | + | |
| 341 | + if (list_empty(&mgr->list)) | |
| 342 | + return 0; | |
| 343 | + | |
| 344 | + list_for_each_entry(handle, &mgr->list, node) { | |
| 345 | + if (!aca_bank_is_valid(handle, bank, type)) | |
| 346 | + continue; | |
| 347 | + | |
| 348 | + ret = handler(handle, bank, type, data); | |
| 349 | + if (ret) | |
| 350 | + return ret; | |
| 351 | + } | |
| 352 | + | |
| 353 | + return 0; | |
| 354 | +} | |
| 355 | + | |
| 356 | +static int aca_dispatch_banks(struct aca_handle_manager *mgr, struct aca_banks *banks, | |
| 357 | + enum aca_error_type type, bank_handler_t handler, void *data) | |
| 358 | +{ | |
| 359 | + struct aca_bank_node *node; | |
| 360 | + struct aca_bank *bank; | |
| 361 | + int ret; | |
| 362 | + | |
| 363 | + if (!mgr || !banks) | |
| 364 | + return -EINVAL; | |
| 365 | + | |
| 366 | + /* pre check to avoid unnecessary operations */ | |
| 367 | + if (list_empty(&mgr->list) || list_empty(&banks->list)) | |
| 368 | + return 0; | |
| 369 | + | |
| 370 | + list_for_each_entry(node, &banks->list, node) { | |
| 371 | + bank = &node->bank; | |
| 372 | + | |
| 373 | + ret = aca_dispatch_bank(mgr, bank, type, handler, data); | |
| 374 | + if (ret) | |
| 375 | + return ret; | |
| 376 | + } | |
| 377 | + | |
| 378 | + return 0; | |
| 379 | +} | |
| 380 | + | |
| 381 | +static int aca_banks_update(struct amdgpu_device *adev, enum aca_error_type type, | |
| 382 | + bank_handler_t handler, void *data) | |
| 383 | +{ | |
| 384 | + struct amdgpu_aca *aca = &adev->aca; | |
| 385 | + struct aca_banks banks; | |
| 386 | + u32 count = 0; | |
| 387 | + int ret; | |
| 388 | + | |
| 389 | + if (list_empty(&aca->mgr.list)) | |
| 390 | + return 0; | |
| 391 | + | |
| 392 | + /* NOTE: pmfw is only support UE and CE */ | |
| 393 | + if (type == ACA_ERROR_TYPE_DEFERRED) | |
| 394 | + type = ACA_ERROR_TYPE_CE; | |
| 395 | + | |
| 396 | + ret = aca_smu_get_valid_aca_count(adev, type, &count); | |
| 397 | + if (ret) | |
| 398 | + return ret; | |
| 399 | + | |
| 400 | + if (!count) | |
| 401 | + return 0; | |
| 402 | + | |
| 403 | + aca_banks_init(&banks); | |
| 404 | + | |
| 405 | + ret = aca_smu_get_valid_aca_banks(adev, type, 0, count, &banks); | |
| 406 | + if (ret) | |
| 407 | + goto err_release_banks; | |
| 408 | + | |
| 409 | + if (list_empty(&banks.list)) { | |
| 410 | + ret = 0; | |
| 411 | + goto err_release_banks; | |
| 412 | + } | |
| 413 | + | |
| 414 | + ret = aca_dispatch_banks(&aca->mgr, &banks, type, | |
| 415 | + handler, data); | |
| 416 | + if (ret) | |
| 417 | + goto err_release_banks; | |
| 418 | + | |
| 419 | +err_release_banks: | |
| 420 | + aca_banks_release(&banks); | |
| 421 | + | |
| 422 | + return ret; | |
| 423 | +} | |
| 424 | + | |
| 425 | +static int aca_log_aca_error_data(struct aca_bank_error *bank_error, enum aca_error_type type, struct ras_err_data *err_data) | |
| 426 | +{ | |
| 427 | + struct aca_bank_info *info; | |
| 428 | + struct amdgpu_smuio_mcm_config_info mcm_info; | |
| 429 | + u64 count; | |
| 430 | + | |
| 431 | + if (type >= ACA_ERROR_TYPE_COUNT) | |
| 432 | + return -EINVAL; | |
| 433 | + | |
| 434 | + count = bank_error->count[type]; | |
| 435 | + if (!count) | |
| 436 | + return 0; | |
| 437 | + | |
| 438 | + info = &bank_error->info; | |
| 439 | + mcm_info.die_id = info->die_id; | |
| 440 | + mcm_info.socket_id = info->socket_id; | |
| 441 | + | |
| 442 | + switch (type) { | |
| 443 | + case ACA_ERROR_TYPE_UE: | |
| 444 | + amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, NULL, count); | |
| 445 | + break; | |
| 446 | + case ACA_ERROR_TYPE_CE: | |
| 447 | + amdgpu_ras_error_statistic_ce_count(err_data, &mcm_info, NULL, count); | |
| 448 | + break; | |
| 449 | + case ACA_ERROR_TYPE_DEFERRED: | |
| 450 | + default: | |
| 451 | + break; | |
| 452 | + } | |
| 453 | + | |
| 454 | + return 0; | |
| 455 | +} | |
| 456 | + | |
| 457 | +static int aca_log_aca_error(struct aca_handle *handle, enum aca_error_type type, struct ras_err_data *err_data) | |
| 458 | +{ | |
| 459 | + struct aca_error_cache *error_cache = &handle->error_cache; | |
| 460 | + struct aca_error *aerr = &error_cache->errors[type]; | |
| 461 | + struct aca_bank_error *bank_error, *tmp; | |
| 462 | + | |
| 463 | + mutex_lock(&aerr->lock); | |
| 464 | + | |
| 465 | + if (list_empty(&aerr->list)) | |
| 466 | + goto out_unlock; | |
| 467 | + | |
| 468 | + list_for_each_entry_safe(bank_error, tmp, &aerr->list, node) { | |
| 469 | + aca_log_aca_error_data(bank_error, type, err_data); | |
| 470 | + aca_bank_error_remove(aerr, bank_error); | |
| 471 | + } | |
| 472 | + | |
| 473 | +out_unlock: | |
| 474 | + mutex_unlock(&aerr->lock); | |
| 475 | + | |
| 476 | + return 0; | |
| 477 | +} | |
| 478 | + | |
| 479 | +static int __aca_get_error_data(struct amdgpu_device *adev, struct aca_handle *handle, enum aca_error_type type, | |
| 480 | + struct ras_err_data *err_data) | |
| 481 | +{ | |
| 482 | + int ret; | |
| 483 | + | |
| 484 | + /* udpate aca bank to aca source error_cache first */ | |
| 485 | + ret = aca_banks_update(adev, type, handler_aca_log_bank_error, NULL); | |
| 486 | + if (ret) | |
| 487 | + return ret; | |
| 488 | + | |
| 489 | + return aca_log_aca_error(handle, type, err_data); | |
| 490 | +} | |
| 491 | + | |
| 492 | +static bool aca_handle_is_valid(struct aca_handle *handle) | |
| 493 | +{ | |
| 494 | + if (!handle->mask || !list_empty(&handle->node)) | |
| 495 | + return false; | |
| 496 | + | |
| 497 | + return true; | |
| 498 | +} | |
| 499 | + | |
| 500 | +int amdgpu_aca_get_error_data(struct amdgpu_device *adev, struct aca_handle *handle, | |
| 501 | + enum aca_error_type type, void *data) | |
| 502 | +{ | |
| 503 | + struct ras_err_data *err_data = (struct ras_err_data *)data; | |
| 504 | + | |
| 505 | + if (!handle || !err_data) | |
| 506 | + return -EINVAL; | |
| 507 | + | |
| 508 | + if (aca_handle_is_valid(handle)) | |
| 509 | + return -EOPNOTSUPP; | |
| 510 | + | |
| 511 | + if (!(BIT(type) & handle->mask)) | |
| 512 | + return 0; | |
| 513 | + | |
| 514 | + return __aca_get_error_data(adev, handle, type, err_data); | |
| 515 | +} | |
| 516 | + | |
| 517 | +static void aca_error_init(struct aca_error *aerr, enum aca_error_type type) | |
| 518 | +{ | |
| 519 | + mutex_init(&aerr->lock); | |
| 520 | + INIT_LIST_HEAD(&aerr->list); | |
| 521 | + aerr->type = type; | |
| 522 | + aerr->nr_errors = 0; | |
| 523 | +} | |
| 524 | + | |
| 525 | +static void aca_init_error_cache(struct aca_handle *handle) | |
| 526 | +{ | |
| 527 | + struct aca_error_cache *error_cache = &handle->error_cache; | |
| 528 | + int type; | |
| 529 | + | |
| 530 | + for (type = ACA_ERROR_TYPE_UE; type < ACA_ERROR_TYPE_COUNT; type++) | |
| 531 | + aca_error_init(&error_cache->errors[type], type); | |
| 532 | +} | |
| 533 | + | |
| 534 | +static void aca_error_fini(struct aca_error *aerr) | |
| 535 | +{ | |
| 536 | + struct aca_bank_error *bank_error, *tmp; | |
| 537 | + | |
| 538 | + mutex_lock(&aerr->lock); | |
| 539 | + list_for_each_entry_safe(bank_error, tmp, &aerr->list, node) | |
| 540 | + aca_bank_error_remove(aerr, bank_error); | |
| 541 | + | |
| 542 | + mutex_destroy(&aerr->lock); | |
| 543 | +} | |
| 544 | + | |
| 545 | +static void aca_fini_error_cache(struct aca_handle *handle) | |
| 546 | +{ | |
| 547 | + struct aca_error_cache *error_cache = &handle->error_cache; | |
| 548 | + int type; | |
| 549 | + | |
| 550 | + for (type = ACA_ERROR_TYPE_UE; type < ACA_ERROR_TYPE_COUNT; type++) | |
| 551 | + aca_error_fini(&error_cache->errors[type]); | |
| 552 | +} | |
| 553 | + | |
| 554 | +static int add_aca_handle(struct amdgpu_device *adev, struct aca_handle_manager *mgr, struct aca_handle *handle, | |
| 555 | + const char *name, const struct aca_info *ras_info, void *data) | |
| 556 | +{ | |
| 557 | + memset(handle, 0, sizeof(*handle)); | |
| 558 | + | |
| 559 | + handle->adev = adev; | |
| 560 | + handle->mgr = mgr; | |
| 561 | + handle->name = name; | |
| 562 | + handle->hwip = ras_info->hwip; | |
| 563 | + handle->mask = ras_info->mask; | |
| 564 | + handle->bank_ops = ras_info->bank_ops; | |
| 565 | + handle->data = data; | |
| 566 | + aca_init_error_cache(handle); | |
| 567 | + | |
| 568 | + INIT_LIST_HEAD(&handle->node); | |
| 569 | + list_add_tail(&handle->node, &mgr->list); | |
| 570 | + mgr->nr_handles++; | |
| 571 | + | |
| 572 | + return 0; | |
| 573 | +} | |
| 574 | + | |
| 575 | +static ssize_t aca_sysfs_read(struct device *dev, | |
| 576 | + struct device_attribute *attr, char *buf) | |
| 577 | +{ | |
| 578 | + struct aca_handle *handle = container_of(attr, struct aca_handle, aca_attr); | |
| 579 | + | |
| 580 | + /* NOTE: the aca cache will be auto cleared once read, | |
| 581 | + * So the driver should unify the query entry point, forward request to ras query interface directly */ | |
| 582 | + return amdgpu_ras_aca_sysfs_read(dev, attr, handle, buf, handle->data); | |
| 583 | +} | |
| 584 | + | |
| 585 | +static int add_aca_sysfs(struct amdgpu_device *adev, struct aca_handle *handle) | |
| 586 | +{ | |
| 587 | + struct device_attribute *aca_attr = &handle->aca_attr; | |
| 588 | + | |
| 589 | + snprintf(handle->attr_name, sizeof(handle->attr_name) - 1, "aca_%s", handle->name); | |
| 590 | + aca_attr->show = aca_sysfs_read; | |
| 591 | + aca_attr->attr.name = handle->attr_name; | |
| 592 | + aca_attr->attr.mode = S_IRUGO; | |
| 593 | + sysfs_attr_init(&aca_attr->attr); | |
| 594 | + | |
| 595 | + return sysfs_add_file_to_group(&adev->dev->kobj, | |
| 596 | + &aca_attr->attr, | |
| 597 | + "ras"); | |
| 598 | +} | |
| 599 | + | |
| 600 | +int amdgpu_aca_add_handle(struct amdgpu_device *adev, struct aca_handle *handle, | |
| 601 | + const char *name, const struct aca_info *ras_info, void *data) | |
| 602 | +{ | |
| 603 | + struct amdgpu_aca *aca = &adev->aca; | |
| 604 | + int ret; | |
| 605 | + | |
| 606 | + if (!amdgpu_aca_is_enabled(adev)) | |
| 607 | + return 0; | |
| 608 | + | |
| 609 | + ret = add_aca_handle(adev, &aca->mgr, handle, name, ras_info, data); | |
| 610 | + if (ret) | |
| 611 | + return ret; | |
| 612 | + | |
| 613 | + return add_aca_sysfs(adev, handle); | |
| 614 | +} | |
| 615 | + | |
| 616 | +static void remove_aca_handle(struct aca_handle *handle) | |
| 617 | +{ | |
| 618 | + struct aca_handle_manager *mgr = handle->mgr; | |
| 619 | + | |
| 620 | + aca_fini_error_cache(handle); | |
| 621 | + list_del(&handle->node); | |
| 622 | + mgr->nr_handles--; | |
| 623 | +} | |
| 624 | + | |
| 625 | +static void remove_aca_sysfs(struct aca_handle *handle) | |
| 626 | +{ | |
| 627 | + struct amdgpu_device *adev = handle->adev; | |
| 628 | + struct device_attribute *aca_attr = &handle->aca_attr; | |
| 629 | + | |
| 630 | + if (adev->dev->kobj.sd) | |
| 631 | + sysfs_remove_file_from_group(&adev->dev->kobj, | |
| 632 | + &aca_attr->attr, | |
| 633 | + "ras"); | |
| 634 | +} | |
| 635 | + | |
| 636 | +void amdgpu_aca_remove_handle(struct aca_handle *handle) | |
| 637 | +{ | |
| 638 | + if (!handle || list_empty(&handle->node)) | |
| 639 | + return; | |
| 640 | + | |
| 641 | + remove_aca_sysfs(handle); | |
| 642 | + remove_aca_handle(handle); | |
| 643 | +} | |
| 644 | + | |
| 645 | +static int aca_manager_init(struct aca_handle_manager *mgr) | |
| 646 | +{ | |
| 647 | + INIT_LIST_HEAD(&mgr->list); | |
| 648 | + mgr->nr_handles = 0; | |
| 649 | + | |
| 650 | + return 0; | |
| 651 | +} | |
| 652 | + | |
| 653 | +static void aca_manager_fini(struct aca_handle_manager *mgr) | |
| 654 | +{ | |
| 655 | + struct aca_handle *handle, *tmp; | |
| 656 | + | |
| 657 | + list_for_each_entry_safe(handle, tmp, &mgr->list, node) | |
| 658 | + amdgpu_aca_remove_handle(handle); | |
| 659 | +} | |
| 660 | + | |
| 661 | +bool amdgpu_aca_is_enabled(struct amdgpu_device *adev) | |
| 662 | +{ | |
| 663 | + return adev->aca.is_enabled; | |
| 664 | +} | |
| 665 | + | |
| 666 | +int amdgpu_aca_init(struct amdgpu_device *adev) | |
| 667 | +{ | |
| 668 | + struct amdgpu_aca *aca = &adev->aca; | |
| 669 | + int ret; | |
| 670 | + | |
| 671 | + ret = aca_manager_init(&aca->mgr); | |
| 672 | + if (ret) | |
| 673 | + return ret; | |
| 674 | + | |
| 675 | + return 0; | |
| 676 | +} | |
| 677 | + | |
| 678 | +void amdgpu_aca_fini(struct amdgpu_device *adev) | |
| 679 | +{ | |
| 680 | + struct amdgpu_aca *aca = &adev->aca; | |
| 681 | + | |
| 682 | + aca_manager_fini(&aca->mgr); | |
| 683 | +} | |
| 684 | + | |
| 685 | +int amdgpu_aca_reset(struct amdgpu_device *adev) | |
| 686 | +{ | |
| 687 | + amdgpu_aca_fini(adev); | |
| 688 | + | |
| 689 | + return amdgpu_aca_init(adev); | |
| 690 | +} | |
| 691 | + | |
| 692 | +void amdgpu_aca_set_smu_funcs(struct amdgpu_device *adev, const struct aca_smu_funcs *smu_funcs) | |
| 693 | +{ | |
| 694 | + struct amdgpu_aca *aca = &adev->aca; | |
| 695 | + | |
| 696 | + WARN_ON(aca->smu_funcs); | |
| 697 | + aca->smu_funcs = smu_funcs; | |
| 698 | +} | |
| 699 | + | |
| 700 | +int aca_bank_info_decode(struct aca_bank *bank, struct aca_bank_info *info) | |
| 701 | +{ | |
| 702 | + u64 ipid; | |
| 703 | + u32 instidhi, instidlo; | |
| 704 | + | |
| 705 | + if (!bank || !info) | |
| 706 | + return -EINVAL; | |
| 707 | + | |
| 708 | + ipid = bank->regs[ACA_REG_IDX_IPID]; | |
| 709 | + info->hwid = ACA_REG__IPID__HARDWAREID(ipid); | |
| 710 | + info->mcatype = ACA_REG__IPID__MCATYPE(ipid); | |
| 711 | + /* | |
| 712 | + * Unfied DieID Format: SAASS. A:AID, S:Socket. | |
| 713 | + * Unfied DieID[4:4] = InstanceId[0:0] | |
| 714 | + * Unfied DieID[0:3] = InstanceIdHi[0:3] | |
| 715 | + */ | |
| 716 | + instidhi = ACA_REG__IPID__INSTANCEIDHI(ipid); | |
| 717 | + instidlo = ACA_REG__IPID__INSTANCEIDLO(ipid); | |
| 718 | + info->die_id = ((instidhi >> 2) & 0x03); | |
| 719 | + info->socket_id = ((instidlo & 0x1) << 2) | (instidhi & 0x03); | |
| 720 | + | |
| 721 | + return 0; | |
| 722 | +} | |
| 723 | + | |
| 724 | +static int aca_bank_get_error_code(struct amdgpu_device *adev, struct aca_bank *bank) | |
| 725 | +{ | |
| 726 | + int error_code; | |
| 727 | + | |
| 728 | + switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { | |
| 729 | + case IP_VERSION(13, 0, 6): | |
| 730 | + if (!(adev->flags & AMD_IS_APU) && adev->pm.fw_version >= 0x00555600) { | |
| 731 | + error_code = ACA_REG__SYND__ERRORINFORMATION(bank->regs[ACA_REG_IDX_SYND]); | |
| 732 | + return error_code & 0xff; | |
| 733 | + } | |
| 734 | + break; | |
| 735 | + default: | |
| 736 | + break; | |
| 737 | + } | |
| 738 | + | |
| 739 | + /* NOTE: the true error code is encoded in status.errorcode[0:7] */ | |
| 740 | + error_code = ACA_REG__STATUS__ERRORCODE(bank->regs[ACA_REG_IDX_STATUS]); | |
| 741 | + | |
| 742 | + return error_code & 0xff; | |
| 743 | +} | |
| 744 | + | |
| 745 | +int aca_bank_check_error_codes(struct amdgpu_device *adev, struct aca_bank *bank, int *err_codes, int size) | |
| 746 | +{ | |
| 747 | + int i, error_code; | |
| 748 | + | |
| 749 | + if (!bank || !err_codes) | |
| 750 | + return -EINVAL; | |
| 751 | + | |
| 752 | + error_code = aca_bank_get_error_code(adev, bank); | |
| 753 | + for (i = 0; i < size; i++) { | |
| 754 | + if (err_codes[i] == error_code) | |
| 755 | + return 0; | |
| 756 | + } | |
| 757 | + | |
| 758 | + return -EINVAL; | |
| 759 | +} | |
| 760 | + | |
| 761 | +int amdgpu_aca_smu_set_debug_mode(struct amdgpu_device *adev, bool en) | |
| 762 | +{ | |
| 763 | + struct amdgpu_aca *aca = &adev->aca; | |
| 764 | + const struct aca_smu_funcs *smu_funcs = aca->smu_funcs; | |
| 765 | + | |
| 766 | + if (!smu_funcs || !smu_funcs->set_debug_mode) | |
| 767 | + return -EOPNOTSUPP; | |
| 768 | + | |
| 769 | + return smu_funcs->set_debug_mode(adev, en); | |
| 770 | +} | |
| 771 | + | |
| 772 | +#if defined(CONFIG_DEBUG_FS) | |
| 773 | +static int amdgpu_aca_smu_debug_mode_set(void *data, u64 val) | |
| 774 | +{ | |
| 775 | + struct amdgpu_device *adev = (struct amdgpu_device *)data; | |
| 776 | + int ret; | |
| 777 | + | |
| 778 | + ret = amdgpu_ras_set_aca_debug_mode(adev, val ? true : false); | |
| 779 | + if (ret) | |
| 780 | + return ret; | |
| 781 | + | |
| 782 | + dev_info(adev->dev, "amdgpu set smu aca debug mode %s success\n", val ? "on" : "off"); | |
| 783 | + | |
| 784 | + return 0; | |
| 785 | +} | |
| 786 | + | |
| 787 | +static void aca_dump_entry(struct seq_file *m, struct aca_bank *bank, enum aca_error_type type, int idx) | |
| 788 | +{ | |
| 789 | + struct aca_bank_info info; | |
| 790 | + int i, ret; | |
| 791 | + | |
| 792 | + ret = aca_bank_info_decode(bank, &info); | |
| 793 | + if (ret) | |
| 794 | + return; | |
| 795 | + | |
| 796 | + seq_printf(m, "aca entry[%d].type: %s\n", idx, type == ACA_ERROR_TYPE_UE ? "UE" : "CE"); | |
| 797 | + seq_printf(m, "aca entry[%d].info: socketid:%d aid:%d hwid:0x%03x mcatype:0x%04x\n", | |
| 798 | + idx, info.socket_id, info.die_id, info.hwid, info.mcatype); | |
| 799 | + | |
| 800 | + for (i = 0; i < ARRAY_SIZE(aca_regs); i++) | |
| 801 | + seq_printf(m, "aca entry[%d].regs[%d]: 0x%016llx\n", idx, aca_regs[i].reg_idx, bank->regs[aca_regs[i].reg_idx]); | |
| 802 | +} | |
| 803 | + | |
| 804 | +struct aca_dump_context { | |
| 805 | + struct seq_file *m; | |
| 806 | + int idx; | |
| 807 | +}; | |
| 808 | + | |
| 809 | +static int handler_aca_bank_dump(struct aca_handle *handle, struct aca_bank *bank, | |
| 810 | + enum aca_error_type type, void *data) | |
| 811 | +{ | |
| 812 | + struct aca_dump_context *ctx = (struct aca_dump_context *)data; | |
| 813 | + | |
| 814 | + aca_dump_entry(ctx->m, bank, type, ctx->idx++); | |
| 815 | + | |
| 816 | + return handler_aca_log_bank_error(handle, bank, type, NULL); | |
| 817 | +} | |
| 818 | + | |
| 819 | +static int aca_dump_show(struct seq_file *m, enum aca_error_type type) | |
| 820 | +{ | |
| 821 | + struct amdgpu_device *adev = (struct amdgpu_device *)m->private; | |
| 822 | + struct aca_dump_context context = { | |
| 823 | + .m = m, | |
| 824 | + .idx = 0, | |
| 825 | + }; | |
| 826 | + | |
| 827 | + return aca_banks_update(adev, type, handler_aca_bank_dump, (void *)&context); | |
| 828 | +} | |
| 829 | + | |
| 830 | +static int aca_dump_ce_show(struct seq_file *m, void *unused) | |
| 831 | +{ | |
| 832 | + return aca_dump_show(m, ACA_ERROR_TYPE_CE); | |
| 833 | +} | |
| 834 | + | |
| 835 | +static int aca_dump_ce_open(struct inode *inode, struct file *file) | |
| 836 | +{ | |
| 837 | + return single_open(file, aca_dump_ce_show, inode->i_private); | |
| 838 | +} | |
| 839 | + | |
| 840 | +static const struct file_operations aca_ce_dump_debug_fops = { | |
| 841 | + .owner = THIS_MODULE, | |
| 842 | + .open = aca_dump_ce_open, | |
| 843 | + .read = seq_read, | |
| 844 | + .llseek = seq_lseek, | |
| 845 | + .release = single_release, | |
| 846 | +}; | |
| 847 | + | |
| 848 | +static int aca_dump_ue_show(struct seq_file *m, void *unused) | |
| 849 | +{ | |
| 850 | + return aca_dump_show(m, ACA_ERROR_TYPE_UE); | |
| 851 | +} | |
| 852 | + | |
| 853 | +static int aca_dump_ue_open(struct inode *inode, struct file *file) | |
| 854 | +{ | |
| 855 | + return single_open(file, aca_dump_ue_show, inode->i_private); | |
| 856 | +} | |
| 857 | + | |
| 858 | +static const struct file_operations aca_ue_dump_debug_fops = { | |
| 859 | + .owner = THIS_MODULE, | |
| 860 | + .open = aca_dump_ue_open, | |
| 861 | + .read = seq_read, | |
| 862 | + .llseek = seq_lseek, | |
| 863 | + .release = single_release, | |
| 864 | +}; | |
| 865 | + | |
| 866 | +DEFINE_DEBUGFS_ATTRIBUTE(aca_debug_mode_fops, NULL, amdgpu_aca_smu_debug_mode_set, "%llu\n"); | |
| 867 | +#endif | |
| 868 | + | |
| 869 | +void amdgpu_aca_smu_debugfs_init(struct amdgpu_device *adev, struct dentry *root) | |
| 870 | +{ | |
| 871 | +#if defined(CONFIG_DEBUG_FS) | |
| 872 | + if (!root || adev->ip_versions[MP1_HWIP][0] != IP_VERSION(13, 0, 6)) | |
| 873 | + return; | |
| 874 | + | |
| 875 | + debugfs_create_file("aca_debug_mode", 0200, root, adev, &aca_debug_mode_fops); | |
| 876 | + debugfs_create_file("aca_ue_dump", 0400, root, adev, &aca_ue_dump_debug_fops); | |
| 877 | + debugfs_create_file("aca_ce_dump", 0400, root, adev, &aca_ce_dump_debug_fops); | |
| 878 | +#endif | |
| 879 | +} | |
| @@ -0,0 +1,202 @@ | ||
| 1 | +/* | |
| 2 | + * Copyright 2023 Advanced Micro Devices, Inc. | |
| 3 | + * | |
| 4 | + * Permission is hereby granted, free of charge, to any person obtaining a | |
| 5 | + * copy of this software and associated documentation files (the "Software"), | |
| 6 | + * to deal in the Software without restriction, including without limitation | |
| 7 | + * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 8 | + * and/or sell copies of the Software, and to permit persons to whom the | |
| 9 | + * Software is furnished to do so, subject to the following conditions: | |
| 10 | + * | |
| 11 | + * The above copyright notice and this permission notice shall be included in | |
| 12 | + * all copies or substantial portions of the Software. | |
| 13 | + * | |
| 14 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
| 15 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 16 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 17 | + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 18 | + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 19 | + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 20 | + * OTHER DEALINGS IN THE SOFTWARE. | |
| 21 | + * | |
| 22 | + */ | |
| 23 | + | |
| 24 | +#ifndef __AMDGPU_ACA_H__ | |
| 25 | +#define __AMDGPU_ACA_H__ | |
| 26 | + | |
| 27 | +#include <linux/list.h> | |
| 28 | + | |
| 29 | +#define ACA_MAX_REGS_COUNT (16) | |
| 30 | + | |
| 31 | +#define ACA_REG_FIELD(x, h, l) (((x) & GENMASK_ULL(h, l)) >> l) | |
| 32 | +#define ACA_REG__STATUS__VAL(x) ACA_REG_FIELD(x, 63, 63) | |
| 33 | +#define ACA_REG__STATUS__OVERFLOW(x) ACA_REG_FIELD(x, 62, 62) | |
| 34 | +#define ACA_REG__STATUS__UC(x) ACA_REG_FIELD(x, 61, 61) | |
| 35 | +#define ACA_REG__STATUS__EN(x) ACA_REG_FIELD(x, 60, 60) | |
| 36 | +#define ACA_REG__STATUS__MISCV(x) ACA_REG_FIELD(x, 59, 59) | |
| 37 | +#define ACA_REG__STATUS__ADDRV(x) ACA_REG_FIELD(x, 58, 58) | |
| 38 | +#define ACA_REG__STATUS__PCC(x) ACA_REG_FIELD(x, 57, 57) | |
| 39 | +#define ACA_REG__STATUS__ERRCOREIDVAL(x) ACA_REG_FIELD(x, 56, 56) | |
| 40 | +#define ACA_REG__STATUS__TCC(x) ACA_REG_FIELD(x, 55, 55) | |
| 41 | +#define ACA_REG__STATUS__SYNDV(x) ACA_REG_FIELD(x, 53, 53) | |
| 42 | +#define ACA_REG__STATUS__CECC(x) ACA_REG_FIELD(x, 46, 46) | |
| 43 | +#define ACA_REG__STATUS__UECC(x) ACA_REG_FIELD(x, 45, 45) | |
| 44 | +#define ACA_REG__STATUS__DEFERRED(x) ACA_REG_FIELD(x, 44, 44) | |
| 45 | +#define ACA_REG__STATUS__POISON(x) ACA_REG_FIELD(x, 43, 43) | |
| 46 | +#define ACA_REG__STATUS__SCRUB(x) ACA_REG_FIELD(x, 40, 40) | |
| 47 | +#define ACA_REG__STATUS__ERRCOREID(x) ACA_REG_FIELD(x, 37, 32) | |
| 48 | +#define ACA_REG__STATUS__ADDRLSB(x) ACA_REG_FIELD(x, 29, 24) | |
| 49 | +#define ACA_REG__STATUS__ERRORCODEEXT(x) ACA_REG_FIELD(x, 21, 16) | |
| 50 | +#define ACA_REG__STATUS__ERRORCODE(x) ACA_REG_FIELD(x, 15, 0) | |
| 51 | + | |
| 52 | +#define ACA_REG__IPID__MCATYPE(x) ACA_REG_FIELD(x, 63, 48) | |
| 53 | +#define ACA_REG__IPID__INSTANCEIDHI(x) ACA_REG_FIELD(x, 47, 44) | |
| 54 | +#define ACA_REG__IPID__HARDWAREID(x) ACA_REG_FIELD(x, 43, 32) | |
| 55 | +#define ACA_REG__IPID__INSTANCEIDLO(x) ACA_REG_FIELD(x, 31, 0) | |
| 56 | + | |
| 57 | +#define ACA_REG__MISC0__VALID(x) ACA_REG_FIELD(x, 63, 63) | |
| 58 | +#define ACA_REG__MISC0__OVRFLW(x) ACA_REG_FIELD(x, 48, 48) | |
| 59 | +#define ACA_REG__MISC0__ERRCNT(x) ACA_REG_FIELD(x, 43, 32) | |
| 60 | + | |
| 61 | +#define ACA_REG__SYND__ERRORINFORMATION(x) ACA_REG_FIELD(x, 17, 0) | |
| 62 | + | |
| 63 | +/* NOTE: The following codes refers to the smu header file */ | |
| 64 | +#define ACA_EXTERROR_CODE_CE 0x3a | |
| 65 | +#define ACA_EXTERROR_CODE_FAULT 0x3b | |
| 66 | + | |
| 67 | +#define ACA_ERROR_UE_MASK BIT_MASK(ACA_ERROR_TYPE_UE) | |
| 68 | +#define ACA_ERROR_CE_MASK BIT_MASK(ACA_ERROR_TYPE_CE) | |
| 69 | +#define ACA_ERROR_DEFERRED_MASK BIT_MASK(ACA_ERROR_TYPE_DEFERRED) | |
| 70 | + | |
| 71 | +enum aca_reg_idx { | |
| 72 | + ACA_REG_IDX_CTL = 0, | |
| 73 | + ACA_REG_IDX_STATUS = 1, | |
| 74 | + ACA_REG_IDX_ADDR = 2, | |
| 75 | + ACA_REG_IDX_MISC0 = 3, | |
| 76 | + ACA_REG_IDX_CONFG = 4, | |
| 77 | + ACA_REG_IDX_IPID = 5, | |
| 78 | + ACA_REG_IDX_SYND = 6, | |
| 79 | + ACA_REG_IDX_DESTAT = 8, | |
| 80 | + ACA_REG_IDX_DEADDR = 9, | |
| 81 | + ACA_REG_IDX_CTL_MASK = 10, | |
| 82 | + ACA_REG_IDX_COUNT = 16, | |
| 83 | +}; | |
| 84 | + | |
| 85 | +enum aca_hwip_type { | |
| 86 | + ACA_HWIP_TYPE_UNKNOW = -1, | |
| 87 | + ACA_HWIP_TYPE_PSP = 0, | |
| 88 | + ACA_HWIP_TYPE_UMC, | |
| 89 | + ACA_HWIP_TYPE_SMU, | |
| 90 | + ACA_HWIP_TYPE_PCS_XGMI, | |
| 91 | + ACA_HWIP_TYPE_COUNT, | |
| 92 | +}; | |
| 93 | + | |
| 94 | +enum aca_error_type { | |
| 95 | + ACA_ERROR_TYPE_INVALID = -1, | |
| 96 | + ACA_ERROR_TYPE_UE = 0, | |
| 97 | + ACA_ERROR_TYPE_CE, | |
| 98 | + ACA_ERROR_TYPE_DEFERRED, | |
| 99 | + ACA_ERROR_TYPE_COUNT | |
| 100 | +}; | |
| 101 | + | |
| 102 | +struct aca_bank { | |
| 103 | + u64 regs[ACA_MAX_REGS_COUNT]; | |
| 104 | +}; | |
| 105 | + | |
| 106 | +struct aca_bank_node { | |
| 107 | + struct aca_bank bank; | |
| 108 | + struct list_head node; | |
| 109 | +}; | |
| 110 | + | |
| 111 | +struct aca_bank_info { | |
| 112 | + int die_id; | |
| 113 | + int socket_id; | |
| 114 | + int hwid; | |
| 115 | + int mcatype; | |
| 116 | +}; | |
| 117 | + | |
| 118 | +struct aca_bank_report { | |
| 119 | + struct aca_bank_info info; | |
| 120 | + u64 count[ACA_ERROR_TYPE_COUNT]; | |
| 121 | +}; | |
| 122 | + | |
| 123 | +struct aca_bank_error { | |
| 124 | + struct list_head node; | |
| 125 | + struct aca_bank_info info; | |
| 126 | + u64 count[ACA_ERROR_TYPE_COUNT]; | |
| 127 | +}; | |
| 128 | + | |
| 129 | +struct aca_error { | |
| 130 | + struct list_head list; | |
| 131 | + struct mutex lock; | |
| 132 | + enum aca_error_type type; | |
| 133 | + int nr_errors; | |
| 134 | +}; | |
| 135 | + | |
| 136 | +struct aca_handle_manager { | |
| 137 | + struct list_head list; | |
| 138 | + int nr_handles; | |
| 139 | +}; | |
| 140 | + | |
| 141 | +struct aca_error_cache { | |
| 142 | + struct aca_error errors[ACA_ERROR_TYPE_COUNT]; | |
| 143 | +}; | |
| 144 | + | |
| 145 | +struct aca_handle { | |
| 146 | + struct list_head node; | |
| 147 | + enum aca_hwip_type hwip; | |
| 148 | + struct amdgpu_device *adev; | |
| 149 | + struct aca_handle_manager *mgr; | |
| 150 | + struct aca_error_cache error_cache; | |
| 151 | + const struct aca_bank_ops *bank_ops; | |
| 152 | + struct device_attribute aca_attr; | |
| 153 | + char attr_name[64]; | |
| 154 | + const char *name; | |
| 155 | + u32 mask; | |
| 156 | + void *data; | |
| 157 | +}; | |
| 158 | + | |
| 159 | +struct aca_bank_ops { | |
| 160 | + int (*aca_bank_generate_report)(struct aca_handle *handle, struct aca_bank *bank, enum aca_error_type type, | |
| 161 | + struct aca_bank_report *report, void *data); | |
| 162 | + bool (*aca_bank_is_valid)(struct aca_handle *handle, struct aca_bank *bank, enum aca_error_type type, | |
| 163 | + void *data); | |
| 164 | +}; | |
| 165 | + | |
| 166 | +struct aca_smu_funcs { | |
| 167 | + int max_ue_bank_count; | |
| 168 | + int max_ce_bank_count; | |
| 169 | + int (*set_debug_mode)(struct amdgpu_device *adev, bool enable); | |
| 170 | + int (*get_valid_aca_count)(struct amdgpu_device *adev, enum aca_error_type type, u32 *count); | |
| 171 | + int (*get_valid_aca_bank)(struct amdgpu_device *adev, enum aca_error_type type, int idx, struct aca_bank *bank); | |
| 172 | +}; | |
| 173 | + | |
| 174 | +struct amdgpu_aca { | |
| 175 | + struct aca_handle_manager mgr; | |
| 176 | + const struct aca_smu_funcs *smu_funcs; | |
| 177 | + bool is_enabled; | |
| 178 | +}; | |
| 179 | + | |
| 180 | +struct aca_info { | |
| 181 | + enum aca_hwip_type hwip; | |
| 182 | + const struct aca_bank_ops *bank_ops; | |
| 183 | + u32 mask; | |
| 184 | +}; | |
| 185 | + | |
| 186 | +int amdgpu_aca_init(struct amdgpu_device *adev); | |
| 187 | +void amdgpu_aca_fini(struct amdgpu_device *adev); | |
| 188 | +int amdgpu_aca_reset(struct amdgpu_device *adev); | |
| 189 | +void amdgpu_aca_set_smu_funcs(struct amdgpu_device *adev, const struct aca_smu_funcs *smu_funcs); | |
| 190 | +bool amdgpu_aca_is_enabled(struct amdgpu_device *adev); | |
| 191 | + | |
| 192 | +int aca_bank_info_decode(struct aca_bank *bank, struct aca_bank_info *info); | |
| 193 | +int aca_bank_check_error_codes(struct amdgpu_device *adev, struct aca_bank *bank, int *err_codes, int size); | |
| 194 | + | |
| 195 | +int amdgpu_aca_add_handle(struct amdgpu_device *adev, struct aca_handle *handle, | |
| 196 | + const char *name, const struct aca_info *aca_info, void *data); | |
| 197 | +void amdgpu_aca_remove_handle(struct aca_handle *handle); | |
| 198 | +int amdgpu_aca_get_error_data(struct amdgpu_device *adev, struct aca_handle *handle, | |
| 199 | + enum aca_error_type type, void *data); | |
| 200 | +int amdgpu_aca_smu_set_debug_mode(struct amdgpu_device *adev, bool en); | |
| 201 | +void amdgpu_aca_smu_debugfs_init(struct amdgpu_device *adev, struct dentry *root); | |
| 202 | +#endif | |
| @@ -141,11 +141,31 @@ static void amdgpu_amdkfd_reset_work(struct work_struct *work) · 140 unmodified lines | ||
| 141 | 141 | static const struct drm_client_funcs kfd_client_funcs = { |
| 142 | 142 | .unregister = drm_client_release, |
| 143 | 143 | }; |
| 144 | + | |
| 145 | +int amdgpu_amdkfd_drm_client_create(struct amdgpu_device *adev) | |
| 146 | +{ | |
| 147 | + int ret; | |
| 148 | + | |
| 149 | + if (!adev->kfd.init_complete) | |
| 150 | + return 0; | |
| 151 | + | |
| 152 | + ret = drm_client_init(&adev->ddev, &adev->kfd.client, "kfd", | |
| 153 | + &kfd_client_funcs); | |
| 154 | + if (ret) { | |
| 155 | + dev_err(adev->dev, "Failed to init DRM client: %d\n", | |
| 156 | + ret); | |
| 157 | + return ret; | |
| 158 | + } | |
| 159 | + | |
| 160 | + drm_client_register(&adev->kfd.client); | |
| 161 | + | |
| 162 | + return 0; | |
| 163 | +} | |
| 164 | + | |
| 144 | 165 | void amdgpu_amdkfd_device_init(struct amdgpu_device *adev) |
| 145 | 166 | { |
| 146 | 167 | int i; |
| 147 | 168 | int last_valid_bit; |
| 148 | − int ret; | |
| 149 | 169 | |
| 150 | 170 | amdgpu_amdkfd_gpuvm_init_mem_limits(); |
| 151 | 171 | |
| @@ -164,12 +184,6 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev) · 12 unmodified lines | ||
| 164 | 184 | .enable_mes = adev->enable_mes, |
| 165 | 185 | }; |
| 166 | 186 | |
| 167 | − ret = drm_client_init(&adev->ddev, &adev->kfd.client, "kfd", &kfd_client_funcs); | |
| 168 | − if (ret) { | |
| 169 | − dev_err(adev->dev, "Failed to init DRM client: %d\n", ret); | |
| 170 | − return; | |
| 171 | − } | |
| 172 | − | |
| 173 | 187 | /* this is going to have a few of the MSBs set that we need to |
| 174 | 188 | * clear |
| 175 | 189 | */ |
| @@ -208,10 +222,6 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev) · 32 unmodified lines | ||
| 208 | 222 | |
| 209 | 223 | adev->kfd.init_complete = kgd2kfd_device_init(adev->kfd.dev, |
| 210 | 224 | &gpu_resources); |
| 211 | − if (adev->kfd.init_complete) | |
| 212 | − drm_client_register(&adev->kfd.client); | |
| 213 | − else | |
| 214 | − drm_client_release(&adev->kfd.client); | |
| 215 | 225 | |
| 216 | 226 | amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size; |
| 217 | 227 | |
| @@ -732,9 +742,10 @@ void amdgpu_amdkfd_debug_mem_fence(struct amdgpu_device *adev) · 514 unmodified lines | ||
| 732 | 742 | amdgpu_device_flush_hdp(adev, NULL); |
| 733 | 743 | } |
| 734 | 744 | |
| 735 | −void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev, bool reset) | |
| 745 | +void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev, | |
| 746 | + enum amdgpu_ras_block block, bool reset) | |
| 736 | 747 | { |
| 737 | − amdgpu_umc_poison_handler(adev, reset); | |
| 748 | + amdgpu_umc_poison_handler(adev, block, reset); | |
| 738 | 749 | } |
| 739 | 750 | |
| 740 | 751 | int amdgpu_amdkfd_send_close_event_drain_irq(struct amdgpu_device *adev, |
| @@ -182,6 +182,8 @@ int amdgpu_queue_mask_bit_to_set_resource_bit(struct amdgpu_device *adev, · 181 unmodified lines | ||
| 182 | 182 | struct amdgpu_amdkfd_fence *amdgpu_amdkfd_fence_create(u64 context, |
| 183 | 183 | struct mm_struct *mm, |
| 184 | 184 | struct svm_range_bo *svm_bo); |
| 185 | + | |
| 186 | +int amdgpu_amdkfd_drm_client_create(struct amdgpu_device *adev); | |
| 185 | 187 | #if defined(CONFIG_DEBUG_FS) |
| 186 | 188 | int kfd_debugfs_kfd_mem_limits(struct seq_file *m, void *data); |
| 187 | 189 | #endif |
| @@ -191,6 +193,9 @@ struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f); · 3 unmodified lines | ||
| 191 | 193 | int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo); |
| 192 | 194 | int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni, |
| 193 | 195 | unsigned long cur_seq, struct kgd_mem *mem); |
| 196 | +int amdgpu_amdkfd_bo_validate_and_fence(struct amdgpu_bo *bo, | |
| 197 | + uint32_t domain, | |
| 198 | + struct dma_fence *fence); | |
| 194 | 199 | #else |
| 195 | 200 | static inline |
| 196 | 201 | bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm) |
| @@ -216,6 +221,13 @@ int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni, · 19 unmodified lines | ||
| 216 | 221 | { |
| 217 | 222 | return 0; |
| 218 | 223 | } |
| 224 | +static inline | |
| 225 | +int amdgpu_amdkfd_bo_validate_and_fence(struct amdgpu_bo *bo, | |
| 226 | + uint32_t domain, | |
| 227 | + struct dma_fence *fence) | |
| 228 | +{ | |
| 229 | + return 0; | |
| 230 | +} | |
| 219 | 231 | #endif |
| 220 | 232 | /* Shared API */ |
| 221 | 233 | int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size, |
| @@ -301,7 +313,7 @@ int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(struct amdgpu_device *adev, · 79 unmodified lines | ||
| 301 | 313 | struct kgd_mem *mem, void *drm_priv); |
| 302 | 314 | int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu( |
| 303 | 315 | struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv); |
| 304 | −void amdgpu_amdkfd_gpuvm_dmaunmap_mem(struct kgd_mem *mem, void *drm_priv); | |
| 316 | +int amdgpu_amdkfd_gpuvm_dmaunmap_mem(struct kgd_mem *mem, void *drm_priv); | |
| 305 | 317 | int amdgpu_amdkfd_gpuvm_sync_memory( |
| 306 | 318 | struct amdgpu_device *adev, struct kgd_mem *mem, bool intr); |
| 307 | 319 | int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_mem *mem, |
| @@ -324,7 +336,7 @@ void amdgpu_amdkfd_debug_mem_fence(struct amdgpu_device *adev); · 16 unmodified lines | ||
| 324 | 336 | int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev, |
| 325 | 337 | struct tile_config *config); |
| 326 | 338 | void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev, |
| 327 | − bool reset); | |
| 339 | + enum amdgpu_ras_block block, bool reset); | |
| 328 | 340 | bool amdgpu_amdkfd_bo_mapped_to_dev(struct amdgpu_device *adev, struct kgd_mem *mem); |
| 329 | 341 | void amdgpu_amdkfd_block_mmu_notifications(void *p); |
| 330 | 342 | int amdgpu_amdkfd_criu_resume(void *p); |
| @@ -290,7 +290,7 @@ static int suspend_resume_compute_scheduler(struct amdgpu_device *adev, bool sus · 289 unmodified lines | ||
| 290 | 290 | for (i = 0; i < adev->gfx.num_compute_rings; i++) { |
| 291 | 291 | struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; |
| 292 | 292 | |
| 293 | − if (!(ring && drm_sched_wqueue_ready(&ring->sched))) | |
| 293 | + if (!amdgpu_ring_sched_ready(ring)) | |
| 294 | 294 | continue; |
| 295 | 295 | |
| 296 | 296 | /* stop secheduler and drain ring. */ |
| @@ -426,9 +426,9 @@ validate_fail: · 425 unmodified lines | ||
| 426 | 426 | return ret; |
| 427 | 427 | } |
| 428 | 428 | |
| 429 | −static int amdgpu_amdkfd_bo_validate_and_fence(struct amdgpu_bo *bo, | |
| 430 | − uint32_t domain, | |
| 431 | − struct dma_fence *fence) | |
| 429 | +int amdgpu_amdkfd_bo_validate_and_fence(struct amdgpu_bo *bo, | |
| 430 | + uint32_t domain, | |
| 431 | + struct dma_fence *fence) | |
| 432 | 432 | { |
| 433 | 433 | int ret = amdgpu_bo_reserve(bo, false); |
| 434 | 434 | |
| @@ -464,13 +464,15 @@ static int amdgpu_amdkfd_validate_vm_bo(void *_unused, struct amdgpu_bo *bo) · 29 unmodified lines | ||
| 464 | 464 | * again. Page directories are only updated after updating page |
| 465 | 465 | * tables. |
| 466 | 466 | */ |
| 467 | −static int vm_validate_pt_pd_bos(struct amdgpu_vm *vm) | |
| 467 | +static int vm_validate_pt_pd_bos(struct amdgpu_vm *vm, | |
| 468 | + struct ww_acquire_ctx *ticket) | |
| 468 | 469 | { |
| 469 | 470 | struct amdgpu_bo *pd = vm->root.bo; |
| 470 | 471 | struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev); |
| 471 | 472 | int ret; |
| 472 | 473 | |
| 473 | − ret = amdgpu_vm_validate_pt_bos(adev, vm, amdgpu_amdkfd_validate_vm_bo, NULL); | |
| 474 | + ret = amdgpu_vm_validate(adev, vm, ticket, | |
| 475 | + amdgpu_amdkfd_validate_vm_bo, NULL); | |
| 474 | 476 | if (ret) { |
| 475 | 477 | pr_err("failed to validate PT BOs\n"); |
| 476 | 478 | return ret; |
| @@ -1310,14 +1312,15 @@ update_gpuvm_pte_failed: · 833 unmodified lines | ||
| 1310 | 1312 | return ret; |
| 1311 | 1313 | } |
| 1312 | 1314 | |
| 1313 | −static int process_validate_vms(struct amdkfd_process_info *process_info) | |
| 1315 | +static int process_validate_vms(struct amdkfd_process_info *process_info, | |
| 1316 | + struct ww_acquire_ctx *ticket) | |
| 1314 | 1317 | { |
| 1315 | 1318 | struct amdgpu_vm *peer_vm; |
| 1316 | 1319 | int ret; |
| 1317 | 1320 | |
| 1318 | 1321 | list_for_each_entry(peer_vm, &process_info->vm_list_head, |
| 1319 | 1322 | vm_list_node) { |
| 1320 | − ret = vm_validate_pt_pd_bos(peer_vm); | |
| 1323 | + ret = vm_validate_pt_pd_bos(peer_vm, ticket); | |
| 1321 | 1324 | if (ret) |
| 1322 | 1325 | return ret; |
| 1323 | 1326 | } |
| @@ -1402,7 +1405,7 @@ static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info, · 78 unmodified lines | ||
| 1402 | 1405 | ret = amdgpu_bo_reserve(vm->root.bo, true); |
| 1403 | 1406 | if (ret) |
| 1404 | 1407 | goto reserve_pd_fail; |
| 1405 | − ret = vm_validate_pt_pd_bos(vm); | |
| 1408 | + ret = vm_validate_pt_pd_bos(vm, NULL); | |
| 1406 | 1409 | if (ret) { |
| 1407 | 1410 | pr_err("validate_pt_pd_bos() failed\n"); |
| 1408 | 1411 | goto validate_pd_fail; |
| @@ -2043,7 +2046,7 @@ int amdgpu_amdkfd_gpuvm_map_memory_to_gpu( · 634 unmodified lines | ||
| 2043 | 2046 | bo->tbo.resource->mem_type == TTM_PL_SYSTEM) |
| 2044 | 2047 | is_invalid_userptr = true; |
| 2045 | 2048 | |
| 2046 | − ret = vm_validate_pt_pd_bos(avm); | |
| 2049 | + ret = vm_validate_pt_pd_bos(avm, NULL); | |
| 2047 | 2050 | if (unlikely(ret)) |
| 2048 | 2051 | goto out_unreserve; |
| 2049 | 2052 | |
| @@ -2085,21 +2088,35 @@ out: · 35 unmodified lines | ||
| 2085 | 2088 | return ret; |
| 2086 | 2089 | } |
| 2087 | 2090 | |
| 2088 | −void amdgpu_amdkfd_gpuvm_dmaunmap_mem(struct kgd_mem *mem, void *drm_priv) | |
| 2091 | +int amdgpu_amdkfd_gpuvm_dmaunmap_mem(struct kgd_mem *mem, void *drm_priv) | |
| 2089 | 2092 | { |
| 2090 | 2093 | struct kfd_mem_attachment *entry; |
| 2091 | 2094 | struct amdgpu_vm *vm; |
| 2095 | + int ret; | |
| 2092 | 2096 | |
| 2093 | 2097 | vm = drm_priv_to_vm(drm_priv); |
| 2094 | 2098 | |
| 2095 | 2099 | mutex_lock(&mem->lock); |
| 2096 | 2100 | |
| 2101 | + ret = amdgpu_bo_reserve(mem->bo, true); | |
| 2102 | + if (ret) | |
| 2103 | + goto out; | |
| 2104 | + | |
| 2097 | 2105 | list_for_each_entry(entry, &mem->attachments, list) { |
| 2098 | − if (entry->bo_va->base.vm == vm) | |
| 2099 | − kfd_mem_dmaunmap_attachment(mem, entry); | |
| 2106 | + if (entry->bo_va->base.vm != vm) | |
| 2107 | + continue; | |
| 2108 | + if (entry->bo_va->base.bo->tbo.ttm && | |
| 2109 | + !entry->bo_va->base.bo->tbo.ttm->sg) | |
| 2110 | + continue; | |
| 2111 | + | |
| 2112 | + kfd_mem_dmaunmap_attachment(mem, entry); | |
| 2100 | 2113 | } |
| 2101 | 2114 | |
| 2115 | + amdgpu_bo_unreserve(mem->bo); | |
| 2116 | +out: | |
| 2102 | 2117 | mutex_unlock(&mem->lock); |
| 2118 | + | |
| 2119 | + return ret; | |
| 2103 | 2120 | } |
| 2104 | 2121 | |
| 2105 | 2122 | int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu( |
| @@ -2122,7 +2139,7 @@ int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu( · 16 unmodified lines | ||
| 2122 | 2139 | goto unreserve_out; |
| 2123 | 2140 | } |
| 2124 | 2141 | |
| 2125 | − ret = vm_validate_pt_pd_bos(avm); | |
| 2142 | + ret = vm_validate_pt_pd_bos(avm, NULL); | |
| 2126 | 2143 | if (unlikely(ret)) |
| 2127 | 2144 | goto unreserve_out; |
| 2128 | 2145 | |
| @@ -2620,7 +2637,7 @@ static int validate_invalid_user_pages(struct amdkfd_process_info *process_info) · 491 unmodified lines | ||
| 2620 | 2637 | } |
| 2621 | 2638 | } |
| 2622 | 2639 | |
| 2623 | − ret = process_validate_vms(process_info); | |
| 2640 | + ret = process_validate_vms(process_info, NULL); | |
| 2624 | 2641 | if (ret) |
| 2625 | 2642 | goto unreserve_out; |
| 2626 | 2643 | |
| @@ -2880,11 +2897,6 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence __rcu * · 253 unmodified lines | ||
| 2880 | 2897 | |
| 2881 | 2898 | amdgpu_sync_create(&sync_obj); |
| 2882 | 2899 | |
| 2883 | − /* Validate PDs and PTs */ | |
| 2884 | − ret = process_validate_vms(process_info); | |
| 2885 | − if (ret) | |
| 2886 | − goto validate_map_fail; | |
| 2887 | − | |
| 2888 | 2900 | /* Validate BOs and map them to GPUVM (update VM page tables). */ |
| 2889 | 2901 | list_for_each_entry(mem, &process_info->kfd_bo_list, |
| 2890 | 2902 | validate_list) { |
| @@ -2935,6 +2947,13 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence __rcu * · 44 unmodified lines | ||
| 2935 | 2947 | if (failed_size) |
| 2936 | 2948 | pr_debug("0x%lx/0x%lx in system\n", failed_size, total_size); |
| 2937 | 2949 | |
| 2950 | + /* Validate PDs, PTs and evicted DMABuf imports last. Otherwise BO | |
| 2951 | + * validations above would invalidate DMABuf imports again. | |
| 2952 | + */ | |
| 2953 | + ret = process_validate_vms(process_info, &exec.ticket); | |
| 2954 | + if (ret) | |
| 2955 | + goto validate_map_fail; | |
| 2956 | + | |
| 2938 | 2957 | /* Update mappings not managed by KFD */ |
| 2939 | 2958 | list_for_each_entry(peer_vm, &process_info->vm_list_head, |
| 2940 | 2959 | vm_list_node) { |
| @@ -3006,7 +3025,7 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence __rcu * · 65 unmodified lines | ||
| 3006 | 3025 | &process_info->eviction_fence->base, |
| 3007 | 3026 | DMA_RESV_USAGE_BOOKKEEP); |
| 3008 | 3027 | } |
| 3009 | − /* Attach eviction fence to PD / PT BOs */ | |
| 3028 | + /* Attach eviction fence to PD / PT BOs and DMABuf imports */ | |
| 3010 | 3029 | list_for_each_entry(peer_vm, &process_info->vm_list_head, |
| 3011 | 3030 | vm_list_node) { |
| 3012 | 3031 | struct amdgpu_bo *bo = peer_vm->root.bo; |
| @@ -1018,7 +1018,8 @@ int amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev, · 1017 unmodified lines | ||
| 1018 | 1018 | if (clock_type == COMPUTE_ENGINE_PLL_PARAM) { |
| 1019 | 1019 | args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock); |
| 1020 | 1020 | |
| 1021 | − amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); | |
| 1021 | + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, | |
| 1022 | + sizeof(args)); | |
| 1022 | 1023 | |
| 1023 | 1024 | dividers->post_div = args.v3.ucPostDiv; |
| 1024 | 1025 | dividers->enable_post_div = (args.v3.ucCntlFlag & |
| @@ -1038,7 +1039,8 @@ int amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev, · 13 unmodified lines | ||
| 1038 | 1039 | if (strobe_mode) |
| 1039 | 1040 | args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN; |
| 1040 | 1041 | |
| 1041 | − amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); | |
| 1042 | + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, | |
| 1043 | + sizeof(args)); | |
| 1042 | 1044 | |
| 1043 | 1045 | dividers->post_div = args.v5.ucPostDiv; |
| 1044 | 1046 | dividers->enable_post_div = (args.v5.ucCntlFlag & |
| @@ -1056,7 +1058,8 @@ int amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev, · 11 unmodified lines | ||
| 1056 | 1058 | /* fusion */ |
| 1057 | 1059 | args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */ |
| 1058 | 1060 | |
| 1059 | − amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); | |
| 1061 | + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, | |
| 1062 | + sizeof(args)); | |
| 1060 | 1063 | |
| 1061 | 1064 | dividers->post_divider = dividers->post_div = args.v4.ucPostDiv; |
| 1062 | 1065 | dividers->real_clock = le32_to_cpu(args.v4.ulClock); |
| @@ -1067,7 +1070,8 @@ int amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev, · 4 unmodified lines | ||
| 1067 | 1070 | args.v6_in.ulClock.ulComputeClockFlag = clock_type; |
| 1068 | 1071 | args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */ |
| 1069 | 1072 | |
| 1070 | − amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); | |
| 1073 | + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, | |
| 1074 | + sizeof(args)); | |
| 1071 | 1075 | |
| 1072 | 1076 | dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv); |
| 1073 | 1077 | dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac); |
| @@ -1109,7 +1113,8 @@ int amdgpu_atombios_get_memory_pll_dividers(struct amdgpu_device *adev, · 35 unmodified lines | ||
| 1109 | 1113 | if (strobe_mode) |
| 1110 | 1114 | args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN; |
| 1111 | 1115 | |
| 1112 | − amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); | |
| 1116 | + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, | |
| 1117 | + sizeof(args)); | |
| 1113 | 1118 | |
| 1114 | 1119 | mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac); |
| 1115 | 1120 | mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv); |
| @@ -1151,7 +1156,8 @@ void amdgpu_atombios_set_engine_dram_timings(struct amdgpu_device *adev, · 35 unmodified lines | ||
| 1151 | 1156 | if (mem_clock) |
| 1152 | 1157 | args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK); |
| 1153 | 1158 | |
| 1154 | − amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); | |
| 1159 | + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, | |
| 1160 | + sizeof(args)); | |
| 1155 | 1161 | } |
| 1156 | 1162 | |
| 1157 | 1163 | void amdgpu_atombios_get_default_voltages(struct amdgpu_device *adev, |
| @@ -1205,7 +1211,8 @@ int amdgpu_atombios_get_max_vddc(struct amdgpu_device *adev, u8 voltage_type, · 47 unmodified lines | ||
| 1205 | 1211 | args.v2.ucVoltageMode = 0; |
| 1206 | 1212 | args.v2.usVoltageLevel = 0; |
| 1207 | 1213 | |
| 1208 | − amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); | |
| 1214 | + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, | |
| 1215 | + sizeof(args)); | |
| 1209 | 1216 | |
| 1210 | 1217 | *voltage = le16_to_cpu(args.v2.usVoltageLevel); |
| 1211 | 1218 | break; |
| @@ -1214,7 +1221,8 @@ int amdgpu_atombios_get_max_vddc(struct amdgpu_device *adev, u8 voltage_type, · 2 unmodified lines | ||
| 1214 | 1221 | args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL; |
| 1215 | 1222 | args.v3.usVoltageLevel = cpu_to_le16(voltage_id); |
| 1216 | 1223 | |
| 1217 | − amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); | |
| 1224 | + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, | |
| 1225 | + sizeof(args)); | |
| 1218 | 1226 | |
| 1219 | 1227 | *voltage = le16_to_cpu(args.v3.usVoltageLevel); |
| 1220 | 1228 | break; |
| @@ -941,5 +941,6 @@ int amdgpu_atomfirmware_asic_init(struct amdgpu_device *adev, bool fb_reset) · 940 unmodified lines | ||
| 941 | 941 | return -EINVAL; |
| 942 | 942 | } |
| 943 | 943 | |
| 944 | − return amdgpu_atom_execute_table(ctx, ATOM_CMD_INIT, (uint32_t *)&asic_init_ps_v2_1); | |
| 944 | + return amdgpu_atom_execute_table(ctx, ATOM_CMD_INIT, (uint32_t *)&asic_init_ps_v2_1, | |
| 945 | + sizeof(asic_init_ps_v2_1)); | |
| 945 | 946 | } |
| @@ -36,7 +36,7 @@ int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev); · 35 unmodified lines | ||
| 36 | 36 | int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev); |
| 37 | 37 | bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev); |
| 38 | 38 | bool amdgpu_atomfirmware_sram_ecc_supported(struct amdgpu_device *adev); |
| 39 | −bool amdgpu_atomfirmware_ras_rom_addr(struct amdgpu_device *adev, uint8_t* i2c_address); | |
| 39 | +bool amdgpu_atomfirmware_ras_rom_addr(struct amdgpu_device *adev, uint8_t *i2c_address); | |
| 40 | 40 | bool amdgpu_atomfirmware_mem_training_supported(struct amdgpu_device *adev); |
| 41 | 41 | bool amdgpu_atomfirmware_dynamic_boot_config_supported(struct amdgpu_device *adev); |
| 42 | 42 | int amdgpu_atomfirmware_get_fw_reserved_fb_size(struct amdgpu_device *adev); |
| @@ -952,10 +952,10 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, · 951 unmodified lines | ||
| 952 | 952 | p->bytes_moved = 0; |
| 953 | 953 | p->bytes_moved_vis = 0; |
| 954 | 954 | |
| 955 | − r = amdgpu_vm_validate_pt_bos(p->adev, &fpriv->vm, | |
| 956 | − amdgpu_cs_bo_validate, p); | |
| 955 | + r = amdgpu_vm_validate(p->adev, &fpriv->vm, NULL, | |
| 956 | + amdgpu_cs_bo_validate, p); | |
| 957 | 957 | if (r) { |
| 958 | − DRM_ERROR("amdgpu_vm_validate_pt_bos() failed.\n"); | |
| 958 | + DRM_ERROR("amdgpu_vm_validate() failed.\n"); | |
| 959 | 959 | goto out_free_user_pages; |
| 960 | 960 | } |
| 961 | 961 | |
| @@ -30,7 +30,7 @@ uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev) · 29 unmodified lines | ||
| 30 | 30 | { |
| 31 | 31 | uint64_t addr = adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT; |
| 32 | 32 | |
| 33 | − addr -= AMDGPU_VA_RESERVED_SIZE; | |
| 33 | + addr -= AMDGPU_VA_RESERVED_CSA_SIZE; | |
| 34 | 34 | addr = amdgpu_gmc_sign_extend(addr); |
| 35 | 35 | |
| 36 | 36 | return addr; |
| @@ -1678,7 +1678,7 @@ static int amdgpu_debugfs_test_ib_show(struct seq_file *m, void *unused) · 1677 unmodified lines | ||
| 1678 | 1678 | for (i = 0; i < AMDGPU_MAX_RINGS; i++) { |
| 1679 | 1679 | struct amdgpu_ring *ring = adev->rings[i]; |
| 1680 | 1680 | |
| 1681 | − if (!ring || !drm_sched_wqueue_ready(&ring->sched)) | |
| 1681 | + if (!amdgpu_ring_sched_ready(ring)) | |
| 1682 | 1682 | continue; |
| 1683 | 1683 | drm_sched_wqueue_stop(&ring->sched); |
| 1684 | 1684 | } |
| @@ -1694,7 +1694,7 @@ static int amdgpu_debugfs_test_ib_show(struct seq_file *m, void *unused) · 9 unmodified lines | ||
| 1694 | 1694 | for (i = 0; i < AMDGPU_MAX_RINGS; i++) { |
| 1695 | 1695 | struct amdgpu_ring *ring = adev->rings[i]; |
| 1696 | 1696 | |
| 1697 | − if (!ring || !drm_sched_wqueue_ready(&ring->sched)) | |
| 1697 | + if (!amdgpu_ring_sched_ready(ring)) | |
| 1698 | 1698 | continue; |
| 1699 | 1699 | drm_sched_wqueue_start(&ring->sched); |
| 1700 | 1700 | } |
| @@ -1916,8 +1916,8 @@ static int amdgpu_debugfs_ib_preempt(void *data, u64 val) · 215 unmodified lines | ||
| 1916 | 1916 | |
| 1917 | 1917 | ring = adev->rings[val]; |
| 1918 | 1918 | |
| 1919 | − if (!ring || !ring->funcs->preempt_ib || | |
| 1920 | − !drm_sched_wqueue_ready(&ring->sched)) | |
| 1919 | + if (!amdgpu_ring_sched_ready(ring) || | |
| 1920 | + !ring->funcs->preempt_ib) | |
| 1921 | 1921 | return -EINVAL; |
| 1922 | 1922 | |
| 1923 | 1923 | /* the last preemption failed */ |
| @@ -96,6 +96,9 @@ MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin"); · 95 unmodified lines | ||
| 96 | 96 | #define AMDGPU_RESUME_MS 2000 |
| 97 | 97 | #define AMDGPU_MAX_RETRY_LIMIT 2 |
| 98 | 98 | #define AMDGPU_RETRY_SRIOV_RESET(r) ((r) == -EBUSY || (r) == -ETIMEDOUT || (r) == -EINVAL) |
| 99 | +#define AMDGPU_PCIE_INDEX_FALLBACK (0x38 >> 2) | |
| 100 | +#define AMDGPU_PCIE_INDEX_HI_FALLBACK (0x44 >> 2) | |
| 101 | +#define AMDGPU_PCIE_DATA_FALLBACK (0x3C >> 2) | |
| 99 | 102 | |
| 100 | 103 | static const struct drm_driver amdgpu_kms_driver; |
| 101 | 104 | |
| @@ -781,12 +784,22 @@ u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev, · 679 unmodified lines | ||
| 781 | 784 | void __iomem *pcie_index_hi_offset; |
| 782 | 785 | void __iomem *pcie_data_offset; |
| 783 | 786 | |
| 784 | − pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); | |
| 785 | − pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); | |
| 786 | − if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offset)) | |
| 787 | − pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev); | |
| 788 | − else | |
| 787 | + if (unlikely(!adev->nbio.funcs)) { | |
| 788 | + pcie_index = AMDGPU_PCIE_INDEX_FALLBACK; | |
| 789 | + pcie_data = AMDGPU_PCIE_DATA_FALLBACK; | |
| 790 | + } else { | |
| 791 | + pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); | |
| 792 | + pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); | |
| 793 | + } | |
| 794 | + | |
| 795 | + if (reg_addr >> 32) { | |
| 796 | + if (unlikely(!adev->nbio.funcs)) | |
| 797 | + pcie_index_hi = AMDGPU_PCIE_INDEX_HI_FALLBACK; | |
| 798 | + else | |
| 799 | + pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev); | |
| 800 | + } else { | |
| 789 | 801 | pcie_index_hi = 0; |
| 802 | + } | |
| 790 | 803 | |
| 791 | 804 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); |
| 792 | 805 | pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; |
| @@ -1218,8 +1231,6 @@ static int amdgpu_device_asic_init(struct amdgpu_device *adev) · 425 unmodified lines | ||
| 1218 | 1231 | amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(11, 0, 0)) { |
| 1219 | 1232 | amdgpu_psp_wait_for_bootloader(adev); |
| 1220 | 1233 | ret = amdgpu_atomfirmware_asic_init(adev, true); |
| 1221 | − /* TODO: check the return val and stop device initialization if boot fails */ | |
| 1222 | − amdgpu_psp_query_boot_status(adev); | |
| 1223 | 1234 | return ret; |
| 1224 | 1235 | } else { |
| 1225 | 1236 | return amdgpu_atom_asic_init(adev->mode_info.atom_context); |
| @@ -1442,6 +1453,10 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev) · 216 unmodified lines | ||
| 1442 | 1453 | if (amdgpu_sriov_vf(adev)) |
| 1443 | 1454 | return 0; |
| 1444 | 1455 | |
| 1456 | + /* PCI_EXT_CAP_ID_VNDR extended capability is located at 0x100 */ | |
| 1457 | + if (!pci_find_ext_capability(adev->pdev, PCI_EXT_CAP_ID_VNDR)) | |
| 1458 | + DRM_WARN("System can't access extended configuration space,please check!!\n"); | |
| 1459 | + | |
| 1445 | 1460 | /* skip if the bios has already enabled large BAR */ |
| 1446 | 1461 | if (adev->gmc.real_vram_size && |
| 1447 | 1462 | (pci_resource_len(adev->pdev, 0) >= adev->gmc.real_vram_size)) |
| @@ -4121,23 +4136,13 @@ int amdgpu_device_init(struct amdgpu_device *adev, · 2673 unmodified lines | ||
| 4121 | 4136 | } |
| 4122 | 4137 | } |
| 4123 | 4138 | } else { |
| 4124 | − switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { | |
| 4125 | − case IP_VERSION(13, 0, 0): | |
| 4126 | − case IP_VERSION(13, 0, 7): | |
| 4127 | − case IP_VERSION(13, 0, 10): | |
| 4128 | − r = psp_gpu_reset(adev); | |
| 4129 | − break; | |
| 4130 | − default: | |
| 4131 | − tmp = amdgpu_reset_method; | |
| 4132 | − /* It should do a default reset when loading or reloading the driver, | |
| 4133 | − * regardless of the module parameter reset_method. | |
| 4134 | − */ | |
| 4135 | − amdgpu_reset_method = AMD_RESET_METHOD_NONE; | |
| 4136 | − r = amdgpu_asic_reset(adev); | |
| 4137 | − amdgpu_reset_method = tmp; | |
| 4138 | − break; | |
| 4139 | − } | |
| 4140 | − | |
| 4139 | + tmp = amdgpu_reset_method; | |
| 4140 | + /* It should do a default reset when loading or reloading the driver, | |
| 4141 | + * regardless of the module parameter reset_method. | |
| 4142 | + */ | |
| 4143 | + amdgpu_reset_method = AMD_RESET_METHOD_NONE; | |
| 4144 | + r = amdgpu_asic_reset(adev); | |
| 4145 | + amdgpu_reset_method = tmp; | |
| 4141 | 4146 | if (r) { |
| 4142 | 4147 | dev_err(adev->dev, "asic reset on init failed\n"); |
| 4143 | 4148 | goto failed; |
| @@ -5031,7 +5036,7 @@ bool amdgpu_device_has_job_running(struct amdgpu_device *adev) · 887 unmodified lines | ||
| 5031 | 5036 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
| 5032 | 5037 | struct amdgpu_ring *ring = adev->rings[i]; |
| 5033 | 5038 | |
| 5034 | − if (!ring || !drm_sched_wqueue_ready(&ring->sched)) | |
| 5039 | + if (!amdgpu_ring_sched_ready(ring)) | |
| 5035 | 5040 | continue; |
| 5036 | 5041 | |
| 5037 | 5042 | spin_lock(&ring->sched.job_list_lock); |
| @@ -5170,7 +5175,7 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, · 132 unmodified lines | ||
| 5170 | 5175 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
| 5171 | 5176 | struct amdgpu_ring *ring = adev->rings[i]; |
| 5172 | 5177 | |
| 5173 | − if (!ring || !drm_sched_wqueue_ready(&ring->sched)) | |
| 5178 | + if (!amdgpu_ring_sched_ready(ring)) | |
| 5174 | 5179 | continue; |
| 5175 | 5180 | |
| 5176 | 5181 | /* Clear job fence from fence drv to avoid force_completion |
| @@ -5637,7 +5642,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, · 460 unmodified lines | ||
| 5637 | 5642 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
| 5638 | 5643 | struct amdgpu_ring *ring = tmp_adev->rings[i]; |
| 5639 | 5644 | |
| 5640 | − if (!ring || !drm_sched_wqueue_ready(&ring->sched)) | |
| 5645 | + if (!amdgpu_ring_sched_ready(ring)) | |
| 5641 | 5646 | continue; |
| 5642 | 5647 | |
| 5643 | 5648 | drm_sched_stop(&ring->sched, job ? &job->base : NULL); |
| @@ -5690,6 +5695,7 @@ retry: /* Rest of adevs pre asic reset from XGMI hive. */ · 46 unmodified lines | ||
| 5690 | 5695 | /* Aldebaran and gfx_11_0_3 support ras in SRIOV, so need resume ras during reset */ |
| 5691 | 5696 | if (amdgpu_ip_version(adev, GC_HWIP, 0) == |
| 5692 | 5697 | IP_VERSION(9, 4, 2) || |
| 5698 | + amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || | |
| 5693 | 5699 | amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 3)) |
| 5694 | 5700 | amdgpu_ras_resume(adev); |
| 5695 | 5701 | } else { |
| @@ -5706,7 +5712,7 @@ skip_hw_reset: · 10 unmodified lines | ||
| 5706 | 5712 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
| 5707 | 5713 | struct amdgpu_ring *ring = tmp_adev->rings[i]; |
| 5708 | 5714 | |
| 5709 | − if (!ring || !drm_sched_wqueue_ready(&ring->sched)) | |
| 5715 | + if (!amdgpu_ring_sched_ready(ring)) | |
| 5710 | 5716 | continue; |
| 5711 | 5717 | |
| 5712 | 5718 | drm_sched_start(&ring->sched, true); |
| @@ -6061,7 +6067,7 @@ pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, pci_channel_sta · 348 unmodified lines | ||
| 6061 | 6067 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
| 6062 | 6068 | struct amdgpu_ring *ring = adev->rings[i]; |
| 6063 | 6069 | |
| 6064 | − if (!ring || !drm_sched_wqueue_ready(&ring->sched)) | |
| 6070 | + if (!amdgpu_ring_sched_ready(ring)) | |
| 6065 | 6071 | continue; |
| 6066 | 6072 | |
| 6067 | 6073 | drm_sched_stop(&ring->sched, NULL); |
| @@ -6111,6 +6117,20 @@ pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev) · 43 unmodified lines | ||
| 6111 | 6117 | struct amdgpu_reset_context reset_context; |
| 6112 | 6118 | u32 memsize; |
| 6113 | 6119 | struct list_head device_list; |
| 6120 | + struct amdgpu_hive_info *hive; | |
| 6121 | + int hive_ras_recovery = 0; | |
| 6122 | + struct amdgpu_ras *ras; | |
| 6123 | + | |
| 6124 | + /* PCI error slot reset should be skipped During RAS recovery */ | |
| 6125 | + hive = amdgpu_get_xgmi_hive(adev); | |
| 6126 | + if (hive) { | |
| 6127 | + hive_ras_recovery = atomic_read(&hive->ras_recovery); | |
| 6128 | + amdgpu_put_xgmi_hive(hive); | |
| 6129 | + } | |
| 6130 | + ras = amdgpu_ras_get_context(adev); | |
| 6131 | + if ((amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) && | |
| 6132 | + ras && (atomic_read(&ras->in_recovery) || hive_ras_recovery)) | |
| 6133 | + return PCI_ERS_RESULT_RECOVERED; | |
| 6114 | 6134 | |
| 6115 | 6135 | DRM_INFO("PCI error: slot reset callback!!\n"); |
| 6116 | 6136 | |
| @@ -6189,7 +6209,7 @@ void amdgpu_pci_resume(struct pci_dev *pdev) · 72 unmodified lines | ||
| 6189 | 6209 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
| 6190 | 6210 | struct amdgpu_ring *ring = adev->rings[i]; |
| 6191 | 6211 | |
| 6192 | − if (!ring || !drm_sched_wqueue_ready(&ring->sched)) | |
| 6212 | + if (!amdgpu_ring_sched_ready(ring)) | |
| 6193 | 6213 | continue; |
| 6194 | 6214 | |
| 6195 | 6215 | drm_sched_start(&ring->sched, true); |
| @@ -27,6 +27,7 @@ · 26 unmodified lines | ||
| 27 | 27 | #include "amdgpu_discovery.h" |
| 28 | 28 | #include "soc15_hw_ip.h" |
| 29 | 29 | #include "discovery.h" |
| 30 | +#include "amdgpu_ras.h" | |
| 30 | 31 | |
| 31 | 32 | #include "soc15.h" |
| 32 | 33 | #include "gfx_v9_0.h" |
| @@ -98,6 +99,7 @@ · 65 unmodified lines | ||
| 98 | 99 | #define FIRMWARE_IP_DISCOVERY "amdgpu/ip_discovery.bin" |
| 99 | 100 | MODULE_FIRMWARE(FIRMWARE_IP_DISCOVERY); |
| 100 | 101 | |
| 102 | +#define mmIP_DISCOVERY_VERSION 0x16A00 | |
| 101 | 103 | #define mmRCC_CONFIG_MEMSIZE 0xde3 |
| 102 | 104 | #define mmMP0_SMN_C2PMSG_33 0x16061 |
| 103 | 105 | #define mmMM_INDEX 0x0 |
| @@ -518,7 +520,9 @@ static int amdgpu_discovery_init(struct amdgpu_device *adev) · 414 unmodified lines | ||
| 518 | 520 | out: |
| 519 | 521 | kfree(adev->mman.discovery_bin); |
| 520 | 522 | adev->mman.discovery_bin = NULL; |
| 521 | − | |
| 523 | + if ((amdgpu_discovery != 2) && | |
| 524 | + (RREG32(mmIP_DISCOVERY_VERSION) == 4)) | |
| 525 | + amdgpu_ras_query_boot_status(adev, 4); | |
| 522 | 526 | return r; |
| 523 | 527 | } |
| 524 | 528 | |
| @@ -1278,11 +1282,10 @@ static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) · 753 unmodified lines | ||
| 1278 | 1282 | * 0b10 : encode is disabled |
| 1279 | 1283 | * 0b01 : decode is disabled |
| 1280 | 1284 | */ |
| 1281 | − adev->vcn.vcn_config[adev->vcn.num_vcn_inst] = | |
| 1282 | − ip->revision & 0xc0; | |
| 1283 | − ip->revision &= ~0xc0; | |
| 1284 | 1285 | if (adev->vcn.num_vcn_inst < |
| 1285 | 1286 | AMDGPU_MAX_VCN_INSTANCES) { |
| 1287 | + adev->vcn.vcn_config[adev->vcn.num_vcn_inst] = | |
| 1288 | + ip->revision & 0xc0; | |
| 1286 | 1289 | adev->vcn.num_vcn_inst++; |
| 1287 | 1290 | adev->vcn.inst_mask |= |
| 1288 | 1291 | (1U << ip->instance_number); |
| @@ -1293,6 +1296,7 @@ static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) · 4 unmodified lines | ||
| 1293 | 1296 | adev->vcn.num_vcn_inst + 1, |
| 1294 | 1297 | AMDGPU_MAX_VCN_INSTANCES); |
| 1295 | 1298 | } |
| 1299 | + ip->revision &= ~0xc0; | |
| 1296 | 1300 | } |
| 1297 | 1301 | if (le16_to_cpu(ip->hw_id) == SDMA0_HWID || |
| 1298 | 1302 | le16_to_cpu(ip->hw_id) == SDMA1_HWID || |
| @@ -377,6 +377,10 @@ amdgpu_dma_buf_move_notify(struct dma_buf_attachment *attach) · 376 unmodified lines | ||
| 377 | 377 | struct amdgpu_vm_bo_base *bo_base; |
| 378 | 378 | int r; |
| 379 | 379 | |
| 380 | + /* FIXME: This should be after the "if", but needs a fix to make sure | |
| 381 | + * DMABuf imports are initialized in the right VM list. | |
| 382 | + */ | |
| 383 | + amdgpu_vm_bo_invalidate(adev, bo, false); | |
| 380 | 384 | if (!bo->tbo.resource || bo->tbo.resource->mem_type == TTM_PL_SYSTEM) |
| 381 | 385 | return; |
| 382 | 386 | |
| @@ -366,7 +366,7 @@ module_param_named(aspm, amdgpu_aspm, int, 0444); · 365 unmodified lines | ||
| 366 | 366 | * Setting the value to 0 disables this functionality. |
| 367 | 367 | * Setting the value to -2 is auto enabled with power down when displays are attached. |
| 368 | 368 | */ |
| 369 | −MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto, -2 = autowith displays)"); | |
| 369 | +MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto, -2 = auto with displays)"); | |
| 370 | 370 | module_param_named(runpm, amdgpu_runtime_pm, int, 0444); |
| 371 | 371 | |
| 372 | 372 | /** |
| @@ -593,7 +593,7 @@ module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); · 220 unmodified lines | ||
| 593 | 593 | #ifdef CONFIG_DRM_AMDGPU_SI |
| 594 | 594 | |
| 595 | 595 | #if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE) |
| 596 | −int amdgpu_si_support = 0; | |
| 596 | +int amdgpu_si_support; | |
| 597 | 597 | MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); |
| 598 | 598 | #else |
| 599 | 599 | int amdgpu_si_support = 1; |
| @@ -612,7 +612,7 @@ module_param_named(si_support, amdgpu_si_support, int, 0444); · 12 unmodified lines | ||
| 612 | 612 | #ifdef CONFIG_DRM_AMDGPU_CIK |
| 613 | 613 | |
| 614 | 614 | #if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE) |
| 615 | −int amdgpu_cik_support = 0; | |
| 615 | +int amdgpu_cik_support; | |
| 616 | 616 | MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); |
| 617 | 617 | #else |
| 618 | 618 | int amdgpu_cik_support = 1; |
| @@ -2255,6 +2255,10 @@ retry_init: · 1636 unmodified lines | ||
| 2255 | 2255 | if (ret) |
| 2256 | 2256 | goto err_pci; |
| 2257 | 2257 | |
| 2258 | + ret = amdgpu_amdkfd_drm_client_create(adev); | |
| 2259 | + if (ret) | |
| 2260 | + goto err_pci; | |
| 2261 | + | |
| 2258 | 2262 | /* |
| 2259 | 2263 | * 1. don't init fbdev on hw without DCE |
| 2260 | 2264 | * 2. don't init fbdev if there are no connectors |
| @@ -2472,6 +2476,7 @@ static int amdgpu_pmops_suspend(struct device *dev) · 211 unmodified lines | ||
| 2472 | 2476 | struct drm_device *drm_dev = dev_get_drvdata(dev); |
| 2473 | 2477 | struct amdgpu_device *adev = drm_to_adev(drm_dev); |
| 2474 | 2478 | |
| 2479 | + adev->suspend_complete = false; | |
| 2475 | 2480 | if (amdgpu_acpi_is_s0ix_active(adev)) |
| 2476 | 2481 | adev->in_s0ix = true; |
| 2477 | 2482 | else if (amdgpu_acpi_is_s3_active(adev)) |
| @@ -2486,6 +2491,7 @@ static int amdgpu_pmops_suspend_noirq(struct device *dev) · 8 unmodified lines | ||
| 2486 | 2491 | struct drm_device *drm_dev = dev_get_drvdata(dev); |
| 2487 | 2492 | struct amdgpu_device *adev = drm_to_adev(drm_dev); |
| 2488 | 2493 | |
| 2494 | + adev->suspend_complete = true; | |
| 2489 | 2495 | if (amdgpu_acpi_should_gpu_reset(adev)) |
| 2490 | 2496 | return amdgpu_asic_reset(adev); |
| 2491 | 2497 | |
| @@ -121,6 +121,7 @@ int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev) · 120 unmodified lines | ||
| 121 | 121 | struct amdgpu_bo_param bp; |
| 122 | 122 | dma_addr_t dma_addr; |
| 123 | 123 | struct page *p; |
| 124 | + unsigned long x; | |
| 124 | 125 | int ret; |
| 125 | 126 | |
| 126 | 127 | if (adev->gart.bo != NULL) |
| @@ -130,6 +131,10 @@ int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev) · 3 unmodified lines | ||
| 130 | 131 | if (!p) |
| 131 | 132 | return -ENOMEM; |
| 132 | 133 | |
| 134 | + /* assign pages to this device */ | |
| 135 | + for (x = 0; x < (1UL << order); x++) | |
| 136 | + p[x].mapping = adev->mman.bdev.dev_mapping; | |
| 137 | + | |
| 133 | 138 | /* If the hardware does not support UTCL2 snooping of the CPU caches |
| 134 | 139 | * then set_memory_wc() could be used as a workaround to mark the pages |
| 135 | 140 | * as write combine memory. |
| @@ -223,6 +228,7 @@ void amdgpu_gart_table_ram_free(struct amdgpu_device *adev) · 87 unmodified lines | ||
| 223 | 228 | unsigned int order = get_order(adev->gart.table_size); |
| 224 | 229 | struct sg_table *sg = adev->gart.bo->tbo.sg; |
| 225 | 230 | struct page *p; |
| 231 | + unsigned long x; | |
| 226 | 232 | int ret; |
| 227 | 233 | |
| 228 | 234 | ret = amdgpu_bo_reserve(adev->gart.bo, false); |
| @@ -234,6 +240,8 @@ void amdgpu_gart_table_ram_free(struct amdgpu_device *adev) · 5 unmodified lines | ||
| 234 | 240 | sg_free_table(sg); |
| 235 | 241 | kfree(sg); |
| 236 | 242 | p = virt_to_page(adev->gart.ptr); |
| 243 | + for (x = 0; x < (1UL << order); x++) | |
| 244 | + p[x].mapping = NULL; | |
| 237 | 245 | __free_pages(p, order); |
| 238 | 246 | |
| 239 | 247 | adev->gart.ptr = NULL; |
| @@ -187,7 +187,34 @@ static int amdgpu_gem_object_open(struct drm_gem_object *obj, · 186 unmodified lines | ||
| 187 | 187 | else |
| 188 | 188 | ++bo_va->ref_count; |
| 189 | 189 | amdgpu_bo_unreserve(abo); |
| 190 | − return 0; | |
| 190 | + | |
| 191 | + /* Validate and add eviction fence to DMABuf imports with dynamic | |
| 192 | + * attachment in compute VMs. Re-validation will be done by | |
| 193 | + * amdgpu_vm_validate. Fences are on the reservation shared with the | |
| 194 | + * export, which is currently required to be validated and fenced | |
| 195 | + * already by amdgpu_amdkfd_gpuvm_restore_process_bos. | |
| 196 | + * | |
| 197 | + * Nested locking below for the case that a GEM object is opened in | |
| 198 | + * kfd_mem_export_dmabuf. Since the lock below is only taken for imports, | |
| 199 | + * but not for export, this is a different lock class that cannot lead to | |
| 200 | + * circular lock dependencies. | |
| 201 | + */ | |
| 202 | + if (!vm->is_compute_context || !vm->process_info) | |
| 203 | + return 0; | |
| 204 | + if (!obj->import_attach || | |
| 205 | + !dma_buf_is_dynamic(obj->import_attach->dmabuf)) | |
| 206 | + return 0; | |
| 207 | + mutex_lock_nested(&vm->process_info->lock, 1); | |
| 208 | + if (!WARN_ON(!vm->process_info->eviction_fence)) { | |
| 209 | + r = amdgpu_amdkfd_bo_validate_and_fence(abo, AMDGPU_GEM_DOMAIN_GTT, | |
| 210 | + &vm->process_info->eviction_fence->base); | |
| 211 | + if (r) | |
| 212 | + dev_warn(adev->dev, "%d: validate_and_fence failed: %d\n", | |
| 213 | + vm->task_info.pid, r); | |
| 214 | + } | |
| 215 | + mutex_unlock(&vm->process_info->lock); | |
| 216 | + | |
| 217 | + return r; | |
| 191 | 218 | } |
| 192 | 219 | |
| 193 | 220 | static void amdgpu_gem_object_close(struct drm_gem_object *obj, |
| @@ -682,10 +709,10 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, · 488 unmodified lines | ||
| 682 | 709 | uint64_t vm_size; |
| 683 | 710 | int r = 0; |
| 684 | 711 | |
| 685 | − if (args->va_address < AMDGPU_VA_RESERVED_SIZE) { | |
| 712 | + if (args->va_address < AMDGPU_VA_RESERVED_BOTTOM) { | |
| 686 | 713 | dev_dbg(dev->dev, |
| 687 | 714 | "va_address 0x%llx is in reserved area 0x%llx\n", |
| 688 | − args->va_address, AMDGPU_VA_RESERVED_SIZE); | |
| 715 | + args->va_address, AMDGPU_VA_RESERVED_BOTTOM); | |
| 689 | 716 | return -EINVAL; |
| 690 | 717 | } |
| 691 | 718 | |
| @@ -701,7 +728,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, · 9 unmodified lines | ||
| 701 | 728 | args->va_address &= AMDGPU_GMC_HOLE_MASK; |
| 702 | 729 | |
| 703 | 730 | vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; |
| 704 | − vm_size -= AMDGPU_VA_RESERVED_SIZE; | |
| 731 | + vm_size -= AMDGPU_VA_RESERVED_TOP; | |
| 705 | 732 | if (args->va_address + args->map_size > vm_size) { |
| 706 | 733 | dev_dbg(dev->dev, |
| 707 | 734 | "va_address 0x%llx is in top reserved area 0x%llx\n", |
| @@ -329,7 +329,8 @@ int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, · 328 unmodified lines | ||
| 329 | 329 | |
| 330 | 330 | ring->eop_gpu_addr = kiq->eop_gpu_addr; |
| 331 | 331 | ring->no_scheduler = true; |
| 332 | − sprintf(ring->name, "kiq_%d.%d.%d.%d", xcc_id, ring->me, ring->pipe, ring->queue); | |
| 332 | + snprintf(ring->name, sizeof(ring->name), "kiq_%d.%d.%d.%d", | |
| 333 | + xcc_id, ring->me, ring->pipe, ring->queue); | |
| 333 | 334 | r = amdgpu_ring_init(adev, ring, 1024, irq, AMDGPU_CP_KIQ_IRQ_DRIVER0, |
| 334 | 335 | AMDGPU_RING_PRIO_DEFAULT, NULL); |
| 335 | 336 | if (r) |
| @@ -642,8 +643,8 @@ int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev, int xcc_id) · 306 unmodified lines | ||
| 642 | 643 | kiq->pmf->kiq_set_resources(kiq_ring, queue_mask); |
| 643 | 644 | for (i = 0; i < adev->gfx.num_compute_rings; i++) { |
| 644 | 645 | j = i + xcc_id * adev->gfx.num_compute_rings; |
| 645 | − kiq->pmf->kiq_map_queues(kiq_ring, | |
| 646 | − &adev->gfx.compute_ring[j]); | |
| 646 | + kiq->pmf->kiq_map_queues(kiq_ring, | |
| 647 | + &adev->gfx.compute_ring[j]); | |
| 647 | 648 | } |
| 648 | 649 | |
| 649 | 650 | r = amdgpu_ring_test_helper(kiq_ring); |
| @@ -52,7 +52,7 @@ int amdgpu_gmc_pdb0_alloc(struct amdgpu_device *adev) · 51 unmodified lines | ||
| 52 | 52 | struct amdgpu_bo_param bp; |
| 53 | 53 | u64 vram_size = adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes; |
| 54 | 54 | uint32_t pde0_page_shift = adev->gmc.vmid0_page_table_block_size + 21; |
| 55 | − uint32_t npdes = (vram_size + (1ULL << pde0_page_shift) -1) >> pde0_page_shift; | |
| 55 | + uint32_t npdes = (vram_size + (1ULL << pde0_page_shift) - 1) >> pde0_page_shift; | |
| 56 | 56 | |
| 57 | 57 | memset(&bp, 0, sizeof(bp)); |
| 58 | 58 | bp.size = PAGE_ALIGN((npdes + 1) * 8); |
| @@ -746,6 +746,59 @@ error_unlock_reset: · 687 unmodified lines | ||
| 746 | 746 | return r; |
| 747 | 747 | } |
| 748 | 748 | |
| 749 | +void amdgpu_gmc_fw_reg_write_reg_wait(struct amdgpu_device *adev, | |
| 750 | + uint32_t reg0, uint32_t reg1, | |
| 751 | + uint32_t ref, uint32_t mask, | |
| 752 | + uint32_t xcc_inst) | |
| 753 | +{ | |
| 754 | + struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_inst]; | |
| 755 | + struct amdgpu_ring *ring = &kiq->ring; | |
| 756 | + signed long r, cnt = 0; | |
| 757 | + unsigned long flags; | |
| 758 | + uint32_t seq; | |
| 759 | + | |
| 760 | + if (adev->mes.ring.sched.ready) { | |
| 761 | + amdgpu_mes_reg_write_reg_wait(adev, reg0, reg1, | |
| 762 | + ref, mask); | |
| 763 | + return; | |
| 764 | + } | |
| 765 | + | |
| 766 | + spin_lock_irqsave(&kiq->ring_lock, flags); | |
| 767 | + amdgpu_ring_alloc(ring, 32); | |
| 768 | + amdgpu_ring_emit_reg_write_reg_wait(ring, reg0, reg1, | |
| 769 | + ref, mask); | |
| 770 | + r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); | |
| 771 | + if (r) | |
| 772 | + goto failed_undo; | |
| 773 | + | |
| 774 | + amdgpu_ring_commit(ring); | |
| 775 | + spin_unlock_irqrestore(&kiq->ring_lock, flags); | |
| 776 | + | |
| 777 | + r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); | |
| 778 | + | |
| 779 | + /* don't wait anymore for IRQ context */ | |
| 780 | + if (r < 1 && in_interrupt()) | |
| 781 | + goto failed_kiq; | |
| 782 | + | |
| 783 | + might_sleep(); | |
| 784 | + while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) { | |
| 785 | + | |
| 786 | + msleep(MAX_KIQ_REG_BAILOUT_INTERVAL); | |
| 787 | + r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); | |
| 788 | + } | |
| 789 | + | |
| 790 | + if (cnt > MAX_KIQ_REG_TRY) | |
| 791 | + goto failed_kiq; | |
| 792 | + | |
| 793 | + return; | |
| 794 | + | |
| 795 | +failed_undo: | |
| 796 | + amdgpu_ring_undo(ring); | |
| 797 | + spin_unlock_irqrestore(&kiq->ring_lock, flags); | |
| 798 | +failed_kiq: | |
| 799 | + dev_err(adev->dev, "failed to write reg %x wait reg %x\n", reg0, reg1); | |
| 800 | +} | |
| 801 | + | |
| 749 | 802 | /** |
| 750 | 803 | * amdgpu_gmc_tmz_set -- check and set if a device supports TMZ |
| 751 | 804 | * @adev: amdgpu_device pointer |
| @@ -417,6 +417,10 @@ void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, · 416 unmodified lines | ||
| 417 | 417 | int amdgpu_gmc_flush_gpu_tlb_pasid(struct amdgpu_device *adev, uint16_t pasid, |
| 418 | 418 | uint32_t flush_type, bool all_hub, |
| 419 | 419 | uint32_t inst); |
| 420 | +void amdgpu_gmc_fw_reg_write_reg_wait(struct amdgpu_device *adev, | |
| 421 | + uint32_t reg0, uint32_t reg1, | |
| 422 | + uint32_t ref, uint32_t mask, | |
| 423 | + uint32_t xcc_inst); | |
| 420 | 424 | |
| 421 | 425 | extern void amdgpu_gmc_tmz_set(struct amdgpu_device *adev); |
| 422 | 426 | extern void amdgpu_gmc_noretry_set(struct amdgpu_device *adev); |
| @@ -62,9 +62,8 @@ int amdgpu_pasid_alloc(unsigned int bits) · 61 unmodified lines | ||
| 62 | 62 | int pasid = -EINVAL; |
| 63 | 63 | |
| 64 | 64 | for (bits = min(bits, 31U); bits > 0; bits--) { |
| 65 | − pasid = ida_simple_get(&amdgpu_pasid_ida, | |
| 66 | − 1U << (bits - 1), 1U << bits, | |
| 67 | − GFP_KERNEL); | |
| 65 | + pasid = ida_alloc_range(&amdgpu_pasid_ida, 1U << (bits - 1), | |
| 66 | + (1U << bits) - 1, GFP_KERNEL); | |
| 68 | 67 | if (pasid != -ENOSPC) |
| 69 | 68 | break; |
| 70 | 69 | } |
| @@ -82,7 +81,7 @@ int amdgpu_pasid_alloc(unsigned int bits) · 11 unmodified lines | ||
| 82 | 81 | void amdgpu_pasid_free(u32 pasid) |
| 83 | 82 | { |
| 84 | 83 | trace_amdgpu_pasid_freed(pasid); |
| 85 | − ida_simple_remove(&amdgpu_pasid_ida, pasid); | |
| 84 | + ida_free(&amdgpu_pasid_ida, pasid); | |
| 86 | 85 | } |
| 87 | 86 | |
| 88 | 87 | static void amdgpu_pasid_free_cb(struct dma_fence *fence, |
| @@ -894,14 +894,14 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) · 893 unmodified lines | ||
| 894 | 894 | dev_info->ids_flags |= AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD; |
| 895 | 895 | |
| 896 | 896 | vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; |
| 897 | − vm_size -= AMDGPU_VA_RESERVED_SIZE; | |
| 897 | + vm_size -= AMDGPU_VA_RESERVED_TOP; | |
| 898 | 898 | |
| 899 | 899 | /* Older VCE FW versions are buggy and can handle only 40bits */ |
| 900 | 900 | if (adev->vce.fw_version && |
| 901 | 901 | adev->vce.fw_version < AMDGPU_VCE_FW_53_45) |
| 902 | 902 | vm_size = min(vm_size, 1ULL << 40); |
| 903 | 903 | |
| 904 | − dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; | |
| 904 | + dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_BOTTOM; | |
| 905 | 905 | dev_info->virtual_address_max = |
| 906 | 906 | min(vm_size, AMDGPU_GMC_HOLE_START); |
| 907 | 907 | |
| @@ -1114,6 +1114,15 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) · 206 unmodified lines | ||
| 1114 | 1114 | } |
| 1115 | 1115 | ui32 >>= 8; |
| 1116 | 1116 | break; |
| 1117 | + case AMDGPU_INFO_SENSOR_GPU_INPUT_POWER: | |
| 1118 | + /* get input GPU power */ | |
| 1119 | + if (amdgpu_dpm_read_sensor(adev, | |
| 1120 | + AMDGPU_PP_SENSOR_GPU_INPUT_POWER, | |
| 1121 | + (void *)&ui32, &ui32_size)) { | |
| 1122 | + return -EINVAL; | |
| 1123 | + } | |
| 1124 | + ui32 >>= 8; | |
| 1125 | + break; | |
| 1117 | 1126 | case AMDGPU_INFO_SENSOR_VDDNB: |
| 1118 | 1127 | /* get VDDNB in millivolts */ |
| 1119 | 1128 | if (amdgpu_dpm_read_sensor(adev, |
| @@ -1370,6 +1379,10 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) · 250 unmodified lines | ||
| 1370 | 1379 | goto error_vm; |
| 1371 | 1380 | } |
| 1372 | 1381 | |
| 1382 | + r = amdgpu_seq64_map(adev, &fpriv->vm, &fpriv->seq64_va); | |
| 1383 | + if (r) | |
| 1384 | + goto error_vm; | |
| 1385 | + | |
| 1373 | 1386 | mutex_init(&fpriv->bo_list_lock); |
| 1374 | 1387 | idr_init_base(&fpriv->bo_list_handles, 1); |
| 1375 | 1388 | |
| @@ -27,6 +27,16 @@ · 26 unmodified lines | ||
| 27 | 27 | #include "umc/umc_6_7_0_offset.h" |
| 28 | 28 | #include "umc/umc_6_7_0_sh_mask.h" |
| 29 | 29 | |
| 30 | +static bool amdgpu_mca_is_deferred_error(struct amdgpu_device *adev, | |
| 31 | + uint64_t mc_status) | |
| 32 | +{ | |
| 33 | + if (adev->umc.ras->check_ecc_err_status) | |
| 34 | + return adev->umc.ras->check_ecc_err_status(adev, | |
| 35 | + AMDGPU_MCA_ERROR_TYPE_DE, &mc_status); | |
| 36 | + | |
| 37 | + return false; | |
| 38 | +} | |
| 39 | + | |
| 30 | 40 | void amdgpu_mca_query_correctable_error_count(struct amdgpu_device *adev, |
| 31 | 41 | uint64_t mc_status_addr, |
| 32 | 42 | unsigned long *error_count) |
| @@ -202,16 +212,16 @@ int amdgpu_mca_smu_set_debug_mode(struct amdgpu_device *adev, bool enable) · 169 unmodified lines | ||
| 202 | 212 | |
| 203 | 213 | static void amdgpu_mca_smu_mca_bank_dump(struct amdgpu_device *adev, int idx, struct mca_bank_entry *entry) |
| 204 | 214 | { |
| 205 | − dev_info(adev->dev, "[Hardware error] Accelerator Check Architecture events logged\n"); | |
| 206 | − dev_info(adev->dev, "[Hardware error] aca entry[%02d].STATUS=0x%016llx\n", | |
| 215 | + dev_info(adev->dev, HW_ERR "Accelerator Check Architecture events logged\n"); | |
| 216 | + dev_info(adev->dev, HW_ERR "aca entry[%02d].STATUS=0x%016llx\n", | |
| 207 | 217 | idx, entry->regs[MCA_REG_IDX_STATUS]); |
| 208 | − dev_info(adev->dev, "[Hardware error] aca entry[%02d].ADDR=0x%016llx\n", | |
| 218 | + dev_info(adev->dev, HW_ERR "aca entry[%02d].ADDR=0x%016llx\n", | |
| 209 | 219 | idx, entry->regs[MCA_REG_IDX_ADDR]); |
| 210 | − dev_info(adev->dev, "[Hardware error] aca entry[%02d].MISC0=0x%016llx\n", | |
| 220 | + dev_info(adev->dev, HW_ERR "aca entry[%02d].MISC0=0x%016llx\n", | |
| 211 | 221 | idx, entry->regs[MCA_REG_IDX_MISC0]); |
| 212 | − dev_info(adev->dev, "[Hardware error] aca entry[%02d].IPID=0x%016llx\n", | |
| 222 | + dev_info(adev->dev, HW_ERR "aca entry[%02d].IPID=0x%016llx\n", | |
| 213 | 223 | idx, entry->regs[MCA_REG_IDX_IPID]); |
| 214 | − dev_info(adev->dev, "[Hardware error] aca entry[%02d].SYND=0x%016llx\n", | |
| 224 | + dev_info(adev->dev, HW_ERR "aca entry[%02d].SYND=0x%016llx\n", | |
| 215 | 225 | idx, entry->regs[MCA_REG_IDX_SYND]); |
| 216 | 226 | } |
| 217 | 227 | |
| @@ -256,9 +266,14 @@ int amdgpu_mca_smu_log_ras_error(struct amdgpu_device *adev, enum amdgpu_ras_blo · 38 unmodified lines | ||
| 256 | 266 | if (type == AMDGPU_MCA_ERROR_TYPE_UE) |
| 257 | 267 | amdgpu_ras_error_statistic_ue_count(err_data, |
| 258 | 268 | &mcm_info, &err_addr, (uint64_t)count); |
| 259 | − else | |
| 260 | − amdgpu_ras_error_statistic_ce_count(err_data, | |
| 261 | − &mcm_info, &err_addr, (uint64_t)count); | |
| 269 | + else { | |
| 270 | + if (amdgpu_mca_is_deferred_error(adev, entry->regs[MCA_REG_IDX_STATUS])) | |
| 271 | + amdgpu_ras_error_statistic_de_count(err_data, | |
| 272 | + &mcm_info, &err_addr, (uint64_t)count); | |
| 273 | + else | |
| 274 | + amdgpu_ras_error_statistic_ce_count(err_data, | |
| 275 | + &mcm_info, &err_addr, (uint64_t)count); | |
| 276 | + } | |
| 262 | 277 | } |
| 263 | 278 | |
| 264 | 279 | out_mca_release: |
| @@ -65,6 +65,7 @@ enum amdgpu_mca_ip { · 64 unmodified lines | ||
| 65 | 65 | enum amdgpu_mca_error_type { |
| 66 | 66 | AMDGPU_MCA_ERROR_TYPE_UE = 0, |
| 67 | 67 | AMDGPU_MCA_ERROR_TYPE_CE, |
| 68 | + AMDGPU_MCA_ERROR_TYPE_DE, | |
| 68 | 69 | }; |
| 69 | 70 | |
| 70 | 71 | struct amdgpu_mca_ras_block { |
| @@ -1398,7 +1398,7 @@ int amdgpu_mes_self_test(struct amdgpu_device *adev) · 1397 unmodified lines | ||
| 1398 | 1398 | goto error_fini; |
| 1399 | 1399 | } |
| 1400 | 1400 | |
| 1401 | − ctx_data.meta_data_gpu_addr = AMDGPU_VA_RESERVED_SIZE; | |
| 1401 | + ctx_data.meta_data_gpu_addr = AMDGPU_VA_RESERVED_BOTTOM; | |
| 1402 | 1402 | r = amdgpu_mes_ctx_map_meta_data(adev, vm, &ctx_data); |
| 1403 | 1403 | if (r) { |
| 1404 | 1404 | DRM_ERROR("failed to map ctx meta data\n"); |
| @@ -1565,9 +1565,9 @@ void amdgpu_debugfs_mes_event_log_init(struct amdgpu_device *adev) · 160 unmodified lines | ||
| 1565 | 1565 | #if defined(CONFIG_DEBUG_FS) |
| 1566 | 1566 | struct drm_minor *minor = adev_to_drm(adev)->primary; |
| 1567 | 1567 | struct dentry *root = minor->debugfs_root; |
| 1568 | − | |
| 1569 | − debugfs_create_file("amdgpu_mes_event_log", 0444, root, | |
| 1570 | − adev, &amdgpu_debugfs_mes_event_log_fops); | |
| 1568 | + if (adev->enable_mes) | |
| 1569 | + debugfs_create_file("amdgpu_mes_event_log", 0444, root, | |
| 1570 | + adev, &amdgpu_debugfs_mes_event_log_fops); | |
| 1571 | 1571 | |
| 1572 | 1572 | #endif |
| 1573 | 1573 | } |
| @@ -220,9 +220,6 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) · 219 unmodified lines | ||
| 220 | 220 | |
| 221 | 221 | placement->num_placement = c; |
| 222 | 222 | placement->placement = places; |
| 223 | − | |
| 224 | − placement->num_busy_placement = c; | |
| 225 | − placement->busy_placement = places; | |
| 226 | 223 | } |
| 227 | 224 | |
| 228 | 225 | /** |
| @@ -1397,8 +1394,7 @@ vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo) · 1168 unmodified lines | ||
| 1397 | 1394 | AMDGPU_GEM_DOMAIN_GTT); |
| 1398 | 1395 | |
| 1399 | 1396 | /* Avoid costly evictions; only set GTT as a busy placement */ |
| 1400 | − abo->placement.num_busy_placement = 1; | |
| 1401 | − abo->placement.busy_placement = &abo->placements[1]; | |
| 1397 | + abo->placements[0].flags |= TTM_PL_FLAG_DESIRED; | |
| 1402 | 1398 | |
| 1403 | 1399 | r = ttm_bo_validate(bo, &abo->placement, &ctx); |
| 1404 | 1400 | if (unlikely(r == -EBUSY || r == -ERESTARTSYS)) |
| @@ -291,21 +291,22 @@ static int psp_memory_training_init(struct psp_context *psp) · 290 unmodified lines | ||
| 291 | 291 | struct psp_memory_training_context *ctx = &psp->mem_train_ctx; |
| 292 | 292 | |
| 293 | 293 | if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { |
| 294 | − DRM_DEBUG("memory training is not supported!\n"); | |
| 294 | + dev_dbg(psp->adev->dev, "memory training is not supported!\n"); | |
| 295 | 295 | return 0; |
| 296 | 296 | } |
| 297 | 297 | |
| 298 | 298 | ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); |
| 299 | 299 | if (ctx->sys_cache == NULL) { |
| 300 | − DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n"); | |
| 300 | + dev_err(psp->adev->dev, "alloc mem_train_ctx.sys_cache failed!\n"); | |
| 301 | 301 | ret = -ENOMEM; |
| 302 | 302 | goto Err_out; |
| 303 | 303 | } |
| 304 | 304 | |
| 305 | − DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", | |
| 306 | − ctx->train_data_size, | |
| 307 | − ctx->p2c_train_data_offset, | |
| 308 | − ctx->c2p_train_data_offset); | |
| 305 | + dev_dbg(psp->adev->dev, | |
| 306 | + "train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", | |
| 307 | + ctx->train_data_size, | |
| 308 | + ctx->p2c_train_data_offset, | |
| 309 | + ctx->c2p_train_data_offset); | |
| 309 | 310 | ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; |
| 310 | 311 | return 0; |
| 311 | 312 | |
| @@ -407,7 +408,7 @@ static int psp_sw_init(void *handle) · 95 unmodified lines | ||
| 407 | 408 | |
| 408 | 409 | psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); |
| 409 | 410 | if (!psp->cmd) { |
| 410 | − DRM_ERROR("Failed to allocate memory to command buffer!\n"); | |
| 411 | + dev_err(adev->dev, "Failed to allocate memory to command buffer!\n"); | |
| 411 | 412 | ret = -ENOMEM; |
| 412 | 413 | } |
| 413 | 414 | |
| @@ -454,13 +455,13 @@ static int psp_sw_init(void *handle) · 40 unmodified lines | ||
| 454 | 455 | if (mem_training_ctx->enable_mem_training) { |
| 455 | 456 | ret = psp_memory_training_init(psp); |
| 456 | 457 | if (ret) { |
| 457 | − DRM_ERROR("Failed to initialize memory training!\n"); | |
| 458 | + dev_err(adev->dev, "Failed to initialize memory training!\n"); | |
| 458 | 459 | return ret; |
| 459 | 460 | } |
| 460 | 461 | |
| 461 | 462 | ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); |
| 462 | 463 | if (ret) { |
| 463 | − DRM_ERROR("Failed to process memory training!\n"); | |
| 464 | + dev_err(adev->dev, "Failed to process memory training!\n"); | |
| 464 | 465 | return ret; |
| 465 | 466 | } |
| 466 | 467 | } |
| @@ -675,9 +676,11 @@ psp_cmd_submit_buf(struct psp_context *psp, · 208 unmodified lines | ||
| 675 | 676 | */ |
| 676 | 677 | if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { |
| 677 | 678 | if (ucode) |
| 678 | − DRM_WARN("failed to load ucode %s(0x%X) ", | |
| 679 | − amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id); | |
| 680 | − DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n", | |
| 679 | + dev_warn(psp->adev->dev, | |
| 680 | + "failed to load ucode %s(0x%X) ", | |
| 681 | + amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id); | |
| 682 | + dev_warn(psp->adev->dev, | |
| 683 | + "psp gfx command %s(0x%X) failed and response status is (0x%X)\n", | |
| 681 | 684 | psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id, |
| 682 | 685 | psp->cmd_buf_mem->resp.status); |
| 683 | 686 | /* If any firmware (including CAP) load fails under SRIOV, it should |
| @@ -807,7 +810,7 @@ static int psp_tmr_init(struct psp_context *psp) · 123 unmodified lines | ||
| 807 | 810 | psp->fw_pri_buf) { |
| 808 | 811 | ret = psp_load_toc(psp, &tmr_size); |
| 809 | 812 | if (ret) { |
| 810 | − DRM_ERROR("Failed to load toc\n"); | |
| 813 | + dev_err(psp->adev->dev, "Failed to load toc\n"); | |
| 811 | 814 | return ret; |
| 812 | 815 | } |
| 813 | 816 | } |
| @@ -855,7 +858,7 @@ static int psp_tmr_load(struct psp_context *psp) · 41 unmodified lines | ||
| 855 | 858 | |
| 856 | 859 | psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); |
| 857 | 860 | if (psp->tmr_bo) |
| 858 | − DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n", | |
| 861 | + dev_info(psp->adev->dev, "reserve 0x%lx from 0x%llx for PSP TMR\n", | |
| 859 | 862 | amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); |
| 860 | 863 | |
| 861 | 864 | ret = psp_cmd_submit_buf(psp, NULL, cmd, |
| @@ -1113,7 +1116,7 @@ int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, · 251 unmodified lines | ||
| 1113 | 1116 | psp_prep_reg_prog_cmd_buf(cmd, reg, value); |
| 1114 | 1117 | ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); |
| 1115 | 1118 | if (ret) |
| 1116 | − DRM_ERROR("PSP failed to program reg id %d", reg); | |
| 1119 | + dev_err(psp->adev->dev, "PSP failed to program reg id %d\n", reg); | |
| 1117 | 1120 | |
| 1118 | 1121 | release_psp_cmd_buf(psp); |
| 1119 | 1122 | |
| @@ -1526,22 +1529,22 @@ static void psp_ras_ta_check_status(struct psp_context *psp) · 406 unmodified lines | ||
| 1526 | 1529 | switch (ras_cmd->ras_status) { |
| 1527 | 1530 | case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP: |
| 1528 | 1531 | dev_warn(psp->adev->dev, |
| 1529 | − "RAS WARNING: cmd failed due to unsupported ip\n"); | |
| 1532 | + "RAS WARNING: cmd failed due to unsupported ip\n"); | |
| 1530 | 1533 | break; |
| 1531 | 1534 | case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ: |
| 1532 | 1535 | dev_warn(psp->adev->dev, |
| 1533 | − "RAS WARNING: cmd failed due to unsupported error injection\n"); | |
| 1536 | + "RAS WARNING: cmd failed due to unsupported error injection\n"); | |
| 1534 | 1537 | break; |
| 1535 | 1538 | case TA_RAS_STATUS__SUCCESS: |
| 1536 | 1539 | break; |
| 1537 | 1540 | case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED: |
| 1538 | 1541 | if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR) |
| 1539 | 1542 | dev_warn(psp->adev->dev, |
| 1540 | − "RAS WARNING: Inject error to critical region is not allowed\n"); | |
| 1543 | + "RAS WARNING: Inject error to critical region is not allowed\n"); | |
| 1541 | 1544 | break; |
| 1542 | 1545 | default: |
| 1543 | 1546 | dev_warn(psp->adev->dev, |
| 1544 | − "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status); | |
| 1547 | + "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status); | |
| 1545 | 1548 | break; |
| 1546 | 1549 | } |
| 1547 | 1550 | } |
| @@ -1565,7 +1568,7 @@ int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) · 17 unmodified lines | ||
| 1565 | 1568 | return ret; |
| 1566 | 1569 | |
| 1567 | 1570 | if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) { |
| 1568 | − DRM_WARN("RAS: Unsupported Interface"); | |
| 1571 | + dev_warn(psp->adev->dev, "RAS: Unsupported Interface\n"); | |
| 1569 | 1572 | return -EINVAL; |
| 1570 | 1573 | } |
| 1571 | 1574 | |
| @@ -1715,7 +1718,7 @@ int psp_ras_initialize(struct psp_context *psp) · 143 unmodified lines | ||
| 1715 | 1718 | psp->ras_context.context.initialized = true; |
| 1716 | 1719 | else { |
| 1717 | 1720 | if (ras_cmd->ras_status) |
| 1718 | − dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); | |
| 1721 | + dev_warn(adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); | |
| 1719 | 1722 | |
| 1720 | 1723 | /* fail to load RAS TA */ |
| 1721 | 1724 | psp->ras_context.context.initialized = false; |
| @@ -1779,6 +1782,31 @@ int psp_ras_trigger_error(struct psp_context *psp, · 57 unmodified lines | ||
| 1779 | 1782 | |
| 1780 | 1783 | return 0; |
| 1781 | 1784 | } |
| 1785 | + | |
| 1786 | +int psp_ras_query_address(struct psp_context *psp, | |
| 1787 | + struct ta_ras_query_address_input *addr_in, | |
| 1788 | + struct ta_ras_query_address_output *addr_out) | |
| 1789 | +{ | |
| 1790 | + struct ta_ras_shared_memory *ras_cmd; | |
| 1791 | + int ret; | |
| 1792 | + | |
| 1793 | + if (!psp->ras_context.context.initialized) | |
| 1794 | + return -EINVAL; | |
| 1795 | + | |
| 1796 | + ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; | |
| 1797 | + memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); | |
| 1798 | + | |
| 1799 | + ras_cmd->cmd_id = TA_RAS_COMMAND__QUERY_ADDRESS; | |
| 1800 | + ras_cmd->ras_in_message.address = *addr_in; | |
| 1801 | + | |
| 1802 | + ret = psp_ras_invoke(psp, ras_cmd->cmd_id); | |
| 1803 | + if (ret || ras_cmd->ras_status || psp->cmd_buf_mem->resp.status) | |
| 1804 | + return -EINVAL; | |
| 1805 | + | |
| 1806 | + *addr_out = ras_cmd->ras_out_message.address; | |
| 1807 | + | |
| 1808 | + return 0; | |
| 1809 | +} | |
| 1782 | 1810 | // ras end |
| 1783 | 1811 | |
| 1784 | 1812 | // HDCP start |
| @@ -2125,19 +2153,14 @@ int amdgpu_psp_wait_for_bootloader(struct amdgpu_device *adev) · 340 unmodified lines | ||
| 2125 | 2153 | return ret; |
| 2126 | 2154 | } |
| 2127 | 2155 | |
| 2128 | −int amdgpu_psp_query_boot_status(struct amdgpu_device *adev) | |
| 2156 | +bool amdgpu_psp_get_ras_capability(struct psp_context *psp) | |
| 2129 | 2157 | { |
| 2130 | − struct psp_context *psp = &adev->psp; | |
| 2131 | − int ret = 0; | |
| 2132 | − | |
| 2133 | − if (amdgpu_sriov_vf(adev) || (adev->flags & AMD_IS_APU)) | |
| 2134 | − return 0; | |
| 2135 | − | |
| 2136 | 2158 | if (psp->funcs && |
| 2137 | − psp->funcs->query_boot_status) | |
| 2138 | − ret = psp->funcs->query_boot_status(psp); | |
| 2139 | − | |
| 2140 | − return ret; | |
| 2159 | + psp->funcs->get_ras_capability) { | |
| 2160 | + return psp->funcs->get_ras_capability(psp); | |
| 2161 | + } else { | |
| 2162 | + return false; | |
| 2163 | + } | |
| 2141 | 2164 | } |
| 2142 | 2165 | |
| 2143 | 2166 | static int psp_hw_start(struct psp_context *psp) |
| @@ -2150,7 +2173,7 @@ static int psp_hw_start(struct psp_context *psp) · 6 unmodified lines | ||
| 2150 | 2173 | (psp->funcs->bootloader_load_kdb != NULL)) { |
| 2151 | 2174 | ret = psp_bootloader_load_kdb(psp); |
| 2152 | 2175 | if (ret) { |
| 2153 | − DRM_ERROR("PSP load kdb failed!\n"); | |
| 2176 | + dev_err(adev->dev, "PSP load kdb failed!\n"); | |
| 2154 | 2177 | return ret; |
| 2155 | 2178 | } |
| 2156 | 2179 | } |
| @@ -2159,7 +2182,7 @@ static int psp_hw_start(struct psp_context *psp) · 2 unmodified lines | ||
| 2159 | 2182 | (psp->funcs->bootloader_load_spl != NULL)) { |
| 2160 | 2183 | ret = psp_bootloader_load_spl(psp); |
| 2161 | 2184 | if (ret) { |
| 2162 | − DRM_ERROR("PSP load spl failed!\n"); | |
| 2185 | + dev_err(adev->dev, "PSP load spl failed!\n"); | |
| 2163 | 2186 | return ret; |
| 2164 | 2187 | } |
| 2165 | 2188 | } |
| @@ -2168,7 +2191,7 @@ static int psp_hw_start(struct psp_context *psp) · 2 unmodified lines | ||
| 2168 | 2191 | (psp->funcs->bootloader_load_sysdrv != NULL)) { |
| 2169 | 2192 | ret = psp_bootloader_load_sysdrv(psp); |
| 2170 | 2193 | if (ret) { |
| 2171 | − DRM_ERROR("PSP load sys drv failed!\n"); | |
| 2194 | + dev_err(adev->dev, "PSP load sys drv failed!\n"); | |
| 2172 | 2195 | return ret; |
| 2173 | 2196 | } |
| 2174 | 2197 | } |
| @@ -2177,7 +2200,7 @@ static int psp_hw_start(struct psp_context *psp) · 2 unmodified lines | ||
| 2177 | 2200 | (psp->funcs->bootloader_load_soc_drv != NULL)) { |
| 2178 | 2201 | ret = psp_bootloader_load_soc_drv(psp); |
| 2179 | 2202 | if (ret) { |
| 2180 | − DRM_ERROR("PSP load soc drv failed!\n"); | |
| 2203 | + dev_err(adev->dev, "PSP load soc drv failed!\n"); | |
| 2181 | 2204 | return ret; |
| 2182 | 2205 | } |
| 2183 | 2206 | } |
| @@ -2186,7 +2209,7 @@ static int psp_hw_start(struct psp_context *psp) · 2 unmodified lines | ||
| 2186 | 2209 | (psp->funcs->bootloader_load_intf_drv != NULL)) { |
| 2187 | 2210 | ret = psp_bootloader_load_intf_drv(psp); |
| 2188 | 2211 | if (ret) { |
| 2189 | − DRM_ERROR("PSP load intf drv failed!\n"); | |
| 2212 | + dev_err(adev->dev, "PSP load intf drv failed!\n"); | |
| 2190 | 2213 | return ret; |
| 2191 | 2214 | } |
| 2192 | 2215 | } |
| @@ -2195,7 +2218,7 @@ static int psp_hw_start(struct psp_context *psp) · 2 unmodified lines | ||
| 2195 | 2218 | (psp->funcs->bootloader_load_dbg_drv != NULL)) { |
| 2196 | 2219 | ret = psp_bootloader_load_dbg_drv(psp); |
| 2197 | 2220 | if (ret) { |
| 2198 | − DRM_ERROR("PSP load dbg drv failed!\n"); | |
| 2221 | + dev_err(adev->dev, "PSP load dbg drv failed!\n"); | |
| 2199 | 2222 | return ret; |
| 2200 | 2223 | } |
| 2201 | 2224 | } |
| @@ -2204,7 +2227,7 @@ static int psp_hw_start(struct psp_context *psp) · 2 unmodified lines | ||
| 2204 | 2227 | (psp->funcs->bootloader_load_ras_drv != NULL)) { |
| 2205 | 2228 | ret = psp_bootloader_load_ras_drv(psp); |
| 2206 | 2229 | if (ret) { |
| 2207 | − DRM_ERROR("PSP load ras_drv failed!\n"); | |
| 2230 | + dev_err(adev->dev, "PSP load ras_drv failed!\n"); | |
| 2208 | 2231 | return ret; |
| 2209 | 2232 | } |
| 2210 | 2233 | } |
| @@ -2213,7 +2236,7 @@ static int psp_hw_start(struct psp_context *psp) · 2 unmodified lines | ||
| 2213 | 2236 | (psp->funcs->bootloader_load_sos != NULL)) { |
| 2214 | 2237 | ret = psp_bootloader_load_sos(psp); |
| 2215 | 2238 | if (ret) { |
| 2216 | − DRM_ERROR("PSP load sos failed!\n"); | |
| 2239 | + dev_err(adev->dev, "PSP load sos failed!\n"); | |
| 2217 | 2240 | return ret; |
| 2218 | 2241 | } |
| 2219 | 2242 | } |
| @@ -2221,7 +2244,7 @@ static int psp_hw_start(struct psp_context *psp) · 1 unmodified line | ||
| 2221 | 2244 | |
| 2222 | 2245 | ret = psp_ring_create(psp, PSP_RING_TYPE__KM); |
| 2223 | 2246 | if (ret) { |
| 2224 | − DRM_ERROR("PSP create ring failed!\n"); | |
| 2247 | + dev_err(adev->dev, "PSP create ring failed!\n"); | |
| 2225 | 2248 | return ret; |
| 2226 | 2249 | } |
| 2227 | 2250 | |
| @@ -2231,7 +2254,7 @@ static int psp_hw_start(struct psp_context *psp) · 3 unmodified lines | ||
| 2231 | 2254 | if (!psp_boottime_tmr(psp)) { |
| 2232 | 2255 | ret = psp_tmr_init(psp); |
| 2233 | 2256 | if (ret) { |
| 2234 | − DRM_ERROR("PSP tmr init failed!\n"); | |
| 2257 | + dev_err(adev->dev, "PSP tmr init failed!\n"); | |
| 2235 | 2258 | return ret; |
| 2236 | 2259 | } |
| 2237 | 2260 | } |
| @@ -2250,7 +2273,7 @@ skip_pin_bo: · 12 unmodified lines | ||
| 2250 | 2273 | |
| 2251 | 2274 | ret = psp_tmr_load(psp); |
| 2252 | 2275 | if (ret) { |
| 2253 | − DRM_ERROR("PSP load tmr failed!\n"); | |
| 2276 | + dev_err(adev->dev, "PSP load tmr failed!\n"); | |
| 2254 | 2277 | return ret; |
| 2255 | 2278 | } |
| 2256 | 2279 | |
| @@ -2518,7 +2541,8 @@ static void psp_print_fw_hdr(struct psp_context *psp, · 261 unmodified lines | ||
| 2518 | 2541 | } |
| 2519 | 2542 | } |
| 2520 | 2543 | |
| 2521 | −static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, | |
| 2544 | +static int psp_prep_load_ip_fw_cmd_buf(struct psp_context *psp, | |
| 2545 | + struct amdgpu_firmware_info *ucode, | |
| 2522 | 2546 | struct psp_gfx_cmd_resp *cmd) |
| 2523 | 2547 | { |
| 2524 | 2548 | int ret; |
| @@ -2531,7 +2555,7 @@ static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, · 6 unmodified lines | ||
| 2531 | 2555 | |
| 2532 | 2556 | ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); |
| 2533 | 2557 | if (ret) |
| 2534 | − DRM_ERROR("Unknown firmware type\n"); | |
| 2558 | + dev_err(psp->adev->dev, "Unknown firmware type\n"); | |
| 2535 | 2559 | |
| 2536 | 2560 | return ret; |
| 2537 | 2561 | } |
| @@ -2542,7 +2566,7 @@ int psp_execute_ip_fw_load(struct psp_context *psp, · 4 unmodified lines | ||
| 2542 | 2566 | int ret = 0; |
| 2543 | 2567 | struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); |
| 2544 | 2568 | |
| 2545 | − ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd); | |
| 2569 | + ret = psp_prep_load_ip_fw_cmd_buf(psp, ucode, cmd); | |
| 2546 | 2570 | if (!ret) { |
| 2547 | 2571 | ret = psp_cmd_submit_buf(psp, ucode, cmd, |
| 2548 | 2572 | psp->fence_buf_mc_addr); |
| @@ -2601,13 +2625,13 @@ static int psp_load_smu_fw(struct psp_context *psp) · 52 unmodified lines | ||
| 2601 | 2625 | amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 2)))) { |
| 2602 | 2626 | ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); |
| 2603 | 2627 | if (ret) |
| 2604 | − DRM_WARN("Failed to set MP1 state prepare for reload\n"); | |
| 2628 | + dev_err(adev->dev, "Failed to set MP1 state prepare for reload\n"); | |
| 2605 | 2629 | } |
| 2606 | 2630 | |
| 2607 | 2631 | ret = psp_execute_ip_fw_load(psp, ucode); |
| 2608 | 2632 | |
| 2609 | 2633 | if (ret) |
| 2610 | − DRM_ERROR("PSP load smu failed!\n"); | |
| 2634 | + dev_err(adev->dev, "PSP load smu failed!\n"); | |
| 2611 | 2635 | |
| 2612 | 2636 | return ret; |
| 2613 | 2637 | } |
| @@ -2712,7 +2736,7 @@ static int psp_load_non_psp_fw(struct psp_context *psp) · 98 unmodified lines | ||
| 2712 | 2736 | adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) { |
| 2713 | 2737 | ret = psp_rlc_autoload_start(psp); |
| 2714 | 2738 | if (ret) { |
| 2715 | − DRM_ERROR("Failed to start rlc autoload\n"); | |
| 2739 | + dev_err(adev->dev, "Failed to start rlc autoload\n"); | |
| 2716 | 2740 | return ret; |
| 2717 | 2741 | } |
| 2718 | 2742 | } |
| @@ -2734,7 +2758,7 @@ static int psp_load_fw(struct amdgpu_device *adev) · 15 unmodified lines | ||
| 2734 | 2758 | |
| 2735 | 2759 | ret = psp_ring_init(psp, PSP_RING_TYPE__KM); |
| 2736 | 2760 | if (ret) { |
| 2737 | − DRM_ERROR("PSP ring init failed!\n"); | |
| 2761 | + dev_err(adev->dev, "PSP ring init failed!\n"); | |
| 2738 | 2762 | goto failed; |
| 2739 | 2763 | } |
| 2740 | 2764 | } |
| @@ -2749,13 +2773,13 @@ static int psp_load_fw(struct amdgpu_device *adev) · 8 unmodified lines | ||
| 2749 | 2773 | |
| 2750 | 2774 | ret = psp_asd_initialize(psp); |
| 2751 | 2775 | if (ret) { |
| 2752 | − DRM_ERROR("PSP load asd failed!\n"); | |
| 2776 | + dev_err(adev->dev, "PSP load asd failed!\n"); | |
| 2753 | 2777 | goto failed1; |
| 2754 | 2778 | } |
| 2755 | 2779 | |
| 2756 | 2780 | ret = psp_rl_load(adev); |
| 2757 | 2781 | if (ret) { |
| 2758 | − DRM_ERROR("PSP load RL failed!\n"); | |
| 2782 | + dev_err(adev->dev, "PSP load RL failed!\n"); | |
| 2759 | 2783 | goto failed1; |
| 2760 | 2784 | } |
| 2761 | 2785 | |
| @@ -2775,7 +2799,7 @@ static int psp_load_fw(struct amdgpu_device *adev) · 13 unmodified lines | ||
| 2775 | 2799 | ret = psp_ras_initialize(psp); |
| 2776 | 2800 | if (ret) |
| 2777 | 2801 | dev_err(psp->adev->dev, |
| 2778 | − "RAS: Failed to initialize RAS\n"); | |
| 2802 | + "RAS: Failed to initialize RAS\n"); | |
| 2779 | 2803 | |
| 2780 | 2804 | ret = psp_hdcp_initialize(psp); |
| 2781 | 2805 | if (ret) |
| @@ -2828,7 +2852,7 @@ static int psp_hw_init(void *handle) · 46 unmodified lines | ||
| 2828 | 2852 | |
| 2829 | 2853 | ret = psp_load_fw(adev); |
| 2830 | 2854 | if (ret) { |
| 2831 | − DRM_ERROR("PSP firmware loading failed\n"); | |
| 2855 | + dev_err(adev->dev, "PSP firmware loading failed\n"); | |
| 2832 | 2856 | goto failed; |
| 2833 | 2857 | } |
| 2834 | 2858 | |
| @@ -2875,7 +2899,7 @@ static int psp_suspend(void *handle) · 40 unmodified lines | ||
| 2875 | 2899 | psp->xgmi_context.context.initialized) { |
| 2876 | 2900 | ret = psp_xgmi_terminate(psp); |
| 2877 | 2901 | if (ret) { |
| 2878 | − DRM_ERROR("Failed to terminate xgmi ta\n"); | |
| 2902 | + dev_err(adev->dev, "Failed to terminate xgmi ta\n"); | |
| 2879 | 2903 | goto out; |
| 2880 | 2904 | } |
| 2881 | 2905 | } |
| @@ -2883,46 +2907,46 @@ static int psp_suspend(void *handle) · 1 unmodified line | ||
| 2883 | 2907 | if (psp->ta_fw) { |
| 2884 | 2908 | ret = psp_ras_terminate(psp); |
| 2885 | 2909 | if (ret) { |
| 2886 | − DRM_ERROR("Failed to terminate ras ta\n"); | |
| 2910 | + dev_err(adev->dev, "Failed to terminate ras ta\n"); | |
| 2887 | 2911 | goto out; |
| 2888 | 2912 | } |
| 2889 | 2913 | ret = psp_hdcp_terminate(psp); |
| 2890 | 2914 | if (ret) { |
| 2891 | − DRM_ERROR("Failed to terminate hdcp ta\n"); | |
| 2915 | + dev_err(adev->dev, "Failed to terminate hdcp ta\n"); | |
| 2892 | 2916 | goto out; |
| 2893 | 2917 | } |
| 2894 | 2918 | ret = psp_dtm_terminate(psp); |
| 2895 | 2919 | if (ret) { |
| 2896 | − DRM_ERROR("Failed to terminate dtm ta\n"); | |
| 2920 | + dev_err(adev->dev, "Failed to terminate dtm ta\n"); | |
| 2897 | 2921 | goto out; |
| 2898 | 2922 | } |
| 2899 | 2923 | ret = psp_rap_terminate(psp); |
| 2900 | 2924 | if (ret) { |
| 2901 | − DRM_ERROR("Failed to terminate rap ta\n"); | |
| 2925 | + dev_err(adev->dev, "Failed to terminate rap ta\n"); | |
| 2902 | 2926 | goto out; |
| 2903 | 2927 | } |
| 2904 | 2928 | ret = psp_securedisplay_terminate(psp); |
| 2905 | 2929 | if (ret) { |
| 2906 | − DRM_ERROR("Failed to terminate securedisplay ta\n"); | |
| 2930 | + dev_err(adev->dev, "Failed to terminate securedisplay ta\n"); | |
| 2907 | 2931 | goto out; |
| 2908 | 2932 | } |
| 2909 | 2933 | } |
| 2910 | 2934 | |
| 2911 | 2935 | ret = psp_asd_terminate(psp); |
| 2912 | 2936 | if (ret) { |
| 2913 | − DRM_ERROR("Failed to terminate asd\n"); | |
| 2937 | + dev_err(adev->dev, "Failed to terminate asd\n"); | |
| 2914 | 2938 | goto out; |
| 2915 | 2939 | } |
| 2916 | 2940 | |
| 2917 | 2941 | ret = psp_tmr_terminate(psp); |
| 2918 | 2942 | if (ret) { |
| 2919 | − DRM_ERROR("Failed to terminate tmr\n"); | |
| 2943 | + dev_err(adev->dev, "Failed to terminate tmr\n"); | |
| 2920 | 2944 | goto out; |
| 2921 | 2945 | } |
| 2922 | 2946 | |
| 2923 | 2947 | ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); |
| 2924 | 2948 | if (ret) |
| 2925 | − DRM_ERROR("PSP ring stop failed\n"); | |
| 2949 | + dev_err(adev->dev, "PSP ring stop failed\n"); | |
| 2926 | 2950 | |
| 2927 | 2951 | out: |
| 2928 | 2952 | return ret; |
| @@ -2934,12 +2958,12 @@ static int psp_resume(void *handle) · 5 unmodified lines | ||
| 2934 | 2958 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 2935 | 2959 | struct psp_context *psp = &adev->psp; |
| 2936 | 2960 | |
| 2937 | − DRM_INFO("PSP is resuming...\n"); | |
| 2961 | + dev_info(adev->dev, "PSP is resuming...\n"); | |
| 2938 | 2962 | |
| 2939 | 2963 | if (psp->mem_train_ctx.enable_mem_training) { |
| 2940 | 2964 | ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); |
| 2941 | 2965 | if (ret) { |
| 2942 | − DRM_ERROR("Failed to process memory training!\n"); | |
| 2966 | + dev_err(adev->dev, "Failed to process memory training!\n"); | |
| 2943 | 2967 | return ret; |
| 2944 | 2968 | } |
| 2945 | 2969 | } |
| @@ -2956,7 +2980,7 @@ static int psp_resume(void *handle) · 10 unmodified lines | ||
| 2956 | 2980 | |
| 2957 | 2981 | ret = psp_asd_initialize(psp); |
| 2958 | 2982 | if (ret) { |
| 2959 | − DRM_ERROR("PSP load asd failed!\n"); | |
| 2983 | + dev_err(adev->dev, "PSP load asd failed!\n"); | |
| 2960 | 2984 | goto failed; |
| 2961 | 2985 | } |
| 2962 | 2986 | |
| @@ -2980,7 +3004,7 @@ static int psp_resume(void *handle) · 17 unmodified lines | ||
| 2980 | 3004 | ret = psp_ras_initialize(psp); |
| 2981 | 3005 | if (ret) |
| 2982 | 3006 | dev_err(psp->adev->dev, |
| 2983 | − "RAS: Failed to initialize RAS\n"); | |
| 3007 | + "RAS: Failed to initialize RAS\n"); | |
| 2984 | 3008 | |
| 2985 | 3009 | ret = psp_hdcp_initialize(psp); |
| 2986 | 3010 | if (ret) |
| @@ -3008,7 +3032,7 @@ static int psp_resume(void *handle) · 21 unmodified lines | ||
| 3008 | 3032 | return 0; |
| 3009 | 3033 | |
| 3010 | 3034 | failed: |
| 3011 | − DRM_ERROR("PSP resume failed\n"); | |
| 3035 | + dev_err(adev->dev, "PSP resume failed\n"); | |
| 3012 | 3036 | mutex_unlock(&adev->firmware.mutex); |
| 3013 | 3037 | return ret; |
| 3014 | 3038 | } |
| @@ -3069,9 +3093,11 @@ int psp_ring_cmd_submit(struct psp_context *psp, · 54 unmodified lines | ||
| 3069 | 3093 | write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); |
| 3070 | 3094 | /* Check invalid write_frame ptr address */ |
| 3071 | 3095 | if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { |
| 3072 | − DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", | |
| 3073 | − ring_buffer_start, ring_buffer_end, write_frame); | |
| 3074 | − DRM_ERROR("write_frame is pointing to address out of bounds\n"); | |
| 3096 | + dev_err(adev->dev, | |
| 3097 | + "ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", | |
| 3098 | + ring_buffer_start, ring_buffer_end, write_frame); | |
| 3099 | + dev_err(adev->dev, | |
| 3100 | + "write_frame is pointing to address out of bounds\n"); | |
| 3075 | 3101 | return -EINVAL; |
| 3076 | 3102 | } |
| 3077 | 3103 | |
| @@ -3597,7 +3623,7 @@ static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, · 519 unmodified lines | ||
| 3597 | 3623 | int ret; |
| 3598 | 3624 | |
| 3599 | 3625 | if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { |
| 3600 | − DRM_INFO("PSP block is not ready yet."); | |
| 3626 | + dev_info(adev->dev, "PSP block is not ready yet\n."); | |
| 3601 | 3627 | return -EBUSY; |
| 3602 | 3628 | } |
| 3603 | 3629 | |
| @@ -3606,7 +3632,7 @@ static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, · 2 unmodified lines | ||
| 3606 | 3632 | mutex_unlock(&adev->psp.mutex); |
| 3607 | 3633 | |
| 3608 | 3634 | if (ret) { |
| 3609 | − DRM_ERROR("Failed to read USBC PD FW, err = %d", ret); | |
| 3635 | + dev_err(adev->dev, "Failed to read USBC PD FW, err = %d\n", ret); | |
| 3610 | 3636 | return ret; |
| 3611 | 3637 | } |
| 3612 | 3638 | |
| @@ -3628,7 +3654,7 @@ static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, · 15 unmodified lines | ||
| 3628 | 3654 | void *fw_pri_cpu_addr; |
| 3629 | 3655 | |
| 3630 | 3656 | if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { |
| 3631 | − DRM_INFO("PSP block is not ready yet."); | |
| 3657 | + dev_err(adev->dev, "PSP block is not ready yet."); | |
| 3632 | 3658 | return -EBUSY; |
| 3633 | 3659 | } |
| 3634 | 3660 | |
| @@ -3661,7 +3687,7 @@ rel_buf: · 26 unmodified lines | ||
| 3661 | 3687 | release_firmware(usbc_pd_fw); |
| 3662 | 3688 | fail: |
| 3663 | 3689 | if (ret) { |
| 3664 | − DRM_ERROR("Failed to load USBC PD FW, err = %d", ret); | |
| 3690 | + dev_err(adev->dev, "Failed to load USBC PD FW, err = %d", ret); | |
| 3665 | 3691 | count = ret; |
| 3666 | 3692 | } |
| 3667 | 3693 | |
| @@ -3708,7 +3734,7 @@ static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj, · 40 unmodified lines | ||
| 3708 | 3734 | |
| 3709 | 3735 | /* Safeguard against memory drain */ |
| 3710 | 3736 | if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) { |
| 3711 | − dev_err(adev->dev, "File size cannot exceed %u", AMD_VBIOS_FILE_MAX_SIZE_B); | |
| 3737 | + dev_err(adev->dev, "File size cannot exceed %u\n", AMD_VBIOS_FILE_MAX_SIZE_B); | |
| 3712 | 3738 | kvfree(adev->psp.vbflash_tmp_buf); |
| 3713 | 3739 | adev->psp.vbflash_tmp_buf = NULL; |
| 3714 | 3740 | adev->psp.vbflash_image_size = 0; |
| @@ -3727,7 +3753,7 @@ static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj, · 12 unmodified lines | ||
| 3727 | 3753 | adev->psp.vbflash_image_size += count; |
| 3728 | 3754 | mutex_unlock(&adev->psp.mutex); |
| 3729 | 3755 | |
| 3730 | − dev_dbg(adev->dev, "IFWI staged for update"); | |
| 3756 | + dev_dbg(adev->dev, "IFWI staged for update\n"); | |
| 3731 | 3757 | |
| 3732 | 3758 | return count; |
| 3733 | 3759 | } |
| @@ -3747,7 +3773,7 @@ static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj, · 13 unmodified lines | ||
| 3747 | 3773 | if (adev->psp.vbflash_image_size == 0) |
| 3748 | 3774 | return -EINVAL; |
| 3749 | 3775 | |
| 3750 | − dev_dbg(adev->dev, "PSP IFWI flash process initiated"); | |
| 3776 | + dev_dbg(adev->dev, "PSP IFWI flash process initiated\n"); | |
| 3751 | 3777 | |
| 3752 | 3778 | ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size, |
| 3753 | 3779 | AMDGPU_GPU_PAGE_SIZE, |
| @@ -3772,11 +3798,11 @@ rel_buf: · 18 unmodified lines | ||
| 3772 | 3798 | adev->psp.vbflash_image_size = 0; |
| 3773 | 3799 | |
| 3774 | 3800 | if (ret) { |
| 3775 | − dev_err(adev->dev, "Failed to load IFWI, err = %d", ret); | |
| 3801 | + dev_err(adev->dev, "Failed to load IFWI, err = %d\n", ret); | |
| 3776 | 3802 | return ret; |
| 3777 | 3803 | } |
| 3778 | 3804 | |
| 3779 | − dev_dbg(adev->dev, "PSP IFWI flash process done"); | |
| 3805 | + dev_dbg(adev->dev, "PSP IFWI flash process done\n"); | |
| 3780 | 3806 | return 0; |
| 3781 | 3807 | } |
| 3782 | 3808 | |
| @@ -134,7 +134,7 @@ struct psp_funcs { · 133 unmodified lines | ||
| 134 | 134 | int (*update_spirom)(struct psp_context *psp, uint64_t fw_pri_mc_addr); |
| 135 | 135 | int (*vbflash_stat)(struct psp_context *psp); |
| 136 | 136 | int (*fatal_error_recovery_quirk)(struct psp_context *psp); |
| 137 | − int (*query_boot_status)(struct psp_context *psp); | |
| 137 | + bool (*get_ras_capability)(struct psp_context *psp); | |
| 138 | 138 | }; |
| 139 | 139 | |
| 140 | 140 | struct ta_funcs { |
| @@ -502,6 +502,9 @@ int psp_ras_enable_features(struct psp_context *psp, · 361 unmodified lines | ||
| 502 | 502 | int psp_ras_trigger_error(struct psp_context *psp, |
| 503 | 503 | struct ta_ras_trigger_error_input *info, uint32_t instance_mask); |
| 504 | 504 | int psp_ras_terminate(struct psp_context *psp); |
| 505 | +int psp_ras_query_address(struct psp_context *psp, | |
| 506 | + struct ta_ras_query_address_input *addr_in, | |
| 507 | + struct ta_ras_query_address_output *addr_out); | |
| 505 | 508 | |
| 506 | 509 | int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id); |
| 507 | 510 | int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id); |
| @@ -538,7 +541,5 @@ int psp_spatial_partition(struct psp_context *psp, int mode); · 30 unmodified lines | ||
| 538 | 541 | int is_psp_fw_valid(struct psp_bin_desc bin); |
| 539 | 542 | |
| 540 | 543 | int amdgpu_psp_wait_for_bootloader(struct amdgpu_device *adev); |
| 541 | − | |
| 542 | −int amdgpu_psp_query_boot_status(struct amdgpu_device *adev); | |
| 543 | − | |
| 544 | +bool amdgpu_psp_get_ras_capability(struct psp_context *psp); | |
| 544 | 545 | #endif |
| @@ -362,7 +362,7 @@ static ssize_t ta_if_invoke_debugfs_write(struct file *fp, const char *buf, size · 361 unmodified lines | ||
| 362 | 362 | } |
| 363 | 363 | } |
| 364 | 364 | |
| 365 | − if (copy_to_user((char *)buf, context->mem_context.shared_buf, shared_buf_len)) | |
| 365 | + if (copy_to_user((char *)&buf[copy_pos], context->mem_context.shared_buf, shared_buf_len)) | |
| 366 | 366 | ret = -EFAULT; |
| 367 | 367 | |
| 368 | 368 | err_free_shared_buf: |
| @@ -39,6 +39,7 @@ · 38 unmodified lines | ||
| 39 | 39 | #include "nbio_v7_9.h" |
| 40 | 40 | #include "atom.h" |
| 41 | 41 | #include "amdgpu_reset.h" |
| 42 | +#include "amdgpu_psp.h" | |
| 42 | 43 | |
| 43 | 44 | #ifdef CONFIG_X86_MCE_AMD |
| 44 | 45 | #include <asm/mce.h> |
| @@ -73,6 +74,8 @@ const char *ras_block_string[] = { · 28 unmodified lines | ||
| 73 | 74 | "mca", |
| 74 | 75 | "vcn", |
| 75 | 76 | "jpeg", |
| 77 | + "ih", | |
| 78 | + "mpio", | |
| 76 | 79 | }; |
| 77 | 80 | |
| 78 | 81 | const char *ras_mca_block_string[] = { |
| @@ -94,7 +97,8 @@ const char *get_ras_block_str(struct ras_common_if *ras_block) · 15 unmodified lines | ||
| 94 | 97 | if (!ras_block) |
| 95 | 98 | return "NULL"; |
| 96 | 99 | |
| 97 | − if (ras_block->block >= AMDGPU_RAS_BLOCK_COUNT) | |
| 100 | + if (ras_block->block >= AMDGPU_RAS_BLOCK_COUNT || | |
| 101 | + ras_block->block >= ARRAY_SIZE(ras_block_string)) | |
| 98 | 102 | return "OUT OF RANGE"; |
| 99 | 103 | |
| 100 | 104 | if (ras_block->block == AMDGPU_RAS_BLOCK__MCA) |
| @@ -116,6 +120,8 @@ const char *get_ras_block_str(struct ras_common_if *ras_block) · 15 unmodified lines | ||
| 116 | 120 | /* typical ECC bad page rate is 1 bad page per 100MB VRAM */ |
| 117 | 121 | #define RAS_BAD_PAGE_COVER (100 * 1024 * 1024ULL) |
| 118 | 122 | |
| 123 | +#define MAX_UMC_POISON_POLLING_TIME_ASYNC 100 //ms | |
| 124 | + | |
| 119 | 125 | enum amdgpu_ras_retire_page_reservation { |
| 120 | 126 | AMDGPU_RAS_RETIRE_PAGE_RESERVED, |
| 121 | 127 | AMDGPU_RAS_RETIRE_PAGE_PENDING, |
| @@ -628,8 +634,12 @@ static ssize_t amdgpu_ras_sysfs_read(struct device *dev, · 506 unmodified lines | ||
| 628 | 634 | dev_warn(obj->adev->dev, "Failed to reset error counter and error status"); |
| 629 | 635 | } |
| 630 | 636 | |
| 631 | − return sysfs_emit(buf, "%s: %lu\n%s: %lu\n", "ue", info.ue_count, | |
| 632 | − "ce", info.ce_count); | |
| 637 | + if (info.head.block == AMDGPU_RAS_BLOCK__UMC) | |
| 638 | + return sysfs_emit(buf, "%s: %lu\n%s: %lu\n%s: %lu\n", "ue", info.ue_count, | |
| 639 | + "ce", info.ce_count, "de", info.de_count); | |
| 640 | + else | |
| 641 | + return sysfs_emit(buf, "%s: %lu\n%s: %lu\n", "ue", info.ue_count, | |
| 642 | + "ce", info.ce_count); | |
| 633 | 643 | } |
| 634 | 644 | |
| 635 | 645 | /* obj begin */ |
| @@ -1036,7 +1046,8 @@ static void amdgpu_ras_error_print_error_data(struct amdgpu_device *adev, · 400 unmodified lines | ||
| 1036 | 1046 | struct ras_manager *ras_mgr, |
| 1037 | 1047 | struct ras_err_data *err_data, |
| 1038 | 1048 | const char *blk_name, |
| 1039 | − bool is_ue) | |
| 1049 | + bool is_ue, | |
| 1050 | + bool is_de) | |
| 1040 | 1051 | { |
| 1041 | 1052 | struct amdgpu_smuio_mcm_config_info *mcm_info; |
| 1042 | 1053 | struct ras_err_node *err_node; |
| @@ -1065,25 +1076,50 @@ static void amdgpu_ras_error_print_error_data(struct amdgpu_device *adev, · 22 unmodified lines | ||
| 1065 | 1076 | } |
| 1066 | 1077 | |
| 1067 | 1078 | } else { |
| 1068 | − for_each_ras_error(err_node, err_data) { | |
| 1069 | − err_info = &err_node->err_info; | |
| 1070 | − mcm_info = &err_info->mcm_info; | |
| 1071 | − if (err_info->ce_count) { | |
| 1079 | + if (is_de) { | |
| 1080 | + for_each_ras_error(err_node, err_data) { | |
| 1081 | + err_info = &err_node->err_info; | |
| 1082 | + mcm_info = &err_info->mcm_info; | |
| 1083 | + if (err_info->de_count) { | |
| 1084 | + dev_info(adev->dev, "socket: %d, die: %d, " | |
| 1085 | + "%lld new deferred hardware errors detected in %s block\n", | |
| 1086 | + mcm_info->socket_id, | |
| 1087 | + mcm_info->die_id, | |
| 1088 | + err_info->de_count, | |
| 1089 | + blk_name); | |
| 1090 | + } | |
| 1091 | + } | |
| 1092 | + | |
| 1093 | + for_each_ras_error(err_node, &ras_mgr->err_data) { | |
| 1094 | + err_info = &err_node->err_info; | |
| 1095 | + mcm_info = &err_info->mcm_info; | |
| 1072 | 1096 | dev_info(adev->dev, "socket: %d, die: %d, " |
| 1073 | − "%lld new correctable hardware errors detected in %s block\n", | |
| 1074 | − mcm_info->socket_id, | |
| 1075 | − mcm_info->die_id, | |
| 1076 | − err_info->ce_count, | |
| 1077 | − blk_name); | |
| 1097 | + "%lld deferred hardware errors detected in total in %s block\n", | |
| 1098 | + mcm_info->socket_id, mcm_info->die_id, | |
| 1099 | + err_info->de_count, blk_name); | |
| 1100 | + } | |
| 1101 | + } else { | |
| 1102 | + for_each_ras_error(err_node, err_data) { | |
| 1103 | + err_info = &err_node->err_info; | |
| 1104 | + mcm_info = &err_info->mcm_info; | |
| 1105 | + if (err_info->ce_count) { | |
| 1106 | + dev_info(adev->dev, "socket: %d, die: %d, " | |
| 1107 | + "%lld new correctable hardware errors detected in %s block\n", | |
| 1108 | + mcm_info->socket_id, | |
| 1109 | + mcm_info->die_id, | |
| 1110 | + err_info->ce_count, | |
| 1111 | + blk_name); | |
| 1112 | + } | |
| 1078 | 1113 | } |
| 1079 | − } | |
| 1080 | 1114 | |
| 1081 | − for_each_ras_error(err_node, &ras_mgr->err_data) { | |
| 1082 | − err_info = &err_node->err_info; | |
| 1083 | − mcm_info = &err_info->mcm_info; | |
| 1084 | − dev_info(adev->dev, "socket: %d, die: %d, " | |
| 1085 | − "%lld correctable hardware errors detected in total in %s block\n", | |
| 1086 | − mcm_info->socket_id, mcm_info->die_id, err_info->ce_count, blk_name); | |
| 1115 | + for_each_ras_error(err_node, &ras_mgr->err_data) { | |
| 1116 | + err_info = &err_node->err_info; | |
| 1117 | + mcm_info = &err_info->mcm_info; | |
| 1118 | + dev_info(adev->dev, "socket: %d, die: %d, " | |
| 1119 | + "%lld correctable hardware errors detected in total in %s block\n", | |
| 1120 | + mcm_info->socket_id, mcm_info->die_id, | |
| 1121 | + err_info->ce_count, blk_name); | |
| 1122 | + } | |
| 1087 | 1123 | } |
| 1088 | 1124 | } |
| 1089 | 1125 | } |
| @@ -1102,7 +1138,8 @@ static void amdgpu_ras_error_generate_report(struct amdgpu_device *adev, · 12 unmodified lines | ||
| 1102 | 1138 | |
| 1103 | 1139 | if (err_data->ce_count) { |
| 1104 | 1140 | if (err_data_has_source_info(err_data)) { |
| 1105 | − amdgpu_ras_error_print_error_data(adev, ras_mgr, err_data, blk_name, false); | |
| 1141 | + amdgpu_ras_error_print_error_data(adev, ras_mgr, err_data, | |
| 1142 | + blk_name, false, false); | |
| 1106 | 1143 | } else if (!adev->aid_mask && |
| 1107 | 1144 | adev->smuio.funcs && |
| 1108 | 1145 | adev->smuio.funcs->get_socket_id && |
| @@ -1124,7 +1161,8 @@ static void amdgpu_ras_error_generate_report(struct amdgpu_device *adev, · 15 unmodified lines | ||
| 1124 | 1161 | |
| 1125 | 1162 | if (err_data->ue_count) { |
| 1126 | 1163 | if (err_data_has_source_info(err_data)) { |
| 1127 | − amdgpu_ras_error_print_error_data(adev, ras_mgr, err_data, blk_name, true); | |
| 1164 | + amdgpu_ras_error_print_error_data(adev, ras_mgr, err_data, | |
| 1165 | + blk_name, true, false); | |
| 1128 | 1166 | } else if (!adev->aid_mask && |
| 1129 | 1167 | adev->smuio.funcs && |
| 1130 | 1168 | adev->smuio.funcs->get_socket_id && |
| @@ -1144,6 +1182,28 @@ static void amdgpu_ras_error_generate_report(struct amdgpu_device *adev, · 13 unmodified lines | ||
| 1144 | 1182 | } |
| 1145 | 1183 | } |
| 1146 | 1184 | |
| 1185 | + if (err_data->de_count) { | |
| 1186 | + if (err_data_has_source_info(err_data)) { | |
| 1187 | + amdgpu_ras_error_print_error_data(adev, ras_mgr, err_data, | |
| 1188 | + blk_name, false, true); | |
| 1189 | + } else if (!adev->aid_mask && | |
| 1190 | + adev->smuio.funcs && | |
| 1191 | + adev->smuio.funcs->get_socket_id && | |
| 1192 | + adev->smuio.funcs->get_die_id) { | |
| 1193 | + dev_info(adev->dev, "socket: %d, die: %d " | |
| 1194 | + "%ld deferred hardware errors " | |
| 1195 | + "detected in %s block\n", | |
| 1196 | + adev->smuio.funcs->get_socket_id(adev), | |
| 1197 | + adev->smuio.funcs->get_die_id(adev), | |
| 1198 | + ras_mgr->err_data.de_count, | |
| 1199 | + blk_name); | |
| 1200 | + } else { | |
| 1201 | + dev_info(adev->dev, "%ld deferred hardware errors " | |
| 1202 | + "detected in %s block\n", | |
| 1203 | + ras_mgr->err_data.de_count, | |
| 1204 | + blk_name); | |
| 1205 | + } | |
| 1206 | + } | |
| 1147 | 1207 | } |
| 1148 | 1208 | |
| 1149 | 1209 | static void amdgpu_rasmgr_error_data_statistic_update(struct ras_manager *obj, struct ras_err_data *err_data) |
| @@ -1154,7 +1214,8 @@ static void amdgpu_rasmgr_error_data_statistic_update(struct ras_manager *obj, s · 4 unmodified lines | ||
| 1154 | 1214 | if (err_data_has_source_info(err_data)) { |
| 1155 | 1215 | for_each_ras_error(err_node, err_data) { |
| 1156 | 1216 | err_info = &err_node->err_info; |
| 1157 | − | |
| 1217 | + amdgpu_ras_error_statistic_de_count(&obj->err_data, | |
| 1218 | + &err_info->mcm_info, NULL, err_info->de_count); | |
| 1158 | 1219 | amdgpu_ras_error_statistic_ce_count(&obj->err_data, |
| 1159 | 1220 | &err_info->mcm_info, NULL, err_info->ce_count); |
| 1160 | 1221 | amdgpu_ras_error_statistic_ue_count(&obj->err_data, |
| @@ -1164,9 +1225,72 @@ static void amdgpu_rasmgr_error_data_statistic_update(struct ras_manager *obj, s · 3 unmodified lines | ||
| 1164 | 1225 | /* for legacy asic path which doesn't has error source info */ |
| 1165 | 1226 | obj->err_data.ue_count += err_data->ue_count; |
| 1166 | 1227 | obj->err_data.ce_count += err_data->ce_count; |
| 1228 | + obj->err_data.de_count += err_data->de_count; | |
| 1167 | 1229 | } |
| 1168 | 1230 | } |
| 1169 | 1231 | |
| 1232 | +static struct ras_manager *get_ras_manager(struct amdgpu_device *adev, enum amdgpu_ras_block blk) | |
| 1233 | +{ | |
| 1234 | + struct ras_common_if head; | |
| 1235 | + | |
| 1236 | + memset(&head, 0, sizeof(head)); | |
| 1237 | + head.block = blk; | |
| 1238 | + | |
| 1239 | + return amdgpu_ras_find_obj(adev, &head); | |
| 1240 | +} | |
| 1241 | + | |
| 1242 | +int amdgpu_ras_bind_aca(struct amdgpu_device *adev, enum amdgpu_ras_block blk, | |
| 1243 | + const struct aca_info *aca_info, void *data) | |
| 1244 | +{ | |
| 1245 | + struct ras_manager *obj; | |
| 1246 | + | |
| 1247 | + obj = get_ras_manager(adev, blk); | |
| 1248 | + if (!obj) | |
| 1249 | + return -EINVAL; | |
| 1250 | + | |
| 1251 | + return amdgpu_aca_add_handle(adev, &obj->aca_handle, ras_block_str(blk), aca_info, data); | |
| 1252 | +} | |
| 1253 | + | |
| 1254 | +int amdgpu_ras_unbind_aca(struct amdgpu_device *adev, enum amdgpu_ras_block blk) | |
| 1255 | +{ | |
| 1256 | + struct ras_manager *obj; | |
| 1257 | + | |
| 1258 | + obj = get_ras_manager(adev, blk); | |
| 1259 | + if (!obj) | |
| 1260 | + return -EINVAL; | |
| 1261 | + | |
| 1262 | + amdgpu_aca_remove_handle(&obj->aca_handle); | |
| 1263 | + | |
| 1264 | + return 0; | |
| 1265 | +} | |
| 1266 | + | |
| 1267 | +static int amdgpu_aca_log_ras_error_data(struct amdgpu_device *adev, enum amdgpu_ras_block blk, | |
| 1268 | + enum aca_error_type type, struct ras_err_data *err_data) | |
| 1269 | +{ | |
| 1270 | + struct ras_manager *obj; | |
| 1271 | + | |
| 1272 | + obj = get_ras_manager(adev, blk); | |
| 1273 | + if (!obj) | |
| 1274 | + return -EINVAL; | |
| 1275 | + | |
| 1276 | + return amdgpu_aca_get_error_data(adev, &obj->aca_handle, type, err_data); | |
| 1277 | +} | |
| 1278 | + | |
| 1279 | +ssize_t amdgpu_ras_aca_sysfs_read(struct device *dev, struct device_attribute *attr, | |
| 1280 | + struct aca_handle *handle, char *buf, void *data) | |
| 1281 | +{ | |
| 1282 | + struct ras_manager *obj = container_of(handle, struct ras_manager, aca_handle); | |
| 1283 | + struct ras_query_if info = { | |
| 1284 | + .head = obj->head, | |
| 1285 | + }; | |
| 1286 | + | |
| 1287 | + if (amdgpu_ras_query_error_status(obj->adev, &info)) | |
| 1288 | + return -EINVAL; | |
| 1289 | + | |
| 1290 | + return sysfs_emit(buf, "%s: %lu\n%s: %lu\n", "ue", info.ue_count, | |
| 1291 | + "ce", info.ce_count); | |
| 1292 | +} | |
| 1293 | + | |
| 1170 | 1294 | static int amdgpu_ras_query_error_status_helper(struct amdgpu_device *adev, |
| 1171 | 1295 | struct ras_query_if *info, |
| 1172 | 1296 | struct ras_err_data *err_data, |
| @@ -1174,6 +1298,7 @@ static int amdgpu_ras_query_error_status_helper(struct amdgpu_device *adev, · 1 unmodified line | ||
| 1174 | 1298 | { |
| 1175 | 1299 | enum amdgpu_ras_block blk = info ? info->head.block : AMDGPU_RAS_BLOCK_COUNT; |
| 1176 | 1300 | struct amdgpu_ras_block_object *block_obj = NULL; |
| 1301 | + int ret; | |
| 1177 | 1302 | |
| 1178 | 1303 | if (blk == AMDGPU_RAS_BLOCK_COUNT) |
| 1179 | 1304 | return -EINVAL; |
| @@ -1203,9 +1328,19 @@ static int amdgpu_ras_query_error_status_helper(struct amdgpu_device *adev, · 23 unmodified lines | ||
| 1203 | 1328 | } |
| 1204 | 1329 | } |
| 1205 | 1330 | } else { |
| 1206 | − /* FIXME: add code to check return value later */ | |
| 1207 | − amdgpu_mca_smu_log_ras_error(adev, blk, AMDGPU_MCA_ERROR_TYPE_UE, err_data); | |
| 1208 | − amdgpu_mca_smu_log_ras_error(adev, blk, AMDGPU_MCA_ERROR_TYPE_CE, err_data); | |
| 1331 | + if (amdgpu_aca_is_enabled(adev)) { | |
| 1332 | + ret = amdgpu_aca_log_ras_error_data(adev, blk, ACA_ERROR_TYPE_UE, err_data); | |
| 1333 | + if (ret) | |
| 1334 | + return ret; | |
| 1335 | + | |
| 1336 | + ret = amdgpu_aca_log_ras_error_data(adev, blk, ACA_ERROR_TYPE_CE, err_data); | |
| 1337 | + if (ret) | |
| 1338 | + return ret; | |
| 1339 | + } else { | |
| 1340 | + /* FIXME: add code to check return value later */ | |
| 1341 | + amdgpu_mca_smu_log_ras_error(adev, blk, AMDGPU_MCA_ERROR_TYPE_UE, err_data); | |
| 1342 | + amdgpu_mca_smu_log_ras_error(adev, blk, AMDGPU_MCA_ERROR_TYPE_CE, err_data); | |
| 1343 | + } | |
| 1209 | 1344 | } |
| 1210 | 1345 | |
| 1211 | 1346 | return 0; |
| @@ -1239,6 +1374,7 @@ int amdgpu_ras_query_error_status(struct amdgpu_device *adev, struct ras_query_i · 27 unmodified lines | ||
| 1239 | 1374 | |
| 1240 | 1375 | info->ue_count = obj->err_data.ue_count; |
| 1241 | 1376 | info->ce_count = obj->err_data.ce_count; |
| 1377 | + info->de_count = obj->err_data.de_count; | |
| 1242 | 1378 | |
| 1243 | 1379 | amdgpu_ras_error_generate_report(adev, info, &err_data); |
| 1244 | 1380 | |
| @@ -1254,6 +1390,7 @@ int amdgpu_ras_reset_error_count(struct amdgpu_device *adev, · 9 unmodified lines | ||
| 1254 | 1390 | struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev, block, 0); |
| 1255 | 1391 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); |
| 1256 | 1392 | const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs; |
| 1393 | + const struct aca_smu_funcs *smu_funcs = adev->aca.smu_funcs; | |
| 1257 | 1394 | struct amdgpu_hive_info *hive; |
| 1258 | 1395 | int hive_ras_recovery = 0; |
| 1259 | 1396 | |
| @@ -1264,7 +1401,7 @@ int amdgpu_ras_reset_error_count(struct amdgpu_device *adev, · 4 unmodified lines | ||
| 1264 | 1401 | } |
| 1265 | 1402 | |
| 1266 | 1403 | if (!amdgpu_ras_is_supported(adev, block) || |
| 1267 | − !amdgpu_ras_get_mca_debug_mode(adev)) | |
| 1404 | + !amdgpu_ras_get_aca_debug_mode(adev)) | |
| 1268 | 1405 | return -EOPNOTSUPP; |
| 1269 | 1406 | |
| 1270 | 1407 | hive = amdgpu_get_xgmi_hive(adev); |
| @@ -1276,7 +1413,8 @@ int amdgpu_ras_reset_error_count(struct amdgpu_device *adev, · 5 unmodified lines | ||
| 1276 | 1413 | /* skip ras error reset in gpu reset */ |
| 1277 | 1414 | if ((amdgpu_in_reset(adev) || atomic_read(&ras->in_recovery) || |
| 1278 | 1415 | hive_ras_recovery) && |
| 1279 | − mca_funcs && mca_funcs->mca_set_debug_mode) | |
| 1416 | + ((smu_funcs && smu_funcs->set_debug_mode) || | |
| 1417 | + (mca_funcs && mca_funcs->mca_set_debug_mode))) | |
| 1280 | 1418 | return -EOPNOTSUPP; |
| 1281 | 1419 | |
| 1282 | 1420 | if (block_obj->hw_ops->reset_ras_error_count) |
| @@ -1772,7 +1910,10 @@ void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev) · 489 unmodified lines | ||
| 1772 | 1910 | } |
| 1773 | 1911 | } |
| 1774 | 1912 | |
| 1775 | − amdgpu_mca_smu_debugfs_init(adev, dir); | |
| 1913 | + if (amdgpu_aca_is_enabled(adev)) | |
| 1914 | + amdgpu_aca_smu_debugfs_init(adev, dir); | |
| 1915 | + else | |
| 1916 | + amdgpu_mca_smu_debugfs_init(adev, dir); | |
| 1776 | 1917 | } |
| 1777 | 1918 | |
| 1778 | 1919 | /* debugfs end */ |
| @@ -1900,7 +2041,7 @@ static void amdgpu_ras_interrupt_poison_consumption_handler(struct ras_manager * · 121 unmodified lines | ||
| 1900 | 2041 | } |
| 1901 | 2042 | } |
| 1902 | 2043 | |
| 1903 | − amdgpu_umc_poison_handler(adev, false); | |
| 2044 | + amdgpu_umc_poison_handler(adev, obj->head.block, false); | |
| 1904 | 2045 | |
| 1905 | 2046 | if (block_obj->hw_ops && block_obj->hw_ops->handle_poison_consumption) |
| 1906 | 2047 | poison_stat = block_obj->hw_ops->handle_poison_consumption(adev); |
| @@ -1951,6 +2092,7 @@ static void amdgpu_ras_interrupt_umc_handler(struct ras_manager *obj, · 44 unmodified lines | ||
| 1951 | 2092 | */ |
| 1952 | 2093 | obj->err_data.ue_count += err_data.ue_count; |
| 1953 | 2094 | obj->err_data.ce_count += err_data.ce_count; |
| 2095 | + obj->err_data.de_count += err_data.de_count; | |
| 1954 | 2096 | } |
| 1955 | 2097 | |
| 1956 | 2098 | amdgpu_ras_error_data_fini(&err_data); |
| @@ -2520,6 +2662,32 @@ static void amdgpu_ras_validate_threshold(struct amdgpu_device *adev, · 563 unmodified lines | ||
| 2520 | 2662 | } |
| 2521 | 2663 | } |
| 2522 | 2664 | |
| 2665 | +static int amdgpu_ras_page_retirement_thread(void *param) | |
| 2666 | +{ | |
| 2667 | + struct amdgpu_device *adev = (struct amdgpu_device *)param; | |
| 2668 | + struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
| 2669 | + | |
| 2670 | + while (!kthread_should_stop()) { | |
| 2671 | + | |
| 2672 | + wait_event_interruptible(con->page_retirement_wq, | |
| 2673 | + kthread_should_stop() || | |
| 2674 | + atomic_read(&con->page_retirement_req_cnt)); | |
| 2675 | + | |
| 2676 | + if (kthread_should_stop()) | |
| 2677 | + break; | |
| 2678 | + | |
| 2679 | + dev_info(adev->dev, "Start processing page retirement. request:%d\n", | |
| 2680 | + atomic_read(&con->page_retirement_req_cnt)); | |
| 2681 | + | |
| 2682 | + atomic_dec(&con->page_retirement_req_cnt); | |
| 2683 | + | |
| 2684 | + amdgpu_umc_bad_page_polling_timeout(adev, | |
| 2685 | + false, MAX_UMC_POISON_POLLING_TIME_ASYNC); | |
| 2686 | + } | |
| 2687 | + | |
| 2688 | + return 0; | |
| 2689 | +} | |
| 2690 | + | |
| 2523 | 2691 | int amdgpu_ras_recovery_init(struct amdgpu_device *adev) |
| 2524 | 2692 | { |
| 2525 | 2693 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
| @@ -2583,6 +2751,16 @@ int amdgpu_ras_recovery_init(struct amdgpu_device *adev) · 57 unmodified lines | ||
| 2583 | 2751 | } |
| 2584 | 2752 | } |
| 2585 | 2753 | |
| 2754 | + mutex_init(&con->page_retirement_lock); | |
| 2755 | + init_waitqueue_head(&con->page_retirement_wq); | |
| 2756 | + atomic_set(&con->page_retirement_req_cnt, 0); | |
| 2757 | + con->page_retirement_thread = | |
| 2758 | + kthread_run(amdgpu_ras_page_retirement_thread, adev, "umc_page_retirement"); | |
| 2759 | + if (IS_ERR(con->page_retirement_thread)) { | |
| 2760 | + con->page_retirement_thread = NULL; | |
| 2761 | + dev_warn(adev->dev, "Failed to create umc_page_retirement thread!!!\n"); | |
| 2762 | + } | |
| 2763 | + | |
| 2586 | 2764 | #ifdef CONFIG_X86_MCE_AMD |
| 2587 | 2765 | if ((adev->asic_type == CHIP_ALDEBARAN) && |
| 2588 | 2766 | (adev->gmc.xgmi.connected_to_cpu)) |
| @@ -2618,6 +2796,11 @@ static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev) · 29 unmodified lines | ||
| 2618 | 2796 | if (!data) |
| 2619 | 2797 | return 0; |
| 2620 | 2798 | |
| 2799 | + if (con->page_retirement_thread) | |
| 2800 | + kthread_stop(con->page_retirement_thread); | |
| 2801 | + | |
| 2802 | + atomic_set(&con->page_retirement_req_cnt, 0); | |
| 2803 | + | |
| 2621 | 2804 | cancel_work_sync(&con->recovery_work); |
| 2622 | 2805 | |
| 2623 | 2806 | mutex_lock(&con->recovery_lock); |
| @@ -2679,6 +2862,87 @@ static void amdgpu_ras_get_quirks(struct amdgpu_device *adev) · 55 unmodified lines | ||
| 2679 | 2862 | adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX); |
| 2680 | 2863 | } |
| 2681 | 2864 | |
| 2865 | +/* Query ras capablity via atomfirmware interface */ | |
| 2866 | +static void amdgpu_ras_query_ras_capablity_from_vbios(struct amdgpu_device *adev) | |
| 2867 | +{ | |
| 2868 | + /* mem_ecc cap */ | |
| 2869 | + if (amdgpu_atomfirmware_mem_ecc_supported(adev)) { | |
| 2870 | + dev_info(adev->dev, "MEM ECC is active.\n"); | |
| 2871 | + adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__UMC | | |
| 2872 | + 1 << AMDGPU_RAS_BLOCK__DF); | |
| 2873 | + } else { | |
| 2874 | + dev_info(adev->dev, "MEM ECC is not presented.\n"); | |
| 2875 | + } | |
| 2876 | + | |
| 2877 | + /* sram_ecc cap */ | |
| 2878 | + if (amdgpu_atomfirmware_sram_ecc_supported(adev)) { | |
| 2879 | + dev_info(adev->dev, "SRAM ECC is active.\n"); | |
| 2880 | + if (!amdgpu_sriov_vf(adev)) | |
| 2881 | + adev->ras_hw_enabled |= ~(1 << AMDGPU_RAS_BLOCK__UMC | | |
| 2882 | + 1 << AMDGPU_RAS_BLOCK__DF); | |
| 2883 | + else | |
| 2884 | + adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__PCIE_BIF | | |
| 2885 | + 1 << AMDGPU_RAS_BLOCK__SDMA | | |
| 2886 | + 1 << AMDGPU_RAS_BLOCK__GFX); | |
| 2887 | + | |
| 2888 | + /* | |
| 2889 | + * VCN/JPEG RAS can be supported on both bare metal and | |
| 2890 | + * SRIOV environment | |
| 2891 | + */ | |
| 2892 | + if (amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(2, 6, 0) || | |
| 2893 | + amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(4, 0, 0) || | |
| 2894 | + amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(4, 0, 3)) | |
| 2895 | + adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__VCN | | |
| 2896 | + 1 << AMDGPU_RAS_BLOCK__JPEG); | |
| 2897 | + else | |
| 2898 | + adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__VCN | | |
| 2899 | + 1 << AMDGPU_RAS_BLOCK__JPEG); | |
| 2900 | + | |
| 2901 | + /* | |
| 2902 | + * XGMI RAS is not supported if xgmi num physical nodes | |
| 2903 | + * is zero | |
| 2904 | + */ | |
| 2905 | + if (!adev->gmc.xgmi.num_physical_nodes) | |
| 2906 | + adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__XGMI_WAFL); | |
| 2907 | + } else { | |
| 2908 | + dev_info(adev->dev, "SRAM ECC is not presented.\n"); | |
| 2909 | + } | |
| 2910 | +} | |
| 2911 | + | |
| 2912 | +/* Query poison mode from umc/df IP callbacks */ | |
| 2913 | +static void amdgpu_ras_query_poison_mode(struct amdgpu_device *adev) | |
| 2914 | +{ | |
| 2915 | + struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
| 2916 | + bool df_poison, umc_poison; | |
| 2917 | + | |
| 2918 | + /* poison setting is useless on SRIOV guest */ | |
| 2919 | + if (amdgpu_sriov_vf(adev) || !con) | |
| 2920 | + return; | |
| 2921 | + | |
| 2922 | + /* Init poison supported flag, the default value is false */ | |
| 2923 | + if (adev->gmc.xgmi.connected_to_cpu || | |
| 2924 | + adev->gmc.is_app_apu) { | |
| 2925 | + /* enabled by default when GPU is connected to CPU */ | |
| 2926 | + con->poison_supported = true; | |
| 2927 | + } else if (adev->df.funcs && | |
| 2928 | + adev->df.funcs->query_ras_poison_mode && | |
| 2929 | + adev->umc.ras && | |
| 2930 | + adev->umc.ras->query_ras_poison_mode) { | |
| 2931 | + df_poison = | |
| 2932 | + adev->df.funcs->query_ras_poison_mode(adev); | |
| 2933 | + umc_poison = | |
| 2934 | + adev->umc.ras->query_ras_poison_mode(adev); | |
| 2935 | + | |
| 2936 | + /* Only poison is set in both DF and UMC, we can support it */ | |
| 2937 | + if (df_poison && umc_poison) | |
| 2938 | + con->poison_supported = true; | |
| 2939 | + else if (df_poison != umc_poison) | |
| 2940 | + dev_warn(adev->dev, | |
| 2941 | + "Poison setting is inconsistent in DF/UMC(%d:%d)!\n", | |
| 2942 | + df_poison, umc_poison); | |
| 2943 | + } | |
| 2944 | +} | |
| 2945 | + | |
| 2682 | 2946 | /* |
| 2683 | 2947 | * check hardware's ras ability which will be saved in hw_supported. |
| 2684 | 2948 | * if hardware does not support ras, we can skip some ras initializtion and |
| @@ -2695,49 +2959,13 @@ static void amdgpu_ras_check_supported(struct amdgpu_device *adev) · 10 unmodified lines | ||
| 2695 | 2959 | if (!amdgpu_ras_asic_supported(adev)) |
| 2696 | 2960 | return; |
| 2697 | 2961 | |
| 2698 | − if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) { | |
| 2699 | − if (amdgpu_atomfirmware_mem_ecc_supported(adev)) { | |
| 2700 | − dev_info(adev->dev, "MEM ECC is active.\n"); | |
| 2701 | − adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__UMC | | |
| 2702 | − 1 << AMDGPU_RAS_BLOCK__DF); | |
| 2703 | − } else { | |
| 2704 | − dev_info(adev->dev, "MEM ECC is not presented.\n"); | |
| 2705 | − } | |
| 2706 | − | |
| 2707 | − if (amdgpu_atomfirmware_sram_ecc_supported(adev)) { | |
| 2708 | − dev_info(adev->dev, "SRAM ECC is active.\n"); | |
| 2709 | − if (!amdgpu_sriov_vf(adev)) | |
| 2710 | − adev->ras_hw_enabled |= ~(1 << AMDGPU_RAS_BLOCK__UMC | | |
| 2711 | − 1 << AMDGPU_RAS_BLOCK__DF); | |
| 2712 | − else | |
| 2713 | − adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__PCIE_BIF | | |
| 2714 | − 1 << AMDGPU_RAS_BLOCK__SDMA | | |
| 2715 | − 1 << AMDGPU_RAS_BLOCK__GFX); | |
| 2716 | − | |
| 2717 | − /* VCN/JPEG RAS can be supported on both bare metal and | |
| 2718 | − * SRIOV environment | |
| 2719 | − */ | |
| 2720 | − if (amdgpu_ip_version(adev, VCN_HWIP, 0) == | |
| 2721 | − IP_VERSION(2, 6, 0) || | |
| 2722 | − amdgpu_ip_version(adev, VCN_HWIP, 0) == | |
| 2723 | − IP_VERSION(4, 0, 0) || | |
| 2724 | − amdgpu_ip_version(adev, VCN_HWIP, 0) == | |
| 2725 | − IP_VERSION(4, 0, 3)) | |
| 2726 | − adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__VCN | | |
| 2727 | − 1 << AMDGPU_RAS_BLOCK__JPEG); | |
| 2728 | − else | |
| 2729 | − adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__VCN | | |
| 2730 | − 1 << AMDGPU_RAS_BLOCK__JPEG); | |
| 2962 | + /* query ras capability from psp */ | |
| 2963 | + if (amdgpu_psp_get_ras_capability(&adev->psp)) | |
| 2964 | + goto init_ras_enabled_flag; | |
| 2731 | 2965 | |
| 2732 | − /* | |
| 2733 | − * XGMI RAS is not supported if xgmi num physical nodes | |
| 2734 | − * is zero | |
| 2735 | − */ | |
| 2736 | − if (!adev->gmc.xgmi.num_physical_nodes) | |
| 2737 | − adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__XGMI_WAFL); | |
| 2738 | − } else { | |
| 2739 | − dev_info(adev->dev, "SRAM ECC is not presented.\n"); | |
| 2740 | − } | |
| 2966 | + /* query ras capablity from bios */ | |
| 2967 | + if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) { | |
| 2968 | + amdgpu_ras_query_ras_capablity_from_vbios(adev); | |
| 2741 | 2969 | } else { |
| 2742 | 2970 | /* driver only manages a few IP blocks RAS feature |
| 2743 | 2971 | * when GPU is connected cpu through XGMI */ |
| @@ -2746,13 +2974,21 @@ static void amdgpu_ras_check_supported(struct amdgpu_device *adev) · 2 unmodified lines | ||
| 2746 | 2974 | 1 << AMDGPU_RAS_BLOCK__MMHUB); |
| 2747 | 2975 | } |
| 2748 | 2976 | |
| 2977 | + /* apply asic specific settings (vega20 only for now) */ | |
| 2749 | 2978 | amdgpu_ras_get_quirks(adev); |
| 2750 | 2979 | |
| 2980 | + /* query poison mode from umc/df ip callback */ | |
| 2981 | + amdgpu_ras_query_poison_mode(adev); | |
| 2982 | + | |
| 2983 | +init_ras_enabled_flag: | |
| 2751 | 2984 | /* hw_supported needs to be aligned with RAS block mask. */ |
| 2752 | 2985 | adev->ras_hw_enabled &= AMDGPU_RAS_BLOCK_MASK; |
| 2753 | 2986 | |
| 2754 | 2987 | adev->ras_enabled = amdgpu_ras_enable == 0 ? 0 : |
| 2755 | 2988 | adev->ras_hw_enabled & amdgpu_ras_mask; |
| 2989 | + | |
| 2990 | + /* aca is disabled by default */ | |
| 2991 | + adev->aca.is_enabled = false; | |
| 2756 | 2992 | } |
| 2757 | 2993 | |
| 2758 | 2994 | static void amdgpu_ras_counte_dw(struct work_struct *work) |
| @@ -2780,39 +3016,6 @@ Out: · 21 unmodified lines | ||
| 2780 | 3016 | pm_runtime_put_autosuspend(dev->dev); |
| 2781 | 3017 | } |
| 2782 | 3018 | |
| 2783 | −static void amdgpu_ras_query_poison_mode(struct amdgpu_device *adev) | |
| 2784 | −{ | |
| 2785 | − struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
| 2786 | − bool df_poison, umc_poison; | |
| 2787 | − | |
| 2788 | − /* poison setting is useless on SRIOV guest */ | |
| 2789 | − if (amdgpu_sriov_vf(adev) || !con) | |
| 2790 | − return; | |
| 2791 | − | |
| 2792 | − /* Init poison supported flag, the default value is false */ | |
| 2793 | − if (adev->gmc.xgmi.connected_to_cpu || | |
| 2794 | − adev->gmc.is_app_apu) { | |
| 2795 | − /* enabled by default when GPU is connected to CPU */ | |
| 2796 | − con->poison_supported = true; | |
| 2797 | − } else if (adev->df.funcs && | |
| 2798 | − adev->df.funcs->query_ras_poison_mode && | |
| 2799 | − adev->umc.ras && | |
| 2800 | − adev->umc.ras->query_ras_poison_mode) { | |
| 2801 | − df_poison = | |
| 2802 | − adev->df.funcs->query_ras_poison_mode(adev); | |
| 2803 | − umc_poison = | |
| 2804 | − adev->umc.ras->query_ras_poison_mode(adev); | |
| 2805 | − | |
| 2806 | − /* Only poison is set in both DF and UMC, we can support it */ | |
| 2807 | − if (df_poison && umc_poison) | |
| 2808 | − con->poison_supported = true; | |
| 2809 | − else if (df_poison != umc_poison) | |
| 2810 | − dev_warn(adev->dev, | |
| 2811 | − "Poison setting is inconsistent in DF/UMC(%d:%d)!\n", | |
| 2812 | − df_poison, umc_poison); | |
| 2813 | − } | |
| 2814 | −} | |
| 2815 | − | |
| 2816 | 3019 | static int amdgpu_get_ras_schema(struct amdgpu_device *adev) |
| 2817 | 3020 | { |
| 2818 | 3021 | return amdgpu_ras_is_poison_mode_supported(adev) ? AMDGPU_RAS_ERROR__POISON : 0 | |
| @@ -2917,12 +3120,11 @@ int amdgpu_ras_init(struct amdgpu_device *adev) · 98 unmodified lines | ||
| 2917 | 3120 | goto release_con; |
| 2918 | 3121 | } |
| 2919 | 3122 | |
| 2920 | − amdgpu_ras_query_poison_mode(adev); | |
| 2921 | − | |
| 2922 | 3123 | /* Packed socket_id to ras feature mask bits[31:29] */ |
| 2923 | 3124 | if (adev->smuio.funcs && |
| 2924 | 3125 | adev->smuio.funcs->get_socket_id) |
| 2925 | − con->features |= ((adev->smuio.funcs->get_socket_id(adev)) << 29); | |
| 3126 | + con->features |= ((adev->smuio.funcs->get_socket_id(adev)) << | |
| 3127 | + AMDGPU_RAS_FEATURES_SOCKETID_SHIFT); | |
| 2926 | 3128 | |
| 2927 | 3129 | /* Get RAS schema for particular SOC */ |
| 2928 | 3130 | con->schema = amdgpu_get_ras_schema(adev); |
| @@ -3128,7 +3330,7 @@ void amdgpu_ras_suspend(struct amdgpu_device *adev) · 199 unmodified lines | ||
| 3128 | 3330 | |
| 3129 | 3331 | amdgpu_ras_disable_all_features(adev, 0); |
| 3130 | 3332 | /* Make sure all ras objects are disabled. */ |
| 3131 | − if (con->features) | |
| 3333 | + if (AMDGPU_RAS_GET_FEATURES(con->features)) | |
| 3132 | 3334 | amdgpu_ras_disable_all_features(adev, 1); |
| 3133 | 3335 | } |
| 3134 | 3336 | |
| @@ -3142,15 +3344,29 @@ int amdgpu_ras_late_init(struct amdgpu_device *adev) · 7 unmodified lines | ||
| 3142 | 3344 | if (amdgpu_sriov_vf(adev)) |
| 3143 | 3345 | return 0; |
| 3144 | 3346 | |
| 3145 | − amdgpu_ras_set_mca_debug_mode(adev, false); | |
| 3347 | + if (amdgpu_aca_is_enabled(adev)) { | |
| 3348 | + if (amdgpu_in_reset(adev)) | |
| 3349 | + r = amdgpu_aca_reset(adev); | |
| 3350 | + else | |
| 3351 | + r = amdgpu_aca_init(adev); | |
| 3352 | + if (r) | |
| 3353 | + return r; | |
| 3354 | + | |
| 3355 | + amdgpu_ras_set_aca_debug_mode(adev, false); | |
| 3356 | + } else { | |
| 3357 | + amdgpu_ras_set_mca_debug_mode(adev, false); | |
| 3358 | + } | |
| 3146 | 3359 | |
| 3147 | 3360 | list_for_each_entry_safe(node, tmp, &adev->ras_list, node) { |
| 3148 | − if (!node->ras_obj) { | |
| 3361 | + obj = node->ras_obj; | |
| 3362 | + if (!obj) { | |
| 3149 | 3363 | dev_warn(adev->dev, "Warning: abnormal ras list node.\n"); |
| 3150 | 3364 | continue; |
| 3151 | 3365 | } |
| 3152 | 3366 | |
| 3153 | − obj = node->ras_obj; | |
| 3367 | + if (!amdgpu_ras_is_supported(adev, obj->ras_comm.block)) | |
| 3368 | + continue; | |
| 3369 | + | |
| 3154 | 3370 | if (obj->ras_late_init) { |
| 3155 | 3371 | r = obj->ras_late_init(adev, &obj->ras_comm); |
| 3156 | 3372 | if (r) { |
| @@ -3175,7 +3391,7 @@ int amdgpu_ras_pre_fini(struct amdgpu_device *adev) · 18 unmodified lines | ||
| 3175 | 3391 | |
| 3176 | 3392 | |
| 3177 | 3393 | /* Need disable ras on all IPs here before ip [hw/sw]fini */ |
| 3178 | − if (con->features) | |
| 3394 | + if (AMDGPU_RAS_GET_FEATURES(con->features)) | |
| 3179 | 3395 | amdgpu_ras_disable_all_features(adev, 0); |
| 3180 | 3396 | amdgpu_ras_recovery_fini(adev); |
| 3181 | 3397 | return 0; |
| @@ -3208,10 +3424,13 @@ int amdgpu_ras_fini(struct amdgpu_device *adev) · 26 unmodified lines | ||
| 3208 | 3424 | amdgpu_ras_fs_fini(adev); |
| 3209 | 3425 | amdgpu_ras_interrupt_remove_all(adev); |
| 3210 | 3426 | |
| 3211 | − WARN(con->features, "Feature mask is not cleared"); | |
| 3427 | + if (amdgpu_aca_is_enabled(adev)) | |
| 3428 | + amdgpu_aca_fini(adev); | |
| 3212 | 3429 | |
| 3213 | − if (con->features) | |
| 3214 | − amdgpu_ras_disable_all_features(adev, 1); | |
| 3430 | + WARN(AMDGPU_RAS_GET_FEATURES(con->features), "Feature mask is not cleared"); | |
| 3431 | + | |
| 3432 | + if (AMDGPU_RAS_GET_FEATURES(con->features)) | |
| 3433 | + amdgpu_ras_disable_all_features(adev, 0); | |
| 3215 | 3434 | |
| 3216 | 3435 | cancel_delayed_work_sync(&con->ras_counte_delay_work); |
| 3217 | 3436 | |
| @@ -3425,22 +3644,41 @@ int amdgpu_ras_set_mca_debug_mode(struct amdgpu_device *adev, bool enable) · 207 unmodified lines | ||
| 3425 | 3644 | if (con) { |
| 3426 | 3645 | ret = amdgpu_mca_smu_set_debug_mode(adev, enable); |
| 3427 | 3646 | if (!ret) |
| 3428 | − con->is_mca_debug_mode = enable; | |
| 3647 | + con->is_aca_debug_mode = enable; | |
| 3648 | + } | |
| 3649 | + | |
| 3650 | + return ret; | |
| 3651 | +} | |
| 3652 | + | |
| 3653 | +int amdgpu_ras_set_aca_debug_mode(struct amdgpu_device *adev, bool enable) | |
| 3654 | +{ | |
| 3655 | + struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
| 3656 | + int ret = 0; | |
| 3657 | + | |
| 3658 | + if (con) { | |
| 3659 | + if (amdgpu_aca_is_enabled(adev)) | |
| 3660 | + ret = amdgpu_aca_smu_set_debug_mode(adev, enable); | |
| 3661 | + else | |
| 3662 | + ret = amdgpu_mca_smu_set_debug_mode(adev, enable); | |
| 3663 | + if (!ret) | |
| 3664 | + con->is_aca_debug_mode = enable; | |
| 3429 | 3665 | } |
| 3430 | 3666 | |
| 3431 | 3667 | return ret; |
| 3432 | 3668 | } |
| 3433 | 3669 | |
| 3434 | −bool amdgpu_ras_get_mca_debug_mode(struct amdgpu_device *adev) | |
| 3670 | +bool amdgpu_ras_get_aca_debug_mode(struct amdgpu_device *adev) | |
| 3435 | 3671 | { |
| 3436 | 3672 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
| 3673 | + const struct aca_smu_funcs *smu_funcs = adev->aca.smu_funcs; | |
| 3437 | 3674 | const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs; |
| 3438 | 3675 | |
| 3439 | 3676 | if (!con) |
| 3440 | 3677 | return false; |
| 3441 | 3678 | |
| 3442 | − if (mca_funcs && mca_funcs->mca_set_debug_mode) | |
| 3443 | − return con->is_mca_debug_mode; | |
| 3679 | + if ((amdgpu_aca_is_enabled(adev) && smu_funcs && smu_funcs->set_debug_mode) || | |
| 3680 | + (!amdgpu_aca_is_enabled(adev) && mca_funcs && mca_funcs->mca_set_debug_mode)) | |
| 3681 | + return con->is_aca_debug_mode; | |
| 3444 | 3682 | else |
| 3445 | 3683 | return true; |
| 3446 | 3684 | } |
| @@ -3450,15 +3688,16 @@ bool amdgpu_ras_get_error_query_mode(struct amdgpu_device *adev, · 3 unmodified lines | ||
| 3450 | 3688 | { |
| 3451 | 3689 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
| 3452 | 3690 | const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs; |
| 3691 | + const struct aca_smu_funcs *smu_funcs = adev->aca.smu_funcs; | |
| 3453 | 3692 | |
| 3454 | 3693 | if (!con) { |
| 3455 | 3694 | *error_query_mode = AMDGPU_RAS_INVALID_ERROR_QUERY; |
| 3456 | 3695 | return false; |
| 3457 | 3696 | } |
| 3458 | 3697 | |
| 3459 | − if (mca_funcs && mca_funcs->mca_set_debug_mode) | |
| 3698 | + if ((smu_funcs && smu_funcs->set_debug_mode) || (mca_funcs && mca_funcs->mca_set_debug_mode)) | |
| 3460 | 3699 | *error_query_mode = |
| 3461 | − (con->is_mca_debug_mode) ? AMDGPU_RAS_DIRECT_ERROR_QUERY : AMDGPU_RAS_FIRMWARE_ERROR_QUERY; | |
| 3700 | + (con->is_aca_debug_mode) ? AMDGPU_RAS_DIRECT_ERROR_QUERY : AMDGPU_RAS_FIRMWARE_ERROR_QUERY; | |
| 3462 | 3701 | else |
| 3463 | 3702 | *error_query_mode = AMDGPU_RAS_DIRECT_ERROR_QUERY; |
| 3464 | 3703 | |
| @@ -3699,8 +3938,7 @@ static int ras_err_info_cmp(void *priv, const struct list_head *a, const struct · 234 unmodified lines | ||
| 3699 | 3938 | } |
| 3700 | 3939 | |
| 3701 | 3940 | static struct ras_err_info *amdgpu_ras_error_get_info(struct ras_err_data *err_data, |
| 3702 | − struct amdgpu_smuio_mcm_config_info *mcm_info, | |
| 3703 | − struct ras_err_addr *err_addr) | |
| 3941 | + struct amdgpu_smuio_mcm_config_info *mcm_info) | |
| 3704 | 3942 | { |
| 3705 | 3943 | struct ras_err_node *err_node; |
| 3706 | 3944 | |
| @@ -3712,10 +3950,9 @@ static struct ras_err_info *amdgpu_ras_error_get_info(struct ras_err_data *err_d · 5 unmodified lines | ||
| 3712 | 3950 | if (!err_node) |
| 3713 | 3951 | return NULL; |
| 3714 | 3952 | |
| 3715 | − memcpy(&err_node->err_info.mcm_info, mcm_info, sizeof(*mcm_info)); | |
| 3953 | + INIT_LIST_HEAD(&err_node->err_info.err_addr_list); | |
| 3716 | 3954 | |
| 3717 | − if (err_addr) | |
| 3718 | − memcpy(&err_node->err_info.err_addr, err_addr, sizeof(*err_addr)); | |
| 3955 | + memcpy(&err_node->err_info.mcm_info, mcm_info, sizeof(*mcm_info)); | |
| 3719 | 3956 | |
| 3720 | 3957 | err_data->err_list_count++; |
| 3721 | 3958 | list_add_tail(&err_node->node, &err_data->err_node_list); |
| @@ -3724,6 +3961,29 @@ static struct ras_err_info *amdgpu_ras_error_get_info(struct ras_err_data *err_d · 2 unmodified lines | ||
| 3724 | 3961 | return &err_node->err_info; |
| 3725 | 3962 | } |
| 3726 | 3963 | |
| 3964 | +void amdgpu_ras_add_mca_err_addr(struct ras_err_info *err_info, struct ras_err_addr *err_addr) | |
| 3965 | +{ | |
| 3966 | + struct ras_err_addr *mca_err_addr; | |
| 3967 | + | |
| 3968 | + mca_err_addr = kzalloc(sizeof(*mca_err_addr), GFP_KERNEL); | |
| 3969 | + if (!mca_err_addr) | |
| 3970 | + return; | |
| 3971 | + | |
| 3972 | + INIT_LIST_HEAD(&mca_err_addr->node); | |
| 3973 | + | |
| 3974 | + mca_err_addr->err_status = err_addr->err_status; | |
| 3975 | + mca_err_addr->err_ipid = err_addr->err_ipid; | |
| 3976 | + mca_err_addr->err_addr = err_addr->err_addr; | |
| 3977 | + | |
| 3978 | + list_add_tail(&mca_err_addr->node, &err_info->err_addr_list); | |
| 3979 | +} | |
| 3980 | + | |
| 3981 | +void amdgpu_ras_del_mca_err_addr(struct ras_err_info *err_info, struct ras_err_addr *mca_err_addr) | |
| 3982 | +{ | |
| 3983 | + list_del(&mca_err_addr->node); | |
| 3984 | + kfree(mca_err_addr); | |
| 3985 | +} | |
| 3986 | + | |
| 3727 | 3987 | int amdgpu_ras_error_statistic_ue_count(struct ras_err_data *err_data, |
| 3728 | 3988 | struct amdgpu_smuio_mcm_config_info *mcm_info, |
| 3729 | 3989 | struct ras_err_addr *err_addr, u64 count) |
| @@ -3736,10 +3996,13 @@ int amdgpu_ras_error_statistic_ue_count(struct ras_err_data *err_data, · 6 unmodified lines | ||
| 3736 | 3996 | if (!count) |
| 3737 | 3997 | return 0; |
| 3738 | 3998 | |
| 3739 | − err_info = amdgpu_ras_error_get_info(err_data, mcm_info, err_addr); | |
| 3999 | + err_info = amdgpu_ras_error_get_info(err_data, mcm_info); | |
| 3740 | 4000 | if (!err_info) |
| 3741 | 4001 | return -EINVAL; |
| 3742 | 4002 | |
| 4003 | + if (err_addr && err_addr->err_status) | |
| 4004 | + amdgpu_ras_add_mca_err_addr(err_info, err_addr); | |
| 4005 | + | |
| 3743 | 4006 | err_info->ue_count += count; |
| 3744 | 4007 | err_data->ue_count += count; |
| 3745 | 4008 | |
| @@ -3758,7 +4021,7 @@ int amdgpu_ras_error_statistic_ce_count(struct ras_err_data *err_data, · 12 unmodified lines | ||
| 3758 | 4021 | if (!count) |
| 3759 | 4022 | return 0; |
| 3760 | 4023 | |
| 3761 | − err_info = amdgpu_ras_error_get_info(err_data, mcm_info, err_addr); | |
| 4024 | + err_info = amdgpu_ras_error_get_info(err_data, mcm_info); | |
| 3762 | 4025 | if (!err_info) |
| 3763 | 4026 | return -EINVAL; |
| 3764 | 4027 | |
| @@ -3767,3 +4030,135 @@ int amdgpu_ras_error_statistic_ce_count(struct ras_err_data *err_data, · 2 unmodified lines | ||
| 3767 | 4030 | |
| 3768 | 4031 | return 0; |
| 3769 | 4032 | } |
| 4033 | + | |
| 4034 | +int amdgpu_ras_error_statistic_de_count(struct ras_err_data *err_data, | |
| 4035 | + struct amdgpu_smuio_mcm_config_info *mcm_info, | |
| 4036 | + struct ras_err_addr *err_addr, u64 count) | |
| 4037 | +{ | |
| 4038 | + struct ras_err_info *err_info; | |
| 4039 | + | |
| 4040 | + if (!err_data || !mcm_info) | |
| 4041 | + return -EINVAL; | |
| 4042 | + | |
| 4043 | + if (!count) | |
| 4044 | + return 0; | |
| 4045 | + | |
| 4046 | + err_info = amdgpu_ras_error_get_info(err_data, mcm_info); | |
| 4047 | + if (!err_info) | |
| 4048 | + return -EINVAL; | |
| 4049 | + | |
| 4050 | + if (err_addr && err_addr->err_status) | |
| 4051 | + amdgpu_ras_add_mca_err_addr(err_info, err_addr); | |
| 4052 | + | |
| 4053 | + err_info->de_count += count; | |
| 4054 | + err_data->de_count += count; | |
| 4055 | + | |
| 4056 | + return 0; | |
| 4057 | +} | |
| 4058 | + | |
| 4059 | +#define mmMP0_SMN_C2PMSG_92 0x1609C | |
| 4060 | +#define mmMP0_SMN_C2PMSG_126 0x160BE | |
| 4061 | +static void amdgpu_ras_boot_time_error_reporting(struct amdgpu_device *adev, | |
| 4062 | + u32 instance, u32 boot_error) | |
| 4063 | +{ | |
| 4064 | + u32 socket_id, aid_id, hbm_id; | |
| 4065 | + u32 reg_data; | |
| 4066 | + u64 reg_addr; | |
| 4067 | + | |
| 4068 | + socket_id = AMDGPU_RAS_GPU_ERR_SOCKET_ID(boot_error); | |
| 4069 | + aid_id = AMDGPU_RAS_GPU_ERR_AID_ID(boot_error); | |
| 4070 | + hbm_id = AMDGPU_RAS_GPU_ERR_HBM_ID(boot_error); | |
| 4071 | + | |
| 4072 | + /* The pattern for smn addressing in other SOC could be different from | |
| 4073 | + * the one for aqua_vanjaram. We should revisit the code if the pattern | |
| 4074 | + * is changed. In such case, replace the aqua_vanjaram implementation | |
| 4075 | + * with more common helper */ | |
| 4076 | + reg_addr = (mmMP0_SMN_C2PMSG_92 << 2) + | |
| 4077 | + aqua_vanjaram_encode_ext_smn_addressing(instance); | |
| 4078 | + | |
| 4079 | + reg_data = amdgpu_device_indirect_rreg_ext(adev, reg_addr); | |
| 4080 | + dev_err(adev->dev, "socket: %d, aid: %d, firmware boot failed, fw status is 0x%x\n", | |
| 4081 | + socket_id, aid_id, reg_data); | |
| 4082 | + | |
| 4083 | + if (AMDGPU_RAS_GPU_ERR_MEM_TRAINING(boot_error)) | |
| 4084 | + dev_info(adev->dev, "socket: %d, aid: %d, hbm: %d, memory training failed\n", | |
| 4085 | + socket_id, aid_id, hbm_id); | |
| 4086 | + | |
| 4087 | + if (AMDGPU_RAS_GPU_ERR_FW_LOAD(boot_error)) | |
| 4088 | + dev_info(adev->dev, "socket: %d, aid: %d, firmware load failed at boot time\n", | |
| 4089 | + socket_id, aid_id); | |
| 4090 | + | |
| 4091 | + if (AMDGPU_RAS_GPU_ERR_WAFL_LINK_TRAINING(boot_error)) | |
| 4092 | + dev_info(adev->dev, "socket: %d, aid: %d, wafl link training failed\n", | |
| 4093 | + socket_id, aid_id); | |
| 4094 | + | |
| 4095 | + if (AMDGPU_RAS_GPU_ERR_XGMI_LINK_TRAINING(boot_error)) | |
| 4096 | + dev_info(adev->dev, "socket: %d, aid: %d, xgmi link training failed\n", | |
| 4097 | + socket_id, aid_id); | |
| 4098 | + | |
| 4099 | + if (AMDGPU_RAS_GPU_ERR_USR_CP_LINK_TRAINING(boot_error)) | |
| 4100 | + dev_info(adev->dev, "socket: %d, aid: %d, usr cp link training failed\n", | |
| 4101 | + socket_id, aid_id); | |
| 4102 | + | |
| 4103 | + if (AMDGPU_RAS_GPU_ERR_USR_DP_LINK_TRAINING(boot_error)) | |
| 4104 | + dev_info(adev->dev, "socket: %d, aid: %d, usr dp link training failed\n", | |
| 4105 | + socket_id, aid_id); | |
| 4106 | + | |
| 4107 | + if (AMDGPU_RAS_GPU_ERR_HBM_MEM_TEST(boot_error)) | |
| 4108 | + dev_info(adev->dev, "socket: %d, aid: %d, hbm: %d, hbm memory test failed\n", | |
| 4109 | + socket_id, aid_id, hbm_id); | |
| 4110 | + | |
| 4111 | + if (AMDGPU_RAS_GPU_ERR_HBM_BIST_TEST(boot_error)) | |
| 4112 | + dev_info(adev->dev, "socket: %d, aid: %d, hbm: %d, hbm bist test failed\n", | |
| 4113 | + socket_id, aid_id, hbm_id); | |
| 4114 | +} | |
| 4115 | + | |
| 4116 | +static int amdgpu_ras_wait_for_boot_complete(struct amdgpu_device *adev, | |
| 4117 | + u32 instance, u32 *boot_error) | |
| 4118 | +{ | |
| 4119 | + u32 reg_addr; | |
| 4120 | + u32 reg_data; | |
| 4121 | + int retry_loop; | |
| 4122 | + | |
| 4123 | + reg_addr = (mmMP0_SMN_C2PMSG_92 << 2) + | |
| 4124 | + aqua_vanjaram_encode_ext_smn_addressing(instance); | |
| 4125 | + | |
| 4126 | + for (retry_loop = 0; retry_loop < AMDGPU_RAS_BOOT_STATUS_POLLING_LIMIT; retry_loop++) { | |
| 4127 | + reg_data = amdgpu_device_indirect_rreg_ext(adev, reg_addr); | |
| 4128 | + if ((reg_data & AMDGPU_RAS_BOOT_STATUS_MASK) == AMDGPU_RAS_BOOT_STEADY_STATUS) { | |
| 4129 | + *boot_error = AMDGPU_RAS_BOOT_SUCEESS; | |
| 4130 | + return 0; | |
| 4131 | + } | |
| 4132 | + msleep(1); | |
| 4133 | + } | |
| 4134 | + | |
| 4135 | + /* The pattern for smn addressing in other SOC could be different from | |
| 4136 | + * the one for aqua_vanjaram. We should revisit the code if the pattern | |
| 4137 | + * is changed. In such case, replace the aqua_vanjaram implementation | |
| 4138 | + * with more common helper */ | |
| 4139 | + reg_addr = (mmMP0_SMN_C2PMSG_126 << 2) + | |
| 4140 | + aqua_vanjaram_encode_ext_smn_addressing(instance); | |
| 4141 | + | |
| 4142 | + for (retry_loop = 0; retry_loop < AMDGPU_RAS_BOOT_STATUS_POLLING_LIMIT; retry_loop++) { | |
| 4143 | + reg_data = amdgpu_device_indirect_rreg_ext(adev, reg_addr); | |
| 4144 | + if (AMDGPU_RAS_GPU_ERR_BOOT_STATUS(reg_data)) { | |
| 4145 | + *boot_error = reg_data; | |
| 4146 | + return 0; | |
| 4147 | + } | |
| 4148 | + msleep(1); | |
| 4149 | + } | |
| 4150 | + | |
| 4151 | + *boot_error = reg_data; | |
| 4152 | + return -ETIME; | |
| 4153 | +} | |
| 4154 | + | |
| 4155 | +void amdgpu_ras_query_boot_status(struct amdgpu_device *adev, u32 num_instances) | |
| 4156 | +{ | |
| 4157 | + u32 boot_error = 0; | |
| 4158 | + u32 i; | |
| 4159 | + | |
| 4160 | + for (i = 0; i < num_instances; i++) { | |
| 4161 | + if (amdgpu_ras_wait_for_boot_complete(adev, i, &boot_error)) | |
| 4162 | + amdgpu_ras_boot_time_error_reporting(adev, i, boot_error); | |
| 4163 | + } | |
| 4164 | +} | |
| @@ -29,9 +29,28 @@ · 28 unmodified lines | ||
| 29 | 29 | #include "ta_ras_if.h" |
| 30 | 30 | #include "amdgpu_ras_eeprom.h" |
| 31 | 31 | #include "amdgpu_smuio.h" |
| 32 | +#include "amdgpu_aca.h" | |
| 32 | 33 | |
| 33 | 34 | struct amdgpu_iv_entry; |
| 34 | 35 | |
| 36 | +#define AMDGPU_RAS_GPU_ERR_MEM_TRAINING(x) AMDGPU_GET_REG_FIELD(x, 0, 0) | |
| 37 | +#define AMDGPU_RAS_GPU_ERR_FW_LOAD(x) AMDGPU_GET_REG_FIELD(x, 1, 1) | |
| 38 | +#define AMDGPU_RAS_GPU_ERR_WAFL_LINK_TRAINING(x) AMDGPU_GET_REG_FIELD(x, 2, 2) | |
| 39 | +#define AMDGPU_RAS_GPU_ERR_XGMI_LINK_TRAINING(x) AMDGPU_GET_REG_FIELD(x, 3, 3) | |
| 40 | +#define AMDGPU_RAS_GPU_ERR_USR_CP_LINK_TRAINING(x) AMDGPU_GET_REG_FIELD(x, 4, 4) | |
| 41 | +#define AMDGPU_RAS_GPU_ERR_USR_DP_LINK_TRAINING(x) AMDGPU_GET_REG_FIELD(x, 5, 5) | |
| 42 | +#define AMDGPU_RAS_GPU_ERR_HBM_MEM_TEST(x) AMDGPU_GET_REG_FIELD(x, 6, 6) | |
| 43 | +#define AMDGPU_RAS_GPU_ERR_HBM_BIST_TEST(x) AMDGPU_GET_REG_FIELD(x, 7, 7) | |
| 44 | +#define AMDGPU_RAS_GPU_ERR_SOCKET_ID(x) AMDGPU_GET_REG_FIELD(x, 10, 8) | |
| 45 | +#define AMDGPU_RAS_GPU_ERR_AID_ID(x) AMDGPU_GET_REG_FIELD(x, 12, 11) | |
| 46 | +#define AMDGPU_RAS_GPU_ERR_HBM_ID(x) AMDGPU_GET_REG_FIELD(x, 13, 13) | |
| 47 | +#define AMDGPU_RAS_GPU_ERR_BOOT_STATUS(x) AMDGPU_GET_REG_FIELD(x, 31, 31) | |
| 48 | + | |
| 49 | +#define AMDGPU_RAS_BOOT_STATUS_POLLING_LIMIT 1000 | |
| 50 | +#define AMDGPU_RAS_BOOT_STEADY_STATUS 0xBA | |
| 51 | +#define AMDGPU_RAS_BOOT_STATUS_MASK 0xFF | |
| 52 | +#define AMDGPU_RAS_BOOT_SUCEESS 0x80000000 | |
| 53 | + | |
| 35 | 54 | #define AMDGPU_RAS_FLAG_INIT_BY_VBIOS (0x1 << 0) |
| 36 | 55 | /* position of instance value in sub_block_index of |
| 37 | 56 | * ta_ras_trigger_error_input, the sub block uses lower 12 bits |
| @@ -39,6 +58,12 @@ struct amdgpu_iv_entry; · 1 unmodified line | ||
| 39 | 58 | #define AMDGPU_RAS_INST_MASK 0xfffff000 |
| 40 | 59 | #define AMDGPU_RAS_INST_SHIFT 0xc |
| 41 | 60 | |
| 61 | +#define AMDGPU_RAS_FEATURES_SOCKETID_SHIFT 29 | |
| 62 | +#define AMDGPU_RAS_FEATURES_SOCKETID_MASK 0xe0000000 | |
| 63 | + | |
| 64 | +/* The high three bits indicates socketid */ | |
| 65 | +#define AMDGPU_RAS_GET_FEATURES(val) ((val) & ~AMDGPU_RAS_FEATURES_SOCKETID_MASK) | |
| 66 | + | |
| 42 | 67 | enum amdgpu_ras_block { |
| 43 | 68 | AMDGPU_RAS_BLOCK__UMC = 0, |
| 44 | 69 | AMDGPU_RAS_BLOCK__SDMA, |
| @@ -57,6 +82,8 @@ enum amdgpu_ras_block { · 12 unmodified lines | ||
| 57 | 82 | AMDGPU_RAS_BLOCK__MCA, |
| 58 | 83 | AMDGPU_RAS_BLOCK__VCN, |
| 59 | 84 | AMDGPU_RAS_BLOCK__JPEG, |
| 85 | + AMDGPU_RAS_BLOCK__IH, | |
| 86 | + AMDGPU_RAS_BLOCK__MPIO, | |
| 60 | 87 | |
| 61 | 88 | AMDGPU_RAS_BLOCK__LAST |
| 62 | 89 | }; |
| @@ -441,10 +468,15 @@ struct amdgpu_ras { · 378 unmodified lines | ||
| 441 | 468 | /* Indicates smu whether need update bad channel info */ |
| 442 | 469 | bool update_channel_flag; |
| 443 | 470 | /* Record status of smu mca debug mode */ |
| 444 | − bool is_mca_debug_mode; | |
| 471 | + bool is_aca_debug_mode; | |
| 445 | 472 | |
| 446 | 473 | /* Record special requirements of gpu reset caller */ |
| 447 | 474 | uint32_t gpu_reset_flags; |
| 475 | + | |
| 476 | + struct task_struct *page_retirement_thread; | |
| 477 | + wait_queue_head_t page_retirement_wq; | |
| 478 | + struct mutex page_retirement_lock; | |
| 479 | + atomic_t page_retirement_req_cnt; | |
| 448 | 480 | }; |
| 449 | 481 | |
| 450 | 482 | struct ras_fs_data { |
| @@ -453,6 +485,7 @@ struct ras_fs_data { · 2 unmodified lines | ||
| 453 | 485 | }; |
| 454 | 486 | |
| 455 | 487 | struct ras_err_addr { |
| 488 | + struct list_head node; | |
| 456 | 489 | uint64_t err_status; |
| 457 | 490 | uint64_t err_ipid; |
| 458 | 491 | uint64_t err_addr; |
| @@ -462,7 +495,8 @@ struct ras_err_info { · 3 unmodified lines | ||
| 462 | 495 | struct amdgpu_smuio_mcm_config_info mcm_info; |
| 463 | 496 | u64 ce_count; |
| 464 | 497 | u64 ue_count; |
| 465 | − struct ras_err_addr err_addr; | |
| 498 | + u64 de_count; | |
| 499 | + struct list_head err_addr_list; | |
| 466 | 500 | }; |
| 467 | 501 | |
| 468 | 502 | struct ras_err_node { |
| @@ -473,6 +507,7 @@ struct ras_err_node { · 4 unmodified lines | ||
| 473 | 507 | struct ras_err_data { |
| 474 | 508 | unsigned long ue_count; |
| 475 | 509 | unsigned long ce_count; |
| 510 | + unsigned long de_count; | |
| 476 | 511 | unsigned long err_addr_cnt; |
| 477 | 512 | struct eeprom_table_record *err_addr; |
| 478 | 513 | u32 err_list_count; |
| @@ -529,6 +564,8 @@ struct ras_manager { · 50 unmodified lines | ||
| 529 | 564 | struct ras_ih_data ih_data; |
| 530 | 565 | |
| 531 | 566 | struct ras_err_data err_data; |
| 567 | + | |
| 568 | + struct aca_handle aca_handle; | |
| 532 | 569 | }; |
| 533 | 570 | |
| 534 | 571 | struct ras_badpage { |
| @@ -548,6 +585,7 @@ struct ras_query_if { · 13 unmodified lines | ||
| 548 | 585 | struct ras_common_if head; |
| 549 | 586 | unsigned long ue_count; |
| 550 | 587 | unsigned long ce_count; |
| 588 | + unsigned long de_count; | |
| 551 | 589 | }; |
| 552 | 590 | |
| 553 | 591 | struct ras_inject_if { |
| @@ -781,7 +819,8 @@ struct amdgpu_ras* amdgpu_ras_get_context(struct amdgpu_device *adev); · 227 unmodified lines | ||
| 781 | 819 | int amdgpu_ras_set_context(struct amdgpu_device *adev, struct amdgpu_ras *ras_con); |
| 782 | 820 | |
| 783 | 821 | int amdgpu_ras_set_mca_debug_mode(struct amdgpu_device *adev, bool enable); |
| 784 | −bool amdgpu_ras_get_mca_debug_mode(struct amdgpu_device *adev); | |
| 822 | +int amdgpu_ras_set_aca_debug_mode(struct amdgpu_device *adev, bool enable); | |
| 823 | +bool amdgpu_ras_get_aca_debug_mode(struct amdgpu_device *adev); | |
| 785 | 824 | bool amdgpu_ras_get_error_query_mode(struct amdgpu_device *adev, |
| 786 | 825 | unsigned int *mode); |
| 787 | 826 | |
| @@ -818,5 +857,20 @@ int amdgpu_ras_error_statistic_ce_count(struct ras_err_data *err_data, · 30 unmodified lines | ||
| 818 | 857 | int amdgpu_ras_error_statistic_ue_count(struct ras_err_data *err_data, |
| 819 | 858 | struct amdgpu_smuio_mcm_config_info *mcm_info, |
| 820 | 859 | struct ras_err_addr *err_addr, u64 count); |
| 860 | +int amdgpu_ras_error_statistic_de_count(struct ras_err_data *err_data, | |
| 861 | + struct amdgpu_smuio_mcm_config_info *mcm_info, | |
| 862 | + struct ras_err_addr *err_addr, u64 count); | |
| 863 | +void amdgpu_ras_query_boot_status(struct amdgpu_device *adev, u32 num_instances); | |
| 864 | +int amdgpu_ras_bind_aca(struct amdgpu_device *adev, enum amdgpu_ras_block blk, | |
| 865 | + const struct aca_info *aca_info, void *data); | |
| 866 | +int amdgpu_ras_unbind_aca(struct amdgpu_device *adev, enum amdgpu_ras_block blk); | |
| 867 | + | |
| 868 | +ssize_t amdgpu_ras_aca_sysfs_read(struct device *dev, struct device_attribute *attr, | |
| 869 | + struct aca_handle *handle, char *buf, void *data); | |
| 870 | + | |
| 871 | +void amdgpu_ras_add_mca_err_addr(struct ras_err_info *err_info, | |
| 872 | + struct ras_err_addr *err_addr); | |
| 821 | 873 | |
| 874 | +void amdgpu_ras_del_mca_err_addr(struct ras_err_info *err_info, | |
| 875 | + struct ras_err_addr *mca_err_addr); | |
| 822 | 876 | #endif |
| @@ -635,6 +635,7 @@ int amdgpu_ring_test_helper(struct amdgpu_ring *ring) · 634 unmodified lines | ||
| 635 | 635 | ring->name); |
| 636 | 636 | |
| 637 | 637 | ring->sched.ready = !r; |
| 638 | + | |
| 638 | 639 | return r; |
| 639 | 640 | } |
| 640 | 641 | |
| @@ -717,3 +718,14 @@ void amdgpu_ring_ib_on_emit_de(struct amdgpu_ring *ring) · 76 unmodified lines | ||
| 717 | 718 | if (ring->is_sw_ring) |
| 718 | 719 | amdgpu_sw_ring_ib_mark_offset(ring, AMDGPU_MUX_OFFSET_TYPE_DE); |
| 719 | 720 | } |
| 721 | + | |
| 722 | +bool amdgpu_ring_sched_ready(struct amdgpu_ring *ring) | |
| 723 | +{ | |
| 724 | + if (!ring) | |
| 725 | + return false; | |
| 726 | + | |
| 727 | + if (ring->no_scheduler || !drm_sched_wqueue_ready(&ring->sched)) | |
| 728 | + return false; | |
| 729 | + | |
| 730 | + return true; | |
| 731 | +} | |
| @@ -450,5 +450,5 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, · 449 unmodified lines | ||
| 450 | 450 | int amdgpu_ib_pool_init(struct amdgpu_device *adev); |
| 451 | 451 | void amdgpu_ib_pool_fini(struct amdgpu_device *adev); |
| 452 | 452 | int amdgpu_ib_ring_tests(struct amdgpu_device *adev); |
| 453 | − | |
| 453 | +bool amdgpu_ring_sched_ready(struct amdgpu_ring *ring); | |
| 454 | 454 | #endif |
| @@ -241,7 +241,7 @@ void amdgpu_gfx_rlc_setup_cp_table(struct amdgpu_device *adev) · 240 unmodified lines | ||
| 241 | 241 | table_size = le32_to_cpu(hdr->jt_size); |
| 242 | 242 | } |
| 243 | 243 | |
| 244 | − for (i = 0; i < table_size; i ++) { | |
| 244 | + for (i = 0; i < table_size; i++) { | |
| 245 | 245 | dst_ptr[bo_offset + i] = |
| 246 | 246 | cpu_to_le32(le32_to_cpu(fw_data[table_offset + i])); |
| 247 | 247 | } |
| @@ -169,7 +169,7 @@ struct amdgpu_rlc_funcs { · 168 unmodified lines | ||
| 169 | 169 | void (*stop)(struct amdgpu_device *adev); |
| 170 | 170 | void (*reset)(struct amdgpu_device *adev); |
| 171 | 171 | void (*start)(struct amdgpu_device *adev); |
| 172 | − void (*update_spm_vmid)(struct amdgpu_device *adev, unsigned vmid); | |
| 172 | + void (*update_spm_vmid)(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned vmid); | |
| 173 | 173 | bool (*is_rlcg_access_range)(struct amdgpu_device *adev, uint32_t reg); |
| 174 | 174 | }; |
| 175 | 175 | |
| @@ -35,14 +35,29 @@ · 34 unmodified lines | ||
| 35 | 35 | * counters and VM updates. It has maximum count of 32768 64 bit slots. |
| 36 | 36 | */ |
| 37 | 37 | |
| 38 | +/** | |
| 39 | + * amdgpu_seq64_get_va_base - Get the seq64 va base address | |
| 40 | + * | |
| 41 | + * @adev: amdgpu_device pointer | |
| 42 | + * | |
| 43 | + * Returns: | |
| 44 | + * va base address on success | |
| 45 | + */ | |
| 46 | +static inline u64 amdgpu_seq64_get_va_base(struct amdgpu_device *adev) | |
| 47 | +{ | |
| 48 | + u64 addr = adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT; | |
| 49 | + | |
| 50 | + addr -= AMDGPU_VA_RESERVED_TOP; | |
| 51 | + | |
| 52 | + return addr; | |
| 53 | +} | |
| 54 | + | |
| 38 | 55 | /** |
| 39 | 56 | * amdgpu_seq64_map - Map the seq64 memory to VM |
| 40 | 57 | * |
| 41 | 58 | * @adev: amdgpu_device pointer |
| 42 | 59 | * @vm: vm pointer |
| 43 | 60 | * @bo_va: bo_va pointer |
| 44 | − * @seq64_addr: seq64 vaddr start address | |
| 45 | − * @size: seq64 pool size | |
| 46 | 61 | * |
| 47 | 62 | * Map the seq64 memory to the given VM. |
| 48 | 63 | * |
| @@ -50,11 +65,11 @@ · 1 unmodified line | ||
| 50 | 65 | * 0 on success or a negative error code on failure |
| 51 | 66 | */ |
| 52 | 67 | int amdgpu_seq64_map(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
| 53 | − struct amdgpu_bo_va **bo_va, u64 seq64_addr, | |
| 54 | − uint32_t size) | |
| 68 | + struct amdgpu_bo_va **bo_va) | |
| 55 | 69 | { |
| 56 | 70 | struct amdgpu_bo *bo; |
| 57 | 71 | struct drm_exec exec; |
| 72 | + u64 seq64_addr; | |
| 58 | 73 | int r; |
| 59 | 74 | |
| 60 | 75 | bo = adev->seq64.sbo; |
| @@ -77,9 +92,9 @@ int amdgpu_seq64_map(struct amdgpu_device *adev, struct amdgpu_vm *vm, · 16 unmodified lines | ||
| 77 | 92 | goto error; |
| 78 | 93 | } |
| 79 | 94 | |
| 80 | − r = amdgpu_vm_bo_map(adev, *bo_va, seq64_addr, 0, size, | |
| 81 | − AMDGPU_PTE_READABLE | AMDGPU_PTE_WRITEABLE | | |
| 82 | − AMDGPU_PTE_EXECUTABLE); | |
| 95 | + seq64_addr = amdgpu_seq64_get_va_base(adev); | |
| 96 | + r = amdgpu_vm_bo_map(adev, *bo_va, seq64_addr, 0, AMDGPU_VA_RESERVED_SEQ64_SIZE, | |
| 97 | + AMDGPU_PTE_READABLE); | |
| 83 | 98 | if (r) { |
| 84 | 99 | DRM_ERROR("failed to do bo_map on userq sem, err=%d\n", r); |
| 85 | 100 | amdgpu_vm_bo_del(adev, *bo_va); |
| @@ -144,31 +159,25 @@ error: · 58 unmodified lines | ||
| 144 | 159 | * amdgpu_seq64_alloc - Allocate a 64 bit memory |
| 145 | 160 | * |
| 146 | 161 | * @adev: amdgpu_device pointer |
| 147 | − * @gpu_addr: allocated gpu VA start address | |
| 148 | − * @cpu_addr: allocated cpu VA start address | |
| 162 | + * @va: VA to access the seq in process address space | |
| 163 | + * @cpu_addr: CPU address to access the seq | |
| 149 | 164 | * |
| 150 | 165 | * Alloc a 64 bit memory from seq64 pool. |
| 151 | 166 | * |
| 152 | 167 | * Returns: |
| 153 | 168 | * 0 on success or a negative error code on failure |
| 154 | 169 | */ |
| 155 | −int amdgpu_seq64_alloc(struct amdgpu_device *adev, u64 *gpu_addr, | |
| 156 | − u64 **cpu_addr) | |
| 170 | +int amdgpu_seq64_alloc(struct amdgpu_device *adev, u64 *va, u64 **cpu_addr) | |
| 157 | 171 | { |
| 158 | 172 | unsigned long bit_pos; |
| 159 | − u32 offset; | |
| 160 | 173 | |
| 161 | 174 | bit_pos = find_first_zero_bit(adev->seq64.used, adev->seq64.num_sem); |
| 175 | + if (bit_pos >= adev->seq64.num_sem) | |
| 176 | + return -ENOSPC; | |
| 162 | 177 | |
| 163 | − if (bit_pos < adev->seq64.num_sem) { | |
| 164 | − __set_bit(bit_pos, adev->seq64.used); | |
| 165 | − offset = bit_pos << 6; /* convert to qw offset */ | |
| 166 | − } else { | |
| 167 | − return -EINVAL; | |
| 168 | − } | |
| 169 | − | |
| 170 | − *gpu_addr = offset + AMDGPU_SEQ64_VADDR_START; | |
| 171 | − *cpu_addr = offset + adev->seq64.cpu_base_addr; | |
| 178 | + __set_bit(bit_pos, adev->seq64.used); | |
| 179 | + *va = bit_pos * sizeof(u64) + amdgpu_seq64_get_va_base(adev); | |
| 180 | + *cpu_addr = bit_pos + adev->seq64.cpu_base_addr; | |
| 172 | 181 | |
| 173 | 182 | return 0; |
| 174 | 183 | } |
| @@ -177,20 +186,17 @@ int amdgpu_seq64_alloc(struct amdgpu_device *adev, u64 *gpu_addr, · 2 unmodified lines | ||
| 177 | 186 | * amdgpu_seq64_free - Free the given 64 bit memory |
| 178 | 187 | * |
| 179 | 188 | * @adev: amdgpu_device pointer |
| 180 | − * @gpu_addr: gpu start address to be freed | |
| 189 | + * @va: gpu start address to be freed | |
| 181 | 190 | * |
| 182 | 191 | * Free the given 64 bit memory from seq64 pool. |
| 183 | − * | |
| 184 | 192 | */ |
| 185 | −void amdgpu_seq64_free(struct amdgpu_device *adev, u64 gpu_addr) | |
| 193 | +void amdgpu_seq64_free(struct amdgpu_device *adev, u64 va) | |
| 186 | 194 | { |
| 187 | − u32 offset; | |
| 188 | − | |
| 189 | − offset = gpu_addr - AMDGPU_SEQ64_VADDR_START; | |
| 195 | + unsigned long bit_pos; | |
| 190 | 196 | |
| 191 | − offset >>= 6; | |
| 192 | − if (offset < adev->seq64.num_sem) | |
| 193 | − __clear_bit(offset, adev->seq64.used); | |
| 197 | + bit_pos = (va - amdgpu_seq64_get_va_base(adev)) / sizeof(u64); | |
| 198 | + if (bit_pos < adev->seq64.num_sem) | |
| 199 | + __clear_bit(bit_pos, adev->seq64.used); | |
| 194 | 200 | } |
| 195 | 201 | |
| 196 | 202 | /** |
| @@ -229,7 +235,7 @@ int amdgpu_seq64_init(struct amdgpu_device *adev) · 32 unmodified lines | ||
| 229 | 235 | * AMDGPU_MAX_SEQ64_SLOTS * sizeof(u64) * 8 = AMDGPU_MAX_SEQ64_SLOTS |
| 230 | 236 | * 64bit slots |
| 231 | 237 | */ |
| 232 | − r = amdgpu_bo_create_kernel(adev, AMDGPU_SEQ64_SIZE, | |
| 238 | + r = amdgpu_bo_create_kernel(adev, AMDGPU_VA_RESERVED_SEQ64_SIZE, | |
| 233 | 239 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, |
| 234 | 240 | &adev->seq64.sbo, NULL, |
| 235 | 241 | (void **)&adev->seq64.cpu_base_addr); |
| @@ -238,7 +244,7 @@ int amdgpu_seq64_init(struct amdgpu_device *adev) · 2 unmodified lines | ||
| 238 | 244 | return r; |
| 239 | 245 | } |
| 240 | 246 | |
| 241 | − memset(adev->seq64.cpu_base_addr, 0, AMDGPU_SEQ64_SIZE); | |
| 247 | + memset(adev->seq64.cpu_base_addr, 0, AMDGPU_VA_RESERVED_SEQ64_SIZE); | |
| 242 | 248 | |
| 243 | 249 | adev->seq64.num_sem = AMDGPU_MAX_SEQ64_SLOTS; |
| 244 | 250 | memset(&adev->seq64.used, 0, sizeof(adev->seq64.used)); |
| @@ -25,10 +25,9 @@ · 24 unmodified lines | ||
| 25 | 25 | #ifndef __AMDGPU_SEQ64_H__ |
| 26 | 26 | #define __AMDGPU_SEQ64_H__ |
| 27 | 27 | |
| 28 | −#define AMDGPU_SEQ64_SIZE (2ULL << 20) | |
| 29 | −#define AMDGPU_MAX_SEQ64_SLOTS (AMDGPU_SEQ64_SIZE / (sizeof(u64) * 8)) | |
| 30 | −#define AMDGPU_SEQ64_VADDR_OFFSET 0x50000 | |
| 31 | −#define AMDGPU_SEQ64_VADDR_START (AMDGPU_VA_RESERVED_SIZE + AMDGPU_SEQ64_VADDR_OFFSET) | |
| 28 | +#include "amdgpu_vm.h" | |
| 29 | + | |
| 30 | +#define AMDGPU_MAX_SEQ64_SLOTS (AMDGPU_VA_RESERVED_SEQ64_SIZE / sizeof(u64)) | |
| 32 | 31 | |
| 33 | 32 | struct amdgpu_seq64 { |
| 34 | 33 | struct amdgpu_bo *sbo; |
| @@ -42,7 +41,7 @@ int amdgpu_seq64_init(struct amdgpu_device *adev); · 7 unmodified lines | ||
| 42 | 41 | int amdgpu_seq64_alloc(struct amdgpu_device *adev, u64 *gpu_addr, u64 **cpu_addr); |
| 43 | 42 | void amdgpu_seq64_free(struct amdgpu_device *adev, u64 gpu_addr); |
| 44 | 43 | int amdgpu_seq64_map(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
| 45 | − struct amdgpu_bo_va **bo_va, u64 seq64_addr, uint32_t size); | |
| 44 | + struct amdgpu_bo_va **bo_va); | |
| 46 | 45 | void amdgpu_seq64_unmap(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv); |
| 47 | 46 | |
| 48 | 47 | #endif |
| @@ -102,23 +102,19 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo, · 101 unmodified lines | ||
| 102 | 102 | /* Don't handle scatter gather BOs */ |
| 103 | 103 | if (bo->type == ttm_bo_type_sg) { |
| 104 | 104 | placement->num_placement = 0; |
| 105 | − placement->num_busy_placement = 0; | |
| 106 | 105 | return; |
| 107 | 106 | } |
| 108 | 107 | |
| 109 | 108 | /* Object isn't an AMDGPU object so ignore */ |
| 110 | 109 | if (!amdgpu_bo_is_amdgpu_bo(bo)) { |
| 111 | 110 | placement->placement = &placements; |
| 112 | − placement->busy_placement = &placements; | |
| 113 | 111 | placement->num_placement = 1; |
| 114 | − placement->num_busy_placement = 1; | |
| 115 | 112 | return; |
| 116 | 113 | } |
| 117 | 114 | |
| 118 | 115 | abo = ttm_to_amdgpu_bo(bo); |
| 119 | 116 | if (abo->flags & AMDGPU_GEM_CREATE_DISCARDABLE) { |
| 120 | 117 | placement->num_placement = 0; |
| 121 | − placement->num_busy_placement = 0; | |
| 122 | 118 | return; |
| 123 | 119 | } |
| 124 | 120 | |
| @@ -128,13 +124,13 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo, · 3 unmodified lines | ||
| 128 | 124 | case AMDGPU_PL_OA: |
| 129 | 125 | case AMDGPU_PL_DOORBELL: |
| 130 | 126 | placement->num_placement = 0; |
| 131 | − placement->num_busy_placement = 0; | |
| 132 | 127 | return; |
| 133 | 128 | |
| 134 | 129 | case TTM_PL_VRAM: |
| 135 | 130 | if (!adev->mman.buffer_funcs_enabled) { |
| 136 | 131 | /* Move to system memory */ |
| 137 | 132 | amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); |
| 133 | + | |
| 138 | 134 | } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && |
| 139 | 135 | !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) && |
| 140 | 136 | amdgpu_bo_in_cpu_visible_vram(abo)) { |
| @@ -149,8 +145,7 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo, · 8 unmodified lines | ||
| 149 | 145 | AMDGPU_GEM_DOMAIN_CPU); |
| 150 | 146 | abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; |
| 151 | 147 | abo->placements[0].lpfn = 0; |
| 152 | − abo->placement.busy_placement = &abo->placements[1]; | |
| 153 | − abo->placement.num_busy_placement = 1; | |
| 148 | + abo->placements[0].flags |= TTM_PL_FLAG_DESIRED; | |
| 154 | 149 | } else { |
| 155 | 150 | /* Move to GTT memory */ |
| 156 | 151 | amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT | |
| @@ -966,8 +961,6 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo) · 809 unmodified lines | ||
| 966 | 961 | /* allocate GART space */ |
| 967 | 962 | placement.num_placement = 1; |
| 968 | 963 | placement.placement = &placements; |
| 969 | − placement.num_busy_placement = 1; | |
| 970 | − placement.busy_placement = &placements; | |
| 971 | 964 | placements.fpfn = 0; |
| 972 | 965 | placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT; |
| 973 | 966 | placements.mem_type = TTM_PL_TT; |
| @@ -23,6 +23,7 @@ · 22 unmodified lines | ||
| 23 | 23 | |
| 24 | 24 | #include "amdgpu.h" |
| 25 | 25 | #include "umc_v6_7.h" |
| 26 | +#define MAX_UMC_POISON_POLLING_TIME_SYNC 20 //ms | |
| 26 | 27 | |
| 27 | 28 | static int amdgpu_umc_convert_error_address(struct amdgpu_device *adev, |
| 28 | 29 | struct ras_err_data *err_data, uint64_t err_addr, |
| @@ -85,18 +86,21 @@ out_fini_err_data: · 56 unmodified lines | ||
| 85 | 86 | return ret; |
| 86 | 87 | } |
| 87 | 88 | |
| 88 | −static int amdgpu_umc_do_page_retirement(struct amdgpu_device *adev, | |
| 89 | − void *ras_error_status, | |
| 90 | − struct amdgpu_iv_entry *entry, | |
| 91 | − bool reset) | |
| 89 | +static void amdgpu_umc_handle_bad_pages(struct amdgpu_device *adev, | |
| 90 | + void *ras_error_status) | |
| 92 | 91 | { |
| 93 | 92 | struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; |
| 94 | 93 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
| 94 | + unsigned int error_query_mode; | |
| 95 | 95 | int ret = 0; |
| 96 | + unsigned long err_count; | |
| 96 | 97 | |
| 97 | − kgd2kfd_set_sram_ecc_flag(adev->kfd.dev); | |
| 98 | + amdgpu_ras_get_error_query_mode(adev, &error_query_mode); | |
| 99 | + | |
| 100 | + mutex_lock(&con->page_retirement_lock); | |
| 98 | 101 | ret = amdgpu_dpm_get_ecc_info(adev, (void *)&(con->umc_ecc)); |
| 99 | − if (ret == -EOPNOTSUPP) { | |
| 102 | + if (ret == -EOPNOTSUPP && | |
| 103 | + error_query_mode == AMDGPU_RAS_DIRECT_ERROR_QUERY) { | |
| 100 | 104 | if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && |
| 101 | 105 | adev->umc.ras->ras_block.hw_ops->query_ras_error_count) |
| 102 | 106 | adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, ras_error_status); |
| @@ -120,7 +124,8 @@ static int amdgpu_umc_do_page_retirement(struct amdgpu_device *adev, · 17 unmodified lines | ||
| 120 | 124 | */ |
| 121 | 125 | adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, ras_error_status); |
| 122 | 126 | } |
| 123 | − } else if (!ret) { | |
| 127 | + } else if (error_query_mode == AMDGPU_RAS_FIRMWARE_ERROR_QUERY || | |
| 128 | + (!ret && error_query_mode == AMDGPU_RAS_DIRECT_ERROR_QUERY)) { | |
| 124 | 129 | if (adev->umc.ras && |
| 125 | 130 | adev->umc.ras->ecc_info_query_ras_error_count) |
| 126 | 131 | adev->umc.ras->ecc_info_query_ras_error_count(adev, ras_error_status); |
| @@ -147,16 +152,13 @@ static int amdgpu_umc_do_page_retirement(struct amdgpu_device *adev, · 20 unmodified lines | ||
| 147 | 152 | } |
| 148 | 153 | |
| 149 | 154 | /* only uncorrectable error needs gpu reset */ |
| 150 | − if (err_data->ue_count) { | |
| 151 | − dev_info(adev->dev, "%ld uncorrectable hardware errors " | |
| 152 | − "detected in UMC block\n", | |
| 153 | − err_data->ue_count); | |
| 154 | − | |
| 155 | + if (err_data->ue_count || err_data->de_count) { | |
| 156 | + err_count = err_data->ue_count + err_data->de_count; | |
| 155 | 157 | if ((amdgpu_bad_page_threshold != 0) && |
| 156 | 158 | err_data->err_addr_cnt) { |
| 157 | 159 | amdgpu_ras_add_bad_pages(adev, err_data->err_addr, |
| 158 | 160 | err_data->err_addr_cnt); |
| 159 | − amdgpu_ras_save_bad_pages(adev, &(err_data->ue_count)); | |
| 161 | + amdgpu_ras_save_bad_pages(adev, &err_count); | |
| 160 | 162 | |
| 161 | 163 | amdgpu_dpm_send_hbm_bad_pages_num(adev, con->eeprom_control.ras_num_recs); |
| 162 | 164 | |
| @@ -165,20 +167,87 @@ static int amdgpu_umc_do_page_retirement(struct amdgpu_device *adev, · 2 unmodified lines | ||
| 165 | 167 | con->update_channel_flag = false; |
| 166 | 168 | } |
| 167 | 169 | } |
| 168 | − | |
| 169 | − if (reset) { | |
| 170 | − /* use mode-2 reset for poison consumption */ | |
| 171 | − if (!entry) | |
| 172 | − con->gpu_reset_flags |= AMDGPU_RAS_GPU_RESET_MODE2_RESET; | |
| 173 | − amdgpu_ras_reset_gpu(adev); | |
| 174 | − } | |
| 175 | 170 | } |
| 176 | 171 | |
| 177 | 172 | kfree(err_data->err_addr); |
| 173 | + | |
| 174 | + mutex_unlock(&con->page_retirement_lock); | |
| 175 | +} | |
| 176 | + | |
| 177 | +static int amdgpu_umc_do_page_retirement(struct amdgpu_device *adev, | |
| 178 | + void *ras_error_status, | |
| 179 | + struct amdgpu_iv_entry *entry, | |
| 180 | + bool reset) | |
| 181 | +{ | |
| 182 | + struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; | |
| 183 | + struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
| 184 | + | |
| 185 | + kgd2kfd_set_sram_ecc_flag(adev->kfd.dev); | |
| 186 | + amdgpu_umc_handle_bad_pages(adev, ras_error_status); | |
| 187 | + | |
| 188 | + if (err_data->ue_count && reset) { | |
| 189 | + /* use mode-2 reset for poison consumption */ | |
| 190 | + if (!entry) | |
| 191 | + con->gpu_reset_flags |= AMDGPU_RAS_GPU_RESET_MODE2_RESET; | |
| 192 | + amdgpu_ras_reset_gpu(adev); | |
| 193 | + } | |
| 194 | + | |
| 178 | 195 | return AMDGPU_RAS_SUCCESS; |
| 179 | 196 | } |
| 180 | 197 | |
| 181 | −int amdgpu_umc_poison_handler(struct amdgpu_device *adev, bool reset) | |
| 198 | +int amdgpu_umc_bad_page_polling_timeout(struct amdgpu_device *adev, | |
| 199 | + bool reset, uint32_t timeout_ms) | |
| 200 | +{ | |
| 201 | + struct ras_err_data err_data; | |
| 202 | + struct ras_common_if head = { | |
| 203 | + .block = AMDGPU_RAS_BLOCK__UMC, | |
| 204 | + }; | |
| 205 | + struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head); | |
| 206 | + uint32_t timeout = timeout_ms; | |
| 207 | + | |
| 208 | + memset(&err_data, 0, sizeof(err_data)); | |
| 209 | + amdgpu_ras_error_data_init(&err_data); | |
| 210 | + | |
| 211 | + do { | |
| 212 | + | |
| 213 | + amdgpu_umc_handle_bad_pages(adev, &err_data); | |
| 214 | + | |
| 215 | + if (timeout && !err_data.de_count) { | |
| 216 | + msleep(1); | |
| 217 | + timeout--; | |
| 218 | + } | |
| 219 | + | |
| 220 | + } while (timeout && !err_data.de_count); | |
| 221 | + | |
| 222 | + if (!timeout) | |
| 223 | + dev_warn(adev->dev, "Can't find bad pages\n"); | |
| 224 | + | |
| 225 | + if (err_data.de_count) | |
| 226 | + dev_info(adev->dev, "%ld new deferred hardware errors detected\n", err_data.de_count); | |
| 227 | + | |
| 228 | + if (obj) { | |
| 229 | + obj->err_data.ue_count += err_data.ue_count; | |
| 230 | + obj->err_data.ce_count += err_data.ce_count; | |
| 231 | + obj->err_data.de_count += err_data.de_count; | |
| 232 | + } | |
| 233 | + | |
| 234 | + amdgpu_ras_error_data_fini(&err_data); | |
| 235 | + | |
| 236 | + kgd2kfd_set_sram_ecc_flag(adev->kfd.dev); | |
| 237 | + | |
| 238 | + if (reset) { | |
| 239 | + struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
| 240 | + | |
| 241 | + /* use mode-2 reset for poison consumption */ | |
| 242 | + con->gpu_reset_flags |= AMDGPU_RAS_GPU_RESET_MODE2_RESET; | |
| 243 | + amdgpu_ras_reset_gpu(adev); | |
| 244 | + } | |
| 245 | + | |
| 246 | + return 0; | |
| 247 | +} | |
| 248 | + | |
| 249 | +int amdgpu_umc_poison_handler(struct amdgpu_device *adev, | |
| 250 | + enum amdgpu_ras_block block, bool reset) | |
| 182 | 251 | { |
| 183 | 252 | int ret = AMDGPU_RAS_SUCCESS; |
| 184 | 253 | |
| @@ -195,27 +264,41 @@ int amdgpu_umc_poison_handler(struct amdgpu_device *adev, bool reset) · 10 unmodified lines | ||
| 195 | 264 | } |
| 196 | 265 | |
| 197 | 266 | if (!amdgpu_sriov_vf(adev)) { |
| 198 | − struct ras_err_data err_data; | |
| 199 | − struct ras_common_if head = { | |
| 200 | − .block = AMDGPU_RAS_BLOCK__UMC, | |
| 201 | − }; | |
| 202 | − struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head); | |
| 267 | + if (amdgpu_ip_version(adev, UMC_HWIP, 0) < IP_VERSION(12, 0, 0)) { | |
| 268 | + struct ras_err_data err_data; | |
| 269 | + struct ras_common_if head = { | |
| 270 | + .block = AMDGPU_RAS_BLOCK__UMC, | |
| 271 | + }; | |
| 272 | + struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head); | |
| 273 | + | |
| 274 | + ret = amdgpu_ras_error_data_init(&err_data); | |
| 275 | + if (ret) | |
| 276 | + return ret; | |
| 203 | 277 | |
| 204 | − ret = amdgpu_ras_error_data_init(&err_data); | |
| 205 | − if (ret) | |
| 206 | − return ret; | |
| 278 | + ret = amdgpu_umc_do_page_retirement(adev, &err_data, NULL, reset); | |
| 207 | 279 | |
| 208 | − ret = amdgpu_umc_do_page_retirement(adev, &err_data, NULL, reset); | |
| 280 | + if (ret == AMDGPU_RAS_SUCCESS && obj) { | |
| 281 | + obj->err_data.ue_count += err_data.ue_count; | |
| 282 | + obj->err_data.ce_count += err_data.ce_count; | |
| 283 | + obj->err_data.de_count += err_data.de_count; | |
| 284 | + } | |
| 209 | 285 | |
| 210 | − if (ret == AMDGPU_RAS_SUCCESS && obj) { | |
| 211 | − obj->err_data.ue_count += err_data.ue_count; | |
| 212 | − obj->err_data.ce_count += err_data.ce_count; | |
| 213 | − } | |
| 286 | + amdgpu_ras_error_data_fini(&err_data); | |
| 287 | + } else { | |
| 288 | + if (reset) { | |
| 289 | + amdgpu_umc_bad_page_polling_timeout(adev, | |
| 290 | + reset, MAX_UMC_POISON_POLLING_TIME_SYNC); | |
| 291 | + } else { | |
| 292 | + struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
| 214 | 293 | |
| 215 | − amdgpu_ras_error_data_fini(&err_data); | |
| 294 | + atomic_inc(&con->page_retirement_req_cnt); | |
| 295 | + | |
| 296 | + wake_up(&con->page_retirement_wq); | |
| 297 | + } | |
| 298 | + } | |
| 216 | 299 | } else { |
| 217 | 300 | if (adev->virt.ops && adev->virt.ops->ras_poison_handler) |
| 218 | − adev->virt.ops->ras_poison_handler(adev); | |
| 301 | + adev->virt.ops->ras_poison_handler(adev, block); | |
| 219 | 302 | else |
| 220 | 303 | dev_warn(adev->dev, |
| 221 | 304 | "No ras_poison_handler interface in SRIOV!\n"); |
| @@ -21,7 +21,7 @@ · 20 unmodified lines | ||
| 21 | 21 | #ifndef __AMDGPU_UMC_H__ |
| 22 | 22 | #define __AMDGPU_UMC_H__ |
| 23 | 23 | #include "amdgpu_ras.h" |
| 24 | − | |
| 24 | +#include "amdgpu_mca.h" | |
| 25 | 25 | /* |
| 26 | 26 | * (addr / 256) * 4096, the higher 26 bits in ErrorAddr |
| 27 | 27 | * is the index of 4KB block |
| @@ -64,6 +64,8 @@ struct amdgpu_umc_ras { · 36 unmodified lines | ||
| 64 | 64 | void *ras_error_status); |
| 65 | 65 | void (*ecc_info_query_ras_error_address)(struct amdgpu_device *adev, |
| 66 | 66 | void *ras_error_status); |
| 67 | + bool (*check_ecc_err_status)(struct amdgpu_device *adev, | |
| 68 | + enum amdgpu_mca_error_type type, void *ras_error_status); | |
| 67 | 69 | /* support different eeprom table version for different asic */ |
| 68 | 70 | void (*set_eeprom_table_version)(struct amdgpu_ras_eeprom_table_header *hdr); |
| 69 | 71 | }; |
| @@ -100,7 +102,8 @@ struct amdgpu_umc { · 30 unmodified lines | ||
| 100 | 102 | |
| 101 | 103 | int amdgpu_umc_ras_sw_init(struct amdgpu_device *adev); |
| 102 | 104 | int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block); |
| 103 | −int amdgpu_umc_poison_handler(struct amdgpu_device *adev, bool reset); | |
| 105 | +int amdgpu_umc_poison_handler(struct amdgpu_device *adev, | |
| 106 | + enum amdgpu_ras_block block, bool reset); | |
| 104 | 107 | int amdgpu_umc_process_ecc_irq(struct amdgpu_device *adev, |
| 105 | 108 | struct amdgpu_irq_src *source, |
| 106 | 109 | struct amdgpu_iv_entry *entry); |
| @@ -118,4 +121,7 @@ int amdgpu_umc_page_retirement_mca(struct amdgpu_device *adev, · 11 unmodified lines | ||
| 118 | 121 | |
| 119 | 122 | int amdgpu_umc_loop_channels(struct amdgpu_device *adev, |
| 120 | 123 | umc_func func, void *data); |
| 124 | + | |
| 125 | +int amdgpu_umc_bad_page_polling_timeout(struct amdgpu_device *adev, | |
| 126 | + bool reset, uint32_t timeout_ms); | |
| 121 | 127 | #endif |
| @@ -69,12 +69,12 @@ struct amdgpu_debugfs_gprwave_data { · 68 unmodified lines | ||
| 69 | 69 | }; |
| 70 | 70 | |
| 71 | 71 | enum AMDGPU_DEBUGFS_REGS2_CMDS { |
| 72 | − AMDGPU_DEBUGFS_REGS2_CMD_SET_STATE=0, | |
| 72 | + AMDGPU_DEBUGFS_REGS2_CMD_SET_STATE = 0, | |
| 73 | 73 | AMDGPU_DEBUGFS_REGS2_CMD_SET_STATE_V2, |
| 74 | 74 | }; |
| 75 | 75 | |
| 76 | 76 | enum AMDGPU_DEBUGFS_GPRWAVE_CMDS { |
| 77 | − AMDGPU_DEBUGFS_GPRWAVE_CMD_SET_STATE=0, | |
| 77 | + AMDGPU_DEBUGFS_GPRWAVE_CMD_SET_STATE = 0, | |
| 78 | 78 | }; |
| 79 | 79 | |
| 80 | 80 | //reg2 interface |
| @@ -358,7 +358,7 @@ static int setup_umsch_mm_test(struct amdgpu_device *adev, · 357 unmodified lines | ||
| 358 | 358 | |
| 359 | 359 | memset(test->ring_data_cpu_addr, 0, sizeof(struct umsch_mm_test_ring_data)); |
| 360 | 360 | |
| 361 | − test->ring_data_gpu_addr = AMDGPU_VA_RESERVED_SIZE; | |
| 361 | + test->ring_data_gpu_addr = AMDGPU_VA_RESERVED_BOTTOM; | |
| 362 | 362 | r = map_ring_data(adev, test->vm, test->ring_data_obj, &test->bo_va, |
| 363 | 363 | test->ring_data_gpu_addr, sizeof(struct umsch_mm_test_ring_data)); |
| 364 | 364 | if (r) |
| @@ -1189,7 +1189,7 @@ int amdgpu_vcn_process_poison_irq(struct amdgpu_device *adev, · 1188 unmodified lines | ||
| 1189 | 1189 | amdgpu_ras_interrupt_dispatch(adev, &ih_data); |
| 1190 | 1190 | } else { |
| 1191 | 1191 | if (adev->virt.ops && adev->virt.ops->ras_poison_handler) |
| 1192 | − adev->virt.ops->ras_poison_handler(adev); | |
| 1192 | + adev->virt.ops->ras_poison_handler(adev, ras_if->block); | |
| 1193 | 1193 | else |
| 1194 | 1194 | dev_warn(adev->dev, |
| 1195 | 1195 | "No ras_poison_handler interface in SRIOV for VCN!\n"); |
| @@ -71,59 +71,6 @@ void amdgpu_virt_init_setting(struct amdgpu_device *adev) · 70 unmodified lines | ||
| 71 | 71 | amdgpu_num_kcq = 2; |
| 72 | 72 | } |
| 73 | 73 | |
| 74 | −void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev, | |
| 75 | − uint32_t reg0, uint32_t reg1, | |
| 76 | − uint32_t ref, uint32_t mask, | |
| 77 | − uint32_t xcc_inst) | |
| 78 | −{ | |
| 79 | − struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_inst]; | |
| 80 | − struct amdgpu_ring *ring = &kiq->ring; | |
| 81 | − signed long r, cnt = 0; | |
| 82 | − unsigned long flags; | |
| 83 | − uint32_t seq; | |
| 84 | − | |
| 85 | − if (adev->mes.ring.sched.ready) { | |
| 86 | − amdgpu_mes_reg_write_reg_wait(adev, reg0, reg1, | |
| 87 | − ref, mask); | |
| 88 | − return; | |
| 89 | − } | |
| 90 | − | |
| 91 | − spin_lock_irqsave(&kiq->ring_lock, flags); | |
| 92 | − amdgpu_ring_alloc(ring, 32); | |
| 93 | − amdgpu_ring_emit_reg_write_reg_wait(ring, reg0, reg1, | |
| 94 | − ref, mask); | |
| 95 | − r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); | |
| 96 | − if (r) | |
| 97 | − goto failed_undo; | |
| 98 | − | |
| 99 | − amdgpu_ring_commit(ring); | |
| 100 | − spin_unlock_irqrestore(&kiq->ring_lock, flags); | |
| 101 | − | |
| 102 | − r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); | |
| 103 | − | |
| 104 | − /* don't wait anymore for IRQ context */ | |
| 105 | − if (r < 1 && in_interrupt()) | |
| 106 | − goto failed_kiq; | |
| 107 | − | |
| 108 | − might_sleep(); | |
| 109 | − while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) { | |
| 110 | − | |
| 111 | − msleep(MAX_KIQ_REG_BAILOUT_INTERVAL); | |
| 112 | − r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); | |
| 113 | − } | |
| 114 | − | |
| 115 | − if (cnt > MAX_KIQ_REG_TRY) | |
| 116 | − goto failed_kiq; | |
| 117 | − | |
| 118 | − return; | |
| 119 | − | |
| 120 | −failed_undo: | |
| 121 | − amdgpu_ring_undo(ring); | |
| 122 | − spin_unlock_irqrestore(&kiq->ring_lock, flags); | |
| 123 | −failed_kiq: | |
| 124 | − dev_err(adev->dev, "failed to write reg %x wait reg %x\n", reg0, reg1); | |
| 125 | −} | |
| 126 | − | |
| 127 | 74 | /** |
| 128 | 75 | * amdgpu_virt_request_full_gpu() - request full gpu access |
| 129 | 76 | * @adev: amdgpu device. |
| @@ -303,11 +250,11 @@ static int amdgpu_virt_init_ras_err_handler_data(struct amdgpu_device *adev) · 173 unmodified lines | ||
| 303 | 250 | if (!*data) |
| 304 | 251 | goto data_failure; |
| 305 | 252 | |
| 306 | − bps = kmalloc_array(align_space, sizeof((*data)->bps), GFP_KERNEL); | |
| 253 | + bps = kmalloc_array(align_space, sizeof(*(*data)->bps), GFP_KERNEL); | |
| 307 | 254 | if (!bps) |
| 308 | 255 | goto bps_failure; |
| 309 | 256 | |
| 310 | − bps_bo = kmalloc_array(align_space, sizeof((*data)->bps_bo), GFP_KERNEL); | |
| 257 | + bps_bo = kmalloc_array(align_space, sizeof(*(*data)->bps_bo), GFP_KERNEL); | |
| 311 | 258 | if (!bps_bo) |
| 312 | 259 | goto bps_bo_failure; |
| 313 | 260 | |
| @@ -340,8 +287,10 @@ static void amdgpu_virt_ras_release_bp(struct amdgpu_device *adev) · 26 unmodified lines | ||
| 340 | 287 | |
| 341 | 288 | for (i = data->last_reserved - 1; i >= 0; i--) { |
| 342 | 289 | bo = data->bps_bo[i]; |
| 343 | − amdgpu_bo_free_kernel(&bo, NULL, NULL); | |
| 344 | − data->bps_bo[i] = bo; | |
| 290 | + if (bo) { | |
| 291 | + amdgpu_bo_free_kernel(&bo, NULL, NULL); | |
| 292 | + data->bps_bo[i] = bo; | |
| 293 | + } | |
| 345 | 294 | data->last_reserved = i; |
| 346 | 295 | } |
| 347 | 296 | } |
| @@ -381,6 +330,8 @@ static void amdgpu_virt_ras_reserve_bps(struct amdgpu_device *adev) · 33 unmodified lines | ||
| 381 | 330 | { |
| 382 | 331 | struct amdgpu_virt *virt = &adev->virt; |
| 383 | 332 | struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; |
| 333 | + struct amdgpu_vram_mgr *mgr = &adev->mman.vram_mgr; | |
| 334 | + struct ttm_resource_manager *man = &mgr->manager; | |
| 384 | 335 | struct amdgpu_bo *bo = NULL; |
| 385 | 336 | uint64_t bp; |
| 386 | 337 | int i; |
| @@ -396,12 +347,18 @@ static void amdgpu_virt_ras_reserve_bps(struct amdgpu_device *adev) · 9 unmodified lines | ||
| 396 | 347 | * 2) a ras bad page has been reserved (duplicate error injection |
| 397 | 348 | * for one page); |
| 398 | 349 | */ |
| 399 | − if (amdgpu_bo_create_kernel_at(adev, bp << AMDGPU_GPU_PAGE_SHIFT, | |
| 400 | − AMDGPU_GPU_PAGE_SIZE, | |
| 401 | − &bo, NULL)) | |
| 402 | − DRM_DEBUG("RAS WARN: reserve vram for retired page %llx fail\n", bp); | |
| 403 | − | |
| 404 | − data->bps_bo[i] = bo; | |
| 350 | + if (ttm_resource_manager_used(man)) { | |
| 351 | + amdgpu_vram_mgr_reserve_range(&adev->mman.vram_mgr, | |
| 352 | + bp << AMDGPU_GPU_PAGE_SHIFT, | |
| 353 | + AMDGPU_GPU_PAGE_SIZE); | |
| 354 | + data->bps_bo[i] = NULL; | |
| 355 | + } else { | |
| 356 | + if (amdgpu_bo_create_kernel_at(adev, bp << AMDGPU_GPU_PAGE_SHIFT, | |
| 357 | + AMDGPU_GPU_PAGE_SIZE, | |
| 358 | + &bo, NULL)) | |
| 359 | + DRM_DEBUG("RAS WARN: reserve vram for retired page %llx fail\n", bp); | |
| 360 | + data->bps_bo[i] = bo; | |
| 361 | + } | |
| 405 | 362 | data->last_reserved = i + 1; |
| 406 | 363 | bo = NULL; |
| 407 | 364 | } |
| @@ -88,7 +88,8 @@ struct amdgpu_virt_ops { · 87 unmodified lines | ||
| 88 | 88 | int (*wait_reset)(struct amdgpu_device *adev); |
| 89 | 89 | void (*trans_msg)(struct amdgpu_device *adev, enum idh_request req, |
| 90 | 90 | u32 data1, u32 data2, u32 data3); |
| 91 | − void (*ras_poison_handler)(struct amdgpu_device *adev); | |
| 91 | + void (*ras_poison_handler)(struct amdgpu_device *adev, | |
| 92 | + enum amdgpu_ras_block block); | |
| 92 | 93 | }; |
| 93 | 94 | |
| 94 | 95 | /* |
| @@ -332,10 +333,6 @@ static inline bool is_virtual_machine(void) · 237 unmodified lines | ||
| 332 | 333 | ((adev)->virt.gim_feature & AMDGIM_FEATURE_VCN_RB_DECOUPLE) |
| 333 | 334 | bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev); |
| 334 | 335 | void amdgpu_virt_init_setting(struct amdgpu_device *adev); |
| 335 | −void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev, | |
| 336 | − uint32_t reg0, uint32_t rreg1, | |
| 337 | − uint32_t ref, uint32_t mask, | |
| 338 | − uint32_t xcc_inst); | |
| 339 | 336 | int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init); |
| 340 | 337 | int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init); |
| 341 | 338 | int amdgpu_virt_reset_gpu(struct amdgpu_device *adev); |
| @@ -660,8 +660,7 @@ static const struct amd_ip_funcs amdgpu_vkms_ip_funcs = { · 659 unmodified lines | ||
| 660 | 660 | .set_powergating_state = amdgpu_vkms_set_powergating_state, |
| 661 | 661 | }; |
| 662 | 662 | |
| 663 | −const struct amdgpu_ip_block_version amdgpu_vkms_ip_block = | |
| 664 | −{ | |
| 663 | +const struct amdgpu_ip_block_version amdgpu_vkms_ip_block = { | |
| 665 | 664 | .type = AMD_IP_BLOCK_TYPE_DCE, |
| 666 | 665 | .major = 1, |
| 667 | 666 | .minor = 0, |
| @@ -233,6 +233,22 @@ static void amdgpu_vm_bo_invalidated(struct amdgpu_vm_bo_base *vm_bo) · 232 unmodified lines | ||
| 233 | 233 | spin_unlock(&vm_bo->vm->status_lock); |
| 234 | 234 | } |
| 235 | 235 | |
| 236 | +/** | |
| 237 | + * amdgpu_vm_bo_evicted_user - vm_bo is evicted | |
| 238 | + * | |
| 239 | + * @vm_bo: vm_bo which is evicted | |
| 240 | + * | |
| 241 | + * State for BOs used by user mode queues which are not at the location they | |
| 242 | + * should be. | |
| 243 | + */ | |
| 244 | +static void amdgpu_vm_bo_evicted_user(struct amdgpu_vm_bo_base *vm_bo) | |
| 245 | +{ | |
| 246 | + vm_bo->moved = true; | |
| 247 | + spin_lock(&vm_bo->vm->status_lock); | |
| 248 | + list_move(&vm_bo->vm_status, &vm_bo->vm->evicted_user); | |
| 249 | + spin_unlock(&vm_bo->vm->status_lock); | |
| 250 | +} | |
| 251 | + | |
| 236 | 252 | /** |
| 237 | 253 | * amdgpu_vm_bo_relocated - vm_bo is reloacted |
| 238 | 254 | * |
| @@ -427,21 +443,25 @@ uint64_t amdgpu_vm_generation(struct amdgpu_device *adev, struct amdgpu_vm *vm) · 188 unmodified lines | ||
| 427 | 443 | } |
| 428 | 444 | |
| 429 | 445 | /** |
| 430 | − * amdgpu_vm_validate_pt_bos - validate the page table BOs | |
| 446 | + * amdgpu_vm_validate - validate evicted BOs tracked in the VM | |
| 431 | 447 | * |
| 432 | 448 | * @adev: amdgpu device pointer |
| 433 | 449 | * @vm: vm providing the BOs |
| 450 | + * @ticket: optional reservation ticket used to reserve the VM | |
| 434 | 451 | * @validate: callback to do the validation |
| 435 | 452 | * @param: parameter for the validation callback |
| 436 | 453 | * |
| 437 | − * Validate the page table BOs on command submission if neccessary. | |
| 454 | + * Validate the page table BOs and per-VM BOs on command submission if | |
| 455 | + * necessary. If a ticket is given, also try to validate evicted user queue | |
| 456 | + * BOs. They must already be reserved with the given ticket. | |
| 438 | 457 | * |
| 439 | 458 | * Returns: |
| 440 | 459 | * Validation result. |
| 441 | 460 | */ |
| 442 | −int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, | |
| 443 | − int (*validate)(void *p, struct amdgpu_bo *bo), | |
| 444 | − void *param) | |
| 461 | +int amdgpu_vm_validate(struct amdgpu_device *adev, struct amdgpu_vm *vm, | |
| 462 | + struct ww_acquire_ctx *ticket, | |
| 463 | + int (*validate)(void *p, struct amdgpu_bo *bo), | |
| 464 | + void *param) | |
| 445 | 465 | { |
| 446 | 466 | struct amdgpu_vm_bo_base *bo_base; |
| 447 | 467 | struct amdgpu_bo *shadow; |
| @@ -484,6 +504,28 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, · 36 unmodified lines | ||
| 484 | 504 | } |
| 485 | 505 | spin_lock(&vm->status_lock); |
| 486 | 506 | } |
| 507 | + while (ticket && !list_empty(&vm->evicted_user)) { | |
| 508 | + bo_base = list_first_entry(&vm->evicted_user, | |
| 509 | + struct amdgpu_vm_bo_base, | |
| 510 | + vm_status); | |
| 511 | + spin_unlock(&vm->status_lock); | |
| 512 | + | |
| 513 | + bo = bo_base->bo; | |
| 514 | + | |
| 515 | + if (dma_resv_locking_ctx(bo->tbo.base.resv) != ticket) { | |
| 516 | + pr_warn_ratelimited("Evicted user BO is not reserved in pid %d\n", | |
| 517 | + vm->task_info.pid); | |
| 518 | + return -EINVAL; | |
| 519 | + } | |
| 520 | + | |
| 521 | + r = validate(param, bo); | |
| 522 | + if (r) | |
| 523 | + return r; | |
| 524 | + | |
| 525 | + amdgpu_vm_bo_invalidated(bo_base); | |
| 526 | + | |
| 527 | + spin_lock(&vm->status_lock); | |
| 528 | + } | |
| 487 | 529 | spin_unlock(&vm->status_lock); |
| 488 | 530 | |
| 489 | 531 | amdgpu_vm_eviction_lock(vm); |
| @@ -651,7 +693,7 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, · 161 unmodified lines | ||
| 651 | 693 | amdgpu_gmc_emit_pasid_mapping(ring, job->vmid, job->pasid); |
| 652 | 694 | |
| 653 | 695 | if (spm_update_needed && adev->gfx.rlc.funcs->update_spm_vmid) |
| 654 | − adev->gfx.rlc.funcs->update_spm_vmid(adev, job->vmid); | |
| 696 | + adev->gfx.rlc.funcs->update_spm_vmid(adev, ring, job->vmid); | |
| 655 | 697 | |
| 656 | 698 | if (!ring->is_mes_queue && ring->funcs->emit_gds_switch && |
| 657 | 699 | gds_switch_needed) { |
| @@ -1426,11 +1468,21 @@ int amdgpu_vm_handle_moved(struct amdgpu_device *adev, · 768 unmodified lines | ||
| 1426 | 1468 | } |
| 1427 | 1469 | |
| 1428 | 1470 | r = amdgpu_vm_bo_update(adev, bo_va, clear); |
| 1429 | − if (r) | |
| 1430 | − return r; | |
| 1431 | 1471 | |
| 1432 | 1472 | if (unlock) |
| 1433 | 1473 | dma_resv_unlock(resv); |
| 1474 | + if (r) | |
| 1475 | + return r; | |
| 1476 | + | |
| 1477 | + /* Remember evicted DMABuf imports in compute VMs for later | |
| 1478 | + * validation | |
| 1479 | + */ | |
| 1480 | + if (vm->is_compute_context && | |
| 1481 | + bo_va->base.bo->tbo.base.import_attach && | |
| 1482 | + (!bo_va->base.bo->tbo.resource || | |
| 1483 | + bo_va->base.bo->tbo.resource->mem_type == TTM_PL_SYSTEM)) | |
| 1484 | + amdgpu_vm_bo_evicted_user(&bo_va->base); | |
| 1485 | + | |
| 1434 | 1486 | spin_lock(&vm->status_lock); |
| 1435 | 1487 | } |
| 1436 | 1488 | spin_unlock(&vm->status_lock); |
| @@ -2196,6 +2248,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, · 759 unmodified lines | ||
| 2196 | 2248 | for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) |
| 2197 | 2249 | vm->reserved_vmid[i] = NULL; |
| 2198 | 2250 | INIT_LIST_HEAD(&vm->evicted); |
| 2251 | + INIT_LIST_HEAD(&vm->evicted_user); | |
| 2199 | 2252 | INIT_LIST_HEAD(&vm->relocated); |
| 2200 | 2253 | INIT_LIST_HEAD(&vm->moved); |
| 2201 | 2254 | INIT_LIST_HEAD(&vm->idle); |
| @@ -136,7 +136,11 @@ struct amdgpu_mem_stats; · 135 unmodified lines | ||
| 136 | 136 | #define AMDGPU_IS_MMHUB1(x) ((x) >= AMDGPU_MMHUB1_START && (x) < AMDGPU_MAX_VMHUBS) |
| 137 | 137 | |
| 138 | 138 | /* Reserve 2MB at top/bottom of address space for kernel use */ |
| 139 | −#define AMDGPU_VA_RESERVED_SIZE (2ULL << 20) | |
| 139 | +#define AMDGPU_VA_RESERVED_CSA_SIZE (2ULL << 20) | |
| 140 | +#define AMDGPU_VA_RESERVED_SEQ64_SIZE (2ULL << 20) | |
| 141 | +#define AMDGPU_VA_RESERVED_BOTTOM (2ULL << 20) | |
| 142 | +#define AMDGPU_VA_RESERVED_TOP (AMDGPU_VA_RESERVED_SEQ64_SIZE + \ | |
| 143 | + AMDGPU_VA_RESERVED_CSA_SIZE) | |
| 140 | 144 | |
| 141 | 145 | /* See vm_update_mode */ |
| 142 | 146 | #define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0) |
| @@ -288,9 +292,12 @@ struct amdgpu_vm { · 145 unmodified lines | ||
| 288 | 292 | /* Lock to protect vm_bo add/del/move on all lists of vm */ |
| 289 | 293 | spinlock_t status_lock; |
| 290 | 294 | |
| 291 | − /* BOs who needs a validation */ | |
| 295 | + /* Per-VM and PT BOs who needs a validation */ | |
| 292 | 296 | struct list_head evicted; |
| 293 | 297 | |
| 298 | + /* BOs for user mode queues that need a validation */ | |
| 299 | + struct list_head evicted_user; | |
| 300 | + | |
| 294 | 301 | /* PT BOs which relocated and their parent need an update */ |
| 295 | 302 | struct list_head relocated; |
| 296 | 303 | |
| @@ -434,9 +441,10 @@ int amdgpu_vm_lock_pd(struct amdgpu_vm *vm, struct drm_exec *exec, · 137 unmodified lines | ||
| 434 | 441 | unsigned int num_fences); |
| 435 | 442 | bool amdgpu_vm_ready(struct amdgpu_vm *vm); |
| 436 | 443 | uint64_t amdgpu_vm_generation(struct amdgpu_device *adev, struct amdgpu_vm *vm); |
| 437 | −int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, | |
| 438 | − int (*callback)(void *p, struct amdgpu_bo *bo), | |
| 439 | − void *param); | |
| 444 | +int amdgpu_vm_validate(struct amdgpu_device *adev, struct amdgpu_vm *vm, | |
| 445 | + struct ww_acquire_ctx *ticket, | |
| 446 | + int (*callback)(void *p, struct amdgpu_bo *bo), | |
| 447 | + void *param); | |
| 440 | 448 | int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync); |
| 441 | 449 | int amdgpu_vm_update_pdes(struct amdgpu_device *adev, |
| 442 | 450 | struct amdgpu_vm *vm, bool immediate); |
| @@ -221,8 +221,23 @@ static struct attribute *amdgpu_vram_mgr_attributes[] = { · 220 unmodified lines | ||
| 221 | 221 | NULL |
| 222 | 222 | }; |
| 223 | 223 | |
| 224 | +static umode_t amdgpu_vram_attrs_is_visible(struct kobject *kobj, | |
| 225 | + struct attribute *attr, int i) | |
| 226 | +{ | |
| 227 | + struct device *dev = kobj_to_dev(kobj); | |
| 228 | + struct drm_device *ddev = dev_get_drvdata(dev); | |
| 229 | + struct amdgpu_device *adev = drm_to_adev(ddev); | |
| 230 | + | |
| 231 | + if (attr == &dev_attr_mem_info_vram_vendor.attr && | |
| 232 | + !adev->gmc.vram_vendor) | |
| 233 | + return 0; | |
| 234 | + | |
| 235 | + return attr->mode; | |
| 236 | +} | |
| 237 | + | |
| 224 | 238 | const struct attribute_group amdgpu_vram_mgr_attr_group = { |
| 225 | − .attrs = amdgpu_vram_mgr_attributes | |
| 239 | + .attrs = amdgpu_vram_mgr_attributes, | |
| 240 | + .is_visible = amdgpu_vram_attrs_is_visible | |
| 226 | 241 | }; |
| 227 | 242 | |
| 228 | 243 | /** |
| @@ -1035,15 +1035,74 @@ int amdgpu_xgmi_remove_device(struct amdgpu_device *adev) · 1034 unmodified lines | ||
| 1035 | 1035 | return 0; |
| 1036 | 1036 | } |
| 1037 | 1037 | |
| 1038 | +static int xgmi_v6_4_0_aca_bank_generate_report(struct aca_handle *handle, struct aca_bank *bank, enum aca_error_type type, | |
| 1039 | + struct aca_bank_report *report, void *data) | |
| 1040 | +{ | |
| 1041 | + struct amdgpu_device *adev = handle->adev; | |
| 1042 | + const char *error_str; | |
| 1043 | + u64 status; | |
| 1044 | + int ret, ext_error_code; | |
| 1045 | + | |
| 1046 | + ret = aca_bank_info_decode(bank, &report->info); | |
| 1047 | + if (ret) | |
| 1048 | + return ret; | |
| 1049 | + | |
| 1050 | + status = bank->regs[ACA_REG_IDX_STATUS]; | |
| 1051 | + ext_error_code = ACA_REG__STATUS__ERRORCODEEXT(status); | |
| 1052 | + | |
| 1053 | + error_str = ext_error_code < ARRAY_SIZE(xgmi_v6_4_0_ras_error_code_ext) ? | |
| 1054 | + xgmi_v6_4_0_ras_error_code_ext[ext_error_code] : NULL; | |
| 1055 | + if (error_str) | |
| 1056 | + dev_info(adev->dev, "%s detected\n", error_str); | |
| 1057 | + | |
| 1058 | + if ((type == ACA_ERROR_TYPE_UE && ext_error_code == 0) || | |
| 1059 | + (type == ACA_ERROR_TYPE_CE && ext_error_code == 6)) | |
| 1060 | + report->count[type] = ACA_REG__MISC0__ERRCNT(bank->regs[ACA_REG_IDX_MISC0]); | |
| 1061 | + | |
| 1062 | + return 0; | |
| 1063 | +} | |
| 1064 | + | |
| 1065 | +static const struct aca_bank_ops xgmi_v6_4_0_aca_bank_ops = { | |
| 1066 | + .aca_bank_generate_report = xgmi_v6_4_0_aca_bank_generate_report, | |
| 1067 | +}; | |
| 1068 | + | |
| 1069 | +static const struct aca_info xgmi_v6_4_0_aca_info = { | |
| 1070 | + .hwip = ACA_HWIP_TYPE_PCS_XGMI, | |
| 1071 | + .mask = ACA_ERROR_UE_MASK | ACA_ERROR_CE_MASK, | |
| 1072 | + .bank_ops = &xgmi_v6_4_0_aca_bank_ops, | |
| 1073 | +}; | |
| 1074 | + | |
| 1038 | 1075 | static int amdgpu_xgmi_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) |
| 1039 | 1076 | { |
| 1077 | + int r; | |
| 1078 | + | |
| 1040 | 1079 | if (!adev->gmc.xgmi.supported || |
| 1041 | 1080 | adev->gmc.xgmi.num_physical_nodes == 0) |
| 1042 | 1081 | return 0; |
| 1043 | 1082 | |
| 1044 | 1083 | amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__XGMI_WAFL); |
| 1045 | 1084 | |
| 1046 | − return amdgpu_ras_block_late_init(adev, ras_block); | |
| 1085 | + r = amdgpu_ras_block_late_init(adev, ras_block); | |
| 1086 | + if (r) | |
| 1087 | + return r; | |
| 1088 | + | |
| 1089 | + switch (amdgpu_ip_version(adev, XGMI_HWIP, 0)) { | |
| 1090 | + case IP_VERSION(6, 4, 0): | |
| 1091 | + r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__XGMI_WAFL, | |
| 1092 | + &xgmi_v6_4_0_aca_info, NULL); | |
| 1093 | + if (r) | |
| 1094 | + goto late_fini; | |
| 1095 | + break; | |
| 1096 | + default: | |
| 1097 | + break; | |
| 1098 | + } | |
| 1099 | + | |
| 1100 | + return 0; | |
| 1101 | + | |
| 1102 | +late_fini: | |
| 1103 | + amdgpu_ras_block_late_fini(adev, ras_block); | |
| 1104 | + | |
| 1105 | + return r; | |
| 1047 | 1106 | } |
| 1048 | 1107 | |
| 1049 | 1108 | uint64_t amdgpu_xgmi_get_relative_phy_addr(struct amdgpu_device *adev, |
| @@ -1099,7 +1158,7 @@ static void amdgpu_xgmi_legacy_reset_ras_error_count(struct amdgpu_device *adev) · 49 unmodified lines | ||
| 1099 | 1158 | |
| 1100 | 1159 | static void __xgmi_v6_4_0_reset_error_count(struct amdgpu_device *adev, int xgmi_inst, u64 mca_base) |
| 1101 | 1160 | { |
| 1102 | − WREG64_MCA(xgmi_inst, mca_base, MCA_REG_IDX_STATUS, 0ULL); | |
| 1161 | + WREG64_MCA(xgmi_inst, mca_base, ACA_REG_IDX_STATUS, 0ULL); | |
| 1103 | 1162 | } |
| 1104 | 1163 | |
| 1105 | 1164 | static void xgmi_v6_4_0_reset_error_count(struct amdgpu_device *adev, int xgmi_inst) |
| @@ -1277,12 +1336,12 @@ static void amdgpu_xgmi_legacy_query_ras_error_count(struct amdgpu_device *adev, · 171 unmodified lines | ||
| 1277 | 1336 | err_data->ce_count += ce_cnt; |
| 1278 | 1337 | } |
| 1279 | 1338 | |
| 1280 | −static enum amdgpu_mca_error_type xgmi_v6_4_0_pcs_mca_get_error_type(struct amdgpu_device *adev, u64 status) | |
| 1339 | +static enum aca_error_type xgmi_v6_4_0_pcs_mca_get_error_type(struct amdgpu_device *adev, u64 status) | |
| 1281 | 1340 | { |
| 1282 | 1341 | const char *error_str; |
| 1283 | 1342 | int ext_error_code; |
| 1284 | 1343 | |
| 1285 | − ext_error_code = MCA_REG__STATUS__ERRORCODEEXT(status); | |
| 1344 | + ext_error_code = ACA_REG__STATUS__ERRORCODEEXT(status); | |
| 1286 | 1345 | |
| 1287 | 1346 | error_str = ext_error_code < ARRAY_SIZE(xgmi_v6_4_0_ras_error_code_ext) ? |
| 1288 | 1347 | xgmi_v6_4_0_ras_error_code_ext[ext_error_code] : NULL; |
| @@ -1291,9 +1350,9 @@ static enum amdgpu_mca_error_type xgmi_v6_4_0_pcs_mca_get_error_type(struct amdg · 2 unmodified lines | ||
| 1291 | 1350 | |
| 1292 | 1351 | switch (ext_error_code) { |
| 1293 | 1352 | case 0: |
| 1294 | − return AMDGPU_MCA_ERROR_TYPE_UE; | |
| 1353 | + return ACA_ERROR_TYPE_UE; | |
| 1295 | 1354 | case 6: |
| 1296 | − return AMDGPU_MCA_ERROR_TYPE_CE; | |
| 1355 | + return ACA_ERROR_TYPE_CE; | |
| 1297 | 1356 | default: |
| 1298 | 1357 | return -EINVAL; |
| 1299 | 1358 | } |
| @@ -1307,22 +1366,22 @@ static void __xgmi_v6_4_0_query_error_count(struct amdgpu_device *adev, struct a · 7 unmodified lines | ||
| 1307 | 1366 | int xgmi_inst = mcm_info->die_id; |
| 1308 | 1367 | u64 status = 0; |
| 1309 | 1368 | |
| 1310 | − status = RREG64_MCA(xgmi_inst, mca_base, MCA_REG_IDX_STATUS); | |
| 1311 | − if (!MCA_REG__STATUS__VAL(status)) | |
| 1369 | + status = RREG64_MCA(xgmi_inst, mca_base, ACA_REG_IDX_STATUS); | |
| 1370 | + if (!ACA_REG__STATUS__VAL(status)) | |
| 1312 | 1371 | return; |
| 1313 | 1372 | |
| 1314 | 1373 | switch (xgmi_v6_4_0_pcs_mca_get_error_type(adev, status)) { |
| 1315 | − case AMDGPU_MCA_ERROR_TYPE_UE: | |
| 1374 | + case ACA_ERROR_TYPE_UE: | |
| 1316 | 1375 | amdgpu_ras_error_statistic_ue_count(err_data, mcm_info, NULL, 1ULL); |
| 1317 | 1376 | break; |
| 1318 | − case AMDGPU_MCA_ERROR_TYPE_CE: | |
| 1377 | + case ACA_ERROR_TYPE_CE: | |
| 1319 | 1378 | amdgpu_ras_error_statistic_ce_count(err_data, mcm_info, NULL, 1ULL); |
| 1320 | 1379 | break; |
| 1321 | 1380 | default: |
| 1322 | 1381 | break; |
| 1323 | 1382 | } |
| 1324 | 1383 | |
| 1325 | − WREG64_MCA(xgmi_inst, mca_base, MCA_REG_IDX_STATUS, 0ULL); | |
| 1384 | + WREG64_MCA(xgmi_inst, mca_base, ACA_REG_IDX_STATUS, 0ULL); | |
| 1326 | 1385 | } |
| 1327 | 1386 | |
| 1328 | 1387 | static void xgmi_v6_4_0_query_error_count(struct amdgpu_device *adev, int xgmi_inst, struct ras_err_data *err_data) |
| @@ -62,6 +62,7 @@ · 61 unmodified lines | ||
| 62 | 62 | typedef struct { |
| 63 | 63 | struct atom_context *ctx; |
| 64 | 64 | uint32_t *ps, *ws; |
| 65 | + int ps_size, ws_size; | |
| 65 | 66 | int ps_shift; |
| 66 | 67 | uint16_t start; |
| 67 | 68 | unsigned last_jump; |
| @@ -70,8 +71,8 @@ typedef struct { · 2 unmodified lines | ||
| 70 | 71 | } atom_exec_context; |
| 71 | 72 | |
| 72 | 73 | int amdgpu_atom_debug; |
| 73 | −static int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t *params); | |
| 74 | −int amdgpu_atom_execute_table(struct atom_context *ctx, int index, uint32_t *params); | |
| 74 | +static int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t *params, int params_size); | |
| 75 | +int amdgpu_atom_execute_table(struct atom_context *ctx, int index, uint32_t *params, int params_size); | |
| 75 | 76 | |
| 76 | 77 | static uint32_t atom_arg_mask[8] = |
| 77 | 78 | { 0xFFFFFFFF, 0xFFFF, 0xFFFF00, 0xFFFF0000, 0xFF, 0xFF00, 0xFF0000, |
| @@ -223,7 +224,10 @@ static uint32_t atom_get_src_int(atom_exec_context *ctx, uint8_t attr, · 145 unmodified lines | ||
| 223 | 224 | (*ptr)++; |
| 224 | 225 | /* get_unaligned_le32 avoids unaligned accesses from atombios |
| 225 | 226 | * tables, noticed on a DEC Alpha. */ |
| 226 | − val = get_unaligned_le32((u32 *)&ctx->ps[idx]); | |
| 227 | + if (idx < ctx->ps_size) | |
| 228 | + val = get_unaligned_le32((u32 *)&ctx->ps[idx]); | |
| 229 | + else | |
| 230 | + pr_info("PS index out of range: %i > %i\n", idx, ctx->ps_size); | |
| 227 | 231 | if (print) |
| 228 | 232 | DEBUG("PS[0x%02X,0x%04X]", idx, val); |
| 229 | 233 | break; |
| @@ -261,7 +265,10 @@ static uint32_t atom_get_src_int(atom_exec_context *ctx, uint8_t attr, · 31 unmodified lines | ||
| 261 | 265 | val = gctx->reg_block; |
| 262 | 266 | break; |
| 263 | 267 | default: |
| 264 | − val = ctx->ws[idx]; | |
| 268 | + if (idx < ctx->ws_size) | |
| 269 | + val = ctx->ws[idx]; | |
| 270 | + else | |
| 271 | + pr_info("WS index out of range: %i > %i\n", idx, ctx->ws_size); | |
| 265 | 272 | } |
| 266 | 273 | break; |
| 267 | 274 | case ATOM_ARG_ID: |
| @@ -495,6 +502,10 @@ static void atom_put_dst(atom_exec_context *ctx, int arg, uint8_t attr, · 227 unmodified lines | ||
| 495 | 502 | idx = U8(*ptr); |
| 496 | 503 | (*ptr)++; |
| 497 | 504 | DEBUG("PS[0x%02X]", idx); |
| 505 | + if (idx >= ctx->ps_size) { | |
| 506 | + pr_info("PS index out of range: %i > %i\n", idx, ctx->ps_size); | |
| 507 | + return; | |
| 508 | + } | |
| 498 | 509 | ctx->ps[idx] = cpu_to_le32(val); |
| 499 | 510 | break; |
| 500 | 511 | case ATOM_ARG_WS: |
| @@ -527,6 +538,10 @@ static void atom_put_dst(atom_exec_context *ctx, int arg, uint8_t attr, · 26 unmodified lines | ||
| 527 | 538 | gctx->reg_block = val; |
| 528 | 539 | break; |
| 529 | 540 | default: |
| 541 | + if (idx >= ctx->ws_size) { | |
| 542 | + pr_info("WS index out of range: %i > %i\n", idx, ctx->ws_size); | |
| 543 | + return; | |
| 544 | + } | |
| 530 | 545 | ctx->ws[idx] = val; |
| 531 | 546 | } |
| 532 | 547 | break; |
| @@ -624,7 +639,7 @@ static void atom_op_calltable(atom_exec_context *ctx, int *ptr, int arg) · 91 unmodified lines | ||
| 624 | 639 | else |
| 625 | 640 | SDEBUG(" table: %d\n", idx); |
| 626 | 641 | if (U16(ctx->ctx->cmd_table + 4 + 2 * idx)) |
| 627 | − r = amdgpu_atom_execute_table_locked(ctx->ctx, idx, ctx->ps + ctx->ps_shift); | |
| 642 | + r = amdgpu_atom_execute_table_locked(ctx->ctx, idx, ctx->ps + ctx->ps_shift, ctx->ps_size - ctx->ps_shift); | |
| 628 | 643 | if (r) { |
| 629 | 644 | ctx->abort = true; |
| 630 | 645 | } |
| @@ -1203,7 +1218,7 @@ static struct { · 572 unmodified lines | ||
| 1203 | 1218 | atom_op_div32, ATOM_ARG_WS}, |
| 1204 | 1219 | }; |
| 1205 | 1220 | |
| 1206 | −static int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t *params) | |
| 1221 | +static int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t *params, int params_size) | |
| 1207 | 1222 | { |
| 1208 | 1223 | int base = CU16(ctx->cmd_table + 4 + 2 * index); |
| 1209 | 1224 | int len, ws, ps, ptr; |
| @@ -1225,12 +1240,16 @@ static int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index, · 15 unmodified lines | ||
| 1225 | 1240 | ectx.ps_shift = ps / 4; |
| 1226 | 1241 | ectx.start = base; |
| 1227 | 1242 | ectx.ps = params; |
| 1243 | + ectx.ps_size = params_size; | |
| 1228 | 1244 | ectx.abort = false; |
| 1229 | 1245 | ectx.last_jump = 0; |
| 1230 | − if (ws) | |
| 1246 | + if (ws) { | |
| 1231 | 1247 | ectx.ws = kcalloc(4, ws, GFP_KERNEL); |
| 1232 | − else | |
| 1248 | + ectx.ws_size = ws; | |
| 1249 | + } else { | |
| 1233 | 1250 | ectx.ws = NULL; |
| 1251 | + ectx.ws_size = 0; | |
| 1252 | + } | |
| 1234 | 1253 | |
| 1235 | 1254 | debug_depth++; |
| 1236 | 1255 | while (1) { |
| @@ -1264,7 +1283,7 @@ free: · 27 unmodified lines | ||
| 1264 | 1283 | return ret; |
| 1265 | 1284 | } |
| 1266 | 1285 | |
| 1267 | −int amdgpu_atom_execute_table(struct atom_context *ctx, int index, uint32_t *params) | |
| 1286 | +int amdgpu_atom_execute_table(struct atom_context *ctx, int index, uint32_t *params, int params_size) | |
| 1268 | 1287 | { |
| 1269 | 1288 | int r; |
| 1270 | 1289 | |
| @@ -1280,7 +1299,7 @@ int amdgpu_atom_execute_table(struct atom_context *ctx, int index, uint32_t *par · 9 unmodified lines | ||
| 1280 | 1299 | /* reset divmul */ |
| 1281 | 1300 | ctx->divmul[0] = 0; |
| 1282 | 1301 | ctx->divmul[1] = 0; |
| 1283 | − r = amdgpu_atom_execute_table_locked(ctx, index, params); | |
| 1302 | + r = amdgpu_atom_execute_table_locked(ctx, index, params, params_size); | |
| 1284 | 1303 | mutex_unlock(&ctx->mutex); |
| 1285 | 1304 | return r; |
| 1286 | 1305 | } |
| @@ -1552,7 +1571,7 @@ int amdgpu_atom_asic_init(struct atom_context *ctx) · 265 unmodified lines | ||
| 1552 | 1571 | |
| 1553 | 1572 | if (!CU16(ctx->cmd_table + 4 + 2 * ATOM_CMD_INIT)) |
| 1554 | 1573 | return 1; |
| 1555 | − ret = amdgpu_atom_execute_table(ctx, ATOM_CMD_INIT, ps); | |
| 1574 | + ret = amdgpu_atom_execute_table(ctx, ATOM_CMD_INIT, ps, 16); | |
| 1556 | 1575 | if (ret) |
| 1557 | 1576 | return ret; |
| 1558 | 1577 | |
| @@ -156,7 +156,7 @@ struct atom_context { · 155 unmodified lines | ||
| 156 | 156 | extern int amdgpu_atom_debug; |
| 157 | 157 | |
| 158 | 158 | struct atom_context *amdgpu_atom_parse(struct card_info *card, void *bios); |
| 159 | −int amdgpu_atom_execute_table(struct atom_context *ctx, int index, uint32_t *params); | |
| 159 | +int amdgpu_atom_execute_table(struct atom_context *ctx, int index, uint32_t *params, int params_size); | |
| 160 | 160 | int amdgpu_atom_asic_init(struct atom_context *ctx); |
| 161 | 161 | void amdgpu_atom_destroy(struct atom_context *ctx); |
| 162 | 162 | bool amdgpu_atom_parse_data_header(struct atom_context *ctx, int index, uint16_t *size, |
| @@ -77,7 +77,7 @@ void amdgpu_atombios_crtc_overscan_setup(struct drm_crtc *crtc, · 76 unmodified lines | ||
| 77 | 77 | args.usOverscanTop = cpu_to_le16(amdgpu_crtc->v_border); |
| 78 | 78 | break; |
| 79 | 79 | } |
| 80 | − amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); | |
| 80 | + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); | |
| 81 | 81 | } |
| 82 | 82 | |
| 83 | 83 | void amdgpu_atombios_crtc_scaler_setup(struct drm_crtc *crtc) |
| @@ -106,7 +106,7 @@ void amdgpu_atombios_crtc_scaler_setup(struct drm_crtc *crtc) · 22 unmodified lines | ||
| 106 | 106 | args.ucEnable = ATOM_SCALER_DISABLE; |
| 107 | 107 | break; |
| 108 | 108 | } |
| 109 | − amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); | |
| 109 | + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); | |
| 110 | 110 | } |
| 111 | 111 | |
| 112 | 112 | void amdgpu_atombios_crtc_lock(struct drm_crtc *crtc, int lock) |
| @@ -123,7 +123,7 @@ void amdgpu_atombios_crtc_lock(struct drm_crtc *crtc, int lock) · 10 unmodified lines | ||
| 123 | 123 | args.ucCRTC = amdgpu_crtc->crtc_id; |
| 124 | 124 | args.ucEnable = lock; |
| 125 | 125 | |
| 126 | − amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); | |
| 126 | + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); | |
| 127 | 127 | } |
| 128 | 128 | |
| 129 | 129 | void amdgpu_atombios_crtc_enable(struct drm_crtc *crtc, int state) |
| @@ -139,7 +139,7 @@ void amdgpu_atombios_crtc_enable(struct drm_crtc *crtc, int state) · 9 unmodified lines | ||
| 139 | 139 | args.ucCRTC = amdgpu_crtc->crtc_id; |
| 140 | 140 | args.ucEnable = state; |
| 141 | 141 | |
| 142 | − amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); | |
| 142 | + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); | |
| 143 | 143 | } |
| 144 | 144 | |
| 145 | 145 | void amdgpu_atombios_crtc_blank(struct drm_crtc *crtc, int state) |
| @@ -155,7 +155,7 @@ void amdgpu_atombios_crtc_blank(struct drm_crtc *crtc, int state) · 9 unmodified lines | ||
| 155 | 155 | args.ucCRTC = amdgpu_crtc->crtc_id; |
| 156 | 156 | args.ucBlanking = state; |
| 157 | 157 | |
| 158 | − amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); | |
| 158 | + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); | |
| 159 | 159 | } |
| 160 | 160 | |
| 161 | 161 | void amdgpu_atombios_crtc_powergate(struct drm_crtc *crtc, int state) |
| @@ -171,7 +171,7 @@ void amdgpu_atombios_crtc_powergate(struct drm_crtc *crtc, int state) · 9 unmodified lines | ||
| 171 | 171 | args.ucDispPipeId = amdgpu_crtc->crtc_id; |
| 172 | 172 | args.ucEnable = state; |
| 173 | 173 | |
| 174 | − amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); | |
| 174 | + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); | |
| 175 | 175 | } |
| 176 | 176 | |
| 177 | 177 | void amdgpu_atombios_crtc_powergate_init(struct amdgpu_device *adev) |
| @@ -183,7 +183,7 @@ void amdgpu_atombios_crtc_powergate_init(struct amdgpu_device *adev) · 5 unmodified lines | ||
| 183 | 183 | |
| 184 | 184 | args.ucEnable = ATOM_INIT; |
| 185 | 185 | |
| 186 | − amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); | |
| 186 | + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); | |
| 187 | 187 | } |
| 188 | 188 | |
| 189 | 189 | void amdgpu_atombios_crtc_set_dtd_timing(struct drm_crtc *crtc, |
| @@ -228,7 +228,7 @@ void amdgpu_atombios_crtc_set_dtd_timing(struct drm_crtc *crtc, · 38 unmodified lines | ||
| 228 | 228 | args.susModeMiscInfo.usAccess = cpu_to_le16(misc); |
| 229 | 229 | args.ucCRTC = amdgpu_crtc->crtc_id; |
| 230 | 230 | |
| 231 | − amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); | |
| 231 | + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); | |
| 232 | 232 | } |
| 233 | 233 | |
| 234 | 234 | union atom_enable_ss { |
| @@ -293,7 +293,7 @@ static void amdgpu_atombios_crtc_program_ss(struct amdgpu_device *adev, · 58 unmodified lines | ||
| 293 | 293 | args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step); |
| 294 | 294 | args.v3.ucEnable = enable; |
| 295 | 295 | |
| 296 | − amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); | |
| 296 | + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); | |
| 297 | 297 | } |
| 298 | 298 | |
| 299 | 299 | union adjust_pixel_clock { |
| @@ -395,7 +395,7 @@ static u32 amdgpu_atombios_crtc_adjust_pll(struct drm_crtc *crtc, · 95 unmodified lines | ||
| 395 | 395 | ADJUST_DISPLAY_CONFIG_SS_ENABLE; |
| 396 | 396 | |
| 397 | 397 | amdgpu_atom_execute_table(adev->mode_info.atom_context, |
| 398 | − index, (uint32_t *)&args); | |
| 398 | + index, (uint32_t *)&args, sizeof(args)); | |
| 399 | 399 | adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10; |
| 400 | 400 | break; |
| 401 | 401 | case 3: |
| @@ -428,7 +428,7 @@ static u32 amdgpu_atombios_crtc_adjust_pll(struct drm_crtc *crtc, · 26 unmodified lines | ||
| 428 | 428 | args.v3.sInput.ucExtTransmitterID = 0; |
| 429 | 429 | |
| 430 | 430 | amdgpu_atom_execute_table(adev->mode_info.atom_context, |
| 431 | − index, (uint32_t *)&args); | |
| 431 | + index, (uint32_t *)&args, sizeof(args)); | |
| 432 | 432 | adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10; |
| 433 | 433 | if (args.v3.sOutput.ucRefDiv) { |
| 434 | 434 | amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_FRAC_FB_DIV; |
| @@ -514,7 +514,7 @@ void amdgpu_atombios_crtc_set_disp_eng_pll(struct amdgpu_device *adev, · 79 unmodified lines | ||
| 514 | 514 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
| 515 | 515 | return; |
| 516 | 516 | } |
| 517 | − amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); | |
| 517 | + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); | |
| 518 | 518 | } |
| 519 | 519 | |
| 520 | 520 | union set_dce_clock { |
| @@ -544,7 +544,7 @@ u32 amdgpu_atombios_crtc_set_dce_clock(struct amdgpu_device *adev, · 23 unmodified lines | ||
| 544 | 544 | args.v2_1.asParam.ulDCEClkFreq = cpu_to_le32(freq); /* 10kHz units */ |
| 545 | 545 | args.v2_1.asParam.ucDCEClkType = clk_type; |
| 546 | 546 | args.v2_1.asParam.ucDCEClkSrc = clk_src; |
| 547 | − amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); | |
| 547 | + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); | |
| 548 | 548 | ret_freq = le32_to_cpu(args.v2_1.asParam.ulDCEClkFreq) * 10; |
| 549 | 549 | break; |
| 550 | 550 | default: |
| @@ -740,7 +740,7 @@ void amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc, · 189 unmodified lines | ||
| 740 | 740 | return; |
| 741 | 741 | } |
| 742 | 742 | |
| 743 | − amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); | |
| 743 | + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); | |
| 744 | 744 | } |
| 745 | 745 | |
| 746 | 746 | int amdgpu_atombios_crtc_prepare_pll(struct drm_crtc *crtc, |
| @@ -83,7 +83,7 @@ static int amdgpu_atombios_dp_process_aux_ch(struct amdgpu_i2c_chan *chan, · 82 unmodified lines | ||
| 83 | 83 | args.v2.ucDelay = delay / 10; |
| 84 | 84 | args.v2.ucHPD_ID = chan->rec.hpd; |
| 85 | 85 | |
| 86 | − amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); | |
| 86 | + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); | |
| 87 | 87 | |
| 88 | 88 | *ack = args.v2.ucReplyStatus; |
| 89 | 89 | |
| @@ -301,7 +301,7 @@ static u8 amdgpu_atombios_dp_encoder_service(struct amdgpu_device *adev, · 211 unmodified lines | ||
| 301 | 301 | args.ucLaneNum = lane_num; |
| 302 | 302 | args.ucStatus = 0; |
| 303 | 303 | |
| 304 | − amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); | |
| 304 | + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); | |
| 305 | 305 | return args.ucStatus; |
| 306 | 306 | } |
| 307 | 307 | |
| @@ -335,7 +335,7 @@ amdgpu_atombios_encoder_setup_dac(struct drm_encoder *encoder, int action) · 334 unmodified lines | ||
| 335 | 335 | args.ucDacStandard = ATOM_DAC1_PS2; |
| 336 | 336 | args.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10); |
| 337 | 337 | |
| 338 | − amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); | |
| 338 | + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); | |
| 339 | 339 | |
| 340 | 340 | } |
| 341 | 341 | |
| @@ -432,7 +432,7 @@ amdgpu_atombios_encoder_setup_dvo(struct drm_encoder *encoder, int action) · 90 unmodified lines | ||
| 432 | 432 | break; |
| 433 | 433 | } |
| 434 | 434 | |
| 435 | − amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); | |
| 435 | + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); | |
| 436 | 436 | } |
| 437 | 437 | |
| 438 | 438 | int amdgpu_atombios_encoder_get_encoder_mode(struct drm_encoder *encoder) |
| @@ -732,7 +732,7 @@ amdgpu_atombios_encoder_setup_dig_encoder(struct drm_encoder *encoder, · 293 unmodified lines | ||
| 732 | 732 | break; |
| 733 | 733 | } |
| 734 | 734 | |
| 735 | − amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); | |
| 735 | + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); | |
| 736 | 736 | |
| 737 | 737 | } |
| 738 | 738 | |
| @@ -1136,7 +1136,7 @@ amdgpu_atombios_encoder_setup_dig_transmitter(struct drm_encoder *encoder, int a · 397 unmodified lines | ||
| 1136 | 1136 | break; |
| 1137 | 1137 | } |
| 1138 | 1138 | |
| 1139 | − amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); | |
| 1139 | + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); | |
| 1140 | 1140 | } |
| 1141 | 1141 | |
| 1142 | 1142 | bool |
| @@ -1164,7 +1164,7 @@ amdgpu_atombios_encoder_set_edp_panel_power(struct drm_connector *connector, · 21 unmodified lines | ||
| 1164 | 1164 | |
| 1165 | 1165 | args.v1.ucAction = action; |
| 1166 | 1166 | |
| 1167 | − amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); | |
| 1167 | + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); | |
| 1168 | 1168 | |
| 1169 | 1169 | /* wait for the panel to power up */ |
| 1170 | 1170 | if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) { |
| @@ -1288,7 +1288,7 @@ amdgpu_atombios_encoder_setup_external_encoder(struct drm_encoder *encoder, · 117 unmodified lines | ||
| 1288 | 1288 | DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); |
| 1289 | 1289 | return; |
| 1290 | 1290 | } |
| 1291 | − amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); | |
| 1291 | + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); | |
| 1292 | 1292 | } |
| 1293 | 1293 | |
| 1294 | 1294 | static void |
| @@ -1633,7 +1633,7 @@ amdgpu_atombios_encoder_set_crtc_source(struct drm_encoder *encoder) · 338 unmodified lines | ||
| 1633 | 1633 | return; |
| 1634 | 1634 | } |
| 1635 | 1635 | |
| 1636 | − amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); | |
| 1636 | + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); | |
| 1637 | 1637 | } |
| 1638 | 1638 | |
| 1639 | 1639 | /* This only needs to be called once at startup */ |
| @@ -1706,7 +1706,7 @@ amdgpu_atombios_encoder_dac_load_detect(struct drm_encoder *encoder, · 66 unmodified lines | ||
| 1706 | 1706 | args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; |
| 1707 | 1707 | } |
| 1708 | 1708 | |
| 1709 | − amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); | |
| 1709 | + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); | |
| 1710 | 1710 | |
| 1711 | 1711 | return true; |
| 1712 | 1712 | } else |
| @@ -86,7 +86,7 @@ static int amdgpu_atombios_i2c_process_i2c_ch(struct amdgpu_i2c_chan *chan, · 85 unmodified lines | ||
| 86 | 86 | args.ucSlaveAddr = slave_addr << 1; |
| 87 | 87 | args.ucLineNumber = chan->rec.i2c_id; |
| 88 | 88 | |
| 89 | − amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); | |
| 89 | + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); | |
| 90 | 90 | |
| 91 | 91 | /* error */ |
| 92 | 92 | if (args.ucStatus != HW_ASSISTED_I2C_STATUS_SUCCESS) { |
| @@ -172,5 +172,5 @@ void amdgpu_atombios_i2c_channel_trans(struct amdgpu_device *adev, u8 slave_addr · 79 unmodified lines | ||
| 172 | 172 | args.ucSlaveAddr = slave_addr; |
| 173 | 173 | args.ucLineNumber = line_number; |
| 174 | 174 | |
| 175 | − amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); | |
| 175 | + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); | |
| 176 | 176 | } |
| @@ -204,6 +204,12 @@ static u32 cik_ih_get_wptr(struct amdgpu_device *adev, · 203 unmodified lines | ||
| 204 | 204 | tmp = RREG32(mmIH_RB_CNTL); |
| 205 | 205 | tmp |= IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK; |
| 206 | 206 | WREG32(mmIH_RB_CNTL, tmp); |
| 207 | + | |
| 208 | + /* Unset the CLEAR_OVERFLOW bit immediately so new overflows | |
| 209 | + * can be detected. | |
| 210 | + */ | |
| 211 | + tmp &= ~IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK; | |
| 212 | + WREG32(mmIH_RB_CNTL, tmp); | |
| 207 | 213 | } |
| 208 | 214 | return (wptr & ih->ptr_mask); |
| 209 | 215 | } |
| @@ -21,8 +21,7 @@ · 20 unmodified lines | ||
| 21 | 21 | * |
| 22 | 22 | */ |
| 23 | 23 | |
| 24 | −static const unsigned int gfx9_SECT_CONTEXT_def_1[] = | |
| 25 | −{ | |
| 24 | +static const unsigned int gfx9_SECT_CONTEXT_def_1[] = { | |
| 26 | 25 | 0x00000000, // DB_RENDER_CONTROL |
| 27 | 26 | 0x00000000, // DB_COUNT_CONTROL |
| 28 | 27 | 0x00000000, // DB_DEPTH_VIEW |
| @@ -236,8 +235,7 @@ static const unsigned int gfx9_SECT_CONTEXT_def_1[] = · 207 unmodified lines | ||
| 236 | 235 | 0x00000000, // PA_SC_VPORT_ZMIN_15 |
| 237 | 236 | 0x3f800000, // PA_SC_VPORT_ZMAX_15 |
| 238 | 237 | }; |
| 239 | −static const unsigned int gfx9_SECT_CONTEXT_def_2[] = | |
| 240 | −{ | |
| 238 | +static const unsigned int gfx9_SECT_CONTEXT_def_2[] = { | |
| 241 | 239 | 0x00000000, // PA_SC_SCREEN_EXTENT_CONTROL |
| 242 | 240 | 0x00000000, // PA_SC_TILE_STEERING_OVERRIDE |
| 243 | 241 | 0x00000000, // CP_PERFMON_CNTX_CNTL |
| @@ -521,15 +519,13 @@ static const unsigned int gfx9_SECT_CONTEXT_def_2[] = · 277 unmodified lines | ||
| 521 | 519 | 0x00000000, // CB_MRT6_EPITCH |
| 522 | 520 | 0x00000000, // CB_MRT7_EPITCH |
| 523 | 521 | }; |
| 524 | −static const unsigned int gfx9_SECT_CONTEXT_def_3[] = | |
| 525 | −{ | |
| 522 | +static const unsigned int gfx9_SECT_CONTEXT_def_3[] = { | |
| 526 | 523 | 0x00000000, // PA_CL_POINT_X_RAD |
| 527 | 524 | 0x00000000, // PA_CL_POINT_Y_RAD |
| 528 | 525 | 0x00000000, // PA_CL_POINT_SIZE |
| 529 | 526 | 0x00000000, // PA_CL_POINT_CULL_RAD |
| 530 | 527 | }; |
| 531 | −static const unsigned int gfx9_SECT_CONTEXT_def_4[] = | |
| 532 | −{ | |
| 528 | +static const unsigned int gfx9_SECT_CONTEXT_def_4[] = { | |
| 533 | 529 | 0x00000000, // DB_DEPTH_CONTROL |
| 534 | 530 | 0x00000000, // DB_EQAA |
| 535 | 531 | 0x00000000, // CB_COLOR_CONTROL |
| @@ -688,17 +684,14 @@ static const unsigned int gfx9_SECT_CONTEXT_def_4[] = · 152 unmodified lines | ||
| 688 | 684 | 0x00000000, // VGT_GS_OUT_PRIM_TYPE |
| 689 | 685 | 0x00000000, // IA_ENHANCE |
| 690 | 686 | }; |
| 691 | −static const unsigned int gfx9_SECT_CONTEXT_def_5[] = | |
| 692 | −{ | |
| 687 | +static const unsigned int gfx9_SECT_CONTEXT_def_5[] = { | |
| 693 | 688 | 0x00000000, // WD_ENHANCE |
| 694 | 689 | 0x00000000, // VGT_PRIMITIVEID_EN |
| 695 | 690 | }; |
| 696 | −static const unsigned int gfx9_SECT_CONTEXT_def_6[] = | |
| 697 | −{ | |
| 691 | +static const unsigned int gfx9_SECT_CONTEXT_def_6[] = { | |
| 698 | 692 | 0x00000000, // VGT_PRIMITIVEID_RESET |
| 699 | 693 | }; |
| 700 | −static const unsigned int gfx9_SECT_CONTEXT_def_7[] = | |
| 701 | −{ | |
| 694 | +static const unsigned int gfx9_SECT_CONTEXT_def_7[] = { | |
| 702 | 695 | 0x00000000, // VGT_GS_MAX_PRIMS_PER_SUBGROUP |
| 703 | 696 | 0x00000000, // VGT_DRAW_PAYLOAD_CNTL |
| 704 | 697 | 0, // HOLE |
| @@ -766,8 +759,7 @@ static const unsigned int gfx9_SECT_CONTEXT_def_7[] = · 61 unmodified lines | ||
| 766 | 759 | 0x00000000, // VGT_STRMOUT_CONFIG |
| 767 | 760 | 0x00000000, // VGT_STRMOUT_BUFFER_CONFIG |
| 768 | 761 | }; |
| 769 | −static const unsigned int gfx9_SECT_CONTEXT_def_8[] = | |
| 770 | −{ | |
| 762 | +static const unsigned int gfx9_SECT_CONTEXT_def_8[] = { | |
| 771 | 763 | 0x00000000, // PA_SC_CENTROID_PRIORITY_0 |
| 772 | 764 | 0x00000000, // PA_SC_CENTROID_PRIORITY_1 |
| 773 | 765 | 0x00001000, // PA_SC_LINE_CNTL |
| @@ -924,8 +916,7 @@ static const unsigned int gfx9_SECT_CONTEXT_def_8[] = · 150 unmodified lines | ||
| 924 | 916 | 0x00000000, // CB_COLOR7_DCC_BASE |
| 925 | 917 | 0x00000000, // CB_COLOR7_DCC_BASE_EXT |
| 926 | 918 | }; |
| 927 | −static const struct cs_extent_def gfx9_SECT_CONTEXT_defs[] = | |
| 928 | −{ | |
| 919 | +static const struct cs_extent_def gfx9_SECT_CONTEXT_defs[] = { | |
| 929 | 920 | {gfx9_SECT_CONTEXT_def_1, 0x0000a000, 212 }, |
| 930 | 921 | {gfx9_SECT_CONTEXT_def_2, 0x0000a0d6, 282 }, |
| 931 | 922 | {gfx9_SECT_CONTEXT_def_3, 0x0000a1f5, 4 }, |
| @@ -21,8 +21,7 @@ · 20 unmodified lines | ||
| 21 | 21 | * |
| 22 | 22 | */ |
| 23 | 23 | |
| 24 | −static const u32 si_SECT_CONTEXT_def_1[] = | |
| 25 | −{ | |
| 24 | +static const u32 si_SECT_CONTEXT_def_1[] = { | |
| 26 | 25 | 0x00000000, // DB_RENDER_CONTROL |
| 27 | 26 | 0x00000000, // DB_COUNT_CONTROL |
| 28 | 27 | 0x00000000, // DB_DEPTH_VIEW |
| @@ -236,8 +235,7 @@ static const u32 si_SECT_CONTEXT_def_1[] = · 207 unmodified lines | ||
| 236 | 235 | 0x00000000, // PA_SC_VPORT_ZMIN_15 |
| 237 | 236 | 0x3f800000, // PA_SC_VPORT_ZMAX_15 |
| 238 | 237 | }; |
| 239 | −static const u32 si_SECT_CONTEXT_def_2[] = | |
| 240 | −{ | |
| 238 | +static const u32 si_SECT_CONTEXT_def_2[] = { | |
| 241 | 239 | 0x00000000, // CP_PERFMON_CNTX_CNTL |
| 242 | 240 | 0x00000000, // CP_RINGID |
| 243 | 241 | 0x00000000, // CP_VMID |
| @@ -511,8 +509,7 @@ static const u32 si_SECT_CONTEXT_def_2[] = · 267 unmodified lines | ||
| 511 | 509 | 0x00000000, // CB_BLEND6_CONTROL |
| 512 | 510 | 0x00000000, // CB_BLEND7_CONTROL |
| 513 | 511 | }; |
| 514 | −static const u32 si_SECT_CONTEXT_def_3[] = | |
| 515 | −{ | |
| 512 | +static const u32 si_SECT_CONTEXT_def_3[] = { | |
| 516 | 513 | 0x00000000, // PA_CL_POINT_X_RAD |
| 517 | 514 | 0x00000000, // PA_CL_POINT_Y_RAD |
| 518 | 515 | 0x00000000, // PA_CL_POINT_SIZE |
| @@ -520,8 +517,7 @@ static const u32 si_SECT_CONTEXT_def_3[] = · 1 unmodified line | ||
| 520 | 517 | 0x00000000, // VGT_DMA_BASE_HI |
| 521 | 518 | 0x00000000, // VGT_DMA_BASE |
| 522 | 519 | }; |
| 523 | −static const u32 si_SECT_CONTEXT_def_4[] = | |
| 524 | −{ | |
| 520 | +static const u32 si_SECT_CONTEXT_def_4[] = { | |
| 525 | 521 | 0x00000000, // DB_DEPTH_CONTROL |
| 526 | 522 | 0x00000000, // DB_EQAA |
| 527 | 523 | 0x00000000, // CB_COLOR_CONTROL |
| @@ -680,16 +676,13 @@ static const u32 si_SECT_CONTEXT_def_4[] = · 152 unmodified lines | ||
| 680 | 676 | 0x00000000, // VGT_GS_OUT_PRIM_TYPE |
| 681 | 677 | 0x00000000, // IA_ENHANCE |
| 682 | 678 | }; |
| 683 | −static const u32 si_SECT_CONTEXT_def_5[] = | |
| 684 | −{ | |
| 679 | +static const u32 si_SECT_CONTEXT_def_5[] = { | |
| 685 | 680 | 0x00000000, // VGT_PRIMITIVEID_EN |
| 686 | 681 | }; |
| 687 | −static const u32 si_SECT_CONTEXT_def_6[] = | |
| 688 | −{ | |
| 682 | +static const u32 si_SECT_CONTEXT_def_6[] = { | |
| 689 | 683 | 0x00000000, // VGT_PRIMITIVEID_RESET |
| 690 | 684 | }; |
| 691 | −static const u32 si_SECT_CONTEXT_def_7[] = | |
| 692 | −{ | |
| 685 | +static const u32 si_SECT_CONTEXT_def_7[] = { | |
| 693 | 686 | 0x00000000, // VGT_MULTI_PRIM_IB_RESET_EN |
| 694 | 687 | 0, // HOLE |
| 695 | 688 | 0, // HOLE |
| @@ -924,8 +917,7 @@ static const u32 si_SECT_CONTEXT_def_7[] = · 228 unmodified lines | ||
| 924 | 917 | 0x00000000, // CB_COLOR7_CLEAR_WORD0 |
| 925 | 918 | 0x00000000, // CB_COLOR7_CLEAR_WORD1 |
| 926 | 919 | }; |
| 927 | −static const struct cs_extent_def si_SECT_CONTEXT_defs[] = | |
| 928 | −{ | |
| 920 | +static const struct cs_extent_def si_SECT_CONTEXT_defs[] = { | |
| 929 | 921 | {si_SECT_CONTEXT_def_1, 0x0000a000, 212 }, |
| 930 | 922 | {si_SECT_CONTEXT_def_2, 0x0000a0d8, 272 }, |
| 931 | 923 | {si_SECT_CONTEXT_def_3, 0x0000a1f5, 6 }, |
| @@ -216,6 +216,11 @@ static u32 cz_ih_get_wptr(struct amdgpu_device *adev, · 215 unmodified lines | ||
| 216 | 216 | tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); |
| 217 | 217 | WREG32(mmIH_RB_CNTL, tmp); |
| 218 | 218 | |
| 219 | + /* Unset the CLEAR_OVERFLOW bit immediately so new overflows | |
| 220 | + * can be detected. | |
| 221 | + */ | |
| 222 | + tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0); | |
| 223 | + WREG32(mmIH_RB_CNTL, tmp); | |
| 219 | 224 | |
| 220 | 225 | out: |
| 221 | 226 | return (wptr & ih->ptr_mask); |
| @@ -52,6 +52,7 @@ · 51 unmodified lines | ||
| 52 | 52 | |
| 53 | 53 | static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev); |
| 54 | 54 | static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev); |
| 55 | +static void dce_v10_0_hpd_int_ack(struct amdgpu_device *adev, int hpd); | |
| 55 | 56 | |
| 56 | 57 | static const u32 crtc_offsets[] = { |
| 57 | 58 | CRTC0_REGISTER_OFFSET, |
| @@ -364,6 +365,7 @@ static void dce_v10_0_hpd_init(struct amdgpu_device *adev) · 306 unmodified lines | ||
| 364 | 365 | AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS); |
| 365 | 366 | WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); |
| 366 | 367 | |
| 368 | + dce_v10_0_hpd_int_ack(adev, amdgpu_connector->hpd.hpd); | |
| 367 | 369 | dce_v10_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); |
| 368 | 370 | amdgpu_irq_get(adev, &adev->hpd_irq, |
| 369 | 371 | amdgpu_connector->hpd.hpd); |
| @@ -52,6 +52,7 @@ · 51 unmodified lines | ||
| 52 | 52 | |
| 53 | 53 | static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev); |
| 54 | 54 | static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev); |
| 55 | +static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev, int hpd); | |
| 55 | 56 | |
| 56 | 57 | static const u32 crtc_offsets[] = |
| 57 | 58 | { |
| @@ -388,6 +389,7 @@ static void dce_v11_0_hpd_init(struct amdgpu_device *adev) · 330 unmodified lines | ||
| 388 | 389 | AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS); |
| 389 | 390 | WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); |
| 390 | 391 | |
| 392 | + dce_v11_0_hpd_int_ack(adev, amdgpu_connector->hpd.hpd); | |
| 391 | 393 | dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); |
| 392 | 394 | amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); |
| 393 | 395 | } |
| @@ -273,6 +273,21 @@ static void dce_v6_0_hpd_set_polarity(struct amdgpu_device *adev, · 272 unmodified lines | ||
| 273 | 273 | WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); |
| 274 | 274 | } |
| 275 | 275 | |
| 276 | +static void dce_v6_0_hpd_int_ack(struct amdgpu_device *adev, | |
| 277 | + int hpd) | |
| 278 | +{ | |
| 279 | + u32 tmp; | |
| 280 | + | |
| 281 | + if (hpd >= adev->mode_info.num_hpd) { | |
| 282 | + DRM_DEBUG("invalid hdp %d\n", hpd); | |
| 283 | + return; | |
| 284 | + } | |
| 285 | + | |
| 286 | + tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); | |
| 287 | + tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK; | |
| 288 | + WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); | |
| 289 | +} | |
| 290 | + | |
| 276 | 291 | /** |
| 277 | 292 | * dce_v6_0_hpd_init - hpd setup callback. |
| 278 | 293 | * |
| @@ -312,6 +327,7 @@ static void dce_v6_0_hpd_init(struct amdgpu_device *adev) · 33 unmodified lines | ||
| 312 | 327 | continue; |
| 313 | 328 | } |
| 314 | 329 | |
| 330 | + dce_v6_0_hpd_int_ack(adev, amdgpu_connector->hpd.hpd); | |
| 315 | 331 | dce_v6_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); |
| 316 | 332 | amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); |
| 317 | 333 | } |
| @@ -3089,7 +3105,7 @@ static int dce_v6_0_hpd_irq(struct amdgpu_device *adev, · 2771 unmodified lines | ||
| 3089 | 3105 | struct amdgpu_irq_src *source, |
| 3090 | 3106 | struct amdgpu_iv_entry *entry) |
| 3091 | 3107 | { |
| 3092 | − uint32_t disp_int, mask, tmp; | |
| 3108 | + uint32_t disp_int, mask; | |
| 3093 | 3109 | unsigned hpd; |
| 3094 | 3110 | |
| 3095 | 3111 | if (entry->src_data[0] >= adev->mode_info.num_hpd) { |
| @@ -3102,9 +3118,7 @@ static int dce_v6_0_hpd_irq(struct amdgpu_device *adev, · 6 unmodified lines | ||
| 3102 | 3118 | mask = interrupt_status_offsets[hpd].hpd; |
| 3103 | 3119 | |
| 3104 | 3120 | if (disp_int & mask) { |
| 3105 | − tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); | |
| 3106 | − tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK; | |
| 3107 | − WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); | |
| 3121 | + dce_v6_0_hpd_int_ack(adev, hpd); | |
| 3108 | 3122 | schedule_delayed_work(&adev->hotplug_work, 0); |
| 3109 | 3123 | DRM_DEBUG("IH: HPD%d\n", hpd + 1); |
| 3110 | 3124 | } |
| @@ -265,6 +265,21 @@ static void dce_v8_0_hpd_set_polarity(struct amdgpu_device *adev, · 264 unmodified lines | ||
| 265 | 265 | WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); |
| 266 | 266 | } |
| 267 | 267 | |
| 268 | +static void dce_v8_0_hpd_int_ack(struct amdgpu_device *adev, | |
| 269 | + int hpd) | |
| 270 | +{ | |
| 271 | + u32 tmp; | |
| 272 | + | |
| 273 | + if (hpd >= adev->mode_info.num_hpd) { | |
| 274 | + DRM_DEBUG("invalid hdp %d\n", hpd); | |
| 275 | + return; | |
| 276 | + } | |
| 277 | + | |
| 278 | + tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); | |
| 279 | + tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK; | |
| 280 | + WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); | |
| 281 | +} | |
| 282 | + | |
| 268 | 283 | /** |
| 269 | 284 | * dce_v8_0_hpd_init - hpd setup callback. |
| 270 | 285 | * |
| @@ -304,6 +319,7 @@ static void dce_v8_0_hpd_init(struct amdgpu_device *adev) · 33 unmodified lines | ||
| 304 | 319 | continue; |
| 305 | 320 | } |
| 306 | 321 | |
| 322 | + dce_v8_0_hpd_int_ack(adev, amdgpu_connector->hpd.hpd); | |
| 307 | 323 | dce_v8_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); |
| 308 | 324 | amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); |
| 309 | 325 | } |
| @@ -3177,7 +3193,7 @@ static int dce_v8_0_hpd_irq(struct amdgpu_device *adev, · 2867 unmodified lines | ||
| 3177 | 3193 | struct amdgpu_irq_src *source, |
| 3178 | 3194 | struct amdgpu_iv_entry *entry) |
| 3179 | 3195 | { |
| 3180 | − uint32_t disp_int, mask, tmp; | |
| 3196 | + uint32_t disp_int, mask; | |
| 3181 | 3197 | unsigned hpd; |
| 3182 | 3198 | |
| 3183 | 3199 | if (entry->src_data[0] >= adev->mode_info.num_hpd) { |
| @@ -3190,9 +3206,7 @@ static int dce_v8_0_hpd_irq(struct amdgpu_device *adev, · 6 unmodified lines | ||
| 3190 | 3206 | mask = interrupt_status_offsets[hpd].hpd; |
| 3191 | 3207 | |
| 3192 | 3208 | if (disp_int & mask) { |
| 3193 | − tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); | |
| 3194 | − tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK; | |
| 3195 | − WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); | |
| 3209 | + dce_v8_0_hpd_int_ack(adev, hpd); | |
| 3196 | 3210 | schedule_delayed_work(&adev->hotplug_work, 0); |
| 3197 | 3211 | DRM_DEBUG("IH: HPD%d\n", hpd + 1); |
| 3198 | 3212 | } |
| @@ -4027,8 +4027,6 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) · 4026 unmodified lines | ||
| 4027 | 4027 | err = 0; |
| 4028 | 4028 | adev->gfx.mec2_fw = NULL; |
| 4029 | 4029 | } |
| 4030 | − amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2); | |
| 4031 | − amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT); | |
| 4032 | 4030 | |
| 4033 | 4031 | gfx_v10_0_check_fw_write_wait(adev); |
| 4034 | 4032 | out: |
| @@ -6589,7 +6587,7 @@ static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m, · 2554 unmodified lines | ||
| 6589 | 6587 | #ifdef __BIG_ENDIAN |
| 6590 | 6588 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); |
| 6591 | 6589 | #endif |
| 6592 | − tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); | |
| 6590 | + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); | |
| 6593 | 6591 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, |
| 6594 | 6592 | prop->allow_tunneling); |
| 6595 | 6593 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); |
| @@ -7949,7 +7947,7 @@ static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev, · 1353 unmodified lines | ||
| 7949 | 7947 | WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data); |
| 7950 | 7948 | } |
| 7951 | 7949 | |
| 7952 | −static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned int vmid) | |
| 7950 | +static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned int vmid) | |
| 7953 | 7951 | { |
| 7954 | 7952 | amdgpu_gfx_off_ctrl(adev, false); |
| 7955 | 7953 | |
| @@ -107,23 +107,6 @@ static const struct soc15_reg_golden golden_settings_gc_11_0_1[] = · 106 unmodified lines | ||
| 107 | 107 | SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL2, 0xfcffffff, 0x0000000a) |
| 108 | 108 | }; |
| 109 | 109 | |
| 110 | −static const struct soc15_reg_golden golden_settings_gc_11_5_0[] = { | |
| 111 | − SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_DEBUG5, 0xffffffff, 0x00000800), | |
| 112 | − SOC15_REG_GOLDEN_VALUE(GC, 0, regGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242), | |
| 113 | − SOC15_REG_GOLDEN_VALUE(GC, 0, regGCR_GENERAL_CNTL, 0x1ff1ffff, 0x00000500), | |
| 114 | − SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), | |
| 115 | − SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), | |
| 116 | − SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL, 0xffffffff, 0xf37fff3f), | |
| 117 | − SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL3, 0xfffffffb, 0x00f40188), | |
| 118 | − SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL4, 0xf0ffffff, 0x80009007), | |
| 119 | − SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_CL_ENHANCE, 0xf1ffffff, 0x00880007), | |
| 120 | − SOC15_REG_GOLDEN_VALUE(GC, 0, regPC_CONFIG_CNTL_1, 0xffffffff, 0x00010000), | |
| 121 | − SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL_AUX, 0xf7f7ffff, 0x01030000), | |
| 122 | − SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL2, 0x007f0000, 0x00000000), | |
| 123 | − SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL2, 0xffcfffff, 0x0000200a), | |
| 124 | − SOC15_REG_GOLDEN_VALUE(GC, 0, regUTCL1_CTRL_2, 0xffffffff, 0x0000048f) | |
| 125 | −}; | |
| 126 | − | |
| 127 | 110 | #define DEFAULT_SH_MEM_CONFIG \ |
| 128 | 111 | ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ |
| 129 | 112 | (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ |
| @@ -304,11 +287,6 @@ static void gfx_v11_0_init_golden_registers(struct amdgpu_device *adev) · 174 unmodified lines | ||
| 304 | 287 | golden_settings_gc_11_0_1, |
| 305 | 288 | (const u32)ARRAY_SIZE(golden_settings_gc_11_0_1)); |
| 306 | 289 | break; |
| 307 | − case IP_VERSION(11, 5, 0): | |
| 308 | − soc15_program_register_sequence(adev, | |
| 309 | − golden_settings_gc_11_5_0, | |
| 310 | − (const u32)ARRAY_SIZE(golden_settings_gc_11_5_0)); | |
| 311 | − break; | |
| 312 | 290 | default: |
| 313 | 291 | break; |
| 314 | 292 | } |
| @@ -749,7 +727,7 @@ static int gfx_v11_0_rlc_init(struct amdgpu_device *adev) · 434 unmodified lines | ||
| 749 | 727 | |
| 750 | 728 | /* init spm vmid with 0xf */ |
| 751 | 729 | if (adev->gfx.rlc.funcs->update_spm_vmid) |
| 752 | − adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); | |
| 730 | + adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); | |
| 753 | 731 | |
| 754 | 732 | return 0; |
| 755 | 733 | } |
| @@ -3846,7 +3824,7 @@ static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m, · 3090 unmodified lines | ||
| 3846 | 3824 | (order_base_2(prop->queue_size / 4) - 1)); |
| 3847 | 3825 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, |
| 3848 | 3826 | (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); |
| 3849 | − tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); | |
| 3827 | + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); | |
| 3850 | 3828 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, |
| 3851 | 3829 | prop->allow_tunneling); |
| 3852 | 3830 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); |
| @@ -5049,7 +5027,7 @@ static int gfx_v11_0_update_gfx_clock_gating(struct amdgpu_device *adev, · 1196 unmodified lines | ||
| 5049 | 5027 | return 0; |
| 5050 | 5028 | } |
| 5051 | 5029 | |
| 5052 | −static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) | |
| 5030 | +static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned vmid) | |
| 5053 | 5031 | { |
| 5054 | 5032 | u32 data; |
| 5055 | 5033 | |
| @@ -5063,6 +5041,14 @@ static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) · 7 unmodified lines | ||
| 5063 | 5041 | WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); |
| 5064 | 5042 | |
| 5065 | 5043 | amdgpu_gfx_off_ctrl(adev, true); |
| 5044 | + | |
| 5045 | + if (ring | |
| 5046 | + && amdgpu_sriov_is_pp_one_vf(adev) | |
| 5047 | + && ((ring->funcs->type == AMDGPU_RING_TYPE_GFX) | |
| 5048 | + || (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) { | |
| 5049 | + uint32_t reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); | |
| 5050 | + amdgpu_ring_emit_wreg(ring, reg, data); | |
| 5051 | + } | |
| 5066 | 5052 | } |
| 5067 | 5053 | |
| 5068 | 5054 | static const struct amdgpu_rlc_funcs gfx_v11_0_rlc_funcs = { |
| @@ -6126,7 +6112,8 @@ static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = { · 1057 unmodified lines | ||
| 6126 | 6112 | .get_rptr = gfx_v11_0_ring_get_rptr_gfx, |
| 6127 | 6113 | .get_wptr = gfx_v11_0_ring_get_wptr_gfx, |
| 6128 | 6114 | .set_wptr = gfx_v11_0_ring_set_wptr_gfx, |
| 6129 | − .emit_frame_size = /* totally 242 maximum if 16 IBs */ | |
| 6115 | + .emit_frame_size = /* totally 247 maximum if 16 IBs */ | |
| 6116 | + 5 + /* update_spm_vmid */ | |
| 6130 | 6117 | 5 + /* COND_EXEC */ |
| 6131 | 6118 | 9 + /* SET_Q_PREEMPTION_MODE */ |
| 6132 | 6119 | 7 + /* PIPELINE_SYNC */ |
| @@ -6176,6 +6163,7 @@ static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_compute = { · 43 unmodified lines | ||
| 6176 | 6163 | .get_wptr = gfx_v11_0_ring_get_wptr_compute, |
| 6177 | 6164 | .set_wptr = gfx_v11_0_ring_set_wptr_compute, |
| 6178 | 6165 | .emit_frame_size = |
| 6166 | + 5 + /* update_spm_vmid */ | |
| 6179 | 6167 | 20 + /* gfx_v11_0_ring_emit_gds_switch */ |
| 6180 | 6168 | 7 + /* gfx_v11_0_ring_emit_hdp_flush */ |
| 6181 | 6169 | 5 + /* hdp invalidate */ |
| @@ -69,7 +69,7 @@ static int gfx_v11_0_3_rlc_gc_fed_irq(struct amdgpu_device *adev, · 68 unmodified lines | ||
| 69 | 69 | amdgpu_ras_interrupt_dispatch(adev, &ih_data); |
| 70 | 70 | } else { |
| 71 | 71 | if (adev->virt.ops && adev->virt.ops->ras_poison_handler) |
| 72 | − adev->virt.ops->ras_poison_handler(adev); | |
| 72 | + adev->virt.ops->ras_poison_handler(adev, ras_if->block); | |
| 73 | 73 | else |
| 74 | 74 | dev_warn(adev->dev, |
| 75 | 75 | "No ras_poison_handler interface in SRIOV for %s!\n", ras_if->name); |
| @@ -3274,7 +3274,7 @@ static int gfx_v7_0_rlc_init(struct amdgpu_device *adev) · 3273 unmodified lines | ||
| 3274 | 3274 | |
| 3275 | 3275 | /* init spm vmid with 0xf */ |
| 3276 | 3276 | if (adev->gfx.rlc.funcs->update_spm_vmid) |
| 3277 | − adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); | |
| 3277 | + adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); | |
| 3278 | 3278 | |
| 3279 | 3279 | return 0; |
| 3280 | 3280 | } |
| @@ -3500,7 +3500,7 @@ static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev) · 219 unmodified lines | ||
| 3500 | 3500 | return 0; |
| 3501 | 3501 | } |
| 3502 | 3502 | |
| 3503 | −static void gfx_v7_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) | |
| 3503 | +static void gfx_v7_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned vmid) | |
| 3504 | 3504 | { |
| 3505 | 3505 | u32 data; |
| 3506 | 3506 | |
| @@ -1288,7 +1288,7 @@ static int gfx_v8_0_rlc_init(struct amdgpu_device *adev) · 1287 unmodified lines | ||
| 1288 | 1288 | |
| 1289 | 1289 | /* init spm vmid with 0xf */ |
| 1290 | 1290 | if (adev->gfx.rlc.funcs->update_spm_vmid) |
| 1291 | − adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); | |
| 1291 | + adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); | |
| 1292 | 1292 | |
| 1293 | 1293 | return 0; |
| 1294 | 1294 | } |
| @@ -5579,7 +5579,7 @@ static void gfx_v8_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id) · 4284 unmodified lines | ||
| 5579 | 5579 | } |
| 5580 | 5580 | } |
| 5581 | 5581 | |
| 5582 | −static void gfx_v8_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) | |
| 5582 | +static void gfx_v8_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned vmid) | |
| 5583 | 5583 | { |
| 5584 | 5584 | u32 data; |
| 5585 | 5585 | |
| @@ -3034,6 +3034,14 @@ static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev) · 3033 unmodified lines | ||
| 3034 | 3034 | |
| 3035 | 3035 | gfx_v9_0_cp_gfx_enable(adev, true); |
| 3036 | 3036 | |
| 3037 | + /* Now only limit the quirk on the APU gfx9 series and already | |
| 3038 | + * confirmed that the APU gfx10/gfx11 needn't such update. | |
| 3039 | + */ | |
| 3040 | + if (adev->flags & AMD_IS_APU && | |
| 3041 | + adev->in_s3 && !adev->suspend_complete) { | |
| 3042 | + DRM_INFO(" Will skip the CSB packet resubmit\n"); | |
| 3043 | + return 0; | |
| 3044 | + } | |
| 3037 | 3045 | r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 + 3); |
| 3038 | 3046 | if (r) { |
| 3039 | 3047 | DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); |
| @@ -4894,7 +4902,7 @@ static void gfx_v9_0_update_spm_vmid_internal(struct amdgpu_device *adev, · 1854 unmodified lines | ||
| 4894 | 4902 | WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data); |
| 4895 | 4903 | } |
| 4896 | 4904 | |
| 4897 | −static void gfx_v9_0_update_spm_vmid(struct amdgpu_device *adev, unsigned int vmid) | |
| 4905 | +static void gfx_v9_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned int vmid) | |
| 4898 | 4906 | { |
| 4899 | 4907 | amdgpu_gfx_off_ctrl(adev, false); |
| 4900 | 4908 | |
| @@ -970,8 +970,9 @@ static void gfx_v9_4_reset_ras_error_count(struct amdgpu_device *adev) · 969 unmodified lines | ||
| 970 | 970 | WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_DSM_INDEX, 255); |
| 971 | 971 | } |
| 972 | 972 | |
| 973 | −static const struct soc15_reg_entry gfx_v9_4_ea_err_status_regs = | |
| 974 | − { SOC15_REG_ENTRY(GC, 0, mmGCEA_ERR_STATUS), 0, 1, 32 }; | |
| 973 | +static const struct soc15_reg_entry gfx_v9_4_ea_err_status_regs = { | |
| 974 | + SOC15_REG_ENTRY(GC, 0, mmGCEA_ERR_STATUS), 0, 1, 32 | |
| 975 | +}; | |
| 975 | 976 | |
| 976 | 977 | static void gfx_v9_4_query_ras_error_status(struct amdgpu_device *adev) |
| 977 | 978 | { |
| @@ -38,6 +38,7 @@ · 37 unmodified lines | ||
| 38 | 38 | |
| 39 | 39 | #include "gfx_v9_4_3.h" |
| 40 | 40 | #include "amdgpu_xcp.h" |
| 41 | +#include "amdgpu_aca.h" | |
| 41 | 42 | |
| 42 | 43 | MODULE_FIRMWARE("amdgpu/gc_9_4_3_mec.bin"); |
| 43 | 44 | MODULE_FIRMWARE("amdgpu/gc_9_4_3_rlc.bin"); |
| @@ -48,6 +49,10 @@ MODULE_FIRMWARE("amdgpu/gc_9_4_3_rlc.bin"); · 4 unmodified lines | ||
| 48 | 49 | #define GOLDEN_GB_ADDR_CONFIG 0x2a114042 |
| 49 | 50 | #define CP_HQD_PERSISTENT_STATE_DEFAULT 0xbe05301 |
| 50 | 51 | |
| 52 | +#define mmSMNAID_XCD0_MCA_SMU 0x36430400 /* SMN AID XCD0 */ | |
| 53 | +#define mmSMNAID_XCD1_MCA_SMU 0x38430400 /* SMN AID XCD1 */ | |
| 54 | +#define mmSMNXCD_XCD0_MCA_SMU 0x40430400 /* SMN XCD XCD0 */ | |
| 55 | + | |
| 51 | 56 | struct amdgpu_gfx_ras gfx_v9_4_3_ras; |
| 52 | 57 | |
| 53 | 58 | static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev); |
| @@ -675,6 +680,66 @@ static const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs = { · 621 unmodified lines | ||
| 675 | 680 | .ih_node_to_logical_xcc = &gfx_v9_4_3_ih_to_xcc_inst, |
| 676 | 681 | }; |
| 677 | 682 | |
| 683 | +static int gfx_v9_4_3_aca_bank_generate_report(struct aca_handle *handle, | |
| 684 | + struct aca_bank *bank, enum aca_error_type type, | |
| 685 | + struct aca_bank_report *report, void *data) | |
| 686 | +{ | |
| 687 | + u64 status, misc0; | |
| 688 | + u32 instlo; | |
| 689 | + int ret; | |
| 690 | + | |
| 691 | + status = bank->regs[ACA_REG_IDX_STATUS]; | |
| 692 | + if ((type == ACA_ERROR_TYPE_UE && | |
| 693 | + ACA_REG__STATUS__ERRORCODEEXT(status) == ACA_EXTERROR_CODE_FAULT) || | |
| 694 | + (type == ACA_ERROR_TYPE_CE && | |
| 695 | + ACA_REG__STATUS__ERRORCODEEXT(status) == ACA_EXTERROR_CODE_CE)) { | |
| 696 | + | |
| 697 | + ret = aca_bank_info_decode(bank, &report->info); | |
| 698 | + if (ret) | |
| 699 | + return ret; | |
| 700 | + | |
| 701 | + /* NOTE: overwrite info.die_id with xcd id for gfx */ | |
| 702 | + instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); | |
| 703 | + instlo &= GENMASK(31, 1); | |
| 704 | + report->info.die_id = instlo == mmSMNAID_XCD0_MCA_SMU ? 0 : 1; | |
| 705 | + | |
| 706 | + misc0 = bank->regs[ACA_REG_IDX_MISC0]; | |
| 707 | + report->count[type] = ACA_REG__MISC0__ERRCNT(misc0); | |
| 708 | + } | |
| 709 | + | |
| 710 | + return 0; | |
| 711 | +} | |
| 712 | + | |
| 713 | +static bool gfx_v9_4_3_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, | |
| 714 | + enum aca_error_type type, void *data) | |
| 715 | +{ | |
| 716 | + u32 instlo; | |
| 717 | + | |
| 718 | + instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); | |
| 719 | + instlo &= GENMASK(31, 1); | |
| 720 | + switch (instlo) { | |
| 721 | + case mmSMNAID_XCD0_MCA_SMU: | |
| 722 | + case mmSMNAID_XCD1_MCA_SMU: | |
| 723 | + case mmSMNXCD_XCD0_MCA_SMU: | |
| 724 | + return true; | |
| 725 | + default: | |
| 726 | + break; | |
| 727 | + } | |
| 728 | + | |
| 729 | + return false; | |
| 730 | +} | |
| 731 | + | |
| 732 | +static const struct aca_bank_ops gfx_v9_4_3_aca_bank_ops = { | |
| 733 | + .aca_bank_generate_report = gfx_v9_4_3_aca_bank_generate_report, | |
| 734 | + .aca_bank_is_valid = gfx_v9_4_3_aca_bank_is_valid, | |
| 735 | +}; | |
| 736 | + | |
| 737 | +static const struct aca_info gfx_v9_4_3_aca_info = { | |
| 738 | + .hwip = ACA_HWIP_TYPE_SMU, | |
| 739 | + .mask = ACA_ERROR_UE_MASK | ACA_ERROR_CE_MASK, | |
| 740 | + .bank_ops = &gfx_v9_4_3_aca_bank_ops, | |
| 741 | +}; | |
| 742 | + | |
| 678 | 743 | static int gfx_v9_4_3_gpu_early_init(struct amdgpu_device *adev) |
| 679 | 744 | { |
| 680 | 745 | u32 gb_addr_config; |
| @@ -1109,7 +1174,7 @@ static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev) · 428 unmodified lines | ||
| 1109 | 1174 | { |
| 1110 | 1175 | /* init spm vmid with 0xf */ |
| 1111 | 1176 | if (adev->gfx.rlc.funcs->update_spm_vmid) |
| 1112 | − adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); | |
| 1177 | + adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); | |
| 1113 | 1178 | |
| 1114 | 1179 | return 0; |
| 1115 | 1180 | } |
| @@ -1320,7 +1385,7 @@ static int gfx_v9_4_3_rlc_resume(struct amdgpu_device *adev) · 204 unmodified lines | ||
| 1320 | 1385 | return 0; |
| 1321 | 1386 | } |
| 1322 | 1387 | |
| 1323 | −static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev, | |
| 1388 | +static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, | |
| 1324 | 1389 | unsigned vmid) |
| 1325 | 1390 | { |
| 1326 | 1391 | u32 reg, data; |
| @@ -4242,9 +4307,32 @@ struct amdgpu_ras_block_hw_ops gfx_v9_4_3_ras_ops = { · 2915 unmodified lines | ||
| 4242 | 4307 | .reset_ras_error_count = &gfx_v9_4_3_reset_ras_error_count, |
| 4243 | 4308 | }; |
| 4244 | 4309 | |
| 4310 | +static int gfx_v9_4_3_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) | |
| 4311 | +{ | |
| 4312 | + int r; | |
| 4313 | + | |
| 4314 | + r = amdgpu_ras_block_late_init(adev, ras_block); | |
| 4315 | + if (r) | |
| 4316 | + return r; | |
| 4317 | + | |
| 4318 | + r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__GFX, | |
| 4319 | + &gfx_v9_4_3_aca_info, | |
| 4320 | + NULL); | |
| 4321 | + if (r) | |
| 4322 | + goto late_fini; | |
| 4323 | + | |
| 4324 | + return 0; | |
| 4325 | + | |
| 4326 | +late_fini: | |
| 4327 | + amdgpu_ras_block_late_fini(adev, ras_block); | |
| 4328 | + | |
| 4329 | + return r; | |
| 4330 | +} | |
| 4331 | + | |
| 4245 | 4332 | struct amdgpu_gfx_ras gfx_v9_4_3_ras = { |
| 4246 | 4333 | .ras_block = { |
| 4247 | 4334 | .hw_ops = &gfx_v9_4_3_ras_ops, |
| 4335 | + .ras_late_init = &gfx_v9_4_3_ras_late_init, | |
| 4248 | 4336 | }, |
| 4249 | 4337 | .enable_watchdog_timer = &gfx_v9_4_3_enable_watchdog_timer, |
| 4250 | 4338 | }; |
| @@ -262,16 +262,17 @@ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, · 261 unmodified lines | ||
| 262 | 262 | /* flush hdp cache */ |
| 263 | 263 | adev->hdp.funcs->flush_hdp(adev, NULL); |
| 264 | 264 | |
| 265 | − /* For SRIOV run time, driver shouldn't access the register through MMIO | |
| 266 | − * Directly use kiq to do the vm invalidation instead | |
| 265 | + /* This is necessary for SRIOV as well as for GFXOFF to function | |
| 266 | + * properly under bare metal | |
| 267 | 267 | */ |
| 268 | 268 | if (adev->gfx.kiq[0].ring.sched.ready && !adev->enable_mes && |
| 269 | 269 | (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) { |
| 270 | − amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req, | |
| 271 | − 1 << vmid, GET_INST(GC, 0)); | |
| 270 | + amdgpu_gmc_fw_reg_write_reg_wait(adev, req, ack, inv_req, | |
| 271 | + 1 << vmid, GET_INST(GC, 0)); | |
| 272 | 272 | return; |
| 273 | 273 | } |
| 274 | 274 | |
| 275 | + /* This path is needed before KIQ/MES/GFXOFF are set up */ | |
| 275 | 276 | hub_ip = (vmhub == AMDGPU_GFXHUB(0)) ? GC_HWIP : MMHUB_HWIP; |
| 276 | 277 | |
| 277 | 278 | spin_lock(&adev->gmc.invalidate_lock); |
| @@ -223,16 +223,17 @@ static void gmc_v11_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, · 222 unmodified lines | ||
| 223 | 223 | /* flush hdp cache */ |
| 224 | 224 | adev->hdp.funcs->flush_hdp(adev, NULL); |
| 225 | 225 | |
| 226 | − /* For SRIOV run time, driver shouldn't access the register through MMIO | |
| 227 | − * Directly use kiq to do the vm invalidation instead | |
| 226 | + /* This is necessary for SRIOV as well as for GFXOFF to function | |
| 227 | + * properly under bare metal | |
| 228 | 228 | */ |
| 229 | 229 | if ((adev->gfx.kiq[0].ring.sched.ready || adev->mes.ring.sched.ready) && |
| 230 | 230 | (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) { |
| 231 | − amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req, | |
| 232 | − 1 << vmid, GET_INST(GC, 0)); | |
| 231 | + amdgpu_gmc_fw_reg_write_reg_wait(adev, req, ack, inv_req, | |
| 232 | + 1 << vmid, GET_INST(GC, 0)); | |
| 233 | 233 | return; |
| 234 | 234 | } |
| 235 | 235 | |
| 236 | + /* This path is needed before KIQ/MES/GFXOFF are set up */ | |
| 236 | 237 | hub_ip = (vmhub == AMDGPU_GFXHUB(0)) ? GC_HWIP : MMHUB_HWIP; |
| 237 | 238 | |
| 238 | 239 | spin_lock(&adev->gmc.invalidate_lock); |
| @@ -435,9 +435,10 @@ static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable) · 434 unmodified lines | ||
| 435 | 435 | WREG32(mmVM_PRT_CNTL, tmp); |
| 436 | 436 | |
| 437 | 437 | if (enable) { |
| 438 | − uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT; | |
| 438 | + uint32_t low = AMDGPU_VA_RESERVED_BOTTOM >> | |
| 439 | + AMDGPU_GPU_PAGE_SHIFT; | |
| 439 | 440 | uint32_t high = adev->vm_manager.max_pfn - |
| 440 | − (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT); | |
| 441 | + (AMDGPU_VA_RESERVED_TOP >> AMDGPU_GPU_PAGE_SHIFT); | |
| 441 | 442 | |
| 442 | 443 | WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low); |
| 443 | 444 | WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low); |
| @@ -915,8 +916,8 @@ static int gmc_v6_0_hw_init(void *handle) · 471 unmodified lines | ||
| 915 | 916 | |
| 916 | 917 | if (amdgpu_emu_mode == 1) |
| 917 | 918 | return amdgpu_gmc_vram_checking(adev); |
| 918 | − else | |
| 919 | − return r; | |
| 919 | + | |
| 920 | + return 0; | |
| 920 | 921 | } |
| 921 | 922 | |
| 922 | 923 | static int gmc_v6_0_hw_fini(void *handle) |
| @@ -563,9 +563,10 @@ static void gmc_v7_0_set_prt(struct amdgpu_device *adev, bool enable) · 562 unmodified lines | ||
| 563 | 563 | WREG32(mmVM_PRT_CNTL, tmp); |
| 564 | 564 | |
| 565 | 565 | if (enable) { |
| 566 | − uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT; | |
| 566 | + uint32_t low = AMDGPU_VA_RESERVED_BOTTOM >> | |
| 567 | + AMDGPU_GPU_PAGE_SHIFT; | |
| 567 | 568 | uint32_t high = adev->vm_manager.max_pfn - |
| 568 | − (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT); | |
| 569 | + (AMDGPU_VA_RESERVED_TOP >> AMDGPU_GPU_PAGE_SHIFT); | |
| 569 | 570 | |
| 570 | 571 | WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low); |
| 571 | 572 | WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low); |
| @@ -1099,8 +1100,8 @@ static int gmc_v7_0_hw_init(void *handle) · 527 unmodified lines | ||
| 1099 | 1100 | |
| 1100 | 1101 | if (amdgpu_emu_mode == 1) |
| 1101 | 1102 | return amdgpu_gmc_vram_checking(adev); |
| 1102 | − else | |
| 1103 | − return r; | |
| 1103 | + | |
| 1104 | + return 0; | |
| 1104 | 1105 | } |
| 1105 | 1106 | |
| 1106 | 1107 | static int gmc_v7_0_hw_fini(void *handle) |
| @@ -777,9 +777,10 @@ static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable) · 776 unmodified lines | ||
| 777 | 777 | WREG32(mmVM_PRT_CNTL, tmp); |
| 778 | 778 | |
| 779 | 779 | if (enable) { |
| 780 | − uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT; | |
| 780 | + uint32_t low = AMDGPU_VA_RESERVED_BOTTOM >> | |
| 781 | + AMDGPU_GPU_PAGE_SHIFT; | |
| 781 | 782 | uint32_t high = adev->vm_manager.max_pfn - |
| 782 | − (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT); | |
| 783 | + (AMDGPU_VA_RESERVED_TOP >> AMDGPU_GPU_PAGE_SHIFT); | |
| 783 | 784 | |
| 784 | 785 | WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low); |
| 785 | 786 | WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low); |
| @@ -1219,8 +1220,8 @@ static int gmc_v8_0_hw_init(void *handle) · 433 unmodified lines | ||
| 1219 | 1220 | |
| 1220 | 1221 | if (amdgpu_emu_mode == 1) |
| 1221 | 1222 | return amdgpu_gmc_vram_checking(adev); |
| 1222 | − else | |
| 1223 | − return r; | |
| 1223 | + | |
| 1224 | + return 0; | |
| 1224 | 1225 | } |
| 1225 | 1226 | |
| 1226 | 1227 | static int gmc_v8_0_hw_fini(void *handle) |
| @@ -829,23 +829,25 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, · 828 unmodified lines | ||
| 829 | 829 | req = hub->vm_inv_eng0_req + hub->eng_distance * eng; |
| 830 | 830 | ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; |
| 831 | 831 | |
| 832 | − /* This is necessary for a HW workaround under SRIOV as well | |
| 833 | − * as GFXOFF under bare metal | |
| 834 | − */ | |
| 835 | 832 | if (vmhub >= AMDGPU_MMHUB0(0)) |
| 836 | 833 | inst = GET_INST(GC, 0); |
| 837 | 834 | else |
| 838 | 835 | inst = vmhub; |
| 836 | + | |
| 837 | + /* This is necessary for SRIOV as well as for GFXOFF to function | |
| 838 | + * properly under bare metal | |
| 839 | + */ | |
| 839 | 840 | if (adev->gfx.kiq[inst].ring.sched.ready && |
| 840 | 841 | (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) { |
| 841 | 842 | uint32_t req = hub->vm_inv_eng0_req + hub->eng_distance * eng; |
| 842 | 843 | uint32_t ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; |
| 843 | 844 | |
| 844 | − amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req, | |
| 845 | − 1 << vmid, inst); | |
| 845 | + amdgpu_gmc_fw_reg_write_reg_wait(adev, req, ack, inv_req, | |
| 846 | + 1 << vmid, inst); | |
| 846 | 847 | return; |
| 847 | 848 | } |
| 848 | 849 | |
| 850 | + /* This path is needed before KIQ/MES/GFXOFF are set up */ | |
| 849 | 851 | spin_lock(&adev->gmc.invalidate_lock); |
| 850 | 852 | |
| 851 | 853 | /* |
| @@ -1947,13 +1949,6 @@ static int gmc_v9_0_init_mem_ranges(struct amdgpu_device *adev) · 1095 unmodified lines | ||
| 1947 | 1949 | |
| 1948 | 1950 | static void gmc_v9_4_3_init_vram_info(struct amdgpu_device *adev) |
| 1949 | 1951 | { |
| 1950 | − static const u32 regBIF_BIOS_SCRATCH_4 = 0x50; | |
| 1951 | − u32 vram_info; | |
| 1952 | − | |
| 1953 | − if (!amdgpu_sriov_vf(adev)) { | |
| 1954 | − vram_info = RREG32(regBIF_BIOS_SCRATCH_4); | |
| 1955 | − adev->gmc.vram_vendor = vram_info & 0xF; | |
| 1956 | − } | |
| 1957 | 1952 | adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM; |
| 1958 | 1953 | adev->gmc.vram_width = 128 * 64; |
| 1959 | 1954 | } |
| @@ -2340,8 +2335,8 @@ static int gmc_v9_0_hw_init(void *handle) · 380 unmodified lines | ||
| 2340 | 2335 | |
| 2341 | 2336 | if (amdgpu_emu_mode == 1) |
| 2342 | 2337 | return amdgpu_gmc_vram_checking(adev); |
| 2343 | − else | |
| 2344 | − return r; | |
| 2338 | + | |
| 2339 | + return 0; | |
| 2345 | 2340 | } |
| 2346 | 2341 | |
| 2347 | 2342 | /** |
| @@ -215,6 +215,11 @@ static u32 iceland_ih_get_wptr(struct amdgpu_device *adev, · 214 unmodified lines | ||
| 215 | 215 | tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); |
| 216 | 216 | WREG32(mmIH_RB_CNTL, tmp); |
| 217 | 217 | |
| 218 | + /* Unset the CLEAR_OVERFLOW bit immediately so new overflows | |
| 219 | + * can be detected. | |
| 220 | + */ | |
| 221 | + tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0); | |
| 222 | + WREG32(mmIH_RB_CNTL, tmp); | |
| 218 | 223 | |
| 219 | 224 | out: |
| 220 | 225 | return (wptr & ih->ptr_mask); |
| @@ -418,6 +418,12 @@ static u32 ih_v6_0_get_wptr(struct amdgpu_device *adev, · 417 unmodified lines | ||
| 418 | 418 | tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); |
| 419 | 419 | tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); |
| 420 | 420 | WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); |
| 421 | + | |
| 422 | + /* Unset the CLEAR_OVERFLOW bit immediately so new overflows | |
| 423 | + * can be detected. | |
| 424 | + */ | |
| 425 | + tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0); | |
| 426 | + WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); | |
| 421 | 427 | out: |
| 422 | 428 | return (wptr & ih->ptr_mask); |
| 423 | 429 | } |
| @@ -418,6 +418,13 @@ static u32 ih_v6_1_get_wptr(struct amdgpu_device *adev, · 417 unmodified lines | ||
| 418 | 418 | tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); |
| 419 | 419 | tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); |
| 420 | 420 | WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); |
| 421 | + | |
| 422 | + /* Unset the CLEAR_OVERFLOW bit immediately so new overflows | |
| 423 | + * can be detected. | |
| 424 | + */ | |
| 425 | + tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0); | |
| 426 | + WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); | |
| 427 | + | |
| 421 | 428 | out: |
| 422 | 429 | return (wptr & ih->ptr_mask); |
| 423 | 430 | } |
| @@ -551,7 +551,7 @@ static int jpeg_v2_5_set_powergating_state(void *handle, · 550 unmodified lines | ||
| 551 | 551 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 552 | 552 | int ret; |
| 553 | 553 | |
| 554 | − if(state == adev->jpeg.cur_state) | |
| 554 | + if (state == adev->jpeg.cur_state) | |
| 555 | 555 | return 0; |
| 556 | 556 | |
| 557 | 557 | if (state == AMD_PG_STATE_GATE) |
| @@ -559,7 +559,7 @@ static int jpeg_v2_5_set_powergating_state(void *handle, · 1 unmodified line | ||
| 559 | 559 | else |
| 560 | 560 | ret = jpeg_v2_5_start(adev); |
| 561 | 561 | |
| 562 | − if(!ret) | |
| 562 | + if (!ret) | |
| 563 | 563 | adev->jpeg.cur_state = state; |
| 564 | 564 | |
| 565 | 565 | return ret; |
| @@ -754,8 +754,7 @@ static void jpeg_v2_5_set_irq_funcs(struct amdgpu_device *adev) · 188 unmodified lines | ||
| 754 | 754 | } |
| 755 | 755 | } |
| 756 | 756 | |
| 757 | −const struct amdgpu_ip_block_version jpeg_v2_5_ip_block = | |
| 758 | −{ | |
| 757 | +const struct amdgpu_ip_block_version jpeg_v2_5_ip_block = { | |
| 759 | 758 | .type = AMD_IP_BLOCK_TYPE_JPEG, |
| 760 | 759 | .major = 2, |
| 761 | 760 | .minor = 5, |
| @@ -763,8 +762,7 @@ const struct amdgpu_ip_block_version jpeg_v2_5_ip_block = · 1 unmodified line | ||
| 763 | 762 | .funcs = &jpeg_v2_5_ip_funcs, |
| 764 | 763 | }; |
| 765 | 764 | |
| 766 | −const struct amdgpu_ip_block_version jpeg_v2_6_ip_block = | |
| 767 | −{ | |
| 765 | +const struct amdgpu_ip_block_version jpeg_v2_6_ip_block = { | |
| 768 | 766 | .type = AMD_IP_BLOCK_TYPE_JPEG, |
| 769 | 767 | .major = 2, |
| 770 | 768 | .minor = 6, |
| @@ -674,14 +674,6 @@ static int jpeg_v4_0_set_powergating_state(void *handle, · 673 unmodified lines | ||
| 674 | 674 | return ret; |
| 675 | 675 | } |
| 676 | 676 | |
| 677 | −static int jpeg_v4_0_set_interrupt_state(struct amdgpu_device *adev, | |
| 678 | − struct amdgpu_irq_src *source, | |
| 679 | − unsigned type, | |
| 680 | − enum amdgpu_interrupt_state state) | |
| 681 | −{ | |
| 682 | − return 0; | |
| 683 | −} | |
| 684 | − | |
| 685 | 677 | static int jpeg_v4_0_set_ras_interrupt_state(struct amdgpu_device *adev, |
| 686 | 678 | struct amdgpu_irq_src *source, |
| 687 | 679 | unsigned int type, |
| @@ -765,7 +757,6 @@ static void jpeg_v4_0_set_dec_ring_funcs(struct amdgpu_device *adev) · 77 unmodified lines | ||
| 765 | 757 | } |
| 766 | 758 | |
| 767 | 759 | static const struct amdgpu_irq_src_funcs jpeg_v4_0_irq_funcs = { |
| 768 | − .set = jpeg_v4_0_set_interrupt_state, | |
| 769 | 760 | .process = jpeg_v4_0_process_interrupt, |
| 770 | 761 | }; |
| 771 | 762 | |
| @@ -181,7 +181,6 @@ static int jpeg_v4_0_5_hw_fini(void *handle) · 180 unmodified lines | ||
| 181 | 181 | RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS)) |
| 182 | 182 | jpeg_v4_0_5_set_powergating_state(adev, AMD_PG_STATE_GATE); |
| 183 | 183 | } |
| 184 | − amdgpu_irq_put(adev, &adev->jpeg.inst->irq, 0); | |
| 185 | 184 | |
| 186 | 185 | return 0; |
| 187 | 186 | } |
| @@ -516,14 +515,6 @@ static int jpeg_v4_0_5_set_powergating_state(void *handle, · 328 unmodified lines | ||
| 516 | 515 | return ret; |
| 517 | 516 | } |
| 518 | 517 | |
| 519 | −static int jpeg_v4_0_5_set_interrupt_state(struct amdgpu_device *adev, | |
| 520 | − struct amdgpu_irq_src *source, | |
| 521 | − unsigned type, | |
| 522 | − enum amdgpu_interrupt_state state) | |
| 523 | −{ | |
| 524 | − return 0; | |
| 525 | −} | |
| 526 | − | |
| 527 | 518 | static int jpeg_v4_0_5_process_interrupt(struct amdgpu_device *adev, |
| 528 | 519 | struct amdgpu_irq_src *source, |
| 529 | 520 | struct amdgpu_iv_entry *entry) |
| @@ -603,7 +594,6 @@ static void jpeg_v4_0_5_set_dec_ring_funcs(struct amdgpu_device *adev) · 73 unmodified lines | ||
| 603 | 594 | } |
| 604 | 595 | |
| 605 | 596 | static const struct amdgpu_irq_src_funcs jpeg_v4_0_5_irq_funcs = { |
| 606 | − .set = jpeg_v4_0_5_set_interrupt_state, | |
| 607 | 597 | .process = jpeg_v4_0_5_process_interrupt, |
| 608 | 598 | }; |
| 609 | 599 | |
| @@ -33,6 +33,7 @@ · 32 unmodified lines | ||
| 33 | 33 | |
| 34 | 34 | #define regVM_L2_CNTL3_DEFAULT 0x80100007 |
| 35 | 35 | #define regVM_L2_CNTL4_DEFAULT 0x000000c1 |
| 36 | +#define mmSMNAID_AID0_MCA_SMU 0x03b30400 | |
| 36 | 37 | |
| 37 | 38 | static u64 mmhub_v1_8_get_fb_location(struct amdgpu_device *adev) |
| 38 | 39 | { |
| @@ -705,8 +706,94 @@ static const struct amdgpu_ras_block_hw_ops mmhub_v1_8_ras_hw_ops = { · 666 unmodified lines | ||
| 705 | 706 | .reset_ras_error_count = mmhub_v1_8_reset_ras_error_count, |
| 706 | 707 | }; |
| 707 | 708 | |
| 709 | +static int mmhub_v1_8_aca_bank_generate_report(struct aca_handle *handle, | |
| 710 | + struct aca_bank *bank, enum aca_error_type type, | |
| 711 | + struct aca_bank_report *report, void *data) | |
| 712 | +{ | |
| 713 | + u64 status, misc0; | |
| 714 | + int ret; | |
| 715 | + | |
| 716 | + status = bank->regs[ACA_REG_IDX_STATUS]; | |
| 717 | + if ((type == ACA_ERROR_TYPE_UE && | |
| 718 | + ACA_REG__STATUS__ERRORCODEEXT(status) == ACA_EXTERROR_CODE_FAULT) || | |
| 719 | + (type == ACA_ERROR_TYPE_CE && | |
| 720 | + ACA_REG__STATUS__ERRORCODEEXT(status) == ACA_EXTERROR_CODE_CE)) { | |
| 721 | + | |
| 722 | + ret = aca_bank_info_decode(bank, &report->info); | |
| 723 | + if (ret) | |
| 724 | + return ret; | |
| 725 | + | |
| 726 | + misc0 = bank->regs[ACA_REG_IDX_MISC0]; | |
| 727 | + report->count[type] = ACA_REG__MISC0__ERRCNT(misc0); | |
| 728 | + } | |
| 729 | + | |
| 730 | + return 0; | |
| 731 | +} | |
| 732 | + | |
| 733 | +/* reference to smu driver if header file */ | |
| 734 | +static int mmhub_v1_8_err_codes[] = { | |
| 735 | + 0, 1, 2, 3, 4, /* CODE_DAGB0 - 4 */ | |
| 736 | + 5, 6, 7, 8, 9, /* CODE_EA0 - 4 */ | |
| 737 | + 10, /* CODE_UTCL2_ROUTER */ | |
| 738 | + 11, /* CODE_VML2 */ | |
| 739 | + 12, /* CODE_VML2_WALKER */ | |
| 740 | + 13, /* CODE_MMCANE */ | |
| 741 | +}; | |
| 742 | + | |
| 743 | +static bool mmhub_v1_8_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, | |
| 744 | + enum aca_error_type type, void *data) | |
| 745 | +{ | |
| 746 | + u32 instlo; | |
| 747 | + | |
| 748 | + instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); | |
| 749 | + instlo &= GENMASK(31, 1); | |
| 750 | + | |
| 751 | + if (instlo != mmSMNAID_AID0_MCA_SMU) | |
| 752 | + return false; | |
| 753 | + | |
| 754 | + if (aca_bank_check_error_codes(handle->adev, bank, | |
| 755 | + mmhub_v1_8_err_codes, | |
| 756 | + ARRAY_SIZE(mmhub_v1_8_err_codes))) | |
| 757 | + return false; | |
| 758 | + | |
| 759 | + return true; | |
| 760 | +} | |
| 761 | + | |
| 762 | +static const struct aca_bank_ops mmhub_v1_8_aca_bank_ops = { | |
| 763 | + .aca_bank_generate_report = mmhub_v1_8_aca_bank_generate_report, | |
| 764 | + .aca_bank_is_valid = mmhub_v1_8_aca_bank_is_valid, | |
| 765 | +}; | |
| 766 | + | |
| 767 | +static const struct aca_info mmhub_v1_8_aca_info = { | |
| 768 | + .hwip = ACA_HWIP_TYPE_SMU, | |
| 769 | + .mask = ACA_ERROR_UE_MASK, | |
| 770 | + .bank_ops = &mmhub_v1_8_aca_bank_ops, | |
| 771 | +}; | |
| 772 | + | |
| 773 | +static int mmhub_v1_8_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) | |
| 774 | +{ | |
| 775 | + int r; | |
| 776 | + | |
| 777 | + r = amdgpu_ras_block_late_init(adev, ras_block); | |
| 778 | + if (r) | |
| 779 | + return r; | |
| 780 | + | |
| 781 | + r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__MMHUB, | |
| 782 | + &mmhub_v1_8_aca_info, NULL); | |
| 783 | + if (r) | |
| 784 | + goto late_fini; | |
| 785 | + | |
| 786 | + return 0; | |
| 787 | + | |
| 788 | +late_fini: | |
| 789 | + amdgpu_ras_block_late_fini(adev, ras_block); | |
| 790 | + | |
| 791 | + return r; | |
| 792 | +} | |
| 793 | + | |
| 708 | 794 | struct amdgpu_mmhub_ras mmhub_v1_8_ras = { |
| 709 | 795 | .ras_block = { |
| 710 | 796 | .hw_ops = &mmhub_v1_8_ras_hw_ops, |
| 797 | + .ras_late_init = mmhub_v1_8_ras_late_init, | |
| 711 | 798 | }, |
| 712 | 799 | }; |
| @@ -404,7 +404,8 @@ static int xgpu_ai_request_init_data(struct amdgpu_device *adev) · 403 unmodified lines | ||
| 404 | 404 | return xgpu_ai_send_access_requests(adev, IDH_REQ_GPU_INIT_DATA); |
| 405 | 405 | } |
| 406 | 406 | |
| 407 | −static void xgpu_ai_ras_poison_handler(struct amdgpu_device *adev) | |
| 407 | +static void xgpu_ai_ras_poison_handler(struct amdgpu_device *adev, | |
| 408 | + enum amdgpu_ras_block block) | |
| 408 | 409 | { |
| 409 | 410 | xgpu_ai_send_access_requests(adev, IDH_RAS_POISON); |
| 410 | 411 | } |
| @@ -152,14 +152,14 @@ static void xgpu_nv_mailbox_trans_msg (struct amdgpu_device *adev, · 151 unmodified lines | ||
| 152 | 152 | xgpu_nv_mailbox_set_valid(adev, false); |
| 153 | 153 | } |
| 154 | 154 | |
| 155 | −static int xgpu_nv_send_access_requests(struct amdgpu_device *adev, | |
| 156 | − enum idh_request req) | |
| 155 | +static int xgpu_nv_send_access_requests_with_param(struct amdgpu_device *adev, | |
| 156 | + enum idh_request req, u32 data1, u32 data2, u32 data3) | |
| 157 | 157 | { |
| 158 | 158 | int r, retry = 1; |
| 159 | 159 | enum idh_event event = -1; |
| 160 | 160 | |
| 161 | 161 | send_request: |
| 162 | − xgpu_nv_mailbox_trans_msg(adev, req, 0, 0, 0); | |
| 162 | + xgpu_nv_mailbox_trans_msg(adev, req, data1, data2, data3); | |
| 163 | 163 | |
| 164 | 164 | switch (req) { |
| 165 | 165 | case IDH_REQ_GPU_INIT_ACCESS: |
| @@ -170,6 +170,10 @@ send_request: · 4 unmodified lines | ||
| 170 | 170 | case IDH_REQ_GPU_INIT_DATA: |
| 171 | 171 | event = IDH_REQ_GPU_INIT_DATA_READY; |
| 172 | 172 | break; |
| 173 | + case IDH_RAS_POISON: | |
| 174 | + if (data1 != 0) | |
| 175 | + event = IDH_RAS_POISON_READY; | |
| 176 | + break; | |
| 173 | 177 | default: |
| 174 | 178 | break; |
| 175 | 179 | } |
| @@ -206,6 +210,13 @@ send_request: · 30 unmodified lines | ||
| 206 | 210 | return 0; |
| 207 | 211 | } |
| 208 | 212 | |
| 213 | +static int xgpu_nv_send_access_requests(struct amdgpu_device *adev, | |
| 214 | + enum idh_request req) | |
| 215 | +{ | |
| 216 | + return xgpu_nv_send_access_requests_with_param(adev, | |
| 217 | + req, 0, 0, 0); | |
| 218 | +} | |
| 219 | + | |
| 209 | 220 | static int xgpu_nv_request_reset(struct amdgpu_device *adev) |
| 210 | 221 | { |
| 211 | 222 | int ret, i = 0; |
| @@ -424,9 +435,17 @@ void xgpu_nv_mailbox_put_irq(struct amdgpu_device *adev) · 212 unmodified lines | ||
| 424 | 435 | amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0); |
| 425 | 436 | } |
| 426 | 437 | |
| 427 | −static void xgpu_nv_ras_poison_handler(struct amdgpu_device *adev) | |
| 438 | +static void xgpu_nv_ras_poison_handler(struct amdgpu_device *adev, | |
| 439 | + enum amdgpu_ras_block block) | |
| 428 | 440 | { |
| 429 | − xgpu_nv_send_access_requests(adev, IDH_RAS_POISON); | |
| 441 | + if (amdgpu_ip_version(adev, UMC_HWIP, 0) < IP_VERSION(12, 0, 0)) { | |
| 442 | + xgpu_nv_send_access_requests(adev, IDH_RAS_POISON); | |
| 443 | + } else { | |
| 444 | + amdgpu_virt_fini_data_exchange(adev); | |
| 445 | + xgpu_nv_send_access_requests_with_param(adev, | |
| 446 | + IDH_RAS_POISON, block, 0, 0); | |
| 447 | + amdgpu_virt_init_data_exchange(adev); | |
| 448 | + } | |
| 430 | 449 | } |
| 431 | 450 | |
| 432 | 451 | const struct amdgpu_virt_ops xgpu_nv_virt_ops = { |
| @@ -51,6 +51,7 @@ enum idh_event { · 50 unmodified lines | ||
| 51 | 51 | IDH_FAIL, |
| 52 | 52 | IDH_QUERY_ALIVE, |
| 53 | 53 | IDH_REQ_GPU_INIT_DATA_READY, |
| 54 | + IDH_RAS_POISON_READY, | |
| 54 | 55 | |
| 55 | 56 | IDH_TEXT_MESSAGE = 255, |
| 56 | 57 | }; |
| @@ -442,6 +442,12 @@ static u32 navi10_ih_get_wptr(struct amdgpu_device *adev, · 441 unmodified lines | ||
| 442 | 442 | tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); |
| 443 | 443 | tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); |
| 444 | 444 | WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); |
| 445 | + | |
| 446 | + /* Unset the CLEAR_OVERFLOW bit immediately so new overflows | |
| 447 | + * can be detected. | |
| 448 | + */ | |
| 449 | + tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0); | |
| 450 | + WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); | |
| 445 | 451 | out: |
| 446 | 452 | return (wptr & ih->ptr_mask); |
| 447 | 453 | } |
| @@ -722,8 +728,7 @@ static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev) · 274 unmodified lines | ||
| 722 | 728 | adev->irq.ih_funcs = &navi10_ih_funcs; |
| 723 | 729 | } |
| 724 | 730 | |
| 725 | −const struct amdgpu_ip_block_version navi10_ih_ip_block = | |
| 726 | −{ | |
| 731 | +const struct amdgpu_ip_block_version navi10_ih_ip_block = { | |
| 727 | 732 | .type = AMD_IP_BLOCK_TYPE_IH, |
| 728 | 733 | .major = 5, |
| 729 | 734 | .minor = 0, |
| @@ -431,6 +431,12 @@ static void nbio_v7_9_init_registers(struct amdgpu_device *adev) · 430 unmodified lines | ||
| 431 | 431 | u32 inst_mask; |
| 432 | 432 | int i; |
| 433 | 433 | |
| 434 | + if (amdgpu_sriov_vf(adev)) | |
| 435 | + adev->rmmio_remap.reg_offset = | |
| 436 | + SOC15_REG_OFFSET( | |
| 437 | + NBIO, 0, | |
| 438 | + regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) | |
| 439 | + << 2; | |
| 434 | 440 | WREG32_SOC15(NBIO, 0, regXCC_DOORBELL_FENCE, |
| 435 | 441 | 0xff & ~(adev->gfx.xcc_mask)); |
| 436 | 442 | |
| @@ -27,6 +27,7 @@ · 26 unmodified lines | ||
| 27 | 27 | #include "amdgpu_ucode.h" |
| 28 | 28 | #include "soc15_common.h" |
| 29 | 29 | #include "psp_v13_0.h" |
| 30 | +#include "amdgpu_ras.h" | |
| 30 | 31 | |
| 31 | 32 | #include "mp/mp_13_0_2_offset.h" |
| 32 | 33 | #include "mp/mp_13_0_2_sh_mask.h" |
| @@ -187,11 +188,18 @@ static int psp_v13_0_wait_for_bootloader(struct psp_context *psp) · 154 unmodified lines | ||
| 187 | 188 | static int psp_v13_0_wait_for_bootloader_steady_state(struct psp_context *psp) |
| 188 | 189 | { |
| 189 | 190 | struct amdgpu_device *adev = psp->adev; |
| 191 | + int ret; | |
| 190 | 192 | |
| 191 | 193 | if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6)) { |
| 192 | − psp_v13_0_wait_for_vmbx_ready(psp); | |
| 194 | + ret = psp_v13_0_wait_for_vmbx_ready(psp); | |
| 195 | + if (ret) | |
| 196 | + amdgpu_ras_query_boot_status(adev, 4); | |
| 197 | + | |
| 198 | + ret = psp_v13_0_wait_for_bootloader(psp); | |
| 199 | + if (ret) | |
| 200 | + amdgpu_ras_query_boot_status(adev, 4); | |
| 193 | 201 | |
| 194 | − return psp_v13_0_wait_for_bootloader(psp); | |
| 202 | + return ret; | |
| 195 | 203 | } |
| 196 | 204 | |
| 197 | 205 | return 0; |
| @@ -763,81 +771,28 @@ static int psp_v13_0_fatal_error_recovery_quirk(struct psp_context *psp) · 565 unmodified lines | ||
| 763 | 771 | return 0; |
| 764 | 772 | } |
| 765 | 773 | |
| 766 | − | |
| 767 | −static void psp_v13_0_boot_error_reporting(struct amdgpu_device *adev, | |
| 768 | − uint32_t inst, | |
| 769 | − uint32_t boot_error) | |
| 770 | −{ | |
| 771 | − uint32_t socket_id; | |
| 772 | − uint32_t aid_id; | |
| 773 | − uint32_t hbm_id; | |
| 774 | − uint32_t reg_data; | |
| 775 | − | |
| 776 | − socket_id = REG_GET_FIELD(boot_error, MP0_SMN_C2PMSG_126, SOCKET_ID); | |
| 777 | − aid_id = REG_GET_FIELD(boot_error, MP0_SMN_C2PMSG_126, AID_ID); | |
| 778 | − hbm_id = REG_GET_FIELD(boot_error, MP0_SMN_C2PMSG_126, HBM_ID); | |
| 779 | − | |
| 780 | − reg_data = RREG32_SOC15(MP0, inst, regMP0_SMN_C2PMSG_109); | |
| 781 | − dev_info(adev->dev, "socket: %d, aid: %d, firmware boot failed, fw status is 0x%x\n", | |
| 782 | − socket_id, aid_id, reg_data); | |
| 783 | − | |
| 784 | − if (REG_GET_FIELD(boot_error, MP0_SMN_C2PMSG_126, GPU_ERR_MEM_TRAINING)) | |
| 785 | − dev_info(adev->dev, "socket: %d, aid: %d, hbm: %d, memory training failed\n", | |
| 786 | − socket_id, aid_id, hbm_id); | |
| 787 | − | |
| 788 | − if (REG_GET_FIELD(boot_error, MP0_SMN_C2PMSG_126, GPU_ERR_FW_LOAD)) | |
| 789 | − dev_info(adev->dev, "socket: %d, aid: %d, firmware load failed at boot time\n", | |
| 790 | − socket_id, aid_id); | |
| 791 | − | |
| 792 | − if (REG_GET_FIELD(boot_error, MP0_SMN_C2PMSG_126, GPU_ERR_WAFL_LINK_TRAINING)) | |
| 793 | − dev_info(adev->dev, "socket: %d, aid: %d, wafl link training failed\n", | |
| 794 | − socket_id, aid_id); | |
| 795 | − | |
| 796 | − if (REG_GET_FIELD(boot_error, MP0_SMN_C2PMSG_126, GPU_ERR_XGMI_LINK_TRAINING)) | |
| 797 | − dev_info(adev->dev, "socket: %d, aid: %d, xgmi link training failed\n", | |
| 798 | − socket_id, aid_id); | |
| 799 | − | |
| 800 | − if (REG_GET_FIELD(boot_error, MP0_SMN_C2PMSG_126, GPU_ERR_USR_CP_LINK_TRAINING)) | |
| 801 | − dev_info(adev->dev, "socket: %d, aid: %d, usr cp link training failed\n", | |
| 802 | − socket_id, aid_id); | |
| 803 | − | |
| 804 | − if (REG_GET_FIELD(boot_error, MP0_SMN_C2PMSG_126, GPU_ERR_USR_DP_LINK_TRAINING)) | |
| 805 | − dev_info(adev->dev, "socket: %d, aid: %d, usr dp link training failed\n", | |
| 806 | − socket_id, aid_id); | |
| 807 | − | |
| 808 | − if (REG_GET_FIELD(boot_error, MP0_SMN_C2PMSG_126, GPU_ERR_HBM_MEM_TEST)) | |
| 809 | − dev_info(adev->dev, "socket: %d, aid: %d, hbm: %d, hbm memory test failed\n", | |
| 810 | − socket_id, aid_id, hbm_id); | |
| 811 | − | |
| 812 | − if (REG_GET_FIELD(boot_error, MP0_SMN_C2PMSG_126, GPU_ERR_HBM_BIST_TEST)) | |
| 813 | − dev_info(adev->dev, "socket: %d, aid: %d, hbm: %d, hbm bist test failed\n", | |
| 814 | − socket_id, aid_id, hbm_id); | |
| 815 | −} | |
| 816 | − | |
| 817 | −static int psp_v13_0_query_boot_status(struct psp_context *psp) | |
| 774 | +static bool psp_v13_0_get_ras_capability(struct psp_context *psp) | |
| 818 | 775 | { |
| 819 | 776 | struct amdgpu_device *adev = psp->adev; |
| 820 | − int inst_mask = adev->aid_mask; | |
| 821 | − uint32_t reg_data; | |
| 822 | − uint32_t i; | |
| 823 | − int ret = 0; | |
| 777 | + struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
| 778 | + u32 reg_data; | |
| 824 | 779 | |
| 825 | − if (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6)) | |
| 826 | − return 0; | |
| 780 | + /* query ras cap should be done from host side */ | |
| 781 | + if (amdgpu_sriov_vf(adev)) | |
| 782 | + return false; | |
| 827 | 783 | |
| 828 | − if (RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_59) < 0x00a10109) | |
| 829 | − return 0; | |
| 784 | + if (!con) | |
| 785 | + return false; | |
| 830 | 786 | |
| 831 | − for_each_inst(i, inst_mask) { | |
| 832 | − reg_data = RREG32_SOC15(MP0, i, regMP0_SMN_C2PMSG_126); | |
| 833 | − if (!REG_GET_FIELD(reg_data, MP0_SMN_C2PMSG_126, BOOT_STATUS)) { | |
| 834 | − psp_v13_0_boot_error_reporting(adev, i, reg_data); | |
| 835 | − ret = -EINVAL; | |
| 836 | − break; | |
| 837 | − } | |
| 787 | + if ((amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6)) && | |
| 788 | + (!(adev->flags & AMD_IS_APU))) { | |
| 789 | + reg_data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_127); | |
| 790 | + adev->ras_hw_enabled = (reg_data & GENMASK_ULL(23, 0)); | |
| 791 | + con->poison_supported = ((reg_data & GENMASK_ULL(24, 24)) >> 24) ? true : false; | |
| 792 | + return true; | |
| 793 | + } else { | |
| 794 | + return false; | |
| 838 | 795 | } |
| 839 | − | |
| 840 | − return ret; | |
| 841 | 796 | } |
| 842 | 797 | |
| 843 | 798 | static const struct psp_funcs psp_v13_0_funcs = { |
| @@ -862,7 +817,7 @@ static const struct psp_funcs psp_v13_0_funcs = { · 18 unmodified lines | ||
| 862 | 817 | .update_spirom = psp_v13_0_update_spirom, |
| 863 | 818 | .vbflash_stat = psp_v13_0_vbflash_status, |
| 864 | 819 | .fatal_error_recovery_quirk = psp_v13_0_fatal_error_recovery_quirk, |
| 865 | − .query_boot_status = psp_v13_0_query_boot_status, | |
| 820 | + .get_ras_capability = psp_v13_0_get_ras_capability, | |
| 866 | 821 | }; |
| 867 | 822 | |
| 868 | 823 | void psp_v13_0_set_psp_funcs(struct psp_context *psp) |
| @@ -57,22 +57,19 @@ static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev); · 56 unmodified lines | ||
| 57 | 57 | MODULE_FIRMWARE("amdgpu/topaz_sdma.bin"); |
| 58 | 58 | MODULE_FIRMWARE("amdgpu/topaz_sdma1.bin"); |
| 59 | 59 | |
| 60 | −static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = | |
| 61 | −{ | |
| 60 | +static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = { | |
| 62 | 61 | SDMA0_REGISTER_OFFSET, |
| 63 | 62 | SDMA1_REGISTER_OFFSET |
| 64 | 63 | }; |
| 65 | 64 | |
| 66 | −static const u32 golden_settings_iceland_a11[] = | |
| 67 | −{ | |
| 65 | +static const u32 golden_settings_iceland_a11[] = { | |
| 68 | 66 | mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, |
| 69 | 67 | mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, |
| 70 | 68 | mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, |
| 71 | 69 | mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, |
| 72 | 70 | }; |
| 73 | 71 | |
| 74 | −static const u32 iceland_mgcg_cgcg_init[] = | |
| 75 | −{ | |
| 72 | +static const u32 iceland_mgcg_cgcg_init[] = { | |
| 76 | 73 | mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, |
| 77 | 74 | mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 |
| 78 | 75 | }; |
| @@ -142,7 +139,8 @@ static int sdma_v2_4_init_microcode(struct amdgpu_device *adev) · 63 unmodified lines | ||
| 142 | 139 | case CHIP_TOPAZ: |
| 143 | 140 | chip_name = "topaz"; |
| 144 | 141 | break; |
| 145 | − default: BUG(); | |
| 142 | + default: | |
| 143 | + BUG(); | |
| 146 | 144 | } |
| 147 | 145 | |
| 148 | 146 | for (i = 0; i < adev->sdma.num_instances; i++) { |
| @@ -1258,8 +1256,7 @@ static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev) · 1109 unmodified lines | ||
| 1258 | 1256 | adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; |
| 1259 | 1257 | } |
| 1260 | 1258 | |
| 1261 | −const struct amdgpu_ip_block_version sdma_v2_4_ip_block = | |
| 1262 | −{ | |
| 1259 | +const struct amdgpu_ip_block_version sdma_v2_4_ip_block = { | |
| 1263 | 1260 | .type = AMD_IP_BLOCK_TYPE_SDMA, |
| 1264 | 1261 | .major = 2, |
| 1265 | 1262 | .minor = 4, |
| @@ -45,6 +45,8 @@ · 44 unmodified lines | ||
| 45 | 45 | |
| 46 | 46 | MODULE_FIRMWARE("amdgpu/sdma_4_4_2.bin"); |
| 47 | 47 | |
| 48 | +#define mmSMNAID_AID0_MCA_SMU 0x03b30400 | |
| 49 | + | |
| 48 | 50 | #define WREG32_SDMA(instance, offset, value) \ |
| 49 | 51 | WREG32(sdma_v4_4_2_get_reg_offset(adev, (instance), (offset)), value) |
| 50 | 52 | #define RREG32_SDMA(instance, offset) \ |
| @@ -2204,9 +2206,79 @@ static const struct amdgpu_ras_block_hw_ops sdma_v4_4_2_ras_hw_ops = { · 2153 unmodified lines | ||
| 2204 | 2206 | .reset_ras_error_count = sdma_v4_4_2_reset_ras_error_count, |
| 2205 | 2207 | }; |
| 2206 | 2208 | |
| 2209 | +static int sdma_v4_4_2_aca_bank_generate_report(struct aca_handle *handle, | |
| 2210 | + struct aca_bank *bank, enum aca_error_type type, | |
| 2211 | + struct aca_bank_report *report, void *data) | |
| 2212 | +{ | |
| 2213 | + u64 status, misc0; | |
| 2214 | + int ret; | |
| 2215 | + | |
| 2216 | + status = bank->regs[ACA_REG_IDX_STATUS]; | |
| 2217 | + if ((type == ACA_ERROR_TYPE_UE && | |
| 2218 | + ACA_REG__STATUS__ERRORCODEEXT(status) == ACA_EXTERROR_CODE_FAULT) || | |
| 2219 | + (type == ACA_ERROR_TYPE_CE && | |
| 2220 | + ACA_REG__STATUS__ERRORCODEEXT(status) == ACA_EXTERROR_CODE_CE)) { | |
| 2221 | + | |
| 2222 | + ret = aca_bank_info_decode(bank, &report->info); | |
| 2223 | + if (ret) | |
| 2224 | + return ret; | |
| 2225 | + | |
| 2226 | + misc0 = bank->regs[ACA_REG_IDX_MISC0]; | |
| 2227 | + report->count[type] = ACA_REG__MISC0__ERRCNT(misc0); | |
| 2228 | + } | |
| 2229 | + | |
| 2230 | + return 0; | |
| 2231 | +} | |
| 2232 | + | |
| 2233 | +/* CODE_SDMA0 - CODE_SDMA4, reference to smu driver if header file */ | |
| 2234 | +static int sdma_v4_4_2_err_codes[] = { 33, 34, 35, 36 }; | |
| 2235 | + | |
| 2236 | +static bool sdma_v4_4_2_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, | |
| 2237 | + enum aca_error_type type, void *data) | |
| 2238 | +{ | |
| 2239 | + u32 instlo; | |
| 2240 | + | |
| 2241 | + instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); | |
| 2242 | + instlo &= GENMASK(31, 1); | |
| 2243 | + | |
| 2244 | + if (instlo != mmSMNAID_AID0_MCA_SMU) | |
| 2245 | + return false; | |
| 2246 | + | |
| 2247 | + if (aca_bank_check_error_codes(handle->adev, bank, | |
| 2248 | + sdma_v4_4_2_err_codes, | |
| 2249 | + ARRAY_SIZE(sdma_v4_4_2_err_codes))) | |
| 2250 | + return false; | |
| 2251 | + | |
| 2252 | + return true; | |
| 2253 | +} | |
| 2254 | + | |
| 2255 | +static const struct aca_bank_ops sdma_v4_4_2_aca_bank_ops = { | |
| 2256 | + .aca_bank_generate_report = sdma_v4_4_2_aca_bank_generate_report, | |
| 2257 | + .aca_bank_is_valid = sdma_v4_4_2_aca_bank_is_valid, | |
| 2258 | +}; | |
| 2259 | + | |
| 2260 | +static const struct aca_info sdma_v4_4_2_aca_info = { | |
| 2261 | + .hwip = ACA_HWIP_TYPE_SMU, | |
| 2262 | + .mask = ACA_ERROR_UE_MASK, | |
| 2263 | + .bank_ops = &sdma_v4_4_2_aca_bank_ops, | |
| 2264 | +}; | |
| 2265 | + | |
| 2266 | +static int sdma_v4_4_2_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) | |
| 2267 | +{ | |
| 2268 | + int r; | |
| 2269 | + | |
| 2270 | + r = amdgpu_sdma_ras_late_init(adev, ras_block); | |
| 2271 | + if (r) | |
| 2272 | + return r; | |
| 2273 | + | |
| 2274 | + return amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__SDMA, | |
| 2275 | + &sdma_v4_4_2_aca_info, NULL); | |
| 2276 | +} | |
| 2277 | + | |
| 2207 | 2278 | static struct amdgpu_sdma_ras sdma_v4_4_2_ras = { |
| 2208 | 2279 | .ras_block = { |
| 2209 | 2280 | .hw_ops = &sdma_v4_4_2_ras_hw_ops, |
| 2281 | + .ras_late_init = sdma_v4_4_2_ras_late_init, | |
| 2210 | 2282 | }, |
| 2211 | 2283 | }; |
| 2212 | 2284 | |
| @@ -119,6 +119,12 @@ static u32 si_ih_get_wptr(struct amdgpu_device *adev, · 118 unmodified lines | ||
| 119 | 119 | tmp = RREG32(IH_RB_CNTL); |
| 120 | 120 | tmp |= IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK; |
| 121 | 121 | WREG32(IH_RB_CNTL, tmp); |
| 122 | + | |
| 123 | + /* Unset the CLEAR_OVERFLOW bit immediately so new overflows | |
| 124 | + * can be detected. | |
| 125 | + */ | |
| 126 | + tmp &= ~IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK; | |
| 127 | + WREG32(IH_RB_CNTL, tmp); | |
| 122 | 128 | } |
| 123 | 129 | return (wptr & ih->ptr_mask); |
| 124 | 130 | } |
| @@ -1298,10 +1298,32 @@ static int soc15_common_suspend(void *handle) · 1297 unmodified lines | ||
| 1298 | 1298 | return soc15_common_hw_fini(adev); |
| 1299 | 1299 | } |
| 1300 | 1300 | |
| 1301 | +static bool soc15_need_reset_on_resume(struct amdgpu_device *adev) | |
| 1302 | +{ | |
| 1303 | + u32 sol_reg; | |
| 1304 | + | |
| 1305 | + sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); | |
| 1306 | + | |
| 1307 | + /* Will reset for the following suspend abort cases. | |
| 1308 | + * 1) Only reset limit on APU side, dGPU hasn't checked yet. | |
| 1309 | + * 2) S3 suspend abort and TOS already launched. | |
| 1310 | + */ | |
| 1311 | + if (adev->flags & AMD_IS_APU && adev->in_s3 && | |
| 1312 | + !adev->suspend_complete && | |
| 1313 | + sol_reg) | |
| 1314 | + return true; | |
| 1315 | + | |
| 1316 | + return false; | |
| 1317 | +} | |
| 1318 | + | |
| 1301 | 1319 | static int soc15_common_resume(void *handle) |
| 1302 | 1320 | { |
| 1303 | 1321 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 1304 | 1322 | |
| 1323 | + if (soc15_need_reset_on_resume(adev)) { | |
| 1324 | + dev_info(adev->dev, "S3 suspend abort case, let's reset ASIC.\n"); | |
| 1325 | + soc15_asic_reset(adev); | |
| 1326 | + } | |
| 1305 | 1327 | return soc15_common_hw_init(adev); |
| 1306 | 1328 | } |
| 1307 | 1329 | |
| @@ -36,6 +36,9 @@ enum ras_command { · 35 unmodified lines | ||
| 36 | 36 | TA_RAS_COMMAND__ENABLE_FEATURES = 0, |
| 37 | 37 | TA_RAS_COMMAND__DISABLE_FEATURES, |
| 38 | 38 | TA_RAS_COMMAND__TRIGGER_ERROR, |
| 39 | + TA_RAS_COMMAND__QUERY_BLOCK_INFO, | |
| 40 | + TA_RAS_COMMAND__QUERY_SUB_BLOCK_INFO, | |
| 41 | + TA_RAS_COMMAND__QUERY_ADDRESS, | |
| 39 | 42 | }; |
| 40 | 43 | |
| 41 | 44 | enum ta_ras_status { |
| @@ -105,6 +108,11 @@ enum ta_ras_error_type { · 63 unmodified lines | ||
| 105 | 108 | TA_RAS_ERROR__POISON = 8, |
| 106 | 109 | }; |
| 107 | 110 | |
| 111 | +enum ta_ras_address_type { | |
| 112 | + TA_RAS_MCA_TO_PA, | |
| 113 | + TA_RAS_PA_TO_MCA, | |
| 114 | +}; | |
| 115 | + | |
| 108 | 116 | /* Input/output structures for RAS commands */ |
| 109 | 117 | /**********************************************************/ |
| 110 | 118 | |
| @@ -133,12 +141,38 @@ struct ta_ras_init_flags { · 22 unmodified lines | ||
| 133 | 141 | uint8_t channel_dis_num; |
| 134 | 142 | }; |
| 135 | 143 | |
| 144 | +struct ta_ras_mca_addr { | |
| 145 | + uint64_t err_addr; | |
| 146 | + uint32_t ch_inst; | |
| 147 | + uint32_t umc_inst; | |
| 148 | + uint32_t node_inst; | |
| 149 | +}; | |
| 150 | + | |
| 151 | +struct ta_ras_phy_addr { | |
| 152 | + uint64_t pa; | |
| 153 | + uint32_t bank; | |
| 154 | + uint32_t channel_idx; | |
| 155 | +}; | |
| 156 | + | |
| 157 | +struct ta_ras_query_address_input { | |
| 158 | + enum ta_ras_address_type addr_type; | |
| 159 | + struct ta_ras_mca_addr ma; | |
| 160 | + struct ta_ras_phy_addr pa; | |
| 161 | +}; | |
| 162 | + | |
| 136 | 163 | struct ta_ras_output_flags { |
| 137 | 164 | uint8_t ras_init_success_flag; |
| 138 | 165 | uint8_t err_inject_switch_disable_flag; |
| 139 | 166 | uint8_t reg_access_failure_flag; |
| 140 | 167 | }; |
| 141 | 168 | |
| 169 | +struct ta_ras_query_address_output { | |
| 170 | + /* don't use the flags here */ | |
| 171 | + struct ta_ras_output_flags flags; | |
| 172 | + struct ta_ras_mca_addr ma; | |
| 173 | + struct ta_ras_phy_addr pa; | |
| 174 | +}; | |
| 175 | + | |
| 142 | 176 | /* Common input structure for RAS callbacks */ |
| 143 | 177 | /**********************************************************/ |
| 144 | 178 | union ta_ras_cmd_input { |
| @@ -146,12 +180,14 @@ union ta_ras_cmd_input { · 1 unmodified line | ||
| 146 | 180 | struct ta_ras_enable_features_input enable_features; |
| 147 | 181 | struct ta_ras_disable_features_input disable_features; |
| 148 | 182 | struct ta_ras_trigger_error_input trigger_error; |
| 183 | + struct ta_ras_query_address_input address; | |
| 149 | 184 | |
| 150 | 185 | uint32_t reserve_pad[256]; |
| 151 | 186 | }; |
| 152 | 187 | |
| 153 | 188 | union ta_ras_cmd_output { |
| 154 | 189 | struct ta_ras_output_flags flags; |
| 190 | + struct ta_ras_query_address_output address; | |
| 155 | 191 | |
| 156 | 192 | uint32_t reserve_pad[256]; |
| 157 | 193 | }; |
| @@ -219,6 +219,12 @@ static u32 tonga_ih_get_wptr(struct amdgpu_device *adev, · 218 unmodified lines | ||
| 219 | 219 | tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); |
| 220 | 220 | WREG32(mmIH_RB_CNTL, tmp); |
| 221 | 221 | |
| 222 | + /* Unset the CLEAR_OVERFLOW bit immediately so new overflows | |
| 223 | + * can be detected. | |
| 224 | + */ | |
| 225 | + tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0); | |
| 226 | + WREG32(mmIH_RB_CNTL, tmp); | |
| 227 | + | |
| 222 | 228 | out: |
| 223 | 229 | return (wptr & ih->ptr_mask); |
| 224 | 230 | } |
| @@ -89,12 +89,28 @@ static void umc_v12_0_reset_error_count(struct amdgpu_device *adev) · 88 unmodified lines | ||
| 89 | 89 | umc_v12_0_reset_error_count_per_channel, NULL); |
| 90 | 90 | } |
| 91 | 91 | |
| 92 | +bool umc_v12_0_is_deferred_error(struct amdgpu_device *adev, uint64_t mc_umc_status) | |
| 93 | +{ | |
| 94 | + dev_info(adev->dev, | |
| 95 | + "MCA_UMC_STATUS(0x%llx): Val:%llu, Poison:%llu, Deferred:%llu, PCC:%llu, UC:%llu, TCC:%llu\n", | |
| 96 | + mc_umc_status, | |
| 97 | + REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val), | |
| 98 | + REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Poison), | |
| 99 | + REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred), | |
| 100 | + REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC), | |
| 101 | + REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC), | |
| 102 | + REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) | |
| 103 | + ); | |
| 104 | + | |
| 105 | + return (amdgpu_ras_is_poison_mode_supported(adev) && | |
| 106 | + (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) && | |
| 107 | + (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1)); | |
| 108 | +} | |
| 109 | + | |
| 92 | 110 | bool umc_v12_0_is_uncorrectable_error(struct amdgpu_device *adev, uint64_t mc_umc_status) |
| 93 | 111 | { |
| 94 | − if (amdgpu_ras_is_poison_mode_supported(adev) && | |
| 95 | − (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) && | |
| 96 | − (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1)) | |
| 97 | − return true; | |
| 112 | + if (umc_v12_0_is_deferred_error(adev, mc_umc_status)) | |
| 113 | + return false; | |
| 98 | 114 | |
| 99 | 115 | return ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) && |
| 100 | 116 | (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 || |
| @@ -104,9 +120,7 @@ bool umc_v12_0_is_uncorrectable_error(struct amdgpu_device *adev, uint64_t mc_um · 3 unmodified lines | ||
| 104 | 120 | |
| 105 | 121 | bool umc_v12_0_is_correctable_error(struct amdgpu_device *adev, uint64_t mc_umc_status) |
| 106 | 122 | { |
| 107 | − if (amdgpu_ras_is_poison_mode_supported(adev) && | |
| 108 | − (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) && | |
| 109 | − (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1)) | |
| 123 | + if (umc_v12_0_is_deferred_error(adev, mc_umc_status)) | |
| 110 | 124 | return false; |
| 111 | 125 | |
| 112 | 126 | return (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && |
| @@ -119,9 +133,10 @@ bool umc_v12_0_is_correctable_error(struct amdgpu_device *adev, uint64_t mc_umc_ · 6 unmodified lines | ||
| 119 | 133 | !(umc_v12_0_is_uncorrectable_error(adev, mc_umc_status))))); |
| 120 | 134 | } |
| 121 | 135 | |
| 122 | −static void umc_v12_0_query_correctable_error_count(struct amdgpu_device *adev, | |
| 136 | +static void umc_v12_0_query_error_count_per_type(struct amdgpu_device *adev, | |
| 123 | 137 | uint64_t umc_reg_offset, |
| 124 | − unsigned long *error_count) | |
| 138 | + unsigned long *error_count, | |
| 139 | + check_error_type_func error_type_func) | |
| 125 | 140 | { |
| 126 | 141 | uint64_t mc_umc_status; |
| 127 | 142 | uint64_t mc_umc_status_addr; |
| @@ -129,31 +144,11 @@ static void umc_v12_0_query_correctable_error_count(struct amdgpu_device *adev, · 1 unmodified line | ||
| 129 | 144 | mc_umc_status_addr = |
| 130 | 145 | SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0); |
| 131 | 146 | |
| 132 | − /* Rely on MCUMC_STATUS for correctable error counter | |
| 133 | − * MCUMC_STATUS is a 64 bit register | |
| 134 | − */ | |
| 147 | + /* Check MCUMC_STATUS */ | |
| 135 | 148 | mc_umc_status = |
| 136 | 149 | RREG64_PCIE_EXT((mc_umc_status_addr + umc_reg_offset) * 4); |
| 137 | 150 | |
| 138 | − if (umc_v12_0_is_correctable_error(adev, mc_umc_status)) | |
| 139 | − *error_count += 1; | |
| 140 | −} | |
| 141 | − | |
| 142 | −static void umc_v12_0_query_uncorrectable_error_count(struct amdgpu_device *adev, | |
| 143 | − uint64_t umc_reg_offset, | |
| 144 | − unsigned long *error_count) | |
| 145 | −{ | |
| 146 | − uint64_t mc_umc_status; | |
| 147 | − uint64_t mc_umc_status_addr; | |
| 148 | − | |
| 149 | − mc_umc_status_addr = | |
| 150 | − SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0); | |
| 151 | − | |
| 152 | − /* Check the MCUMC_STATUS. */ | |
| 153 | − mc_umc_status = | |
| 154 | − RREG64_PCIE_EXT((mc_umc_status_addr + umc_reg_offset) * 4); | |
| 155 | − | |
| 156 | − if (umc_v12_0_is_uncorrectable_error(adev, mc_umc_status)) | |
| 151 | + if (error_type_func(adev, mc_umc_status)) | |
| 157 | 152 | *error_count += 1; |
| 158 | 153 | } |
| 159 | 154 | |
| @@ -162,7 +157,7 @@ static int umc_v12_0_query_error_count(struct amdgpu_device *adev, · 2 unmodified lines | ||
| 162 | 157 | uint32_t ch_inst, void *data) |
| 163 | 158 | { |
| 164 | 159 | struct ras_err_data *err_data = (struct ras_err_data *)data; |
| 165 | − unsigned long ue_count = 0, ce_count = 0; | |
| 160 | + unsigned long ue_count = 0, ce_count = 0, de_count = 0; | |
| 166 | 161 | |
| 167 | 162 | /* NOTE: node_inst is converted by adev->umc.active_mask and the range is [0-3], |
| 168 | 163 | * which can be used as die ID directly */ |
| @@ -174,11 +169,16 @@ static int umc_v12_0_query_error_count(struct amdgpu_device *adev, · 5 unmodified lines | ||
| 174 | 169 | uint64_t umc_reg_offset = |
| 175 | 170 | get_umc_v12_0_reg_offset(adev, node_inst, umc_inst, ch_inst); |
| 176 | 171 | |
| 177 | − umc_v12_0_query_correctable_error_count(adev, umc_reg_offset, &ce_count); | |
| 178 | − umc_v12_0_query_uncorrectable_error_count(adev, umc_reg_offset, &ue_count); | |
| 172 | + umc_v12_0_query_error_count_per_type(adev, umc_reg_offset, | |
| 173 | + &ce_count, umc_v12_0_is_correctable_error); | |
| 174 | + umc_v12_0_query_error_count_per_type(adev, umc_reg_offset, | |
| 175 | + &ue_count, umc_v12_0_is_uncorrectable_error); | |
| 176 | + umc_v12_0_query_error_count_per_type(adev, umc_reg_offset, | |
| 177 | + &de_count, umc_v12_0_is_deferred_error); | |
| 179 | 178 | |
| 180 | 179 | amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, NULL, ue_count); |
| 181 | 180 | amdgpu_ras_error_statistic_ce_count(err_data, &mcm_info, NULL, ce_count); |
| 181 | + amdgpu_ras_error_statistic_de_count(err_data, &mcm_info, NULL, de_count); | |
| 182 | 182 | |
| 183 | 183 | return 0; |
| 184 | 184 | } |
| @@ -203,14 +203,14 @@ static bool umc_v12_0_bit_wise_xor(uint32_t val) · 18 unmodified lines | ||
| 203 | 203 | return result; |
| 204 | 204 | } |
| 205 | 205 | |
| 206 | −static void umc_v12_0_convert_error_address(struct amdgpu_device *adev, | |
| 207 | − struct ras_err_data *err_data, uint64_t err_addr, | |
| 208 | − uint32_t ch_inst, uint32_t umc_inst, | |
| 209 | − uint32_t node_inst) | |
| 206 | +static void umc_v12_0_mca_addr_to_pa(struct amdgpu_device *adev, | |
| 207 | + uint64_t err_addr, uint32_t ch_inst, uint32_t umc_inst, | |
| 208 | + uint32_t node_inst, | |
| 209 | + struct ta_ras_query_address_output *addr_out) | |
| 210 | 210 | { |
| 211 | 211 | uint32_t channel_index, i; |
| 212 | − uint64_t soc_pa, na, retired_page, column; | |
| 213 | − uint32_t bank_hash0, bank_hash1, bank_hash2, bank_hash3, col, row, row_xor; | |
| 212 | + uint64_t na, soc_pa; | |
| 213 | + uint32_t bank_hash0, bank_hash1, bank_hash2, bank_hash3, col, row; | |
| 214 | 214 | uint32_t bank0, bank1, bank2, bank3, bank; |
| 215 | 215 | |
| 216 | 216 | bank_hash0 = (err_addr >> UMC_V12_0_MCA_B0_BIT) & 0x1ULL; |
| @@ -260,12 +260,44 @@ static void umc_v12_0_convert_error_address(struct amdgpu_device *adev, · 43 unmodified lines | ||
| 260 | 260 | /* the umc channel bits are not original values, they are hashed */ |
| 261 | 261 | UMC_V12_0_SET_CHANNEL_HASH(channel_index, soc_pa); |
| 262 | 262 | |
| 263 | + addr_out->pa.pa = soc_pa; | |
| 264 | + addr_out->pa.bank = bank; | |
| 265 | + addr_out->pa.channel_idx = channel_index; | |
| 266 | +} | |
| 267 | + | |
| 268 | +static void umc_v12_0_convert_error_address(struct amdgpu_device *adev, | |
| 269 | + struct ras_err_data *err_data, uint64_t err_addr, | |
| 270 | + uint32_t ch_inst, uint32_t umc_inst, | |
| 271 | + uint32_t node_inst) | |
| 272 | +{ | |
| 273 | + uint32_t col, row, row_xor, bank, channel_index; | |
| 274 | + uint64_t soc_pa, retired_page, column; | |
| 275 | + struct ta_ras_query_address_input addr_in; | |
| 276 | + struct ta_ras_query_address_output addr_out; | |
| 277 | + | |
| 278 | + addr_in.addr_type = TA_RAS_MCA_TO_PA; | |
| 279 | + addr_in.ma.err_addr = err_addr; | |
| 280 | + addr_in.ma.ch_inst = ch_inst; | |
| 281 | + addr_in.ma.umc_inst = umc_inst; | |
| 282 | + addr_in.ma.node_inst = node_inst; | |
| 283 | + | |
| 284 | + if (psp_ras_query_address(&adev->psp, &addr_in, &addr_out)) | |
| 285 | + /* fallback to old path if fail to get pa from psp */ | |
| 286 | + umc_v12_0_mca_addr_to_pa(adev, err_addr, ch_inst, umc_inst, | |
| 287 | + node_inst, &addr_out); | |
| 288 | + | |
| 289 | + soc_pa = addr_out.pa.pa; | |
| 290 | + bank = addr_out.pa.bank; | |
| 291 | + channel_index = addr_out.pa.channel_idx; | |
| 292 | + | |
| 293 | + col = (err_addr >> 1) & 0x1fULL; | |
| 294 | + row = (err_addr >> 10) & 0x3fffULL; | |
| 295 | + row_xor = row ^ (0x1ULL << 13); | |
| 263 | 296 | /* clear [C3 C2] in soc physical address */ |
| 264 | 297 | soc_pa &= ~(0x3ULL << UMC_V12_0_PA_C2_BIT); |
| 265 | 298 | /* clear [C4] in soc physical address */ |
| 266 | 299 | soc_pa &= ~(0x1ULL << UMC_V12_0_PA_C4_BIT); |
| 267 | 300 | |
| 268 | − row_xor = row ^ (0x1ULL << 13); | |
| 269 | 301 | /* loop for all possibilities of [C4 C3 C2] */ |
| 270 | 302 | for (column = 0; column < UMC_V12_0_NA_MAP_PA_NUM; column++) { |
| 271 | 303 | retired_page = soc_pa | ((column & 0x3) << UMC_V12_0_PA_C2_BIT); |
| @@ -316,10 +348,7 @@ static int umc_v12_0_query_error_address(struct amdgpu_device *adev, · 44 unmodified lines | ||
| 316 | 348 | } |
| 317 | 349 | |
| 318 | 350 | /* calculate error address if ue error is detected */ |
| 319 | − if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && | |
| 320 | − REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, AddrV) == 1 && | |
| 321 | − REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1) { | |
| 322 | − | |
| 351 | + if (umc_v12_0_is_uncorrectable_error(adev, mc_umc_status)) { | |
| 323 | 352 | mc_umc_addrt0 = |
| 324 | 353 | SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_ADDRT0); |
| 325 | 354 | |
| @@ -385,45 +414,69 @@ static void umc_v12_0_ecc_info_query_ras_error_address(struct amdgpu_device *ade · 59 unmodified lines | ||
| 385 | 414 | { |
| 386 | 415 | struct ras_err_node *err_node; |
| 387 | 416 | uint64_t mc_umc_status; |
| 417 | + struct ras_err_info *err_info; | |
| 418 | + struct ras_err_addr *mca_err_addr, *tmp; | |
| 388 | 419 | struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; |
| 389 | 420 | |
| 390 | 421 | for_each_ras_error(err_node, err_data) { |
| 391 | − mc_umc_status = err_node->err_info.err_addr.err_status; | |
| 392 | − if (!mc_umc_status) | |
| 422 | + err_info = &err_node->err_info; | |
| 423 | + if (list_empty(&err_info->err_addr_list)) | |
| 393 | 424 | continue; |
| 394 | 425 | |
| 395 | − if (umc_v12_0_is_uncorrectable_error(adev, mc_umc_status)) { | |
| 396 | − uint64_t mca_addr, err_addr, mca_ipid; | |
| 397 | − uint32_t InstanceIdLo; | |
| 398 | − struct amdgpu_smuio_mcm_config_info *mcm_info; | |
| 399 | − | |
| 400 | − mcm_info = &err_node->err_info.mcm_info; | |
| 401 | − mca_addr = err_node->err_info.err_addr.err_addr; | |
| 402 | − mca_ipid = err_node->err_info.err_addr.err_ipid; | |
| 403 | − | |
| 404 | − err_addr = REG_GET_FIELD(mca_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr); | |
| 405 | − InstanceIdLo = REG_GET_FIELD(mca_ipid, MCMP1_IPIDT0, InstanceIdLo); | |
| 406 | − | |
| 407 | − dev_info(adev->dev, "UMC:IPID:0x%llx, aid:%d, inst:%d, ch:%d, err_addr:0x%llx\n", | |
| 408 | − mca_ipid, | |
| 409 | − mcm_info->die_id, | |
| 410 | − MCA_IPID_LO_2_UMC_INST(InstanceIdLo), | |
| 411 | − MCA_IPID_LO_2_UMC_CH(InstanceIdLo), | |
| 412 | − err_addr); | |
| 413 | − | |
| 414 | − umc_v12_0_convert_error_address(adev, | |
| 415 | − err_data, err_addr, | |
| 416 | − MCA_IPID_LO_2_UMC_CH(InstanceIdLo), | |
| 417 | − MCA_IPID_LO_2_UMC_INST(InstanceIdLo), | |
| 418 | − mcm_info->die_id); | |
| 419 | − | |
| 420 | − /* Clear umc error address content */ | |
| 421 | − memset(&err_node->err_info.err_addr, | |
| 422 | − 0, sizeof(err_node->err_info.err_addr)); | |
| 426 | + list_for_each_entry_safe(mca_err_addr, tmp, &err_info->err_addr_list, node) { | |
| 427 | + mc_umc_status = mca_err_addr->err_status; | |
| 428 | + if (mc_umc_status && | |
| 429 | + (umc_v12_0_is_uncorrectable_error(adev, mc_umc_status) || | |
| 430 | + umc_v12_0_is_deferred_error(adev, mc_umc_status))) { | |
| 431 | + uint64_t mca_addr, err_addr, mca_ipid; | |
| 432 | + uint32_t InstanceIdLo; | |
| 433 | + | |
| 434 | + mca_addr = mca_err_addr->err_addr; | |
| 435 | + mca_ipid = mca_err_addr->err_ipid; | |
| 436 | + | |
| 437 | + err_addr = REG_GET_FIELD(mca_addr, | |
| 438 | + MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr); | |
| 439 | + InstanceIdLo = REG_GET_FIELD(mca_ipid, MCMP1_IPIDT0, InstanceIdLo); | |
| 440 | + | |
| 441 | + dev_info(adev->dev, "UMC:IPID:0x%llx, aid:%d, inst:%d, ch:%d, err_addr:0x%llx\n", | |
| 442 | + mca_ipid, | |
| 443 | + err_info->mcm_info.die_id, | |
| 444 | + MCA_IPID_LO_2_UMC_INST(InstanceIdLo), | |
| 445 | + MCA_IPID_LO_2_UMC_CH(InstanceIdLo), | |
| 446 | + err_addr); | |
| 447 | + | |
| 448 | + umc_v12_0_convert_error_address(adev, | |
| 449 | + err_data, err_addr, | |
| 450 | + MCA_IPID_LO_2_UMC_CH(InstanceIdLo), | |
| 451 | + MCA_IPID_LO_2_UMC_INST(InstanceIdLo), | |
| 452 | + err_info->mcm_info.die_id); | |
| 453 | + } | |
| 454 | + | |
| 455 | + /* Delete error address node from list and free memory */ | |
| 456 | + amdgpu_ras_del_mca_err_addr(err_info, mca_err_addr); | |
| 423 | 457 | } |
| 424 | 458 | } |
| 425 | 459 | } |
| 426 | 460 | |
| 461 | +static bool umc_v12_0_check_ecc_err_status(struct amdgpu_device *adev, | |
| 462 | + enum amdgpu_mca_error_type type, void *ras_error_status) | |
| 463 | +{ | |
| 464 | + uint64_t mc_umc_status = *(uint64_t *)ras_error_status; | |
| 465 | + | |
| 466 | + switch (type) { | |
| 467 | + case AMDGPU_MCA_ERROR_TYPE_UE: | |
| 468 | + return umc_v12_0_is_uncorrectable_error(adev, mc_umc_status); | |
| 469 | + case AMDGPU_MCA_ERROR_TYPE_CE: | |
| 470 | + return umc_v12_0_is_correctable_error(adev, mc_umc_status); | |
| 471 | + case AMDGPU_MCA_ERROR_TYPE_DE: | |
| 472 | + return umc_v12_0_is_deferred_error(adev, mc_umc_status); | |
| 473 | + default: | |
| 474 | + return false; | |
| 475 | + } | |
| 476 | + | |
| 477 | + return false; | |
| 478 | +} | |
| 479 | + | |
| 427 | 480 | static void umc_v12_0_err_cnt_init(struct amdgpu_device *adev) |
| 428 | 481 | { |
| 429 | 482 | amdgpu_umc_loop_channels(adev, |
| @@ -444,12 +497,71 @@ const struct amdgpu_ras_block_hw_ops umc_v12_0_ras_hw_ops = { · 14 unmodified lines | ||
| 444 | 497 | .query_ras_error_address = umc_v12_0_query_ras_error_address, |
| 445 | 498 | }; |
| 446 | 499 | |
| 500 | +static int umc_v12_0_aca_bank_generate_report(struct aca_handle *handle, struct aca_bank *bank, enum aca_error_type type, | |
| 501 | + struct aca_bank_report *report, void *data) | |
| 502 | +{ | |
| 503 | + struct amdgpu_device *adev = handle->adev; | |
| 504 | + u64 status; | |
| 505 | + int ret; | |
| 506 | + | |
| 507 | + ret = aca_bank_info_decode(bank, &report->info); | |
| 508 | + if (ret) | |
| 509 | + return ret; | |
| 510 | + | |
| 511 | + status = bank->regs[ACA_REG_IDX_STATUS]; | |
| 512 | + switch (type) { | |
| 513 | + case ACA_ERROR_TYPE_UE: | |
| 514 | + if (umc_v12_0_is_uncorrectable_error(adev, status)) { | |
| 515 | + report->count[type] = 1; | |
| 516 | + } | |
| 517 | + break; | |
| 518 | + case ACA_ERROR_TYPE_CE: | |
| 519 | + if (umc_v12_0_is_correctable_error(adev, status)) { | |
| 520 | + report->count[type] = 1; | |
| 521 | + } | |
| 522 | + break; | |
| 523 | + default: | |
| 524 | + return -EINVAL; | |
| 525 | + } | |
| 526 | + | |
| 527 | + return 0; | |
| 528 | +} | |
| 529 | + | |
| 530 | +static const struct aca_bank_ops umc_v12_0_aca_bank_ops = { | |
| 531 | + .aca_bank_generate_report = umc_v12_0_aca_bank_generate_report, | |
| 532 | +}; | |
| 533 | + | |
| 534 | +const struct aca_info umc_v12_0_aca_info = { | |
| 535 | + .hwip = ACA_HWIP_TYPE_UMC, | |
| 536 | + .mask = ACA_ERROR_UE_MASK | ACA_ERROR_CE_MASK, | |
| 537 | + .bank_ops = &umc_v12_0_aca_bank_ops, | |
| 538 | +}; | |
| 539 | + | |
| 540 | +static int umc_v12_0_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) | |
| 541 | +{ | |
| 542 | + int ret; | |
| 543 | + | |
| 544 | + ret = amdgpu_umc_ras_late_init(adev, ras_block); | |
| 545 | + if (ret) | |
| 546 | + return ret; | |
| 547 | + | |
| 548 | + ret = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__UMC, | |
| 549 | + &umc_v12_0_aca_info, NULL); | |
| 550 | + if (ret) | |
| 551 | + return ret; | |
| 552 | + | |
| 553 | + return 0; | |
| 554 | +} | |
| 555 | + | |
| 447 | 556 | struct amdgpu_umc_ras umc_v12_0_ras = { |
| 448 | 557 | .ras_block = { |
| 449 | 558 | .hw_ops = &umc_v12_0_ras_hw_ops, |
| 559 | + .ras_late_init = umc_v12_0_ras_late_init, | |
| 450 | 560 | }, |
| 451 | 561 | .err_cnt_init = umc_v12_0_err_cnt_init, |
| 452 | 562 | .query_ras_poison_mode = umc_v12_0_query_ras_poison_mode, |
| 453 | 563 | .ecc_info_query_ras_error_count = umc_v12_0_ecc_info_query_ras_error_count, |
| 454 | 564 | .ecc_info_query_ras_error_address = umc_v12_0_ecc_info_query_ras_error_address, |
| 565 | + .check_ecc_err_status = umc_v12_0_check_ecc_err_status, | |
| 455 | 566 | }; |
| 567 | + | |
| @@ -121,9 +121,12 @@ · 120 unmodified lines | ||
| 121 | 121 | (((_ipid_lo) >> 12) & 0xF)) |
| 122 | 122 | #define MCA_IPID_LO_2_UMC_INST(_ipid_lo) (((_ipid_lo) >> 21) & 0x7) |
| 123 | 123 | |
| 124 | +bool umc_v12_0_is_deferred_error(struct amdgpu_device *adev, uint64_t mc_umc_status); | |
| 124 | 125 | bool umc_v12_0_is_uncorrectable_error(struct amdgpu_device *adev, uint64_t mc_umc_status); |
| 125 | 126 | bool umc_v12_0_is_correctable_error(struct amdgpu_device *adev, uint64_t mc_umc_status); |
| 126 | 127 | |
| 128 | +typedef bool (*check_error_type_func)(struct amdgpu_device *adev, uint64_t mc_umc_status); | |
| 129 | + | |
| 127 | 130 | extern const uint32_t |
| 128 | 131 | umc_v12_0_channel_idx_tbl[] |
| 129 | 132 | [UMC_V12_0_UMC_INSTANCE_NUM] |
| @@ -25,7 +25,7 @@ · 24 unmodified lines | ||
| 25 | 25 | |
| 26 | 26 | static void umc_v6_0_init_registers(struct amdgpu_device *adev) |
| 27 | 27 | { |
| 28 | − unsigned i,j; | |
| 28 | + unsigned i, j; | |
| 29 | 29 | |
| 30 | 30 | for (i = 0; i < 4; i++) |
| 31 | 31 | for (j = 0; j < 4; j++) |
| @@ -2017,22 +2017,6 @@ static int vcn_v4_0_set_powergating_state(void *handle, enum amd_powergating_sta · 2016 unmodified lines | ||
| 2017 | 2017 | return ret; |
| 2018 | 2018 | } |
| 2019 | 2019 | |
| 2020 | −/** | |
| 2021 | − * vcn_v4_0_set_interrupt_state - set VCN block interrupt state | |
| 2022 | − * | |
| 2023 | − * @adev: amdgpu_device pointer | |
| 2024 | − * @source: interrupt sources | |
| 2025 | − * @type: interrupt types | |
| 2026 | − * @state: interrupt states | |
| 2027 | − * | |
| 2028 | − * Set VCN block interrupt state | |
| 2029 | − */ | |
| 2030 | −static int vcn_v4_0_set_interrupt_state(struct amdgpu_device *adev, struct amdgpu_irq_src *source, | |
| 2031 | − unsigned type, enum amdgpu_interrupt_state state) | |
| 2032 | −{ | |
| 2033 | − return 0; | |
| 2034 | −} | |
| 2035 | − | |
| 2036 | 2020 | /** |
| 2037 | 2021 | * vcn_v4_0_set_ras_interrupt_state - set VCN block RAS interrupt state |
| 2038 | 2022 | * |
| @@ -2097,7 +2081,6 @@ static int vcn_v4_0_process_interrupt(struct amdgpu_device *adev, struct amdgpu_ · 58 unmodified lines | ||
| 2097 | 2081 | } |
| 2098 | 2082 | |
| 2099 | 2083 | static const struct amdgpu_irq_src_funcs vcn_v4_0_irq_funcs = { |
| 2100 | − .set = vcn_v4_0_set_interrupt_state, | |
| 2101 | 2084 | .process = vcn_v4_0_process_interrupt, |
| 2102 | 2085 | }; |
| 2103 | 2086 | |
| @@ -269,8 +269,6 @@ static int vcn_v4_0_5_hw_fini(void *handle) · 268 unmodified lines | ||
| 269 | 269 | vcn_v4_0_5_set_powergating_state(adev, AMD_PG_STATE_GATE); |
| 270 | 270 | } |
| 271 | 271 | } |
| 272 | − | |
| 273 | − amdgpu_irq_put(adev, &adev->vcn.inst[i].irq, 0); | |
| 274 | 272 | } |
| 275 | 273 | |
| 276 | 274 | return 0; |
| @@ -1668,22 +1666,6 @@ static int vcn_v4_0_5_set_powergating_state(void *handle, enum amd_powergating_s · 1391 unmodified lines | ||
| 1668 | 1666 | return ret; |
| 1669 | 1667 | } |
| 1670 | 1668 | |
| 1671 | −/** | |
| 1672 | − * vcn_v4_0_5_set_interrupt_state - set VCN block interrupt state | |
| 1673 | − * | |
| 1674 | − * @adev: amdgpu_device pointer | |
| 1675 | − * @source: interrupt sources | |
| 1676 | − * @type: interrupt types | |
| 1677 | − * @state: interrupt states | |
| 1678 | − * | |
| 1679 | − * Set VCN block interrupt state | |
| 1680 | − */ | |
| 1681 | −static int vcn_v4_0_5_set_interrupt_state(struct amdgpu_device *adev, struct amdgpu_irq_src *source, | |
| 1682 | − unsigned type, enum amdgpu_interrupt_state state) | |
| 1683 | −{ | |
| 1684 | − return 0; | |
| 1685 | −} | |
| 1686 | − | |
| 1687 | 1669 | /** |
| 1688 | 1670 | * vcn_v4_0_5_process_interrupt - process VCN block interrupt |
| 1689 | 1671 | * |
| @@ -1726,7 +1708,6 @@ static int vcn_v4_0_5_process_interrupt(struct amdgpu_device *adev, struct amdgp · 36 unmodified lines | ||
| 1726 | 1708 | } |
| 1727 | 1709 | |
| 1728 | 1710 | static const struct amdgpu_irq_src_funcs vcn_v4_0_5_irq_funcs = { |
| 1729 | − .set = vcn_v4_0_5_set_interrupt_state, | |
| 1730 | 1711 | .process = vcn_v4_0_5_process_interrupt, |
| 1731 | 1712 | }; |
| 1732 | 1713 | |
| @@ -373,6 +373,12 @@ static u32 vega10_ih_get_wptr(struct amdgpu_device *adev, · 372 unmodified lines | ||
| 373 | 373 | tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); |
| 374 | 374 | WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); |
| 375 | 375 | |
| 376 | + /* Unset the CLEAR_OVERFLOW bit immediately so new overflows | |
| 377 | + * can be detected. | |
| 378 | + */ | |
| 379 | + tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0); | |
| 380 | + WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); | |
| 381 | + | |
| 376 | 382 | out: |
| 377 | 383 | return (wptr & ih->ptr_mask); |
| 378 | 384 | } |
| @@ -421,6 +421,12 @@ static u32 vega20_ih_get_wptr(struct amdgpu_device *adev, · 420 unmodified lines | ||
| 421 | 421 | tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); |
| 422 | 422 | WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); |
| 423 | 423 | |
| 424 | + /* Unset the CLEAR_OVERFLOW bit immediately so new overflows | |
| 425 | + * can be detected. | |
| 426 | + */ | |
| 427 | + tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0); | |
| 428 | + WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); | |
| 429 | + | |
| 424 | 430 | out: |
| 425 | 431 | return (wptr & ih->ptr_mask); |
| 426 | 432 | } |
| @@ -674,7 +674,7 @@ static const uint32_t cwsr_trap_gfx9_hex[] = { · 673 unmodified lines | ||
| 674 | 674 | 0x86ea6a6a, 0x8f6e837a, |
| 675 | 675 | 0xb96ee0c2, 0xbf800002, |
| 676 | 676 | 0xb97a0002, 0xbf8a0000, |
| 677 | − 0xbe801f6c, 0xbf810000, | |
| 677 | + 0xbe801f6c, 0xbf9b0000, | |
| 678 | 678 | }; |
| 679 | 679 | |
| 680 | 680 | static const uint32_t cwsr_trap_nv1x_hex[] = { |
| @@ -1091,7 +1091,7 @@ static const uint32_t cwsr_trap_nv1x_hex[] = { · 410 unmodified lines | ||
| 1091 | 1091 | 0xb9eef807, 0x876dff6d, |
| 1092 | 1092 | 0x0000ffff, 0x87fe7e7e, |
| 1093 | 1093 | 0x87ea6a6a, 0xb9faf802, |
| 1094 | − 0xbe80226c, 0xbf810000, | |
| 1094 | + 0xbe80226c, 0xbf9b0000, | |
| 1095 | 1095 | 0xbf9f0000, 0xbf9f0000, |
| 1096 | 1096 | 0xbf9f0000, 0xbf9f0000, |
| 1097 | 1097 | 0xbf9f0000, 0x00000000, |
| @@ -1574,7 +1574,7 @@ static const uint32_t cwsr_trap_arcturus_hex[] = { · 476 unmodified lines | ||
| 1574 | 1574 | 0x86ea6a6a, 0x8f6e837a, |
| 1575 | 1575 | 0xb96ee0c2, 0xbf800002, |
| 1576 | 1576 | 0xb97a0002, 0xbf8a0000, |
| 1577 | − 0xbe801f6c, 0xbf810000, | |
| 1577 | + 0xbe801f6c, 0xbf9b0000, | |
| 1578 | 1578 | }; |
| 1579 | 1579 | |
| 1580 | 1580 | static const uint32_t cwsr_trap_aldebaran_hex[] = { |
| @@ -2065,7 +2065,7 @@ static const uint32_t cwsr_trap_aldebaran_hex[] = { · 484 unmodified lines | ||
| 2065 | 2065 | 0x86ea6a6a, 0x8f6e837a, |
| 2066 | 2066 | 0xb96ee0c2, 0xbf800002, |
| 2067 | 2067 | 0xb97a0002, 0xbf8a0000, |
| 2068 | − 0xbe801f6c, 0xbf810000, | |
| 2068 | + 0xbe801f6c, 0xbf9b0000, | |
| 2069 | 2069 | }; |
| 2070 | 2070 | |
| 2071 | 2071 | static const uint32_t cwsr_trap_gfx10_hex[] = { |
| @@ -2500,7 +2500,7 @@ static const uint32_t cwsr_trap_gfx10_hex[] = { · 428 unmodified lines | ||
| 2500 | 2500 | 0x876dff6d, 0x0000ffff, |
| 2501 | 2501 | 0x87fe7e7e, 0x87ea6a6a, |
| 2502 | 2502 | 0xb9faf802, 0xbe80226c, |
| 2503 | − 0xbf810000, 0xbf9f0000, | |
| 2503 | + 0xbf9b0000, 0xbf9f0000, | |
| 2504 | 2504 | 0xbf9f0000, 0xbf9f0000, |
| 2505 | 2505 | 0xbf9f0000, 0xbf9f0000, |
| 2506 | 2506 | }; |
| @@ -2944,7 +2944,7 @@ static const uint32_t cwsr_trap_gfx11_hex[] = { · 437 unmodified lines | ||
| 2944 | 2944 | 0xb8eef802, 0xbf0d866e, |
| 2945 | 2945 | 0xbfa20002, 0xb97af802, |
| 2946 | 2946 | 0xbe80486c, 0xb97af802, |
| 2947 | − 0xbe804a6c, 0xbfb00000, | |
| 2947 | + 0xbe804a6c, 0xbfb10000, | |
| 2948 | 2948 | 0xbf9f0000, 0xbf9f0000, |
| 2949 | 2949 | 0xbf9f0000, 0xbf9f0000, |
| 2950 | 2950 | 0xbf9f0000, 0x00000000, |
| @@ -3436,5 +3436,5 @@ static const uint32_t cwsr_trap_gfx9_4_3_hex[] = { · 485 unmodified lines | ||
| 3436 | 3436 | 0x86ea6a6a, 0x8f6e837a, |
| 3437 | 3437 | 0xb96ee0c2, 0xbf800002, |
| 3438 | 3438 | 0xb97a0002, 0xbf8a0000, |
| 3439 | − 0xbe801f6c, 0xbf810000, | |
| 3439 | + 0xbe801f6c, 0xbf9b0000, | |
| 3440 | 3440 | }; |
| @@ -1104,7 +1104,7 @@ L_RETURN_WITHOUT_PRIV: · 1103 unmodified lines | ||
| 1104 | 1104 | s_rfe_b64 s_restore_pc_lo //Return to the main shader program and resume execution |
| 1105 | 1105 | |
| 1106 | 1106 | L_END_PGM: |
| 1107 | − s_endpgm | |
| 1107 | + s_endpgm_saved | |
| 1108 | 1108 | end |
| 1109 | 1109 | |
| 1110 | 1110 | function write_hwreg_to_mem(s, s_rsrc, s_mem_offset) |
| @@ -921,7 +921,7 @@ L_RESTORE: · 920 unmodified lines | ||
| 921 | 921 | /* the END */ |
| 922 | 922 | /**************************************************************************/ |
| 923 | 923 | L_END_PGM: |
| 924 | − s_endpgm | |
| 924 | + s_endpgm_saved | |
| 925 | 925 | |
| 926 | 926 | end |
| 927 | 927 | |
| @@ -1442,7 +1442,9 @@ static int kfd_ioctl_unmap_memory_from_gpu(struct file *filep, · 1441 unmodified lines | ||
| 1442 | 1442 | kfd_flush_tlb(peer_pdd, TLB_FLUSH_HEAVYWEIGHT); |
| 1443 | 1443 | |
| 1444 | 1444 | /* Remove dma mapping after tlb flush to avoid IO_PAGE_FAULT */ |
| 1445 | − amdgpu_amdkfd_gpuvm_dmaunmap_mem(mem, peer_pdd->drm_priv); | |
| 1445 | + err = amdgpu_amdkfd_gpuvm_dmaunmap_mem(mem, peer_pdd->drm_priv); | |
| 1446 | + if (err) | |
| 1447 | + goto sync_memory_failed; | |
| 1446 | 1448 | } |
| 1447 | 1449 | |
| 1448 | 1450 | mutex_unlock(&p->mutex); |
| @@ -55,6 +55,7 @@ static struct kfd_gpu_cache_info kaveri_cache_info[] = { · 54 unmodified lines | ||
| 55 | 55 | /* TCP L1 Cache per CU */ |
| 56 | 56 | .cache_size = 16, |
| 57 | 57 | .cache_level = 1, |
| 58 | + .cache_line_size = 64, | |
| 58 | 59 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 59 | 60 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 60 | 61 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -64,6 +65,7 @@ static struct kfd_gpu_cache_info kaveri_cache_info[] = { · 3 unmodified lines | ||
| 64 | 65 | /* Scalar L1 Instruction Cache (in SQC module) per bank */ |
| 65 | 66 | .cache_size = 16, |
| 66 | 67 | .cache_level = 1, |
| 68 | + .cache_line_size = 64, | |
| 67 | 69 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 68 | 70 | CRAT_CACHE_FLAGS_INST_CACHE | |
| 69 | 71 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -73,6 +75,7 @@ static struct kfd_gpu_cache_info kaveri_cache_info[] = { · 3 unmodified lines | ||
| 73 | 75 | /* Scalar L1 Data Cache (in SQC module) per bank */ |
| 74 | 76 | .cache_size = 8, |
| 75 | 77 | .cache_level = 1, |
| 78 | + .cache_line_size = 64, | |
| 76 | 79 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 77 | 80 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 78 | 81 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -88,6 +91,7 @@ static struct kfd_gpu_cache_info carrizo_cache_info[] = { · 9 unmodified lines | ||
| 88 | 91 | /* TCP L1 Cache per CU */ |
| 89 | 92 | .cache_size = 16, |
| 90 | 93 | .cache_level = 1, |
| 94 | + .cache_line_size = 64, | |
| 91 | 95 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 92 | 96 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 93 | 97 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -95,8 +99,9 @@ static struct kfd_gpu_cache_info carrizo_cache_info[] = { · 1 unmodified line | ||
| 95 | 99 | }, |
| 96 | 100 | { |
| 97 | 101 | /* Scalar L1 Instruction Cache (in SQC module) per bank */ |
| 98 | − .cache_size = 8, | |
| 102 | + .cache_size = 32, | |
| 99 | 103 | .cache_level = 1, |
| 104 | + .cache_line_size = 64, | |
| 100 | 105 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 101 | 106 | CRAT_CACHE_FLAGS_INST_CACHE | |
| 102 | 107 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -104,8 +109,9 @@ static struct kfd_gpu_cache_info carrizo_cache_info[] = { · 1 unmodified line | ||
| 104 | 109 | }, |
| 105 | 110 | { |
| 106 | 111 | /* Scalar L1 Data Cache (in SQC module) per bank. */ |
| 107 | − .cache_size = 4, | |
| 112 | + .cache_size = 16, | |
| 108 | 113 | .cache_level = 1, |
| 114 | + .cache_line_size = 64, | |
| 109 | 115 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 110 | 116 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 111 | 117 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -135,6 +141,7 @@ static struct kfd_gpu_cache_info vega10_cache_info[] = { · 23 unmodified lines | ||
| 135 | 141 | /* TCP L1 Cache per CU */ |
| 136 | 142 | .cache_size = 16, |
| 137 | 143 | .cache_level = 1, |
| 144 | + .cache_line_size = 64, | |
| 138 | 145 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 139 | 146 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 140 | 147 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -144,6 +151,7 @@ static struct kfd_gpu_cache_info vega10_cache_info[] = { · 3 unmodified lines | ||
| 144 | 151 | /* Scalar L1 Instruction Cache per SQC */ |
| 145 | 152 | .cache_size = 32, |
| 146 | 153 | .cache_level = 1, |
| 154 | + .cache_line_size = 64, | |
| 147 | 155 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 148 | 156 | CRAT_CACHE_FLAGS_INST_CACHE | |
| 149 | 157 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -153,6 +161,7 @@ static struct kfd_gpu_cache_info vega10_cache_info[] = { · 3 unmodified lines | ||
| 153 | 161 | /* Scalar L1 Data Cache per SQC */ |
| 154 | 162 | .cache_size = 16, |
| 155 | 163 | .cache_level = 1, |
| 164 | + .cache_line_size = 64, | |
| 156 | 165 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 157 | 166 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 158 | 167 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -162,6 +171,7 @@ static struct kfd_gpu_cache_info vega10_cache_info[] = { · 3 unmodified lines | ||
| 162 | 171 | /* L2 Data Cache per GPU (Total Tex Cache) */ |
| 163 | 172 | .cache_size = 4096, |
| 164 | 173 | .cache_level = 2, |
| 174 | + .cache_line_size = 64, | |
| 165 | 175 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 166 | 176 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 167 | 177 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -174,6 +184,7 @@ static struct kfd_gpu_cache_info raven_cache_info[] = { · 6 unmodified lines | ||
| 174 | 184 | /* TCP L1 Cache per CU */ |
| 175 | 185 | .cache_size = 16, |
| 176 | 186 | .cache_level = 1, |
| 187 | + .cache_line_size = 64, | |
| 177 | 188 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 178 | 189 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 179 | 190 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -183,6 +194,7 @@ static struct kfd_gpu_cache_info raven_cache_info[] = { · 3 unmodified lines | ||
| 183 | 194 | /* Scalar L1 Instruction Cache per SQC */ |
| 184 | 195 | .cache_size = 32, |
| 185 | 196 | .cache_level = 1, |
| 197 | + .cache_line_size = 64, | |
| 186 | 198 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 187 | 199 | CRAT_CACHE_FLAGS_INST_CACHE | |
| 188 | 200 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -192,6 +204,7 @@ static struct kfd_gpu_cache_info raven_cache_info[] = { · 3 unmodified lines | ||
| 192 | 204 | /* Scalar L1 Data Cache per SQC */ |
| 193 | 205 | .cache_size = 16, |
| 194 | 206 | .cache_level = 1, |
| 207 | + .cache_line_size = 64, | |
| 195 | 208 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 196 | 209 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 197 | 210 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -201,6 +214,7 @@ static struct kfd_gpu_cache_info raven_cache_info[] = { · 3 unmodified lines | ||
| 201 | 214 | /* L2 Data Cache per GPU (Total Tex Cache) */ |
| 202 | 215 | .cache_size = 1024, |
| 203 | 216 | .cache_level = 2, |
| 217 | + .cache_line_size = 64, | |
| 204 | 218 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 205 | 219 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 206 | 220 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -213,6 +227,7 @@ static struct kfd_gpu_cache_info renoir_cache_info[] = { · 6 unmodified lines | ||
| 213 | 227 | /* TCP L1 Cache per CU */ |
| 214 | 228 | .cache_size = 16, |
| 215 | 229 | .cache_level = 1, |
| 230 | + .cache_line_size = 64, | |
| 216 | 231 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 217 | 232 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 218 | 233 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -222,6 +237,7 @@ static struct kfd_gpu_cache_info renoir_cache_info[] = { · 3 unmodified lines | ||
| 222 | 237 | /* Scalar L1 Instruction Cache per SQC */ |
| 223 | 238 | .cache_size = 32, |
| 224 | 239 | .cache_level = 1, |
| 240 | + .cache_line_size = 64, | |
| 225 | 241 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 226 | 242 | CRAT_CACHE_FLAGS_INST_CACHE | |
| 227 | 243 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -231,6 +247,7 @@ static struct kfd_gpu_cache_info renoir_cache_info[] = { · 3 unmodified lines | ||
| 231 | 247 | /* Scalar L1 Data Cache per SQC */ |
| 232 | 248 | .cache_size = 16, |
| 233 | 249 | .cache_level = 1, |
| 250 | + .cache_line_size = 64, | |
| 234 | 251 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 235 | 252 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 236 | 253 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -240,6 +257,7 @@ static struct kfd_gpu_cache_info renoir_cache_info[] = { · 3 unmodified lines | ||
| 240 | 257 | /* L2 Data Cache per GPU (Total Tex Cache) */ |
| 241 | 258 | .cache_size = 1024, |
| 242 | 259 | .cache_level = 2, |
| 260 | + .cache_line_size = 64, | |
| 243 | 261 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 244 | 262 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 245 | 263 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -252,6 +270,7 @@ static struct kfd_gpu_cache_info vega12_cache_info[] = { · 6 unmodified lines | ||
| 252 | 270 | /* TCP L1 Cache per CU */ |
| 253 | 271 | .cache_size = 16, |
| 254 | 272 | .cache_level = 1, |
| 273 | + .cache_line_size = 64, | |
| 255 | 274 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 256 | 275 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 257 | 276 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -261,6 +280,7 @@ static struct kfd_gpu_cache_info vega12_cache_info[] = { · 3 unmodified lines | ||
| 261 | 280 | /* Scalar L1 Instruction Cache per SQC */ |
| 262 | 281 | .cache_size = 32, |
| 263 | 282 | .cache_level = 1, |
| 283 | + .cache_line_size = 64, | |
| 264 | 284 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 265 | 285 | CRAT_CACHE_FLAGS_INST_CACHE | |
| 266 | 286 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -270,6 +290,7 @@ static struct kfd_gpu_cache_info vega12_cache_info[] = { · 3 unmodified lines | ||
| 270 | 290 | /* Scalar L1 Data Cache per SQC */ |
| 271 | 291 | .cache_size = 16, |
| 272 | 292 | .cache_level = 1, |
| 293 | + .cache_line_size = 64, | |
| 273 | 294 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 274 | 295 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 275 | 296 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -279,6 +300,7 @@ static struct kfd_gpu_cache_info vega12_cache_info[] = { · 3 unmodified lines | ||
| 279 | 300 | /* L2 Data Cache per GPU (Total Tex Cache) */ |
| 280 | 301 | .cache_size = 2048, |
| 281 | 302 | .cache_level = 2, |
| 303 | + .cache_line_size = 64, | |
| 282 | 304 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 283 | 305 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 284 | 306 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -291,6 +313,7 @@ static struct kfd_gpu_cache_info vega20_cache_info[] = { · 6 unmodified lines | ||
| 291 | 313 | /* TCP L1 Cache per CU */ |
| 292 | 314 | .cache_size = 16, |
| 293 | 315 | .cache_level = 1, |
| 316 | + .cache_line_size = 64, | |
| 294 | 317 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 295 | 318 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 296 | 319 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -300,6 +323,7 @@ static struct kfd_gpu_cache_info vega20_cache_info[] = { · 3 unmodified lines | ||
| 300 | 323 | /* Scalar L1 Instruction Cache per SQC */ |
| 301 | 324 | .cache_size = 32, |
| 302 | 325 | .cache_level = 1, |
| 326 | + .cache_line_size = 64, | |
| 303 | 327 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 304 | 328 | CRAT_CACHE_FLAGS_INST_CACHE | |
| 305 | 329 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -309,6 +333,7 @@ static struct kfd_gpu_cache_info vega20_cache_info[] = { · 3 unmodified lines | ||
| 309 | 333 | /* Scalar L1 Data Cache per SQC */ |
| 310 | 334 | .cache_size = 16, |
| 311 | 335 | .cache_level = 1, |
| 336 | + .cache_line_size = 64, | |
| 312 | 337 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 313 | 338 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 314 | 339 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -318,6 +343,7 @@ static struct kfd_gpu_cache_info vega20_cache_info[] = { · 3 unmodified lines | ||
| 318 | 343 | /* L2 Data Cache per GPU (Total Tex Cache) */ |
| 319 | 344 | .cache_size = 8192, |
| 320 | 345 | .cache_level = 2, |
| 346 | + .cache_line_size = 64, | |
| 321 | 347 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 322 | 348 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 323 | 349 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -330,6 +356,7 @@ static struct kfd_gpu_cache_info aldebaran_cache_info[] = { · 6 unmodified lines | ||
| 330 | 356 | /* TCP L1 Cache per CU */ |
| 331 | 357 | .cache_size = 16, |
| 332 | 358 | .cache_level = 1, |
| 359 | + .cache_line_size = 64, | |
| 333 | 360 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 334 | 361 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 335 | 362 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -339,6 +366,7 @@ static struct kfd_gpu_cache_info aldebaran_cache_info[] = { · 3 unmodified lines | ||
| 339 | 366 | /* Scalar L1 Instruction Cache per SQC */ |
| 340 | 367 | .cache_size = 32, |
| 341 | 368 | .cache_level = 1, |
| 369 | + .cache_line_size = 64, | |
| 342 | 370 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 343 | 371 | CRAT_CACHE_FLAGS_INST_CACHE | |
| 344 | 372 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -348,6 +376,7 @@ static struct kfd_gpu_cache_info aldebaran_cache_info[] = { · 3 unmodified lines | ||
| 348 | 376 | /* Scalar L1 Data Cache per SQC */ |
| 349 | 377 | .cache_size = 16, |
| 350 | 378 | .cache_level = 1, |
| 379 | + .cache_line_size = 64, | |
| 351 | 380 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 352 | 381 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 353 | 382 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -357,6 +386,7 @@ static struct kfd_gpu_cache_info aldebaran_cache_info[] = { · 3 unmodified lines | ||
| 357 | 386 | /* L2 Data Cache per GPU (Total Tex Cache) */ |
| 358 | 387 | .cache_size = 8192, |
| 359 | 388 | .cache_level = 2, |
| 389 | + .cache_line_size = 128, | |
| 360 | 390 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 361 | 391 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 362 | 392 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -369,6 +399,7 @@ static struct kfd_gpu_cache_info navi10_cache_info[] = { · 6 unmodified lines | ||
| 369 | 399 | /* TCP L1 Cache per CU */ |
| 370 | 400 | .cache_size = 16, |
| 371 | 401 | .cache_level = 1, |
| 402 | + .cache_line_size = 128, | |
| 372 | 403 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 373 | 404 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 374 | 405 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -378,6 +409,7 @@ static struct kfd_gpu_cache_info navi10_cache_info[] = { · 3 unmodified lines | ||
| 378 | 409 | /* Scalar L1 Instruction Cache per SQC */ |
| 379 | 410 | .cache_size = 32, |
| 380 | 411 | .cache_level = 1, |
| 412 | + .cache_line_size = 64, | |
| 381 | 413 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 382 | 414 | CRAT_CACHE_FLAGS_INST_CACHE | |
| 383 | 415 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -387,6 +419,7 @@ static struct kfd_gpu_cache_info navi10_cache_info[] = { · 3 unmodified lines | ||
| 387 | 419 | /* Scalar L1 Data Cache per SQC */ |
| 388 | 420 | .cache_size = 16, |
| 389 | 421 | .cache_level = 1, |
| 422 | + .cache_line_size = 64, | |
| 390 | 423 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 391 | 424 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 392 | 425 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -396,6 +429,7 @@ static struct kfd_gpu_cache_info navi10_cache_info[] = { · 3 unmodified lines | ||
| 396 | 429 | /* GL1 Data Cache per SA */ |
| 397 | 430 | .cache_size = 128, |
| 398 | 431 | .cache_level = 1, |
| 432 | + .cache_line_size = 128, | |
| 399 | 433 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 400 | 434 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 401 | 435 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -405,6 +439,7 @@ static struct kfd_gpu_cache_info navi10_cache_info[] = { · 3 unmodified lines | ||
| 405 | 439 | /* L2 Data Cache per GPU (Total Tex Cache) */ |
| 406 | 440 | .cache_size = 4096, |
| 407 | 441 | .cache_level = 2, |
| 442 | + .cache_line_size = 128, | |
| 408 | 443 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 409 | 444 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 410 | 445 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -417,6 +452,7 @@ static struct kfd_gpu_cache_info vangogh_cache_info[] = { · 6 unmodified lines | ||
| 417 | 452 | /* TCP L1 Cache per CU */ |
| 418 | 453 | .cache_size = 16, |
| 419 | 454 | .cache_level = 1, |
| 455 | + .cache_line_size = 128, | |
| 420 | 456 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 421 | 457 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 422 | 458 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -426,6 +462,7 @@ static struct kfd_gpu_cache_info vangogh_cache_info[] = { · 3 unmodified lines | ||
| 426 | 462 | /* Scalar L1 Instruction Cache per SQC */ |
| 427 | 463 | .cache_size = 32, |
| 428 | 464 | .cache_level = 1, |
| 465 | + .cache_line_size = 64, | |
| 429 | 466 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 430 | 467 | CRAT_CACHE_FLAGS_INST_CACHE | |
| 431 | 468 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -435,6 +472,7 @@ static struct kfd_gpu_cache_info vangogh_cache_info[] = { · 3 unmodified lines | ||
| 435 | 472 | /* Scalar L1 Data Cache per SQC */ |
| 436 | 473 | .cache_size = 16, |
| 437 | 474 | .cache_level = 1, |
| 475 | + .cache_line_size = 64, | |
| 438 | 476 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 439 | 477 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 440 | 478 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -444,6 +482,7 @@ static struct kfd_gpu_cache_info vangogh_cache_info[] = { · 3 unmodified lines | ||
| 444 | 482 | /* GL1 Data Cache per SA */ |
| 445 | 483 | .cache_size = 128, |
| 446 | 484 | .cache_level = 1, |
| 485 | + .cache_line_size = 128, | |
| 447 | 486 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 448 | 487 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 449 | 488 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -453,6 +492,7 @@ static struct kfd_gpu_cache_info vangogh_cache_info[] = { · 3 unmodified lines | ||
| 453 | 492 | /* L2 Data Cache per GPU (Total Tex Cache) */ |
| 454 | 493 | .cache_size = 1024, |
| 455 | 494 | .cache_level = 2, |
| 495 | + .cache_line_size = 128, | |
| 456 | 496 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 457 | 497 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 458 | 498 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -465,6 +505,7 @@ static struct kfd_gpu_cache_info navi14_cache_info[] = { · 6 unmodified lines | ||
| 465 | 505 | /* TCP L1 Cache per CU */ |
| 466 | 506 | .cache_size = 16, |
| 467 | 507 | .cache_level = 1, |
| 508 | + .cache_line_size = 128, | |
| 468 | 509 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 469 | 510 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 470 | 511 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -474,6 +515,7 @@ static struct kfd_gpu_cache_info navi14_cache_info[] = { · 3 unmodified lines | ||
| 474 | 515 | /* Scalar L1 Instruction Cache per SQC */ |
| 475 | 516 | .cache_size = 32, |
| 476 | 517 | .cache_level = 1, |
| 518 | + .cache_line_size = 64, | |
| 477 | 519 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 478 | 520 | CRAT_CACHE_FLAGS_INST_CACHE | |
| 479 | 521 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -483,6 +525,7 @@ static struct kfd_gpu_cache_info navi14_cache_info[] = { · 3 unmodified lines | ||
| 483 | 525 | /* Scalar L1 Data Cache per SQC */ |
| 484 | 526 | .cache_size = 16, |
| 485 | 527 | .cache_level = 1, |
| 528 | + .cache_line_size = 64, | |
| 486 | 529 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 487 | 530 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 488 | 531 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -492,6 +535,7 @@ static struct kfd_gpu_cache_info navi14_cache_info[] = { · 3 unmodified lines | ||
| 492 | 535 | /* GL1 Data Cache per SA */ |
| 493 | 536 | .cache_size = 128, |
| 494 | 537 | .cache_level = 1, |
| 538 | + .cache_line_size = 128, | |
| 495 | 539 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 496 | 540 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 497 | 541 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -501,6 +545,7 @@ static struct kfd_gpu_cache_info navi14_cache_info[] = { · 3 unmodified lines | ||
| 501 | 545 | /* L2 Data Cache per GPU (Total Tex Cache) */ |
| 502 | 546 | .cache_size = 2048, |
| 503 | 547 | .cache_level = 2, |
| 548 | + .cache_line_size = 128, | |
| 504 | 549 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 505 | 550 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 506 | 551 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -513,6 +558,7 @@ static struct kfd_gpu_cache_info sienna_cichlid_cache_info[] = { · 6 unmodified lines | ||
| 513 | 558 | /* TCP L1 Cache per CU */ |
| 514 | 559 | .cache_size = 16, |
| 515 | 560 | .cache_level = 1, |
| 561 | + .cache_line_size = 128, | |
| 516 | 562 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 517 | 563 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 518 | 564 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -522,6 +568,7 @@ static struct kfd_gpu_cache_info sienna_cichlid_cache_info[] = { · 3 unmodified lines | ||
| 522 | 568 | /* Scalar L1 Instruction Cache per SQC */ |
| 523 | 569 | .cache_size = 32, |
| 524 | 570 | .cache_level = 1, |
| 571 | + .cache_line_size = 64, | |
| 525 | 572 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 526 | 573 | CRAT_CACHE_FLAGS_INST_CACHE | |
| 527 | 574 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -531,6 +578,7 @@ static struct kfd_gpu_cache_info sienna_cichlid_cache_info[] = { · 3 unmodified lines | ||
| 531 | 578 | /* Scalar L1 Data Cache per SQC */ |
| 532 | 579 | .cache_size = 16, |
| 533 | 580 | .cache_level = 1, |
| 581 | + .cache_line_size = 64, | |
| 534 | 582 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 535 | 583 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 536 | 584 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -540,6 +588,7 @@ static struct kfd_gpu_cache_info sienna_cichlid_cache_info[] = { · 3 unmodified lines | ||
| 540 | 588 | /* GL1 Data Cache per SA */ |
| 541 | 589 | .cache_size = 128, |
| 542 | 590 | .cache_level = 1, |
| 591 | + .cache_line_size = 128, | |
| 543 | 592 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 544 | 593 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 545 | 594 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -549,6 +598,7 @@ static struct kfd_gpu_cache_info sienna_cichlid_cache_info[] = { · 3 unmodified lines | ||
| 549 | 598 | /* L2 Data Cache per GPU (Total Tex Cache) */ |
| 550 | 599 | .cache_size = 4096, |
| 551 | 600 | .cache_level = 2, |
| 601 | + .cache_line_size = 128, | |
| 552 | 602 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 553 | 603 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 554 | 604 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -558,6 +608,7 @@ static struct kfd_gpu_cache_info sienna_cichlid_cache_info[] = { · 3 unmodified lines | ||
| 558 | 608 | /* L3 Data Cache per GPU */ |
| 559 | 609 | .cache_size = 128*1024, |
| 560 | 610 | .cache_level = 3, |
| 611 | + .cache_line_size = 64, | |
| 561 | 612 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 562 | 613 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 563 | 614 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -570,6 +621,7 @@ static struct kfd_gpu_cache_info navy_flounder_cache_info[] = { · 6 unmodified lines | ||
| 570 | 621 | /* TCP L1 Cache per CU */ |
| 571 | 622 | .cache_size = 16, |
| 572 | 623 | .cache_level = 1, |
| 624 | + .cache_line_size = 128, | |
| 573 | 625 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 574 | 626 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 575 | 627 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -579,6 +631,7 @@ static struct kfd_gpu_cache_info navy_flounder_cache_info[] = { · 3 unmodified lines | ||
| 579 | 631 | /* Scalar L1 Instruction Cache per SQC */ |
| 580 | 632 | .cache_size = 32, |
| 581 | 633 | .cache_level = 1, |
| 634 | + .cache_line_size = 64, | |
| 582 | 635 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 583 | 636 | CRAT_CACHE_FLAGS_INST_CACHE | |
| 584 | 637 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -588,6 +641,7 @@ static struct kfd_gpu_cache_info navy_flounder_cache_info[] = { · 3 unmodified lines | ||
| 588 | 641 | /* Scalar L1 Data Cache per SQC */ |
| 589 | 642 | .cache_size = 16, |
| 590 | 643 | .cache_level = 1, |
| 644 | + .cache_line_size = 64, | |
| 591 | 645 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 592 | 646 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 593 | 647 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -597,6 +651,7 @@ static struct kfd_gpu_cache_info navy_flounder_cache_info[] = { · 3 unmodified lines | ||
| 597 | 651 | /* GL1 Data Cache per SA */ |
| 598 | 652 | .cache_size = 128, |
| 599 | 653 | .cache_level = 1, |
| 654 | + .cache_line_size = 128, | |
| 600 | 655 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 601 | 656 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 602 | 657 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -606,6 +661,7 @@ static struct kfd_gpu_cache_info navy_flounder_cache_info[] = { · 3 unmodified lines | ||
| 606 | 661 | /* L2 Data Cache per GPU (Total Tex Cache) */ |
| 607 | 662 | .cache_size = 3072, |
| 608 | 663 | .cache_level = 2, |
| 664 | + .cache_line_size = 128, | |
| 609 | 665 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 610 | 666 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 611 | 667 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -615,6 +671,7 @@ static struct kfd_gpu_cache_info navy_flounder_cache_info[] = { · 3 unmodified lines | ||
| 615 | 671 | /* L3 Data Cache per GPU */ |
| 616 | 672 | .cache_size = 96*1024, |
| 617 | 673 | .cache_level = 3, |
| 674 | + .cache_line_size = 64, | |
| 618 | 675 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 619 | 676 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 620 | 677 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -627,6 +684,7 @@ static struct kfd_gpu_cache_info dimgrey_cavefish_cache_info[] = { · 6 unmodified lines | ||
| 627 | 684 | /* TCP L1 Cache per CU */ |
| 628 | 685 | .cache_size = 16, |
| 629 | 686 | .cache_level = 1, |
| 687 | + .cache_line_size = 128, | |
| 630 | 688 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 631 | 689 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 632 | 690 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -636,6 +694,7 @@ static struct kfd_gpu_cache_info dimgrey_cavefish_cache_info[] = { · 3 unmodified lines | ||
| 636 | 694 | /* Scalar L1 Instruction Cache per SQC */ |
| 637 | 695 | .cache_size = 32, |
| 638 | 696 | .cache_level = 1, |
| 697 | + .cache_line_size = 64, | |
| 639 | 698 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 640 | 699 | CRAT_CACHE_FLAGS_INST_CACHE | |
| 641 | 700 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -645,6 +704,7 @@ static struct kfd_gpu_cache_info dimgrey_cavefish_cache_info[] = { · 3 unmodified lines | ||
| 645 | 704 | /* Scalar L1 Data Cache per SQC */ |
| 646 | 705 | .cache_size = 16, |
| 647 | 706 | .cache_level = 1, |
| 707 | + .cache_line_size = 64, | |
| 648 | 708 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 649 | 709 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 650 | 710 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -654,6 +714,7 @@ static struct kfd_gpu_cache_info dimgrey_cavefish_cache_info[] = { · 3 unmodified lines | ||
| 654 | 714 | /* GL1 Data Cache per SA */ |
| 655 | 715 | .cache_size = 128, |
| 656 | 716 | .cache_level = 1, |
| 717 | + .cache_line_size = 128, | |
| 657 | 718 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 658 | 719 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 659 | 720 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -663,6 +724,7 @@ static struct kfd_gpu_cache_info dimgrey_cavefish_cache_info[] = { · 3 unmodified lines | ||
| 663 | 724 | /* L2 Data Cache per GPU (Total Tex Cache) */ |
| 664 | 725 | .cache_size = 2048, |
| 665 | 726 | .cache_level = 2, |
| 727 | + .cache_line_size = 128, | |
| 666 | 728 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 667 | 729 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 668 | 730 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -672,6 +734,7 @@ static struct kfd_gpu_cache_info dimgrey_cavefish_cache_info[] = { · 3 unmodified lines | ||
| 672 | 734 | /* L3 Data Cache per GPU */ |
| 673 | 735 | .cache_size = 32*1024, |
| 674 | 736 | .cache_level = 3, |
| 737 | + .cache_line_size = 64, | |
| 675 | 738 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 676 | 739 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 677 | 740 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -684,6 +747,7 @@ static struct kfd_gpu_cache_info beige_goby_cache_info[] = { · 6 unmodified lines | ||
| 684 | 747 | /* TCP L1 Cache per CU */ |
| 685 | 748 | .cache_size = 16, |
| 686 | 749 | .cache_level = 1, |
| 750 | + .cache_line_size = 128, | |
| 687 | 751 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 688 | 752 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 689 | 753 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -693,6 +757,7 @@ static struct kfd_gpu_cache_info beige_goby_cache_info[] = { · 3 unmodified lines | ||
| 693 | 757 | /* Scalar L1 Instruction Cache per SQC */ |
| 694 | 758 | .cache_size = 32, |
| 695 | 759 | .cache_level = 1, |
| 760 | + .cache_line_size = 64, | |
| 696 | 761 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 697 | 762 | CRAT_CACHE_FLAGS_INST_CACHE | |
| 698 | 763 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -702,6 +767,7 @@ static struct kfd_gpu_cache_info beige_goby_cache_info[] = { · 3 unmodified lines | ||
| 702 | 767 | /* Scalar L1 Data Cache per SQC */ |
| 703 | 768 | .cache_size = 16, |
| 704 | 769 | .cache_level = 1, |
| 770 | + .cache_line_size = 64, | |
| 705 | 771 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 706 | 772 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 707 | 773 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -711,6 +777,7 @@ static struct kfd_gpu_cache_info beige_goby_cache_info[] = { · 3 unmodified lines | ||
| 711 | 777 | /* GL1 Data Cache per SA */ |
| 712 | 778 | .cache_size = 128, |
| 713 | 779 | .cache_level = 1, |
| 780 | + .cache_line_size = 128, | |
| 714 | 781 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 715 | 782 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 716 | 783 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -720,6 +787,7 @@ static struct kfd_gpu_cache_info beige_goby_cache_info[] = { · 3 unmodified lines | ||
| 720 | 787 | /* L2 Data Cache per GPU (Total Tex Cache) */ |
| 721 | 788 | .cache_size = 1024, |
| 722 | 789 | .cache_level = 2, |
| 790 | + .cache_line_size = 128, | |
| 723 | 791 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 724 | 792 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 725 | 793 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -729,6 +797,7 @@ static struct kfd_gpu_cache_info beige_goby_cache_info[] = { · 3 unmodified lines | ||
| 729 | 797 | /* L3 Data Cache per GPU */ |
| 730 | 798 | .cache_size = 16*1024, |
| 731 | 799 | .cache_level = 3, |
| 800 | + .cache_line_size = 64, | |
| 732 | 801 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 733 | 802 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 734 | 803 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -741,6 +810,7 @@ static struct kfd_gpu_cache_info yellow_carp_cache_info[] = { · 6 unmodified lines | ||
| 741 | 810 | /* TCP L1 Cache per CU */ |
| 742 | 811 | .cache_size = 16, |
| 743 | 812 | .cache_level = 1, |
| 813 | + .cache_line_size = 128, | |
| 744 | 814 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 745 | 815 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 746 | 816 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -750,6 +820,7 @@ static struct kfd_gpu_cache_info yellow_carp_cache_info[] = { · 3 unmodified lines | ||
| 750 | 820 | /* Scalar L1 Instruction Cache per SQC */ |
| 751 | 821 | .cache_size = 32, |
| 752 | 822 | .cache_level = 1, |
| 823 | + .cache_line_size = 64, | |
| 753 | 824 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 754 | 825 | CRAT_CACHE_FLAGS_INST_CACHE | |
| 755 | 826 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -759,6 +830,7 @@ static struct kfd_gpu_cache_info yellow_carp_cache_info[] = { · 3 unmodified lines | ||
| 759 | 830 | /* Scalar L1 Data Cache per SQC */ |
| 760 | 831 | .cache_size = 16, |
| 761 | 832 | .cache_level = 1, |
| 833 | + .cache_line_size = 64, | |
| 762 | 834 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 763 | 835 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 764 | 836 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -768,6 +840,7 @@ static struct kfd_gpu_cache_info yellow_carp_cache_info[] = { · 3 unmodified lines | ||
| 768 | 840 | /* GL1 Data Cache per SA */ |
| 769 | 841 | .cache_size = 128, |
| 770 | 842 | .cache_level = 1, |
| 843 | + .cache_line_size = 128, | |
| 771 | 844 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 772 | 845 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 773 | 846 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -777,6 +850,7 @@ static struct kfd_gpu_cache_info yellow_carp_cache_info[] = { · 3 unmodified lines | ||
| 777 | 850 | /* L2 Data Cache per GPU (Total Tex Cache) */ |
| 778 | 851 | .cache_size = 2048, |
| 779 | 852 | .cache_level = 2, |
| 853 | + .cache_line_size = 128, | |
| 780 | 854 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 781 | 855 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 782 | 856 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -789,6 +863,7 @@ static struct kfd_gpu_cache_info gfx1037_cache_info[] = { · 6 unmodified lines | ||
| 789 | 863 | /* TCP L1 Cache per CU */ |
| 790 | 864 | .cache_size = 16, |
| 791 | 865 | .cache_level = 1, |
| 866 | + .cache_line_size = 128, | |
| 792 | 867 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 793 | 868 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 794 | 869 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -798,6 +873,7 @@ static struct kfd_gpu_cache_info gfx1037_cache_info[] = { · 3 unmodified lines | ||
| 798 | 873 | /* Scalar L1 Instruction Cache per SQC */ |
| 799 | 874 | .cache_size = 32, |
| 800 | 875 | .cache_level = 1, |
| 876 | + .cache_line_size = 64, | |
| 801 | 877 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 802 | 878 | CRAT_CACHE_FLAGS_INST_CACHE | |
| 803 | 879 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -807,6 +883,7 @@ static struct kfd_gpu_cache_info gfx1037_cache_info[] = { · 3 unmodified lines | ||
| 807 | 883 | /* Scalar L1 Data Cache per SQC */ |
| 808 | 884 | .cache_size = 16, |
| 809 | 885 | .cache_level = 1, |
| 886 | + .cache_line_size = 64, | |
| 810 | 887 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 811 | 888 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 812 | 889 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -816,6 +893,7 @@ static struct kfd_gpu_cache_info gfx1037_cache_info[] = { · 3 unmodified lines | ||
| 816 | 893 | /* GL1 Data Cache per SA */ |
| 817 | 894 | .cache_size = 128, |
| 818 | 895 | .cache_level = 1, |
| 896 | + .cache_line_size = 128, | |
| 819 | 897 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 820 | 898 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 821 | 899 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -825,6 +903,7 @@ static struct kfd_gpu_cache_info gfx1037_cache_info[] = { · 3 unmodified lines | ||
| 825 | 903 | /* L2 Data Cache per GPU (Total Tex Cache) */ |
| 826 | 904 | .cache_size = 256, |
| 827 | 905 | .cache_level = 2, |
| 906 | + .cache_line_size = 128, | |
| 828 | 907 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 829 | 908 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 830 | 909 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -837,6 +916,7 @@ static struct kfd_gpu_cache_info gc_10_3_6_cache_info[] = { · 6 unmodified lines | ||
| 837 | 916 | /* TCP L1 Cache per CU */ |
| 838 | 917 | .cache_size = 16, |
| 839 | 918 | .cache_level = 1, |
| 919 | + .cache_line_size = 128, | |
| 840 | 920 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 841 | 921 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 842 | 922 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -846,6 +926,7 @@ static struct kfd_gpu_cache_info gc_10_3_6_cache_info[] = { · 3 unmodified lines | ||
| 846 | 926 | /* Scalar L1 Instruction Cache per SQC */ |
| 847 | 927 | .cache_size = 32, |
| 848 | 928 | .cache_level = 1, |
| 929 | + .cache_line_size = 64, | |
| 849 | 930 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 850 | 931 | CRAT_CACHE_FLAGS_INST_CACHE | |
| 851 | 932 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -855,6 +936,7 @@ static struct kfd_gpu_cache_info gc_10_3_6_cache_info[] = { · 3 unmodified lines | ||
| 855 | 936 | /* Scalar L1 Data Cache per SQC */ |
| 856 | 937 | .cache_size = 16, |
| 857 | 938 | .cache_level = 1, |
| 939 | + .cache_line_size = 64, | |
| 858 | 940 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 859 | 941 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 860 | 942 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -864,6 +946,7 @@ static struct kfd_gpu_cache_info gc_10_3_6_cache_info[] = { · 3 unmodified lines | ||
| 864 | 946 | /* GL1 Data Cache per SA */ |
| 865 | 947 | .cache_size = 128, |
| 866 | 948 | .cache_level = 1, |
| 949 | + .cache_line_size = 128, | |
| 867 | 950 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 868 | 951 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 869 | 952 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -873,6 +956,7 @@ static struct kfd_gpu_cache_info gc_10_3_6_cache_info[] = { · 3 unmodified lines | ||
| 873 | 956 | /* L2 Data Cache per GPU (Total Tex Cache) */ |
| 874 | 957 | .cache_size = 256, |
| 875 | 958 | .cache_level = 2, |
| 959 | + .cache_line_size = 128, | |
| 876 | 960 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 877 | 961 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 878 | 962 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -885,6 +969,7 @@ static struct kfd_gpu_cache_info dummy_cache_info[] = { · 6 unmodified lines | ||
| 885 | 969 | /* TCP L1 Cache per CU */ |
| 886 | 970 | .cache_size = 16, |
| 887 | 971 | .cache_level = 1, |
| 972 | + .cache_line_size = 64, | |
| 888 | 973 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 889 | 974 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 890 | 975 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -894,6 +979,7 @@ static struct kfd_gpu_cache_info dummy_cache_info[] = { · 3 unmodified lines | ||
| 894 | 979 | /* Scalar L1 Instruction Cache per SQC */ |
| 895 | 980 | .cache_size = 32, |
| 896 | 981 | .cache_level = 1, |
| 982 | + .cache_line_size = 64, | |
| 897 | 983 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 898 | 984 | CRAT_CACHE_FLAGS_INST_CACHE | |
| 899 | 985 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -903,6 +989,7 @@ static struct kfd_gpu_cache_info dummy_cache_info[] = { · 3 unmodified lines | ||
| 903 | 989 | /* Scalar L1 Data Cache per SQC */ |
| 904 | 990 | .cache_size = 16, |
| 905 | 991 | .cache_level = 1, |
| 992 | + .cache_line_size = 64, | |
| 906 | 993 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 907 | 994 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 908 | 995 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -912,6 +999,7 @@ static struct kfd_gpu_cache_info dummy_cache_info[] = { · 3 unmodified lines | ||
| 912 | 999 | /* GL1 Data Cache per SA */ |
| 913 | 1000 | .cache_size = 128, |
| 914 | 1001 | .cache_level = 1, |
| 1002 | + .cache_line_size = 64, | |
| 915 | 1003 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 916 | 1004 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 917 | 1005 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -921,6 +1009,7 @@ static struct kfd_gpu_cache_info dummy_cache_info[] = { · 3 unmodified lines | ||
| 921 | 1009 | /* L2 Data Cache per GPU (Total Tex Cache) */ |
| 922 | 1010 | .cache_size = 2048, |
| 923 | 1011 | .cache_level = 2, |
| 1012 | + .cache_line_size = 64, | |
| 924 | 1013 | .flags = (CRAT_CACHE_FLAGS_ENABLED | |
| 925 | 1014 | CRAT_CACHE_FLAGS_DATA_CACHE | |
| 926 | 1015 | CRAT_CACHE_FLAGS_SIMD_CACHE), |
| @@ -303,6 +303,7 @@ struct kfd_node; · 302 unmodified lines | ||
| 303 | 303 | struct kfd_gpu_cache_info { |
| 304 | 304 | uint32_t cache_size; |
| 305 | 305 | uint32_t cache_level; |
| 306 | + uint32_t cache_line_size; | |
| 306 | 307 | uint32_t flags; |
| 307 | 308 | /* Indicates how many Compute Units share this cache |
| 308 | 309 | * within a SA. Value = 1 indicates the cache is not shared |
| @@ -1018,12 +1018,14 @@ int kfd_dbg_trap_device_snapshot(struct kfd_process *target, · 1017 unmodified lines | ||
| 1018 | 1018 | uint32_t *entry_size) |
| 1019 | 1019 | { |
| 1020 | 1020 | struct kfd_dbg_device_info_entry device_info; |
| 1021 | − uint32_t tmp_entry_size = *entry_size, tmp_num_devices; | |
| 1021 | + uint32_t tmp_entry_size, tmp_num_devices; | |
| 1022 | 1022 | int i, r = 0; |
| 1023 | 1023 | |
| 1024 | 1024 | if (!(target && user_info && number_of_device_infos && entry_size)) |
| 1025 | 1025 | return -EINVAL; |
| 1026 | 1026 | |
| 1027 | + tmp_entry_size = *entry_size; | |
| 1028 | + | |
| 1027 | 1029 | tmp_num_devices = min_t(size_t, *number_of_device_infos, target->n_pdds); |
| 1028 | 1030 | *number_of_device_infos = target->n_pdds; |
| 1029 | 1031 | *entry_size = min_t(size_t, *entry_size, sizeof(device_info)); |
| @@ -1285,8 +1285,10 @@ void kfd_signal_poison_consumed_event(struct kfd_node *dev, u32 pasid) · 1284 unmodified lines | ||
| 1285 | 1285 | uint32_t id = KFD_FIRST_NONSIGNAL_EVENT_ID; |
| 1286 | 1286 | int user_gpu_id; |
| 1287 | 1287 | |
| 1288 | − if (!p) | |
| 1288 | + if (!p) { | |
| 1289 | + dev_warn(dev->adev->dev, "Not find process with pasid:%d\n", pasid); | |
| 1289 | 1290 | return; /* Presumably process exited. */ |
| 1291 | + } | |
| 1290 | 1292 | |
| 1291 | 1293 | user_gpu_id = kfd_process_get_user_gpu_id(p, dev->id); |
| 1292 | 1294 | if (unlikely(user_gpu_id == -EINVAL)) { |
| @@ -1322,6 +1324,8 @@ void kfd_signal_poison_consumed_event(struct kfd_node *dev, u32 pasid) · 29 unmodified lines | ||
| 1322 | 1324 | } |
| 1323 | 1325 | } |
| 1324 | 1326 | |
| 1327 | + dev_warn(dev->adev->dev, "Send SIGBUS to process %s(pasid:%d)\n", | |
| 1328 | + p->lead_thread->comm, pasid); | |
| 1325 | 1329 | rcu_read_unlock(); |
| 1326 | 1330 | |
| 1327 | 1331 | /* user application will handle SIGBUS signal */ |
| @@ -132,6 +132,7 @@ enum SQ_INTERRUPT_ERROR_TYPE { · 131 unmodified lines | ||
| 132 | 132 | static void event_interrupt_poison_consumption(struct kfd_node *dev, |
| 133 | 133 | uint16_t pasid, uint16_t client_id) |
| 134 | 134 | { |
| 135 | + enum amdgpu_ras_block block = 0; | |
| 135 | 136 | int old_poison, ret = -EINVAL; |
| 136 | 137 | struct kfd_process *p = kfd_lookup_process_by_pasid(pasid); |
| 137 | 138 | |
| @@ -151,12 +152,14 @@ static void event_interrupt_poison_consumption(struct kfd_node *dev, · 13 unmodified lines | ||
| 151 | 152 | case SOC15_IH_CLIENTID_SE3SH: |
| 152 | 153 | case SOC15_IH_CLIENTID_UTCL2: |
| 153 | 154 | ret = kfd_dqm_evict_pasid(dev->dqm, pasid); |
| 155 | + block = AMDGPU_RAS_BLOCK__GFX; | |
| 154 | 156 | break; |
| 155 | 157 | case SOC15_IH_CLIENTID_SDMA0: |
| 156 | 158 | case SOC15_IH_CLIENTID_SDMA1: |
| 157 | 159 | case SOC15_IH_CLIENTID_SDMA2: |
| 158 | 160 | case SOC15_IH_CLIENTID_SDMA3: |
| 159 | 161 | case SOC15_IH_CLIENTID_SDMA4: |
| 162 | + block = AMDGPU_RAS_BLOCK__SDMA; | |
| 160 | 163 | break; |
| 161 | 164 | default: |
| 162 | 165 | break; |
| @@ -171,12 +174,12 @@ static void event_interrupt_poison_consumption(struct kfd_node *dev, · 8 unmodified lines | ||
| 171 | 174 | dev_warn(dev->adev->dev, |
| 172 | 175 | "RAS poison consumption, unmap queue flow succeeded: client id %d\n", |
| 173 | 176 | client_id); |
| 174 | − amdgpu_amdkfd_ras_poison_consumption_handler(dev->adev, false); | |
| 177 | + amdgpu_amdkfd_ras_poison_consumption_handler(dev->adev, block, false); | |
| 175 | 178 | } else { |
| 176 | 179 | dev_warn(dev->adev->dev, |
| 177 | 180 | "RAS poison consumption, fall back to gpu reset flow: client id %d\n", |
| 178 | 181 | client_id); |
| 179 | − amdgpu_amdkfd_ras_poison_consumption_handler(dev->adev, true); | |
| 182 | + amdgpu_amdkfd_ras_poison_consumption_handler(dev->adev, block, true); | |
| 180 | 183 | } |
| 181 | 184 | } |
| 182 | 185 | |
| @@ -191,6 +191,7 @@ static void print_sq_intr_info_error(uint32_t context_id0, uint32_t context_id1) · 190 unmodified lines | ||
| 191 | 191 | static void event_interrupt_poison_consumption_v11(struct kfd_node *dev, |
| 192 | 192 | uint16_t pasid, uint16_t source_id) |
| 193 | 193 | { |
| 194 | + enum amdgpu_ras_block block = 0; | |
| 194 | 195 | int ret = -EINVAL; |
| 195 | 196 | struct kfd_process *p = kfd_lookup_process_by_pasid(pasid); |
| 196 | 197 | |
| @@ -210,9 +211,11 @@ static void event_interrupt_poison_consumption_v11(struct kfd_node *dev, · 13 unmodified lines | ||
| 210 | 211 | case SOC15_INTSRC_SQ_INTERRUPT_MSG: |
| 211 | 212 | if (dev->dqm->ops.reset_queues) |
| 212 | 213 | ret = dev->dqm->ops.reset_queues(dev->dqm, pasid); |
| 214 | + block = AMDGPU_RAS_BLOCK__GFX; | |
| 213 | 215 | break; |
| 214 | 216 | case SOC21_INTSRC_SDMA_ECC: |
| 215 | 217 | default: |
| 218 | + block = AMDGPU_RAS_BLOCK__GFX; | |
| 216 | 219 | break; |
| 217 | 220 | } |
| 218 | 221 | |
| @@ -221,9 +224,9 @@ static void event_interrupt_poison_consumption_v11(struct kfd_node *dev, · 2 unmodified lines | ||
| 221 | 224 | /* resetting queue passes, do page retirement without gpu reset |
| 222 | 225 | resetting queue fails, fallback to gpu reset solution */ |
| 223 | 226 | if (!ret) |
| 224 | − amdgpu_amdkfd_ras_poison_consumption_handler(dev->adev, false); | |
| 227 | + amdgpu_amdkfd_ras_poison_consumption_handler(dev->adev, block, false); | |
| 225 | 228 | else |
| 226 | − amdgpu_amdkfd_ras_poison_consumption_handler(dev->adev, true); | |
| 229 | + amdgpu_amdkfd_ras_poison_consumption_handler(dev->adev, block, true); | |
| 227 | 230 | } |
| 228 | 231 | |
| 229 | 232 | static bool event_interrupt_isr_v11(struct kfd_node *dev, |
| @@ -143,6 +143,7 @@ enum SQ_INTERRUPT_ERROR_TYPE { · 142 unmodified lines | ||
| 143 | 143 | static void event_interrupt_poison_consumption_v9(struct kfd_node *dev, |
| 144 | 144 | uint16_t pasid, uint16_t client_id) |
| 145 | 145 | { |
| 146 | + enum amdgpu_ras_block block = 0; | |
| 146 | 147 | int old_poison, ret = -EINVAL; |
| 147 | 148 | struct kfd_process *p = kfd_lookup_process_by_pasid(pasid); |
| 148 | 149 | |
| @@ -162,12 +163,14 @@ static void event_interrupt_poison_consumption_v9(struct kfd_node *dev, · 13 unmodified lines | ||
| 162 | 163 | case SOC15_IH_CLIENTID_SE3SH: |
| 163 | 164 | case SOC15_IH_CLIENTID_UTCL2: |
| 164 | 165 | ret = kfd_dqm_evict_pasid(dev->dqm, pasid); |
| 166 | + block = AMDGPU_RAS_BLOCK__GFX; | |
| 165 | 167 | break; |
| 166 | 168 | case SOC15_IH_CLIENTID_SDMA0: |
| 167 | 169 | case SOC15_IH_CLIENTID_SDMA1: |
| 168 | 170 | case SOC15_IH_CLIENTID_SDMA2: |
| 169 | 171 | case SOC15_IH_CLIENTID_SDMA3: |
| 170 | 172 | case SOC15_IH_CLIENTID_SDMA4: |
| 173 | + block = AMDGPU_RAS_BLOCK__SDMA; | |
| 171 | 174 | break; |
| 172 | 175 | default: |
| 173 | 176 | break; |
| @@ -182,12 +185,12 @@ static void event_interrupt_poison_consumption_v9(struct kfd_node *dev, · 8 unmodified lines | ||
| 182 | 185 | dev_warn(dev->adev->dev, |
| 183 | 186 | "RAS poison consumption, unmap queue flow succeeded: client id %d\n", |
| 184 | 187 | client_id); |
| 185 | − amdgpu_amdkfd_ras_poison_consumption_handler(dev->adev, false); | |
| 188 | + amdgpu_amdkfd_ras_poison_consumption_handler(dev->adev, block, false); | |
| 186 | 189 | } else { |
| 187 | 190 | dev_warn(dev->adev->dev, |
| 188 | 191 | "RAS poison consumption, fall back to gpu reset flow: client id %d\n", |
| 189 | 192 | client_id); |
| 190 | − amdgpu_amdkfd_ras_poison_consumption_handler(dev->adev, true); | |
| 193 | + amdgpu_amdkfd_ras_poison_consumption_handler(dev->adev, block, true); | |
| 191 | 194 | } |
| 192 | 195 | } |
| 193 | 196 | |
| @@ -574,7 +574,7 @@ svm_migrate_copy_to_ram(struct amdgpu_device *adev, struct svm_range *prange, · 573 unmodified lines | ||
| 574 | 574 | pr_debug("svms 0x%p [0x%lx 0x%lx]\n", prange->svms, prange->start, |
| 575 | 575 | prange->last); |
| 576 | 576 | |
| 577 | − addr = prange->start << PAGE_SHIFT; | |
| 577 | + addr = migrate->start; | |
| 578 | 578 | |
| 579 | 579 | src = (uint64_t *)(scratch + npages); |
| 580 | 580 | dst = scratch; |
| @@ -170,6 +170,7 @@ static void update_mqd(struct mqd_manager *mm, void *mqd, · 169 unmodified lines | ||
| 170 | 170 | m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; |
| 171 | 171 | m->cp_hqd_pq_control |= |
| 172 | 172 | ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1; |
| 173 | + m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK; | |
| 173 | 174 | pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); |
| 174 | 175 | |
| 175 | 176 | m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); |
| @@ -224,6 +224,7 @@ static void update_mqd(struct mqd_manager *mm, void *mqd, · 223 unmodified lines | ||
| 224 | 224 | m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; |
| 225 | 225 | m->cp_hqd_pq_control |= |
| 226 | 226 | ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1; |
| 227 | + m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK; | |
| 227 | 228 | pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); |
| 228 | 229 | |
| 229 | 230 | m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); |
| @@ -1488,10 +1488,15 @@ void kfd_dec_compute_active(struct kfd_node *dev); · 1487 unmodified lines | ||
| 1488 | 1488 | |
| 1489 | 1489 | /* Cgroup Support */ |
| 1490 | 1490 | /* Check with device cgroup if @kfd device is accessible */ |
| 1491 | −static inline int kfd_devcgroup_check_permission(struct kfd_node *kfd) | |
| 1491 | +static inline int kfd_devcgroup_check_permission(struct kfd_node *node) | |
| 1492 | 1492 | { |
| 1493 | 1493 | #if defined(CONFIG_CGROUP_DEVICE) || defined(CONFIG_CGROUP_BPF) |
| 1494 | − struct drm_device *ddev = adev_to_drm(kfd->adev); | |
| 1494 | + struct drm_device *ddev; | |
| 1495 | + | |
| 1496 | + if (node->xcp) | |
| 1497 | + ddev = node->xcp->ddev; | |
| 1498 | + else | |
| 1499 | + ddev = adev_to_drm(node->adev); | |
| 1495 | 1500 | |
| 1496 | 1501 | return devcgroup_check_permission(DEVCG_DEV_CHAR, DRM_MAJOR, |
| 1497 | 1502 | ddev->render->index, |
| @@ -1515,9 +1515,9 @@ static int svm_range_reserve_bos(struct svm_validate_context *ctx, bool intr) · 1514 unmodified lines | ||
| 1515 | 1515 | goto unreserve_out; |
| 1516 | 1516 | } |
| 1517 | 1517 | |
| 1518 | − r = amdgpu_vm_validate_pt_bos(pdd->dev->adev, | |
| 1519 | − drm_priv_to_vm(pdd->drm_priv), | |
| 1520 | − svm_range_bo_validate, NULL); | |
| 1518 | + r = amdgpu_vm_validate(pdd->dev->adev, | |
| 1519 | + drm_priv_to_vm(pdd->drm_priv), NULL, | |
| 1520 | + svm_range_bo_validate, NULL); | |
| 1521 | 1521 | if (r) { |
| 1522 | 1522 | pr_debug("failed %d validate pt bos\n", r); |
| 1523 | 1523 | goto unreserve_out; |
| @@ -1641,7 +1641,9 @@ static int svm_range_validate_and_map(struct mm_struct *mm, · 117 unmodified lines | ||
| 1641 | 1641 | goto free_ctx; |
| 1642 | 1642 | } |
| 1643 | 1643 | |
| 1644 | − svm_range_reserve_bos(ctx, intr); | |
| 1644 | + r = svm_range_reserve_bos(ctx, intr); | |
| 1645 | + if (r) | |
| 1646 | + goto free_ctx; | |
| 1645 | 1647 | |
| 1646 | 1648 | p = container_of(prange->svms, struct kfd_process, svms); |
| 1647 | 1649 | owner = kfd_svm_page_owner(p, find_first_bit(ctx->bitmap, |
| @@ -1564,6 +1564,7 @@ static int fill_in_l1_pcache(struct kfd_cache_properties **props_ext, · 1563 unmodified lines | ||
| 1564 | 1564 | pcache->processor_id_low = cu_processor_id + (first_active_cu - 1); |
| 1565 | 1565 | pcache->cache_level = pcache_info[cache_type].cache_level; |
| 1566 | 1566 | pcache->cache_size = pcache_info[cache_type].cache_size; |
| 1567 | + pcache->cacheline_size = pcache_info[cache_type].cache_line_size; | |
| 1567 | 1568 | |
| 1568 | 1569 | if (pcache_info[cache_type].flags & CRAT_CACHE_FLAGS_DATA_CACHE) |
| 1569 | 1570 | pcache->cache_type |= HSA_CACHE_TYPE_DATA; |
| @@ -1632,6 +1633,7 @@ static int fill_in_l2_l3_pcache(struct kfd_cache_properties **props_ext, · 62 unmodified lines | ||
| 1632 | 1633 | pcache->processor_id_low = cu_processor_id |
| 1633 | 1634 | + (first_active_cu - 1); |
| 1634 | 1635 | pcache->cache_level = pcache_info[cache_type].cache_level; |
| 1636 | + pcache->cacheline_size = pcache_info[cache_type].cache_line_size; | |
| 1635 | 1637 | |
| 1636 | 1638 | if (KFD_GC_VERSION(knode) == IP_VERSION(9, 4, 3)) |
| 1637 | 1639 | mode = adev->gmc.gmc_funcs->query_mem_partition_mode(adev); |
| @@ -1705,6 +1707,7 @@ static void kfd_fill_cache_non_crat_info(struct kfd_topology_device *dev, struct · 67 unmodified lines | ||
| 1705 | 1707 | |
| 1706 | 1708 | gpu_processor_id = dev->node_props.simd_id_base; |
| 1707 | 1709 | |
| 1710 | + memset(cache_info, 0, sizeof(cache_info)); | |
| 1708 | 1711 | pcache_info = cache_info; |
| 1709 | 1712 | num_of_cache_types = kfd_get_gpu_cache_info(kdev, &pcache_info); |
| 1710 | 1713 | if (!num_of_cache_types) { |
| @@ -1,110 +0,0 @@ | ||
| 1 | −=============================================================================== | |
| 2 | −TODOs | |
| 3 | −=============================================================================== | |
| 4 | − | |
| 5 | −1. Base this on drm-next - WIP | |
| 6 | − | |
| 7 | − | |
| 8 | −2. Cleanup commit history | |
| 9 | − | |
| 10 | − | |
| 11 | −3. WIP - Drop page flip helper and use DRM's version | |
| 12 | − | |
| 13 | − | |
| 14 | −4. DONE - Flatten all DC objects | |
| 15 | − * dc_stream/core_stream/stream should just be dc_stream | |
| 16 | − * Same for other DC objects | |
| 17 | − | |
| 18 | − "Is there any major reason to keep all those abstractions? | |
| 19 | − | |
| 20 | − Could you collapse everything into struct dc_stream? | |
| 21 | − | |
| 22 | − I haven't looked recently but I didn't get the impression there was a | |
| 23 | − lot of design around what was public/protected, more whatever needed | |
| 24 | − to be used by someone else was in public." | |
| 25 | − ~ Dave Airlie | |
| 26 | − | |
| 27 | − | |
| 28 | −5. DONE - Rename DC objects to align more with DRM | |
| 29 | − * dc_surface -> dc_plane_state | |
| 30 | − * dc_stream -> dc_stream_state | |
| 31 | − | |
| 32 | − | |
| 33 | −6. DONE - Per-plane and per-stream validation | |
| 34 | − | |
| 35 | − | |
| 36 | −7. WIP - Per-plane and per-stream commit | |
| 37 | − | |
| 38 | − | |
| 39 | −8. WIP - Split pipe_ctx into plane and stream resource structs | |
| 40 | − | |
| 41 | − | |
| 42 | −9. Attach plane and stream reources to state object instead of validate_context | |
| 43 | − | |
| 44 | − | |
| 45 | −10. Remove dc_edid_caps and drm_helpers_parse_edid_caps | |
| 46 | − * Use drm_display_info instead | |
| 47 | − * Remove DC's edid quirks and rely on DRM's quirks (add quirks if needed) | |
| 48 | − | |
| 49 | − "Making sure you use the sink-specific helper libraries and kernel | |
| 50 | − subsystems, since there's really no good reason to have 2nd | |
| 51 | − implementation of those in the kernel. Looks likes that's done for mst | |
| 52 | − and edid parsing. There's still a bit a midlayer feeling to the edid | |
| 53 | − parsing side (e.g. dc_edid_caps and dm_helpers_parse_edid_caps, I | |
| 54 | − think it'd be much better if you convert that over to reading stuff | |
| 55 | − from drm_display_info and if needed, push stuff into the core). Also, | |
| 56 | − I can't come up with a good reason why DC needs all this (except to | |
| 57 | − reimplement half of our edid quirk table, which really isn't a good | |
| 58 | − idea). Might be good if you put this onto the list of things to fix | |
| 59 | − long-term, but imo not a blocker. Definitely make sure new stuff | |
| 60 | − doesn't slip in (i.e. if you start adding edid quirks to DC instead of | |
| 61 | − the drm core, refactoring to use the core edid stuff was pointless)." | |
| 62 | − ~ Daniel Vetter | |
| 63 | − | |
| 64 | − | |
| 65 | −11. Remove dc/i2caux. This folder can be somewhat misleading. It's basically an | |
| 66 | −overy complicated HW programming function for sendind and receiving i2c/aux | |
| 67 | −commands. We can greatly simplify that and move it into dc/dceXYZ like other | |
| 68 | −HW blocks. | |
| 69 | − | |
| 70 | −12. drm_modeset_lock in MST should no longer be needed in recent kernels | |
| 71 | − * Adopt appropriate locking scheme | |
| 72 | − | |
| 73 | −13. get_modes and best_encoder callbacks look a bit funny. Can probably rip out | |
| 74 | −a few indirections, and consider removing entirely and using the | |
| 75 | −drm_atomic_helper_best_encoder default behaviour. | |
| 76 | − | |
| 77 | −14. core/dc_debug.c, consider switching to the atomic state debug helpers and | |
| 78 | −moving all your driver state printing into the various atomic_print_state | |
| 79 | −callbacks. There's also plans to expose this stuff in a standard way across all | |
| 80 | −drivers, to make debugging userspace compositors easier across different hw. | |
| 81 | − | |
| 82 | −15. Move DP/HDMI dual mode adaptors to drm_dp_dual_mode_helper.c. See | |
| 83 | −dal_ddc_service_i2c_query_dp_dual_mode_adaptor. | |
| 84 | − | |
| 85 | −16. Move to core SCDC helpers (I think those are new since initial DC review). | |
| 86 | − | |
| 87 | −17. There's still a pretty massive layer cake around dp aux and DPCD handling, | |
| 88 | −with like 3 levels of abstraction and using your own structures instead of the | |
| 89 | −stuff in drm_dp_helper.h. drm_dp_helper.h isn't really great and already has 2 | |
| 90 | −incompatible styles, just means more reasons not to add a third (or well third | |
| 91 | −one gets to do the cleanup refactor). | |
| 92 | − | |
| 93 | −18. There's a pile of sink handling code, both for DP and HDMI where I didn't | |
| 94 | −immediately recognize the standard. I think long term it'd be best for the drm | |
| 95 | −subsystem if we try to move as much of that into helpers/core as possible, and | |
| 96 | −share it with drivers. But that's a very long term goal, and by far not just an | |
| 97 | −issue with DC - other drivers, especially around DP sink handling, are equally | |
| 98 | −guilty. | |
| 99 | − | |
| 100 | −19. DONE - The DC logger is still a rather sore thing, but I know that the | |
| 101 | −DRM_DEBUG stuff just isn't up to the challenges either. We need to figure out | |
| 102 | −something that integrates better with DRM and linux debug printing, while not | |
| 103 | −being useless with filtering output. dynamic debug printing might be an option. | |
| 104 | − | |
| 105 | −20. Use kernel i2c device to program HDMI retimer. Some boards have an HDMI | |
| 106 | −retimer that we need to program to pass PHY compliance. Currently that's | |
| 107 | −bypassing the i2c device and goes directly to HW. This should be changed. | |
| 108 | − | |
| 109 | −21. Remove vector.c from dc/basics. It's used in DDC code which can probably | |
| 110 | −be simplified enough to no longer need a vector implementation. | |
| @@ -67,6 +67,7 @@ · 66 unmodified lines | ||
| 67 | 67 | #include "amdgpu_dm_debugfs.h" |
| 68 | 68 | #endif |
| 69 | 69 | #include "amdgpu_dm_psr.h" |
| 70 | +#include "amdgpu_dm_replay.h" | |
| 70 | 71 | |
| 71 | 72 | #include "ivsrcid/ivsrcid_vislands30.h" |
| 72 | 73 | |
| @@ -272,6 +273,7 @@ static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, · 199 unmodified lines | ||
| 272 | 273 | { |
| 273 | 274 | u32 v_blank_start, v_blank_end, h_position, v_position; |
| 274 | 275 | struct amdgpu_crtc *acrtc = NULL; |
| 276 | + struct dc *dc = adev->dm.dc; | |
| 275 | 277 | |
| 276 | 278 | if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) |
| 277 | 279 | return -EINVAL; |
| @@ -284,6 +286,9 @@ static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, · 6 unmodified lines | ||
| 284 | 286 | return 0; |
| 285 | 287 | } |
| 286 | 288 | |
| 289 | + if (dc && dc->caps.ips_support && dc->idle_optimizations_allowed) | |
| 290 | + dc_allow_idle_optimizations(dc, false); | |
| 291 | + | |
| 287 | 292 | /* |
| 288 | 293 | * TODO rework base driver to use values directly. |
| 289 | 294 | * for now parse it back into reg-format |
| @@ -1715,7 +1720,10 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) · 1425 unmodified lines | ||
| 1715 | 1720 | init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0]; |
| 1716 | 1721 | init_data.clk_reg_offsets = adev->reg_offset[CLK_HWIP][0]; |
| 1717 | 1722 | |
| 1718 | − init_data.flags.disable_ips = DMUB_IPS_DISABLE_ALL; | |
| 1723 | + if (amdgpu_dc_debug_mask & DC_DISABLE_IPS) | |
| 1724 | + init_data.flags.disable_ips = DMUB_IPS_DISABLE_ALL; | |
| 1725 | + | |
| 1726 | + init_data.flags.disable_ips_in_vpb = 1; | |
| 1719 | 1727 | |
| 1720 | 1728 | /* Enable DWB for tested platforms only */ |
| 1721 | 1729 | if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0)) |
| @@ -2114,6 +2122,16 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev) · 392 unmodified lines | ||
| 2114 | 2122 | const struct dmcub_firmware_header_v1_0 *hdr; |
| 2115 | 2123 | enum dmub_asic dmub_asic; |
| 2116 | 2124 | enum dmub_status status; |
| 2125 | + static enum dmub_window_memory_type window_memory_type[DMUB_WINDOW_TOTAL] = { | |
| 2126 | + DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_0_INST_CONST | |
| 2127 | + DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_1_STACK | |
| 2128 | + DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_2_BSS_DATA | |
| 2129 | + DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_3_VBIOS | |
| 2130 | + DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_4_MAILBOX | |
| 2131 | + DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_5_TRACEBUFF | |
| 2132 | + DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_6_FW_STATE | |
| 2133 | + DMUB_WINDOW_MEMORY_TYPE_FB //DMUB_WINDOW_7_SCRATCH_MEM | |
| 2134 | + }; | |
| 2117 | 2135 | int r; |
| 2118 | 2136 | |
| 2119 | 2137 | switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { |
| @@ -2211,7 +2229,7 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev) · 91 unmodified lines | ||
| 2211 | 2229 | adev->dm.dmub_fw->data + |
| 2212 | 2230 | le32_to_cpu(hdr->header.ucode_array_offset_bytes) + |
| 2213 | 2231 | PSP_HEADER_BYTES; |
| 2214 | − region_params.is_mailbox_in_inbox = false; | |
| 2232 | + region_params.window_memory_type = window_memory_type; | |
| 2215 | 2233 | |
| 2216 | 2234 | status = dmub_srv_calc_region_info(dmub_srv, ®ion_params, |
| 2217 | 2235 | ®ion_info); |
| @@ -2239,6 +2257,7 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev) · 21 unmodified lines | ||
| 2239 | 2257 | memory_params.cpu_fb_addr = adev->dm.dmub_bo_cpu_addr; |
| 2240 | 2258 | memory_params.gpu_fb_addr = adev->dm.dmub_bo_gpu_addr; |
| 2241 | 2259 | memory_params.region_info = ®ion_info; |
| 2260 | + memory_params.window_memory_type = window_memory_type; | |
| 2242 | 2261 | |
| 2243 | 2262 | adev->dm.dmub_fb_info = |
| 2244 | 2263 | kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL); |
| @@ -4392,6 +4411,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) · 2147 unmodified lines | ||
| 4392 | 4411 | enum dc_connection_type new_connection_type = dc_connection_none; |
| 4393 | 4412 | const struct dc_plane_cap *plane; |
| 4394 | 4413 | bool psr_feature_enabled = false; |
| 4414 | + bool replay_feature_enabled = false; | |
| 4395 | 4415 | int max_overlay = dm->dc->caps.max_slave_planes; |
| 4396 | 4416 | |
| 4397 | 4417 | dm->display_indexes_num = dm->dc->caps.max_streams; |
| @@ -4503,6 +4523,23 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) · 105 unmodified lines | ||
| 4503 | 4523 | } |
| 4504 | 4524 | } |
| 4505 | 4525 | |
| 4526 | + /* Determine whether to enable Replay support by default. */ | |
| 4527 | + if (!(amdgpu_dc_debug_mask & DC_DISABLE_REPLAY)) { | |
| 4528 | + switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { | |
| 4529 | + case IP_VERSION(3, 1, 4): | |
| 4530 | + case IP_VERSION(3, 1, 5): | |
| 4531 | + case IP_VERSION(3, 1, 6): | |
| 4532 | + case IP_VERSION(3, 2, 0): | |
| 4533 | + case IP_VERSION(3, 2, 1): | |
| 4534 | + case IP_VERSION(3, 5, 0): | |
| 4535 | + replay_feature_enabled = true; | |
| 4536 | + break; | |
| 4537 | + default: | |
| 4538 | + replay_feature_enabled = amdgpu_dc_feature_mask & DC_REPLAY_MASK; | |
| 4539 | + break; | |
| 4540 | + } | |
| 4541 | + } | |
| 4542 | + | |
| 4506 | 4543 | /* loops over all connectors on the board */ |
| 4507 | 4544 | for (i = 0; i < link_cnt; i++) { |
| 4508 | 4545 | struct dc_link *link = NULL; |
| @@ -4571,6 +4608,11 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) · 62 unmodified lines | ||
| 4571 | 4608 | amdgpu_dm_update_connector_after_detect(aconnector); |
| 4572 | 4609 | setup_backlight_device(dm, aconnector); |
| 4573 | 4610 | |
| 4611 | + /* Disable PSR if Replay can be enabled */ | |
| 4612 | + if (replay_feature_enabled) | |
| 4613 | + if (amdgpu_dm_set_replay_caps(link, aconnector)) | |
| 4614 | + psr_feature_enabled = false; | |
| 4615 | + | |
| 4574 | 4616 | if (psr_feature_enabled) |
| 4575 | 4617 | amdgpu_dm_set_psr_caps(link); |
| 4576 | 4618 | |
| @@ -6395,10 +6437,81 @@ int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, · 1818 unmodified lines | ||
| 6395 | 6437 | return ret; |
| 6396 | 6438 | } |
| 6397 | 6439 | |
| 6440 | +/** | |
| 6441 | + * DOC: panel power savings | |
| 6442 | + * | |
| 6443 | + * The display manager allows you to set your desired **panel power savings** | |
| 6444 | + * level (between 0-4, with 0 representing off), e.g. using the following:: | |
| 6445 | + * | |
| 6446 | + * # echo 3 > /sys/class/drm/card0-eDP-1/amdgpu/panel_power_savings | |
| 6447 | + * | |
| 6448 | + * Modifying this value can have implications on color accuracy, so tread | |
| 6449 | + * carefully. | |
| 6450 | + */ | |
| 6451 | + | |
| 6452 | +static ssize_t panel_power_savings_show(struct device *device, | |
| 6453 | + struct device_attribute *attr, | |
| 6454 | + char *buf) | |
| 6455 | +{ | |
| 6456 | + struct drm_connector *connector = dev_get_drvdata(device); | |
| 6457 | + struct drm_device *dev = connector->dev; | |
| 6458 | + u8 val; | |
| 6459 | + | |
| 6460 | + drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); | |
| 6461 | + val = to_dm_connector_state(connector->state)->abm_level == | |
| 6462 | + ABM_LEVEL_IMMEDIATE_DISABLE ? 0 : | |
| 6463 | + to_dm_connector_state(connector->state)->abm_level; | |
| 6464 | + drm_modeset_unlock(&dev->mode_config.connection_mutex); | |
| 6465 | + | |
| 6466 | + return sysfs_emit(buf, "%u\n", val); | |
| 6467 | +} | |
| 6468 | + | |
| 6469 | +static ssize_t panel_power_savings_store(struct device *device, | |
| 6470 | + struct device_attribute *attr, | |
| 6471 | + const char *buf, size_t count) | |
| 6472 | +{ | |
| 6473 | + struct drm_connector *connector = dev_get_drvdata(device); | |
| 6474 | + struct drm_device *dev = connector->dev; | |
| 6475 | + long val; | |
| 6476 | + int ret; | |
| 6477 | + | |
| 6478 | + ret = kstrtol(buf, 0, &val); | |
| 6479 | + | |
| 6480 | + if (ret) | |
| 6481 | + return ret; | |
| 6482 | + | |
| 6483 | + if (val < 0 || val > 4) | |
| 6484 | + return -EINVAL; | |
| 6485 | + | |
| 6486 | + drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); | |
| 6487 | + to_dm_connector_state(connector->state)->abm_level = val ?: | |
| 6488 | + ABM_LEVEL_IMMEDIATE_DISABLE; | |
| 6489 | + drm_modeset_unlock(&dev->mode_config.connection_mutex); | |
| 6490 | + | |
| 6491 | + drm_kms_helper_hotplug_event(dev); | |
| 6492 | + | |
| 6493 | + return count; | |
| 6494 | +} | |
| 6495 | + | |
| 6496 | +static DEVICE_ATTR_RW(panel_power_savings); | |
| 6497 | + | |
| 6498 | +static struct attribute *amdgpu_attrs[] = { | |
| 6499 | + &dev_attr_panel_power_savings.attr, | |
| 6500 | + NULL | |
| 6501 | +}; | |
| 6502 | + | |
| 6503 | +static const struct attribute_group amdgpu_group = { | |
| 6504 | + .name = "amdgpu", | |
| 6505 | + .attrs = amdgpu_attrs | |
| 6506 | +}; | |
| 6507 | + | |
| 6398 | 6508 | static void amdgpu_dm_connector_unregister(struct drm_connector *connector) |
| 6399 | 6509 | { |
| 6400 | 6510 | struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector); |
| 6401 | 6511 | |
| 6512 | + if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
| 6513 | + sysfs_remove_group(&connector->kdev->kobj, &amdgpu_group); | |
| 6514 | + | |
| 6402 | 6515 | drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux); |
| 6403 | 6516 | } |
| 6404 | 6517 | |
| @@ -6500,6 +6613,13 @@ amdgpu_dm_connector_late_register(struct drm_connector *connector) · 95 unmodified lines | ||
| 6500 | 6613 | to_amdgpu_dm_connector(connector); |
| 6501 | 6614 | int r; |
| 6502 | 6615 | |
| 6616 | + if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { | |
| 6617 | + r = sysfs_create_group(&connector->kdev->kobj, | |
| 6618 | + &amdgpu_group); | |
| 6619 | + if (r) | |
| 6620 | + return r; | |
| 6621 | + } | |
| 6622 | + | |
| 6503 | 6623 | amdgpu_dm_register_backlight_device(amdgpu_dm_connector); |
| 6504 | 6624 | |
| 6505 | 6625 | if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || |
| @@ -8519,10 +8639,22 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, · 2013 unmodified lines | ||
| 8519 | 8639 | dm_update_pflip_irq_state(drm_to_adev(dev), |
| 8520 | 8640 | acrtc_attach); |
| 8521 | 8641 | |
| 8522 | − if ((acrtc_state->update_type > UPDATE_TYPE_FAST) && | |
| 8523 | − acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED && | |
| 8524 | − !acrtc_state->stream->link->psr_settings.psr_feature_enabled) | |
| 8525 | − amdgpu_dm_link_setup_psr(acrtc_state->stream); | |
| 8642 | + if (acrtc_state->update_type > UPDATE_TYPE_FAST) { | |
| 8643 | + if (acrtc_state->stream->link->replay_settings.config.replay_supported && | |
| 8644 | + !acrtc_state->stream->link->replay_settings.replay_feature_enabled) { | |
| 8645 | + struct amdgpu_dm_connector *aconn = | |
| 8646 | + (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context; | |
| 8647 | + amdgpu_dm_link_setup_replay(acrtc_state->stream->link, aconn); | |
| 8648 | + } else if (acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED && | |
| 8649 | + !acrtc_state->stream->link->psr_settings.psr_feature_enabled) { | |
| 8650 | + | |
| 8651 | + struct amdgpu_dm_connector *aconn = (struct amdgpu_dm_connector *) | |
| 8652 | + acrtc_state->stream->dm_stream_context; | |
| 8653 | + | |
| 8654 | + if (!aconn->disallow_edp_enter_psr) | |
| 8655 | + amdgpu_dm_link_setup_psr(acrtc_state->stream); | |
| 8656 | + } | |
| 8657 | + } | |
| 8526 | 8658 | |
| 8527 | 8659 | /* Decrement skip count when PSR is enabled and we're doing fast updates. */ |
| 8528 | 8660 | if (acrtc_state->update_type == UPDATE_TYPE_FAST && |
| @@ -8549,6 +8681,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, · 20 unmodified lines | ||
| 8549 | 8681 | !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) && |
| 8550 | 8682 | #endif |
| 8551 | 8683 | !acrtc_state->stream->link->psr_settings.psr_allow_active && |
| 8684 | + !aconn->disallow_edp_enter_psr && | |
| 8552 | 8685 | (timestamp_ns - |
| 8553 | 8686 | acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns) > |
| 8554 | 8687 | 500000000) |
| @@ -8811,11 +8944,12 @@ static void amdgpu_dm_commit_streams(struct drm_atomic_state *state, · 256 unmodified lines | ||
| 8811 | 8944 | } |
| 8812 | 8945 | } /* for_each_crtc_in_state() */ |
| 8813 | 8946 | |
| 8814 | − /* if there mode set or reset, disable eDP PSR */ | |
| 8947 | + /* if there mode set or reset, disable eDP PSR, Replay */ | |
| 8815 | 8948 | if (mode_set_reset_required) { |
| 8816 | 8949 | if (dm->vblank_control_workqueue) |
| 8817 | 8950 | flush_workqueue(dm->vblank_control_workqueue); |
| 8818 | 8951 | |
| 8952 | + amdgpu_dm_replay_disable_all(dm); | |
| 8819 | 8953 | amdgpu_dm_psr_disable_all(dm); |
| 8820 | 8954 | } |
| 8821 | 8955 | |
| @@ -8976,16 +9110,8 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) · 154 unmodified lines | ||
| 8976 | 9110 | |
| 8977 | 9111 | trace_amdgpu_dm_atomic_commit_tail_begin(state); |
| 8978 | 9112 | |
| 8979 | − if (dm->dc->caps.ips_support) { | |
| 8980 | − for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { | |
| 8981 | − if (new_con_state->crtc && | |
| 8982 | − new_con_state->crtc->state->active && | |
| 8983 | − drm_atomic_crtc_needs_modeset(new_con_state->crtc->state)) { | |
| 8984 | − dc_dmub_srv_apply_idle_power_optimizations(dm->dc, false); | |
| 8985 | − break; | |
| 8986 | − } | |
| 8987 | − } | |
| 8988 | − } | |
| 9113 | + if (dm->dc->caps.ips_support && dm->dc->idle_optimizations_allowed) | |
| 9114 | + dc_allow_idle_optimizations(dm->dc, false); | |
| 8989 | 9115 | |
| 8990 | 9116 | drm_atomic_helper_update_legacy_modeset_state(dev, state); |
| 8991 | 9117 | drm_dp_mst_atomic_wait_for_dependencies(state); |
| @@ -9188,6 +9314,10 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) · 196 unmodified lines | ||
| 9188 | 9314 | * To fix this, DC should permit updating only stream properties. |
| 9189 | 9315 | */ |
| 9190 | 9316 | dummy_updates = kzalloc(sizeof(struct dc_surface_update) * MAX_SURFACES, GFP_ATOMIC); |
| 9317 | + if (!dummy_updates) { | |
| 9318 | + DRM_ERROR("Failed to allocate memory for dummy_updates.\n"); | |
| 9319 | + continue; | |
| 9320 | + } | |
| 9191 | 9321 | for (j = 0; j < status->plane_count; j++) |
| 9192 | 9322 | dummy_updates[j].surface = status->plane_states[0]; |
| 9193 | 9323 | |
| @@ -10728,11 +10858,13 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, · 1534 unmodified lines | ||
| 10728 | 10858 | goto fail; |
| 10729 | 10859 | } |
| 10730 | 10860 | |
| 10731 | − ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars); | |
| 10732 | − if (ret) { | |
| 10733 | − DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n"); | |
| 10734 | − ret = -EINVAL; | |
| 10735 | − goto fail; | |
| 10861 | + if (dc_resource_is_dsc_encoding_supported(dc)) { | |
| 10862 | + ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars); | |
| 10863 | + if (ret) { | |
| 10864 | + DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n"); | |
| 10865 | + ret = -EINVAL; | |
| 10866 | + goto fail; | |
| 10867 | + } | |
| 10736 | 10868 | } |
| 10737 | 10869 | |
| 10738 | 10870 | ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars); |
| @@ -693,6 +693,7 @@ struct amdgpu_dm_connector { · 692 unmodified lines | ||
| 693 | 693 | struct drm_display_mode freesync_vid_base; |
| 694 | 694 | |
| 695 | 695 | int psr_skip_count; |
| 696 | + bool disallow_edp_enter_psr; | |
| 696 | 697 | |
| 697 | 698 | /* Record progress status of mst*/ |
| 698 | 699 | uint8_t mst_status; |
| @@ -29,6 +29,7 @@ · 28 unmodified lines | ||
| 29 | 29 | #include "dc.h" |
| 30 | 30 | #include "amdgpu.h" |
| 31 | 31 | #include "amdgpu_dm_psr.h" |
| 32 | +#include "amdgpu_dm_replay.h" | |
| 32 | 33 | #include "amdgpu_dm_crtc.h" |
| 33 | 34 | #include "amdgpu_dm_plane.h" |
| 34 | 35 | #include "amdgpu_dm_trace.h" |
| @@ -95,6 +96,61 @@ bool amdgpu_dm_crtc_vrr_active(struct dm_crtc_state *dm_state) · 60 unmodified lines | ||
| 95 | 96 | dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED; |
| 96 | 97 | } |
| 97 | 98 | |
| 99 | +/** | |
| 100 | + * amdgpu_dm_crtc_set_panel_sr_feature() - Manage panel self-refresh features. | |
| 101 | + * | |
| 102 | + * @vblank_work: is a pointer to a struct vblank_control_work object. | |
| 103 | + * @vblank_enabled: indicates whether the DRM vblank counter is currently | |
| 104 | + * enabled (true) or disabled (false). | |
| 105 | + * @allow_sr_entry: represents whether entry into the self-refresh mode is | |
| 106 | + * allowed (true) or not allowed (false). | |
| 107 | + * | |
| 108 | + * The DRM vblank counter enable/disable action is used as the trigger to enable | |
| 109 | + * or disable various panel self-refresh features: | |
| 110 | + * | |
| 111 | + * Panel Replay and PSR SU | |
| 112 | + * - Enable when: | |
| 113 | + * - vblank counter is disabled | |
| 114 | + * - entry is allowed: usermode demonstrates an adequate number of fast | |
| 115 | + * commits) | |
| 116 | + * - CRC capture window isn't active | |
| 117 | + * - Keep enabled even when vblank counter gets enabled | |
| 118 | + * | |
| 119 | + * PSR1 | |
| 120 | + * - Enable condition same as above | |
| 121 | + * - Disable when vblank counter is enabled | |
| 122 | + */ | |
| 123 | +static void amdgpu_dm_crtc_set_panel_sr_feature( | |
| 124 | + struct vblank_control_work *vblank_work, | |
| 125 | + bool vblank_enabled, bool allow_sr_entry) | |
| 126 | +{ | |
| 127 | + struct dc_link *link = vblank_work->stream->link; | |
| 128 | + bool is_sr_active = (link->replay_settings.replay_allow_active || | |
| 129 | + link->psr_settings.psr_allow_active); | |
| 130 | + bool is_crc_window_active = false; | |
| 131 | + | |
| 132 | +#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY | |
| 133 | + is_crc_window_active = | |
| 134 | + amdgpu_dm_crc_window_is_activated(&vblank_work->acrtc->base); | |
| 135 | +#endif | |
| 136 | + | |
| 137 | + if (link->replay_settings.replay_feature_enabled && | |
| 138 | + allow_sr_entry && !is_sr_active && !is_crc_window_active) { | |
| 139 | + amdgpu_dm_replay_enable(vblank_work->stream, true); | |
| 140 | + } else if (vblank_enabled) { | |
| 141 | + if (link->psr_settings.psr_version < DC_PSR_VERSION_SU_1 && is_sr_active) | |
| 142 | + amdgpu_dm_psr_disable(vblank_work->stream); | |
| 143 | + } else if (link->psr_settings.psr_feature_enabled && | |
| 144 | + allow_sr_entry && !is_sr_active && !is_crc_window_active) { | |
| 145 | + | |
| 146 | + struct amdgpu_dm_connector *aconn = | |
| 147 | + (struct amdgpu_dm_connector *) vblank_work->stream->dm_stream_context; | |
| 148 | + | |
| 149 | + if (!aconn->disallow_edp_enter_psr) | |
| 150 | + amdgpu_dm_psr_enable(vblank_work->stream); | |
| 151 | + } | |
| 152 | +} | |
| 153 | + | |
| 98 | 154 | static void amdgpu_dm_crtc_vblank_control_worker(struct work_struct *work) |
| 99 | 155 | { |
| 100 | 156 | struct vblank_control_work *vblank_work = |
| @@ -123,18 +179,10 @@ static void amdgpu_dm_crtc_vblank_control_worker(struct work_struct *work) · 22 unmodified lines | ||
| 123 | 179 | * fill_dc_dirty_rects(). |
| 124 | 180 | */ |
| 125 | 181 | if (vblank_work->stream && vblank_work->stream->link) { |
| 126 | − if (vblank_work->enable) { | |
| 127 | − if (vblank_work->stream->link->psr_settings.psr_version < DC_PSR_VERSION_SU_1 && | |
| 128 | − vblank_work->stream->link->psr_settings.psr_allow_active) | |
| 129 | − amdgpu_dm_psr_disable(vblank_work->stream); | |
| 130 | − } else if (vblank_work->stream->link->psr_settings.psr_feature_enabled && | |
| 131 | − !vblank_work->stream->link->psr_settings.psr_allow_active && | |
| 132 | −#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY | |
| 133 | − !amdgpu_dm_crc_window_is_activated(&vblank_work->acrtc->base) && | |
| 134 | −#endif | |
| 135 | − vblank_work->acrtc->dm_irq_params.allow_psr_entry) { | |
| 136 | − amdgpu_dm_psr_enable(vblank_work->stream); | |
| 137 | − } | |
| 182 | + amdgpu_dm_crtc_set_panel_sr_feature( | |
| 183 | + vblank_work, vblank_work->enable, | |
| 184 | + vblank_work->acrtc->dm_irq_params.allow_psr_entry || | |
| 185 | + vblank_work->stream->link->replay_settings.replay_feature_enabled); | |
| 138 | 186 | } |
| 139 | 187 | |
| 140 | 188 | mutex_unlock(&dm->dc_lock); |
| @@ -1483,7 +1483,7 @@ static ssize_t dp_dsc_clock_en_read(struct file *f, char __user *buf, · 1482 unmodified lines | ||
| 1483 | 1483 | const uint32_t rd_buf_size = 10; |
| 1484 | 1484 | struct pipe_ctx *pipe_ctx; |
| 1485 | 1485 | ssize_t result = 0; |
| 1486 | − int i, r, str_len = 30; | |
| 1486 | + int i, r, str_len = 10; | |
| 1487 | 1487 | |
| 1488 | 1488 | rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); |
| 1489 | 1489 | |
| @@ -2971,6 +2971,53 @@ static int allow_edp_hotplug_detection_set(void *data, u64 val) · 1481 unmodified lines | ||
| 2971 | 2971 | return 0; |
| 2972 | 2972 | } |
| 2973 | 2973 | |
| 2974 | +/* check if kernel disallow eDP enter psr state | |
| 2975 | + * cat /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr | |
| 2976 | + * 0: allow edp enter psr; 1: disallow | |
| 2977 | + */ | |
| 2978 | +static int disallow_edp_enter_psr_get(void *data, u64 *val) | |
| 2979 | +{ | |
| 2980 | + struct amdgpu_dm_connector *aconnector = data; | |
| 2981 | + | |
| 2982 | + *val = (u64) aconnector->disallow_edp_enter_psr; | |
| 2983 | + return 0; | |
| 2984 | +} | |
| 2985 | + | |
| 2986 | +/* set kernel disallow eDP enter psr state | |
| 2987 | + * echo 0x0 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr | |
| 2988 | + * 0: allow edp enter psr; 1: disallow | |
| 2989 | + * | |
| 2990 | + * usage: test app read crc from PSR eDP rx. | |
| 2991 | + * | |
| 2992 | + * during kernel boot up, kernel write dpcd 0x170 = 5. | |
| 2993 | + * this notify eDP rx psr enable and let rx check crc. | |
| 2994 | + * rx fw will start checking crc for rx internal logic. | |
| 2995 | + * crc read count within dpcd 0x246 is not updated and | |
| 2996 | + * value is 0. when eDP tx driver wants to read rx crc | |
| 2997 | + * from dpcd 0x246, 0x270, read count 0 lead tx driver | |
| 2998 | + * timeout. | |
| 2999 | + * | |
| 3000 | + * to avoid this, we add this debugfs to let test app to disbable | |
| 3001 | + * rx crc checking for rx internal logic. then test app can read | |
| 3002 | + * non-zero crc read count. | |
| 3003 | + * | |
| 3004 | + * expected app sequence is as below: | |
| 3005 | + * 1. disable eDP PHY and notify eDP rx with dpcd 0x600 = 2. | |
| 3006 | + * 2. echo 0x1 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr | |
| 3007 | + * 3. enable eDP PHY and notify eDP rx with dpcd 0x600 = 1 but | |
| 3008 | + * without dpcd 0x170 = 5. | |
| 3009 | + * 4. read crc from rx dpcd 0x270, 0x246, etc. | |
| 3010 | + * 5. echo 0x0 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr. | |
| 3011 | + * this will let eDP back to normal with psr setup dpcd 0x170 = 5. | |
| 3012 | + */ | |
| 3013 | +static int disallow_edp_enter_psr_set(void *data, u64 val) | |
| 3014 | +{ | |
| 3015 | + struct amdgpu_dm_connector *aconnector = data; | |
| 3016 | + | |
| 3017 | + aconnector->disallow_edp_enter_psr = val ? true : false; | |
| 3018 | + return 0; | |
| 3019 | +} | |
| 3020 | + | |
| 2974 | 3021 | static int dmub_trace_mask_set(void *data, u64 val) |
| 2975 | 3022 | { |
| 2976 | 3023 | struct amdgpu_device *adev = data; |
| @@ -3092,6 +3139,10 @@ DEFINE_DEBUGFS_ATTRIBUTE(allow_edp_hotplug_detection_fops, · 115 unmodified lines | ||
| 3092 | 3139 | allow_edp_hotplug_detection_get, |
| 3093 | 3140 | allow_edp_hotplug_detection_set, "%llu\n"); |
| 3094 | 3141 | |
| 3142 | +DEFINE_DEBUGFS_ATTRIBUTE(disallow_edp_enter_psr_fops, | |
| 3143 | + disallow_edp_enter_psr_get, | |
| 3144 | + disallow_edp_enter_psr_set, "%llu\n"); | |
| 3145 | + | |
| 3095 | 3146 | DEFINE_SHOW_ATTRIBUTE(current_backlight); |
| 3096 | 3147 | DEFINE_SHOW_ATTRIBUTE(target_backlight); |
| 3097 | 3148 | |
| @@ -3265,6 +3316,8 @@ void connector_debugfs_init(struct amdgpu_dm_connector *connector) · 167 unmodified lines | ||
| 3265 | 3316 | &edp_ilr_debugfs_fops); |
| 3266 | 3317 | debugfs_create_file("allow_edp_hotplug_detection", 0644, dir, connector, |
| 3267 | 3318 | &allow_edp_hotplug_detection_fops); |
| 3319 | + debugfs_create_file("disallow_edp_enter_psr", 0644, dir, connector, | |
| 3320 | + &disallow_edp_enter_psr_fops); | |
| 3268 | 3321 | } |
| 3269 | 3322 | |
| 3270 | 3323 | for (i = 0; i < ARRAY_SIZE(connector_debugfs_entries); i++) { |
| @@ -711,7 +711,7 @@ static inline int dm_irq_state(struct amdgpu_device *adev, · 710 unmodified lines | ||
| 711 | 711 | { |
| 712 | 712 | bool st; |
| 713 | 713 | enum dc_irq_source irq_source; |
| 714 | − | |
| 714 | + struct dc *dc = adev->dm.dc; | |
| 715 | 715 | struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc_id]; |
| 716 | 716 | |
| 717 | 717 | if (!acrtc) { |
| @@ -729,6 +729,9 @@ static inline int dm_irq_state(struct amdgpu_device *adev, · 11 unmodified lines | ||
| 729 | 729 | |
| 730 | 730 | st = (state == AMDGPU_IRQ_STATE_ENABLE); |
| 731 | 731 | |
| 732 | + if (dc && dc->caps.ips_support && dc->idle_optimizations_allowed) | |
| 733 | + dc_allow_idle_optimizations(dc, false); | |
| 734 | + | |
| 732 | 735 | dc_interrupt_set(adev->dm.dc, irq_source, st); |
| 733 | 736 | return 0; |
| 734 | 737 | } |
| @@ -60,21 +60,26 @@ static bool link_supports_replay(struct dc_link *link, struct amdgpu_dm_connecto · 59 unmodified lines | ||
| 60 | 60 | if (!as_caps->dp_adap_sync_caps.bits.ADAPTIVE_SYNC_SDP_SUPPORT) |
| 61 | 61 | return false; |
| 62 | 62 | |
| 63 | + // Sink shall populate line deviation information | |
| 64 | + if (dpcd_caps->pr_info.pixel_deviation_per_line == 0 || | |
| 65 | + dpcd_caps->pr_info.max_deviation_line == 0) | |
| 66 | + return false; | |
| 67 | + | |
| 63 | 68 | return true; |
| 64 | 69 | } |
| 65 | 70 | |
| 66 | 71 | /* |
| 67 | − * amdgpu_dm_setup_replay() - setup replay configuration | |
| 72 | + * amdgpu_dm_set_replay_caps() - setup Replay capabilities | |
| 68 | 73 | * @link: link |
| 69 | 74 | * @aconnector: aconnector |
| 70 | 75 | * |
| 71 | 76 | */ |
| 72 | −bool amdgpu_dm_setup_replay(struct dc_link *link, struct amdgpu_dm_connector *aconnector) | |
| 77 | +bool amdgpu_dm_set_replay_caps(struct dc_link *link, struct amdgpu_dm_connector *aconnector) | |
| 73 | 78 | { |
| 74 | − struct replay_config pr_config; | |
| 79 | + struct replay_config pr_config = { 0 }; | |
| 75 | 80 | union replay_debug_flags *debug_flags = NULL; |
| 76 | 81 | |
| 77 | − // For eDP, if Replay is supported, return true to skip checks | |
| 82 | + // If Replay is already set to support, return true to skip checks | |
| 78 | 83 | if (link->replay_settings.config.replay_supported) |
| 79 | 84 | return true; |
| 80 | 85 | |
| @@ -87,27 +92,50 @@ bool amdgpu_dm_setup_replay(struct dc_link *link, struct amdgpu_dm_connector *ac · 6 unmodified lines | ||
| 87 | 92 | if (!link_supports_replay(link, aconnector)) |
| 88 | 93 | return false; |
| 89 | 94 | |
| 90 | − // Mark Replay is supported in link and update related attributes | |
| 95 | + // Mark Replay is supported in pr_config | |
| 91 | 96 | pr_config.replay_supported = true; |
| 92 | − pr_config.replay_power_opt_supported = 0; | |
| 93 | − pr_config.replay_enable_option |= pr_enable_option_static_screen; | |
| 94 | − pr_config.replay_timing_sync_supported = aconnector->max_vfreq >= 2 * aconnector->min_vfreq; | |
| 95 | − | |
| 96 | − if (!pr_config.replay_timing_sync_supported) | |
| 97 | − pr_config.replay_enable_option &= ~pr_enable_option_general_ui; | |
| 98 | 97 | |
| 99 | 98 | debug_flags = (union replay_debug_flags *)&pr_config.debug_flags; |
| 100 | 99 | debug_flags->u32All = 0; |
| 101 | 100 | debug_flags->bitfields.visual_confirm = |
| 102 | 101 | link->ctx->dc->debug.visual_confirm == VISUAL_CONFIRM_REPLAY; |
| 103 | 102 | |
| 104 | − link->replay_settings.replay_feature_enabled = true; | |
| 105 | − | |
| 106 | 103 | init_replay_config(link, &pr_config); |
| 107 | 104 | |
| 108 | 105 | return true; |
| 109 | 106 | } |
| 110 | 107 | |
| 108 | +/* | |
| 109 | + * amdgpu_dm_link_setup_replay() - configure replay link | |
| 110 | + * @link: link | |
| 111 | + * @aconnector: aconnector | |
| 112 | + * | |
| 113 | + */ | |
| 114 | +bool amdgpu_dm_link_setup_replay(struct dc_link *link, struct amdgpu_dm_connector *aconnector) | |
| 115 | +{ | |
| 116 | + struct replay_config *pr_config; | |
| 117 | + | |
| 118 | + if (link == NULL || aconnector == NULL) | |
| 119 | + return false; | |
| 120 | + | |
| 121 | + pr_config = &link->replay_settings.config; | |
| 122 | + | |
| 123 | + if (!pr_config->replay_supported) | |
| 124 | + return false; | |
| 125 | + | |
| 126 | + pr_config->replay_power_opt_supported = 0x11; | |
| 127 | + pr_config->replay_smu_opt_supported = false; | |
| 128 | + pr_config->replay_enable_option |= pr_enable_option_static_screen; | |
| 129 | + pr_config->replay_support_fast_resync_in_ultra_sleep_mode = aconnector->max_vfreq >= 2 * aconnector->min_vfreq; | |
| 130 | + pr_config->replay_timing_sync_supported = false; | |
| 131 | + | |
| 132 | + if (!pr_config->replay_timing_sync_supported) | |
| 133 | + pr_config->replay_enable_option &= ~pr_enable_option_general_ui; | |
| 134 | + | |
| 135 | + link->replay_settings.replay_feature_enabled = true; | |
| 136 | + | |
| 137 | + return true; | |
| 138 | +} | |
| 111 | 139 | |
| 112 | 140 | /* |
| 113 | 141 | * amdgpu_dm_replay_enable() - enable replay f/w |
| @@ -117,51 +145,23 @@ bool amdgpu_dm_setup_replay(struct dc_link *link, struct amdgpu_dm_connector *ac · 3 unmodified lines | ||
| 117 | 145 | */ |
| 118 | 146 | bool amdgpu_dm_replay_enable(struct dc_stream_state *stream, bool wait) |
| 119 | 147 | { |
| 120 | − uint64_t state; | |
| 121 | − unsigned int retry_count; | |
| 122 | 148 | bool replay_active = true; |
| 123 | − const unsigned int max_retry = 1000; | |
| 124 | − bool force_static = true; | |
| 125 | 149 | struct dc_link *link = NULL; |
| 126 | 150 | |
| 127 | − | |
| 128 | 151 | if (stream == NULL) |
| 129 | 152 | return false; |
| 130 | 153 | |
| 131 | 154 | link = stream->link; |
| 132 | 155 | |
| 133 | − if (link == NULL) | |
| 134 | − return false; | |
| 135 | − | |
| 136 | − link->dc->link_srv->edp_setup_replay(link, stream); | |
| 137 | − | |
| 138 | − link->dc->link_srv->edp_set_replay_allow_active(link, NULL, false, false, NULL); | |
| 139 | − | |
| 140 | − link->dc->link_srv->edp_set_replay_allow_active(link, &replay_active, false, true, NULL); | |
| 141 | − | |
| 142 | − if (wait == true) { | |
| 143 | − | |
| 144 | − for (retry_count = 0; retry_count <= max_retry; retry_count++) { | |
| 145 | − dc_link_get_replay_state(link, &state); | |
| 146 | − if (replay_active) { | |
| 147 | − if (state != REPLAY_STATE_0 && | |
| 148 | − (!force_static || state == REPLAY_STATE_3)) | |
| 149 | − break; | |
| 150 | − } else { | |
| 151 | − if (state == REPLAY_STATE_0) | |
| 152 | − break; | |
| 153 | − } | |
| 154 | − udelay(500); | |
| 155 | − } | |
| 156 | − | |
| 157 | − /* assert if max retry hit */ | |
| 158 | − if (retry_count >= max_retry) | |
| 159 | − ASSERT(0); | |
| 160 | − } else { | |
| 161 | − /* To-do: Add trace log */ | |
| 156 | + if (link) { | |
| 157 | + link->dc->link_srv->edp_setup_replay(link, stream); | |
| 158 | + link->dc->link_srv->edp_set_coasting_vtotal(link, stream->timing.v_total); | |
| 159 | + DRM_DEBUG_DRIVER("Enabling replay...\n"); | |
| 160 | + link->dc->link_srv->edp_set_replay_allow_active(link, &replay_active, wait, false, NULL); | |
| 161 | + return true; | |
| 162 | 162 | } |
| 163 | 163 | |
| 164 | − return true; | |
| 164 | + return false; | |
| 165 | 165 | } |
| 166 | 166 | |
| 167 | 167 | /* |
| @@ -172,12 +172,31 @@ bool amdgpu_dm_replay_enable(struct dc_stream_state *stream, bool wait) · 4 unmodified lines | ||
| 172 | 172 | */ |
| 173 | 173 | bool amdgpu_dm_replay_disable(struct dc_stream_state *stream) |
| 174 | 174 | { |
| 175 | + bool replay_active = false; | |
| 176 | + struct dc_link *link = NULL; | |
| 175 | 177 | |
| 176 | − if (stream->link) { | |
| 178 | + if (stream == NULL) | |
| 179 | + return false; | |
| 180 | + | |
| 181 | + link = stream->link; | |
| 182 | + | |
| 183 | + if (link) { | |
| 177 | 184 | DRM_DEBUG_DRIVER("Disabling replay...\n"); |
| 178 | − stream->link->dc->link_srv->edp_set_replay_allow_active(stream->link, NULL, false, false, NULL); | |
| 185 | + link->dc->link_srv->edp_set_replay_allow_active(stream->link, &replay_active, true, false, NULL); | |
| 179 | 186 | return true; |
| 180 | 187 | } |
| 181 | 188 | |
| 182 | 189 | return false; |
| 183 | 190 | } |
| 191 | + | |
| 192 | +/* | |
| 193 | + * amdgpu_dm_replay_disable_all() - disable replay f/w | |
| 194 | + * if replay is enabled on any stream | |
| 195 | + * | |
| 196 | + * Return: true if success | |
| 197 | + */ | |
| 198 | +bool amdgpu_dm_replay_disable_all(struct amdgpu_display_manager *dm) | |
| 199 | +{ | |
| 200 | + DRM_DEBUG_DRIVER("Disabling replay if replay is enabled on any stream\n"); | |
| 201 | + return dc_set_replay_allow_active(dm->dc, false); | |
| 202 | +} | |
| @@ -40,7 +40,9 @@ enum replay_enable_option { · 39 unmodified lines | ||
| 40 | 40 | |
| 41 | 41 | |
| 42 | 42 | bool amdgpu_dm_replay_enable(struct dc_stream_state *stream, bool enable); |
| 43 | −bool amdgpu_dm_setup_replay(struct dc_link *link, struct amdgpu_dm_connector *aconnector); | |
| 43 | +bool amdgpu_dm_set_replay_caps(struct dc_link *link, struct amdgpu_dm_connector *aconnector); | |
| 44 | +bool amdgpu_dm_link_setup_replay(struct dc_link *link, struct amdgpu_dm_connector *aconnector); | |
| 44 | 45 | bool amdgpu_dm_replay_disable(struct dc_stream_state *stream); |
| 46 | +bool amdgpu_dm_replay_disable_all(struct amdgpu_display_manager *dm); | |
| 45 | 47 | |
| 46 | 48 | #endif /* AMDGPU_DM_AMDGPU_DM_REPLAY_H_ */ |
| @@ -101,6 +101,40 @@ void convert_float_matrix( · 100 unmodified lines | ||
| 101 | 101 | } |
| 102 | 102 | } |
| 103 | 103 | |
| 104 | +static struct fixed31_32 int_frac_to_fixed_point(uint16_t arg, | |
| 105 | + uint8_t integer_bits, | |
| 106 | + uint8_t fractional_bits) | |
| 107 | +{ | |
| 108 | + struct fixed31_32 result; | |
| 109 | + uint16_t sign_mask = 1 << (fractional_bits + integer_bits); | |
| 110 | + uint16_t value_mask = sign_mask - 1; | |
| 111 | + | |
| 112 | + result.value = (long long)(arg & value_mask) << | |
| 113 | + (FIXED31_32_BITS_PER_FRACTIONAL_PART - fractional_bits); | |
| 114 | + | |
| 115 | + if (arg & sign_mask) | |
| 116 | + result = dc_fixpt_neg(result); | |
| 117 | + | |
| 118 | + return result; | |
| 119 | +} | |
| 120 | + | |
| 121 | +/** | |
| 122 | + * convert_hw_matrix - converts HW values into fixed31_32 matrix. | |
| 123 | + * @matrix: fixed point 31.32 matrix | |
| 124 | + * @reg: array of register values | |
| 125 | + * @buffer_size: size of the array of register values | |
| 126 | + * | |
| 127 | + * Converts HW register spec defined format S2D13 into a fixed-point 31.32 | |
| 128 | + * matrix. | |
| 129 | + */ | |
| 130 | +void convert_hw_matrix(struct fixed31_32 *matrix, | |
| 131 | + uint16_t *reg, | |
| 132 | + uint32_t buffer_size) | |
| 133 | +{ | |
| 134 | + for (int i = 0; i < buffer_size; ++i) | |
| 135 | + matrix[i] = int_frac_to_fixed_point(reg[i], 2, 13); | |
| 136 | +} | |
| 137 | + | |
| 104 | 138 | static uint32_t find_gcd(uint32_t a, uint32_t b) |
| 105 | 139 | { |
| 106 | 140 | uint32_t remainder; |
| @@ -41,6 +41,10 @@ void convert_float_matrix( · 40 unmodified lines | ||
| 41 | 41 | void reduce_fraction(uint32_t num, uint32_t den, |
| 42 | 42 | uint32_t *out_num, uint32_t *out_den); |
| 43 | 43 | |
| 44 | +void convert_hw_matrix(struct fixed31_32 *matrix, | |
| 45 | + uint16_t *reg, | |
| 46 | + uint32_t buffer_size); | |
| 47 | + | |
| 44 | 48 | static inline unsigned int log_2(unsigned int num) |
| 45 | 49 | { |
| 46 | 50 | return ilog2(num); |
| @@ -37,7 +37,7 @@ · 36 unmodified lines | ||
| 37 | 37 | #define EXEC_BIOS_CMD_TABLE(command, params)\ |
| 38 | 38 | (amdgpu_atom_execute_table(((struct amdgpu_device *)bp->base.ctx->driver_context)->mode_info.atom_context, \ |
| 39 | 39 | GetIndexIntoMasterTable(COMMAND, command), \ |
| 40 | − (uint32_t *)¶ms) == 0) | |
| 40 | + (uint32_t *)¶ms, sizeof(params)) == 0) | |
| 41 | 41 | |
| 42 | 42 | #define BIOS_CMD_TABLE_REVISION(command, frev, crev)\ |
| 43 | 43 | amdgpu_atom_parse_cmd_header(((struct amdgpu_device *)bp->base.ctx->driver_context)->mode_info.atom_context, \ |
| @@ -49,7 +49,7 @@ · 48 unmodified lines | ||
| 49 | 49 | #define EXEC_BIOS_CMD_TABLE(fname, params)\ |
| 50 | 50 | (amdgpu_atom_execute_table(((struct amdgpu_device *)bp->base.ctx->driver_context)->mode_info.atom_context, \ |
| 51 | 51 | GET_INDEX_INTO_MASTER_TABLE(command, fname), \ |
| 52 | − (uint32_t *)¶ms) == 0) | |
| 52 | + (uint32_t *)¶ms, sizeof(params)) == 0) | |
| 53 | 53 | |
| 54 | 54 | #define BIOS_CMD_TABLE_REVISION(fname, frev, crev)\ |
| 55 | 55 | amdgpu_atom_parse_cmd_header(((struct amdgpu_device *)bp->base.ctx->driver_context)->mode_info.atom_context, \ |
| @@ -707,9 +707,7 @@ void rn_clk_mgr_construct( · 706 unmodified lines | ||
| 707 | 707 | int is_green_sardine = 0; |
| 708 | 708 | struct clk_log_info log_info = {0}; |
| 709 | 709 | |
| 710 | −#if defined(CONFIG_DRM_AMD_DC_FP) | |
| 711 | 710 | is_green_sardine = ASICREV_IS_GREEN_SARDINE(ctx->asic_id.hw_internal_rev); |
| 712 | −#endif | |
| 713 | 711 | |
| 714 | 712 | clk_mgr->base.ctx = ctx; |
| 715 | 713 | clk_mgr->base.funcs = &dcn21_funcs; |
| @@ -185,10 +185,6 @@ int rn_vbios_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int reque · 184 unmodified lines | ||
| 185 | 185 | VBIOSSMC_MSG_SetHardMinDcfclkByFreq, |
| 186 | 186 | khz_to_mhz_ceil(requested_dcfclk_khz)); |
| 187 | 187 | |
| 188 | −#ifdef DBG | |
| 189 | − smu_print("actual_dcfclk_set_mhz %d is set to : %d\n", actual_dcfclk_set_mhz, actual_dcfclk_set_mhz * 1000); | |
| 190 | −#endif | |
| 191 | − | |
| 192 | 188 | return actual_dcfclk_set_mhz * 1000; |
| 193 | 189 | } |
| 194 | 190 | |
| @@ -180,10 +180,6 @@ int dcn301_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int request · 179 unmodified lines | ||
| 180 | 180 | VBIOSSMC_MSG_SetHardMinDcfclkByFreq, |
| 181 | 181 | khz_to_mhz_ceil(requested_dcfclk_khz)); |
| 182 | 182 | |
| 183 | −#ifdef DBG | |
| 184 | − smu_print("actual_dcfclk_set_mhz %d is set to : %d\n", actual_dcfclk_set_mhz, actual_dcfclk_set_mhz * 1000); | |
| 185 | −#endif | |
| 186 | − | |
| 187 | 183 | return actual_dcfclk_set_mhz * 1000; |
| 188 | 184 | } |
| 189 | 185 | |
| @@ -202,10 +202,6 @@ int dcn31_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requeste · 201 unmodified lines | ||
| 202 | 202 | VBIOSSMC_MSG_SetHardMinDcfclkByFreq, |
| 203 | 203 | khz_to_mhz_ceil(requested_dcfclk_khz)); |
| 204 | 204 | |
| 205 | −#ifdef DBG | |
| 206 | − smu_print("actual_dcfclk_set_mhz %d is set to : %d\n", actual_dcfclk_set_mhz, actual_dcfclk_set_mhz * 1000); | |
| 207 | −#endif | |
| 208 | − | |
| 209 | 205 | return actual_dcfclk_set_mhz * 1000; |
| 210 | 206 | } |
| 211 | 207 | |
| @@ -220,12 +220,6 @@ int dcn314_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int request · 219 unmodified lines | ||
| 220 | 220 | VBIOSSMC_MSG_SetHardMinDcfclkByFreq, |
| 221 | 221 | khz_to_mhz_ceil(requested_dcfclk_khz)); |
| 222 | 222 | |
| 223 | −#ifdef DBG | |
| 224 | − smu_print("actual_dcfclk_set_mhz %d is set to : %d\n", | |
| 225 | − actual_dcfclk_set_mhz, | |
| 226 | − actual_dcfclk_set_mhz * 1000); | |
| 227 | −#endif | |
| 228 | − | |
| 229 | 223 | return actual_dcfclk_set_mhz * 1000; |
| 230 | 224 | } |
| 231 | 225 | |
| @@ -215,10 +215,6 @@ int dcn315_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int request · 214 unmodified lines | ||
| 215 | 215 | VBIOSSMC_MSG_SetHardMinDcfclkByFreq, |
| 216 | 216 | khz_to_mhz_ceil(requested_dcfclk_khz)); |
| 217 | 217 | |
| 218 | −#ifdef DBG | |
| 219 | − smu_print("actual_dcfclk_set_mhz %d is set to : %d\n", actual_dcfclk_set_mhz, actual_dcfclk_set_mhz * 1000); | |
| 220 | −#endif | |
| 221 | − | |
| 222 | 218 | return actual_dcfclk_set_mhz * 1000; |
| 223 | 219 | } |
| 224 | 220 | |
| @@ -189,10 +189,6 @@ int dcn316_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int request · 188 unmodified lines | ||
| 189 | 189 | VBIOSSMC_MSG_SetHardMinDcfclkByFreq, |
| 190 | 190 | khz_to_mhz_ceil(requested_dcfclk_khz)); |
| 191 | 191 | |
| 192 | −#ifdef DBG | |
| 193 | − smu_print("actual_dcfclk_set_mhz %d is set to : %d\n", actual_dcfclk_set_mhz, actual_dcfclk_set_mhz * 1000); | |
| 194 | −#endif | |
| 195 | − | |
| 196 | 192 | return actual_dcfclk_set_mhz * 1000; |
| 197 | 193 | } |
| 198 | 194 | |
| @@ -387,7 +387,15 @@ static void dcn32_update_clocks_update_dentist( · 386 unmodified lines | ||
| 387 | 387 | uint32_t temp_dispclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / temp_disp_divider; |
| 388 | 388 | |
| 389 | 389 | if (clk_mgr->smu_present) |
| 390 | − dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, khz_to_mhz_ceil(temp_dispclk_khz)); | |
| 390 | + /* | |
| 391 | + * SMU uses discrete dispclk presets. We applied | |
| 392 | + * the same formula to increase our dppclk_khz | |
| 393 | + * to the next matching discrete value. By | |
| 394 | + * contract, we should use the preset dispclk | |
| 395 | + * floored in Mhz to describe the intended clock. | |
| 396 | + */ | |
| 397 | + dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, | |
| 398 | + khz_to_mhz_floor(temp_dispclk_khz)); | |
| 391 | 399 | |
| 392 | 400 | if (dc->debug.override_dispclk_programming) { |
| 393 | 401 | REG_GET(DENTIST_DISPCLK_CNTL, |
| @@ -426,7 +434,15 @@ static void dcn32_update_clocks_update_dentist( · 32 unmodified lines | ||
| 426 | 434 | |
| 427 | 435 | /* do requested DISPCLK updates*/ |
| 428 | 436 | if (clk_mgr->smu_present) |
| 429 | − dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, khz_to_mhz_ceil(clk_mgr->base.clks.dispclk_khz)); | |
| 437 | + /* | |
| 438 | + * SMU uses discrete dispclk presets. We applied | |
| 439 | + * the same formula to increase our dppclk_khz | |
| 440 | + * to the next matching discrete value. By | |
| 441 | + * contract, we should use the preset dispclk | |
| 442 | + * floored in Mhz to describe the intended clock. | |
| 443 | + */ | |
| 444 | + dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, | |
| 445 | + khz_to_mhz_floor(clk_mgr->base.clks.dispclk_khz)); | |
| 430 | 446 | |
| 431 | 447 | if (dc->debug.override_dispclk_programming) { |
| 432 | 448 | REG_GET(DENTIST_DISPCLK_CNTL, |
| @@ -493,6 +509,8 @@ static void dcn32_auto_dpm_test_log( · 60 unmodified lines | ||
| 493 | 509 | } |
| 494 | 510 | } |
| 495 | 511 | |
| 512 | + msleep(5); | |
| 513 | + | |
| 496 | 514 | mall_ss_size_bytes = context->bw_ctx.bw.dcn.mall_ss_size_bytes; |
| 497 | 515 | |
| 498 | 516 | dispclk_khz_reg = REG_READ(CLK1_CLK0_CURRENT_CNT); // DISPCLK |
| @@ -734,7 +752,15 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base, · 235 unmodified lines | ||
| 734 | 752 | clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz; |
| 735 | 753 | |
| 736 | 754 | if (clk_mgr->smu_present && !dpp_clock_lowered) |
| 737 | − dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz)); | |
| 755 | + /* | |
| 756 | + * SMU uses discrete dppclk presets. We applied | |
| 757 | + * the same formula to increase our dppclk_khz | |
| 758 | + * to the next matching discrete value. By | |
| 759 | + * contract, we should use the preset dppclk | |
| 760 | + * floored in Mhz to describe the intended clock. | |
| 761 | + */ | |
| 762 | + dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK, | |
| 763 | + khz_to_mhz_floor(clk_mgr_base->clks.dppclk_khz)); | |
| 738 | 764 | |
| 739 | 765 | update_dppclk = true; |
| 740 | 766 | } |
| @@ -765,7 +791,15 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base, · 24 unmodified lines | ||
| 765 | 791 | dcn32_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); |
| 766 | 792 | dcn32_update_clocks_update_dentist(clk_mgr, context); |
| 767 | 793 | if (clk_mgr->smu_present) |
| 768 | − dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz)); | |
| 794 | + /* | |
| 795 | + * SMU uses discrete dppclk presets. We applied | |
| 796 | + * the same formula to increase our dppclk_khz | |
| 797 | + * to the next matching discrete value. By | |
| 798 | + * contract, we should use the preset dppclk | |
| 799 | + * floored in Mhz to describe the intended clock. | |
| 800 | + */ | |
| 801 | + dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK, | |
| 802 | + khz_to_mhz_floor(clk_mgr_base->clks.dppclk_khz)); | |
| 769 | 803 | } else { |
| 770 | 804 | /* if clock is being raised, increase refclk before lowering DTO */ |
| 771 | 805 | if (update_dppclk || update_dispclk) |
| @@ -36,8 +36,7 @@ · 35 unmodified lines | ||
| 36 | 36 | #define DALSMC_MSG_SetCabForUclkPstate 0x12 |
| 37 | 37 | #define DALSMC_Result_OK 0x1 |
| 38 | 38 | |
| 39 | −void | |
| 40 | −dcn32_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool enable); | |
| 39 | +void dcn32_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool enable); | |
| 41 | 40 | void dcn32_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr); |
| 42 | 41 | void dcn32_smu_set_pme_workaround(struct clk_mgr_internal *clk_mgr); |
| 43 | 42 | void dcn32_smu_send_cab_for_uclk_message(struct clk_mgr_internal *clk_mgr, unsigned int num_ways); |
| @@ -384,19 +384,6 @@ static void dcn35_enable_pme_wa(struct clk_mgr *clk_mgr_base) · 383 unmodified lines | ||
| 384 | 384 | dcn35_smu_enable_pme_wa(clk_mgr); |
| 385 | 385 | } |
| 386 | 386 | |
| 387 | −void dcn35_init_clocks(struct clk_mgr *clk_mgr) | |
| 388 | −{ | |
| 389 | − uint32_t ref_dtbclk = clk_mgr->clks.ref_dtbclk_khz; | |
| 390 | − | |
| 391 | − memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); | |
| 392 | − | |
| 393 | − // Assumption is that boot state always supports pstate | |
| 394 | − clk_mgr->clks.ref_dtbclk_khz = ref_dtbclk; // restore ref_dtbclk | |
| 395 | − clk_mgr->clks.p_state_change_support = true; | |
| 396 | − clk_mgr->clks.prev_p_state_change_support = true; | |
| 397 | − clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN; | |
| 398 | − clk_mgr->clks.zstate_support = DCN_ZSTATE_SUPPORT_UNKNOWN; | |
| 399 | −} | |
| 400 | 387 | |
| 401 | 388 | bool dcn35_are_clock_states_equal(struct dc_clocks *a, |
| 402 | 389 | struct dc_clocks *b) |
| @@ -422,6 +409,23 @@ static void dcn35_dump_clk_registers(struct clk_state_registers_and_bypass *regs · 19 unmodified lines | ||
| 422 | 409 | { |
| 423 | 410 | } |
| 424 | 411 | |
| 412 | +static void init_clk_states(struct clk_mgr *clk_mgr) | |
| 413 | +{ | |
| 414 | + uint32_t ref_dtbclk = clk_mgr->clks.ref_dtbclk_khz; | |
| 415 | + memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); | |
| 416 | + | |
| 417 | + clk_mgr->clks.dtbclk_en = true; | |
| 418 | + clk_mgr->clks.ref_dtbclk_khz = ref_dtbclk; // restore ref_dtbclk | |
| 419 | + clk_mgr->clks.p_state_change_support = true; | |
| 420 | + clk_mgr->clks.prev_p_state_change_support = true; | |
| 421 | + clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN; | |
| 422 | + clk_mgr->clks.zstate_support = DCN_ZSTATE_SUPPORT_UNKNOWN; | |
| 423 | +} | |
| 424 | + | |
| 425 | +void dcn35_init_clocks(struct clk_mgr *clk_mgr) | |
| 426 | +{ | |
| 427 | + init_clk_states(clk_mgr); | |
| 428 | +} | |
| 425 | 429 | static struct clk_bw_params dcn35_bw_params = { |
| 426 | 430 | .vram_type = Ddr4MemType, |
| 427 | 431 | .num_channels = 1, |
| @@ -437,32 +441,32 @@ static struct wm_table ddr5_wm_table = { · 9 unmodified lines | ||
| 437 | 441 | .wm_inst = WM_A, |
| 438 | 442 | .wm_type = WM_TYPE_PSTATE_CHG, |
| 439 | 443 | .pstate_latency_us = 11.72, |
| 440 | − .sr_exit_time_us = 14.0, | |
| 441 | − .sr_enter_plus_exit_time_us = 16.0, | |
| 444 | + .sr_exit_time_us = 28.0, | |
| 445 | + .sr_enter_plus_exit_time_us = 30.0, | |
| 442 | 446 | .valid = true, |
| 443 | 447 | }, |
| 444 | 448 | { |
| 445 | 449 | .wm_inst = WM_B, |
| 446 | 450 | .wm_type = WM_TYPE_PSTATE_CHG, |
| 447 | 451 | .pstate_latency_us = 11.72, |
| 448 | − .sr_exit_time_us = 14.0, | |
| 449 | − .sr_enter_plus_exit_time_us = 16.0, | |
| 452 | + .sr_exit_time_us = 28.0, | |
| 453 | + .sr_enter_plus_exit_time_us = 30.0, | |
| 450 | 454 | .valid = true, |
| 451 | 455 | }, |
| 452 | 456 | { |
| 453 | 457 | .wm_inst = WM_C, |
| 454 | 458 | .wm_type = WM_TYPE_PSTATE_CHG, |
| 455 | 459 | .pstate_latency_us = 11.72, |
| 456 | − .sr_exit_time_us = 14.0, | |
| 457 | − .sr_enter_plus_exit_time_us = 16.0, | |
| 460 | + .sr_exit_time_us = 28.0, | |
| 461 | + .sr_enter_plus_exit_time_us = 30.0, | |
| 458 | 462 | .valid = true, |
| 459 | 463 | }, |
| 460 | 464 | { |
| 461 | 465 | .wm_inst = WM_D, |
| 462 | 466 | .wm_type = WM_TYPE_PSTATE_CHG, |
| 463 | 467 | .pstate_latency_us = 11.72, |
| 464 | − .sr_exit_time_us = 14.0, | |
| 465 | − .sr_enter_plus_exit_time_us = 16.0, | |
| 468 | + .sr_exit_time_us = 28.0, | |
| 469 | + .sr_enter_plus_exit_time_us = 30.0, | |
| 466 | 470 | .valid = true, |
| 467 | 471 | }, |
| 468 | 472 | } |
| @@ -474,32 +478,32 @@ static struct wm_table lpddr5_wm_table = { · 5 unmodified lines | ||
| 474 | 478 | .wm_inst = WM_A, |
| 475 | 479 | .wm_type = WM_TYPE_PSTATE_CHG, |
| 476 | 480 | .pstate_latency_us = 11.65333, |
| 477 | − .sr_exit_time_us = 14.0, | |
| 478 | − .sr_enter_plus_exit_time_us = 16.0, | |
| 481 | + .sr_exit_time_us = 28.0, | |
| 482 | + .sr_enter_plus_exit_time_us = 30.0, | |
| 479 | 483 | .valid = true, |
| 480 | 484 | }, |
| 481 | 485 | { |
| 482 | 486 | .wm_inst = WM_B, |
| 483 | 487 | .wm_type = WM_TYPE_PSTATE_CHG, |
| 484 | 488 | .pstate_latency_us = 11.65333, |
| 485 | − .sr_exit_time_us = 14.0, | |
| 486 | − .sr_enter_plus_exit_time_us = 16.0, | |
| 489 | + .sr_exit_time_us = 28.0, | |
| 490 | + .sr_enter_plus_exit_time_us = 30.0, | |
| 487 | 491 | .valid = true, |
| 488 | 492 | }, |
| 489 | 493 | { |
| 490 | 494 | .wm_inst = WM_C, |
| 491 | 495 | .wm_type = WM_TYPE_PSTATE_CHG, |
| 492 | 496 | .pstate_latency_us = 11.65333, |
| 493 | − .sr_exit_time_us = 14.0, | |
| 494 | − .sr_enter_plus_exit_time_us = 16.0, | |
| 497 | + .sr_exit_time_us = 28.0, | |
| 498 | + .sr_enter_plus_exit_time_us = 30.0, | |
| 495 | 499 | .valid = true, |
| 496 | 500 | }, |
| 497 | 501 | { |
| 498 | 502 | .wm_inst = WM_D, |
| 499 | 503 | .wm_type = WM_TYPE_PSTATE_CHG, |
| 500 | 504 | .pstate_latency_us = 11.65333, |
| 501 | − .sr_exit_time_us = 14.0, | |
| 502 | − .sr_enter_plus_exit_time_us = 16.0, | |
| 505 | + .sr_exit_time_us = 28.0, | |
| 506 | + .sr_enter_plus_exit_time_us = 30.0, | |
| 503 | 507 | .valid = true, |
| 504 | 508 | }, |
| 505 | 509 | } |
| @@ -826,7 +830,7 @@ static void dcn35_set_low_power_state(struct clk_mgr *clk_mgr_base) · 320 unmodified lines | ||
| 826 | 830 | } |
| 827 | 831 | } |
| 828 | 832 | |
| 829 | −static void dcn35_set_idle_state(struct clk_mgr *clk_mgr_base, bool allow_idle) | |
| 833 | +static void dcn35_set_ips_idle_state(struct clk_mgr *clk_mgr_base, bool allow_idle) | |
| 830 | 834 | { |
| 831 | 835 | struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); |
| 832 | 836 | struct dc *dc = clk_mgr_base->ctx->dc; |
| @@ -874,7 +878,7 @@ static bool dcn35_is_ips_supported(struct clk_mgr *clk_mgr_base) · 41 unmodified lines | ||
| 874 | 878 | return ips_supported; |
| 875 | 879 | } |
| 876 | 880 | |
| 877 | −static uint32_t dcn35_get_idle_state(struct clk_mgr *clk_mgr_base) | |
| 881 | +static uint32_t dcn35_get_ips_idle_state(struct clk_mgr *clk_mgr_base) | |
| 878 | 882 | { |
| 879 | 883 | struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); |
| 880 | 884 | |
| @@ -883,7 +887,7 @@ static uint32_t dcn35_get_idle_state(struct clk_mgr *clk_mgr_base) · 2 unmodified lines | ||
| 883 | 887 | |
| 884 | 888 | static void dcn35_init_clocks_fpga(struct clk_mgr *clk_mgr) |
| 885 | 889 | { |
| 886 | − dcn35_init_clocks(clk_mgr); | |
| 890 | + init_clk_states(clk_mgr); | |
| 887 | 891 | |
| 888 | 892 | /* TODO: Implement the functions and remove the ifndef guard */ |
| 889 | 893 | } |
| @@ -968,8 +972,8 @@ static struct clk_mgr_funcs dcn35_funcs = { · 78 unmodified lines | ||
| 968 | 972 | .set_low_power_state = dcn35_set_low_power_state, |
| 969 | 973 | .exit_low_power_state = dcn35_exit_low_power_state, |
| 970 | 974 | .is_ips_supported = dcn35_is_ips_supported, |
| 971 | − .set_idle_state = dcn35_set_idle_state, | |
| 972 | − .get_idle_state = dcn35_get_idle_state | |
| 975 | + .set_idle_state = dcn35_set_ips_idle_state, | |
| 976 | + .get_idle_state = dcn35_get_ips_idle_state | |
| 973 | 977 | }; |
| 974 | 978 | |
| 975 | 979 | struct clk_mgr_funcs dcn35_fpga_funcs = { |
| @@ -447,6 +447,9 @@ void dcn35_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable) · 446 unmodified lines | ||
| 447 | 447 | |
| 448 | 448 | void dcn35_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable) |
| 449 | 449 | { |
| 450 | + if (!clk_mgr->smu_present) | |
| 451 | + return; | |
| 452 | + | |
| 450 | 453 | dcn35_smu_send_msg_with_param( |
| 451 | 454 | clk_mgr, |
| 452 | 455 | VBIOSSMC_MSG_EnableTmdp48MHzRefclkPwrDown, |
| @@ -458,6 +461,9 @@ int dcn35_smu_exit_low_power_state(struct clk_mgr_internal *clk_mgr) · 5 unmodified lines | ||
| 458 | 461 | { |
| 459 | 462 | int retv; |
| 460 | 463 | |
| 464 | + if (!clk_mgr->smu_present) | |
| 465 | + return 0; | |
| 466 | + | |
| 461 | 467 | retv = dcn35_smu_send_msg_with_param( |
| 462 | 468 | clk_mgr, |
| 463 | 469 | VBIOSSMC_MSG_DispPsrExit, |
| @@ -470,6 +476,9 @@ int dcn35_smu_get_ips_supported(struct clk_mgr_internal *clk_mgr) · 6 unmodified lines | ||
| 470 | 476 | { |
| 471 | 477 | int retv; |
| 472 | 478 | |
| 479 | + if (!clk_mgr->smu_present) | |
| 480 | + return 0; | |
| 481 | + | |
| 473 | 482 | retv = dcn35_smu_send_msg_with_param( |
| 474 | 483 | clk_mgr, |
| 475 | 484 | VBIOSSMC_MSG_QueryIPS2Support, |
| @@ -481,6 +490,9 @@ int dcn35_smu_get_ips_supported(struct clk_mgr_internal *clk_mgr) · 5 unmodified lines | ||
| 481 | 490 | |
| 482 | 491 | void dcn35_smu_write_ips_scratch(struct clk_mgr_internal *clk_mgr, uint32_t param) |
| 483 | 492 | { |
| 493 | + if (!clk_mgr->smu_present) | |
| 494 | + return; | |
| 495 | + | |
| 484 | 496 | REG_WRITE(MP1_SMN_C2PMSG_71, param); |
| 485 | 497 | //smu_print("%s: write_ips_scratch = %x\n", __func__, param); |
| 486 | 498 | } |
| @@ -489,6 +501,9 @@ uint32_t dcn35_smu_read_ips_scratch(struct clk_mgr_internal *clk_mgr) · 2 unmodified lines | ||
| 489 | 501 | { |
| 490 | 502 | uint32_t retv; |
| 491 | 503 | |
| 504 | + if (!clk_mgr->smu_present) | |
| 505 | + return 0; | |
| 506 | + | |
| 492 | 507 | retv = REG_READ(MP1_SMN_C2PMSG_71); |
| 493 | 508 | //smu_print("%s: dcn35_smu_read_ips_scratch = %x\n", __func__, retv); |
| 494 | 509 | return retv; |
| @@ -414,6 +414,8 @@ bool dc_stream_adjust_vmin_vmax(struct dc *dc, · 413 unmodified lines | ||
| 414 | 414 | if (dc->optimized_required || dc->wm_optimized_required) |
| 415 | 415 | return false; |
| 416 | 416 | |
| 417 | + dc_exit_ips_for_hw_access(dc); | |
| 418 | + | |
| 417 | 419 | stream->adjust.v_total_max = adjust->v_total_max; |
| 418 | 420 | stream->adjust.v_total_mid = adjust->v_total_mid; |
| 419 | 421 | stream->adjust.v_total_mid_frame_num = adjust->v_total_mid_frame_num; |
| @@ -454,6 +456,8 @@ bool dc_stream_get_last_used_drr_vtotal(struct dc *dc, · 34 unmodified lines | ||
| 454 | 456 | |
| 455 | 457 | int i = 0; |
| 456 | 458 | |
| 459 | + dc_exit_ips_for_hw_access(dc); | |
| 460 | + | |
| 457 | 461 | for (i = 0; i < MAX_PIPES; i++) { |
| 458 | 462 | struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; |
| 459 | 463 | |
| @@ -484,6 +488,8 @@ bool dc_stream_get_crtc_position(struct dc *dc, · 24 unmodified lines | ||
| 484 | 488 | bool ret = false; |
| 485 | 489 | struct crtc_position position; |
| 486 | 490 | |
| 491 | + dc_exit_ips_for_hw_access(dc); | |
| 492 | + | |
| 487 | 493 | for (i = 0; i < MAX_PIPES; i++) { |
| 488 | 494 | struct pipe_ctx *pipe = |
| 489 | 495 | &dc->current_state->res_ctx.pipe_ctx[i]; |
| @@ -603,6 +609,8 @@ bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream, · 113 unmodified lines | ||
| 603 | 609 | if (pipe == NULL) |
| 604 | 610 | return false; |
| 605 | 611 | |
| 612 | + dc_exit_ips_for_hw_access(dc); | |
| 613 | + | |
| 606 | 614 | /* By default, capture the full frame */ |
| 607 | 615 | param.windowa_x_start = 0; |
| 608 | 616 | param.windowa_y_start = 0; |
| @@ -662,6 +670,8 @@ bool dc_stream_get_crc(struct dc *dc, struct dc_stream_state *stream, · 53 unmodified lines | ||
| 662 | 670 | struct pipe_ctx *pipe; |
| 663 | 671 | struct timing_generator *tg; |
| 664 | 672 | |
| 673 | + dc_exit_ips_for_hw_access(dc); | |
| 674 | + | |
| 665 | 675 | for (i = 0; i < MAX_PIPES; i++) { |
| 666 | 676 | pipe = &dc->current_state->res_ctx.pipe_ctx[i]; |
| 667 | 677 | if (pipe->stream == stream) |
| @@ -686,6 +696,8 @@ void dc_stream_set_dyn_expansion(struct dc *dc, struct dc_stream_state *stream, · 18 unmodified lines | ||
| 686 | 696 | int i; |
| 687 | 697 | struct pipe_ctx *pipe_ctx; |
| 688 | 698 | |
| 699 | + dc_exit_ips_for_hw_access(dc); | |
| 700 | + | |
| 689 | 701 | for (i = 0; i < MAX_PIPES; i++) { |
| 690 | 702 | if (dc->current_state->res_ctx.pipe_ctx[i].stream |
| 691 | 703 | == stream) { |
| @@ -721,6 +733,8 @@ void dc_stream_set_dither_option(struct dc_stream_state *stream, · 29 unmodified lines | ||
| 721 | 733 | if (option > DITHER_OPTION_MAX) |
| 722 | 734 | return; |
| 723 | 735 | |
| 736 | + dc_exit_ips_for_hw_access(stream->ctx->dc); | |
| 737 | + | |
| 724 | 738 | stream->dither_option = option; |
| 725 | 739 | |
| 726 | 740 | memset(¶ms, 0, sizeof(params)); |
| @@ -745,6 +759,8 @@ bool dc_stream_set_gamut_remap(struct dc *dc, const struct dc_stream_state *stre · 18 unmodified lines | ||
| 745 | 759 | bool ret = false; |
| 746 | 760 | struct pipe_ctx *pipes; |
| 747 | 761 | |
| 762 | + dc_exit_ips_for_hw_access(dc); | |
| 763 | + | |
| 748 | 764 | for (i = 0; i < MAX_PIPES; i++) { |
| 749 | 765 | if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) { |
| 750 | 766 | pipes = &dc->current_state->res_ctx.pipe_ctx[i]; |
| @@ -762,6 +778,8 @@ bool dc_stream_program_csc_matrix(struct dc *dc, struct dc_stream_state *stream) · 11 unmodified lines | ||
| 762 | 778 | bool ret = false; |
| 763 | 779 | struct pipe_ctx *pipes; |
| 764 | 780 | |
| 781 | + dc_exit_ips_for_hw_access(dc); | |
| 782 | + | |
| 765 | 783 | for (i = 0; i < MAX_PIPES; i++) { |
| 766 | 784 | if (dc->current_state->res_ctx.pipe_ctx[i].stream |
| 767 | 785 | == stream) { |
| @@ -788,6 +806,8 @@ void dc_stream_set_static_screen_params(struct dc *dc, · 20 unmodified lines | ||
| 788 | 806 | struct pipe_ctx *pipes_affected[MAX_PIPES]; |
| 789 | 807 | int num_pipes_affected = 0; |
| 790 | 808 | |
| 809 | + dc_exit_ips_for_hw_access(dc); | |
| 810 | + | |
| 791 | 811 | for (i = 0; i < num_streams; i++) { |
| 792 | 812 | struct dc_stream_state *stream = streams[i]; |
| 793 | 813 | |
| @@ -1766,6 +1786,8 @@ void dc_enable_stereo( · 972 unmodified lines | ||
| 1766 | 1786 | int i, j; |
| 1767 | 1787 | struct pipe_ctx *pipe; |
| 1768 | 1788 | |
| 1789 | + dc_exit_ips_for_hw_access(dc); | |
| 1790 | + | |
| 1769 | 1791 | for (i = 0; i < MAX_PIPES; i++) { |
| 1770 | 1792 | if (context != NULL) { |
| 1771 | 1793 | pipe = &context->res_ctx.pipe_ctx[i]; |
| @@ -1785,6 +1807,8 @@ void dc_enable_stereo( · 13 unmodified lines | ||
| 1785 | 1807 | void dc_trigger_sync(struct dc *dc, struct dc_state *context) |
| 1786 | 1808 | { |
| 1787 | 1809 | if (context->stream_count > 1 && !dc->debug.disable_timing_sync) { |
| 1810 | + dc_exit_ips_for_hw_access(dc); | |
| 1811 | + | |
| 1788 | 1812 | enable_timing_multisync(dc, context); |
| 1789 | 1813 | program_timing_sync(dc, context); |
| 1790 | 1814 | } |
| @@ -2041,6 +2065,8 @@ enum dc_status dc_commit_streams(struct dc *dc, · 250 unmodified lines | ||
| 2041 | 2065 | if (!streams_changed(dc, streams, stream_count)) |
| 2042 | 2066 | return res; |
| 2043 | 2067 | |
| 2068 | + dc_exit_ips_for_hw_access(dc); | |
| 2069 | + | |
| 2044 | 2070 | DC_LOG_DC("%s: %d streams\n", __func__, stream_count); |
| 2045 | 2071 | |
| 2046 | 2072 | for (i = 0; i < stream_count; i++) { |
| @@ -3067,6 +3093,10 @@ static bool update_planes_and_stream_state(struct dc *dc, · 1020 unmodified lines | ||
| 3067 | 3093 | |
| 3068 | 3094 | if (otg_master && otg_master->stream->test_pattern.type != DP_TEST_PATTERN_VIDEO_MODE) |
| 3069 | 3095 | resource_build_test_pattern_params(&context->res_ctx, otg_master); |
| 3096 | + | |
| 3097 | + if (otg_master && (otg_master->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422 || | |
| 3098 | + otg_master->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)) | |
| 3099 | + resource_build_subsampling_params(&context->res_ctx, otg_master); | |
| 3070 | 3100 | } |
| 3071 | 3101 | } |
| 3072 | 3102 | |
| @@ -3376,6 +3406,8 @@ static void commit_planes_for_stream_fast(struct dc *dc, · 303 unmodified lines | ||
| 3376 | 3406 | int i, j; |
| 3377 | 3407 | struct pipe_ctx *top_pipe_to_program = NULL; |
| 3378 | 3408 | struct dc_stream_status *stream_status = NULL; |
| 3409 | + dc_exit_ips_for_hw_access(dc); | |
| 3410 | + | |
| 3379 | 3411 | dc_z10_restore(dc); |
| 3380 | 3412 | |
| 3381 | 3413 | top_pipe_to_program = resource_get_otg_master_for_stream( |
| @@ -3503,10 +3535,23 @@ static void commit_planes_for_stream(struct dc *dc, · 121 unmodified lines | ||
| 3503 | 3535 | // dc->current_state anymore, so we have to cache it before we apply |
| 3504 | 3536 | // the new SubVP context |
| 3505 | 3537 | subvp_prev_use = false; |
| 3538 | + dc_exit_ips_for_hw_access(dc); | |
| 3539 | + | |
| 3506 | 3540 | dc_z10_restore(dc); |
| 3507 | 3541 | if (update_type == UPDATE_TYPE_FULL) |
| 3508 | 3542 | wait_for_outstanding_hw_updates(dc, context); |
| 3509 | 3543 | |
| 3544 | + for (i = 0; i < dc->res_pool->pipe_count; i++) { | |
| 3545 | + struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; | |
| 3546 | + | |
| 3547 | + if (pipe->stream && pipe->plane_state) { | |
| 3548 | + set_p_state_switch_method(dc, context, pipe); | |
| 3549 | + | |
| 3550 | + if (dc->debug.visual_confirm) | |
| 3551 | + dc_update_visual_confirm_color(dc, context, pipe); | |
| 3552 | + } | |
| 3553 | + } | |
| 3554 | + | |
| 3510 | 3555 | if (update_type == UPDATE_TYPE_FULL) { |
| 3511 | 3556 | dc_allow_idle_optimizations(dc, false); |
| 3512 | 3557 | |
| @@ -3541,17 +3586,6 @@ static void commit_planes_for_stream(struct dc *dc, · 28 unmodified lines | ||
| 3541 | 3586 | } |
| 3542 | 3587 | } |
| 3543 | 3588 | |
| 3544 | − for (i = 0; i < dc->res_pool->pipe_count; i++) { | |
| 3545 | − struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; | |
| 3546 | − | |
| 3547 | − if (pipe->stream && pipe->plane_state) { | |
| 3548 | − set_p_state_switch_method(dc, context, pipe); | |
| 3549 | − | |
| 3550 | − if (dc->debug.visual_confirm) | |
| 3551 | − dc_update_visual_confirm_color(dc, context, pipe); | |
| 3552 | − } | |
| 3553 | − } | |
| 3554 | − | |
| 3555 | 3589 | if (stream->test_pattern.type != DP_TEST_PATTERN_VIDEO_MODE) { |
| 3556 | 3590 | struct pipe_ctx *mpcc_pipe; |
| 3557 | 3591 | struct pipe_ctx *odm_pipe; |
| @@ -3817,7 +3851,9 @@ static void commit_planes_for_stream(struct dc *dc, · 259 unmodified lines | ||
| 3817 | 3851 | * programming has completed (we turn on phantom OTG in order |
| 3818 | 3852 | * to complete the plane disable for phantom pipes). |
| 3819 | 3853 | */ |
| 3820 | − dc->hwss.apply_ctx_to_hw(dc, context); | |
| 3854 | + | |
| 3855 | + if (dc->hwss.disable_phantom_streams) | |
| 3856 | + dc->hwss.disable_phantom_streams(dc, context); | |
| 3821 | 3857 | } |
| 3822 | 3858 | |
| 3823 | 3859 | if (update_type != UPDATE_TYPE_FAST) |
| @@ -4382,6 +4418,8 @@ bool dc_update_planes_and_stream(struct dc *dc, · 558 unmodified lines | ||
| 4382 | 4418 | bool is_plane_addition = 0; |
| 4383 | 4419 | bool is_fast_update_only; |
| 4384 | 4420 | |
| 4421 | + dc_exit_ips_for_hw_access(dc); | |
| 4422 | + | |
| 4385 | 4423 | populate_fast_updates(fast_update, srf_updates, surface_count, stream_update); |
| 4386 | 4424 | is_fast_update_only = fast_update_only(dc, fast_update, srf_updates, |
| 4387 | 4425 | surface_count, stream_update, stream); |
| @@ -4502,6 +4540,8 @@ void dc_commit_updates_for_stream(struct dc *dc, · 114 unmodified lines | ||
| 4502 | 4540 | int i, j; |
| 4503 | 4541 | struct dc_fast_update fast_update[MAX_SURFACES] = {0}; |
| 4504 | 4542 | |
| 4543 | + dc_exit_ips_for_hw_access(dc); | |
| 4544 | + | |
| 4505 | 4545 | populate_fast_updates(fast_update, srf_updates, surface_count, stream_update); |
| 4506 | 4546 | stream_status = dc_stream_get_status(stream); |
| 4507 | 4547 | context = dc->current_state; |
| @@ -4686,6 +4726,8 @@ void dc_set_power_state( · 178 unmodified lines | ||
| 4686 | 4726 | case DC_ACPI_CM_POWER_STATE_D0: |
| 4687 | 4727 | dc_state_construct(dc, dc->current_state); |
| 4688 | 4728 | |
| 4729 | + dc_exit_ips_for_hw_access(dc); | |
| 4730 | + | |
| 4689 | 4731 | dc_z10_restore(dc); |
| 4690 | 4732 | |
| 4691 | 4733 | dc->hwss.init_hw(dc); |
| @@ -4827,6 +4869,12 @@ void dc_allow_idle_optimizations(struct dc *dc, bool allow) · 135 unmodified lines | ||
| 4827 | 4869 | dc->idle_optimizations_allowed = allow; |
| 4828 | 4870 | } |
| 4829 | 4871 | |
| 4872 | +void dc_exit_ips_for_hw_access(struct dc *dc) | |
| 4873 | +{ | |
| 4874 | + if (dc->caps.ips_support) | |
| 4875 | + dc_allow_idle_optimizations(dc, false); | |
| 4876 | +} | |
| 4877 | + | |
| 4830 | 4878 | bool dc_dmub_is_ips_idle_state(struct dc *dc) |
| 4831 | 4879 | { |
| 4832 | 4880 | uint32_t idle_state = 0; |
| @@ -822,6 +822,16 @@ static struct rect calculate_odm_slice_in_timing_active(struct pipe_ctx *pipe_ct · 821 unmodified lines | ||
| 822 | 822 | stream->timing.v_border_bottom + |
| 823 | 823 | stream->timing.v_border_top; |
| 824 | 824 | |
| 825 | + /* Recout for ODM slices after the first slice need one extra left edge pixel | |
| 826 | + * for 3-tap chroma subsampling. | |
| 827 | + */ | |
| 828 | + if (odm_slice_idx > 0 && | |
| 829 | + (pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422 || | |
| 830 | + pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)) { | |
| 831 | + odm_rec.x -= 1; | |
| 832 | + odm_rec.width += 1; | |
| 833 | + } | |
| 834 | + | |
| 825 | 835 | return odm_rec; |
| 826 | 836 | } |
| 827 | 837 | |
| @@ -1438,6 +1448,7 @@ void resource_build_test_pattern_params(struct resource_context *res_ctx, · 610 unmodified lines | ||
| 1438 | 1448 | enum controller_dp_test_pattern controller_test_pattern; |
| 1439 | 1449 | enum controller_dp_color_space controller_color_space; |
| 1440 | 1450 | enum dc_color_depth color_depth = otg_master->stream->timing.display_color_depth; |
| 1451 | + enum dc_pixel_encoding pixel_encoding = otg_master->stream->timing.pixel_encoding; | |
| 1441 | 1452 | int h_active = otg_master->stream->timing.h_addressable + |
| 1442 | 1453 | otg_master->stream->timing.h_border_left + |
| 1443 | 1454 | otg_master->stream->timing.h_border_right; |
| @@ -1469,10 +1480,36 @@ void resource_build_test_pattern_params(struct resource_context *res_ctx, · 25 unmodified lines | ||
| 1469 | 1480 | else |
| 1470 | 1481 | params->width = last_odm_slice_width; |
| 1471 | 1482 | |
| 1483 | + /* Extra left edge pixel is required for 3-tap chroma subsampling. */ | |
| 1484 | + if (i != 0 && (pixel_encoding == PIXEL_ENCODING_YCBCR422 || | |
| 1485 | + pixel_encoding == PIXEL_ENCODING_YCBCR420)) { | |
| 1486 | + params->offset -= 1; | |
| 1487 | + params->width += 1; | |
| 1488 | + } | |
| 1489 | + | |
| 1472 | 1490 | offset += odm_slice_width; |
| 1473 | 1491 | } |
| 1474 | 1492 | } |
| 1475 | 1493 | |
| 1494 | +void resource_build_subsampling_params(struct resource_context *res_ctx, | |
| 1495 | + struct pipe_ctx *otg_master) | |
| 1496 | +{ | |
| 1497 | + struct pipe_ctx *opp_heads[MAX_PIPES]; | |
| 1498 | + int odm_cnt = 1; | |
| 1499 | + int i; | |
| 1500 | + | |
| 1501 | + odm_cnt = resource_get_opp_heads_for_otg_master(otg_master, res_ctx, opp_heads); | |
| 1502 | + | |
| 1503 | + /* For ODM slices after the first slice, extra left edge pixel is required | |
| 1504 | + * for 3-tap chroma subsampling. | |
| 1505 | + */ | |
| 1506 | + if (otg_master->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422 || | |
| 1507 | + otg_master->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) { | |
| 1508 | + for (i = 0; i < odm_cnt; i++) | |
| 1509 | + opp_heads[i]->stream_res.left_edge_extra_pixel = (i == 0) ? false : true; | |
| 1510 | + } | |
| 1511 | +} | |
| 1512 | + | |
| 1476 | 1513 | bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) |
| 1477 | 1514 | { |
| 1478 | 1515 | const struct dc_plane_state *plane_state = pipe_ctx->plane_state; |
| @@ -1834,23 +1871,6 @@ int resource_find_any_free_pipe(struct resource_context *new_res_ctx, · 355 unmodified lines | ||
| 1834 | 1871 | |
| 1835 | 1872 | bool resource_is_pipe_type(const struct pipe_ctx *pipe_ctx, enum pipe_type type) |
| 1836 | 1873 | { |
| 1837 | −#ifdef DBG | |
| 1838 | − if (pipe_ctx->stream == NULL) { | |
| 1839 | − /* a free pipe with dangling states */ | |
| 1840 | − ASSERT(!pipe_ctx->plane_state); | |
| 1841 | − ASSERT(!pipe_ctx->prev_odm_pipe); | |
| 1842 | − ASSERT(!pipe_ctx->next_odm_pipe); | |
| 1843 | − ASSERT(!pipe_ctx->top_pipe); | |
| 1844 | − ASSERT(!pipe_ctx->bottom_pipe); | |
| 1845 | − } else if (pipe_ctx->top_pipe) { | |
| 1846 | − /* a secondary DPP pipe must be signed to a plane */ | |
| 1847 | − ASSERT(pipe_ctx->plane_state) | |
| 1848 | − } | |
| 1849 | − /* Add more checks here to prevent corrupted pipe ctx. It is very hard | |
| 1850 | − * to debug this issue afterwards because we can't pinpoint the code | |
| 1851 | − * location causing inconsistent pipe context states. | |
| 1852 | − */ | |
| 1853 | −#endif | |
| 1854 | 1874 | switch (type) { |
| 1855 | 1875 | case OTG_MASTER: |
| 1856 | 1876 | return !pipe_ctx->prev_odm_pipe && |
| @@ -291,11 +291,14 @@ void dc_state_destruct(struct dc_state *state) · 290 unmodified lines | ||
| 291 | 291 | dc_stream_release(state->phantom_streams[i]); |
| 292 | 292 | state->phantom_streams[i] = NULL; |
| 293 | 293 | } |
| 294 | + state->phantom_stream_count = 0; | |
| 294 | 295 | |
| 295 | 296 | for (i = 0; i < state->phantom_plane_count; i++) { |
| 296 | 297 | dc_plane_state_release(state->phantom_planes[i]); |
| 297 | 298 | state->phantom_planes[i] = NULL; |
| 298 | 299 | } |
| 300 | + state->phantom_plane_count = 0; | |
| 301 | + | |
| 299 | 302 | state->stream_mask = 0; |
| 300 | 303 | memset(&state->res_ctx, 0, sizeof(state->res_ctx)); |
| 301 | 304 | memset(&state->pp_display_cfg, 0, sizeof(state->pp_display_cfg)); |
| @@ -423,6 +423,8 @@ bool dc_stream_add_writeback(struct dc *dc, · 422 unmodified lines | ||
| 423 | 423 | return false; |
| 424 | 424 | } |
| 425 | 425 | |
| 426 | + dc_exit_ips_for_hw_access(dc); | |
| 427 | + | |
| 426 | 428 | wb_info->dwb_params.out_transfer_func = stream->out_transfer_func; |
| 427 | 429 | |
| 428 | 430 | dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; |
| @@ -493,6 +495,8 @@ bool dc_stream_fc_disable_writeback(struct dc *dc, · 64 unmodified lines | ||
| 493 | 495 | return false; |
| 494 | 496 | } |
| 495 | 497 | |
| 498 | + dc_exit_ips_for_hw_access(dc); | |
| 499 | + | |
| 496 | 500 | if (dwb->funcs->set_fc_enable) |
| 497 | 501 | dwb->funcs->set_fc_enable(dwb, DWB_FRAME_CAPTURE_DISABLE); |
| 498 | 502 | |
| @@ -542,6 +546,8 @@ bool dc_stream_remove_writeback(struct dc *dc, · 43 unmodified lines | ||
| 542 | 546 | return false; |
| 543 | 547 | } |
| 544 | 548 | |
| 549 | + dc_exit_ips_for_hw_access(dc); | |
| 550 | + | |
| 545 | 551 | /* disable writeback */ |
| 546 | 552 | if (dc->hwss.disable_writeback) { |
| 547 | 553 | struct dwbc *dwb = dc->res_pool->dwbc[dwb_pipe_inst]; |
| @@ -557,6 +563,8 @@ bool dc_stream_warmup_writeback(struct dc *dc, · 9 unmodified lines | ||
| 557 | 563 | int num_dwb, |
| 558 | 564 | struct dc_writeback_info *wb_info) |
| 559 | 565 | { |
| 566 | + dc_exit_ips_for_hw_access(dc); | |
| 567 | + | |
| 560 | 568 | if (dc->hwss.mmhubbub_warmup) |
| 561 | 569 | return dc->hwss.mmhubbub_warmup(dc, num_dwb, wb_info); |
| 562 | 570 | else |
| @@ -569,6 +577,8 @@ uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream) · 6 unmodified lines | ||
| 569 | 577 | struct resource_context *res_ctx = |
| 570 | 578 | &dc->current_state->res_ctx; |
| 571 | 579 | |
| 580 | + dc_exit_ips_for_hw_access(dc); | |
| 581 | + | |
| 572 | 582 | for (i = 0; i < MAX_PIPES; i++) { |
| 573 | 583 | struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg; |
| 574 | 584 | |
| @@ -597,6 +607,8 @@ bool dc_stream_send_dp_sdp(const struct dc_stream_state *stream, · 22 unmodified lines | ||
| 597 | 607 | dc = stream->ctx->dc; |
| 598 | 608 | res_ctx = &dc->current_state->res_ctx; |
| 599 | 609 | |
| 610 | + dc_exit_ips_for_hw_access(dc); | |
| 611 | + | |
| 600 | 612 | for (i = 0; i < MAX_PIPES; i++) { |
| 601 | 613 | struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; |
| 602 | 614 | |
| @@ -628,6 +640,8 @@ bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream, · 25 unmodified lines | ||
| 628 | 640 | struct resource_context *res_ctx = |
| 629 | 641 | &dc->current_state->res_ctx; |
| 630 | 642 | |
| 643 | + dc_exit_ips_for_hw_access(dc); | |
| 644 | + | |
| 631 | 645 | for (i = 0; i < MAX_PIPES; i++) { |
| 632 | 646 | struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg; |
| 633 | 647 | |
| @@ -664,6 +678,8 @@ bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream) · 30 unmodified lines | ||
| 664 | 678 | if (i == MAX_PIPES) |
| 665 | 679 | return true; |
| 666 | 680 | |
| 681 | + dc_exit_ips_for_hw_access(dc); | |
| 682 | + | |
| 667 | 683 | return dc->hwss.dmdata_status_done(pipe); |
| 668 | 684 | } |
| 669 | 685 | |
| @@ -698,6 +714,8 @@ bool dc_stream_set_dynamic_metadata(struct dc *dc, · 28 unmodified lines | ||
| 698 | 714 | |
| 699 | 715 | pipe_ctx->stream->dmdata_address = attr->address; |
| 700 | 716 | |
| 717 | + dc_exit_ips_for_hw_access(dc); | |
| 718 | + | |
| 701 | 719 | dc->hwss.program_dmdata_engine(pipe_ctx); |
| 702 | 720 | |
| 703 | 721 | if (hubp->funcs->dmdata_set_attributes != NULL && |
| @@ -161,6 +161,8 @@ const struct dc_plane_status *dc_plane_get_status( · 160 unmodified lines | ||
| 161 | 161 | break; |
| 162 | 162 | } |
| 163 | 163 | |
| 164 | + dc_exit_ips_for_hw_access(dc); | |
| 165 | + | |
| 164 | 166 | for (i = 0; i < dc->res_pool->pipe_count; i++) { |
| 165 | 167 | struct pipe_ctx *pipe_ctx = |
| 166 | 168 | &dc->current_state->res_ctx.pipe_ctx[i]; |
| @@ -51,7 +51,7 @@ struct aux_payload; · 50 unmodified lines | ||
| 51 | 51 | struct set_config_cmd_payload; |
| 52 | 52 | struct dmub_notification; |
| 53 | 53 | |
| 54 | −#define DC_VER "3.2.266" | |
| 54 | +#define DC_VER "3.2.271" | |
| 55 | 55 | |
| 56 | 56 | #define MAX_SURFACES 3 |
| 57 | 57 | #define MAX_PLANES 6 |
| @@ -429,11 +429,12 @@ struct dc_config { · 371 unmodified lines | ||
| 429 | 429 | bool force_bios_enable_lttpr; |
| 430 | 430 | uint8_t force_bios_fixed_vs; |
| 431 | 431 | int sdpif_request_limit_words_per_umc; |
| 432 | − bool use_old_fixed_vs_sequence; | |
| 433 | 432 | bool dc_mode_clk_limit_support; |
| 434 | 433 | bool EnableMinDispClkODM; |
| 435 | 434 | bool enable_auto_dpm_test_logs; |
| 436 | 435 | unsigned int disable_ips; |
| 436 | + unsigned int disable_ips_in_vpb; | |
| 437 | + bool usb4_bw_alloc_support; | |
| 437 | 438 | }; |
| 438 | 439 | |
| 439 | 440 | enum visual_confirm { |
| @@ -986,9 +987,11 @@ struct dc_debug_options { · 546 unmodified lines | ||
| 986 | 987 | bool psp_disabled_wa; |
| 987 | 988 | unsigned int ips2_eval_delay_us; |
| 988 | 989 | unsigned int ips2_entry_delay_us; |
| 990 | + bool disable_dmub_reallow_idle; | |
| 989 | 991 | bool disable_timeout; |
| 990 | 992 | bool disable_extblankadj; |
| 991 | 993 | unsigned int static_screen_wait_frames; |
| 994 | + bool force_chroma_subsampling_1tap; | |
| 992 | 995 | }; |
| 993 | 996 | |
| 994 | 997 | struct gpu_info_soc_bounding_box_v1_0; |
| @@ -1067,6 +1070,7 @@ struct dc { · 72 unmodified lines | ||
| 1067 | 1070 | } scratch; |
| 1068 | 1071 | |
| 1069 | 1072 | struct dml2_configuration_options dml2_options; |
| 1073 | + enum dc_acpi_cm_power_state power_state; | |
| 1070 | 1074 | }; |
| 1071 | 1075 | |
| 1072 | 1076 | enum frame_buffer_mode { |
| @@ -2218,11 +2222,9 @@ struct dc_sink_dsc_caps { · 1145 unmodified lines | ||
| 2218 | 2222 | // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), |
| 2219 | 2223 | // 'false' if they are sink's DSC caps |
| 2220 | 2224 | bool is_virtual_dpcd_dsc; |
| 2221 | −#if defined(CONFIG_DRM_AMD_DC_FP) | |
| 2222 | 2225 | // 'true' if MST topology supports DSC passthrough for sink |
| 2223 | 2226 | // 'false' if MST topology does not support DSC passthrough |
| 2224 | 2227 | bool is_dsc_passthrough_supported; |
| 2225 | −#endif | |
| 2226 | 2228 | struct dsc_dec_dpcd_caps dsc_dec_caps; |
| 2227 | 2229 | }; |
| 2228 | 2230 | |
| @@ -2324,6 +2326,7 @@ bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_ · 95 unmodified lines | ||
| 2324 | 2326 | struct dc_cursor_attributes *cursor_attr); |
| 2325 | 2327 | |
| 2326 | 2328 | void dc_allow_idle_optimizations(struct dc *dc, bool allow); |
| 2329 | +void dc_exit_ips_for_hw_access(struct dc *dc); | |
| 2327 | 2330 | bool dc_dmub_is_ips_idle_state(struct dc *dc); |
| 2328 | 2331 | |
| 2329 | 2332 | /* set min and max memory clock to lowest and highest DPM level, respectively */ |
| @@ -74,7 +74,10 @@ void dc_dmub_srv_wait_idle(struct dc_dmub_srv *dc_dmub_srv) · 73 unmodified lines | ||
| 74 | 74 | struct dc_context *dc_ctx = dc_dmub_srv->ctx; |
| 75 | 75 | enum dmub_status status; |
| 76 | 76 | |
| 77 | − status = dmub_srv_wait_for_idle(dmub, 100000); | |
| 77 | + do { | |
| 78 | + status = dmub_srv_wait_for_idle(dmub, 100000); | |
| 79 | + } while (dc_dmub_srv->ctx->dc->debug.disable_timeout && status != DMUB_STATUS_OK); | |
| 80 | + | |
| 78 | 81 | if (status != DMUB_STATUS_OK) { |
| 79 | 82 | DC_ERROR("Error waiting for DMUB idle: status=%d\n", status); |
| 80 | 83 | dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); |
| @@ -145,7 +148,9 @@ bool dc_dmub_srv_cmd_list_queue_execute(struct dc_dmub_srv *dc_dmub_srv, · 64 unmodified lines | ||
| 145 | 148 | if (status == DMUB_STATUS_POWER_STATE_D3) |
| 146 | 149 | return false; |
| 147 | 150 | |
| 148 | − dmub_srv_wait_for_idle(dmub, 100000); | |
| 151 | + do { | |
| 152 | + status = dmub_srv_wait_for_idle(dmub, 100000); | |
| 153 | + } while (dc_dmub_srv->ctx->dc->debug.disable_timeout && status != DMUB_STATUS_OK); | |
| 149 | 154 | |
| 150 | 155 | /* Requeue the command. */ |
| 151 | 156 | status = dmub_srv_cmd_queue(dmub, &cmd_list[i]); |
| @@ -186,7 +191,9 @@ bool dc_dmub_srv_wait_for_idle(struct dc_dmub_srv *dc_dmub_srv, · 34 unmodified lines | ||
| 186 | 191 | |
| 187 | 192 | // Wait for DMUB to process command |
| 188 | 193 | if (wait_type != DM_DMUB_WAIT_TYPE_NO_WAIT) { |
| 189 | − status = dmub_srv_wait_for_idle(dmub, 100000); | |
| 194 | + do { | |
| 195 | + status = dmub_srv_wait_for_idle(dmub, 100000); | |
| 196 | + } while (dc_dmub_srv->ctx->dc->debug.disable_timeout && status != DMUB_STATUS_OK); | |
| 190 | 197 | |
| 191 | 198 | if (status != DMUB_STATUS_OK) { |
| 192 | 199 | DC_LOG_DEBUG("No reply for DMUB command: status=%d\n", status); |
| @@ -780,21 +787,22 @@ static void populate_subvp_cmd_pipe_info(struct dc *dc, · 587 unmodified lines | ||
| 780 | 787 | } else if (subvp_pipe->next_odm_pipe) { |
| 781 | 788 | pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->next_odm_pipe->pipe_idx; |
| 782 | 789 | } else { |
| 783 | − pipe_data->pipe_config.subvp_data.main_split_pipe_index = 0; | |
| 790 | + pipe_data->pipe_config.subvp_data.main_split_pipe_index = 0xF; | |
| 784 | 791 | } |
| 785 | 792 | |
| 786 | 793 | // Find phantom pipe index based on phantom stream |
| 787 | 794 | for (j = 0; j < dc->res_pool->pipe_count; j++) { |
| 788 | 795 | struct pipe_ctx *phantom_pipe = &context->res_ctx.pipe_ctx[j]; |
| 789 | 796 | |
| 790 | − if (phantom_pipe->stream == dc_state_get_paired_subvp_stream(context, subvp_pipe->stream)) { | |
| 797 | + if (resource_is_pipe_type(phantom_pipe, OTG_MASTER) && | |
| 798 | + phantom_pipe->stream == dc_state_get_paired_subvp_stream(context, subvp_pipe->stream)) { | |
| 791 | 799 | pipe_data->pipe_config.subvp_data.phantom_pipe_index = phantom_pipe->stream_res.tg->inst; |
| 792 | 800 | if (phantom_pipe->bottom_pipe) { |
| 793 | 801 | pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->bottom_pipe->plane_res.hubp->inst; |
| 794 | 802 | } else if (phantom_pipe->next_odm_pipe) { |
| 795 | 803 | pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->next_odm_pipe->plane_res.hubp->inst; |
| 796 | 804 | } else { |
| 797 | − pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = 0; | |
| 805 | + pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = 0xF; | |
| 798 | 806 | } |
| 799 | 807 | break; |
| 800 | 808 | } |
| @@ -1195,6 +1203,9 @@ static void dc_dmub_srv_notify_idle(const struct dc *dc, bool allow_idle) · 394 unmodified lines | ||
| 1195 | 1203 | if (dc->debug.dmcub_emulation) |
| 1196 | 1204 | return; |
| 1197 | 1205 | |
| 1206 | + if (!dc->ctx->dmub_srv || !dc->ctx->dmub_srv->dmub) | |
| 1207 | + return; | |
| 1208 | + | |
| 1198 | 1209 | memset(&cmd, 0, sizeof(cmd)); |
| 1199 | 1210 | cmd.idle_opt_notify_idle.header.type = DMUB_CMD__IDLE_OPT; |
| 1200 | 1211 | cmd.idle_opt_notify_idle.header.sub_type = DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE; |
| @@ -1205,13 +1216,15 @@ static void dc_dmub_srv_notify_idle(const struct dc *dc, bool allow_idle) · 4 unmodified lines | ||
| 1205 | 1216 | cmd.idle_opt_notify_idle.cntl_data.driver_idle = allow_idle; |
| 1206 | 1217 | |
| 1207 | 1218 | if (allow_idle) { |
| 1219 | + dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); | |
| 1220 | + | |
| 1208 | 1221 | if (dc->hwss.set_idle_state) |
| 1209 | 1222 | dc->hwss.set_idle_state(dc, true); |
| 1210 | 1223 | } |
| 1211 | 1224 | |
| 1212 | 1225 | /* NOTE: This does not use the "wake" interface since this is part of the wake path. */ |
| 1213 | 1226 | /* We also do not perform a wait since DMCUB could enter idle after the notification. */ |
| 1214 | − dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT); | |
| 1227 | + dm_execute_dmub_cmd(dc->ctx, &cmd, allow_idle ? DM_DMUB_WAIT_TYPE_NO_WAIT : DM_DMUB_WAIT_TYPE_WAIT); | |
| 1215 | 1228 | } |
| 1216 | 1229 | |
| 1217 | 1230 | static void dc_dmub_srv_exit_low_power_state(const struct dc *dc) |
| @@ -1361,7 +1374,7 @@ bool dc_wake_and_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned in · 143 unmodified lines | ||
| 1361 | 1374 | else |
| 1362 | 1375 | result = dm_execute_dmub_cmd(ctx, cmd, wait_type); |
| 1363 | 1376 | |
| 1364 | − if (result && reallow_idle) | |
| 1377 | + if (result && reallow_idle && !ctx->dc->debug.disable_dmub_reallow_idle) | |
| 1365 | 1378 | dc_dmub_srv_apply_idle_power_optimizations(ctx->dc, true); |
| 1366 | 1379 | |
| 1367 | 1380 | return result; |
| @@ -1410,7 +1423,7 @@ bool dc_wake_and_execute_gpint(const struct dc_context *ctx, enum dmub_gpint_com · 42 unmodified lines | ||
| 1410 | 1423 | |
| 1411 | 1424 | result = dc_dmub_execute_gpint(ctx, command_code, param, response, wait_type); |
| 1412 | 1425 | |
| 1413 | − if (result && reallow_idle) | |
| 1426 | + if (result && reallow_idle && !ctx->dc->debug.disable_dmub_reallow_idle) | |
| 1414 | 1427 | dc_dmub_srv_apply_idle_power_optimizations(ctx->dc, true); |
| 1415 | 1428 | |
| 1416 | 1429 | return result; |
| @@ -827,9 +827,7 @@ struct dc_dsc_config { · 826 unmodified lines | ||
| 827 | 827 | uint32_t version_minor; /* DSC minor version. Full version is formed as 1.version_minor. */ |
| 828 | 828 | bool ycbcr422_simple; /* Tell DSC engine to convert YCbCr 4:2:2 to 'YCbCr 4:2:2 simple'. */ |
| 829 | 829 | int32_t rc_buffer_size; /* DSC RC buffer block size in bytes */ |
| 830 | −#if defined(CONFIG_DRM_AMD_DC_FP) | |
| 831 | 830 | bool is_frl; /* indicate if DSC is applied based on HDMI FRL sink's capability */ |
| 832 | −#endif | |
| 833 | 831 | bool is_dp; /* indicate if DSC is applied based on DP's capability */ |
| 834 | 832 | uint32_t mst_pbn; /* pbn of display on dsc mst hub */ |
| 835 | 833 | const struct dc_dsc_rc_params_override *rc_params_ovrd; /* DM owned memory. If not NULL, apply custom dsc rc params */ |
| @@ -942,6 +940,7 @@ struct dc_crtc_timing { · 106 unmodified lines | ||
| 942 | 940 | uint32_t hdmi_vic; |
| 943 | 941 | uint32_t rid; |
| 944 | 942 | uint32_t fr_index; |
| 943 | + uint32_t frl_uncompressed_video_bandwidth_in_kbps; | |
| 945 | 944 | enum dc_timing_3d_format timing_3d_format; |
| 946 | 945 | enum dc_color_depth display_color_depth; |
| 947 | 946 | enum dc_pixel_encoding pixel_encoding; |
| @@ -1034,6 +1034,7 @@ enum replay_FW_Message_type { · 1033 unmodified lines | ||
| 1034 | 1034 | Replay_Msg_Not_Support = -1, |
| 1035 | 1035 | Replay_Set_Timing_Sync_Supported, |
| 1036 | 1036 | Replay_Set_Residency_Frameupdate_Timer, |
| 1037 | + Replay_Set_Pseudo_VTotal, | |
| 1037 | 1038 | }; |
| 1038 | 1039 | |
| 1039 | 1040 | union replay_error_status { |
| @@ -1089,6 +1090,10 @@ struct replay_settings { · 49 unmodified lines | ||
| 1089 | 1090 | uint16_t coasting_vtotal_table[PR_COASTING_TYPE_NUM]; |
| 1090 | 1091 | /* Maximum link off frame count */ |
| 1091 | 1092 | enum replay_link_off_frame_count_level link_off_frame_count_level; |
| 1093 | + /* Replay pseudo vtotal for abm + ips on full screen video which can improve ips residency */ | |
| 1094 | + uint16_t abm_with_ips_on_full_screen_video_pseudo_vtotal; | |
| 1095 | + /* Replay last pseudo vtotal set to DMUB */ | |
| 1096 | + uint16_t last_pseudo_vtotal; | |
| 1092 | 1097 | }; |
| 1093 | 1098 | |
| 1094 | 1099 | /* To split out "global" and "per-panel" config settings. |
| @@ -239,27 +239,294 @@ static void check_audio_bandwidth_hdmi( · 238 unmodified lines | ||
| 239 | 239 | } |
| 240 | 240 | } |
| 241 | 241 | } |
| 242 | +static struct fixed31_32 get_link_symbol_clk_freq_mhz(enum dc_link_rate link_rate) | |
| 243 | +{ | |
| 244 | + switch (link_rate) { | |
| 245 | + case LINK_RATE_LOW: | |
| 246 | + return dc_fixpt_from_int(162); /* 162 MHz */ | |
| 247 | + case LINK_RATE_HIGH: | |
| 248 | + return dc_fixpt_from_int(270); /* 270 MHz */ | |
| 249 | + case LINK_RATE_HIGH2: | |
| 250 | + return dc_fixpt_from_int(540); /* 540 MHz */ | |
| 251 | + case LINK_RATE_HIGH3: | |
| 252 | + return dc_fixpt_from_int(810); /* 810 MHz */ | |
| 253 | + case LINK_RATE_UHBR10: | |
| 254 | + return dc_fixpt_from_fraction(3125, 10); /* 312.5 MHz */ | |
| 255 | + case LINK_RATE_UHBR13_5: | |
| 256 | + return dc_fixpt_from_fraction(421875, 1000); /* 421.875 MHz */ | |
| 257 | + case LINK_RATE_UHBR20: | |
| 258 | + return dc_fixpt_from_int(625); /* 625 MHz */ | |
| 259 | + default: | |
| 260 | + /* Unexpected case, this requires debug if encountered. */ | |
| 261 | + ASSERT(0); | |
| 262 | + return dc_fixpt_from_int(0); | |
| 263 | + } | |
| 264 | +} | |
| 265 | + | |
| 266 | +struct dp_audio_layout_config { | |
| 267 | + uint8_t layouts_per_sample_denom; | |
| 268 | + uint8_t symbols_per_layout; | |
| 269 | + uint8_t max_layouts_per_audio_sdp; | |
| 270 | +}; | |
| 271 | + | |
| 272 | +static void get_audio_layout_config( | |
| 273 | + uint32_t channel_count, | |
| 274 | + enum dp_link_encoding encoding, | |
| 275 | + struct dp_audio_layout_config *output) | |
| 276 | +{ | |
| 277 | + /* Assuming L-PCM audio. Current implementation uses max 1 layout per SDP, | |
| 278 | + * with each layout being the same size (8ch layout). | |
| 279 | + */ | |
| 280 | + if (encoding == DP_8b_10b_ENCODING) { | |
| 281 | + if (channel_count == 2) { | |
| 282 | + output->layouts_per_sample_denom = 4; | |
| 283 | + output->symbols_per_layout = 40; | |
| 284 | + output->max_layouts_per_audio_sdp = 1; | |
| 285 | + } else if (channel_count == 8 || channel_count == 6) { | |
| 286 | + output->layouts_per_sample_denom = 1; | |
| 287 | + output->symbols_per_layout = 40; | |
| 288 | + output->max_layouts_per_audio_sdp = 1; | |
| 289 | + } | |
| 290 | + } else if (encoding == DP_128b_132b_ENCODING) { | |
| 291 | + if (channel_count == 2) { | |
| 292 | + output->layouts_per_sample_denom = 4; | |
| 293 | + output->symbols_per_layout = 10; | |
| 294 | + output->max_layouts_per_audio_sdp = 1; | |
| 295 | + } else if (channel_count == 8 || channel_count == 6) { | |
| 296 | + output->layouts_per_sample_denom = 1; | |
| 297 | + output->symbols_per_layout = 10; | |
| 298 | + output->max_layouts_per_audio_sdp = 1; | |
| 299 | + } | |
| 300 | + } | |
| 301 | +} | |
| 242 | 302 | |
| 243 | −/*For DP SST, calculate if specified sample rates can fit into a given timing */ | |
| 244 | −static void check_audio_bandwidth_dpsst( | |
| 303 | +static uint32_t get_av_stream_map_lane_count( | |
| 304 | + enum dp_link_encoding encoding, | |
| 305 | + enum dc_lane_count lane_count, | |
| 306 | + bool is_mst) | |
| 307 | +{ | |
| 308 | + uint32_t av_stream_map_lane_count = 0; | |
| 309 | + | |
| 310 | + if (encoding == DP_8b_10b_ENCODING) { | |
| 311 | + if (!is_mst) | |
| 312 | + av_stream_map_lane_count = lane_count; | |
| 313 | + else | |
| 314 | + av_stream_map_lane_count = 4; | |
| 315 | + } else if (encoding == DP_128b_132b_ENCODING) { | |
| 316 | + av_stream_map_lane_count = 4; | |
| 317 | + } | |
| 318 | + | |
| 319 | + ASSERT(av_stream_map_lane_count != 0); | |
| 320 | + | |
| 321 | + return av_stream_map_lane_count; | |
| 322 | +} | |
| 323 | + | |
| 324 | +static uint32_t get_audio_sdp_overhead( | |
| 325 | + enum dp_link_encoding encoding, | |
| 326 | + enum dc_lane_count lane_count, | |
| 327 | + bool is_mst) | |
| 328 | +{ | |
| 329 | + uint32_t audio_sdp_overhead = 0; | |
| 330 | + | |
| 331 | + if (encoding == DP_8b_10b_ENCODING) { | |
| 332 | + if (is_mst) | |
| 333 | + audio_sdp_overhead = 16; /* 4 * 2 + 8 */ | |
| 334 | + else | |
| 335 | + audio_sdp_overhead = lane_count * 2 + 8; | |
| 336 | + } else if (encoding == DP_128b_132b_ENCODING) { | |
| 337 | + audio_sdp_overhead = 10; /* 4 x 2.5 */ | |
| 338 | + } | |
| 339 | + | |
| 340 | + ASSERT(audio_sdp_overhead != 0); | |
| 341 | + | |
| 342 | + return audio_sdp_overhead; | |
| 343 | +} | |
| 344 | + | |
| 345 | +static uint32_t calculate_required_audio_bw_in_symbols( | |
| 245 | 346 | const struct audio_crtc_info *crtc_info, |
| 347 | + const struct dp_audio_layout_config *layout_config, | |
| 246 | 348 | uint32_t channel_count, |
| 247 | − union audio_sample_rates *sample_rates) | |
| 349 | + uint32_t sample_rate_hz, | |
| 350 | + uint32_t av_stream_map_lane_count, | |
| 351 | + uint32_t audio_sdp_overhead) | |
| 352 | +{ | |
| 353 | + /* DP spec recommends between 1.05 to 1.1 safety margin to prevent sample under-run */ | |
| 354 | + struct fixed31_32 audio_sdp_margin = dc_fixpt_from_fraction(110, 100); | |
| 355 | + struct fixed31_32 horizontal_line_freq_khz = dc_fixpt_from_fraction( | |
| 356 | + crtc_info->requested_pixel_clock_100Hz, crtc_info->h_total * 10); | |
| 357 | + struct fixed31_32 samples_per_line; | |
| 358 | + struct fixed31_32 layouts_per_line; | |
| 359 | + struct fixed31_32 symbols_per_sdp_max_layout; | |
| 360 | + struct fixed31_32 remainder; | |
| 361 | + uint32_t num_sdp_with_max_layouts; | |
| 362 | + uint32_t required_symbols_per_hblank; | |
| 363 | + | |
| 364 | + samples_per_line = dc_fixpt_from_fraction(sample_rate_hz, 1000); | |
| 365 | + samples_per_line = dc_fixpt_div(samples_per_line, horizontal_line_freq_khz); | |
| 366 | + layouts_per_line = dc_fixpt_div_int(samples_per_line, layout_config->layouts_per_sample_denom); | |
| 367 | + | |
| 368 | + num_sdp_with_max_layouts = dc_fixpt_floor( | |
| 369 | + dc_fixpt_div_int(layouts_per_line, layout_config->max_layouts_per_audio_sdp)); | |
| 370 | + symbols_per_sdp_max_layout = dc_fixpt_from_int( | |
| 371 | + layout_config->max_layouts_per_audio_sdp * layout_config->symbols_per_layout); | |
| 372 | + symbols_per_sdp_max_layout = dc_fixpt_add_int(symbols_per_sdp_max_layout, audio_sdp_overhead); | |
| 373 | + symbols_per_sdp_max_layout = dc_fixpt_mul(symbols_per_sdp_max_layout, audio_sdp_margin); | |
| 374 | + required_symbols_per_hblank = num_sdp_with_max_layouts; | |
| 375 | + required_symbols_per_hblank *= ((dc_fixpt_ceil(symbols_per_sdp_max_layout) + av_stream_map_lane_count) / | |
| 376 | + av_stream_map_lane_count) * av_stream_map_lane_count; | |
| 377 | + | |
| 378 | + if (num_sdp_with_max_layouts != dc_fixpt_ceil( | |
| 379 | + dc_fixpt_div_int(layouts_per_line, layout_config->max_layouts_per_audio_sdp))) { | |
| 380 | + remainder = dc_fixpt_sub_int(layouts_per_line, | |
| 381 | + num_sdp_with_max_layouts * layout_config->max_layouts_per_audio_sdp); | |
| 382 | + remainder = dc_fixpt_mul_int(remainder, layout_config->symbols_per_layout); | |
| 383 | + remainder = dc_fixpt_add_int(remainder, audio_sdp_overhead); | |
| 384 | + remainder = dc_fixpt_mul(remainder, audio_sdp_margin); | |
| 385 | + required_symbols_per_hblank += ((dc_fixpt_ceil(remainder) + av_stream_map_lane_count) / | |
| 386 | + av_stream_map_lane_count) * av_stream_map_lane_count; | |
| 387 | + } | |
| 388 | + | |
| 389 | + return required_symbols_per_hblank; | |
| 390 | +} | |
| 391 | + | |
| 392 | +/* Current calculation only applicable for 8b/10b MST and 128b/132b SST/MST. | |
| 393 | + */ | |
| 394 | +static uint32_t calculate_available_hblank_bw_in_symbols( | |
| 395 | + const struct audio_crtc_info *crtc_info, | |
| 396 | + const struct audio_dp_link_info *dp_link_info) | |
| 248 | 397 | { |
| 249 | − /* do nothing */ | |
| 398 | + uint64_t hblank = crtc_info->h_total - crtc_info->h_active; | |
| 399 | + struct fixed31_32 hblank_time_msec = | |
| 400 | + dc_fixpt_from_fraction(hblank * 10, crtc_info->requested_pixel_clock_100Hz); | |
| 401 | + struct fixed31_32 lsclkfreq_mhz = | |
| 402 | + get_link_symbol_clk_freq_mhz(dp_link_info->link_rate); | |
| 403 | + struct fixed31_32 average_stream_sym_bw_frac; | |
| 404 | + struct fixed31_32 peak_stream_bw_kbps; | |
| 405 | + struct fixed31_32 bits_per_pixel; | |
| 406 | + struct fixed31_32 link_bw_kbps; | |
| 407 | + struct fixed31_32 available_stream_sym_count; | |
| 408 | + uint32_t available_hblank_bw = 0; /* in stream symbols */ | |
| 409 | + | |
| 410 | + if (crtc_info->dsc_bits_per_pixel) { | |
| 411 | + bits_per_pixel = dc_fixpt_from_fraction(crtc_info->dsc_bits_per_pixel, 16); | |
| 412 | + } else { | |
| 413 | + switch (crtc_info->color_depth) { | |
| 414 | + case COLOR_DEPTH_666: | |
| 415 | + bits_per_pixel = dc_fixpt_from_int(6); | |
| 416 | + break; | |
| 417 | + case COLOR_DEPTH_888: | |
| 418 | + bits_per_pixel = dc_fixpt_from_int(8); | |
| 419 | + break; | |
| 420 | + case COLOR_DEPTH_101010: | |
| 421 | + bits_per_pixel = dc_fixpt_from_int(10); | |
| 422 | + break; | |
| 423 | + case COLOR_DEPTH_121212: | |
| 424 | + bits_per_pixel = dc_fixpt_from_int(12); | |
| 425 | + break; | |
| 426 | + default: | |
| 427 | + /* Default to commonly supported color depth. */ | |
| 428 | + bits_per_pixel = dc_fixpt_from_int(8); | |
| 429 | + break; | |
| 430 | + } | |
| 431 | + | |
| 432 | + bits_per_pixel = dc_fixpt_mul_int(bits_per_pixel, 3); | |
| 433 | + | |
| 434 | + if (crtc_info->pixel_encoding == PIXEL_ENCODING_YCBCR422) { | |
| 435 | + bits_per_pixel = dc_fixpt_div_int(bits_per_pixel, 3); | |
| 436 | + bits_per_pixel = dc_fixpt_mul_int(bits_per_pixel, 2); | |
| 437 | + } else if (crtc_info->pixel_encoding == PIXEL_ENCODING_YCBCR420) { | |
| 438 | + bits_per_pixel = dc_fixpt_div_int(bits_per_pixel, 2); | |
| 439 | + } | |
| 440 | + } | |
| 441 | + | |
| 442 | + /* Use simple stream BW calculation because mainlink overhead is | |
| 443 | + * accounted for separately in the audio BW calculations. | |
| 444 | + */ | |
| 445 | + peak_stream_bw_kbps = dc_fixpt_from_fraction(crtc_info->requested_pixel_clock_100Hz, 10); | |
| 446 | + peak_stream_bw_kbps = dc_fixpt_mul(peak_stream_bw_kbps, bits_per_pixel); | |
| 447 | + link_bw_kbps = dc_fixpt_from_int(dp_link_info->link_bandwidth_kbps); | |
| 448 | + average_stream_sym_bw_frac = dc_fixpt_div(peak_stream_bw_kbps, link_bw_kbps); | |
| 449 | + | |
| 450 | + available_stream_sym_count = dc_fixpt_mul_int(hblank_time_msec, 1000); | |
| 451 | + available_stream_sym_count = dc_fixpt_mul(available_stream_sym_count, lsclkfreq_mhz); | |
| 452 | + available_stream_sym_count = dc_fixpt_mul(available_stream_sym_count, average_stream_sym_bw_frac); | |
| 453 | + available_hblank_bw = dc_fixpt_floor(available_stream_sym_count); | |
| 454 | + available_hblank_bw *= dp_link_info->lane_count; | |
| 455 | + available_hblank_bw -= crtc_info->dsc_num_slices * 4; /* EOC overhead */ | |
| 456 | + | |
| 457 | + if (available_hblank_bw < dp_link_info->hblank_min_symbol_width) | |
| 458 | + available_hblank_bw = dp_link_info->hblank_min_symbol_width; | |
| 459 | + | |
| 460 | + if (available_hblank_bw < 12) | |
| 461 | + available_hblank_bw = 0; | |
| 462 | + else | |
| 463 | + available_hblank_bw -= 12; /* Main link overhead */ | |
| 464 | + | |
| 465 | + return available_hblank_bw; | |
| 250 | 466 | } |
| 251 | 467 | |
| 252 | −/*For DP MST, calculate if specified sample rates can fit into a given timing */ | |
| 253 | −static void check_audio_bandwidth_dpmst( | |
| 468 | +static void check_audio_bandwidth_dp( | |
| 254 | 469 | const struct audio_crtc_info *crtc_info, |
| 470 | + const struct audio_dp_link_info *dp_link_info, | |
| 255 | 471 | uint32_t channel_count, |
| 256 | 472 | union audio_sample_rates *sample_rates) |
| 257 | 473 | { |
| 258 | − /* do nothing */ | |
| 474 | + struct dp_audio_layout_config layout_config = {0}; | |
| 475 | + uint32_t available_hblank_bw; | |
| 476 | + uint32_t av_stream_map_lane_count; | |
| 477 | + uint32_t audio_sdp_overhead; | |
| 478 | + | |
| 479 | + /* TODO: Add validation for SST 8b/10 case */ | |
| 480 | + if (!dp_link_info->is_mst && dp_link_info->encoding == DP_8b_10b_ENCODING) | |
| 481 | + return; | |
| 482 | + | |
| 483 | + available_hblank_bw = calculate_available_hblank_bw_in_symbols( | |
| 484 | + crtc_info, dp_link_info); | |
| 485 | + av_stream_map_lane_count = get_av_stream_map_lane_count( | |
| 486 | + dp_link_info->encoding, dp_link_info->lane_count, dp_link_info->is_mst); | |
| 487 | + audio_sdp_overhead = get_audio_sdp_overhead( | |
| 488 | + dp_link_info->encoding, dp_link_info->lane_count, dp_link_info->is_mst); | |
| 489 | + get_audio_layout_config( | |
| 490 | + channel_count, dp_link_info->encoding, &layout_config); | |
| 491 | + | |
| 492 | + if (layout_config.max_layouts_per_audio_sdp == 0 || | |
| 493 | + layout_config.symbols_per_layout == 0 || | |
| 494 | + layout_config.layouts_per_sample_denom == 0) { | |
| 495 | + return; | |
| 496 | + } | |
| 497 | + if (available_hblank_bw < calculate_required_audio_bw_in_symbols( | |
| 498 | + crtc_info, &layout_config, channel_count, 192000, | |
| 499 | + av_stream_map_lane_count, audio_sdp_overhead)) | |
| 500 | + sample_rates->rate.RATE_192 = 0; | |
| 501 | + if (available_hblank_bw < calculate_required_audio_bw_in_symbols( | |
| 502 | + crtc_info, &layout_config, channel_count, 176400, | |
| 503 | + av_stream_map_lane_count, audio_sdp_overhead)) | |
| 504 | + sample_rates->rate.RATE_176_4 = 0; | |
| 505 | + if (available_hblank_bw < calculate_required_audio_bw_in_symbols( | |
| 506 | + crtc_info, &layout_config, channel_count, 96000, | |
| 507 | + av_stream_map_lane_count, audio_sdp_overhead)) | |
| 508 | + sample_rates->rate.RATE_96 = 0; | |
| 509 | + if (available_hblank_bw < calculate_required_audio_bw_in_symbols( | |
| 510 | + crtc_info, &layout_config, channel_count, 88200, | |
| 511 | + av_stream_map_lane_count, audio_sdp_overhead)) | |
| 512 | + sample_rates->rate.RATE_88_2 = 0; | |
| 513 | + if (available_hblank_bw < calculate_required_audio_bw_in_symbols( | |
| 514 | + crtc_info, &layout_config, channel_count, 48000, | |
| 515 | + av_stream_map_lane_count, audio_sdp_overhead)) | |
| 516 | + sample_rates->rate.RATE_48 = 0; | |
| 517 | + if (available_hblank_bw < calculate_required_audio_bw_in_symbols( | |
| 518 | + crtc_info, &layout_config, channel_count, 44100, | |
| 519 | + av_stream_map_lane_count, audio_sdp_overhead)) | |
| 520 | + sample_rates->rate.RATE_44_1 = 0; | |
| 521 | + if (available_hblank_bw < calculate_required_audio_bw_in_symbols( | |
| 522 | + crtc_info, &layout_config, channel_count, 32000, | |
| 523 | + av_stream_map_lane_count, audio_sdp_overhead)) | |
| 524 | + sample_rates->rate.RATE_32 = 0; | |
| 259 | 525 | } |
| 260 | 526 | |
| 261 | 527 | static void check_audio_bandwidth( |
| 262 | 528 | const struct audio_crtc_info *crtc_info, |
| 529 | + const struct audio_dp_link_info *dp_link_info, | |
| 263 | 530 | uint32_t channel_count, |
| 264 | 531 | enum signal_type signal, |
| 265 | 532 | union audio_sample_rates *sample_rates) |
| @@ -271,12 +538,9 @@ static void check_audio_bandwidth( · 5 unmodified lines | ||
| 271 | 538 | break; |
| 272 | 539 | case SIGNAL_TYPE_EDP: |
| 273 | 540 | case SIGNAL_TYPE_DISPLAY_PORT: |
| 274 | − check_audio_bandwidth_dpsst( | |
| 275 | − crtc_info, channel_count, sample_rates); | |
| 276 | − break; | |
| 277 | 541 | case SIGNAL_TYPE_DISPLAY_PORT_MST: |
| 278 | − check_audio_bandwidth_dpmst( | |
| 279 | − crtc_info, channel_count, sample_rates); | |
| 542 | + check_audio_bandwidth_dp( | |
| 543 | + crtc_info, dp_link_info, channel_count, sample_rates); | |
| 280 | 544 | break; |
| 281 | 545 | default: |
| 282 | 546 | break; |
| @@ -394,7 +658,8 @@ void dce_aud_az_configure( · 111 unmodified lines | ||
| 394 | 658 | struct audio *audio, |
| 395 | 659 | enum signal_type signal, |
| 396 | 660 | const struct audio_crtc_info *crtc_info, |
| 397 | − const struct audio_info *audio_info) | |
| 661 | + const struct audio_info *audio_info, | |
| 662 | + const struct audio_dp_link_info *dp_link_info) | |
| 398 | 663 | { |
| 399 | 664 | struct dce_audio *aud = DCE_AUD(audio); |
| 400 | 665 | |
| @@ -529,6 +794,7 @@ void dce_aud_az_configure( · 128 unmodified lines | ||
| 529 | 794 | |
| 530 | 795 | check_audio_bandwidth( |
| 531 | 796 | crtc_info, |
| 797 | + dp_link_info, | |
| 532 | 798 | channel_count, |
| 533 | 799 | signal, |
| 534 | 800 | &sample_rates); |
| @@ -588,6 +854,7 @@ void dce_aud_az_configure( · 53 unmodified lines | ||
| 588 | 854 | |
| 589 | 855 | check_audio_bandwidth( |
| 590 | 856 | crtc_info, |
| 857 | + dp_link_info, | |
| 591 | 858 | 8, |
| 592 | 859 | signal, |
| 593 | 860 | &sample_rate); |
| @@ -170,7 +170,8 @@ void dce_aud_az_disable(struct audio *audio); · 169 unmodified lines | ||
| 170 | 170 | void dce_aud_az_configure(struct audio *audio, |
| 171 | 171 | enum signal_type signal, |
| 172 | 172 | const struct audio_crtc_info *crtc_info, |
| 173 | − const struct audio_info *audio_info); | |
| 173 | + const struct audio_info *audio_info, | |
| 174 | + const struct audio_dp_link_info *dp_link_info); | |
| 174 | 175 | |
| 175 | 176 | void dce_aud_wall_dto_setup(struct audio *audio, |
| 176 | 177 | enum signal_type signal, |
| @@ -258,7 +258,7 @@ static void dmub_replay_residency(struct dmub_replay *dmub, uint8_t panel_inst, · 257 unmodified lines | ||
| 258 | 258 | *residency = 0; |
| 259 | 259 | } |
| 260 | 260 | |
| 261 | −/** | |
| 261 | +/* | |
| 262 | 262 | * Set REPLAY power optimization flags and coasting vtotal. |
| 263 | 263 | */ |
| 264 | 264 | static void dmub_replay_set_power_opt_and_coasting_vtotal(struct dmub_replay *dmub, |
| @@ -280,7 +280,7 @@ static void dmub_replay_set_power_opt_and_coasting_vtotal(struct dmub_replay *dm · 15 unmodified lines | ||
| 280 | 280 | dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT); |
| 281 | 281 | } |
| 282 | 282 | |
| 283 | −/** | |
| 283 | +/* | |
| 284 | 284 | * send Replay general cmd to DMUB. |
| 285 | 285 | */ |
| 286 | 286 | static void dmub_replay_send_cmd(struct dmub_replay *dmub, |
| @@ -62,6 +62,26 @@ void cm_helper_program_color_matrices( · 61 unmodified lines | ||
| 62 | 62 | |
| 63 | 63 | } |
| 64 | 64 | |
| 65 | +void cm_helper_read_color_matrices(struct dc_context *ctx, | |
| 66 | + uint16_t *regval, | |
| 67 | + const struct color_matrices_reg *reg) | |
| 68 | +{ | |
| 69 | + uint32_t cur_csc_reg, regval0, regval1; | |
| 70 | + unsigned int i = 0; | |
| 71 | + | |
| 72 | + for (cur_csc_reg = reg->csc_c11_c12; | |
| 73 | + cur_csc_reg <= reg->csc_c33_c34; cur_csc_reg++) { | |
| 74 | + REG_GET_2(cur_csc_reg, | |
| 75 | + csc_c11, ®val0, | |
| 76 | + csc_c12, ®val1); | |
| 77 | + | |
| 78 | + regval[2 * i] = regval0; | |
| 79 | + regval[(2 * i) + 1] = regval1; | |
| 80 | + | |
| 81 | + i++; | |
| 82 | + } | |
| 83 | +} | |
| 84 | + | |
| 65 | 85 | void cm_helper_program_xfer_func( |
| 66 | 86 | struct dc_context *ctx, |
| 67 | 87 | const struct pwl_params *params, |
| @@ -114,5 +114,7 @@ bool cm_helper_translate_curve_to_degamma_hw_format( · 113 unmodified lines | ||
| 114 | 114 | const struct dc_transfer_func *output_tf, |
| 115 | 115 | struct pwl_params *lut_params); |
| 116 | 116 | |
| 117 | − | |
| 117 | +void cm_helper_read_color_matrices(struct dc_context *ctx, | |
| 118 | + uint16_t *regval, | |
| 119 | + const struct color_matrices_reg *reg); | |
| 118 | 120 | #endif |
| @@ -543,7 +543,8 @@ static const struct dpp_funcs dcn10_dpp_funcs = { · 542 unmodified lines | ||
| 543 | 543 | .dpp_set_hdr_multiplier = dpp1_set_hdr_multiplier, |
| 544 | 544 | .dpp_program_blnd_lut = NULL, |
| 545 | 545 | .dpp_program_shaper_lut = NULL, |
| 546 | − .dpp_program_3dlut = NULL | |
| 546 | + .dpp_program_3dlut = NULL, | |
| 547 | + .dpp_get_gamut_remap = dpp1_cm_get_gamut_remap, | |
| 547 | 548 | }; |
| 548 | 549 | |
| 549 | 550 | static struct dpp_caps dcn10_dpp_cap = { |
| @@ -1521,4 +1521,7 @@ void dpp1_construct(struct dcn10_dpp *dpp1, · 1520 unmodified lines | ||
| 1521 | 1521 | const struct dcn_dpp_registers *tf_regs, |
| 1522 | 1522 | const struct dcn_dpp_shift *tf_shift, |
| 1523 | 1523 | const struct dcn_dpp_mask *tf_mask); |
| 1524 | + | |
| 1525 | +void dpp1_cm_get_gamut_remap(struct dpp *dpp_base, | |
| 1526 | + struct dpp_grph_csc_adjustment *adjust); | |
| 1524 | 1527 | #endif |
| @@ -98,7 +98,7 @@ static void program_gamut_remap( · 97 unmodified lines | ||
| 98 | 98 | |
| 99 | 99 | if (regval == NULL || select == GAMUT_REMAP_BYPASS) { |
| 100 | 100 | REG_SET(CM_GAMUT_REMAP_CONTROL, 0, |
| 101 | − CM_GAMUT_REMAP_MODE, 0); | |
| 101 | + CM_GAMUT_REMAP_MODE, 0); | |
| 102 | 102 | return; |
| 103 | 103 | } |
| 104 | 104 | switch (select) { |
| @@ -181,6 +181,74 @@ void dpp1_cm_set_gamut_remap( · 76 unmodified lines | ||
| 181 | 181 | } |
| 182 | 182 | } |
| 183 | 183 | |
| 184 | +static void read_gamut_remap(struct dcn10_dpp *dpp, | |
| 185 | + uint16_t *regval, | |
| 186 | + enum gamut_remap_select *select) | |
| 187 | +{ | |
| 188 | + struct color_matrices_reg gam_regs; | |
| 189 | + uint32_t selection; | |
| 190 | + | |
| 191 | + REG_GET(CM_GAMUT_REMAP_CONTROL, | |
| 192 | + CM_GAMUT_REMAP_MODE, &selection); | |
| 193 | + | |
| 194 | + *select = selection; | |
| 195 | + | |
| 196 | + gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; | |
| 197 | + gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; | |
| 198 | + gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12; | |
| 199 | + gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12; | |
| 200 | + | |
| 201 | + if (*select == GAMUT_REMAP_COEFF) { | |
| 202 | + | |
| 203 | + gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_C11_C12); | |
| 204 | + gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_C33_C34); | |
| 205 | + | |
| 206 | + cm_helper_read_color_matrices( | |
| 207 | + dpp->base.ctx, | |
| 208 | + regval, | |
| 209 | + &gam_regs); | |
| 210 | + | |
| 211 | + } else if (*select == GAMUT_REMAP_COMA_COEFF) { | |
| 212 | + | |
| 213 | + gam_regs.csc_c11_c12 = REG(CM_COMA_C11_C12); | |
| 214 | + gam_regs.csc_c33_c34 = REG(CM_COMA_C33_C34); | |
| 215 | + | |
| 216 | + cm_helper_read_color_matrices( | |
| 217 | + dpp->base.ctx, | |
| 218 | + regval, | |
| 219 | + &gam_regs); | |
| 220 | + | |
| 221 | + } else if (*select == GAMUT_REMAP_COMB_COEFF) { | |
| 222 | + | |
| 223 | + gam_regs.csc_c11_c12 = REG(CM_COMB_C11_C12); | |
| 224 | + gam_regs.csc_c33_c34 = REG(CM_COMB_C33_C34); | |
| 225 | + | |
| 226 | + cm_helper_read_color_matrices( | |
| 227 | + dpp->base.ctx, | |
| 228 | + regval, | |
| 229 | + &gam_regs); | |
| 230 | + } | |
| 231 | +} | |
| 232 | + | |
| 233 | +void dpp1_cm_get_gamut_remap(struct dpp *dpp_base, | |
| 234 | + struct dpp_grph_csc_adjustment *adjust) | |
| 235 | +{ | |
| 236 | + struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); | |
| 237 | + uint16_t arr_reg_val[12]; | |
| 238 | + enum gamut_remap_select select; | |
| 239 | + | |
| 240 | + read_gamut_remap(dpp, arr_reg_val, &select); | |
| 241 | + | |
| 242 | + if (select == GAMUT_REMAP_BYPASS) { | |
| 243 | + adjust->gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; | |
| 244 | + return; | |
| 245 | + } | |
| 246 | + | |
| 247 | + adjust->gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; | |
| 248 | + convert_hw_matrix(adjust->temperature_matrix, | |
| 249 | + arr_reg_val, ARRAY_SIZE(arr_reg_val)); | |
| 250 | +} | |
| 251 | + | |
| 184 | 252 | static void dpp1_cm_program_color_matrix( |
| 185 | 253 | struct dcn10_dpp *dpp, |
| 186 | 254 | const uint16_t *regval) |
| @@ -23,6 +23,7 @@ · 22 unmodified lines | ||
| 23 | 23 | * |
| 24 | 24 | */ |
| 25 | 25 | |
| 26 | +#include "core_types.h" | |
| 26 | 27 | #include "dm_services.h" |
| 27 | 28 | #include "dcn10_opp.h" |
| 28 | 29 | #include "reg_helper.h" |
| @@ -160,6 +161,9 @@ static void opp1_set_pixel_encoding( · 131 unmodified lines | ||
| 160 | 161 | struct dcn10_opp *oppn10, |
| 161 | 162 | const struct clamping_and_pixel_encoding_params *params) |
| 162 | 163 | { |
| 164 | + bool force_chroma_subsampling_1tap = | |
| 165 | + oppn10->base.ctx->dc->debug.force_chroma_subsampling_1tap; | |
| 166 | + | |
| 163 | 167 | switch (params->pixel_encoding) { |
| 164 | 168 | |
| 165 | 169 | case PIXEL_ENCODING_RGB: |
| @@ -178,6 +182,9 @@ static void opp1_set_pixel_encoding( · 12 unmodified lines | ||
| 178 | 182 | default: |
| 179 | 183 | break; |
| 180 | 184 | } |
| 185 | + | |
| 186 | + if (force_chroma_subsampling_1tap) | |
| 187 | + REG_UPDATE(FMT_CONTROL, FMT_SUBSAMPLING_MODE, 0); | |
| 181 | 188 | } |
| 182 | 189 | |
| 183 | 190 | /** |
| @@ -55,21 +55,23 @@ void dpp20_read_state(struct dpp *dpp_base, · 54 unmodified lines | ||
| 55 | 55 | |
| 56 | 56 | REG_GET(DPP_CONTROL, |
| 57 | 57 | DPP_CLOCK_ENABLE, &s->is_enabled); |
| 58 | + | |
| 59 | + // Degamma LUT (RAM) | |
| 58 | 60 | REG_GET(CM_DGAM_CONTROL, |
| 59 | − CM_DGAM_LUT_MODE, &s->dgam_lut_mode); | |
| 60 | − // BGAM has no ROM, and definition is different, can't reuse same dump | |
| 61 | − //REG_GET(CM_BLNDGAM_CONTROL, | |
| 62 | − // CM_BLNDGAM_LUT_MODE, &s->rgam_lut_mode); | |
| 63 | − REG_GET(CM_GAMUT_REMAP_CONTROL, | |
| 64 | − CM_GAMUT_REMAP_MODE, &s->gamut_remap_mode); | |
| 65 | − if (s->gamut_remap_mode) { | |
| 66 | − s->gamut_remap_c11_c12 = REG_READ(CM_GAMUT_REMAP_C11_C12); | |
| 67 | − s->gamut_remap_c13_c14 = REG_READ(CM_GAMUT_REMAP_C13_C14); | |
| 68 | − s->gamut_remap_c21_c22 = REG_READ(CM_GAMUT_REMAP_C21_C22); | |
| 69 | − s->gamut_remap_c23_c24 = REG_READ(CM_GAMUT_REMAP_C23_C24); | |
| 70 | − s->gamut_remap_c31_c32 = REG_READ(CM_GAMUT_REMAP_C31_C32); | |
| 71 | − s->gamut_remap_c33_c34 = REG_READ(CM_GAMUT_REMAP_C33_C34); | |
| 72 | − } | |
| 61 | + CM_DGAM_LUT_MODE, &s->dgam_lut_mode); | |
| 62 | + | |
| 63 | + // Shaper LUT (RAM), 3D LUT (mode, bit-depth, size) | |
| 64 | + REG_GET(CM_SHAPER_CONTROL, | |
| 65 | + CM_SHAPER_LUT_MODE, &s->shaper_lut_mode); | |
| 66 | + REG_GET_2(CM_3DLUT_READ_WRITE_CONTROL, | |
| 67 | + CM_3DLUT_CONFIG_STATUS, &s->lut3d_mode, | |
| 68 | + CM_3DLUT_30BIT_EN, &s->lut3d_bit_depth); | |
| 69 | + REG_GET(CM_3DLUT_MODE, | |
| 70 | + CM_3DLUT_SIZE, &s->lut3d_size); | |
| 71 | + | |
| 72 | + // Blend/Out Gamma (RAM) | |
| 73 | + REG_GET(CM_BLNDGAM_LUT_WRITE_EN_MASK, | |
| 74 | + CM_BLNDGAM_CONFIG_STATUS, &s->rgam_lut_mode); | |
| 73 | 75 | } |
| 74 | 76 | |
| 75 | 77 | void dpp2_power_on_obuf( |
| @@ -393,6 +395,7 @@ static struct dpp_funcs dcn20_dpp_funcs = { · 317 unmodified lines | ||
| 393 | 395 | .set_optional_cursor_attributes = dpp1_cnv_set_optional_cursor_attributes, |
| 394 | 396 | .dpp_dppclk_control = dpp1_dppclk_control, |
| 395 | 397 | .dpp_set_hdr_multiplier = dpp2_set_hdr_multiplier, |
| 398 | + .dpp_get_gamut_remap = dpp2_cm_get_gamut_remap, | |
| 396 | 399 | }; |
| 397 | 400 | |
| 398 | 401 | static struct dpp_caps dcn20_dpp_cap = { |
| @@ -775,4 +775,7 @@ bool dpp2_construct(struct dcn20_dpp *dpp2, · 774 unmodified lines | ||
| 775 | 775 | void dpp2_power_on_obuf( |
| 776 | 776 | struct dpp *dpp_base, |
| 777 | 777 | bool power_on); |
| 778 | + | |
| 779 | +void dpp2_cm_get_gamut_remap(struct dpp *dpp_base, | |
| 780 | + struct dpp_grph_csc_adjustment *adjust); | |
| 778 | 781 | #endif /* __DC_HWSS_DCN20_H__ */ |
| @@ -234,6 +234,61 @@ void dpp2_cm_set_gamut_remap( · 233 unmodified lines | ||
| 234 | 234 | } |
| 235 | 235 | } |
| 236 | 236 | |
| 237 | +static void read_gamut_remap(struct dcn20_dpp *dpp, | |
| 238 | + uint16_t *regval, | |
| 239 | + enum dcn20_gamut_remap_select *select) | |
| 240 | +{ | |
| 241 | + struct color_matrices_reg gam_regs; | |
| 242 | + uint32_t selection; | |
| 243 | + | |
| 244 | + IX_REG_GET(CM_TEST_DEBUG_INDEX, CM_TEST_DEBUG_DATA, | |
| 245 | + CM_TEST_DEBUG_DATA_STATUS_IDX, | |
| 246 | + CM_TEST_DEBUG_DATA_GAMUT_REMAP_MODE, &selection); | |
| 247 | + | |
| 248 | + *select = selection; | |
| 249 | + | |
| 250 | + gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; | |
| 251 | + gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; | |
| 252 | + gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12; | |
| 253 | + gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12; | |
| 254 | + | |
| 255 | + if (*select == DCN2_GAMUT_REMAP_COEF_A) { | |
| 256 | + gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_C11_C12); | |
| 257 | + gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_C33_C34); | |
| 258 | + | |
| 259 | + cm_helper_read_color_matrices(dpp->base.ctx, | |
| 260 | + regval, | |
| 261 | + &gam_regs); | |
| 262 | + | |
| 263 | + } else if (*select == DCN2_GAMUT_REMAP_COEF_B) { | |
| 264 | + gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_B_C11_C12); | |
| 265 | + gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_B_C33_C34); | |
| 266 | + | |
| 267 | + cm_helper_read_color_matrices(dpp->base.ctx, | |
| 268 | + regval, | |
| 269 | + &gam_regs); | |
| 270 | + } | |
| 271 | +} | |
| 272 | + | |
| 273 | +void dpp2_cm_get_gamut_remap(struct dpp *dpp_base, | |
| 274 | + struct dpp_grph_csc_adjustment *adjust) | |
| 275 | +{ | |
| 276 | + struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); | |
| 277 | + uint16_t arr_reg_val[12]; | |
| 278 | + enum dcn20_gamut_remap_select select; | |
| 279 | + | |
| 280 | + read_gamut_remap(dpp, arr_reg_val, &select); | |
| 281 | + | |
| 282 | + if (select == DCN2_GAMUT_REMAP_BYPASS) { | |
| 283 | + adjust->gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; | |
| 284 | + return; | |
| 285 | + } | |
| 286 | + | |
| 287 | + adjust->gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; | |
| 288 | + convert_hw_matrix(adjust->temperature_matrix, | |
| 289 | + arr_reg_val, ARRAY_SIZE(arr_reg_val)); | |
| 290 | +} | |
| 291 | + | |
| 237 | 292 | void dpp2_program_input_csc( |
| 238 | 293 | struct dpp *dpp_base, |
| 239 | 294 | enum dc_color_space color_space, |
| @@ -542,8 +542,30 @@ static struct mpcc *mpc2_get_mpcc_for_dpp(struct mpc_tree *tree, int dpp_id) · 541 unmodified lines | ||
| 542 | 542 | return NULL; |
| 543 | 543 | } |
| 544 | 544 | |
| 545 | +static void mpc2_read_mpcc_state( | |
| 546 | + struct mpc *mpc, | |
| 547 | + int mpcc_inst, | |
| 548 | + struct mpcc_state *s) | |
| 549 | +{ | |
| 550 | + struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc); | |
| 551 | + | |
| 552 | + REG_GET(MPCC_OPP_ID[mpcc_inst], MPCC_OPP_ID, &s->opp_id); | |
| 553 | + REG_GET(MPCC_TOP_SEL[mpcc_inst], MPCC_TOP_SEL, &s->dpp_id); | |
| 554 | + REG_GET(MPCC_BOT_SEL[mpcc_inst], MPCC_BOT_SEL, &s->bot_mpcc_id); | |
| 555 | + REG_GET_4(MPCC_CONTROL[mpcc_inst], MPCC_MODE, &s->mode, | |
| 556 | + MPCC_ALPHA_BLND_MODE, &s->alpha_mode, | |
| 557 | + MPCC_ALPHA_MULTIPLIED_MODE, &s->pre_multiplied_alpha, | |
| 558 | + MPCC_BLND_ACTIVE_OVERLAP_ONLY, &s->overlap_only); | |
| 559 | + REG_GET_2(MPCC_STATUS[mpcc_inst], MPCC_IDLE, &s->idle, | |
| 560 | + MPCC_BUSY, &s->busy); | |
| 561 | + | |
| 562 | + /* Gamma block state */ | |
| 563 | + REG_GET(MPCC_OGAM_LUT_RAM_CONTROL[mpcc_inst], | |
| 564 | + MPCC_OGAM_CONFIG_STATUS, &s->rgam_mode); | |
| 565 | +} | |
| 566 | + | |
| 545 | 567 | static const struct mpc_funcs dcn20_mpc_funcs = { |
| 546 | − .read_mpcc_state = mpc1_read_mpcc_state, | |
| 568 | + .read_mpcc_state = mpc2_read_mpcc_state, | |
| 547 | 569 | .insert_plane = mpc1_insert_plane, |
| 548 | 570 | .remove_mpcc = mpc1_remove_mpcc, |
| 549 | 571 | .mpc_init = mpc1_mpc_init, |
| @@ -275,6 +275,7 @@ static struct dpp_funcs dcn201_dpp_funcs = { · 274 unmodified lines | ||
| 275 | 275 | .set_optional_cursor_attributes = dpp1_cnv_set_optional_cursor_attributes, |
| 276 | 276 | .dpp_dppclk_control = dpp1_dppclk_control, |
| 277 | 277 | .dpp_set_hdr_multiplier = dpp2_set_hdr_multiplier, |
| 278 | + .dpp_get_gamut_remap = dpp2_cm_get_gamut_remap, | |
| 278 | 279 | }; |
| 279 | 280 | |
| 280 | 281 | static struct dpp_caps dcn201_dpp_cap = { |
| @@ -44,12 +44,45 @@ · 43 unmodified lines | ||
| 44 | 44 | void dpp30_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s) |
| 45 | 45 | { |
| 46 | 46 | struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); |
| 47 | + uint32_t gamcor_lut_mode, rgam_lut_mode; | |
| 47 | 48 | |
| 48 | 49 | REG_GET(DPP_CONTROL, |
| 49 | − DPP_CLOCK_ENABLE, &s->is_enabled); | |
| 50 | + DPP_CLOCK_ENABLE, &s->is_enabled); | |
| 51 | + | |
| 52 | + // Pre-degamma (ROM) | |
| 53 | + REG_GET_2(PRE_DEGAM, | |
| 54 | + PRE_DEGAM_MODE, &s->pre_dgam_mode, | |
| 55 | + PRE_DEGAM_SELECT, &s->pre_dgam_select); | |
| 56 | + | |
| 57 | + // Gamma Correction (RAM) | |
| 58 | + REG_GET(CM_GAMCOR_CONTROL, | |
| 59 | + CM_GAMCOR_MODE_CURRENT, &s->gamcor_mode); | |
| 60 | + if (s->gamcor_mode) { | |
| 61 | + REG_GET(CM_GAMCOR_CONTROL, CM_GAMCOR_SELECT_CURRENT, &gamcor_lut_mode); | |
| 62 | + if (!gamcor_lut_mode) | |
| 63 | + s->gamcor_mode = LUT_RAM_A; // Otherwise, LUT_RAM_B | |
| 64 | + } | |
| 50 | 65 | |
| 51 | − // TODO: Implement for DCN3 | |
| 66 | + // Shaper LUT (RAM), 3D LUT (mode, bit-depth, size) | |
| 67 | + REG_GET(CM_SHAPER_CONTROL, | |
| 68 | + CM_SHAPER_LUT_MODE, &s->shaper_lut_mode); | |
| 69 | + REG_GET(CM_3DLUT_MODE, | |
| 70 | + CM_3DLUT_MODE_CURRENT, &s->lut3d_mode); | |
| 71 | + REG_GET(CM_3DLUT_READ_WRITE_CONTROL, | |
| 72 | + CM_3DLUT_30BIT_EN, &s->lut3d_bit_depth); | |
| 73 | + REG_GET(CM_3DLUT_MODE, | |
| 74 | + CM_3DLUT_SIZE, &s->lut3d_size); | |
| 75 | + | |
| 76 | + // Blend/Out Gamma (RAM) | |
| 77 | + REG_GET(CM_BLNDGAM_CONTROL, | |
| 78 | + CM_BLNDGAM_MODE_CURRENT, &s->rgam_lut_mode); | |
| 79 | + if (s->rgam_lut_mode){ | |
| 80 | + REG_GET(CM_BLNDGAM_CONTROL, CM_BLNDGAM_SELECT_CURRENT, &rgam_lut_mode); | |
| 81 | + if (!rgam_lut_mode) | |
| 82 | + s->rgam_lut_mode = LUT_RAM_A; // Otherwise, LUT_RAM_B | |
| 83 | + } | |
| 52 | 84 | } |
| 85 | + | |
| 53 | 86 | /*program post scaler scs block in dpp CM*/ |
| 54 | 87 | void dpp3_program_post_csc( |
| 55 | 88 | struct dpp *dpp_base, |
| @@ -1462,6 +1495,7 @@ static struct dpp_funcs dcn30_dpp_funcs = { · 1406 unmodified lines | ||
| 1462 | 1495 | .set_optional_cursor_attributes = dpp1_cnv_set_optional_cursor_attributes, |
| 1463 | 1496 | .dpp_dppclk_control = dpp1_dppclk_control, |
| 1464 | 1497 | .dpp_set_hdr_multiplier = dpp3_set_hdr_multiplier, |
| 1498 | + .dpp_get_gamut_remap = dpp3_cm_get_gamut_remap, | |
| 1465 | 1499 | }; |
| 1466 | 1500 | |
| 1467 | 1501 | |
| @@ -637,4 +637,6 @@ void dpp3_program_cm_dealpha( · 636 unmodified lines | ||
| 637 | 637 | struct dpp *dpp_base, |
| 638 | 638 | uint32_t enable, uint32_t additive_blending); |
| 639 | 639 | |
| 640 | +void dpp3_cm_get_gamut_remap(struct dpp *dpp_base, | |
| 641 | + struct dpp_grph_csc_adjustment *adjust); | |
| 640 | 642 | #endif /* __DC_HWSS_DCN30_H__ */ |
| @@ -408,3 +408,57 @@ void dpp3_cm_set_gamut_remap( · 407 unmodified lines | ||
| 408 | 408 | program_gamut_remap(dpp, arr_reg_val, gamut_mode); |
| 409 | 409 | } |
| 410 | 410 | } |
| 411 | + | |
| 412 | +static void read_gamut_remap(struct dcn3_dpp *dpp, | |
| 413 | + uint16_t *regval, | |
| 414 | + int *select) | |
| 415 | +{ | |
| 416 | + struct color_matrices_reg gam_regs; | |
| 417 | + uint32_t selection; | |
| 418 | + | |
| 419 | + //current coefficient set in use | |
| 420 | + REG_GET(CM_GAMUT_REMAP_CONTROL, CM_GAMUT_REMAP_MODE_CURRENT, &selection); | |
| 421 | + | |
| 422 | + *select = selection; | |
| 423 | + | |
| 424 | + gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; | |
| 425 | + gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; | |
| 426 | + gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12; | |
| 427 | + gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12; | |
| 428 | + | |
| 429 | + if (*select == GAMUT_REMAP_COEFF) { | |
| 430 | + gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_C11_C12); | |
| 431 | + gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_C33_C34); | |
| 432 | + | |
| 433 | + cm_helper_read_color_matrices(dpp->base.ctx, | |
| 434 | + regval, | |
| 435 | + &gam_regs); | |
| 436 | + | |
| 437 | + } else if (*select == GAMUT_REMAP_COMA_COEFF) { | |
| 438 | + gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_B_C11_C12); | |
| 439 | + gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_B_C33_C34); | |
| 440 | + | |
| 441 | + cm_helper_read_color_matrices(dpp->base.ctx, | |
| 442 | + regval, | |
| 443 | + &gam_regs); | |
| 444 | + } | |
| 445 | +} | |
| 446 | + | |
| 447 | +void dpp3_cm_get_gamut_remap(struct dpp *dpp_base, | |
| 448 | + struct dpp_grph_csc_adjustment *adjust) | |
| 449 | +{ | |
| 450 | + struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); | |
| 451 | + uint16_t arr_reg_val[12]; | |
| 452 | + int select; | |
| 453 | + | |
| 454 | + read_gamut_remap(dpp, arr_reg_val, &select); | |
| 455 | + | |
| 456 | + if (select == GAMUT_REMAP_BYPASS) { | |
| 457 | + adjust->gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; | |
| 458 | + return; | |
| 459 | + } | |
| 460 | + | |
| 461 | + adjust->gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; | |
| 462 | + convert_hw_matrix(adjust->temperature_matrix, | |
| 463 | + arr_reg_val, ARRAY_SIZE(arr_reg_val)); | |
| 464 | +} | |
| @@ -1129,6 +1129,64 @@ void mpc3_set_gamut_remap( · 1128 unmodified lines | ||
| 1129 | 1129 | } |
| 1130 | 1130 | } |
| 1131 | 1131 | |
| 1132 | +static void read_gamut_remap(struct dcn30_mpc *mpc30, | |
| 1133 | + int mpcc_id, | |
| 1134 | + uint16_t *regval, | |
| 1135 | + uint32_t *select) | |
| 1136 | +{ | |
| 1137 | + struct color_matrices_reg gam_regs; | |
| 1138 | + | |
| 1139 | + //current coefficient set in use | |
| 1140 | + REG_GET(MPCC_GAMUT_REMAP_MODE[mpcc_id], MPCC_GAMUT_REMAP_MODE_CURRENT, select); | |
| 1141 | + | |
| 1142 | + gam_regs.shifts.csc_c11 = mpc30->mpc_shift->MPCC_GAMUT_REMAP_C11_A; | |
| 1143 | + gam_regs.masks.csc_c11 = mpc30->mpc_mask->MPCC_GAMUT_REMAP_C11_A; | |
| 1144 | + gam_regs.shifts.csc_c12 = mpc30->mpc_shift->MPCC_GAMUT_REMAP_C12_A; | |
| 1145 | + gam_regs.masks.csc_c12 = mpc30->mpc_mask->MPCC_GAMUT_REMAP_C12_A; | |
| 1146 | + | |
| 1147 | + if (*select == GAMUT_REMAP_COEFF) { | |
| 1148 | + gam_regs.csc_c11_c12 = REG(MPC_GAMUT_REMAP_C11_C12_A[mpcc_id]); | |
| 1149 | + gam_regs.csc_c33_c34 = REG(MPC_GAMUT_REMAP_C33_C34_A[mpcc_id]); | |
| 1150 | + | |
| 1151 | + cm_helper_read_color_matrices( | |
| 1152 | + mpc30->base.ctx, | |
| 1153 | + regval, | |
| 1154 | + &gam_regs); | |
| 1155 | + | |
| 1156 | + } else if (*select == GAMUT_REMAP_COMA_COEFF) { | |
| 1157 | + | |
| 1158 | + gam_regs.csc_c11_c12 = REG(MPC_GAMUT_REMAP_C11_C12_B[mpcc_id]); | |
| 1159 | + gam_regs.csc_c33_c34 = REG(MPC_GAMUT_REMAP_C33_C34_B[mpcc_id]); | |
| 1160 | + | |
| 1161 | + cm_helper_read_color_matrices( | |
| 1162 | + mpc30->base.ctx, | |
| 1163 | + regval, | |
| 1164 | + &gam_regs); | |
| 1165 | + | |
| 1166 | + } | |
| 1167 | + | |
| 1168 | +} | |
| 1169 | + | |
| 1170 | +void mpc3_get_gamut_remap(struct mpc *mpc, | |
| 1171 | + int mpcc_id, | |
| 1172 | + struct mpc_grph_gamut_adjustment *adjust) | |
| 1173 | +{ | |
| 1174 | + struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); | |
| 1175 | + uint16_t arr_reg_val[12]; | |
| 1176 | + int select; | |
| 1177 | + | |
| 1178 | + read_gamut_remap(mpc30, mpcc_id, arr_reg_val, &select); | |
| 1179 | + | |
| 1180 | + if (select == GAMUT_REMAP_BYPASS) { | |
| 1181 | + adjust->gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; | |
| 1182 | + return; | |
| 1183 | + } | |
| 1184 | + | |
| 1185 | + adjust->gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; | |
| 1186 | + convert_hw_matrix(adjust->temperature_matrix, | |
| 1187 | + arr_reg_val, ARRAY_SIZE(arr_reg_val)); | |
| 1188 | +} | |
| 1189 | + | |
| 1132 | 1190 | bool mpc3_program_3dlut( |
| 1133 | 1191 | struct mpc *mpc, |
| 1134 | 1192 | const struct tetrahedral_params *params, |
| @@ -1382,8 +1440,54 @@ static void mpc3_set_mpc_mem_lp_mode(struct mpc *mpc) · 247 unmodified lines | ||
| 1382 | 1440 | } |
| 1383 | 1441 | } |
| 1384 | 1442 | |
| 1443 | +static void mpc3_read_mpcc_state( | |
| 1444 | + struct mpc *mpc, | |
| 1445 | + int mpcc_inst, | |
| 1446 | + struct mpcc_state *s) | |
| 1447 | +{ | |
| 1448 | + struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); | |
| 1449 | + uint32_t rmu_status = 0xf; | |
| 1450 | + | |
| 1451 | + REG_GET(MPCC_OPP_ID[mpcc_inst], MPCC_OPP_ID, &s->opp_id); | |
| 1452 | + REG_GET(MPCC_TOP_SEL[mpcc_inst], MPCC_TOP_SEL, &s->dpp_id); | |
| 1453 | + REG_GET(MPCC_BOT_SEL[mpcc_inst], MPCC_BOT_SEL, &s->bot_mpcc_id); | |
| 1454 | + REG_GET_4(MPCC_CONTROL[mpcc_inst], MPCC_MODE, &s->mode, | |
| 1455 | + MPCC_ALPHA_BLND_MODE, &s->alpha_mode, | |
| 1456 | + MPCC_ALPHA_MULTIPLIED_MODE, &s->pre_multiplied_alpha, | |
| 1457 | + MPCC_BLND_ACTIVE_OVERLAP_ONLY, &s->overlap_only); | |
| 1458 | + REG_GET_2(MPCC_STATUS[mpcc_inst], MPCC_IDLE, &s->idle, | |
| 1459 | + MPCC_BUSY, &s->busy); | |
| 1460 | + | |
| 1461 | + /* Color blocks state */ | |
| 1462 | + REG_GET(MPC_RMU_CONTROL, MPC_RMU0_MUX_STATUS, &rmu_status); | |
| 1463 | + | |
| 1464 | + if (rmu_status == mpcc_inst) { | |
| 1465 | + REG_GET(SHAPER_CONTROL[0], | |
| 1466 | + MPC_RMU_SHAPER_LUT_MODE_CURRENT, &s->shaper_lut_mode); | |
| 1467 | + REG_GET(RMU_3DLUT_MODE[0], | |
| 1468 | + MPC_RMU_3DLUT_MODE_CURRENT, &s->lut3d_mode); | |
| 1469 | + REG_GET(RMU_3DLUT_READ_WRITE_CONTROL[0], | |
| 1470 | + MPC_RMU_3DLUT_30BIT_EN, &s->lut3d_bit_depth); | |
| 1471 | + REG_GET(RMU_3DLUT_MODE[0], | |
| 1472 | + MPC_RMU_3DLUT_SIZE, &s->lut3d_size); | |
| 1473 | + } else { | |
| 1474 | + REG_GET(SHAPER_CONTROL[1], | |
| 1475 | + MPC_RMU_SHAPER_LUT_MODE_CURRENT, &s->shaper_lut_mode); | |
| 1476 | + REG_GET(RMU_3DLUT_MODE[1], | |
| 1477 | + MPC_RMU_3DLUT_MODE_CURRENT, &s->lut3d_mode); | |
| 1478 | + REG_GET(RMU_3DLUT_READ_WRITE_CONTROL[1], | |
| 1479 | + MPC_RMU_3DLUT_30BIT_EN, &s->lut3d_bit_depth); | |
| 1480 | + REG_GET(RMU_3DLUT_MODE[1], | |
| 1481 | + MPC_RMU_3DLUT_SIZE, &s->lut3d_size); | |
| 1482 | + } | |
| 1483 | + | |
| 1484 | + REG_GET_2(MPCC_OGAM_CONTROL[mpcc_inst], | |
| 1485 | + MPCC_OGAM_MODE_CURRENT, &s->rgam_mode, | |
| 1486 | + MPCC_OGAM_SELECT_CURRENT, &s->rgam_lut); | |
| 1487 | +} | |
| 1488 | + | |
| 1385 | 1489 | static const struct mpc_funcs dcn30_mpc_funcs = { |
| 1386 | − .read_mpcc_state = mpc1_read_mpcc_state, | |
| 1490 | + .read_mpcc_state = mpc3_read_mpcc_state, | |
| 1387 | 1491 | .insert_plane = mpc1_insert_plane, |
| 1388 | 1492 | .remove_mpcc = mpc1_remove_mpcc, |
| 1389 | 1493 | .mpc_init = mpc1_mpc_init, |
| @@ -1056,6 +1056,10 @@ void mpc3_set_gamut_remap( · 1055 unmodified lines | ||
| 1056 | 1056 | int mpcc_id, |
| 1057 | 1057 | const struct mpc_grph_gamut_adjustment *adjust); |
| 1058 | 1058 | |
| 1059 | +void mpc3_get_gamut_remap(struct mpc *mpc, | |
| 1060 | + int mpcc_id, | |
| 1061 | + struct mpc_grph_gamut_adjustment *adjust); | |
| 1062 | + | |
| 1059 | 1063 | void mpc3_set_rmu_mux( |
| 1060 | 1064 | struct mpc *mpc, |
| 1061 | 1065 | int rmu_idx, |
| @@ -203,12 +203,12 @@ void dcn32_link_encoder_construct( · 202 unmodified lines | ||
| 203 | 203 | enc10->base.hpd_source = init_data->hpd_source; |
| 204 | 204 | enc10->base.connector = init_data->connector; |
| 205 | 205 | |
| 206 | − if (enc10->base.connector.id == CONNECTOR_ID_USBC) | |
| 207 | − enc10->base.features.flags.bits.DP_IS_USB_C = 1; | |
| 208 | 206 | |
| 209 | 207 | enc10->base.preferred_engine = ENGINE_ID_UNKNOWN; |
| 210 | 208 | |
| 211 | 209 | enc10->base.features = *enc_features; |
| 210 | + if (enc10->base.connector.id == CONNECTOR_ID_USBC) | |
| 211 | + enc10->base.features.flags.bits.DP_IS_USB_C = 1; | |
| 212 | 212 | |
| 213 | 213 | enc10->base.transmitter = init_data->transmitter; |
| 214 | 214 | |
| @@ -133,6 +133,7 @@ static struct dpp_funcs dcn32_dpp_funcs = { · 132 unmodified lines | ||
| 133 | 133 | .set_optional_cursor_attributes = dpp1_cnv_set_optional_cursor_attributes, |
| 134 | 134 | .dpp_dppclk_control = dpp1_dppclk_control, |
| 135 | 135 | .dpp_set_hdr_multiplier = dpp3_set_hdr_multiplier, |
| 136 | + .dpp_get_gamut_remap = dpp3_cm_get_gamut_remap, | |
| 136 | 137 | }; |
| 137 | 138 | |
| 138 | 139 | |
| @@ -184,8 +184,6 @@ void dcn35_link_encoder_construct( · 183 unmodified lines | ||
| 184 | 184 | enc10->base.hpd_source = init_data->hpd_source; |
| 185 | 185 | enc10->base.connector = init_data->connector; |
| 186 | 186 | |
| 187 | − if (enc10->base.connector.id == CONNECTOR_ID_USBC) | |
| 188 | − enc10->base.features.flags.bits.DP_IS_USB_C = 1; | |
| 189 | 187 | |
| 190 | 188 | enc10->base.preferred_engine = ENGINE_ID_UNKNOWN; |
| 191 | 189 | |
| @@ -240,6 +238,8 @@ void dcn35_link_encoder_construct( · 48 unmodified lines | ||
| 240 | 238 | } |
| 241 | 239 | |
| 242 | 240 | enc10->base.features.flags.bits.HDMI_6GB_EN = 1; |
| 241 | + if (enc10->base.connector.id == CONNECTOR_ID_USBC) | |
| 242 | + enc10->base.features.flags.bits.DP_IS_USB_C = 1; | |
| 243 | 243 | |
| 244 | 244 | if (bp_funcs->get_connector_speed_cap_info) |
| 245 | 245 | result = bp_funcs->get_connector_speed_cap_info(enc10->base.ctx->dc_bios, |
| @@ -26,6 +26,9 @@ · 25 unmodified lines | ||
| 26 | 26 | #ifndef DM_CP_PSP_IF__H |
| 27 | 27 | #define DM_CP_PSP_IF__H |
| 28 | 28 | |
| 29 | +/* | |
| 30 | + * Interface to CPLIB/PSP to enable ASSR | |
| 31 | + */ | |
| 29 | 32 | struct dc_link; |
| 30 | 33 | |
| 31 | 34 | struct cp_psp_stream_config { |
| @@ -72,11 +72,11 @@ CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_ccflags) · 71 unmodified lines | ||
| 72 | 72 | CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_vba.o := $(dml_ccflags) |
| 73 | 73 | CFLAGS_$(AMDDALPATH)/dc/dml/dcn10/dcn10_fpu.o := $(dml_ccflags) |
| 74 | 74 | CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/dcn20_fpu.o := $(dml_ccflags) |
| 75 | −CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20.o := $(dml_ccflags) | |
| 75 | +CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20.o := $(dml_ccflags) $(frame_warn_flag) | |
| 76 | 76 | CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_rq_dlg_calc_20.o := $(dml_ccflags) |
| 77 | −CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20v2.o := $(dml_ccflags) | |
| 77 | +CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20v2.o := $(dml_ccflags) $(frame_warn_flag) | |
| 78 | 78 | CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_rq_dlg_calc_20v2.o := $(dml_ccflags) |
| 79 | −CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_mode_vba_21.o := $(dml_ccflags) | |
| 79 | +CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_mode_vba_21.o := $(dml_ccflags) $(frame_warn_flag) | |
| 80 | 80 | CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_rq_dlg_calc_21.o := $(dml_ccflags) |
| 81 | 81 | CFLAGS_$(AMDDALPATH)/dc/dml/dcn30/display_mode_vba_30.o := $(dml_ccflags) $(frame_warn_flag) |
| 82 | 82 | CFLAGS_$(AMDDALPATH)/dc/dml/dcn30/display_rq_dlg_calc_30.o := $(dml_ccflags) |
| @@ -4273,7 +4273,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l · 4272 unmodified lines | ||
| 4273 | 4273 | |
| 4274 | 4274 | //Calculate Swath, DET Configuration, DCFCLKDeepSleep |
| 4275 | 4275 | // |
| 4276 | − for (i = 0; i < mode_lib->soc.num_states; ++i) { | |
| 4276 | + for (i = start_state; i < mode_lib->soc.num_states; ++i) { | |
| 4277 | 4277 | for (j = 0; j <= 1; ++j) { |
| 4278 | 4278 | for (k = 0; k < v->NumberOfActivePlanes; ++k) { |
| 4279 | 4279 | v->RequiredDPPCLKThisState[k] = v->RequiredDPPCLK[i][j][k]; |
| @@ -4576,7 +4576,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l · 296 unmodified lines | ||
| 4576 | 4576 | |
| 4577 | 4577 | //Calculate Return BW |
| 4578 | 4578 | |
| 4579 | − for (i = 0; i < mode_lib->soc.num_states; ++i) { | |
| 4579 | + for (i = start_state; i < mode_lib->soc.num_states; ++i) { | |
| 4580 | 4580 | for (j = 0; j <= 1; ++j) { |
| 4581 | 4581 | for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) { |
| 4582 | 4582 | if (v->BlendingAndTiming[k] == k) { |
| @@ -4635,7 +4635,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l · 52 unmodified lines | ||
| 4635 | 4635 | v->UrgentOutOfOrderReturnPerChannelVMDataOnly); |
| 4636 | 4636 | v->FinalDRAMClockChangeLatency = (v->DRAMClockChangeLatencyOverride > 0 ? v->DRAMClockChangeLatencyOverride : v->DRAMClockChangeLatency); |
| 4637 | 4637 | |
| 4638 | − for (i = 0; i < mode_lib->soc.num_states; ++i) { | |
| 4638 | + for (i = start_state; i < mode_lib->soc.num_states; ++i) { | |
| 4639 | 4639 | for (j = 0; j <= 1; ++j) { |
| 4640 | 4640 | v->DCFCLKState[i][j] = v->DCFCLKPerState[i]; |
| 4641 | 4641 | } |
| @@ -4646,7 +4646,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l · 4 unmodified lines | ||
| 4646 | 4646 | |
| 4647 | 4647 | if (v->ClampMinDCFCLK) { |
| 4648 | 4648 | /* Clamp calculated values to actual minimum */ |
| 4649 | − for (i = 0; i < mode_lib->soc.num_states; ++i) { | |
| 4649 | + for (i = start_state; i < mode_lib->soc.num_states; ++i) { | |
| 4650 | 4650 | for (j = 0; j <= 1; ++j) { |
| 4651 | 4651 | if (v->DCFCLKState[i][j] < mode_lib->soc.min_dcfclk) { |
| 4652 | 4652 | v->DCFCLKState[i][j] = mode_lib->soc.min_dcfclk; |
| @@ -4656,7 +4656,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l · 3 unmodified lines | ||
| 4656 | 4656 | } |
| 4657 | 4657 | } |
| 4658 | 4658 | |
| 4659 | − for (i = 0; i < mode_lib->soc.num_states; ++i) { | |
| 4659 | + for (i = start_state; i < mode_lib->soc.num_states; ++i) { | |
| 4660 | 4660 | for (j = 0; j <= 1; ++j) { |
| 4661 | 4661 | v->IdealSDPPortBandwidthPerState[i][j] = dml_min3( |
| 4662 | 4662 | v->ReturnBusWidth * v->DCFCLKState[i][j], |
| @@ -4674,7 +4674,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l · 11 unmodified lines | ||
| 4674 | 4674 | |
| 4675 | 4675 | //Re-ordering Buffer Support Check |
| 4676 | 4676 | |
| 4677 | − for (i = 0; i < mode_lib->soc.num_states; ++i) { | |
| 4677 | + for (i = start_state; i < mode_lib->soc.num_states; ++i) { | |
| 4678 | 4678 | for (j = 0; j <= 1; ++j) { |
| 4679 | 4679 | if ((v->ROBBufferSizeInKByte - v->PixelChunkSizeInKByte) * 1024 / v->ReturnBWPerState[i][j] |
| 4680 | 4680 | > (v->RoundTripPingLatencyCycles + 32) / v->DCFCLKState[i][j] + ReorderingBytes / v->ReturnBWPerState[i][j]) { |
| @@ -4692,7 +4692,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l · 11 unmodified lines | ||
| 4692 | 4692 | MaxTotalVActiveRDBandwidth = MaxTotalVActiveRDBandwidth + v->ReadBandwidthLuma[k] + v->ReadBandwidthChroma[k]; |
| 4693 | 4693 | } |
| 4694 | 4694 | |
| 4695 | − for (i = 0; i < mode_lib->soc.num_states; ++i) { | |
| 4695 | + for (i = start_state; i < mode_lib->soc.num_states; ++i) { | |
| 4696 | 4696 | for (j = 0; j <= 1; ++j) { |
| 4697 | 4697 | v->MaxTotalVerticalActiveAvailableBandwidth[i][j] = dml_min( |
| 4698 | 4698 | v->IdealSDPPortBandwidthPerState[i][j] * v->MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperation / 100, |
| @@ -4708,7 +4708,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l · 9 unmodified lines | ||
| 4708 | 4708 | |
| 4709 | 4709 | //Prefetch Check |
| 4710 | 4710 | |
| 4711 | − for (i = 0; i < mode_lib->soc.num_states; ++i) { | |
| 4711 | + for (i = start_state; i < mode_lib->soc.num_states; ++i) { | |
| 4712 | 4712 | for (j = 0; j <= 1; ++j) { |
| 4713 | 4713 | int NextPrefetchModeState = MinPrefetchMode; |
| 4714 | 4714 | |
| @@ -266,6 +266,17 @@ void dcn303_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_p · 265 unmodified lines | ||
| 266 | 266 | optimal_uclk_for_dcfclk_sta_targets[i] = |
| 267 | 267 | bw_params->clk_table.entries[j].memclk_mhz * 16; |
| 268 | 268 | break; |
| 269 | + } else { | |
| 270 | + /* condition where (dcfclk_sta_targets[i] >= optimal_dcfclk_for_uclk[j]): | |
| 271 | + * This is required for dcn303 because it just so happens that the memory | |
| 272 | + * bandwidth is low enough such that all the optimal DCFCLK for each UCLK | |
| 273 | + * is lower than the smallest DCFCLK STA target. In this case we need to | |
| 274 | + * populate the optimal UCLK for each DCFCLK STA target to be the max UCLK. | |
| 275 | + */ | |
| 276 | + if (j == num_uclk_states - 1) { | |
| 277 | + optimal_uclk_for_dcfclk_sta_targets[i] = | |
| 278 | + bw_params->clk_table.entries[j].memclk_mhz * 16; | |
| 279 | + } | |
| 269 | 280 | } |
| 270 | 281 | } |
| 271 | 282 | } |
| @@ -1112,7 +1112,7 @@ struct pipe_slice_table { · 1111 unmodified lines | ||
| 1112 | 1112 | struct pipe_ctx *pri_pipe; |
| 1113 | 1113 | struct dc_plane_state *plane; |
| 1114 | 1114 | int slice_count; |
| 1115 | − } mpc_combines[MAX_SURFACES]; | |
| 1115 | + } mpc_combines[MAX_PLANES]; | |
| 1116 | 1116 | int mpc_combine_count; |
| 1117 | 1117 | }; |
| 1118 | 1118 | |
| @@ -1288,7 +1288,7 @@ static bool update_pipes_with_split_flags(struct dc *dc, struct dc_state *contex · 169 unmodified lines | ||
| 1288 | 1288 | return updated; |
| 1289 | 1289 | } |
| 1290 | 1290 | |
| 1291 | −static bool should_allow_odm_power_optimization(struct dc *dc, | |
| 1291 | +static bool should_apply_odm_power_optimization(struct dc *dc, | |
| 1292 | 1292 | struct dc_state *context, struct vba_vars_st *v, int *split, |
| 1293 | 1293 | bool *merge) |
| 1294 | 1294 | { |
| @@ -1392,9 +1392,12 @@ static void try_odm_power_optimization_and_revalidate( · 97 unmodified lines | ||
| 1392 | 1392 | { |
| 1393 | 1393 | int i; |
| 1394 | 1394 | unsigned int new_vlevel; |
| 1395 | + unsigned int cur_policy[MAX_PIPES]; | |
| 1395 | 1396 | |
| 1396 | − for (i = 0; i < pipe_cnt; i++) | |
| 1397 | + for (i = 0; i < pipe_cnt; i++) { | |
| 1398 | + cur_policy[i] = pipes[i].pipe.dest.odm_combine_policy; | |
| 1397 | 1399 | pipes[i].pipe.dest.odm_combine_policy = dm_odm_combine_policy_2to1; |
| 1400 | + } | |
| 1398 | 1401 | |
| 1399 | 1402 | new_vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); |
| 1400 | 1403 | |
| @@ -1403,6 +1406,9 @@ static void try_odm_power_optimization_and_revalidate( · 2 unmodified lines | ||
| 1403 | 1406 | memset(merge, 0, MAX_PIPES * sizeof(bool)); |
| 1404 | 1407 | *vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, new_vlevel, split, merge); |
| 1405 | 1408 | context->bw_ctx.dml.vba.VoltageLevel = *vlevel; |
| 1409 | + } else { | |
| 1410 | + for (i = 0; i < pipe_cnt; i++) | |
| 1411 | + pipes[i].pipe.dest.odm_combine_policy = cur_policy[i]; | |
| 1406 | 1412 | } |
| 1407 | 1413 | } |
| 1408 | 1414 | |
| @@ -1580,7 +1586,7 @@ static void dcn32_full_validate_bw_helper(struct dc *dc, · 171 unmodified lines | ||
| 1580 | 1586 | } |
| 1581 | 1587 | } |
| 1582 | 1588 | |
| 1583 | − if (should_allow_odm_power_optimization(dc, context, vba, split, merge)) | |
| 1589 | + if (should_apply_odm_power_optimization(dc, context, vba, split, merge)) | |
| 1584 | 1590 | try_odm_power_optimization_and_revalidate( |
| 1585 | 1591 | dc, context, pipes, split, merge, vlevel, *pipe_cnt); |
| 1586 | 1592 | |
| @@ -2209,7 +2215,8 @@ bool dcn32_internal_validate_bw(struct dc *dc, · 622 unmodified lines | ||
| 2209 | 2215 | int i; |
| 2210 | 2216 | |
| 2211 | 2217 | pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate); |
| 2212 | − dcn32_update_dml_pipes_odm_policy_based_on_context(dc, context, pipes); | |
| 2218 | + if (!dc->config.enable_windowed_mpo_odm) | |
| 2219 | + dcn32_update_dml_pipes_odm_policy_based_on_context(dc, context, pipes); | |
| 2213 | 2220 | |
| 2214 | 2221 | /* repopulate_pipes = 1 means the pipes were either split or merged. In this case |
| 2215 | 2222 | * we have to re-calculate the DET allocation and run through DML once more to |
| @@ -2753,7 +2760,7 @@ static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk · 537 unmodified lines | ||
| 2753 | 2760 | struct _vcs_dpi_voltage_scaling_st entry = {0}; |
| 2754 | 2761 | struct clk_limit_table_entry max_clk_data = {0}; |
| 2755 | 2762 | |
| 2756 | − unsigned int min_dcfclk_mhz = 199, min_fclk_mhz = 299; | |
| 2763 | + unsigned int min_dcfclk_mhz = 399, min_fclk_mhz = 599; | |
| 2757 | 2764 | |
| 2758 | 2765 | static const unsigned int num_dcfclk_stas = 5; |
| 2759 | 2766 | unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564}; |
| @@ -164,8 +164,8 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_5_soc = { · 163 unmodified lines | ||
| 164 | 164 | }, |
| 165 | 165 | }, |
| 166 | 166 | .num_states = 5, |
| 167 | − .sr_exit_time_us = 14.0, | |
| 168 | − .sr_enter_plus_exit_time_us = 16.0, | |
| 167 | + .sr_exit_time_us = 28.0, | |
| 168 | + .sr_enter_plus_exit_time_us = 30.0, | |
| 169 | 169 | .sr_exit_z8_time_us = 210.0, |
| 170 | 170 | .sr_enter_plus_exit_z8_time_us = 320.0, |
| 171 | 171 | .fclk_change_latency_us = 24.0, |
| @@ -583,9 +583,9 @@ void dcn35_decide_zstate_support(struct dc *dc, struct dc_state *context) · 411 unmodified lines | ||
| 583 | 583 | plane_count++; |
| 584 | 584 | } |
| 585 | 585 | |
| 586 | − if (plane_count == 0) { | |
| 586 | + if (context->stream_count == 0 || plane_count == 0) { | |
| 587 | 587 | support = DCN_ZSTATE_SUPPORT_ALLOW; |
| 588 | − } else if (plane_count == 1 && context->stream_count == 1 && context->streams[0]->signal == SIGNAL_TYPE_EDP) { | |
| 588 | + } else if (context->stream_count == 1 && context->streams[0]->signal == SIGNAL_TYPE_EDP) { | |
| 589 | 589 | struct dc_link *link = context->streams[0]->sink->link; |
| 590 | 590 | bool is_pwrseq0 = link && link->link_index == 0; |
| 591 | 591 | bool is_psr1 = link && link->psr_settings.psr_version == DC_PSR_VERSION_1 && !link->panel_config.psr.disable_psr; |
| @@ -141,14 +141,33 @@ static unsigned int find_pipes_assigned_to_plane(struct dml2_context *ctx, · 140 unmodified lines | ||
| 141 | 141 | { |
| 142 | 142 | int i; |
| 143 | 143 | unsigned int num_found = 0; |
| 144 | − unsigned int plane_id_assigned_to_pipe; | |
| 144 | + unsigned int plane_id_assigned_to_pipe = -1; | |
| 145 | 145 | |
| 146 | 146 | for (i = 0; i < ctx->config.dcn_pipe_count; i++) { |
| 147 | − if (state->res_ctx.pipe_ctx[i].plane_state && get_plane_id(ctx, state, state->res_ctx.pipe_ctx[i].plane_state, | |
| 148 | − state->res_ctx.pipe_ctx[i].stream->stream_id, | |
| 149 | − ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[state->res_ctx.pipe_ctx[i].pipe_idx], &plane_id_assigned_to_pipe)) { | |
| 150 | − if (plane_id_assigned_to_pipe == plane_id) | |
| 151 | − pipes[num_found++] = i; | |
| 147 | + struct pipe_ctx *pipe = &state->res_ctx.pipe_ctx[i]; | |
| 148 | + | |
| 149 | + if (!pipe->plane_state || !pipe->stream) | |
| 150 | + continue; | |
| 151 | + | |
| 152 | + get_plane_id(ctx, state, pipe->plane_state, pipe->stream->stream_id, | |
| 153 | + ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[pipe->pipe_idx], | |
| 154 | + &plane_id_assigned_to_pipe); | |
| 155 | + if (plane_id_assigned_to_pipe == plane_id && !pipe->prev_odm_pipe | |
| 156 | + && (!pipe->top_pipe || pipe->top_pipe->plane_state != pipe->plane_state)) { | |
| 157 | + while (pipe) { | |
| 158 | + struct pipe_ctx *mpc_pipe = pipe; | |
| 159 | + | |
| 160 | + while (mpc_pipe) { | |
| 161 | + pipes[num_found++] = mpc_pipe->pipe_idx; | |
| 162 | + mpc_pipe = mpc_pipe->bottom_pipe; | |
| 163 | + if (!mpc_pipe) | |
| 164 | + break; | |
| 165 | + if (mpc_pipe->plane_state != pipe->plane_state) | |
| 166 | + mpc_pipe = NULL; | |
| 167 | + } | |
| 168 | + pipe = pipe->next_odm_pipe; | |
| 169 | + } | |
| 170 | + break; | |
| 152 | 171 | } |
| 153 | 172 | } |
| 154 | 173 | |
| @@ -566,8 +585,14 @@ static unsigned int find_pipes_assigned_to_stream(struct dml2_context *ctx, stru · 411 unmodified lines | ||
| 566 | 585 | unsigned int num_found = 0; |
| 567 | 586 | |
| 568 | 587 | for (i = 0; i < ctx->config.dcn_pipe_count; i++) { |
| 569 | − if (state->res_ctx.pipe_ctx[i].stream && state->res_ctx.pipe_ctx[i].stream->stream_id == stream_id) { | |
| 570 | − pipes[num_found++] = i; | |
| 588 | + struct pipe_ctx *pipe = &state->res_ctx.pipe_ctx[i]; | |
| 589 | + | |
| 590 | + if (pipe->stream && pipe->stream->stream_id == stream_id && !pipe->top_pipe && !pipe->prev_odm_pipe) { | |
| 591 | + while (pipe) { | |
| 592 | + pipes[num_found++] = pipe->pipe_idx; | |
| 593 | + pipe = pipe->next_odm_pipe; | |
| 594 | + } | |
| 595 | + break; | |
| 571 | 596 | } |
| 572 | 597 | } |
| 573 | 598 | |
| @@ -341,9 +341,6 @@ void dml2_init_soc_states(struct dml2_context *dml2, const struct dc *in_dc, · 340 unmodified lines | ||
| 341 | 341 | break; |
| 342 | 342 | } |
| 343 | 343 | |
| 344 | − if (dml2->config.bbox_overrides.clks_table.num_states) | |
| 345 | − p->in_states->num_states = dml2->config.bbox_overrides.clks_table.num_states; | |
| 346 | − | |
| 347 | 344 | /* Override from passed values, if available */ |
| 348 | 345 | for (i = 0; i < p->in_states->num_states; i++) { |
| 349 | 346 | if (dml2->config.bbox_overrides.sr_exit_latency_us) { |
| @@ -400,6 +397,7 @@ void dml2_init_soc_states(struct dml2_context *dml2, const struct dc *in_dc, · 50 unmodified lines | ||
| 400 | 397 | } |
| 401 | 398 | /* Copy clocks tables entries, if available */ |
| 402 | 399 | if (dml2->config.bbox_overrides.clks_table.num_states) { |
| 400 | + p->in_states->num_states = dml2->config.bbox_overrides.clks_table.num_states; | |
| 403 | 401 | |
| 404 | 402 | for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels; i++) { |
| 405 | 403 | p->in_states->state_array[i].dcfclk_mhz = dml2->config.bbox_overrides.clks_table.clk_entries[i].dcfclk_mhz; |
| @@ -793,35 +791,28 @@ static void populate_dml_surface_cfg_from_plane_state(enum dml_project_id dml2_p · 387 unmodified lines | ||
| 793 | 791 | } |
| 794 | 792 | } |
| 795 | 793 | |
| 796 | −/*TODO no support for mpc combine, need rework - should calculate scaling params based on plane+stream*/ | |
| 797 | −static struct scaler_data get_scaler_data_for_plane(const struct dc_plane_state *in, const struct dc_state *context) | |
| 794 | +static struct scaler_data get_scaler_data_for_plane(const struct dc_plane_state *in, struct dc_state *context) | |
| 798 | 795 | { |
| 799 | 796 | int i; |
| 800 | − struct scaler_data data = { 0 }; | |
| 797 | + struct pipe_ctx *temp_pipe = &context->res_ctx.temp_pipe; | |
| 798 | + | |
| 799 | + memset(temp_pipe, 0, sizeof(struct pipe_ctx)); | |
| 801 | 800 | |
| 802 | 801 | for (i = 0; i < MAX_PIPES; i++) { |
| 803 | 802 | const struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; |
| 804 | 803 | |
| 805 | 804 | if (pipe->plane_state == in && !pipe->prev_odm_pipe) { |
| 806 | − const struct pipe_ctx *next_pipe = pipe->next_odm_pipe; | |
| 807 | − | |
| 808 | − data = context->res_ctx.pipe_ctx[i].plane_res.scl_data; | |
| 809 | − while (next_pipe) { | |
| 810 | − data.h_active += next_pipe->plane_res.scl_data.h_active; | |
| 811 | − data.recout.width += next_pipe->plane_res.scl_data.recout.width; | |
| 812 | − if (in->rotation == ROTATION_ANGLE_0 || in->rotation == ROTATION_ANGLE_180) { | |
| 813 | − data.viewport.width += next_pipe->plane_res.scl_data.viewport.width; | |
| 814 | − } else { | |
| 815 | − data.viewport.height += next_pipe->plane_res.scl_data.viewport.height; | |
| 816 | − } | |
| 817 | − next_pipe = next_pipe->next_odm_pipe; | |
| 818 | − } | |
| 805 | + temp_pipe->stream = pipe->stream; | |
| 806 | + temp_pipe->plane_state = pipe->plane_state; | |
| 807 | + temp_pipe->plane_res.scl_data.taps = pipe->plane_res.scl_data.taps; | |
| 808 | + | |
| 809 | + resource_build_scaling_params(temp_pipe); | |
| 819 | 810 | break; |
| 820 | 811 | } |
| 821 | 812 | } |
| 822 | 813 | |
| 823 | 814 | ASSERT(i < MAX_PIPES); |
| 824 | − return data; | |
| 815 | + return temp_pipe->plane_res.scl_data; | |
| 825 | 816 | } |
| 826 | 817 | |
| 827 | 818 | static void populate_dummy_dml_plane_cfg(struct dml_plane_cfg_st *out, unsigned int location, const struct dc_stream_state *in) |
| @@ -866,7 +857,7 @@ static void populate_dummy_dml_plane_cfg(struct dml_plane_cfg_st *out, unsigned · 38 unmodified lines | ||
| 866 | 857 | out->ScalerEnabled[location] = false; |
| 867 | 858 | } |
| 868 | 859 | |
| 869 | −static void populate_dml_plane_cfg_from_plane_state(struct dml_plane_cfg_st *out, unsigned int location, const struct dc_plane_state *in, const struct dc_state *context) | |
| 860 | +static void populate_dml_plane_cfg_from_plane_state(struct dml_plane_cfg_st *out, unsigned int location, const struct dc_plane_state *in, struct dc_state *context) | |
| 870 | 861 | { |
| 871 | 862 | const struct scaler_data scaler_data = get_scaler_data_for_plane(in, context); |
| 872 | 863 | |
| @@ -234,7 +234,7 @@ static bool get_plane_id(struct dml2_context *dml2, const struct dc_state *state · 233 unmodified lines | ||
| 234 | 234 | if (state->streams[i]->stream_id == stream_id) { |
| 235 | 235 | for (j = 0; j < state->stream_status[i].plane_count; j++) { |
| 236 | 236 | if (state->stream_status[i].plane_states[j] == plane && |
| 237 | − (!is_plane_duplicate || (is_plane_duplicate && (j == plane_index)))) { | |
| 237 | + (!is_plane_duplicate || (j == plane_index))) { | |
| 238 | 238 | *plane_id = (i << 16) | j; |
| 239 | 239 | return true; |
| 240 | 240 | } |
| @@ -137,6 +137,11 @@ uint32_t dc_bandwidth_in_kbps_from_timing( · 136 unmodified lines | ||
| 137 | 137 | if (link_encoding == DC_LINK_ENCODING_DP_128b_132b) |
| 138 | 138 | kbps = apply_128b_132b_stream_overhead(timing, kbps); |
| 139 | 139 | |
| 140 | + if (link_encoding == DC_LINK_ENCODING_HDMI_FRL && | |
| 141 | + timing->vic == 0 && timing->hdmi_vic == 0 && | |
| 142 | + timing->frl_uncompressed_video_bandwidth_in_kbps != 0) | |
| 143 | + kbps = timing->frl_uncompressed_video_bandwidth_in_kbps; | |
| 144 | + | |
| 140 | 145 | return kbps; |
| 141 | 146 | } |
| 142 | 147 | |
| @@ -1183,9 +1183,9 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx) · 1182 unmodified lines | ||
| 1183 | 1183 | dto_params.timing = &pipe_ctx->stream->timing; |
| 1184 | 1184 | dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst; |
| 1185 | 1185 | if (dccg) { |
| 1186 | − dccg->funcs->set_dtbclk_dto(dccg, &dto_params); | |
| 1187 | 1186 | dccg->funcs->disable_symclk32_se(dccg, dp_hpo_inst); |
| 1188 | 1187 | dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst, dp_hpo_inst); |
| 1188 | + dccg->funcs->set_dtbclk_dto(dccg, &dto_params); | |
| 1189 | 1189 | } |
| 1190 | 1190 | } else if (dccg && dccg->funcs->disable_symclk_se) { |
| 1191 | 1191 | dccg->funcs->disable_symclk_se(dccg, stream_enc->stream_enc_inst, |
| @@ -1291,6 +1291,46 @@ static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id) · 99 unmodified lines | ||
| 1291 | 1291 | } |
| 1292 | 1292 | } |
| 1293 | 1293 | |
| 1294 | +static void populate_audio_dp_link_info( | |
| 1295 | + const struct pipe_ctx *pipe_ctx, | |
| 1296 | + struct audio_dp_link_info *dp_link_info) | |
| 1297 | +{ | |
| 1298 | + const struct dc_stream_state *stream = pipe_ctx->stream; | |
| 1299 | + const struct dc_link *link = stream->link; | |
| 1300 | + struct fixed31_32 link_bw_kbps; | |
| 1301 | + | |
| 1302 | + dp_link_info->encoding = link->dc->link_srv->dp_get_encoding_format( | |
| 1303 | + &pipe_ctx->link_config.dp_link_settings); | |
| 1304 | + dp_link_info->is_mst = (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST); | |
| 1305 | + dp_link_info->lane_count = pipe_ctx->link_config.dp_link_settings.lane_count; | |
| 1306 | + dp_link_info->link_rate = pipe_ctx->link_config.dp_link_settings.link_rate; | |
| 1307 | + | |
| 1308 | + link_bw_kbps = dc_fixpt_from_int(dc_link_bandwidth_kbps(link, | |
| 1309 | + &pipe_ctx->link_config.dp_link_settings)); | |
| 1310 | + | |
| 1311 | + /* For audio stream calculations, the video stream should not include FEC or SSC | |
| 1312 | + * in order to get the most pessimistic values. | |
| 1313 | + */ | |
| 1314 | + if (dp_link_info->encoding == DP_8b_10b_ENCODING && | |
| 1315 | + link->dc->link_srv->dp_is_fec_supported(link)) { | |
| 1316 | + link_bw_kbps = dc_fixpt_mul(link_bw_kbps, | |
| 1317 | + dc_fixpt_from_fraction(100, DATA_EFFICIENCY_8b_10b_FEC_EFFICIENCY_x100)); | |
| 1318 | + } else if (dp_link_info->encoding == DP_128b_132b_ENCODING) { | |
| 1319 | + link_bw_kbps = dc_fixpt_mul(link_bw_kbps, | |
| 1320 | + dc_fixpt_from_fraction(10000, 9975)); /* 99.75% SSC overhead*/ | |
| 1321 | + } | |
| 1322 | + | |
| 1323 | + dp_link_info->link_bandwidth_kbps = dc_fixpt_floor(link_bw_kbps); | |
| 1324 | + | |
| 1325 | + /* HW minimum for 128b/132b HBlank is 4 frame symbols. | |
| 1326 | + * TODO: Plumb the actual programmed HBlank min symbol width to here. | |
| 1327 | + */ | |
| 1328 | + if (dp_link_info->encoding == DP_128b_132b_ENCODING) | |
| 1329 | + dp_link_info->hblank_min_symbol_width = 4; | |
| 1330 | + else | |
| 1331 | + dp_link_info->hblank_min_symbol_width = 0; | |
| 1332 | +} | |
| 1333 | + | |
| 1294 | 1334 | static void build_audio_output( |
| 1295 | 1335 | struct dc_state *state, |
| 1296 | 1336 | const struct pipe_ctx *pipe_ctx, |
| @@ -1338,6 +1378,15 @@ static void build_audio_output( · 41 unmodified lines | ||
| 1338 | 1378 | audio_output->crtc_info.calculated_pixel_clock_100Hz = |
| 1339 | 1379 | pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz; |
| 1340 | 1380 | |
| 1381 | + audio_output->crtc_info.pixel_encoding = | |
| 1382 | + stream->timing.pixel_encoding; | |
| 1383 | + | |
| 1384 | + audio_output->crtc_info.dsc_bits_per_pixel = | |
| 1385 | + stream->timing.dsc_cfg.bits_per_pixel; | |
| 1386 | + | |
| 1387 | + audio_output->crtc_info.dsc_num_slices = | |
| 1388 | + stream->timing.dsc_cfg.num_slices_h; | |
| 1389 | + | |
| 1341 | 1390 | /*for HDMI, audio ACR is with deep color ratio factor*/ |
| 1342 | 1391 | if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) && |
| 1343 | 1392 | audio_output->crtc_info.requested_pixel_clock_100Hz == |
| @@ -1371,6 +1420,10 @@ static void build_audio_output( · 27 unmodified lines | ||
| 1371 | 1420 | |
| 1372 | 1421 | audio_output->pll_info.ss_percentage = |
| 1373 | 1422 | pipe_ctx->pll_settings.ss_percentage; |
| 1423 | + | |
| 1424 | + if (dc_is_dp_signal(pipe_ctx->stream->signal)) { | |
| 1425 | + populate_audio_dp_link_info(pipe_ctx, &audio_output->dp_link_info); | |
| 1426 | + } | |
| 1374 | 1427 | } |
| 1375 | 1428 | |
| 1376 | 1429 | static void program_scaler(const struct dc *dc, |
| @@ -1476,7 +1529,7 @@ static enum dc_status dce110_enable_stream_timing( · 99 unmodified lines | ||
| 1476 | 1529 | return DC_OK; |
| 1477 | 1530 | } |
| 1478 | 1531 | |
| 1479 | −static enum dc_status apply_single_controller_ctx_to_hw( | |
| 1532 | +enum dc_status dce110_apply_single_controller_ctx_to_hw( | |
| 1480 | 1533 | struct pipe_ctx *pipe_ctx, |
| 1481 | 1534 | struct dc_state *context, |
| 1482 | 1535 | struct dc *dc) |
| @@ -1507,7 +1560,8 @@ static enum dc_status apply_single_controller_ctx_to_hw( · 24 unmodified lines | ||
| 1507 | 1560 | pipe_ctx->stream_res.audio, |
| 1508 | 1561 | pipe_ctx->stream->signal, |
| 1509 | 1562 | &audio_output.crtc_info, |
| 1510 | − &pipe_ctx->stream->audio_info); | |
| 1563 | + &pipe_ctx->stream->audio_info, | |
| 1564 | + &audio_output.dp_link_info); | |
| 1511 | 1565 | } |
| 1512 | 1566 | |
| 1513 | 1567 | /* make sure no pipes syncd to the pipe being enabled */ |
| @@ -2302,7 +2356,7 @@ enum dc_status dce110_apply_ctx_to_hw( · 788 unmodified lines | ||
| 2302 | 2356 | if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe) |
| 2303 | 2357 | continue; |
| 2304 | 2358 | |
| 2305 | − status = apply_single_controller_ctx_to_hw( | |
| 2359 | + status = dce110_apply_single_controller_ctx_to_hw( | |
| 2306 | 2360 | pipe_ctx, |
| 2307 | 2361 | context, |
| 2308 | 2362 | dc); |
| @@ -39,6 +39,10 @@ enum dc_status dce110_apply_ctx_to_hw( · 38 unmodified lines | ||
| 39 | 39 | struct dc *dc, |
| 40 | 40 | struct dc_state *context); |
| 41 | 41 | |
| 42 | +enum dc_status dce110_apply_single_controller_ctx_to_hw( | |
| 43 | + struct pipe_ctx *pipe_ctx, | |
| 44 | + struct dc_state *context, | |
| 45 | + struct dc *dc); | |
| 42 | 46 | |
| 43 | 47 | void dce110_enable_stream(struct pipe_ctx *pipe_ctx); |
| 44 | 48 | |
| @@ -283,33 +283,33 @@ static void dcn10_log_hubp_states(struct dc *dc, void *log_ctx) · 282 unmodified lines | ||
| 283 | 283 | DTN_INFO("\n"); |
| 284 | 284 | } |
| 285 | 285 | |
| 286 | −void dcn10_log_hw_state(struct dc *dc, | |
| 287 | − struct dc_log_buffer_ctx *log_ctx) | |
| 286 | +static void dcn10_log_color_state(struct dc *dc, | |
| 287 | + struct dc_log_buffer_ctx *log_ctx) | |
| 288 | 288 | { |
| 289 | 289 | struct dc_context *dc_ctx = dc->ctx; |
| 290 | 290 | struct resource_pool *pool = dc->res_pool; |
| 291 | 291 | int i; |
| 292 | 292 | |
| 293 | − DTN_INFO_BEGIN(); | |
| 294 | − | |
| 295 | − dcn10_log_hubbub_state(dc, log_ctx); | |
| 296 | − | |
| 297 | − dcn10_log_hubp_states(dc, log_ctx); | |
| 298 | − | |
| 299 | − DTN_INFO("DPP: IGAM format IGAM mode DGAM mode RGAM mode" | |
| 300 | − " GAMUT mode C11 C12 C13 C14 C21 C22 C23 C24 " | |
| 301 | − "C31 C32 C33 C34\n"); | |
| 293 | + DTN_INFO("DPP: IGAM format IGAM mode DGAM mode RGAM mode" | |
| 294 | + " GAMUT adjust " | |
| 295 | + "C11 C12 C13 C14 " | |
| 296 | + "C21 C22 C23 C24 " | |
| 297 | + "C31 C32 C33 C34 \n"); | |
| 302 | 298 | for (i = 0; i < pool->pipe_count; i++) { |
| 303 | 299 | struct dpp *dpp = pool->dpps[i]; |
| 304 | 300 | struct dcn_dpp_state s = {0}; |
| 305 | 301 | |
| 306 | 302 | dpp->funcs->dpp_read_state(dpp, &s); |
| 303 | + dpp->funcs->dpp_get_gamut_remap(dpp, &s.gamut_remap); | |
| 307 | 304 | |
| 308 | 305 | if (!s.is_enabled) |
| 309 | 306 | continue; |
| 310 | 307 | |
| 311 | − DTN_INFO("[%2d]: %11xh %-11s %-11s %-11s" | |
| 312 | − "%8x %08xh %08xh %08xh %08xh %08xh %08xh", | |
| 308 | + DTN_INFO("[%2d]: %11xh %11s %9s %9s" | |
| 309 | + " %12s " | |
| 310 | + "%010lld %010lld %010lld %010lld " | |
| 311 | + "%010lld %010lld %010lld %010lld " | |
| 312 | + "%010lld %010lld %010lld %010lld", | |
| 313 | 313 | dpp->inst, |
| 314 | 314 | s.igam_input_format, |
| 315 | 315 | (s.igam_lut_mode == 0) ? "BypassFixed" : |
| @@ -329,16 +329,42 @@ void dcn10_log_hw_state(struct dc *dc, · 13 unmodified lines | ||
| 329 | 329 | ((s.rgam_lut_mode == 3) ? "RAM" : |
| 330 | 330 | ((s.rgam_lut_mode == 4) ? "RAM" : |
| 331 | 331 | "Unknown")))), |
| 332 | − s.gamut_remap_mode, | |
| 333 | − s.gamut_remap_c11_c12, | |
| 334 | − s.gamut_remap_c13_c14, | |
| 335 | − s.gamut_remap_c21_c22, | |
| 336 | − s.gamut_remap_c23_c24, | |
| 337 | − s.gamut_remap_c31_c32, | |
| 338 | − s.gamut_remap_c33_c34); | |
| 332 | + (s.gamut_remap.gamut_adjust_type == 0) ? "Bypass" : | |
| 333 | + ((s.gamut_remap.gamut_adjust_type == 1) ? "HW" : | |
| 334 | + "SW"), | |
| 335 | + s.gamut_remap.temperature_matrix[0].value, | |
| 336 | + s.gamut_remap.temperature_matrix[1].value, | |
| 337 | + s.gamut_remap.temperature_matrix[2].value, | |
| 338 | + s.gamut_remap.temperature_matrix[3].value, | |
| 339 | + s.gamut_remap.temperature_matrix[4].value, | |
| 340 | + s.gamut_remap.temperature_matrix[5].value, | |
| 341 | + s.gamut_remap.temperature_matrix[6].value, | |
| 342 | + s.gamut_remap.temperature_matrix[7].value, | |
| 343 | + s.gamut_remap.temperature_matrix[8].value, | |
| 344 | + s.gamut_remap.temperature_matrix[9].value, | |
| 345 | + s.gamut_remap.temperature_matrix[10].value, | |
| 346 | + s.gamut_remap.temperature_matrix[11].value); | |
| 339 | 347 | DTN_INFO("\n"); |
| 340 | 348 | } |
| 341 | 349 | DTN_INFO("\n"); |
| 350 | + DTN_INFO("DPP Color Caps: input_lut_shared:%d icsc:%d" | |
| 351 | + " dgam_ram:%d dgam_rom: srgb:%d,bt2020:%d,gamma2_2:%d,pq:%d,hlg:%d" | |
| 352 | + " post_csc:%d gamcor:%d dgam_rom_for_yuv:%d 3d_lut:%d" | |
| 353 | + " blnd_lut:%d oscs:%d\n\n", | |
| 354 | + dc->caps.color.dpp.input_lut_shared, | |
| 355 | + dc->caps.color.dpp.icsc, | |
| 356 | + dc->caps.color.dpp.dgam_ram, | |
| 357 | + dc->caps.color.dpp.dgam_rom_caps.srgb, | |
| 358 | + dc->caps.color.dpp.dgam_rom_caps.bt2020, | |
| 359 | + dc->caps.color.dpp.dgam_rom_caps.gamma2_2, | |
| 360 | + dc->caps.color.dpp.dgam_rom_caps.pq, | |
| 361 | + dc->caps.color.dpp.dgam_rom_caps.hlg, | |
| 362 | + dc->caps.color.dpp.post_csc, | |
| 363 | + dc->caps.color.dpp.gamma_corr, | |
| 364 | + dc->caps.color.dpp.dgam_rom_for_yuv, | |
| 365 | + dc->caps.color.dpp.hw_3d_lut, | |
| 366 | + dc->caps.color.dpp.ogam_ram, | |
| 367 | + dc->caps.color.dpp.ocsc); | |
| 342 | 368 | |
| 343 | 369 | DTN_INFO("MPCC: OPP DPP MPCCBOT MODE ALPHA_MODE PREMULT OVERLAP_ONLY IDLE\n"); |
| 344 | 370 | for (i = 0; i < pool->pipe_count; i++) { |
| @@ -352,6 +378,30 @@ void dcn10_log_hw_state(struct dc *dc, · 7 unmodified lines | ||
| 352 | 378 | s.idle); |
| 353 | 379 | } |
| 354 | 380 | DTN_INFO("\n"); |
| 381 | + DTN_INFO("MPC Color Caps: gamut_remap:%d, 3dlut:%d, ogam_ram:%d, ocsc:%d\n\n", | |
| 382 | + dc->caps.color.mpc.gamut_remap, | |
| 383 | + dc->caps.color.mpc.num_3dluts, | |
| 384 | + dc->caps.color.mpc.ogam_ram, | |
| 385 | + dc->caps.color.mpc.ocsc); | |
| 386 | +} | |
| 387 | + | |
| 388 | +void dcn10_log_hw_state(struct dc *dc, | |
| 389 | + struct dc_log_buffer_ctx *log_ctx) | |
| 390 | +{ | |
| 391 | + struct dc_context *dc_ctx = dc->ctx; | |
| 392 | + struct resource_pool *pool = dc->res_pool; | |
| 393 | + int i; | |
| 394 | + | |
| 395 | + DTN_INFO_BEGIN(); | |
| 396 | + | |
| 397 | + dcn10_log_hubbub_state(dc, log_ctx); | |
| 398 | + | |
| 399 | + dcn10_log_hubp_states(dc, log_ctx); | |
| 400 | + | |
| 401 | + if (dc->hwss.log_color_state) | |
| 402 | + dc->hwss.log_color_state(dc, log_ctx); | |
| 403 | + else | |
| 404 | + dcn10_log_color_state(dc, log_ctx); | |
| 355 | 405 | |
| 356 | 406 | DTN_INFO("OTG: v_bs v_be v_ss v_se vpol vmax vmin vmax_sel vmin_sel h_bs h_be h_ss h_se hpol htot vtot underflow blank_en\n"); |
| 357 | 407 | |
| @@ -1840,6 +1890,9 @@ bool dcn10_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, · 1482 unmodified lines | ||
| 1840 | 1890 | { |
| 1841 | 1891 | struct dpp *dpp = pipe_ctx->plane_res.dpp; |
| 1842 | 1892 | |
| 1893 | + if (!stream) | |
| 1894 | + return false; | |
| 1895 | + | |
| 1843 | 1896 | if (dpp == NULL) |
| 1844 | 1897 | return false; |
| 1845 | 1898 | |
| @@ -1862,8 +1915,8 @@ bool dcn10_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, · 16 unmodified lines | ||
| 1862 | 1915 | } else |
| 1863 | 1916 | dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_BYPASS); |
| 1864 | 1917 | |
| 1865 | − if (stream != NULL && stream->ctx != NULL && | |
| 1866 | − stream->out_transfer_func != NULL) { | |
| 1918 | + if (stream->ctx && | |
| 1919 | + stream->out_transfer_func) { | |
| 1867 | 1920 | log_tf(stream->ctx, |
| 1868 | 1921 | stream->out_transfer_func, |
| 1869 | 1922 | dpp->regamma_params.hw_points_num); |
| @@ -71,6 +71,112 @@ · 70 unmodified lines | ||
| 71 | 71 | #define FN(reg_name, field_name) \ |
| 72 | 72 | hws->shifts->field_name, hws->masks->field_name |
| 73 | 73 | |
| 74 | +void dcn20_log_color_state(struct dc *dc, | |
| 75 | + struct dc_log_buffer_ctx *log_ctx) | |
| 76 | +{ | |
| 77 | + struct dc_context *dc_ctx = dc->ctx; | |
| 78 | + struct resource_pool *pool = dc->res_pool; | |
| 79 | + int i; | |
| 80 | + | |
| 81 | + DTN_INFO("DPP: DGAM mode SHAPER mode 3DLUT mode 3DLUT bit depth" | |
| 82 | + " 3DLUT size RGAM mode GAMUT adjust " | |
| 83 | + "C11 C12 C13 C14 " | |
| 84 | + "C21 C22 C23 C24 " | |
| 85 | + "C31 C32 C33 C34 \n"); | |
| 86 | + | |
| 87 | + for (i = 0; i < pool->pipe_count; i++) { | |
| 88 | + struct dpp *dpp = pool->dpps[i]; | |
| 89 | + struct dcn_dpp_state s = {0}; | |
| 90 | + | |
| 91 | + dpp->funcs->dpp_read_state(dpp, &s); | |
| 92 | + dpp->funcs->dpp_get_gamut_remap(dpp, &s.gamut_remap); | |
| 93 | + | |
| 94 | + if (!s.is_enabled) | |
| 95 | + continue; | |
| 96 | + | |
| 97 | + DTN_INFO("[%2d]: %8s %11s %10s %15s %10s %9s %12s " | |
| 98 | + "%010lld %010lld %010lld %010lld " | |
| 99 | + "%010lld %010lld %010lld %010lld " | |
| 100 | + "%010lld %010lld %010lld %010lld", | |
| 101 | + dpp->inst, | |
| 102 | + (s.dgam_lut_mode == 0) ? "Bypass" : | |
| 103 | + ((s.dgam_lut_mode == 1) ? "sRGB" : | |
| 104 | + ((s.dgam_lut_mode == 2) ? "Ycc" : | |
| 105 | + ((s.dgam_lut_mode == 3) ? "RAM" : | |
| 106 | + ((s.dgam_lut_mode == 4) ? "RAM" : | |
| 107 | + "Unknown")))), | |
| 108 | + (s.shaper_lut_mode == 1) ? "RAM A" : | |
| 109 | + ((s.shaper_lut_mode == 2) ? "RAM B" : | |
| 110 | + "Bypass"), | |
| 111 | + (s.lut3d_mode == 1) ? "RAM A" : | |
| 112 | + ((s.lut3d_mode == 2) ? "RAM B" : | |
| 113 | + "Bypass"), | |
| 114 | + (s.lut3d_bit_depth <= 0) ? "12-bit" : "10-bit", | |
| 115 | + (s.lut3d_size == 0) ? "17x17x17" : "9x9x9", | |
| 116 | + (s.rgam_lut_mode == 1) ? "RAM A" : | |
| 117 | + ((s.rgam_lut_mode == 1) ? "RAM B" : "Bypass"), | |
| 118 | + (s.gamut_remap.gamut_adjust_type == 0) ? "Bypass" : | |
| 119 | + ((s.gamut_remap.gamut_adjust_type == 1) ? "HW" : | |
| 120 | + "SW"), | |
| 121 | + s.gamut_remap.temperature_matrix[0].value, | |
| 122 | + s.gamut_remap.temperature_matrix[1].value, | |
| 123 | + s.gamut_remap.temperature_matrix[2].value, | |
| 124 | + s.gamut_remap.temperature_matrix[3].value, | |
| 125 | + s.gamut_remap.temperature_matrix[4].value, | |
| 126 | + s.gamut_remap.temperature_matrix[5].value, | |
| 127 | + s.gamut_remap.temperature_matrix[6].value, | |
| 128 | + s.gamut_remap.temperature_matrix[7].value, | |
| 129 | + s.gamut_remap.temperature_matrix[8].value, | |
| 130 | + s.gamut_remap.temperature_matrix[9].value, | |
| 131 | + s.gamut_remap.temperature_matrix[10].value, | |
| 132 | + s.gamut_remap.temperature_matrix[11].value); | |
| 133 | + DTN_INFO("\n"); | |
| 134 | + } | |
| 135 | + DTN_INFO("\n"); | |
| 136 | + DTN_INFO("DPP Color Caps: input_lut_shared:%d icsc:%d" | |
| 137 | + " dgam_ram:%d dgam_rom: srgb:%d,bt2020:%d,gamma2_2:%d,pq:%d,hlg:%d" | |
| 138 | + " post_csc:%d gamcor:%d dgam_rom_for_yuv:%d 3d_lut:%d" | |
| 139 | + " blnd_lut:%d oscs:%d\n\n", | |
| 140 | + dc->caps.color.dpp.input_lut_shared, | |
| 141 | + dc->caps.color.dpp.icsc, | |
| 142 | + dc->caps.color.dpp.dgam_ram, | |
| 143 | + dc->caps.color.dpp.dgam_rom_caps.srgb, | |
| 144 | + dc->caps.color.dpp.dgam_rom_caps.bt2020, | |
| 145 | + dc->caps.color.dpp.dgam_rom_caps.gamma2_2, | |
| 146 | + dc->caps.color.dpp.dgam_rom_caps.pq, | |
| 147 | + dc->caps.color.dpp.dgam_rom_caps.hlg, | |
| 148 | + dc->caps.color.dpp.post_csc, | |
| 149 | + dc->caps.color.dpp.gamma_corr, | |
| 150 | + dc->caps.color.dpp.dgam_rom_for_yuv, | |
| 151 | + dc->caps.color.dpp.hw_3d_lut, | |
| 152 | + dc->caps.color.dpp.ogam_ram, | |
| 153 | + dc->caps.color.dpp.ocsc); | |
| 154 | + | |
| 155 | + DTN_INFO("MPCC: OPP DPP MPCCBOT MODE ALPHA_MODE PREMULT OVERLAP_ONLY IDLE" | |
| 156 | + " OGAM mode\n"); | |
| 157 | + | |
| 158 | + for (i = 0; i < pool->pipe_count; i++) { | |
| 159 | + struct mpcc_state s = {0}; | |
| 160 | + | |
| 161 | + pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s); | |
| 162 | + if (s.opp_id != 0xf) | |
| 163 | + DTN_INFO("[%2d]: %2xh %2xh %6xh %4d %10d %7d %12d %4d %9s\n", | |
| 164 | + i, s.opp_id, s.dpp_id, s.bot_mpcc_id, | |
| 165 | + s.mode, s.alpha_mode, s.pre_multiplied_alpha, s.overlap_only, | |
| 166 | + s.idle, | |
| 167 | + (s.rgam_mode == 1) ? "RAM A" : | |
| 168 | + ((s.rgam_mode == 2) ? "RAM B" : | |
| 169 | + "Bypass")); | |
| 170 | + } | |
| 171 | + DTN_INFO("\n"); | |
| 172 | + DTN_INFO("MPC Color Caps: gamut_remap:%d, 3dlut:%d, ogam_ram:%d, ocsc:%d\n\n", | |
| 173 | + dc->caps.color.mpc.gamut_remap, | |
| 174 | + dc->caps.color.mpc.num_3dluts, | |
| 175 | + dc->caps.color.mpc.ogam_ram, | |
| 176 | + dc->caps.color.mpc.ocsc); | |
| 177 | +} | |
| 178 | + | |
| 179 | + | |
| 74 | 180 | static int find_free_gsl_group(const struct dc *dc) |
| 75 | 181 | { |
| 76 | 182 | if (dc->res_pool->gsl_groups.gsl_0 == 0) |
| @@ -1467,7 +1573,8 @@ static void dcn20_detect_pipe_changes(struct dc_state *old_state, · 1390 unmodified lines | ||
| 1467 | 1573 | * makes this assumption at the moment with how hubp reset is matched to |
| 1468 | 1574 | * same index mpcc reset. |
| 1469 | 1575 | */ |
| 1470 | − if (old_pipe->stream_res.opp != new_pipe->stream_res.opp) | |
| 1576 | + if (old_pipe->stream_res.opp != new_pipe->stream_res.opp || | |
| 1577 | + old_pipe->stream_res.left_edge_extra_pixel != new_pipe->stream_res.left_edge_extra_pixel) | |
| 1471 | 1578 | new_pipe->update_flags.bits.opp_changed = 1; |
| 1472 | 1579 | if (old_pipe->stream_res.tg != new_pipe->stream_res.tg) |
| 1473 | 1580 | new_pipe->update_flags.bits.tg_changed = 1; |
| @@ -1853,6 +1960,10 @@ static void dcn20_program_pipe( · 379 unmodified lines | ||
| 1853 | 1960 | pipe_ctx->stream_res.opp, |
| 1854 | 1961 | &pipe_ctx->stream->bit_depth_params, |
| 1855 | 1962 | &pipe_ctx->stream->clamping); |
| 1963 | + | |
| 1964 | + pipe_ctx->stream_res.opp->funcs->opp_program_left_edge_extra_pixel( | |
| 1965 | + pipe_ctx->stream_res.opp, | |
| 1966 | + pipe_ctx->stream_res.left_edge_extra_pixel); | |
| 1856 | 1967 | } |
| 1857 | 1968 | |
| 1858 | 1969 | /* Set ABM pipe after other pipe configurations done */ |
| @@ -1958,7 +2069,6 @@ void dcn20_program_front_end_for_ctx( · 99 unmodified lines | ||
| 1958 | 2069 | && context->res_ctx.pipe_ctx[i].stream) |
| 1959 | 2070 | hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true); |
| 1960 | 2071 | |
| 1961 | − | |
| 1962 | 2072 | /* Disconnect mpcc */ |
| 1963 | 2073 | for (i = 0; i < dc->res_pool->pipe_count; i++) |
| 1964 | 2074 | if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable |
| @@ -2561,7 +2671,7 @@ void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx) · 596 unmodified lines | ||
| 2561 | 2671 | tg->funcs->setup_vertical_interrupt2(tg, start_line); |
| 2562 | 2672 | } |
| 2563 | 2673 | |
| 2564 | −static void dcn20_reset_back_end_for_pipe( | |
| 2674 | +void dcn20_reset_back_end_for_pipe( | |
| 2565 | 2675 | struct dc *dc, |
| 2566 | 2676 | struct pipe_ctx *pipe_ctx, |
| 2567 | 2677 | struct dc_state *context) |
| @@ -2790,18 +2900,17 @@ void dcn20_enable_stream(struct pipe_ctx *pipe_ctx) · 222 unmodified lines | ||
| 2790 | 2900 | } |
| 2791 | 2901 | |
| 2792 | 2902 | if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { |
| 2793 | − dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst; | |
| 2794 | − dccg->funcs->set_dpstreamclk(dccg, DTBCLK0, tg->inst, dp_hpo_inst); | |
| 2795 | − | |
| 2796 | − phyd32clk = get_phyd32clk_src(link); | |
| 2797 | − dccg->funcs->enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk); | |
| 2798 | − | |
| 2799 | 2903 | dto_params.otg_inst = tg->inst; |
| 2800 | 2904 | dto_params.pixclk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10; |
| 2801 | 2905 | dto_params.num_odm_segments = get_odm_segment_count(pipe_ctx); |
| 2802 | 2906 | dto_params.timing = &pipe_ctx->stream->timing; |
| 2803 | 2907 | dto_params.ref_dtbclk_khz = dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr); |
| 2804 | 2908 | dccg->funcs->set_dtbclk_dto(dccg, &dto_params); |
| 2909 | + dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst; | |
| 2910 | + dccg->funcs->set_dpstreamclk(dccg, DTBCLK0, tg->inst, dp_hpo_inst); | |
| 2911 | + | |
| 2912 | + phyd32clk = get_phyd32clk_src(link); | |
| 2913 | + dccg->funcs->enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk); | |
| 2805 | 2914 | } else { |
| 2806 | 2915 | if (dccg->funcs->enable_symclk_se) |
| 2807 | 2916 | dccg->funcs->enable_symclk_se(dccg, stream_enc->stream_enc_inst, |
| @@ -28,6 +28,8 @@ · 27 unmodified lines | ||
| 28 | 28 | |
| 29 | 29 | #include "hw_sequencer_private.h" |
| 30 | 30 | |
| 31 | +void dcn20_log_color_state(struct dc *dc, | |
| 32 | + struct dc_log_buffer_ctx *log_ctx); | |
| 31 | 33 | bool dcn20_set_blend_lut( |
| 32 | 34 | struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state); |
| 33 | 35 | bool dcn20_set_shaper_3dlut( |
| @@ -84,6 +86,10 @@ enum dc_status dcn20_enable_stream_timing( · 50 unmodified lines | ||
| 84 | 86 | void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx); |
| 85 | 87 | void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx); |
| 86 | 88 | void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx); |
| 89 | +void dcn20_reset_back_end_for_pipe( | |
| 90 | + struct dc *dc, | |
| 91 | + struct pipe_ctx *pipe_ctx, | |
| 92 | + struct dc_state *context); | |
| 87 | 93 | void dcn20_init_blank( |
| 88 | 94 | struct dc *dc, |
| 89 | 95 | struct timing_generator *tg); |
| @@ -206,28 +206,32 @@ void dcn21_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx) · 205 unmodified lines | ||
| 206 | 206 | void dcn21_set_pipe(struct pipe_ctx *pipe_ctx) |
| 207 | 207 | { |
| 208 | 208 | struct abm *abm = pipe_ctx->stream_res.abm; |
| 209 | − uint32_t otg_inst = pipe_ctx->stream_res.tg->inst; | |
| 209 | + struct timing_generator *tg = pipe_ctx->stream_res.tg; | |
| 210 | 210 | struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl; |
| 211 | 211 | struct dmcu *dmcu = pipe_ctx->stream->ctx->dc->res_pool->dmcu; |
| 212 | + uint32_t otg_inst; | |
| 213 | + | |
| 214 | + if (!abm && !tg && !panel_cntl) | |
| 215 | + return; | |
| 216 | + | |
| 217 | + otg_inst = tg->inst; | |
| 212 | 218 | |
| 213 | 219 | if (dmcu) { |
| 214 | 220 | dce110_set_pipe(pipe_ctx); |
| 215 | 221 | return; |
| 216 | 222 | } |
| 217 | 223 | |
| 218 | − if (abm && panel_cntl) { | |
| 219 | − if (abm->funcs && abm->funcs->set_pipe_ex) { | |
| 220 | − abm->funcs->set_pipe_ex(abm, | |
| 224 | + if (abm->funcs && abm->funcs->set_pipe_ex) { | |
| 225 | + abm->funcs->set_pipe_ex(abm, | |
| 221 | 226 | otg_inst, |
| 222 | 227 | SET_ABM_PIPE_NORMAL, |
| 223 | 228 | panel_cntl->inst, |
| 224 | 229 | panel_cntl->pwrseq_inst); |
| 225 | − } else { | |
| 226 | − dmub_abm_set_pipe(abm, otg_inst, | |
| 227 | − SET_ABM_PIPE_NORMAL, | |
| 228 | − panel_cntl->inst, | |
| 229 | − panel_cntl->pwrseq_inst); | |
| 230 | − } | |
| 230 | + } else { | |
| 231 | + dmub_abm_set_pipe(abm, otg_inst, | |
| 232 | + SET_ABM_PIPE_NORMAL, | |
| 233 | + panel_cntl->inst, | |
| 234 | + panel_cntl->pwrseq_inst); | |
| 231 | 235 | } |
| 232 | 236 | } |
| 233 | 237 | |
| @@ -237,34 +241,35 @@ bool dcn21_set_backlight_level(struct pipe_ctx *pipe_ctx, · 3 unmodified lines | ||
| 237 | 241 | { |
| 238 | 242 | struct dc_context *dc = pipe_ctx->stream->ctx; |
| 239 | 243 | struct abm *abm = pipe_ctx->stream_res.abm; |
| 244 | + struct timing_generator *tg = pipe_ctx->stream_res.tg; | |
| 240 | 245 | struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl; |
| 246 | + uint32_t otg_inst; | |
| 247 | + | |
| 248 | + if (!abm && !tg && !panel_cntl) | |
| 249 | + return false; | |
| 250 | + | |
| 251 | + otg_inst = tg->inst; | |
| 241 | 252 | |
| 242 | 253 | if (dc->dc->res_pool->dmcu) { |
| 243 | 254 | dce110_set_backlight_level(pipe_ctx, backlight_pwm_u16_16, frame_ramp); |
| 244 | 255 | return true; |
| 245 | 256 | } |
| 246 | 257 | |
| 247 | − if (abm != NULL) { | |
| 248 | − uint32_t otg_inst = pipe_ctx->stream_res.tg->inst; | |
| 249 | − | |
| 250 | − if (abm && panel_cntl) { | |
| 251 | − if (abm->funcs && abm->funcs->set_pipe_ex) { | |
| 252 | − abm->funcs->set_pipe_ex(abm, | |
| 253 | − otg_inst, | |
| 254 | − SET_ABM_PIPE_NORMAL, | |
| 255 | − panel_cntl->inst, | |
| 256 | − panel_cntl->pwrseq_inst); | |
| 257 | − } else { | |
| 258 | − dmub_abm_set_pipe(abm, | |
| 259 | − otg_inst, | |
| 260 | − SET_ABM_PIPE_NORMAL, | |
| 261 | − panel_cntl->inst, | |
| 262 | − panel_cntl->pwrseq_inst); | |
| 263 | − } | |
| 264 | − } | |
| 258 | + if (abm->funcs && abm->funcs->set_pipe_ex) { | |
| 259 | + abm->funcs->set_pipe_ex(abm, | |
| 260 | + otg_inst, | |
| 261 | + SET_ABM_PIPE_NORMAL, | |
| 262 | + panel_cntl->inst, | |
| 263 | + panel_cntl->pwrseq_inst); | |
| 264 | + } else { | |
| 265 | + dmub_abm_set_pipe(abm, | |
| 266 | + otg_inst, | |
| 267 | + SET_ABM_PIPE_NORMAL, | |
| 268 | + panel_cntl->inst, | |
| 269 | + panel_cntl->pwrseq_inst); | |
| 265 | 270 | } |
| 266 | 271 | |
| 267 | − if (abm && abm->funcs && abm->funcs->set_backlight_level_pwm) | |
| 272 | + if (abm->funcs && abm->funcs->set_backlight_level_pwm) | |
| 268 | 273 | abm->funcs->set_backlight_level_pwm(abm, backlight_pwm_u16_16, |
| 269 | 274 | frame_ramp, 0, panel_cntl->inst); |
| 270 | 275 | else |
| @@ -69,6 +69,155 @@ · 68 unmodified lines | ||
| 69 | 69 | #define FN(reg_name, field_name) \ |
| 70 | 70 | hws->shifts->field_name, hws->masks->field_name |
| 71 | 71 | |
| 72 | +void dcn30_log_color_state(struct dc *dc, | |
| 73 | + struct dc_log_buffer_ctx *log_ctx) | |
| 74 | +{ | |
| 75 | + struct dc_context *dc_ctx = dc->ctx; | |
| 76 | + struct resource_pool *pool = dc->res_pool; | |
| 77 | + int i; | |
| 78 | + | |
| 79 | + DTN_INFO("DPP: DGAM ROM DGAM ROM type DGAM LUT SHAPER mode" | |
| 80 | + " 3DLUT mode 3DLUT bit depth 3DLUT size RGAM mode" | |
| 81 | + " GAMUT adjust " | |
| 82 | + "C11 C12 C13 C14 " | |
| 83 | + "C21 C22 C23 C24 " | |
| 84 | + "C31 C32 C33 C34 \n"); | |
| 85 | + | |
| 86 | + for (i = 0; i < pool->pipe_count; i++) { | |
| 87 | + struct dpp *dpp = pool->dpps[i]; | |
| 88 | + struct dcn_dpp_state s = {0}; | |
| 89 | + | |
| 90 | + dpp->funcs->dpp_read_state(dpp, &s); | |
| 91 | + dpp->funcs->dpp_get_gamut_remap(dpp, &s.gamut_remap); | |
| 92 | + | |
| 93 | + if (!s.is_enabled) | |
| 94 | + continue; | |
| 95 | + | |
| 96 | + DTN_INFO("[%2d]: %7x %13s %8s %11s %10s %15s %10s %9s" | |
| 97 | + " %12s " | |
| 98 | + "%010lld %010lld %010lld %010lld " | |
| 99 | + "%010lld %010lld %010lld %010lld " | |
| 100 | + "%010lld %010lld %010lld %010lld", | |
| 101 | + dpp->inst, | |
| 102 | + s.pre_dgam_mode, | |
| 103 | + (s.pre_dgam_select == 0) ? "sRGB" : | |
| 104 | + ((s.pre_dgam_select == 1) ? "Gamma 2.2" : | |
| 105 | + ((s.pre_dgam_select == 2) ? "Gamma 2.4" : | |
| 106 | + ((s.pre_dgam_select == 3) ? "Gamma 2.6" : | |
| 107 | + ((s.pre_dgam_select == 4) ? "BT.709" : | |
| 108 | + ((s.pre_dgam_select == 5) ? "PQ" : | |
| 109 | + ((s.pre_dgam_select == 6) ? "HLG" : | |
| 110 | + "Unknown")))))), | |
| 111 | + (s.gamcor_mode == 0) ? "Bypass" : | |
| 112 | + ((s.gamcor_mode == 1) ? "RAM A" : | |
| 113 | + "RAM B"), | |
| 114 | + (s.shaper_lut_mode == 1) ? "RAM A" : | |
| 115 | + ((s.shaper_lut_mode == 2) ? "RAM B" : | |
| 116 | + "Bypass"), | |
| 117 | + (s.lut3d_mode == 1) ? "RAM A" : | |
| 118 | + ((s.lut3d_mode == 2) ? "RAM B" : | |
| 119 | + "Bypass"), | |
| 120 | + (s.lut3d_bit_depth <= 0) ? "12-bit" : "10-bit", | |
| 121 | + (s.lut3d_size == 0) ? "17x17x17" : "9x9x9", | |
| 122 | + (s.rgam_lut_mode == 0) ? "Bypass" : | |
| 123 | + ((s.rgam_lut_mode == 1) ? "RAM A" : | |
| 124 | + "RAM B"), | |
| 125 | + (s.gamut_remap.gamut_adjust_type == 0) ? "Bypass" : | |
| 126 | + ((s.gamut_remap.gamut_adjust_type == 1) ? "HW" : | |
| 127 | + "SW"), | |
| 128 | + s.gamut_remap.temperature_matrix[0].value, | |
| 129 | + s.gamut_remap.temperature_matrix[1].value, | |
| 130 | + s.gamut_remap.temperature_matrix[2].value, | |
| 131 | + s.gamut_remap.temperature_matrix[3].value, | |
| 132 | + s.gamut_remap.temperature_matrix[4].value, | |
| 133 | + s.gamut_remap.temperature_matrix[5].value, | |
| 134 | + s.gamut_remap.temperature_matrix[6].value, | |
| 135 | + s.gamut_remap.temperature_matrix[7].value, | |
| 136 | + s.gamut_remap.temperature_matrix[8].value, | |
| 137 | + s.gamut_remap.temperature_matrix[9].value, | |
| 138 | + s.gamut_remap.temperature_matrix[10].value, | |
| 139 | + s.gamut_remap.temperature_matrix[11].value); | |
| 140 | + DTN_INFO("\n"); | |
| 141 | + } | |
| 142 | + DTN_INFO("\n"); | |
| 143 | + DTN_INFO("DPP Color Caps: input_lut_shared:%d icsc:%d" | |
| 144 | + " dgam_ram:%d dgam_rom: srgb:%d,bt2020:%d,gamma2_2:%d,pq:%d,hlg:%d" | |
| 145 | + " post_csc:%d gamcor:%d dgam_rom_for_yuv:%d 3d_lut:%d" | |
| 146 | + " blnd_lut:%d oscs:%d\n\n", | |
| 147 | + dc->caps.color.dpp.input_lut_shared, | |
| 148 | + dc->caps.color.dpp.icsc, | |
| 149 | + dc->caps.color.dpp.dgam_ram, | |
| 150 | + dc->caps.color.dpp.dgam_rom_caps.srgb, | |
| 151 | + dc->caps.color.dpp.dgam_rom_caps.bt2020, | |
| 152 | + dc->caps.color.dpp.dgam_rom_caps.gamma2_2, | |
| 153 | + dc->caps.color.dpp.dgam_rom_caps.pq, | |
| 154 | + dc->caps.color.dpp.dgam_rom_caps.hlg, | |
| 155 | + dc->caps.color.dpp.post_csc, | |
| 156 | + dc->caps.color.dpp.gamma_corr, | |
| 157 | + dc->caps.color.dpp.dgam_rom_for_yuv, | |
| 158 | + dc->caps.color.dpp.hw_3d_lut, | |
| 159 | + dc->caps.color.dpp.ogam_ram, | |
| 160 | + dc->caps.color.dpp.ocsc); | |
| 161 | + | |
| 162 | + DTN_INFO("MPCC: OPP DPP MPCCBOT MODE ALPHA_MODE PREMULT OVERLAP_ONLY IDLE" | |
| 163 | + " SHAPER mode 3DLUT mode 3DLUT bit-depth 3DLUT size OGAM mode OGAM LUT" | |
| 164 | + " GAMUT adjust " | |
| 165 | + "C11 C12 C13 C14 " | |
| 166 | + "C21 C22 C23 C24 " | |
| 167 | + "C31 C32 C33 C34 \n"); | |
| 168 | + | |
| 169 | + for (i = 0; i < pool->pipe_count; i++) { | |
| 170 | + struct mpcc_state s = {0}; | |
| 171 | + | |
| 172 | + pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s); | |
| 173 | + mpc3_get_gamut_remap(pool->mpc, i, &s.gamut_remap); | |
| 174 | + | |
| 175 | + if (s.opp_id != 0xf) | |
| 176 | + DTN_INFO("[%2d]: %2xh %2xh %6xh %4d %10d %7d %12d %4d %11s %11s %16s %11s %10s %9s" | |
| 177 | + " %-12s " | |
| 178 | + "%010lld %010lld %010lld %010lld " | |
| 179 | + "%010lld %010lld %010lld %010lld " | |
| 180 | + "%010lld %010lld %010lld %010lld\n", | |
| 181 | + i, s.opp_id, s.dpp_id, s.bot_mpcc_id, | |
| 182 | + s.mode, s.alpha_mode, s.pre_multiplied_alpha, s.overlap_only, | |
| 183 | + s.idle, | |
| 184 | + (s.shaper_lut_mode == 1) ? "RAM A" : | |
| 185 | + ((s.shaper_lut_mode == 2) ? "RAM B" : | |
| 186 | + "Bypass"), | |
| 187 | + (s.lut3d_mode == 1) ? "RAM A" : | |
| 188 | + ((s.lut3d_mode == 2) ? "RAM B" : | |
| 189 | + "Bypass"), | |
| 190 | + (s.lut3d_bit_depth <= 0) ? "12-bit" : "10-bit", | |
| 191 | + (s.lut3d_size == 0) ? "17x17x17" : "9x9x9", | |
| 192 | + (s.rgam_mode == 0) ? "Bypass" : | |
| 193 | + ((s.rgam_mode == 2) ? "RAM" : | |
| 194 | + "Unknown"), | |
| 195 | + (s.rgam_mode == 1) ? "B" : "A", | |
| 196 | + (s.gamut_remap.gamut_adjust_type == 0) ? "Bypass" : | |
| 197 | + ((s.gamut_remap.gamut_adjust_type == 1) ? "HW" : | |
| 198 | + "SW"), | |
| 199 | + s.gamut_remap.temperature_matrix[0].value, | |
| 200 | + s.gamut_remap.temperature_matrix[1].value, | |
| 201 | + s.gamut_remap.temperature_matrix[2].value, | |
| 202 | + s.gamut_remap.temperature_matrix[3].value, | |
| 203 | + s.gamut_remap.temperature_matrix[4].value, | |
| 204 | + s.gamut_remap.temperature_matrix[5].value, | |
| 205 | + s.gamut_remap.temperature_matrix[6].value, | |
| 206 | + s.gamut_remap.temperature_matrix[7].value, | |
| 207 | + s.gamut_remap.temperature_matrix[8].value, | |
| 208 | + s.gamut_remap.temperature_matrix[9].value, | |
| 209 | + s.gamut_remap.temperature_matrix[10].value, | |
| 210 | + s.gamut_remap.temperature_matrix[11].value); | |
| 211 | + | |
| 212 | + } | |
| 213 | + DTN_INFO("\n"); | |
| 214 | + DTN_INFO("MPC Color Caps: gamut_remap:%d, 3dlut:%d, ogam_ram:%d, ocsc:%d\n\n", | |
| 215 | + dc->caps.color.mpc.gamut_remap, | |
| 216 | + dc->caps.color.mpc.num_3dluts, | |
| 217 | + dc->caps.color.mpc.ogam_ram, | |
| 218 | + dc->caps.color.mpc.ocsc); | |
| 219 | +} | |
| 220 | + | |
| 72 | 221 | bool dcn30_set_blend_lut( |
| 73 | 222 | struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) |
| 74 | 223 | { |
| @@ -1015,21 +1164,3 @@ void dcn30_prepare_bandwidth(struct dc *dc, · 940 unmodified lines | ||
| 1015 | 1164 | if (!dc->clk_mgr->clks.fw_based_mclk_switching) |
| 1016 | 1165 | dc_dmub_srv_p_state_delegate(dc, false, context); |
| 1017 | 1166 | } |
| 1018 | − | |
| 1019 | −void dcn30_set_static_screen_control(struct pipe_ctx **pipe_ctx, | |
| 1020 | − int num_pipes, const struct dc_static_screen_params *params) | |
| 1021 | −{ | |
| 1022 | − unsigned int i; | |
| 1023 | − unsigned int triggers = 0; | |
| 1024 | − | |
| 1025 | − if (params->triggers.surface_update) | |
| 1026 | − triggers |= 0x100; | |
| 1027 | − if (params->triggers.cursor_update) | |
| 1028 | − triggers |= 0x8; | |
| 1029 | − if (params->triggers.force_trigger) | |
| 1030 | − triggers |= 0x1; | |
| 1031 | − | |
| 1032 | − for (i = 0; i < num_pipes; i++) | |
| 1033 | − pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(pipe_ctx[i]->stream_res.tg, | |
| 1034 | − triggers, params->num_frames); | |
| 1035 | −} | |
| @@ -52,6 +52,9 @@ bool dcn30_mmhubbub_warmup( · 51 unmodified lines | ||
| 52 | 52 | unsigned int num_dwb, |
| 53 | 53 | struct dc_writeback_info *wb_info); |
| 54 | 54 | |
| 55 | +void dcn30_log_color_state(struct dc *dc, | |
| 56 | + struct dc_log_buffer_ctx *log_ctx); | |
| 57 | + | |
| 55 | 58 | bool dcn30_set_blend_lut(struct pipe_ctx *pipe_ctx, |
| 56 | 59 | const struct dc_plane_state *plane_state); |
| 57 | 60 | |
| @@ -90,7 +93,4 @@ void dcn30_set_hubp_blank(const struct dc *dc, · 32 unmodified lines | ||
| 90 | 93 | void dcn30_prepare_bandwidth(struct dc *dc, |
| 91 | 94 | struct dc_state *context); |
| 92 | 95 | |
| 93 | −void dcn30_set_static_screen_control(struct pipe_ctx **pipe_ctx, | |
| 94 | − int num_pipes, const struct dc_static_screen_params *params); | |
| 95 | − | |
| 96 | 96 | #endif /* __DC_HWSS_DCN30_H__ */ |
| @@ -64,7 +64,7 @@ static const struct hw_sequencer_funcs dcn30_funcs = { · 63 unmodified lines | ||
| 64 | 64 | .update_bandwidth = dcn20_update_bandwidth, |
| 65 | 65 | .set_drr = dcn10_set_drr, |
| 66 | 66 | .get_position = dcn10_get_position, |
| 67 | − .set_static_screen_control = dcn30_set_static_screen_control, | |
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