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drm/msm: Utilize gpu scheduler priorities

The drm/scheduler provides additional prioritization on top of that provided by however many number of ringbuffers (each with their own priority level) is supported on a given generation. Expose the additional levels of priority to userspace and map the userspace priority back to ring (first level of priority) and schedular priority (additional priority levels within the ring).

Rob Clark committed 5 years ago

Commit fc40e5e1 parent e3e24ee5 files · +88 −27Browse files

Showing the changes to include/uapi (1 of 5 files). Show all

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include/uapi/drm/msm_drm.h+13−1
@@ -73,11 +73,19 @@ struct drm_msm_timespec { · 72 unmodified lines
7373 #define MSM_PARAM_MAX_FREQ 0x04
7474 #define MSM_PARAM_TIMESTAMP 0x05
7575 #define MSM_PARAM_GMEM_BASE 0x06
76−#define MSM_PARAM_NR_RINGS 0x07
76+#define MSM_PARAM_PRIORITIES 0x07 /* The # of priority levels */
7777 #define MSM_PARAM_PP_PGTABLE 0x08 /* => 1 for per-process pagetables, else 0 */
7878 #define MSM_PARAM_FAULTS 0x09
7979 #define MSM_PARAM_SUSPENDS 0x0a
8080
81+/* For backwards compat. The original support for preemption was based on
82+ * a single ring per priority level so # of priority levels equals the #
83+ * of rings. With drm/scheduler providing additional levels of priority,
84+ * the number of priorities is greater than the # of rings. The param is
85+ * renamed to better reflect this.
86+ */
87+#define MSM_PARAM_NR_RINGS MSM_PARAM_PRIORITIES
88+
8189 struct drm_msm_param {
8290 __u32 pipe; /* in, MSM_PIPE_x */
8391 __u32 param; /* in, MSM_PARAM_x */
@@ -304,6 +312,10 @@ struct drm_msm_gem_madvise { · 220 unmodified lines
304312
305313 #define MSM_SUBMITQUEUE_FLAGS (0)
306314
315+/*
316+ * The submitqueue priority should be between 0 and MSM_PARAM_PRIORITIES-1,
317+ * a lower numeric value is higher priority.
318+ */
307319 struct drm_msm_submitqueue {
308320 __u32 flags; /* in, MSM_SUBMITQUEUE_x */
309321 __u32 prio; /* in, Priority level */

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