ODP support for XRC transport is not enabled by default in FW, so we need separate ODP checks to enable/disable it. While that, rewrite the set of ODP SRQ support capabilities in way that tests each field separately for clearness, which is not needed for current FW, but better to have it separated.
Unified · Split
| @@ -465,6 +465,7 @@ static int handle_hca_cap_odp(struct mlx5_core_dev *dev) · 464 unmodified lines | |||
| 465 | void *set_hca_cap; | 465 | void *set_hca_cap; |
| 466 | void *set_ctx; | 466 | void *set_ctx; |
| 467 | int set_sz; | 467 | int set_sz; |
| 468 | bool do_set = false; | ||
| 468 | int err; | 469 | int err; |
| 469 | 470 | ||
| 470 | if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) || | 471 | if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) || |
| @@ -475,11 +476,6 @@ static int handle_hca_cap_odp(struct mlx5_core_dev *dev) · 4 unmodified lines | |||
| 475 | if (err) | 476 | if (err) |
| 476 | return err; | 477 | return err; |
| 477 | 478 | ||
| 478 | if (!(MLX5_CAP_ODP_MAX(dev, ud_odp_caps.srq_receive) || | ||
| 479 | MLX5_CAP_ODP_MAX(dev, rc_odp_caps.srq_receive) || | ||
| 480 | MLX5_CAP_ODP_MAX(dev, xrc_odp_caps.srq_receive))) | ||
| 481 | return 0; | ||
| 482 | |||
| 483 | set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); | 479 | set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); |
| 484 | set_ctx = kzalloc(set_sz, GFP_KERNEL); | 480 | set_ctx = kzalloc(set_sz, GFP_KERNEL); |
| 485 | if (!set_ctx) | 481 | if (!set_ctx) |
| @@ -489,19 +485,30 @@ static int handle_hca_cap_odp(struct mlx5_core_dev *dev) · 3 unmodified lines | |||
| 489 | memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_ODP], | 485 | memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_ODP], |
| 490 | MLX5_ST_SZ_BYTES(odp_cap)); | 486 | MLX5_ST_SZ_BYTES(odp_cap)); |
| 491 | 487 | ||
| 492 | /* set ODP SRQ support for RC/UD and XRC transports */ | 488 | #define ODP_CAP_SET_MAX(dev, field) \ |
| 493 | MLX5_SET(odp_cap, set_hca_cap, ud_odp_caps.srq_receive, | 489 | do { \ |
| 494 | MLX5_CAP_ODP_MAX(dev, ud_odp_caps.srq_receive)); | 490 | u32 _res = MLX5_CAP_ODP_MAX(dev, field); \ |
| 495 | 491 | if (_res) { \ | |
| 496 | MLX5_SET(odp_cap, set_hca_cap, rc_odp_caps.srq_receive, | 492 | do_set = true; \ |
| 497 | MLX5_CAP_ODP_MAX(dev, rc_odp_caps.srq_receive)); | 493 | MLX5_SET(odp_cap, set_hca_cap, field, _res); \ |
| 498 | 494 | } \ | |
| 499 | MLX5_SET(odp_cap, set_hca_cap, xrc_odp_caps.srq_receive, | 495 | } while (0) |
| 500 | MLX5_CAP_ODP_MAX(dev, xrc_odp_caps.srq_receive)); | 496 | |
| 501 | 497 | ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive); | |
| 502 | err = set_caps(dev, set_ctx, set_sz, MLX5_SET_HCA_CAP_OP_MOD_ODP); | 498 | ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive); |
| 499 | ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive); | ||
| 500 | ODP_CAP_SET_MAX(dev, xrc_odp_caps.send); | ||
| 501 | ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive); | ||
| 502 | ODP_CAP_SET_MAX(dev, xrc_odp_caps.write); | ||
| 503 | ODP_CAP_SET_MAX(dev, xrc_odp_caps.read); | ||
| 504 | ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic); | ||
| 505 | |||
| 506 | if (do_set) | ||
| 507 | err = set_caps(dev, set_ctx, set_sz, | ||
| 508 | MLX5_SET_HCA_CAP_OP_MOD_ODP); | ||
| 503 | 509 | ||
| 504 | kfree(set_ctx); | 510 | kfree(set_ctx); |
| 511 | |||
| 505 | return err; | 512 | return err; |
| 506 | } | 513 | } |
| 507 | 514 | ||