perf: Pass last sampling period to perf_sample_data_init()

We always need to pass the last sample period to perf_sample_data_init(), otherwise the event distribution will be wrong. Thus, modifiyng the function interface with the required period as argument. So basically a pattern like this: perf_sample_data_init(&data, ~0ULL); data.period = event->hw.last_period; will now be like that: perf_sample_data_init(&data, ~0ULL, event->hw.last_period); Avoids unininitialized data.period and simplifies code.

Robert Richter committed 14 years ago

Commit fd0d0001 parent c75841a15 files · +25 −43Browse files

Unified · Split

15 files

arch/alpha/kernel/perf_event.c +1 −2
arch/arm/kernel/perf_event_v6.c +1 −3
arch/arm/kernel/perf_event_v7.c +1 −3
arch/arm/kernel/perf_event_xscale.c +2 −6
arch/mips/kernel/perf_event_mipsxx.c +1 −1
arch/powerpc/perf/core-book3s.c +1 −2
arch/powerpc/perf/core-fsl-emb.c +1 −2
arch/sparc/kernel/perf_event.c +1 −3
arch/x86/kernel/cpu/perf_event.c +1 −3
arch/x86/kernel/cpu/perf_event_amd_ibs.c +1 −2
arch/x86/kernel/cpu/perf_event_intel.c +1 −3
arch/x86/kernel/cpu/perf_event_intel_ds.c +2 −4
arch/x86/kernel/cpu/perf_event_p4.c +3 −3
include/linux/perf_event.h +4 −1
kernel/events/core.c +4 −5

arch/alpha/kernel/perf_event.c+1−2

 	idx = la_ptr;
-	perf_sample_data_init(&data, 0);
 	for (j = 0; j < cpuc->n_events; j++) {
 		if (cpuc->current_idx[j] == idx)
 			break;
 	hwc = &event->hw;
 	alpha_perf_event_update(event, hwc, idx, alpha_pmu->pmc_max_period[idx]+1);
-	data.period = event->hw.last_period;
+	perf_sample_data_init(&data, 0, hwc->last_period);
 	if (alpha_perf_event_set_period(event, hwc, idx)) {
 		if (perf_event_overflow(event, &data, regs)) {

arch/arm/kernel/perf_event_v6.c+1−3

 	 */
 	armv6_pmcr_write(pmcr);
-	perf_sample_data_init(&data, 0);
 	cpuc = &__get_cpu_var(cpu_hw_events);
 	for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
 		struct perf_event *event = cpuc->events[idx];
 		hwc = &event->hw;
 		armpmu_event_update(event, hwc, idx);
-		data.period = event->hw.last_period;
+		perf_sample_data_init(&data, 0, hwc->last_period);
 		if (!armpmu_event_set_period(event, hwc, idx))
 			continue;

arch/arm/kernel/perf_event_v7.c+1−3

 	 */
 	regs = get_irq_regs();
-	perf_sample_data_init(&data, 0);
 	cpuc = &__get_cpu_var(cpu_hw_events);
 	for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
 		struct perf_event *event = cpuc->events[idx];
 		hwc = &event->hw;
 		armpmu_event_update(event, hwc, idx);
-		data.period = event->hw.last_period;
+		perf_sample_data_init(&data, 0, hwc->last_period);
 		if (!armpmu_event_set_period(event, hwc, idx))
 			continue;

arch/arm/kernel/perf_event_xscale.c+2−6

 	regs = get_irq_regs();
-	perf_sample_data_init(&data, 0);
 	cpuc = &__get_cpu_var(cpu_hw_events);
 	for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
 		struct perf_event *event = cpuc->events[idx];
 		hwc = &event->hw;
 		armpmu_event_update(event, hwc, idx);
-		data.period = event->hw.last_period;
+		perf_sample_data_init(&data, 0, hwc->last_period);
 		if (!armpmu_event_set_period(event, hwc, idx))
 			continue;
 	regs = get_irq_regs();
-	perf_sample_data_init(&data, 0);
 	cpuc = &__get_cpu_var(cpu_hw_events);
 	for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
 		struct perf_event *event = cpuc->events[idx];
 		hwc = &event->hw;
 		armpmu_event_update(event, hwc, idx);
-		data.period = event->hw.last_period;
+		perf_sample_data_init(&data, 0, hwc->last_period);
 		if (!armpmu_event_set_period(event, hwc, idx))
 			continue;

arch/mips/kernel/perf_event_mipsxx.c+1−1

@@ -1325,7 +1325,7 @@ static int mipsxx_pmu_handle_shared_irq(void) · 1324 unmodified lines
1325		1325
1326	regs = get_irq_regs();	1326	regs = get_irq_regs();
1327		1327
1328	perf_sample_data_init(&data, 0);	1328	perf_sample_data_init(&data, 0, 0);
1329		1329
1330	switch (counters) {	1330	switch (counters) {
1331	#define HANDLE_COUNTER(n) \	1331	#define HANDLE_COUNTER(n) \

arch/powerpc/perf/core-book3s.c+1−2

@@ -1299,8 +1299,7 @@ static void record_and_restart(struct perf_event *event, unsigned long val, · 1298 unmodified lines
1299	if (record) {	1299	if (record) {
1300	struct perf_sample_data data;	1300	struct perf_sample_data data;
1301		1301
1302	perf_sample_data_init(&data, ~0ULL);	1302	perf_sample_data_init(&data, ~0ULL, event->hw.last_period);
1303	data.period = event->hw.last_period;
1304		1303
1305	if (event->attr.sample_type & PERF_SAMPLE_ADDR)	1304	if (event->attr.sample_type & PERF_SAMPLE_ADDR)
1306	perf_get_data_addr(regs, &data.addr);	1305	perf_get_data_addr(regs, &data.addr);

arch/powerpc/perf/core-fsl-emb.c+1−2

@@ -613,8 +613,7 @@ static void record_and_restart(struct perf_event *event, unsigned long val, · 612 unmodified lines
613	if (record) {	613	if (record) {
614	struct perf_sample_data data;	614	struct perf_sample_data data;
615		615
616	perf_sample_data_init(&data, 0);	616	perf_sample_data_init(&data, 0, event->hw.last_period);
617	data.period = event->hw.last_period;
618		617
619	if (perf_event_overflow(event, &data, regs))	618	if (perf_event_overflow(event, &data, regs))
620	fsl_emb_pmu_stop(event, 0);	619	fsl_emb_pmu_stop(event, 0);

arch/sparc/kernel/perf_event.c+1−3

 	regs = args->regs;
-	perf_sample_data_init(&data, 0);
 	cpuc = &__get_cpu_var(cpu_hw_events);
 	/* If the PMU has the TOE IRQ enable bits, we need to do a
 		if (val & (1ULL << 31))
 			continue;
-		data.period = event->hw.last_period;
+		perf_sample_data_init(&data, 0, hwc->last_period);
 		if (!sparc_perf_event_set_period(event, hwc, idx))
 			continue;

arch/x86/kernel/cpu/perf_event.c+1−3

 	int idx, handled = 0;
 	u64 val;
-	perf_sample_data_init(&data, 0);
 	cpuc = &__get_cpu_var(cpu_hw_events);
 	/*
 		 * event overflow
 		 */
 		handled++;
-		data.period	= event->hw.last_period;
+		perf_sample_data_init(&data, 0, event->hw.last_period);
 		if (!x86_perf_event_set_period(event))
 			continue;

arch/x86/kernel/cpu/perf_event_amd_ibs.c+1−2

@@ -398,8 +398,7 @@ static int perf_ibs_handle_irq(struct perf_ibs perf_ibs, struct pt_regs iregs) · 397 unmodified lines
398	}	398	}
399		399
400	perf_ibs_event_update(perf_ibs, event, config);	400	perf_ibs_event_update(perf_ibs, event, config);
401	perf_sample_data_init(&data, 0);	401	perf_sample_data_init(&data, 0, hwc->last_period);
402	data.period = event->hw.last_period;
403		402
404	if (event->attr.sample_type & PERF_SAMPLE_RAW) {	403	if (event->attr.sample_type & PERF_SAMPLE_RAW) {
405	ibs_data.caps = ibs_caps;	404	ibs_data.caps = ibs_caps;

arch/x86/kernel/cpu/perf_event_intel.c+1−3

 	u64 status;
 	int handled;
-	perf_sample_data_init(&data, 0);
 	cpuc = &__get_cpu_var(cpu_hw_events);
 	/*
 		if (!intel_pmu_save_and_restart(event))
 			continue;
-		data.period = event->hw.last_period;
+		perf_sample_data_init(&data, 0, event->hw.last_period);
 		if (has_branch_stack(event))
 			data.br_stack = &cpuc->lbr_stack;

arch/x86/kernel/cpu/perf_event_intel_ds.c+2−4

 	ds->bts_index = ds->bts_buffer_base;
-	perf_sample_data_init(&data, 0);
+	perf_sample_data_init(&data, 0, event->hw.last_period);
-	data.period = event->hw.last_period;
 	regs.ip     = 0;
 	/*
 	if (!intel_pmu_save_and_restart(event))
 		return;
-	perf_sample_data_init(&data, 0);
+	perf_sample_data_init(&data, 0, event->hw.last_period);
-	data.period = event->hw.last_period;
 	/*
 	 * We use the interrupt regs as a base because the PEBS record

arch/x86/kernel/cpu/perf_event_p4.c+3−3

 	int idx, handled = 0;
 	u64 val;
-	perf_sample_data_init(&data, 0);
 	cpuc = &__get_cpu_var(cpu_hw_events);
 	for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 		handled += overflow;
 		/* event overflow for sure */
-		data.period = event->hw.last_period;
+		perf_sample_data_init(&data, 0, hwc->last_period);
 		if (!x86_perf_event_set_period(event))
 			continue;
 		if (perf_event_overflow(event, &data, regs))
 			x86_pmu_stop(event, 0);
 	}

include/linux/perf_event.h+4−1

 	struct perf_branch_stack	*br_stack;
 };
-static inline void perf_sample_data_init(struct perf_sample_data *data, u64 addr)
+static inline void perf_sample_data_init(struct perf_sample_data *data,
+					 u64 addr, u64 period)
 {
+	/* remaining struct members initialized in perf_prepare_sample() */
 	data->addr = addr;
 	data->raw  = NULL;
 	data->br_stack = NULL;
+	data->period	= period;
 }
 extern void perf_output_sample(struct perf_output_handle *handle,

kernel/events/core.c+4−5

 	if (rctx < 0)
 		return;
-	perf_sample_data_init(&data, addr);
+	perf_sample_data_init(&data, addr, 0);
 	do_perf_sw_event(PERF_TYPE_SOFTWARE, event_id, nr, &data, regs);
 		.data = record,
 	};
-	perf_sample_data_init(&data, addr);
+	perf_sample_data_init(&data, addr, 0);
 	data.raw = &raw;
 	hlist_for_each_entry_rcu(event, node, head, hlist_entry) {
 	struct perf_sample_data sample;
 	struct pt_regs *regs = data;
-	perf_sample_data_init(&sample, bp->attr.bp_addr);
+	perf_sample_data_init(&sample, bp->attr.bp_addr, 0);
 	if (!bp->hw.state && !perf_exclude_event(bp, regs))
 		perf_swevent_event(bp, 1, &sample, regs);
 	event->pmu->read(event);
-	perf_sample_data_init(&data, 0);
+	perf_sample_data_init(&data, 0, event->hw.last_period);
-	data.period = event->hw.last_period;
 	regs = get_irq_regs();
 	if (regs && !perf_exclude_event(event, regs)) {