Merge tag 'v5.13-rc7' into rdma.git for-next

Linux 5.13-rc7 Needed for dependencies in following patches. Merge conflict in rxe_cmop.c resolved by compining both patches.

Jason Gunthorpe committed 5 years ago

Commit fdcebbc2 parents 6d33cab 13311e71665 files · +18578 −8916Browse files

Unified · Split

1665 files

.clang-format +11 −2
.mailmap +4 −0
Documentation/ABI/obsolete/sysfs-class-dax +1 −1
Documentation/ABI/obsolete/sysfs-kernel-fadump_registered +1 −1
Documentation/ABI/obsolete/sysfs-kernel-fadump_release_mem +1 −1
Documentation/ABI/removed/sysfs-bus-nfit +1 −1
Documentation/ABI/testing/sysfs-bus-nfit +20 −20
Documentation/ABI/testing/sysfs-bus-papr-pmem +2 −2
Documentation/ABI/testing/sysfs-module +2 −2
Documentation/admin-guide/sysctl/kernel.rst +19 −7
Documentation/block/data-integrity.rst +1 −1
Documentation/cdrom/cdrom-standard.rst +15 −15
Documentation/devicetree/bindings/clock/idt,versaclock5.yaml +0 −2
Documentation/devicetree/bindings/connector/usb-connector.yaml +15 −0
Documentation/devicetree/bindings/hwmon/ti,ads7828.yaml +1 −1
Documentation/devicetree/bindings/i2c/i2c-mpc.yaml +7 −0
Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml +0 −1
Documentation/devicetree/bindings/input/input.yaml +0 −1
Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml +0 −1
Documentation/devicetree/bindings/leds/leds-bcm6328.txt +2 −2
Documentation/devicetree/bindings/leds/leds-bcm6358.txt +1 −1
Documentation/devicetree/bindings/media/renesas,drif.yaml +8 −16
Documentation/devicetree/bindings/net/qcom,ipa.yaml +0 −1
Documentation/devicetree/bindings/net/renesas,ether.yaml +1 −1
Documentation/devicetree/bindings/nvmem/mtk-efuse.txt +0 −1
Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml +1 −1
Documentation/devicetree/bindings/power/supply/sc2731-charger.yaml +1 −1
Documentation/devicetree/bindings/sound/amlogic,gx-sound-card.yaml +2 −2
Documentation/devicetree/bindings/sound/fsl,rpmsg.yaml +1 −1
Documentation/devicetree/bindings/spi/spi-mux.yaml +1 −1
Documentation/driver-api/nvdimm/nvdimm.rst +1 −1
Documentation/driver-api/serial/index.rst +0 −1
Documentation/driver-api/usb/usb.rst +11 −6
Documentation/filesystems/erofs.rst +102 −73
Documentation/hwmon/tmp103.rst +2 −2
Documentation/networking/device_drivers/ethernet/intel/i40e.rst +2 −2
Documentation/networking/device_drivers/ethernet/intel/iavf.rst +1 −1
Documentation/powerpc/syscall64-abi.rst +10 −0
Documentation/process/kernel-enforcement-statement.rst +1 −1
Documentation/riscv/vm-layout.rst +2 −2
Documentation/security/tpm/xen-tpmfront.rst +1 −1
Documentation/timers/no_hz.rst +1 −1
Documentation/translations/zh_CN/SecurityBugs +0 −50
Documentation/usb/gadget_configfs.rst +1 −1
Documentation/usb/mtouchusb.rst +1 −1
Documentation/usb/usb-serial.rst +1 −1
Documentation/userspace-api/seccomp_filter.rst +8 −8
Documentation/virt/kvm/amd-memory-encryption.rst +1 −1
Documentation/virt/kvm/api.rst +2 −2
Documentation/virt/kvm/mmu.rst +2 −2
Documentation/virt/kvm/vcpu-requests.rst +5 −3
Documentation/vm/slub.rst +5 −5
Documentation/x86/amd-memory-encryption.rst +3 −3
MAINTAINERS +58 −30
Makefile +10 −2
arch/alpha/kernel/syscalls/syscall.tbl +1 −1
arch/arc/Makefile +1 −1
arch/arc/include/asm/cmpxchg.h +2 −2
arch/arc/include/asm/page.h +12 −0
arch/arc/include/asm/pgtable.h +3 −9
arch/arc/include/uapi/asm/page.h +0 −1
arch/arc/include/uapi/asm/sigcontext.h +1 −0
arch/arc/kernel/entry.S +2 −2
arch/arc/kernel/kgdb.c +1 −0
arch/arc/kernel/process.c +4 −4
arch/arc/kernel/signal.c +45 −2
arch/arc/kernel/vmlinux.lds.S +1 −1
arch/arc/mm/init.c +10 −1
arch/arc/mm/ioremap.c +3 −2
arch/arc/mm/tlb.c +1 −1
arch/arm/boot/dts/imx6dl-yapp4-common.dtsi +5 −1
arch/arm/boot/dts/imx6q-dhcom-som.dtsi +12 −0
arch/arm/boot/dts/imx6qdl-emcon-avari.dtsi +1 −1
arch/arm/boot/dts/imx7d-meerkat96.dts +1 −1
arch/arm/boot/dts/imx7d-pico.dtsi +1 −1
arch/arm/include/asm/cpuidle.h +3 −2
arch/arm/mach-imx/pm-imx27.c +1 −0
arch/arm/mach-npcm/Kconfig +1 −0
arch/arm/mach-omap1/board-ams-delta.c +0 −14
arch/arm/mach-omap1/board-h2.c +3 −1
arch/arm/mach-omap1/pm.c +7 −3
arch/arm/mach-omap2/board-n8x0.c +1 −1
arch/arm/mach-pxa/pxa_cplds_irqs.c +6 −1
arch/arm/tools/syscall.tbl +1 −1
arch/arm/xen/mm.c +7 −13
arch/arm64/Kbuild +1 −2
arch/arm64/Kconfig.platforms +1 −0
arch/arm64/Makefile +3 −0
arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dts +2 −1
arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts +2 −3
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +2 −2
arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dts +5 −5
arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi +7 −16
arch/arm64/boot/dts/renesas/hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi +0 −2
arch/arm64/boot/dts/renesas/r8a774a1.dtsi +8 −0
arch/arm64/boot/dts/renesas/r8a774b1.dtsi +8 −0
arch/arm64/boot/dts/renesas/r8a774c0-ek874-mipi-2.1.dts +1 −1
arch/arm64/boot/dts/renesas/r8a774c0.dtsi +4 −0
arch/arm64/boot/dts/renesas/r8a774e1.dtsi +8 −0
arch/arm64/boot/dts/renesas/r8a77950.dtsi +4 −0
arch/arm64/boot/dts/renesas/r8a77951.dtsi +12 −0
arch/arm64/boot/dts/renesas/r8a77960.dtsi +8 −0
arch/arm64/boot/dts/renesas/r8a77961.dtsi +8 −0
arch/arm64/boot/dts/renesas/r8a77965.dtsi +8 −0
arch/arm64/boot/dts/renesas/r8a77970.dtsi +4 −0
arch/arm64/boot/dts/renesas/r8a77980.dtsi +8 −0
arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts +0 −2
arch/arm64/boot/dts/renesas/r8a77990.dtsi +4 −0
arch/arm64/boot/dts/renesas/salvator-common.dtsi +0 −3
arch/arm64/boot/dts/ti/k3-am64-main.dtsi +6 −5
arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi +2 −1
arch/arm64/boot/dts/ti/k3-am65-main.dtsi +6 −4
arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +2 −2
arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi +7 −6
arch/arm64/boot/dts/ti/k3-am654-base-board.dts +0 −31
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +6 −2
arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +4 −3
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +6 −4
arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +6 −5
arch/arm64/include/asm/Kbuild +2 −0
arch/arm64/include/asm/barrier.h +1 −1
arch/arm64/include/asm/cpucaps.h +0 −74
arch/arm64/include/asm/kvm_asm.h +3 −0
arch/arm64/include/asm/kvm_emulate.h +5 −0
arch/arm64/include/asm/unistd32.h +1 −2
arch/arm64/kvm/arm.c +17 −3
arch/arm64/kvm/hyp/exception.c +17 −1
arch/arm64/kvm/hyp/include/hyp/adjust_pc.h +0 −18
arch/arm64/kvm/hyp/nvhe/hyp-main.c +8 −0
arch/arm64/kvm/hyp/nvhe/mem_protect.c +2 −2
arch/arm64/kvm/hyp/nvhe/setup.c +1 −1
arch/arm64/kvm/hyp/nvhe/switch.c +1 −2
arch/arm64/kvm/hyp/vhe/switch.c +1 −2
arch/arm64/kvm/mmu.c +6 −6
arch/arm64/kvm/reset.c +24 −4
arch/arm64/kvm/sys_regs.c +21 −21
arch/arm64/mm/flush.c +3 −1
arch/arm64/mm/init.c +2 −1
arch/arm64/mm/mmu.c +2 −1
arch/arm64/mm/proc.S +12 −0
arch/arm64/tools/Makefile +22 −0
arch/arm64/tools/cpucaps +65 −0
arch/arm64/tools/gen-cpucaps.awk +40 −0
arch/ia64/kernel/syscalls/syscall.tbl +1 −1
arch/m68k/kernel/signal.c +2 −1
arch/m68k/kernel/syscalls/syscall.tbl +1 −1
arch/microblaze/kernel/syscalls/syscall.tbl +1 −1
arch/mips/alchemy/board-xxs1500.c +1 −0
arch/mips/include/asm/mips-boards/launch.h +5 −0
arch/mips/kernel/syscalls/syscall_n32.tbl +1 −1
arch/mips/kernel/syscalls/syscall_n64.tbl +1 −1
arch/mips/kernel/syscalls/syscall_o32.tbl +1 −1
arch/mips/lib/mips-atomic.c +6 −6
arch/mips/mm/cache.c +14 −16
arch/mips/ralink/of.c +2 −0
arch/openrisc/include/asm/barrier.h +9 −0
arch/openrisc/kernel/setup.c +2 −0
arch/openrisc/mm/init.c +1 −5
arch/parisc/kernel/syscalls/syscall.tbl +1 −1
arch/powerpc/boot/dts/fsl/p1010si-post.dtsi +8 −0
arch/powerpc/boot/dts/fsl/p2041si-post.dtsi +16 −0
arch/powerpc/include/asm/hvcall.h +3 −0
arch/powerpc/include/asm/interrupt.h +7 −2
arch/powerpc/include/asm/jump_label.h +1 −1
arch/powerpc/include/asm/kvm_host.h +1 −0
arch/powerpc/include/asm/paravirt.h +19 −3
arch/powerpc/include/asm/plpar_wrappers.h +5 −1
arch/powerpc/include/asm/pte-walk.h +29 −0
arch/powerpc/include/asm/ptrace.h +26 −19
arch/powerpc/include/asm/syscall.h +26 −16
arch/powerpc/include/asm/uaccess.h +1 −1
arch/powerpc/kernel/eeh.c +1 −22
arch/powerpc/kernel/exceptions-64e.S +24 −14
arch/powerpc/kernel/interrupt.c +1 −3
arch/powerpc/kernel/io-workarounds.c +3 −13
arch/powerpc/kernel/iommu.c +5 −6
arch/powerpc/kernel/kprobes.c +2 −2
arch/powerpc/kernel/legacy_serial.c +5 −2
arch/powerpc/kernel/setup_64.c +2 −2
arch/powerpc/kernel/signal.h +2 −2
arch/powerpc/kernel/signal_64.c +4 −5
arch/powerpc/kernel/syscalls/syscall.tbl +1 −1
arch/powerpc/kvm/book3s_64_mmu_hv.c +1 −1
arch/powerpc/kvm/book3s_hv.c +1 −2
arch/powerpc/kvm/book3s_hv_rm_mmu.c +2 −13
arch/powerpc/kvm/book3s_hv_rmhandlers.S +7 −0
arch/powerpc/lib/feature-fixups.c +85 −29
arch/powerpc/mm/mem.c +1 −0
arch/powerpc/perf/core-book3s.c +1 −1
arch/powerpc/platforms/pseries/hvCall.S +10 −0
arch/powerpc/platforms/pseries/lpar.c +12 −17
arch/riscv/Kconfig +10 −9
arch/riscv/Kconfig.socs +1 −0
arch/riscv/Makefile +10 −1
arch/riscv/boot/dts/microchip/Makefile +1 −0
arch/riscv/boot/dts/sifive/Makefile +1 −0
arch/riscv/boot/dts/sifive/fu740-c000.dtsi +1 −1
arch/riscv/errata/sifive/Makefile +1 −1
arch/riscv/include/asm/alternative-macros.h +2 −2
arch/riscv/include/asm/kexec.h +2 −2
arch/riscv/include/asm/pgtable.h +2 −3
arch/riscv/kernel/machine_kexec.c +6 −5
arch/riscv/kernel/probes/kprobes.c +2 −0
arch/riscv/kernel/setup.c +2 −2
arch/riscv/kernel/stacktrace.c +7 −7
arch/riscv/kernel/traps.c +9 −4
arch/riscv/kernel/vmlinux-xip.lds.S +14 −1
arch/riscv/mm/init.c +6 −2
arch/riscv/mm/kasan_init.c +5 −5
arch/s390/kernel/entry.S +2 −2
arch/s390/kernel/syscalls/syscall.tbl +1 −1
arch/sh/kernel/syscalls/syscall.tbl +1 −1
arch/sh/kernel/traps.c +0 −1
arch/sparc/kernel/syscalls/syscall.tbl +1 −1
arch/x86/Makefile +7 −6
arch/x86/boot/compressed/Makefile +4 −3
arch/x86/boot/compressed/misc.c +1 −1
arch/x86/boot/compressed/misc.h +1 −1
arch/x86/boot/compressed/sev.c +2 −2
arch/x86/entry/syscalls/syscall_32.tbl +1 −1
arch/x86/entry/syscalls/syscall_64.tbl +1 −1
arch/x86/events/core.c +4 −2
arch/x86/events/intel/core.c +1 −1
arch/x86/events/intel/lbr.c +20 −6
arch/x86/events/intel/uncore_snbep.c +6 −3
arch/x86/events/perf_event.h +6 −0
arch/x86/include/asm/apic.h +1 −0
arch/x86/include/asm/disabled-features.h +2 −5
arch/x86/include/asm/fpu/api.h +1 −5
arch/x86/include/asm/fpu/internal.h +10 −10
arch/x86/include/asm/kvm-x86-ops.h +1 −0
arch/x86/include/asm/kvm_host.h +13 −3
arch/x86/include/asm/kvm_para.h +2 −8
arch/x86/include/asm/msr-index.h +3 −3
arch/x86/include/asm/processor.h +2 −0
arch/x86/include/asm/sev-common.h +62 −0
arch/x86/include/asm/sev.h +4 −26
arch/x86/include/asm/thermal.h +3 −1
arch/x86/include/asm/vdso/clocksource.h +2 −0
arch/x86/include/uapi/asm/kvm.h +2 −0
arch/x86/kernel/Makefile +3 −3
arch/x86/kernel/alternative.c +46 −18
arch/x86/kernel/apic/apic.c +1 −0
arch/x86/kernel/apic/vector.c +20 −0
arch/x86/kernel/cpu/amd.c +18 −2
arch/x86/kernel/cpu/mtrr/cleanup.c +1 −1
arch/x86/kernel/cpu/mtrr/generic.c +2 −2
arch/x86/kernel/cpu/perfctr-watchdog.c +2 −2
arch/x86/kernel/cpu/sgx/virt.c +1 −0
arch/x86/kernel/fpu/signal.c +35 −19
arch/x86/kernel/fpu/xstate.c +0 −57
arch/x86/kernel/head64.c +1 −1
arch/x86/kernel/kvm.c +83 −46
arch/x86/kernel/kvmclock.c +1 −25
arch/x86/kernel/mmconf-fam10h_64.c +1 −1
arch/x86/kernel/nmi.c +1 −1
arch/x86/kernel/setup.c +30 −14
arch/x86/kernel/sev-shared.c +11 −10
arch/x86/kernel/sev.c +87 −53
arch/x86/kernel/signal_compat.c +7 −2
arch/x86/kernel/smpboot.c +1 −1
arch/x86/kvm/cpuid.c +19 −2
arch/x86/kvm/emulate.c +4 −3
arch/x86/kvm/hyperv.c +8 −0
arch/x86/kvm/kvm_emulate.h +2 −2
arch/x86/kvm/lapic.c +27 −11
arch/x86/kvm/mmu/mmu.c +35 −11
arch/x86/kvm/mmu/paging_tmpl.h +9 −5
arch/x86/kvm/mmu/tdp_mmu.c +19 −4
arch/x86/kvm/svm/avic.c +5 −7
arch/x86/kvm/svm/nested.c +19 −4
arch/x86/kvm/svm/sev.c +31 −27
arch/x86/kvm/svm/svm.c +31 −39
arch/x86/kvm/svm/svm.h +6 −35
arch/x86/kvm/trace.h +3 −3
arch/x86/kvm/vmx/capabilities.h +4 −2
arch/x86/kvm/vmx/nested.c +19 −10
arch/x86/kvm/vmx/posted_intr.c +14 −0
arch/x86/kvm/vmx/posted_intr.h +1 −0
arch/x86/kvm/vmx/vmx.c +114 −113
arch/x86/kvm/vmx/vmx.h +10 −2
arch/x86/kvm/x86.c +150 −57
arch/x86/mm/extable.c +1 −1
arch/x86/mm/fault.c +2 −2
arch/x86/mm/ioremap.c +3 −1
arch/x86/mm/mem_encrypt_identity.c +9 −8
arch/x86/mm/numa.c +7 −1
arch/x86/pci/amd_bus.c +1 −1
arch/x86/pci/fixup.c +44 −0
arch/x86/platform/efi/efi_64.c +1 −1
arch/x86/platform/efi/quirks.c +12 −0
arch/x86/realmode/init.c +9 −7
arch/x86/realmode/rm/trampoline_64.S +2 −2
arch/x86/xen/enlighten_pv.c +4 −4
arch/xtensa/kernel/syscalls/syscall.tbl +1 −1
block/bfq-iosched.c +30 −4
block/blk-iocost.c +12 −2
block/blk-mq-sched.c +5 −3
block/blk-mq.c +7 −4
block/genhd.c +1 −10
block/kyber-iosched.c +3 −2
block/mq-deadline.c +1 −2
block/partitions/efi.c +1 −1
crypto/async_tx/async_xor.c +2 −1
drivers/acpi/acpi_apd.c +1 −0
drivers/acpi/acpica/utdelete.c +8 −0
drivers/acpi/bus.c +8 −19
drivers/acpi/device_pm.c +1 −0
drivers/acpi/internal.h +2 −1
drivers/acpi/nfit/core.c +11 −4
drivers/acpi/power.c +47 −14
drivers/acpi/scan.c +3 −0
drivers/acpi/sleep.c +2 −4
drivers/acpi/sleep.h +0 −1
drivers/android/binder.c +1 −1
drivers/base/core.c +38 −33
drivers/base/memory.c +3 −3
drivers/base/power/runtime.c +7 −3
drivers/block/loop.c +7 −18
drivers/block/loop.h +1 −0
drivers/block/nbd.c +5 −5
drivers/bluetooth/btusb.c +23 −2
drivers/bus/mhi/pci_generic.c +38 −4
drivers/bus/ti-sysc.c +54 −6
drivers/cdrom/gdrom.c +10 −3
drivers/char/hpet.c +2 −0
drivers/char/tpm/tpm2-cmd.c +1 −0
drivers/char/tpm/tpm_tis_core.c +14 −8
drivers/clk/clk.c +9 −0
drivers/clocksource/hyperv_timer.c +2 −2
drivers/cpufreq/Kconfig.arm +0 −10
drivers/cpufreq/acpi-cpufreq.c +5 −1
drivers/cpufreq/cppc_cpufreq.c +12 −233
drivers/cpufreq/intel_pstate.c +13 −1
drivers/crypto/cavium/nitrox/nitrox_main.c +0 −1
drivers/dma-buf/dma-buf.c +5 −5
drivers/dma/Kconfig +2 −0
drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c +3 −0
drivers/dma/idxd/cdev.c +1 −0
drivers/dma/idxd/init.c +62 −5
drivers/dma/ipu/ipu_irq.c +1 −1
drivers/dma/mediatek/mtk-uart-apdma.c +14 −13
drivers/dma/pl330.c +4 −2
drivers/dma/qcom/Kconfig +1 −0
drivers/dma/qcom/hidma_mgmt.c +16 −1
drivers/dma/sf-pdma/Kconfig +1 −0
drivers/dma/sh/rcar-dmac.c +1 −1
drivers/dma/ste_dma40.c +3 −0
drivers/dma/stm32-mdma.c +2 −2
drivers/dma/xilinx/xilinx_dpdma.c +28 −3
drivers/dma/xilinx/zynqmp_dma.c +1 −1
drivers/edac/amd64_edac.c +1 −1
drivers/firmware/arm_scmi/notify.h +0 −2
drivers/firmware/arm_scpi.c +3 −1
drivers/firmware/efi/cper.c +1 −3
drivers/firmware/efi/fdtparams.c +3 −0
drivers/firmware/efi/libstub/file.c +1 −1
drivers/firmware/efi/memattr.c +0 −5
drivers/gpio/gpio-cadence.c +1 −0
drivers/gpio/gpio-tegra186.c +0 −11
drivers/gpio/gpio-wcd934x.c +1 −1
drivers/gpio/gpio-xilinx.c +1 −1
drivers/gpu/drm/amd/amdgpu/amdgpu.h +1 −0
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c +6 −6
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c +0 −16
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +17 −3
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +28 −0
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h +1 −0
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +2 −2
drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c +3 −0
drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c +23 −19
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +2 −2
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h +1 −0
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +2 −1
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +30 −8
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +12 −4
drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c +2 −0
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c +2 −4
drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c +2 −4
drivers/gpu/drm/amd/amdgpu/nv.c +23 −15
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c +2 −1
drivers/gpu/drm/amd/amdgpu/psp_v3_1.c +2 −1
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tools/perf/util/stat-display.c +3 −5
tools/perf/util/symbol-elf.c +1 −0
tools/scripts/Makefile.include +15 −15
tools/testing/nvdimm/test/iomap.c +1 −1
tools/testing/nvdimm/test/nfit.c +25 −17
tools/testing/selftests/arm64/bti/test.c +1 −0
tools/testing/selftests/bpf/network_helpers.c +1 −1
tools/testing/selftests/bpf/network_helpers.h +1 −0
tools/testing/selftests/bpf/prog_tests/ringbuf.c +48 −1
tools/testing/selftests/bpf/prog_tests/tc_redirect.c +785 −0
tools/testing/selftests/bpf/progs/test_tc_neigh.c +10 −23
tools/testing/selftests/bpf/progs/test_tc_neigh_fib.c +6 −3
tools/testing/selftests/bpf/progs/test_tc_peer.c +37 −19
tools/testing/selftests/bpf/test_tc_redirect.sh +0 −216
tools/testing/selftests/bpf/test_verifier.c +1 −1
tools/testing/selftests/bpf/verifier/and.c +2 −0
tools/testing/selftests/bpf/verifier/bounds.c +14 −0
tools/testing/selftests/bpf/verifier/dead_code.c +2 −0
tools/testing/selftests/bpf/verifier/jmp32.c +22 −0
tools/testing/selftests/bpf/verifier/jset.c +6 −4
tools/testing/selftests/bpf/verifier/stack_ptr.c +0 −2
tools/testing/selftests/bpf/verifier/unpriv.c +2 −0
tools/testing/selftests/bpf/verifier/value_ptr_arith.c +4 −11
tools/testing/selftests/exec/Makefile +3 −3
tools/testing/selftests/kvm/.gitignore +1 −0
tools/testing/selftests/kvm/Makefile +2 −1
tools/testing/selftests/kvm/demand_paging_test.c +109 −65
tools/testing/selftests/kvm/hardware_disable_test.c +31 −1
tools/testing/selftests/kvm/include/kvm_util.h +9 −5
tools/testing/selftests/kvm/include/test_util.h +12 −0
tools/testing/selftests/kvm/kvm_page_table_test.c +1 −1
tools/testing/selftests/kvm/lib/kvm_util.c +263 −67
tools/testing/selftests/kvm/lib/kvm_util_internal.h +15 −2
tools/testing/selftests/kvm/lib/perf_test_util.c +4 −2
tools/testing/selftests/kvm/lib/rbtree.c +1 −0
tools/testing/selftests/kvm/lib/test_util.c +35 −16
tools/testing/selftests/kvm/lib/x86_64/handlers.S +2 −2
tools/testing/selftests/kvm/lib/x86_64/processor.c +4 −12
tools/testing/selftests/kvm/memslot_modification_stress_test.c +11 −7
tools/testing/selftests/kvm/memslot_perf_test.c +1037 −0
tools/testing/selftests/kvm/x86_64/evmcs_test.c +70 −18
tools/testing/selftests/kvm/x86_64/get_cpuid_test.c +5 −0
tools/testing/selftests/kvm/x86_64/get_msr_index_features.c +2 −6
tools/testing/selftests/nci/.gitignore +1 −0
tools/testing/selftests/net/fib_tests.sh +25 −0
tools/testing/selftests/net/icmp.sh +74 −0
tools/testing/selftests/net/mptcp/mptcp_connect.sh +17 −7
tools/testing/selftests/net/udpgro_fwd.sh +1 −1
tools/testing/selftests/net/veth.sh +3 −2
tools/testing/selftests/netfilter/Makefile +1 −1
tools/testing/selftests/netfilter/nft_fib.sh +221 −0
tools/testing/selftests/perf_events/sigtrap_threads.c +7 −7
tools/testing/selftests/proc/.gitignore +1 −0
tools/testing/selftests/seccomp/seccomp_bpf.c +18 −9
tools/testing/selftests/tc-testing/tc-tests/qdiscs/fq_pie.json +4 −4
tools/testing/selftests/wireguard/netns.sh +1 −0
tools/testing/selftests/wireguard/qemu/kernel.config +0 −1
virt/kvm/kvm_main.c +6 −3
virt/lib/irqbypass.c +6 −10

.clang-format+11−2

@@ -109,8 +109,8 @@ ForEachMacros: · 108 unmodified lines
109	109	- 'css_for_each_child'
110	110	- 'css_for_each_descendant_post'
111	111	- 'css_for_each_descendant_pre'
112		− - 'cxl_for_each_cmd'
113	112	- 'device_for_each_child_node'
	113	+ - 'displayid_iter_for_each'
114	114	- 'dma_fence_chain_for_each'
115	115	- 'do_for_each_ftrace_op'
116	116	- 'drm_atomic_crtc_for_each_plane'
@@ -136,6 +136,7 @@ ForEachMacros: · 19 unmodified lines
136	136	- 'drm_mm_for_each_node_in_range'
137	137	- 'drm_mm_for_each_node_safe'
138	138	- 'flow_action_for_each'
	139	+ - 'for_each_acpi_dev_match'
139	140	- 'for_each_active_dev_scope'
140	141	- 'for_each_active_drhd_unit'
141	142	- 'for_each_active_iommu'
@@ -171,7 +172,6 @@ ForEachMacros: · 29 unmodified lines
171	172	- 'for_each_dapm_widgets'
172	173	- 'for_each_dev_addr'
173	174	- 'for_each_dev_scope'
174		− - 'for_each_displayid_db'
175	175	- 'for_each_dma_cap_mask'
176	176	- 'for_each_dpcm_be'
177	177	- 'for_each_dpcm_be_rollback'
@@ -179,6 +179,7 @@ ForEachMacros: · 1 unmodified line
179	179	- 'for_each_dpcm_fe'
180	180	- 'for_each_drhd_unit'
181	181	- 'for_each_dss_dev'
	182	+ - 'for_each_dtpm_table'
182	183	- 'for_each_efi_memory_desc'
183	184	- 'for_each_efi_memory_desc_in_map'
184	185	- 'for_each_element'
@@ -215,6 +216,7 @@ ForEachMacros: · 30 unmodified lines
215	216	- 'for_each_migratetype_order'
216	217	- 'for_each_msi_entry'
217	218	- 'for_each_msi_entry_safe'
	219	+ - 'for_each_msi_vector'
218	220	- 'for_each_net'
219	221	- 'for_each_net_continue_reverse'
220	222	- 'for_each_netdev'
@@ -270,6 +272,12 @@ ForEachMacros: · 49 unmodified lines
270	272	- 'for_each_prime_number_from'
271	273	- 'for_each_process'
272	274	- 'for_each_process_thread'
	275	+ - 'for_each_prop_codec_conf'
	276	+ - 'for_each_prop_dai_codec'
	277	+ - 'for_each_prop_dai_cpu'
	278	+ - 'for_each_prop_dlc_codecs'
	279	+ - 'for_each_prop_dlc_cpus'
	280	+ - 'for_each_prop_dlc_platforms'
273	281	- 'for_each_property_of_node'
274	282	- 'for_each_registered_fb'
275	283	- 'for_each_requested_gpio'
@@ -430,6 +438,7 @@ ForEachMacros: · 154 unmodified lines
430	438	- 'queue_for_each_hw_ctx'
431	439	- 'radix_tree_for_each_slot'
432	440	- 'radix_tree_for_each_tagged'
	441	+ - 'rb_for_each'
433	442	- 'rbtree_postorder_for_each_entry_safe'
434	443	- 'rdma_for_each_block'
435	444	- 'rdma_for_each_port'

.mailmap+4−0

@@ -160,6 +160,7 @@ Jeff Layton <jlayton@kernel.org> <jlayton@primarydata.com> · 159 unmodified lines
160	160	Jeff Layton <jlayton@kernel.org> <jlayton@redhat.com>
161	161	Jens Axboe <axboe@suse.de>
162	162	Jens Osterkamp <Jens.Osterkamp@de.ibm.com>
	163	+Jernej Skrabec <jernej.skrabec@gmail.com> <jernej.skrabec@siol.net>
163	164	Jiri Slaby <jirislaby@kernel.org> <jirislaby@gmail.com>
164	165	Jiri Slaby <jirislaby@kernel.org> <jslaby@novell.com>
165	166	Jiri Slaby <jirislaby@kernel.org> <jslaby@suse.com>
@@ -242,6 +243,9 @@ Maxime Ripard <mripard@kernel.org> <maxime.ripard@free-electrons.com> · 76 unmodified lines
242	243	Mayuresh Janorkar <mayur@ti.com>
243	244	Michael Buesch <m@bues.ch>
244	245	Michel Dänzer <michel@tungstengraphics.com>
	246	+Michel Lespinasse <michel@lespinasse.org>
	247	+Michel Lespinasse <michel@lespinasse.org> <walken@google.com>
	248	+Michel Lespinasse <michel@lespinasse.org> <walken@zoy.org>
245	249	Miguel Ojeda <ojeda@kernel.org> <miguel.ojeda.sandonis@gmail.com>
246	250	Mike Rapoport <rppt@kernel.org> <mike@compulab.co.il>
247	251	Mike Rapoport <rppt@kernel.org> <mike.rapoport@gmail.com>

Documentation/ABI/obsolete/sysfs-class-dax+1−1

@@ -1,7 +1,7 @@
1	1	What: /sys/class/dax/
2	2	Date: May, 2016
3	3	KernelVersion: v4.7
4		−Contact: linux-nvdimm@lists.01.org
	4	+Contact: nvdimm@lists.linux.dev
5	5	Description: Device DAX is the device-centric analogue of Filesystem
6	6	DAX (CONFIG_FS_DAX). It allows memory ranges to be
7	7	allocated and mapped without need of an intervening file

Documentation/ABI/obsolete/sysfs-kernel-fadump_registered+1−1

@@ -1,4 +1,4 @@
1		−This ABI is renamed and moved to a new location /sys/kernel/fadump/registered.¬
	1	+This ABI is renamed and moved to a new location /sys/kernel/fadump/registered.
2	2
3	3	What: /sys/kernel/fadump_registered
4	4	Date: Feb 2012

Documentation/ABI/obsolete/sysfs-kernel-fadump_release_mem+1−1

@@ -1,4 +1,4 @@
1		−This ABI is renamed and moved to a new location /sys/kernel/fadump/release_mem.¬
	1	+This ABI is renamed and moved to a new location /sys/kernel/fadump/release_mem.
2	2
3	3	What: /sys/kernel/fadump_release_mem
4	4	Date: Feb 2012

Documentation/ABI/removed/sysfs-bus-nfit+1−1

@@ -1,7 +1,7 @@
1	1	What: /sys/bus/nd/devices/regionX/nfit/ecc_unit_size
2	2	Date: Aug, 2017
3	3	KernelVersion: v4.14 (Removed v4.18)
4		−Contact: linux-nvdimm@lists.01.org
	4	+Contact: nvdimm@lists.linux.dev
5	5	Description:
6	6	(RO) Size of a write request to a DIMM that will not incur a
7	7	read-modify-write cycle at the memory controller.

Documentation/ABI/testing/sysfs-bus-nfit+20−20

@@ -5,7 +5,7 @@ Interface Table (NFIT)' section in the ACPI specification · 4 unmodified lines
5	5	What: /sys/bus/nd/devices/nmemX/nfit/serial
6	6	Date: Jun, 2015
7	7	KernelVersion: v4.2
8		−Contact: linux-nvdimm@lists.01.org
	8	+Contact: nvdimm@lists.linux.dev
9	9	Description:
10	10	(RO) Serial number of the NVDIMM (non-volatile dual in-line
11	11	memory module), assigned by the module vendor.
@@ -14,7 +14,7 @@ Description: · 2 unmodified lines
14	14	What: /sys/bus/nd/devices/nmemX/nfit/handle
15	15	Date: Apr, 2015
16	16	KernelVersion: v4.2
17		−Contact: linux-nvdimm@lists.01.org
	17	+Contact: nvdimm@lists.linux.dev
18	18	Description:
19	19	(RO) The address (given by the _ADR object) of the device on its
20	20	parent bus of the NVDIMM device containing the NVDIMM region.
@@ -23,7 +23,7 @@ Description: · 2 unmodified lines
23	23	What: /sys/bus/nd/devices/nmemX/nfit/device
24	24	Date: Apr, 2015
25	25	KernelVersion: v4.1
26		−Contact: linux-nvdimm@lists.01.org
	26	+Contact: nvdimm@lists.linux.dev
27	27	Description:
28	28	(RO) Device id for the NVDIMM, assigned by the module vendor.
29	29
@@ -31,7 +31,7 @@ Description: · 1 unmodified line
31	31	What: /sys/bus/nd/devices/nmemX/nfit/rev_id
32	32	Date: Jun, 2015
33	33	KernelVersion: v4.2
34		−Contact: linux-nvdimm@lists.01.org
	34	+Contact: nvdimm@lists.linux.dev
35	35	Description:
36	36	(RO) Revision of the NVDIMM, assigned by the module vendor.
37	37
@@ -39,7 +39,7 @@ Description: · 1 unmodified line
39	39	What: /sys/bus/nd/devices/nmemX/nfit/phys_id
40	40	Date: Apr, 2015
41	41	KernelVersion: v4.2
42		−Contact: linux-nvdimm@lists.01.org
	42	+Contact: nvdimm@lists.linux.dev
43	43	Description:
44	44	(RO) Handle (i.e., instance number) for the SMBIOS (system
45	45	management BIOS) Memory Device structure describing the NVDIMM
@@ -49,7 +49,7 @@ Description: · 3 unmodified lines
49	49	What: /sys/bus/nd/devices/nmemX/nfit/flags
50	50	Date: Jun, 2015
51	51	KernelVersion: v4.2
52		−Contact: linux-nvdimm@lists.01.org
	52	+Contact: nvdimm@lists.linux.dev
53	53	Description:
54	54	(RO) The flags in the NFIT memory device sub-structure indicate
55	55	the state of the data on the nvdimm relative to its energy
@@ -68,7 +68,7 @@ What: /sys/bus/nd/devices/nmemX/nfit/format1 · 12 unmodified lines
68	68	What: /sys/bus/nd/devices/nmemX/nfit/formats
69	69	Date: Apr, 2016
70	70	KernelVersion: v4.7
71		−Contact: linux-nvdimm@lists.01.org
	71	+Contact: nvdimm@lists.linux.dev
72	72	Description:
73	73	(RO) The interface codes indicate support for persistent memory
74	74	mapped directly into system physical address space and / or a
@@ -84,7 +84,7 @@ Description: · 9 unmodified lines
84	84	What: /sys/bus/nd/devices/nmemX/nfit/vendor
85	85	Date: Apr, 2016
86	86	KernelVersion: v4.7
87		−Contact: linux-nvdimm@lists.01.org
	87	+Contact: nvdimm@lists.linux.dev
88	88	Description:
89	89	(RO) Vendor id of the NVDIMM.
90	90
@@ -92,7 +92,7 @@ Description: · 1 unmodified line
92	92	What: /sys/bus/nd/devices/nmemX/nfit/dsm_mask
93	93	Date: May, 2016
94	94	KernelVersion: v4.7
95		−Contact: linux-nvdimm@lists.01.org
	95	+Contact: nvdimm@lists.linux.dev
96	96	Description:
97	97	(RO) The bitmask indicates the supported device specific control
98	98	functions relative to the NVDIMM command family supported by the
@@ -102,7 +102,7 @@ Description: · 3 unmodified lines
102	102	What: /sys/bus/nd/devices/nmemX/nfit/family
103	103	Date: Apr, 2016
104	104	KernelVersion: v4.7
105		−Contact: linux-nvdimm@lists.01.org
	105	+Contact: nvdimm@lists.linux.dev
106	106	Description:
107	107	(RO) Displays the NVDIMM family command sets. Values
108	108	0, 1, 2 and 3 correspond to NVDIMM_FAMILY_INTEL,
@@ -118,7 +118,7 @@ Description: · 9 unmodified lines
118	118	What: /sys/bus/nd/devices/nmemX/nfit/id
119	119	Date: Apr, 2016
120	120	KernelVersion: v4.7
121		−Contact: linux-nvdimm@lists.01.org
	121	+Contact: nvdimm@lists.linux.dev
122	122	Description:
123	123	(RO) ACPI specification 6.2 section 5.2.25.9, defines an
124	124	identifier for an NVDIMM, which refelects the id attribute.
@@ -127,7 +127,7 @@ Description: · 2 unmodified lines
127	127	What: /sys/bus/nd/devices/nmemX/nfit/subsystem_vendor
128	128	Date: Apr, 2016
129	129	KernelVersion: v4.7
130		−Contact: linux-nvdimm@lists.01.org
	130	+Contact: nvdimm@lists.linux.dev
131	131	Description:
132	132	(RO) Sub-system vendor id of the NVDIMM non-volatile memory
133	133	subsystem controller.
@@ -136,7 +136,7 @@ Description: · 2 unmodified lines
136	136	What: /sys/bus/nd/devices/nmemX/nfit/subsystem_rev_id
137	137	Date: Apr, 2016
138	138	KernelVersion: v4.7
139		−Contact: linux-nvdimm@lists.01.org
	139	+Contact: nvdimm@lists.linux.dev
140	140	Description:
141	141	(RO) Sub-system revision id of the NVDIMM non-volatile memory subsystem
142	142	controller, assigned by the non-volatile memory subsystem
@@ -146,7 +146,7 @@ Description: · 3 unmodified lines
146	146	What: /sys/bus/nd/devices/nmemX/nfit/subsystem_device
147	147	Date: Apr, 2016
148	148	KernelVersion: v4.7
149		−Contact: linux-nvdimm@lists.01.org
	149	+Contact: nvdimm@lists.linux.dev
150	150	Description:
151	151	(RO) Sub-system device id for the NVDIMM non-volatile memory
152	152	subsystem controller, assigned by the non-volatile memory
@@ -156,7 +156,7 @@ Description: · 3 unmodified lines
156	156	What: /sys/bus/nd/devices/ndbusX/nfit/revision
157	157	Date: Jun, 2015
158	158	KernelVersion: v4.2
159		−Contact: linux-nvdimm@lists.01.org
	159	+Contact: nvdimm@lists.linux.dev
160	160	Description:
161	161	(RO) ACPI NFIT table revision number.
162	162
@@ -164,7 +164,7 @@ Description: · 1 unmodified line
164	164	What: /sys/bus/nd/devices/ndbusX/nfit/scrub
165	165	Date: Sep, 2016
166	166	KernelVersion: v4.9
167		−Contact: linux-nvdimm@lists.01.org
	167	+Contact: nvdimm@lists.linux.dev
168	168	Description:
169	169	(RW) This shows the number of full Address Range Scrubs (ARS)
170	170	that have been completed since driver load time. Userspace can
@@ -177,7 +177,7 @@ Description: · 6 unmodified lines
177	177	What: /sys/bus/nd/devices/ndbusX/nfit/hw_error_scrub
178	178	Date: Sep, 2016
179	179	KernelVersion: v4.9
180		−Contact: linux-nvdimm@lists.01.org
	180	+Contact: nvdimm@lists.linux.dev
181	181	Description:
182	182	(RW) Provides a way to toggle the behavior between just adding
183	183	the address (cache line) where the MCE happened to the poison
@@ -196,7 +196,7 @@ Description: · 12 unmodified lines
196	196	What: /sys/bus/nd/devices/ndbusX/nfit/dsm_mask
197	197	Date: Jun, 2017
198	198	KernelVersion: v4.13
199		−Contact: linux-nvdimm@lists.01.org
	199	+Contact: nvdimm@lists.linux.dev
200	200	Description:
201	201	(RO) The bitmask indicates the supported bus specific control
202	202	functions. See the section named 'NVDIMM Root Device _DSMs' in
@@ -205,7 +205,7 @@ Description: · 2 unmodified lines
205	205	What: /sys/bus/nd/devices/ndbusX/nfit/firmware_activate_noidle
206	206	Date: Apr, 2020
207	207	KernelVersion: v5.8
208		−Contact: linux-nvdimm@lists.01.org
	208	+Contact: nvdimm@lists.linux.dev
209	209	Description:
210	210	(RW) The Intel platform implementation of firmware activate
211	211	support exposes an option let the platform force idle devices in
@@ -225,7 +225,7 @@ Description: · 13 unmodified lines
225	225	What: /sys/bus/nd/devices/regionX/nfit/range_index
226	226	Date: Jun, 2015
227	227	KernelVersion: v4.2
228		−Contact: linux-nvdimm@lists.01.org
	228	+Contact: nvdimm@lists.linux.dev
229	229	Description:
230	230	(RO) A unique number provided by the BIOS to identify an address
231	231	range. Used by NVDIMM Region Mapping Structure to uniquely refer

Documentation/ABI/testing/sysfs-bus-papr-pmem+2−2

@@ -1,7 +1,7 @@
1	1	What: /sys/bus/nd/devices/nmemX/papr/flags
2	2	Date: Apr, 2020
3	3	KernelVersion: v5.8
4		−Contact: linuxppc-dev <linuxppc-dev@lists.ozlabs.org>, linux-nvdimm@lists.01.org,
	4	+Contact: linuxppc-dev <linuxppc-dev@lists.ozlabs.org>, nvdimm@lists.linux.dev,
5	5	Description:
6	6	(RO) Report flags indicating various states of a
7	7	papr-pmem NVDIMM device. Each flag maps to a one or
@@ -36,7 +36,7 @@ Description: · 28 unmodified lines
36	36	What: /sys/bus/nd/devices/nmemX/papr/perf_stats
37	37	Date: May, 2020
38	38	KernelVersion: v5.9
39		−Contact: linuxppc-dev <linuxppc-dev@lists.ozlabs.org>, linux-nvdimm@lists.01.org,
	39	+Contact: linuxppc-dev <linuxppc-dev@lists.ozlabs.org>, nvdimm@lists.linux.dev,
40	40	Description:
41	41	(RO) Report various performance stats related to papr-scm NVDIMM
42	42	device. Each stat is reported on a new line with each line

Documentation/ABI/testing/sysfs-module+2−2

@@ -37,13 +37,13 @@ Description: Maximum time allowed for periodic transfers per microframe (μs) · 36 unmodified lines
37	37
38	38	What: /sys/module/*/{coresize,initsize}
39	39	Date: Jan 2012
40		−KernelVersion:»·3.3
	40	+KernelVersion: 3.3
41	41	Contact: Kay Sievers <kay.sievers@vrfy.org>
42	42	Description: Module size in bytes.
43	43
44	44	What: /sys/module/*/taint
45	45	Date: Jan 2012
46		−KernelVersion:»·3.3
	46	+KernelVersion: 3.3
47	47	Contact: Kay Sievers <kay.sievers@vrfy.org>
48	48	Description: Module taint flags:
49	49	== =====================

Documentation/admin-guide/sysctl/kernel.rst+19−7

@@ -483,10 +483,11 @@ modprobe · 482 unmodified lines
483	483	========
484	484
485	485	The full path to the usermode helper for autoloading kernel modules,
486		−by default "/sbin/modprobe". This binary is executed when the kernel
487		−requests a module. For example, if userspace passes an unknown
488		−filesystem type to mount(), then the kernel will automatically request
489		−the corresponding filesystem module by executing this usermode helper.
	486	+by default ``CONFIG_MODPROBE_PATH``, which in turn defaults to
	487	+"/sbin/modprobe". This binary is executed when the kernel requests a
	488	+module. For example, if userspace passes an unknown filesystem type
	489	+to mount(), then the kernel will automatically request the
	490	+corresponding filesystem module by executing this usermode helper.
490	491	This usermode helper should insert the needed module into the kernel.
491	492
492	493	This sysctl only affects module autoloading. It has no effect on the
@@ -1457,11 +1458,22 @@ unprivileged_bpf_disabled · 964 unmodified lines
1457	1458	=========================
1458	1459
1459	1460	Writing 1 to this entry will disable unprivileged calls to ``bpf()``;
1460		−once disabled, calling ``bpf()`` without ``CAP_SYS_ADMIN`` will return
1461		−``-EPERM``.
	1461	+once disabled, calling ``bpf()`` without ``CAP_SYS_ADMIN`` or ``CAP_BPF``
	1462	+will return ``-EPERM``. Once set to 1, this can't be cleared from the
	1463	+running kernel anymore.
1462	1464
1463		−Once set, this can't be cleared.
	1465	+Writing 2 to this entry will also disable unprivileged calls to ``bpf()``,
	1466	+however, an admin can still change this setting later on, if needed, by
	1467	+writing 0 or 1 to this entry.
1464	1468
	1469	+If ``BPF_UNPRIV_DEFAULT_OFF`` is enabled in the kernel config, then this
	1470	+entry will default to 2 instead of 0.
	1471	+
	1472	+= =============================================================
	1473	+0 Unprivileged calls to ``bpf()`` are enabled
	1474	+1 Unprivileged calls to ``bpf()`` are disabled without recovery
	1475	+2 Unprivileged calls to ``bpf()`` are disabled
	1476	+= =============================================================
1465	1477
1466	1478	watchdog
1467	1479	========

Documentation/block/data-integrity.rst+1−1

@@ -1,4 +1,4 @@
1		−==============
	1	+==============
2	2	Data Integrity
3	3	==============
4	4

Documentation/cdrom/cdrom-standard.rst+15−15

@@ -146,18 +146,18 @@ with the kernel as a block device by registering the following general · 145 unmodified lines
146	146	struct file_operations::
147	147
148	148	struct file_operations cdrom_fops = {
149		− NULL, /∗ lseek ∗/
150		− block _read , /∗ read—general block-dev read ∗/
151		− block _write, /∗ write—general block-dev write ∗/
152		− NULL, /∗ readdir ∗/
153		− NULL, /∗ select ∗/
154		− cdrom_ioctl, /∗ ioctl ∗/
155		− NULL, /∗ mmap ∗/
156		− cdrom_open, /∗ open ∗/
157		− cdrom_release, /∗ release ∗/
158		− NULL, /∗ fsync ∗/
159		− NULL, /∗ fasync ∗/
160		− NULL /∗ revalidate ∗/
	149	+ NULL, /* lseek */
	150	+ block _read , /* read--general block-dev read */
	151	+ block _write, /* write--general block-dev write */
	152	+ NULL, /* readdir */
	153	+ NULL, /* select */
	154	+ cdrom_ioctl, /* ioctl */
	155	+ NULL, /* mmap */
	156	+ cdrom_open, /* open */
	157	+ cdrom_release, /* release */
	158	+ NULL, /* fsync */
	159	+ NULL, /* fasync */
	160	+ NULL /* revalidate */
161	161	};
162	162
163	163	Every active CD-ROM device shares this struct. The routines
@@ -250,12 +250,12 @@ The drive-specific, minor-like information that is registered with · 86 unmodified lines
250	250	`cdrom.c`, currently contains the following fields::
251	251
252	252	struct cdrom_device_info {
253		− const struct cdrom_device_ops * ops; /* device operations for this major */
	253	+ const struct cdrom_device_ops * ops; /* device operations for this major */
254	254	struct list_head list; /* linked list of all device_info */
255	255	struct gendisk * disk; /* matching block layer disk */
256	256	void * handle; /* driver-dependent data */
257	257
258		− int mask; /* mask of capability: disables them */
	258	+ int mask; /* mask of capability: disables them */
259	259	int speed; /* maximum speed for reading data */
260	260	int capacity; /* number of discs in a jukebox */
261	261
@@ -569,7 +569,7 @@ the CDC_CLOSE_TRAY bit in mask. · 307 unmodified lines
569	569
570	570	In the file `cdrom.c` you will encounter many constructions of the type::
571	571
572		− if (cdo->capability & ∼cdi->mask & CDC _⟨capability⟩) ...
	572	+ if (cdo->capability & ~cdi->mask & CDC _<capability>) ...
573	573
574	574	There is no ioctl to set the mask... The reason is that
575	575	I think it is better to control the behavior rather than the

Documentation/devicetree/bindings/clock/idt,versaclock5.yaml+0−2

@@ -60,7 +60,6 @@ properties: · 59 unmodified lines
60	60	maxItems: 2
61	61
62	62	idt,xtal-load-femtofarads:
63		− $ref: /schemas/types.yaml#/definitions/uint32
64	63	minimum: 9000
65	64	maximum: 22760
66	65	description: Optional load capacitor for XTAL1 and XTAL2
@@ -84,7 +83,6 @@ patternProperties: · 17 unmodified lines
84	83	enum: [ 1800000, 2500000, 3300000 ]
85	84	idt,slew-percent:
86	85	description: The Slew rate control for CMOS single-ended.
87		− $ref: /schemas/types.yaml#/definitions/uint32
88	86	enum: [ 80, 85, 90, 100 ]
89	87
90	88	required:

Documentation/devicetree/bindings/connector/usb-connector.yaml+15−0

@@ -149,6 +149,17 @@ properties: · 148 unmodified lines
149	149	maxItems: 6
150	150	$ref: /schemas/types.yaml#/definitions/uint32-array
151	151
	152	+ sink-vdos-v1:
	153	+ description: An array of u32 with each entry, a Vendor Defined Message Object (VDO),
	154	+ providing additional information corresponding to the product, the detailed bit
	155	+ definitions and the order of each VDO can be found in
	156	+ "USB Power Delivery Specification Revision 2.0, Version 1.3" chapter 6.4.4.3.1 Discover
	157	+ Identity. User can specify the VDO array via VDO_IDH/_CERT/_PRODUCT/_CABLE/_AMA defined in
	158	+ dt-bindings/usb/pd.h.
	159	+ minItems: 3
	160	+ maxItems: 6
	161	+ $ref: /schemas/types.yaml#/definitions/uint32-array
	162	+
152	163	op-sink-microwatt:
153	164	description: Sink required operating power in microwatt, if source can't
154	165	offer the power, Capability Mismatch is set. Required for power sink and
@@ -207,6 +218,10 @@ properties: · 52 unmodified lines
207	218	SNK_READY for non-pd link.
208	219	type: boolean
209	220
	221	+dependencies:
	222	+ sink-vdos-v1: [ 'sink-vdos' ]
	223	+ sink-vdos: [ 'sink-vdos-v1' ]
	224	+
210	225	required:
211	226	- compatible
212	227

Documentation/devicetree/bindings/hwmon/ti,ads7828.yaml+1−1

@@ -49,7 +49,7 @@ examples: · 48 unmodified lines
49	49	#size-cells = <0>;
50	50
51	51	adc@48 {
52		− comatible = "ti,ads7828";
	52	+ compatible = "ti,ads7828";
53	53	reg = <0x48>;
54	54	vref-supply = <&vref>;
55	55	ti,differential-input;

Documentation/devicetree/bindings/i2c/i2c-mpc.yaml+7−0

@@ -46,6 +46,13 @@ properties: · 45 unmodified lines
46	46	description: \|
47	47	I2C bus timeout in microseconds
48	48
	49	+ fsl,i2c-erratum-a004447:
	50	+ $ref: /schemas/types.yaml#/definitions/flag
	51	+ description: \|
	52	+ Indicates the presence of QorIQ erratum A-004447, which
	53	+ says that the standard i2c recovery scheme mechanism does
	54	+ not work and an alternate implementation is needed.
	55	+
49	56	required:
50	57	- compatible
51	58	- reg

Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml+0−1

@@ -102,7 +102,6 @@ patternProperties: · 101 unmodified lines
102	102
103	103	st,adc-channel-names:
104	104	description: List of single-ended channel names.
105		− $ref: /schemas/types.yaml#/definitions/string-array
106	105
107	106	st,filter-order:
108	107	description: \|

Documentation/devicetree/bindings/input/input.yaml+0−1

@@ -38,6 +38,5 @@ properties: · 37 unmodified lines
38	38	Duration in seconds which the key should be kept pressed for device to
39	39	reset automatically. Device with key pressed reset feature can specify
40	40	this property.
41		− $ref: /schemas/types.yaml#/definitions/uint32
42	41
43	42	additionalProperties: true

Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml+0−1

@@ -92,7 +92,6 @@ properties: · 91 unmodified lines
92	92	this interconnect to send RPMh commands.
93	93
94	94	qcom,bcm-voter-names:
95		− $ref: /schemas/types.yaml#/definitions/string-array
96	95	description: \|
97	96	Names for each of the qcom,bcm-voters specified.
98	97

Documentation/devicetree/bindings/leds/leds-bcm6328.txt+2−2

@@ -4,8 +4,8 @@ This controller is present on BCM6318, BCM6328, BCM6362 and BCM63268. · 3 unmodified lines
4	4	In these SoCs it's possible to control LEDs both as GPIOs or by hardware.
5	5	However, on some devices there are Serial LEDs (LEDs connected to a 74x164
6	6	controller), which can either be controlled by software (exporting the 74x164
7		−as spi-gpio. See Documentation/devicetree/bindings/gpio/gpio-74x164.txt), or
8		−by hardware using this driver.
	7	+as spi-gpio. See Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml),
	8	+or by hardware using this driver.
9	9	Some of these Serial LEDs are hardware controlled (e.g. ethernet LEDs) and
10	10	exporting the 74x164 as spi-gpio prevents those LEDs to be hardware
11	11	controlled, so the only chance to keep them working is by using this driver.

Documentation/devicetree/bindings/leds/leds-bcm6358.txt+1−1

@@ -3,7 +3,7 @@ LEDs connected to Broadcom BCM6358 controller · 2 unmodified lines
3	3	This controller is present on BCM6358 and BCM6368.
4	4	In these SoCs there are Serial LEDs (LEDs connected to a 74x164 controller),
5	5	which can either be controlled by software (exporting the 74x164 as spi-gpio.
6		−See Documentation/devicetree/bindings/gpio/gpio-74x164.txt), or
	6	+See Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml), or
7	7	by hardware using this driver.
8	8
9	9	Required properties:

Documentation/devicetree/bindings/media/renesas,drif.yaml+8−16

@@ -67,9 +67,7 @@ properties: · 66 unmodified lines
67	67	maxItems: 1
68	68
69	69	clock-names:
70		− maxItems: 1
71		− items:
72		− - const: fck
	70	+ const: fck
73	71
74	72	resets:
75	73	maxItems: 1
@@ -99,32 +97,26 @@ properties: · 23 unmodified lines
99	97	Indicates that the channel acts as primary among the bonded channels.
100	98
101	99	port:
102		− type: object
	100	+ $ref: /schemas/graph.yaml#/properties/port
	101	+ unevaluatedProperties: false
103	102	description:
104		− Child port node corresponding to the data input, in accordance with the
105		− video interface bindings defined in
106		− Documentation/devicetree/bindings/media/video-interfaces.txt.
107		− The port node must contain at least one endpoint.
	103	+ Child port node corresponding to the data input. The port node must
	104	+ contain at least one endpoint.
108	105
109	106	properties:
110	107	endpoint:
111		− type: object
	108	+ $ref: /schemas/graph.yaml#/$defs/endpoint-base
	109	+ unevaluatedProperties: false
112	110
113	111	properties:
114		− remote-endpoint:
115		− description:
116		− A phandle to the remote tuner endpoint subnode in remote node
117		− port.
118		−
119	112	sync-active:
	113	+ $ref: /schemas/types.yaml#/definitions/uint32
120	114	enum: [0, 1]
121	115	description:
122	116	Indicates sync signal polarity, 0/1 for low/high respectively.
123	117	This property maps to SYNCAC bit in the hardware manual. The
124	118	default is 1 (active high).
125	119
126		− additionalProperties: false
127		−
128	120	required:
129	121	- compatible
130	122	- reg

Documentation/devicetree/bindings/net/qcom,ipa.yaml+0−1

@@ -105,7 +105,6 @@ properties: · 104 unmodified lines
105	105	- description: Whether the IPA clock is enabled (if valid)
106	106
107	107	qcom,smem-state-names:
108		− $ref: /schemas/types.yaml#/definitions/string-array
109	108	description: The names of the state bits used for SMP2P output
110	109	items:
111	110	- const: ipa-clock-enabled-valid

Documentation/devicetree/bindings/net/renesas,ether.yaml+1−1

@@ -10,7 +10,7 @@ allOf: · 9 unmodified lines
10	10	- $ref: ethernet-controller.yaml#
11	11
12	12	maintainers:
13		− - Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
	13	+ - Sergei Shtylyov <sergei.shtylyov@gmail.com>
14	14
15	15	properties:
16	16	compatible:

Documentation/devicetree/bindings/nvmem/mtk-efuse.txt+0−1

@@ -9,7 +9,6 @@ Required properties: · 8 unmodified lines
9	9	"mediatek,mt8173-efuse" or "mediatek,efuse": for MT8173
10	10	"mediatek,mt8192-efuse", "mediatek,efuse": for MT8192
11	11	"mediatek,mt8516-efuse", "mediatek,efuse": for MT8516
12		− "mediatek,mt8192-efuse", "mediatek,efuse": for MT8192
13	12	- reg: Should contain registers location and length
14	13
15	14	= Data cells =

Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml+1−1

@@ -118,7 +118,7 @@ patternProperties: · 117 unmodified lines
118	118	description:
119	119	Specifies the Spread Spectrum Clocking mode used. It can be NO_SSC,
120	120	EXTERNAL_SSC or INTERNAL_SSC.
121		− Refer include/dt-bindings/phy/phy-cadence-torrent.h for the constants to be used.
	121	+ Refer include/dt-bindings/phy/phy-cadence.h for the constants to be used.
122	122	$ref: /schemas/types.yaml#/definitions/uint32
123	123	enum: [0, 1, 2]
124	124	default: 0

Documentation/devicetree/bindings/power/supply/sc2731-charger.yaml+1−1

@@ -20,7 +20,7 @@ properties: · 19 unmodified lines
20	20	maxItems: 1
21	21
22	22	phys:
23		− $ref: /schemas/types.yaml#/definitions/phandle
	23	+ maxItems: 1
24	24	description: phandle to the USB phy
25	25
26	26	monitored-battery:

Documentation/devicetree/bindings/sound/amlogic,gx-sound-card.yaml+2−2

@@ -57,7 +57,7 @@ patternProperties: · 56 unmodified lines
57	57	rate
58	58
59	59	sound-dai:
60		− $ref: /schemas/types.yaml#/definitions/phandle
	60	+ $ref: /schemas/types.yaml#/definitions/phandle-array
61	61	description: phandle of the CPU DAI
62	62
63	63	patternProperties:
@@ -71,7 +71,7 @@ patternProperties: · 7 unmodified lines
71	71
72	72	properties:
73	73	sound-dai:
74		− $ref: /schemas/types.yaml#/definitions/phandle
	74	+ $ref: /schemas/types.yaml#/definitions/phandle-array
75	75	description: phandle of the codec DAI
76	76
77	77	required:

Documentation/devicetree/bindings/sound/fsl,rpmsg.yaml+1−1

@@ -49,7 +49,7 @@ properties: · 48 unmodified lines
49	49	maxItems: 1
50	50
51	51	memory-region:
52		− $ref: /schemas/types.yaml#/definitions/phandle
	52	+ maxItems: 1
53	53	description:
54	54	phandle to a node describing reserved memory (System RAM memory)
55	55	The M core can't access all the DDR memory space on some platform,

Documentation/devicetree/bindings/spi/spi-mux.yaml+1−1

@@ -72,7 +72,7 @@ examples: · 71 unmodified lines
72	72
73	73	mux-controls = <&mux>;
74	74
75		− spi-flash@0 {
	75	+ flash@0 {
76	76	compatible = "jedec,spi-nor";
77	77	reg = <0>;
78	78	spi-max-frequency = <40000000>;

Documentation/driver-api/nvdimm/nvdimm.rst+1−1

@@ -4,7 +4,7 @@ LIBNVDIMM: Non-Volatile Devices · 3 unmodified lines
4	4
5	5	libnvdimm - kernel / libndctl - userspace helper library
6	6
7		−linux-nvdimm@lists.01.org
	7	+nvdimm@lists.linux.dev
8	8
9	9	Version 13
10	10

Documentation/driver-api/serial/index.rst+0−1

@@ -19,7 +19,6 @@ Serial drivers · 18 unmodified lines
19	19
20	20	moxa-smartio
21	21	n_gsm
22		− rocket
23	22	serial-iso7816
24	23	serial-rs485
25	24

Documentation/driver-api/usb/usb.rst+11−6

@@ -109,16 +109,21 @@ well as to make sure they aren't relying on some HCD-specific behavior. · 108 unmodified lines
109	109	USB-Standard Types
110	110	==================
111	111
112		−In ``drivers/usb/common/common.c`` and ``drivers/usb/common/debug.c`` you
113		−will find the USB data types defined in chapter 9 of the USB specification.
114		−These data types are used throughout USB, and in APIs including this host
115		−side API, gadget APIs, usb character devices and debugfs interfaces.
	112	+In ``include/uapi/linux/usb/ch9.h`` you will find the USB data types defined
	113	+in chapter 9 of the USB specification. These data types are used throughout
	114	+USB, and in APIs including this host side API, gadget APIs, usb character
	115	+devices and debugfs interfaces. That file is itself included by
	116	+``include/linux/usb/ch9.h``, which also contains declarations of a few
	117	+utility routines for manipulating these data types; the implementations
	118	+are in ``drivers/usb/common/common.c``.
116	119
117	120	.. kernel-doc:: drivers/usb/common/common.c
118	121	:export:
119	122
120		−.. kernel-doc:: drivers/usb/common/debug.c
121		− :export:
	123	+In addition, some functions useful for creating debugging output are
	124	+defined in ``drivers/usb/common/debug.c``.
	125	+
	126	+.. _usb_header:
122	127
123	128	Host-Side Data Types and Macros
124	129	===============================

Documentation/filesystems/erofs.rst+102−73

@@ -50,8 +50,8 @@ Here is the main features of EROFS: · 49 unmodified lines
50	50
51	51	- Support POSIX.1e ACLs by using xattrs;
52	52
53		− - Support transparent file compression as an option:
54		− LZ4 algorithm with 4 KB fixed-sized output compression for high performance.
	53	+ - Support transparent data compression as an option:
	54	+ LZ4 algorithm with the fixed-sized output compression for high performance.
55	55
56	56	The following git tree provides the file system user-space tools under
57	57	development (ex, formatting tool mkfs.erofs):
@@ -113,31 +113,31 @@ may not. All metadatas can be now observed in two different spaces (views): · 55 unmodified lines
113	113
114	114	::
115	115
116		− \|-> aligned with 8B
117		− \|-> followed closely
118		− + meta_blkaddr blocks \|-> another slot
119		− _____________________________________________________________________
120		− \| ... \| inode \| xattrs \| extents \| data inline \| ... \| inode ...
121		− \|________\|_______\|(optional)\|(optional)\|__(optional)_\|_____\|__________
122		− \|-> aligned with the inode slot size
123		− . .
124		− . .
125		− . .
126		− . .
127		− . .
128		− . .
129		− .____________________________________________________\|-> aligned with 4B
130		− \| xattr_ibody_header \| shared xattrs \| inline xattrs \|
131		− \|____________________\|_______________\|_______________\|
132		− \|-> 12 bytes <-\|->x * 4 bytes<-\| .
133		− . . .
134		− . . .
135		− . . .
136		− ._______________________________.______________________.
137		− \| id \| id \| id \| id \| ... \| id \| ent \| ... \| ent\| ... \|
138		− \|____\|____\|____\|____\|______\|____\|_____\|_____\|____\|_____\|
139		− \|-> aligned with 4B
140		− \|-> aligned with 4B
	116	+ \|-> aligned with 8B
	117	+ \|-> followed closely
	118	+ + meta_blkaddr blocks \|-> another slot
	119	+ _____________________________________________________________________
	120	+ \| ... \| inode \| xattrs \| extents \| data inline \| ... \| inode ...
	121	+ \|________\|_______\|(optional)\|(optional)\|__(optional)_\|_____\|__________
	122	+ \|-> aligned with the inode slot size
	123	+ . .
	124	+ . .
	125	+ . .
	126	+ . .
	127	+ . .
	128	+ . .
	129	+ .____________________________________________________\|-> aligned with 4B
	130	+ \| xattr_ibody_header \| shared xattrs \| inline xattrs \|
	131	+ \|____________________\|_______________\|_______________\|
	132	+ \|-> 12 bytes <-\|->x * 4 bytes<-\| .
	133	+ . . .
	134	+ . . .
	135	+ . . .
	136	+ ._______________________________.______________________.
	137	+ \| id \| id \| id \| id \| ... \| id \| ent \| ... \| ent\| ... \|
	138	+ \|____\|____\|____\|____\|______\|____\|_____\|_____\|____\|_____\|
	139	+ \|-> aligned with 4B
	140	+ \|-> aligned with 4B
141	141
142	142	Inode could be 32 or 64 bytes, which can be distinguished from a common
143	143	field which all inode versions have -- i_format::
@@ -175,13 +175,13 @@ may not. All metadatas can be now observed in two different spaces (views): · 31 unmodified lines
175	175	Each share xattr can also be directly found by the following formula:
176	176	xattr offset = xattr_blkaddr * block_size + 4 * xattr_id
177	177
178		− ::
	178	+::
179	179
180		− \|-> aligned by 4 bytes
181		− + xattr_blkaddr blocks \|-> aligned with 4 bytes
182		− _________________________________________________________________________
183		− \| ... \| xattr_entry \| xattr data \| ... \| xattr_entry \| xattr data ...
184		− \|________\|_____________\|_____________\|_____\|______________\|_______________
	180	+ \|-> aligned by 4 bytes
	181	+ + xattr_blkaddr blocks \|-> aligned with 4 bytes
	182	+ _________________________________________________________________________
	183	+ \| ... \| xattr_entry \| xattr data \| ... \| xattr_entry \| xattr data ...
	184	+ \|________\|_____________\|_____________\|_____\|______________\|_______________
185	185
186	186	Directories
187	187	-----------
@@ -193,48 +193,77 @@ algorithm (could refer to the related source code). · 5 unmodified lines
193	193
194	194	::
195	195
196		− ___________________________
197		− / \|
198		− / ______________\|________________
199		− / / \| nameoff1 \| nameoffN-1
200		− ____________.______________._______________v________________v__________
201		− \| dirent \| dirent \| ... \| dirent \| filename \| filename \| ... \| filename \|
202		− \|___.0___\|____1___\|_____\|___N-1__\|____0_____\|____1_____\|_____\|___N-1____\|
203		− \ ^
204		− \ \| * could have
205		− \ \| trailing '\0'
206		− \________________________\| nameoff0
207		−
208		− Directory block
	196	+ ___________________________
	197	+ / \|
	198	+ / ______________\|________________
	199	+ / / \| nameoff1 \| nameoffN-1
	200	+ ____________.______________._______________v________________v__________
	201	+ \| dirent \| dirent \| ... \| dirent \| filename \| filename \| ... \| filename \|
	202	+ \|___.0___\|____1___\|_____\|___N-1__\|____0_____\|____1_____\|_____\|___N-1____\|
	203	+ \ ^
	204	+ \ \| * could have
	205	+ \ \| trailing '\0'
	206	+ \________________________\| nameoff0
	207	+ Directory block
209	208
210	209	Note that apart from the offset of the first filename, nameoff0 also indicates
211	210	the total number of directory entries in this block since it is no need to
212	211	introduce another on-disk field at all.
213	212
214		−Compression
215		−-----------
216		−Currently, EROFS supports 4KB fixed-sized output transparent file compression,
217		−as illustrated below::
218		−
219		− \|---- Variant-Length Extent ----\|-------- VLE --------\|----- VLE -----
220		− clusterofs clusterofs clusterofs
221		− \| \| \| logical data
222		− _________v_______________________________v_____________________v_______________
223		− ... \| . \| \| . \| \| . \| ...
224		− ____\|____.________\|_____________\|________.____\|_____________\|__.__________\|____
225		− \|-> cluster <-\|-> cluster <-\|-> cluster <-\|-> cluster <-\|-> cluster <-\|
226		− size size size size size
227		− . . . .
228		− . . . .
229		− . . . .
230		− _______._____________._____________._____________._____________________
231		− ... \| \| \| \| ... physical data
232		− _______\|_____________\|_____________\|_____________\|_____________________
233		− \|-> cluster <-\|-> cluster <-\|-> cluster <-\|
234		− size size size
235		−
236		−Currently each on-disk physical cluster can contain 4KB (un)compressed data
237		−at most. For each logical cluster, there is a corresponding on-disk index to
238		−describe its cluster type, physical cluster address, etc.
239		−
240		−See "struct z_erofs_vle_decompressed_index" in erofs_fs.h for more details.
	213	+Data compression
	214	+----------------
	215	+EROFS implements LZ4 fixed-sized output compression which generates fixed-sized
	216	+compressed data blocks from variable-sized input in contrast to other existing
	217	+fixed-sized input solutions. Relatively higher compression ratios can be gotten
	218	+by using fixed-sized output compression since nowadays popular data compression
	219	+algorithms are mostly LZ77-based and such fixed-sized output approach can be
	220	+benefited from the historical dictionary (aka. sliding window).
	221	+
	222	+In details, original (uncompressed) data is turned into several variable-sized
	223	+extents and in the meanwhile, compressed into physical clusters (pclusters).
	224	+In order to record each variable-sized extent, logical clusters (lclusters) are
	225	+introduced as the basic unit of compress indexes to indicate whether a new
	226	+extent is generated within the range (HEAD) or not (NONHEAD). Lclusters are now
	227	+fixed in block size, as illustrated below::
	228	+
	229	+ \|<- variable-sized extent ->\|<- VLE ->\|
	230	+ clusterofs clusterofs clusterofs
	231	+ \| \| \|
	232	+ _________v_________________________________v_______________________v________
	233	+ ... \| . \| \| . \| \| . ...
	234	+ ____\|____._________\|______________\|________.___ _\|______________\|__.________
	235	+ \|-> lcluster <-\|-> lcluster <-\|-> lcluster <-\|-> lcluster <-\|
	236	+ (HEAD) (NONHEAD) (HEAD) (NONHEAD) .
	237	+ . CBLKCNT . .
	238	+ . . .
	239	+ . . .
	240	+ _______._____________________________.______________._________________
	241	+ ... \| \| \| \| ...
	242	+ _______\|______________\|______________\|______________\|_________________
	243	+ \|-> big pcluster <-\|-> pcluster <-\|
	244	+
	245	+A physical cluster can be seen as a container of physical compressed blocks
	246	+which contains compressed data. Previously, only lcluster-sized (4KB) pclusters
	247	+were supported. After big pcluster feature is introduced (available since
	248	+Linux v5.13), pcluster can be a multiple of lcluster size.
	249	+
	250	+For each HEAD lcluster, clusterofs is recorded to indicate where a new extent
	251	+starts and blkaddr is used to seek the compressed data. For each NONHEAD
	252	+lcluster, delta0 and delta1 are available instead of blkaddr to indicate the
	253	+distance to its HEAD lcluster and the next HEAD lcluster. A PLAIN lcluster is
	254	+also a HEAD lcluster except that its data is uncompressed. See the comments
	255	+around "struct z_erofs_vle_decompressed_index" in erofs_fs.h for more details.
	256	+
	257	+If big pcluster is enabled, pcluster size in lclusters needs to be recorded as
	258	+well. Let the delta0 of the first NONHEAD lcluster store the compressed block
	259	+count with a special flag as a new called CBLKCNT NONHEAD lcluster. It's easy
	260	+to understand its delta0 is constantly 1, as illustrated below::
	261	+
	262	+ __________________________________________________________
	263	+ \| HEAD \| NONHEAD \| NONHEAD \| ... \| NONHEAD \| HEAD \| HEAD \|
	264	+ \|__:___\|_(CBLKCNT)_\|_________\|_____\|_________\|__:___\|____:_\|
	265	+ \|<----- a big pcluster (with CBLKCNT) ------>\|<-- -->\|
	266	+ a lcluster-sized pcluster (without CBLKCNT) ^
	267	+
	268	+If another HEAD follows a HEAD lcluster, there is no room to record CBLKCNT,
	269	+but it's easy to know the size of such pcluster is 1 lcluster as well.

Documentation/hwmon/tmp103.rst+2−2

@@ -21,10 +21,10 @@ Description · 20 unmodified lines
21	21	The TMP103 is a digital output temperature sensor in a four-ball
22	22	wafer chip-scale package (WCSP). The TMP103 is capable of reading
23	23	temperatures to a resolution of 1°C. The TMP103 is specified for
24		−operation over a temperature range of –40°C to +125°C.
	24	+operation over a temperature range of -40°C to +125°C.
25	25
26	26	Resolution: 8 Bits
27		−Accuracy: ±1°C Typ (–10°C to +100°C)
	27	+Accuracy: ±1°C Typ (-10°C to +100°C)
28	28
29	29	The driver provides the common sysfs-interface for temperatures (see
30	30	Documentation/hwmon/sysfs-interface.rst under Temperatures).

Documentation/networking/device_drivers/ethernet/intel/i40e.rst+2−2

@@ -173,7 +173,7 @@ Director rule is added from ethtool (Sideband filter), ATR is turned off by the · 172 unmodified lines
173	173	driver. To re-enable ATR, the sideband can be disabled with the ethtool -K
174	174	option. For example::
175	175
176		− ethtool –K [adapter] ntuple [off\|on]
	176	+ ethtool -K [adapter] ntuple [off\|on]
177	177
178	178	If sideband is re-enabled after ATR is re-enabled, ATR remains enabled until a
179	179	TCP-IP flow is added. When all TCP-IP sideband rules are deleted, ATR is
@@ -688,7 +688,7 @@ shaper bw_rlimit: for each tc, sets minimum and maximum bandwidth rates. · 508 unmodified lines
688	688	Totals must be equal or less than port speed.
689	689
690	690	For example: min_rate 1Gbit 3Gbit: Verify bandwidth limit using network
691		−monitoring tools such as ifstat or sar –n DEV [interval] [number of samples]
	691	+monitoring tools such as `ifstat` or `sar -n DEV [interval] [number of samples]`
692	692
693	693	2. Enable HW TC offload on interface::
694	694

Documentation/networking/device_drivers/ethernet/intel/iavf.rst+1−1

@@ -179,7 +179,7 @@ shaper bw_rlimit: for each tc, sets minimum and maximum bandwidth rates. · 178 unmodified lines
179	179	Totals must be equal or less than port speed.
180	180
181	181	For example: min_rate 1Gbit 3Gbit: Verify bandwidth limit using network
182		−monitoring tools such as ifstat or sar –n DEV [interval] [number of samples]
	182	+monitoring tools such as ``ifstat`` or ``sar -n DEV [interval] [number of samples]``
183	183
184	184	NOTE:
185	185	Setting up channels via ethtool (ethtool -L) is not supported when the

Documentation/powerpc/syscall64-abi.rst+10−0

@@ -109,6 +109,16 @@ auxiliary vector. · 108 unmodified lines
109	109
110	110	scv 0 syscalls will always behave as PPC_FEATURE2_HTM_NOSC.
111	111
	112	+ptrace
	113	+------
	114	+When ptracing system calls (PTRACE_SYSCALL), the pt_regs.trap value contains
	115	+the system call type that can be used to distinguish between sc and scv 0
	116	+system calls, and the different register conventions can be accounted for.
	117	+
	118	+If the value of (pt_regs.trap & 0xfff0) is 0xc00 then the system call was
	119	+performed with the sc instruction, if it is 0x3000 then the system call was
	120	+performed with the scv 0 instruction.
	121	+
112	122	vsyscall
113	123	========
114	124

Documentation/process/kernel-enforcement-statement.rst+1−1

@@ -1,4 +1,4 @@
1		−.. _process_statement_kernel:
	1	+.. _process_statement_kernel:
2	2
3	3	Linux Kernel Enforcement Statement
4	4	----------------------------------

Documentation/riscv/vm-layout.rst+2−2

@@ -58,6 +58,6 @@ RISC-V Linux Kernel SV39 · 57 unmodified lines
58	58	\|
59	59	____________________________________________________________\|____________________________________________________________
60	60	\| \| \| \|
61		− ffffffff00000000 \| -4 GB \| ffffffff7fffffff \| 2 GB \| modules
62		− ffffffff80000000 \| -2 GB \| ffffffffffffffff \| 2 GB \| kernel, BPF
	61	+ ffffffff00000000 \| -4 GB \| ffffffff7fffffff \| 2 GB \| modules, BPF
	62	+ ffffffff80000000 \| -2 GB \| ffffffffffffffff \| 2 GB \| kernel
63	63	__________________\|____________\|__________________\|_________\|____________________________________________________________

Documentation/security/tpm/xen-tpmfront.rst+1−1

@@ -1,4 +1,4 @@
1		−=============================
	1	+=============================
2	2	Virtual TPM interface for Xen
3	3	=============================
4	4

Documentation/timers/no_hz.rst+1−1

@@ -1,4 +1,4 @@
1		−======================================
	1	+======================================
2	2	NO_HZ: Reducing Scheduling-Clock Ticks
3	3	======================================
4	4

Documentation/translations/zh_CN/SecurityBugs+0−50

@@ -1,50 +0,0 @@
1		−Chinese translated version of Documentation/admin-guide/security-bugs.rst
2		−
3		−If you have any comment or update to the content, please contact the
4		−original document maintainer directly. However, if you have a problem
5		−communicating in English you can also ask the Chinese maintainer for
6		−help. Contact the Chinese maintainer if this translation is outdated
7		−or if there is a problem with the translation.
8		−
9		−Chinese maintainer: Harry Wei <harryxiyou@gmail.com>
10		−---------------------------------------------------------------------
11		−Documentation/admin-guide/security-bugs.rst 的中文翻译
12		−
13		−如果想评论或更新本文的内容，请直接联系原文档的维护者。如果你使用英文
14		−交流有困难的话，也可以向中文版维护者求助。如果本翻译更新不及时或者翻
15		−译存在问题，请联系中文版维护者。
16		−
17		−中文版维护者：贾威威 Harry Wei <harryxiyou@gmail.com>
18		−中文版翻译者：贾威威 Harry Wei <harryxiyou@gmail.com>
19		−中文版校译者：贾威威 Harry Wei <harryxiyou@gmail.com>
20		−
21		−
22		−以下为正文
23		−---------------------------------------------------------------------
24		−Linux内核开发者认为安全非常重要。因此，我们想要知道当一个有关于
25		−安全的漏洞被发现的时候，并且它可能会被尽快的修复或者公开。请把这个安全
26		−漏洞报告给Linux内核安全团队。
27		−
28		−1) 联系
29		−
30		−linux内核安全团队可以通过email<security@kernel.org>来联系。这是
31		−一组独立的安全工作人员，可以帮助改善漏洞报告并且公布和取消一个修复。安
32		−全团队有可能会从部分的维护者那里引进额外的帮助来了解并且修复安全漏洞。
33		−当遇到任何漏洞，所能提供的信息越多就越能诊断和修复。如果你不清楚什么
34		−是有帮助的信息，那就请重温一下admin-guide/reporting-bugs.rst文件中的概述过程。任
35		−何攻击性的代码都是非常有用的，未经报告者的同意不会被取消，除非它已经
36		−被公布于众。
37		−
38		−2) 公开
39		−
40		−Linux内核安全团队的宗旨就是和漏洞提交者一起处理漏洞的解决方案直
41		−到公开。我们喜欢尽快地完全公开漏洞。当一个漏洞或者修复还没有被完全地理
42		−解，解决方案没有通过测试或者供应商协调，可以合理地延迟公开。然而，我们
43		−期望这些延迟尽可能的短些，是可数的几天，而不是几个星期或者几个月。公开
44		−日期是通过安全团队和漏洞提供者以及供应商洽谈后的结果。公开时间表是从很
45		−短（特殊的，它已经被公众所知道）到几个星期。作为一个基本的默认政策，我
46		−们所期望通知公众的日期是7天的安排。
47		−
48		−3) 保密协议
49		−
50		−Linux内核安全团队不是一个正式的团体，因此不能加入任何的保密协议。

Documentation/usb/gadget_configfs.rst+1−1

@@ -140,7 +140,7 @@ is an arbitrary string allowed in a filesystem, e.g.:: · 139 unmodified lines
140	140	Each function provides its specific set of attributes, with either read-only
141	141	or read-write access. Where applicable they need to be written to as
142	142	appropriate.
143		−Please refer to Documentation/ABI//configfs-usb-gadget for more information.
	143	+Please refer to Documentation/ABI/testing/configfs-usb-gadget for more information.
144	144
145	145	4. Associating the functions with their configurations
146	146	------------------------------------------------------

Documentation/usb/mtouchusb.rst+1−1

@@ -1,4 +1,4 @@
1		−================
	1	+================
2	2	mtouchusb driver
3	3	================
4	4

Documentation/usb/usb-serial.rst+1−1

@@ -1,4 +1,4 @@
1		−==========
	1	+==========
2	2	USB serial
3	3	==========
4	4

Documentation/userspace-api/seccomp_filter.rst+8−8

@@ -250,14 +250,14 @@ Users can read via ``ioctl(SECCOMP_IOCTL_NOTIF_RECV)`` (or ``poll()``) on a · 249 unmodified lines
250	250	seccomp notification fd to receive a ``struct seccomp_notif``, which contains
251	251	five members: the input length of the structure, a unique-per-filter ``id``,
252	252	the ``pid`` of the task which triggered this request (which may be 0 if the
253		−task is in a pid ns not visible from the listener's pid namespace), a ``flags``
254		−member which for now only has ``SECCOMP_NOTIF_FLAG_SIGNALED``, representing
255		−whether or not the notification is a result of a non-fatal signal, and the
256		−``data`` passed to seccomp. Userspace can then make a decision based on this
257		−information about what to do, and ``ioctl(SECCOMP_IOCTL_NOTIF_SEND)`` a
258		−response, indicating what should be returned to userspace. The ``id`` member of
259		−``struct seccomp_notif_resp`` should be the same ``id`` as in ``struct
260		−seccomp_notif``.
	253	+task is in a pid ns not visible from the listener's pid namespace). The
	254	+notification also contains the ``data`` passed to seccomp, and a filters flag.
	255	+The structure should be zeroed out prior to calling the ioctl.
	256	+
	257	+Userspace can then make a decision based on this information about what to do,
	258	+and ``ioctl(SECCOMP_IOCTL_NOTIF_SEND)`` a response, indicating what should be
	259	+returned to userspace. The ``id`` member of ``struct seccomp_notif_resp`` should
	260	+be the same ``id`` as in ``struct seccomp_notif``.
261	261
262	262	It is worth noting that ``struct seccomp_data`` contains the values of register
263	263	arguments to the syscall, but does not contain pointers to memory. The task's

Documentation/virt/kvm/amd-memory-encryption.rst+1−1

@@ -22,7 +22,7 @@ to SEV:: · 21 unmodified lines
22	22	[ecx]:
23	23	Bits[31:0] Number of encrypted guests supported simultaneously
24	24
25		−If support for SEV is present, MSR 0xc001_0010 (MSR_K8_SYSCFG) and MSR 0xc001_0015
	25	+If support for SEV is present, MSR 0xc001_0010 (MSR_AMD64_SYSCFG) and MSR 0xc001_0015
26	26	(MSR_K7_HWCR) can be used to determine if it can be enabled::
27	27
28	28	0xc001_0010:

Documentation/virt/kvm/api.rst+2−2

@@ -4803,7 +4803,7 @@ KVM_PV_VM_VERIFY · 4802 unmodified lines
4803	4803	4.126 KVM_X86_SET_MSR_FILTER
4804	4804	----------------------------
4805	4805
4806		−:Capability: KVM_X86_SET_MSR_FILTER
	4806	+:Capability: KVM_CAP_X86_MSR_FILTER
4807	4807	:Architectures: x86
4808	4808	:Type: vm ioctl
4809	4809	:Parameters: struct kvm_msr_filter
@@ -6715,7 +6715,7 @@ accesses that would usually trigger a #GP by KVM into the guest will · 1905 unmodified lines
6715	6715	instead get bounced to user space through the KVM_EXIT_X86_RDMSR and
6716	6716	KVM_EXIT_X86_WRMSR exit notifications.
6717	6717
6718		−8.27 KVM_X86_SET_MSR_FILTER
	6718	+8.27 KVM_CAP_X86_MSR_FILTER
6719	6719	---------------------------
6720	6720
6721	6721	:Architectures: x86

Documentation/virt/kvm/mmu.rst+2−2

@@ -171,8 +171,8 @@ Shadow pages contain the following information: · 170 unmodified lines
171	171	shadow pages) so role.quadrant takes values in the range 0..3. Each
172	172	quadrant maps 1GB virtual address space.
173	173	role.access:
174		− Inherited guest access permissions in the form uwx. Note execute
175		− permission is positive, not negative.
	174	+ Inherited guest access permissions from the parent ptes in the form uwx.
	175	+ Note execute permission is positive, not negative.
176	176	role.invalid:
177	177	The page is invalid and should not be used. It is a root page that is
178	178	currently pinned (by a cpu hardware register pointing to it); once it is

Documentation/virt/kvm/vcpu-requests.rst+5−3

@@ -118,10 +118,12 @@ KVM_REQ_MMU_RELOAD · 117 unmodified lines
118	118	necessary to inform each VCPU to completely refresh the tables. This
119	119	request is used for that.
120	120
121		−KVM_REQ_PENDING_TIMER
	121	+KVM_REQ_UNBLOCK
122	122
123		− This request may be made from a timer handler run on the host on behalf
124		− of a VCPU. It informs the VCPU thread to inject a timer interrupt.
	123	+ This request informs the vCPU to exit kvm_vcpu_block. It is used for
	124	+ example from timer handlers that run on the host on behalf of a vCPU,
	125	+ or in order to update the interrupt routing and ensure that assigned
	126	+ devices will wake up the vCPU.
125	127
126	128	KVM_REQ_UNHALT
127	129

Documentation/vm/slub.rst+5−5

@@ -181,7 +181,7 @@ SLUB Debug output · 180 unmodified lines
181	181	Here is a sample of slub debug output::
182	182
183	183	====================================================================
184		− BUG kmalloc-8: Redzone overwritten
	184	+ BUG kmalloc-8: Right Redzone overwritten
185	185	--------------------------------------------------------------------
186	186
187	187	INFO: 0xc90f6d28-0xc90f6d2b. First byte 0x00 instead of 0xcc
@@ -189,10 +189,10 @@ Here is a sample of slub debug output:: · 1 unmodified line
189	189	INFO: Object 0xc90f6d20 @offset=3360 fp=0xc90f6d58
190	190	INFO: Allocated in get_modalias+0x61/0xf5 age=53 cpu=1 pid=554
191	191
192		− Bytes b4 0xc90f6d10: 00 00 00 00 00 00 00 00 5a 5a 5a 5a 5a 5a 5a 5a ........ZZZZZZZZ
193		− Object 0xc90f6d20: 31 30 31 39 2e 30 30 35 1019.005
194		− Redzone 0xc90f6d28: 00 cc cc cc .
195		− Padding 0xc90f6d50: 5a 5a 5a 5a 5a 5a 5a 5a ZZZZZZZZ
	192	+ Bytes b4 (0xc90f6d10): 00 00 00 00 00 00 00 00 5a 5a 5a 5a 5a 5a 5a 5a ........ZZZZZZZZ
	193	+ Object (0xc90f6d20): 31 30 31 39 2e 30 30 35 1019.005
	194	+ Redzone (0xc90f6d28): 00 cc cc cc .
	195	+ Padding (0xc90f6d50): 5a 5a 5a 5a 5a 5a 5a 5a ZZZZZZZZ
196	196
197	197	[<c010523d>] dump_trace+0x63/0x1eb
198	198	[<c01053df>] show_trace_log_lvl+0x1a/0x2f

Documentation/x86/amd-memory-encryption.rst+3−3

@@ -53,7 +53,7 @@ CPUID function 0x8000001f reports information related to SME:: · 52 unmodified lines
53	53	system physical addresses, not guest physical
54	54	addresses)
55	55
56		−If support for SME is present, MSR 0xc00100010 (MSR_K8_SYSCFG) can be used to
	56	+If support for SME is present, MSR 0xc00100010 (MSR_AMD64_SYSCFG) can be used to
57	57	determine if SME is enabled and/or to enable memory encryption::
58	58
59	59	0xc0010010:
@@ -79,7 +79,7 @@ The state of SME in the Linux kernel can be documented as follows: · 19 unmodified lines
79	79	The CPU supports SME (determined through CPUID instruction).
80	80
81	81	- Enabled:
82		− Supported and bit 23 of MSR_K8_SYSCFG is set.
	82	+ Supported and bit 23 of MSR_AMD64_SYSCFG is set.
83	83
84	84	- Active:
85	85	Supported, Enabled and the Linux kernel is actively applying
@@ -89,7 +89,7 @@ The state of SME in the Linux kernel can be documented as follows: · 3 unmodified lines
89	89	SME can also be enabled and activated in the BIOS. If SME is enabled and
90	90	activated in the BIOS, then all memory accesses will be encrypted and it will
91	91	not be necessary to activate the Linux memory encryption support. If the BIOS
92		−merely enables SME (sets bit 23 of the MSR_K8_SYSCFG), then Linux can activate
	92	+merely enables SME (sets bit 23 of the MSR_AMD64_SYSCFG), then Linux can activate
93	93	memory encryption by default (CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT=y) or
94	94	by supplying mem_encrypt=on on the kernel command line. However, if BIOS does
95	95	not enable SME, then Linux will not be able to activate memory encryption, even

MAINTAINERS+58−30

@@ -1578,7 +1578,7 @@ F: drivers/clk/sunxi/ · 1577 unmodified lines
1578	1578	ARM/Allwinner sunXi SoC support
1579	1579	M: Maxime Ripard <mripard@kernel.org>
1580	1580	M: Chen-Yu Tsai <wens@csie.org>
1581		−R: Jernej Skrabec <jernej.skrabec@siol.net>
	1581	+R: Jernej Skrabec <jernej.skrabec@gmail.com>
1582	1582	L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
1583	1583	S: Maintained
1584	1584	T: git git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux.git
@@ -1618,8 +1618,8 @@ F: Documentation/devicetree/bindings/sound/amlogic* · 33 unmodified lines
1618	1618	F: sound/soc/meson/
1619	1619
1620	1620	ARM/Amlogic Meson SoC support
	1621	+M: Neil Armstrong <narmstrong@baylibre.com>
1621	1622	M: Kevin Hilman <khilman@baylibre.com>
1622		−R: Neil Armstrong <narmstrong@baylibre.com>
1623	1623	R: Jerome Brunet <jbrunet@baylibre.com>
1624	1624	R: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
1625	1625	L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@@ -3875,6 +3875,7 @@ L: linux-btrfs@vger.kernel.org · 2249 unmodified lines
3875	3875	S: Maintained
3876	3876	W: http://btrfs.wiki.kernel.org/
3877	3877	Q: http://patchwork.kernel.org/project/linux-btrfs/list/
	3878	+C: irc://irc.libera.chat/btrfs
3878	3879	T: git git://git.kernel.org/pub/scm/linux/kernel/git/kdave/linux.git
3879	3880	F: Documentation/filesystems/btrfs.rst
3880	3881	F: fs/btrfs/
@@ -4136,6 +4137,14 @@ S: Odd Fixes · 255 unmodified lines
4136	4137	F: Documentation/devicetree/bindings/arm/cavium-thunder2.txt
4137	4138	F: arch/arm64/boot/dts/cavium/thunder2-99xx*
4138	4139
	4140	+CBS/ETF/TAPRIO QDISCS
	4141	+M: Vinicius Costa Gomes <vinicius.gomes@intel.com>
	4142	+S: Maintained
	4143	+L: netdev@vger.kernel.org
	4144	+F: net/sched/sch_cbs.c
	4145	+F: net/sched/sch_etf.c
	4146	+F: net/sched/sch_taprio.c
	4147	+
4139	4148	CC2520 IEEE-802.15.4 RADIO DRIVER
4140	4149	M: Varka Bhadram <varkabhadram@gmail.com>
4141	4150	L: linux-wpan@vger.kernel.org
@@ -5087,7 +5096,7 @@ S: Maintained · 945 unmodified lines
5087	5096	F: drivers/net/fddi/defza.*
5088	5097
5089	5098	DEINTERLACE DRIVERS FOR ALLWINNER H3
5090		−M: Jernej Skrabec <jernej.skrabec@siol.net>
	5099	+M: Jernej Skrabec <jernej.skrabec@gmail.com>
5091	5100	L: linux-media@vger.kernel.org
5092	5101	S: Maintained
5093	5102	T: git git://linuxtv.org/media_tree.git
@@ -5235,7 +5244,7 @@ DEVICE DIRECT ACCESS (DAX) · 141 unmodified lines
5235	5244	M: Dan Williams <dan.j.williams@intel.com>
5236	5245	M: Vishal Verma <vishal.l.verma@intel.com>
5237	5246	M: Dave Jiang <dave.jiang@intel.com>
5238		−L: linux-nvdimm@lists.01.org
	5247	+L: nvdimm@lists.linux.dev
5239	5248	S: Supported
5240	5249	F: drivers/dax/
5241	5250
@@ -5567,7 +5576,6 @@ F: drivers/soc/fsl/dpio · 325 unmodified lines
5567	5576
5568	5577	DPAA2 ETHERNET DRIVER
5569	5578	M: Ioana Ciornei <ioana.ciornei@nxp.com>
5570		−M: Ioana Radulescu <ruxandra.radulescu@nxp.com>
5571	5579	L: netdev@vger.kernel.org
5572	5580	S: Maintained
5573	5581	F: Documentation/networking/device_drivers/ethernet/freescale/dpaa2/ethernet-driver.rst
@@ -5630,14 +5638,14 @@ F: include/linux/power/smartreflex.h · 56 unmodified lines
5630	5638	DRM DRIVER FOR ALLWINNER DE2 AND DE3 ENGINE
5631	5639	M: Maxime Ripard <mripard@kernel.org>
5632	5640	M: Chen-Yu Tsai <wens@csie.org>
5633		−R: Jernej Skrabec <jernej.skrabec@siol.net>
	5641	+R: Jernej Skrabec <jernej.skrabec@gmail.com>
5634	5642	L: dri-devel@lists.freedesktop.org
5635	5643	S: Supported
5636	5644	T: git git://anongit.freedesktop.org/drm/drm-misc
5637	5645	F: drivers/gpu/drm/sun4i/sun8i*
5638	5646
5639	5647	DRM DRIVER FOR ARM PL111 CLCD
5640		−M: Eric Anholt <eric@anholt.net>
	5648	+M: Emma Anholt <emma@anholt.net>
5641	5649	S: Supported
5642	5650	T: git git://anongit.freedesktop.org/drm/drm-misc
5643	5651	F: drivers/gpu/drm/pl111/
@@ -5717,7 +5725,7 @@ T: git git://anongit.freedesktop.org/drm/drm-misc · 73 unmodified lines
5717	5725	F: drivers/gpu/drm/tiny/gm12u320.c
5718	5726
5719	5727	DRM DRIVER FOR HX8357D PANELS
5720		−M: Eric Anholt <eric@anholt.net>
	5728	+M: Emma Anholt <emma@anholt.net>
5721	5729	S: Maintained
5722	5730	T: git git://anongit.freedesktop.org/drm/drm-misc
5723	5731	F: Documentation/devicetree/bindings/display/himax,hx8357d.txt
@@ -6021,7 +6029,7 @@ M: Neil Armstrong <narmstrong@baylibre.com> · 297 unmodified lines
6021	6029	M: Robert Foss <robert.foss@linaro.org>
6022	6030	R: Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
6023	6031	R: Jonas Karlman <jonas@kwiboo.se>
6024		−R: Jernej Skrabec <jernej.skrabec@siol.net>
	6032	+R: Jernej Skrabec <jernej.skrabec@gmail.com>
6025	6033	S: Maintained
6026	6034	T: git git://anongit.freedesktop.org/drm/drm-misc
6027	6035	F: drivers/gpu/drm/bridge/
@@ -6175,7 +6183,7 @@ F: Documentation/devicetree/bindings/display/ti/ · 147 unmodified lines
6175	6183	F: drivers/gpu/drm/omapdrm/
6176	6184
6177	6185	DRM DRIVERS FOR V3D
6178		−M: Eric Anholt <eric@anholt.net>
	6186	+M: Emma Anholt <emma@anholt.net>
6179	6187	S: Supported
6180	6188	T: git git://anongit.freedesktop.org/drm/drm-misc
6181	6189	F: Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml
@@ -6183,7 +6191,7 @@ F: drivers/gpu/drm/v3d/ · 1 unmodified line
6183	6191	F: include/uapi/drm/v3d_drm.h
6184	6192
6185	6193	DRM DRIVERS FOR VC4
6186		−M: Eric Anholt <eric@anholt.net>
	6194	+M: Emma Anholt <emma@anholt.net>
6187	6195	M: Maxime Ripard <mripard@kernel.org>
6188	6196	S: Supported
6189	6197	T: git git://github.com/anholt/linux
@@ -6936,6 +6944,7 @@ F: net/core/failover.c · 746 unmodified lines
6936	6944	FANOTIFY
6937	6945	M: Jan Kara <jack@suse.cz>
6938	6946	R: Amir Goldstein <amir73il@gmail.com>
	6947	+R: Matthew Bobrowski <repnop@google.com>
6939	6948	L: linux-fsdevel@vger.kernel.org
6940	6949	S: Maintained
6941	6950	F: fs/notify/fanotify/
@@ -7004,7 +7013,7 @@ M: Dan Williams <dan.j.williams@intel.com> · 62 unmodified lines
7004	7013	R: Matthew Wilcox <willy@infradead.org>
7005	7014	R: Jan Kara <jack@suse.cz>
7006	7015	L: linux-fsdevel@vger.kernel.org
7007		−L: linux-nvdimm@lists.01.org
	7016	+L: nvdimm@lists.linux.dev
7008	7017	S: Supported
7009	7018	F: fs/dax.c
7010	7019	F: include/linux/dax.h
@@ -10377,7 +10386,7 @@ LIBNVDIMM BLK: MMIO-APERTURE DRIVER · 3366 unmodified lines
10377	10386	M: Dan Williams <dan.j.williams@intel.com>
10378	10387	M: Vishal Verma <vishal.l.verma@intel.com>
10379	10388	M: Dave Jiang <dave.jiang@intel.com>
10380		−L: linux-nvdimm@lists.01.org
	10389	+L: nvdimm@lists.linux.dev
10381	10390	S: Supported
10382	10391	Q: https://patchwork.kernel.org/project/linux-nvdimm/list/
10383	10392	P: Documentation/nvdimm/maintainer-entry-profile.rst
@@ -10388,7 +10397,7 @@ LIBNVDIMM BTT: BLOCK TRANSLATION TABLE · 4 unmodified lines
10388	10397	M: Vishal Verma <vishal.l.verma@intel.com>
10389	10398	M: Dan Williams <dan.j.williams@intel.com>
10390	10399	M: Dave Jiang <dave.jiang@intel.com>
10391		−L: linux-nvdimm@lists.01.org
	10400	+L: nvdimm@lists.linux.dev
10392	10401	S: Supported
10393	10402	Q: https://patchwork.kernel.org/project/linux-nvdimm/list/
10394	10403	P: Documentation/nvdimm/maintainer-entry-profile.rst
@@ -10398,7 +10407,7 @@ LIBNVDIMM PMEM: PERSISTENT MEMORY DRIVER · 3 unmodified lines
10398	10407	M: Dan Williams <dan.j.williams@intel.com>
10399	10408	M: Vishal Verma <vishal.l.verma@intel.com>
10400	10409	M: Dave Jiang <dave.jiang@intel.com>
10401		−L: linux-nvdimm@lists.01.org
	10410	+L: nvdimm@lists.linux.dev
10402	10411	S: Supported
10403	10412	Q: https://patchwork.kernel.org/project/linux-nvdimm/list/
10404	10413	P: Documentation/nvdimm/maintainer-entry-profile.rst
@@ -10406,7 +10415,7 @@ F: drivers/nvdimm/pmem* · 1 unmodified line
10406	10415
10407	10416	LIBNVDIMM: DEVICETREE BINDINGS
10408	10417	M: Oliver O'Halloran <oohall@gmail.com>
10409		−L: linux-nvdimm@lists.01.org
	10418	+L: nvdimm@lists.linux.dev
10410	10419	S: Supported
10411	10420	Q: https://patchwork.kernel.org/project/linux-nvdimm/list/
10412	10421	F: Documentation/devicetree/bindings/pmem/pmem-region.txt
@@ -10417,7 +10426,7 @@ M: Dan Williams <dan.j.williams@intel.com> · 4 unmodified lines
10417	10426	M: Vishal Verma <vishal.l.verma@intel.com>
10418	10427	M: Dave Jiang <dave.jiang@intel.com>
10419	10428	M: Ira Weiny <ira.weiny@intel.com>
10420		−L: linux-nvdimm@lists.01.org
	10429	+L: nvdimm@lists.linux.dev
10421	10430	S: Supported
10422	10431	Q: https://patchwork.kernel.org/project/linux-nvdimm/list/
10423	10432	P: Documentation/nvdimm/maintainer-entry-profile.rst
@@ -12179,6 +12188,7 @@ F: drivers/platform/surface/surfacepro3_button.c · 1755 unmodified lines
12179	12188
12180	12189	MICROSOFT SURFACE SYSTEM AGGREGATOR SUBSYSTEM
12181	12190	M: Maximilian Luz <luzmaximilian@gmail.com>
	12191	+L: platform-driver-x86@vger.kernel.org
12182	12192	S: Maintained
12183	12193	W: https://github.com/linux-surface/surface-aggregator-module
12184	12194	C: irc://chat.freenode.net/##linux-surface
@@ -12679,9 +12689,9 @@ F: drivers/rtc/rtc-ntxec.c · 494 unmodified lines
12679	12689	F: include/linux/mfd/ntxec.h
12680	12690
12681	12691	NETRONOME ETHERNET DRIVERS
12682		−M: Simon Horman <simon.horman@netronome.com>
	12692	+M: Simon Horman <simon.horman@corigine.com>
12683	12693	R: Jakub Kicinski <kuba@kernel.org>
12684		−L: oss-drivers@netronome.com
	12694	+L: oss-drivers@corigine.com
12685	12695	S: Maintained
12686	12696	F: drivers/net/ethernet/netronome/
12687	12697
@@ -12708,7 +12718,6 @@ M: "David S. Miller" <davem@davemloft.net> · 20 unmodified lines
12708	12718	M: Jakub Kicinski <kuba@kernel.org>
12709	12719	L: netdev@vger.kernel.org
12710	12720	S: Maintained
12711		−W: http://www.linuxfoundation.org/en/Net
12712	12721	Q: https://patchwork.kernel.org/project/netdevbpf/list/
12713	12722	T: git git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net.git
12714	12723	T: git git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git
@@ -12753,7 +12762,6 @@ M: "David S. Miller" <davem@davemloft.net> · 38 unmodified lines
12753	12762	M: Jakub Kicinski <kuba@kernel.org>
12754	12763	L: netdev@vger.kernel.org
12755	12764	S: Maintained
12756		−W: http://www.linuxfoundation.org/en/Net
12757	12765	Q: https://patchwork.kernel.org/project/netdevbpf/list/
12758	12766	B: mailto:netdev@vger.kernel.org
12759	12767	T: git git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net.git
@@ -12895,8 +12903,10 @@ F: include/uapi/linux/nexthop.h · 135 unmodified lines
12895	12903	F: net/ipv4/nexthop.c
12896	12904
12897	12905	NFC SUBSYSTEM
	12906	+M: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
	12907	+L: linux-nfc@lists.01.org (subscribers-only)
12898	12908	L: netdev@vger.kernel.org
12899		−S: Orphan
	12909	+S: Maintained
12900	12910	F: Documentation/devicetree/bindings/net/nfc/
12901	12911	F: drivers/nfc/
12902	12912	F: include/linux/platform_data/nfcmrvl.h
@@ -12907,7 +12917,7 @@ F: net/nfc/ · 4 unmodified lines
12907	12917	NFC VIRTUAL NCI DEVICE DRIVER
12908	12918	M: Bongsu Jeon <bongsu.jeon@samsung.com>
12909	12919	L: netdev@vger.kernel.org
12910		−L: linux-nfc@lists.01.org (moderated for non-subscribers)
	12920	+L: linux-nfc@lists.01.org (subscribers-only)
12911	12921	S: Supported
12912	12922	F: drivers/nfc/virtual_ncidev.c
12913	12923	F: tools/testing/selftests/nci/
@@ -13204,9 +13214,8 @@ F: Documentation/devicetree/bindings/sound/tfa9879.txt · 290 unmodified lines
13204	13214	F: sound/soc/codecs/tfa9879*
13205	13215
13206	13216	NXP-NCI NFC DRIVER
13207		−M: Clément Perrochaud <clement.perrochaud@effinnov.com>
13208	13217	R: Charles Gorand <charles.gorand@effinnov.com>
13209		−L: linux-nfc@lists.01.org (moderated for non-subscribers)
	13218	+L: linux-nfc@lists.01.org (subscribers-only)
13210	13219	S: Supported
13211	13220	F: drivers/nfc/nxp-nci
13212	13221
@@ -14109,6 +14118,7 @@ F: drivers/pci/controller/pci-v3-semi.c · 896 unmodified lines
14109	14118	PCI ENDPOINT SUBSYSTEM
14110	14119	M: Kishon Vijay Abraham I <kishon@ti.com>
14111	14120	M: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
	14121	+R: Krzysztof Wilczyński <kw@linux.com>
14112	14122	L: linux-pci@vger.kernel.org
14113	14123	S: Supported
14114	14124	F: Documentation/PCI/endpoint/*
@@ -14157,6 +14167,7 @@ F: drivers/pci/controller/pci-xgene-msi.c · 42 unmodified lines
14157	14167	PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS
14158	14168	M: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
14159	14169	R: Rob Herring <robh@kernel.org>
	14170	+R: Krzysztof Wilczyński <kw@linux.com>
14160	14171	L: linux-pci@vger.kernel.org
14161	14172	S: Supported
14162	14173	Q: http://patchwork.ozlabs.org/project/linux-pci/list/
@@ -14316,10 +14327,12 @@ PER-CPU MEMORY ALLOCATOR · 153 unmodified lines
14316	14327	M: Dennis Zhou <dennis@kernel.org>
14317	14328	M: Tejun Heo <tj@kernel.org>
14318	14329	M: Christoph Lameter <cl@linux.com>
	14330	+L: linux-mm@kvack.org
14319	14331	S: Maintained
14320	14332	T: git git://git.kernel.org/pub/scm/linux/kernel/git/dennis/percpu.git
14321	14333	F: arch/*/include/asm/percpu.h
14322	14334	F: include/linux/percpu*.h
	14335	+F: lib/percpu*.c
14323	14336	F: mm/percpu*.c
14324	14337
14325	14338	PER-TASK DELAY ACCOUNTING
@@ -14733,7 +14746,6 @@ W: https://wireless.wiki.kernel.org/en/users/Drivers/p54 · 407 unmodified lines
14733	14746	F: drivers/net/wireless/intersil/prism54/
14734	14747
14735	14748	PROC FILESYSTEM
14736		−R: Alexey Dobriyan <adobriyan@gmail.com>
14737	14749	L: linux-kernel@vger.kernel.org
14738	14750	L: linux-fsdevel@vger.kernel.org
14739	14751	S: Maintained
@@ -15814,7 +15826,7 @@ F: include/uapi/linux/rose.h · 1074 unmodified lines
15814	15826	F: net/rose/
15815	15827
15816	15828	ROTATION DRIVER FOR ALLWINNER A83T
15817		−M: Jernej Skrabec <jernej.skrabec@siol.net>
	15829	+M: Jernej Skrabec <jernej.skrabec@gmail.com>
15818	15830	L: linux-media@vger.kernel.org
15819	15831	S: Maintained
15820	15832	T: git git://linuxtv.org/media_tree.git
@@ -15944,6 +15956,7 @@ S390 IUCV NETWORK LAYER · 123 unmodified lines
15944	15956	M: Julian Wiedmann <jwi@linux.ibm.com>
15945	15957	M: Karsten Graul <kgraul@linux.ibm.com>
15946	15958	L: linux-s390@vger.kernel.org
	15959	+L: netdev@vger.kernel.org
15947	15960	S: Supported
15948	15961	W: http://www.ibm.com/developerworks/linux/linux390/
15949	15962	F: drivers/s390/net/iucv
@@ -15954,6 +15967,7 @@ S390 NETWORK DRIVERS · 4 unmodified lines
15954	15967	M: Julian Wiedmann <jwi@linux.ibm.com>
15955	15968	M: Karsten Graul <kgraul@linux.ibm.com>
15956	15969	L: linux-s390@vger.kernel.org
	15970	+L: netdev@vger.kernel.org
15957	15971	S: Supported
15958	15972	W: http://www.ibm.com/developerworks/linux/linux390/
15959	15973	F: drivers/s390/net/
@@ -16132,7 +16146,7 @@ F: include/media/drv-intf/s3c_camif.h · 172 unmodified lines
16132	16146	SAMSUNG S3FWRN5 NFC DRIVER
16133	16147	M: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
16134	16148	M: Krzysztof Opasiak <k.opasiak@samsung.com>
16135		−L: linux-nfc@lists.01.org (moderated for non-subscribers)
	16149	+L: linux-nfc@lists.01.org (subscribers-only)
16136	16150	S: Maintained
16137	16151	F: Documentation/devicetree/bindings/net/nfc/samsung,s3fwrn5.yaml
16138	16152	F: drivers/nfc/s3fwrn5
@@ -16545,6 +16559,7 @@ F: drivers/misc/sgi-xp/ · 406 unmodified lines
16545	16559
16546	16560	SHARED MEMORY COMMUNICATIONS (SMC) SOCKETS
16547	16561	M: Karsten Graul <kgraul@linux.ibm.com>
	16562	+M: Guvenc Gulce <guvenc@linux.ibm.com>
16548	16563	L: linux-s390@vger.kernel.org
16549	16564	S: Supported
16550	16565	W: http://www.ibm.com/developerworks/linux/linux390/
@@ -17303,6 +17318,12 @@ L: linux-i2c@vger.kernel.org · 752 unmodified lines
17303	17318	S: Maintained
17304	17319	F: drivers/i2c/busses/i2c-stm32*
17305	17320
	17321	+ST STM32 SPI DRIVER
	17322	+M: Alain Volmat <alain.volmat@foss.st.com>
	17323	+L: linux-spi@vger.kernel.org
	17324	+S: Maintained
	17325	+F: drivers/spi/spi-stm32.c
	17326	+
17306	17327	ST STPDDC60 DRIVER
17307	17328	M: Daniel Nilsson <daniel.nilsson@flex.com>
17308	17329	L: linux-hwmon@vger.kernel.org
@@ -17661,7 +17682,6 @@ R: Mika Westerberg <mika.westerberg@linux.intel.com> · 352 unmodified lines
17661	17682	L: linux-i2c@vger.kernel.org
17662	17683	S: Maintained
17663	17684	F: drivers/i2c/busses/i2c-designware-*
17664		−F: include/linux/platform_data/i2c-designware.h
17665	17685
17666	17686	SYNOPSYS DESIGNWARE MMC/SD/SDIO DRIVER
17667	17687	M: Jaehoon Chung <jh80.chung@samsung.com>
@@ -18317,7 +18337,7 @@ F: sound/soc/codecs/tas571x* · 649 unmodified lines
18317	18337	TI TRF7970A NFC DRIVER
18318	18338	M: Mark Greer <mgreer@animalcreek.com>
18319	18339	L: linux-wireless@vger.kernel.org
18320		−L: linux-nfc@lists.01.org (moderated for non-subscribers)
	18340	+L: linux-nfc@lists.01.org (subscribers-only)
18321	18341	S: Supported
18322	18342	F: Documentation/devicetree/bindings/net/nfc/trf7970a.txt
18323	18343	F: drivers/nfc/trf7970a.c
@@ -18853,6 +18873,13 @@ S: Maintained · 529 unmodified lines
18853	18873	F: drivers/usb/host/isp116x*
18854	18874	F: include/linux/usb/isp116x.h
18855	18875
	18876	+USB ISP1760 DRIVER
	18877	+M: Rui Miguel Silva <rui.silva@linaro.org>
	18878	+L: linux-usb@vger.kernel.org
	18879	+S: Maintained
	18880	+F: drivers/usb/isp1760/*
	18881	+F: Documentation/devicetree/bindings/usb/nxp,isp1760.yaml
	18882	+
18856	18883	USB LAN78XX ETHERNET DRIVER
18857	18884	M: Woojung Huh <woojung.huh@microchip.com>
18858	18885	M: UNGLinuxDriver@microchip.com
@@ -19997,6 +20024,7 @@ F: arch/x86/xen/swiotlb · 1138 unmodified lines
19997	20024	F: drivers/xen/swiotlb
19998	20025
19999	20026	XFS FILESYSTEM
	20027	+C: irc://irc.oftc.net/xfs
20000	20028	M: Darrick J. Wong <djwong@kernel.org>
20001	20029	M: linux-xfs@vger.kernel.org
20002	20030	L: linux-xfs@vger.kernel.org

Makefile+10−2

@@ -2,8 +2,8 @@ · 1 unmodified line
2	2	VERSION = 5
3	3	PATCHLEVEL = 13
4	4	SUBLEVEL = 0
5		−EXTRAVERSION = -rc1
6		−NAME = Frozen Wasteland
	5	+EXTRAVERSION = -rc7
	6	+NAME = Opossums on Parade
7	7
8	8	# DOCUMENTATION
9	9	# To see a list of typical targets execute "make help"
@@ -928,6 +928,14 @@ CC_FLAGS_LTO += -fvisibility=hidden · 918 unmodified lines
928	928
929	929	# Limit inlining across translation units to reduce binary size
930	930	KBUILD_LDFLAGS += -mllvm -import-instr-limit=5
	931	+
	932	+# Check for frame size exceeding threshold during prolog/epilog insertion
	933	+# when using lld < 13.0.0.
	934	+ifneq ($(CONFIG_FRAME_WARN),0)
	935	+ifeq ($(shell test $(CONFIG_LLD_VERSION) -lt 130000; echo $$?),0)
	936	+KBUILD_LDFLAGS += -plugin-opt=-warn-stack-size=$(CONFIG_FRAME_WARN)
	937	+endif
	938	+endif
931	939	endif
932	940
933	941	ifdef CONFIG_LTO

arch/alpha/kernel/syscalls/syscall.tbl+1−1

@@ -482,7 +482,7 @@ · 481 unmodified lines
482	482	550 common process_madvise sys_process_madvise
483	483	551 common epoll_pwait2 sys_epoll_pwait2
484	484	552 common mount_setattr sys_mount_setattr
485		−553 common quotactl_path sys_quotactl_path
	485	+# 553 reserved for quotactl_path
486	486	554 common landlock_create_ruleset sys_landlock_create_ruleset
487	487	555 common landlock_add_rule sys_landlock_add_rule
488	488	556 common landlock_restrict_self sys_landlock_restrict_self

arch/arc/Makefile+1−1

@@ -31,7 +31,7 @@ endif · 30 unmodified lines
31	31
32	32
33	33	ifdef CONFIG_ARC_CURR_IN_REG
34		−# For a global register defintion, make sure it gets passed to every file
	34	+# For a global register definition, make sure it gets passed to every file
35	35	# We had a customer reported bug where some code built in kernel was NOT using
36	36	# any kernel headers, and missing the r25 global register
37	37	# Can't do unconditionally because of recursive include issues

arch/arc/include/asm/cmpxchg.h+2−2

@@ -116,7 +116,7 @@ static inline unsigned long __xchg(unsigned long val, volatile void *ptr, · 115 unmodified lines
116	116	*
117	117	* Technically the lock is also needed for UP (boils down to irq save/restore)
118	118	* but we can cheat a bit since cmpxchg() atomic_ops_lock() would cause irqs to
119		− * be disabled thus can't possibly be interrpted/preempted/clobbered by xchg()
	119	+ * be disabled thus can't possibly be interrupted/preempted/clobbered by xchg()
120	120	* Other way around, xchg is one instruction anyways, so can't be interrupted
121	121	* as such
122	122	*/
@@ -143,7 +143,7 @@ static inline unsigned long __xchg(unsigned long val, volatile void *ptr, · 20 unmodified lines
143	143	/*
144	144	* "atomic" variant of xchg()
145	145	* REQ: It needs to follow the same serialization rules as other atomic_xxx()
146		− * Since xchg() doesn't always do that, it would seem that following defintion
	146	+ * Since xchg() doesn't always do that, it would seem that following definition
147	147	* is incorrect. But here's the rationale:
148	148	* SMP : Even xchg() takes the atomic_ops_lock, so OK.
149	149	* LLSC: atomic_ops_lock are not relevant at all (even if SMP, since LLSC

arch/arc/include/asm/page.h+12−0

@@ -7,6 +7,18 @@ · 6 unmodified lines
7	7
8	8	#include <uapi/asm/page.h>
9	9
	10	+#ifdef CONFIG_ARC_HAS_PAE40
	11	+
	12	+#define MAX_POSSIBLE_PHYSMEM_BITS 40
	13	+#define PAGE_MASK_PHYS (0xff00000000ull \| PAGE_MASK)
	14	+
	15	+#else /* CONFIG_ARC_HAS_PAE40 */
	16	+
	17	+#define MAX_POSSIBLE_PHYSMEM_BITS 32
	18	+#define PAGE_MASK_PHYS PAGE_MASK
	19	+
	20	+#endif /* CONFIG_ARC_HAS_PAE40 */
	21	+
10	22	#ifndef __ASSEMBLY__
11	23
12	24	#define clear_page(paddr) memset((paddr), 0, PAGE_SIZE)

arch/arc/include/asm/pgtable.h+3−9

@@ -107,8 +107,8 @@ · 106 unmodified lines
107	107	#define ___DEF (_PAGE_PRESENT \| _PAGE_CACHEABLE)
108	108
109	109	/* Set of bits not changed in pte_modify */
110		−#define _PAGE_CHG_MASK (PAGE_MASK \| _PAGE_ACCESSED \| _PAGE_DIRTY \| _PAGE_SPECIAL)
111		−
	110	+#define _PAGE_CHG_MASK (PAGE_MASK_PHYS \| _PAGE_ACCESSED \| _PAGE_DIRTY \| \
	111	+ _PAGE_SPECIAL)
112	112	/* More Abbrevaited helpers */
113	113	#define PAGE_U_NONE __pgprot(___DEF)
114	114	#define PAGE_U_R __pgprot(___DEF \| _PAGE_READ)
@@ -132,13 +132,7 @@ · 17 unmodified lines
132	132	#define PTE_BITS_IN_PD0 (_PAGE_GLOBAL \| _PAGE_PRESENT \| _PAGE_HW_SZ)
133	133	#define PTE_BITS_RWX (_PAGE_EXECUTE \| _PAGE_WRITE \| _PAGE_READ)
134	134
135		−#ifdef CONFIG_ARC_HAS_PAE40
136		−#define PTE_BITS_NON_RWX_IN_PD1 (0xff00000000 \| PAGE_MASK \| _PAGE_CACHEABLE)
137		−#define MAX_POSSIBLE_PHYSMEM_BITS 40
138		−#else
139		−#define PTE_BITS_NON_RWX_IN_PD1 (PAGE_MASK \| _PAGE_CACHEABLE)
140		−#define MAX_POSSIBLE_PHYSMEM_BITS 32
141		−#endif
	135	+#define PTE_BITS_NON_RWX_IN_PD1 (PAGE_MASK_PHYS \| _PAGE_CACHEABLE)
142	136
143	137	/**************************************************************************
144	138	* Mapping of vm_flags (Generic VM) to PTE flags (arch specific)

arch/arc/include/uapi/asm/page.h+0−1

@@ -33,5 +33,4 @@ · 32 unmodified lines
33	33
34	34	#define PAGE_MASK (~(PAGE_SIZE-1))
35	35
36		−
37	36	#endif /* _UAPI__ASM_ARC_PAGE_H */

arch/arc/include/uapi/asm/sigcontext.h+1−0

@@ -18,6 +18,7 @@ · 17 unmodified lines
18	18	*/
19	19	struct sigcontext {
20	20	struct user_regs_struct regs;
	21	+ struct user_regs_arcv2 v2abi;
21	22	};
22	23
23	24	#endif /* _ASM_ARC_SIGCONTEXT_H */

arch/arc/kernel/entry.S+2−2

@@ -177,7 +177,7 @@ tracesys: · 176 unmodified lines
177	177
178	178	; Do the Sys Call as we normally would.
179	179	; Validate the Sys Call number
180		− cmp r8, NR_syscalls
	180	+ cmp r8, NR_syscalls - 1
181	181	mov.hi r0, -ENOSYS
182	182	bhi tracesys_exit
183	183
@@ -255,7 +255,7 @@ ENTRY(EV_Trap) · 71 unmodified lines
255	255	;============ Normal syscall case
256	256
257	257	; syscall num shd not exceed the total system calls avail
258		− cmp r8, NR_syscalls
	258	+ cmp r8, NR_syscalls - 1
259	259	mov.hi r0, -ENOSYS
260	260	bhi .Lret_from_system_call
261	261

arch/arc/kernel/kgdb.c+1−0

@@ -140,6 +140,7 @@ int kgdb_arch_handle_exception(int e_vector, int signo, int err_code, · 139 unmodified lines
140	140	ptr = &remcomInBuffer[1];
141	141	if (kgdb_hex2long(&ptr, &addr))
142	142	regs->ret = addr;
	143	+ fallthrough;
143	144
144	145	case 'D':
145	146	case 'k':

arch/arc/kernel/process.c+4−4

@@ -50,14 +50,14 @@ SYSCALL_DEFINE3(arc_usr_cmpxchg, int *, uaddr, int, expected, int, new) · 49 unmodified lines
50	50	int ret;
51	51
52	52	/*
53		− * This is only for old cores lacking LLOCK/SCOND, which by defintion
	53	+ * This is only for old cores lacking LLOCK/SCOND, which by definition
54	54	* can't possibly be SMP. Thus doesn't need to be SMP safe.
55	55	* And this also helps reduce the overhead for serializing in
56	56	* the UP case
57	57	*/
58	58	WARN_ON_ONCE(IS_ENABLED(CONFIG_SMP));
59	59
60		− /* Z indicates to userspace if operation succeded */
	60	+ /* Z indicates to userspace if operation succeeded */
61	61	regs->status32 &= ~STATUS_Z_MASK;
62	62
63	63	ret = access_ok(uaddr, sizeof(*uaddr));
@@ -107,7 +107,7 @@ fail: · 43 unmodified lines
107	107
108	108	void arch_cpu_idle(void)
109	109	{
110		− /* Re-enable interrupts <= default irq priority before commiting SLEEP */
	110	+ /* Re-enable interrupts <= default irq priority before committing SLEEP */
111	111	const unsigned int arg = 0x10 \| ARCV2_IRQ_DEF_PRIO;
112	112
113	113	__asm__ __volatile__(
@@ -120,7 +120,7 @@ void arch_cpu_idle(void) · 6 unmodified lines
120	120
121	121	void arch_cpu_idle(void)
122	122	{
123		− /* sleep, but enable both set E1/E2 (levels of interrutps) before committing */
	123	+ /* sleep, but enable both set E1/E2 (levels of interrupts) before committing */
124	124	__asm__ __volatile__("sleep 0x3 \n");
125	125	}
126	126

arch/arc/kernel/signal.c+45−2

@@ -61,6 +61,41 @@ struct rt_sigframe { · 60 unmodified lines
61	61	unsigned int sigret_magic;
62	62	};
63	63
	64	+static int save_arcv2_regs(struct sigcontext mctx, struct pt_regs regs)
	65	+{
	66	+ int err = 0;
	67	+#ifndef CONFIG_ISA_ARCOMPACT
	68	+ struct user_regs_arcv2 v2abi;
	69	+
	70	+ v2abi.r30 = regs->r30;
	71	+#ifdef CONFIG_ARC_HAS_ACCL_REGS
	72	+ v2abi.r58 = regs->r58;
	73	+ v2abi.r59 = regs->r59;
	74	+#else
	75	+ v2abi.r58 = v2abi.r59 = 0;
	76	+#endif
	77	+ err = __copy_to_user(&mctx->v2abi, &v2abi, sizeof(v2abi));
	78	+#endif
	79	+ return err;
	80	+}
	81	+
	82	+static int restore_arcv2_regs(struct sigcontext mctx, struct pt_regs regs)
	83	+{
	84	+ int err = 0;
	85	+#ifndef CONFIG_ISA_ARCOMPACT
	86	+ struct user_regs_arcv2 v2abi;
	87	+
	88	+ err = __copy_from_user(&v2abi, &mctx->v2abi, sizeof(v2abi));
	89	+
	90	+ regs->r30 = v2abi.r30;
	91	+#ifdef CONFIG_ARC_HAS_ACCL_REGS
	92	+ regs->r58 = v2abi.r58;
	93	+ regs->r59 = v2abi.r59;
	94	+#endif
	95	+#endif
	96	+ return err;
	97	+}
	98	+
64	99	static int
65	100	stash_usr_regs(struct rt_sigframe __user sf, struct pt_regs regs,
66	101	sigset_t *set)
@@ -94,6 +129,10 @@ stash_usr_regs(struct rt_sigframe __user sf, struct pt_regs regs, · 27 unmodified lines
94	129
95	130	err = __copy_to_user(&(sf->uc.uc_mcontext.regs.scratch), &uregs.scratch,
96	131	sizeof(sf->uc.uc_mcontext.regs.scratch));
	132	+
	133	+ if (is_isa_arcv2())
	134	+ err \|= save_arcv2_regs(&(sf->uc.uc_mcontext), regs);
	135	+
97	136	err \|= __copy_to_user(&sf->uc.uc_sigmask, set, sizeof(sigset_t));
98	137
99	138	return err ? -EFAULT : 0;
@@ -109,6 +148,10 @@ static int restore_usr_regs(struct pt_regs regs, struct rt_sigframe __user sf) · 9 unmodified lines
109	148	err \|= __copy_from_user(&uregs.scratch,
110	149	&(sf->uc.uc_mcontext.regs.scratch),
111	150	sizeof(sf->uc.uc_mcontext.regs.scratch));
	151	+
	152	+ if (is_isa_arcv2())
	153	+ err \|= restore_arcv2_regs(&(sf->uc.uc_mcontext), regs);
	154	+
112	155	if (err)
113	156	return -EFAULT;
114	157
@@ -259,7 +302,7 @@ setup_rt_frame(struct ksignal ksig, sigset_t set, struct pt_regs *regs) · 144 unmodified lines
259	302	regs->r2 = (unsigned long)&sf->uc;
260	303
261	304	/*
262		− * small optim to avoid unconditonally calling do_sigaltstack
	305	+ * small optim to avoid unconditionally calling do_sigaltstack
263	306	* in sigreturn path, now that we only have rt_sigreturn
264	307	*/
265	308	magic = MAGIC_SIGALTSTK;
@@ -391,7 +434,7 @@ void do_signal(struct pt_regs *regs) · 125 unmodified lines
391	434	void do_notify_resume(struct pt_regs *regs)
392	435	{
393	436	/*
394		− * ASM glue gaurantees that this is only called when returning to
	437	+ * ASM glue guarantees that this is only called when returning to
395	438	* user mode
396	439	*/
397	440	if (test_thread_flag(TIF_NOTIFY_RESUME))

arch/arc/kernel/vmlinux.lds.S+1−1

@@ -57,7 +57,6 @@ SECTIONS · 56 unmodified lines
57	57	.init.ramfs : { INIT_RAM_FS }
58	58
59	59	. = ALIGN(PAGE_SIZE);
60		− _stext = .;
61	60
62	61	HEAD_TEXT_SECTION
63	62	INIT_TEXT_SECTION(L1_CACHE_BYTES)
@@ -83,6 +82,7 @@ SECTIONS · 19 unmodified lines
83	82
84	83	.text : {
85	84	_text = .;
	85	+ _stext = .;
86	86	TEXT_TEXT
87	87	SCHED_TEXT
88	88	CPUIDLE_TEXT

arch/arc/mm/init.c+10−1

@@ -157,7 +157,16 @@ void __init setup_arch_memory(void) · 156 unmodified lines
157	157	min_high_pfn = PFN_DOWN(high_mem_start);
158	158	max_high_pfn = PFN_DOWN(high_mem_start + high_mem_sz);
159	159
160		− max_zone_pfn[ZONE_HIGHMEM] = min_low_pfn;
	160	+ /*
	161	+ * max_high_pfn should be ok here for both HIGHMEM and HIGHMEM+PAE.
	162	+ * For HIGHMEM without PAE max_high_pfn should be less than
	163	+ * min_low_pfn to guarantee that these two regions don't overlap.
	164	+ * For PAE case highmem is greater than lowmem, so it is natural
	165	+ * to use max_high_pfn.
	166	+ *
	167	+ * In both cases, holes should be handled by pfn_valid().
	168	+ */
	169	+ max_zone_pfn[ZONE_HIGHMEM] = max_high_pfn;
161	170
162	171	high_memory = (void *)(min_high_pfn << PAGE_SHIFT);
163	172

arch/arc/mm/ioremap.c+3−2

@@ -53,9 +53,10 @@ EXPORT_SYMBOL(ioremap); · 52 unmodified lines
53	53	void __iomem *ioremap_prot(phys_addr_t paddr, unsigned long size,
54	54	unsigned long flags)
55	55	{
	56	+ unsigned int off;
56	57	unsigned long vaddr;
57	58	struct vm_struct *area;
58		− phys_addr_t off, end;
	59	+ phys_addr_t end;
59	60	pgprot_t prot = __pgprot(flags);
60	61
61	62	/* Don't allow wraparound, zero size */
@@ -72,7 +73,7 @@ void __iomem *ioremap_prot(phys_addr_t paddr, unsigned long size, · 10 unmodified lines
72	73
73	74	/* Mappings have to be page-aligned */
74	75	off = paddr & ~PAGE_MASK;
75		− paddr &= PAGE_MASK;
	76	+ paddr &= PAGE_MASK_PHYS;
76	77	size = PAGE_ALIGN(end + 1) - paddr;
77	78
78	79	/*

arch/arc/mm/tlb.c+1−1

@@ -576,7 +576,7 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddr_unaligned, · 575 unmodified lines
576	576	pte_t *ptep)
577	577	{
578	578	unsigned long vaddr = vaddr_unaligned & PAGE_MASK;
579		− phys_addr_t paddr = pte_val(*ptep) & PAGE_MASK;
	579	+ phys_addr_t paddr = pte_val(*ptep) & PAGE_MASK_PHYS;
580	580	struct page page = pfn_to_page(pte_pfn(ptep));
581	581
582	582	create_tlb(vma, vaddr, ptep);

arch/arm/boot/dts/imx6dl-yapp4-common.dtsi+5−1

@@ -105,9 +105,13 @@ · 104 unmodified lines
105	105	phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
106	106	phy-reset-duration = <20>;
107	107	phy-supply = <&sw2_reg>;
108		− phy-handle = <&ethphy0>;
109	108	status = "okay";
110	109
	110	+ fixed-link {
	111	+ speed = <1000>;
	112	+ full-duplex;
	113	+ };
	114	+
111	115	mdio {
112	116	#address-cells = <1>;
113	117	#size-cells = <0>;

arch/arm/boot/dts/imx6q-dhcom-som.dtsi+12−0

@@ -406,6 +406,18 @@ · 405 unmodified lines
406	406	vin-supply = <&sw1_reg>;
407	407	};
408	408
	409	+&reg_pu {
	410	+ vin-supply = <&sw1_reg>;
	411	+};
	412	+
	413	+&reg_vdd1p1 {
	414	+ vin-supply = <&sw2_reg>;
	415	+};
	416	+
	417	+&reg_vdd2p5 {
	418	+ vin-supply = <&sw2_reg>;
	419	+};
	420	+
409	421	&uart1 {
410	422	pinctrl-names = "default";
411	423	pinctrl-0 = <&pinctrl_uart1>;

arch/arm/boot/dts/imx6qdl-emcon-avari.dtsi+1−1

@@ -126,7 +126,7 @@ · 125 unmodified lines
126	126	compatible = "nxp,pca8574";
127	127	reg = <0x3a>;
128	128	gpio-controller;
129		− #gpio-cells = <1>;
	129	+ #gpio-cells = <2>;
130	130	};
131	131	};
132	132

arch/arm/boot/dts/imx7d-meerkat96.dts+1−1

@@ -193,7 +193,7 @@ · 192 unmodified lines
193	193	pinctrl-names = "default";
194	194	pinctrl-0 = <&pinctrl_usdhc1>;
195	195	keep-power-in-suspend;
196		− tuning-step = <2>;
	196	+ fsl,tuning-step = <2>;
197	197	vmmc-supply = <&reg_3p3v>;
198	198	no-1-8-v;
199	199	broken-cd;

arch/arm/boot/dts/imx7d-pico.dtsi+1−1

@@ -351,7 +351,7 @@ · 350 unmodified lines
351	351	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
352	352	cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
353	353	bus-width = <4>;
354		− tuning-step = <2>;
	354	+ fsl,tuning-step = <2>;
355	355	vmmc-supply = <&reg_3p3v>;
356	356	wakeup-source;
357	357	no-1-8-v;

arch/arm/include/asm/cpuidle.h+3−2

@@ -7,9 +7,11 @@ · 6 unmodified lines
7	7	#ifdef CONFIG_CPU_IDLE
8	8	extern int arm_cpuidle_simple_enter(struct cpuidle_device *dev,
9	9	struct cpuidle_driver *drv, int index);
	10	+#define __cpuidle_method_section __used __section("__cpuidle_method_of_table")
10	11	#else
11	12	static inline int arm_cpuidle_simple_enter(struct cpuidle_device *dev,
12	13	struct cpuidle_driver *drv, int index) { return -ENODEV; }
	14	+#define __cpuidle_method_section __maybe_unused /* drop silently */
13	15	#endif
14	16
15	17	/* Common ARM WFI state */
@@ -42,8 +44,7 @@ struct of_cpuidle_method { · 26 unmodified lines
42	44
43	45	#define CPUIDLE_METHOD_OF_DECLARE(name, _method, _ops) \
44	46	static const struct of_cpuidle_method __cpuidle_method_of_table_##name \
45		− __used __section("__cpuidle_method_of_table") \
46		− = { .method = _method, .ops = _ops }
	47	+ __cpuidle_method_section = { .method = _method, .ops = _ops }
47	48
48	49	extern int arm_cpuidle_suspend(int index);
49	50

arch/arm/mach-imx/pm-imx27.c+1−0

@@ -12,6 +12,7 @@ · 11 unmodified lines
12	12	#include <linux/suspend.h>
13	13	#include <linux/io.h>
14	14
	15	+#include "common.h"
15	16	#include "hardware.h"
16	17
17	18	static int mx27_suspend_enter(suspend_state_t state)

arch/arm/mach-npcm/Kconfig+1−0

@@ -10,6 +10,7 @@ config ARCH_WPCM450 · 9 unmodified lines
10	10	bool "Support for WPCM450 BMC (Hermon)"
11	11	depends on ARCH_MULTI_V5
12	12	select CPU_ARM926T
	13	+ select WPCM450_AIC
13	14	select NPCM7XX_TIMER
14	15	help
15	16	General support for WPCM450 BMC (Hermon).

arch/arm/mach-omap1/board-ams-delta.c+0−14

@@ -458,20 +458,6 @@ static struct gpiod_lookup_table leds_gpio_table = { · 457 unmodified lines
458	458
459	459	#ifdef CONFIG_LEDS_TRIGGERS
460	460	DEFINE_LED_TRIGGER(ams_delta_camera_led_trigger);
461		−
462		−static int ams_delta_camera_power(struct device *dev, int power)
463		−{
464		− /*
465		− * turn on camera LED
466		− */
467		− if (power)
468		− led_trigger_event(ams_delta_camera_led_trigger, LED_FULL);
469		− else
470		− led_trigger_event(ams_delta_camera_led_trigger, LED_OFF);
471		− return 0;
472		−}
473		−#else
474		−#define ams_delta_camera_power NULL
475	461	#endif
476	462
477	463	static struct platform_device ams_delta_audio_device = {

arch/arm/mach-omap1/board-h2.c+3−1

@@ -320,7 +320,7 @@ static int tps_setup(struct i2c_client client, void context) · 319 unmodified lines
320	320	{
321	321	if (!IS_BUILTIN(CONFIG_TPS65010))
322	322	return -ENOSYS;
323		−
	323	+
324	324	tps65010_config_vregs1(TPS_LDO2_ENABLE \| TPS_VLDO2_3_0V \|
325	325	TPS_LDO1_ENABLE \| TPS_VLDO1_3_0V);
326	326
@@ -394,6 +394,8 @@ static void __init h2_init(void) · 67 unmodified lines
394	394	BUG_ON(gpio_request(H2_NAND_RB_GPIO_PIN, "NAND ready") < 0);
395	395	gpio_direction_input(H2_NAND_RB_GPIO_PIN);
396	396
	397	+ gpiod_add_lookup_table(&isp1301_gpiod_table);
	398	+
397	399	omap_cfg_reg(L3_1610_FLASH_CS2B_OE);
398	400	omap_cfg_reg(M8_1610_FLASH_CS2B_WE);
399	401

arch/arm/mach-omap1/pm.c+7−3

@@ -655,9 +655,13 @@ static int __init omap_pm_init(void) · 654 unmodified lines
655	655	irq = INT_7XX_WAKE_UP_REQ;
656	656	else if (cpu_is_omap16xx())
657	657	irq = INT_1610_WAKE_UP_REQ;
658		− if (request_irq(irq, omap_wakeup_interrupt, 0, "peripheral wakeup",
659		− NULL))
660		− pr_err("Failed to request irq %d (peripheral wakeup)\n", irq);
	658	+ else
	659	+ irq = -1;
	660	+
	661	+ if (irq >= 0) {
	662	+ if (request_irq(irq, omap_wakeup_interrupt, 0, "peripheral wakeup", NULL))
	663	+ pr_err("Failed to request irq %d (peripheral wakeup)\n", irq);
	664	+ }
661	665
662	666	/* Program new power ramp-up time
663	667	* (0 for most boards since we don't lower voltage when in deep sleep)

arch/arm/mach-omap2/board-n8x0.c+1−1

@@ -322,6 +322,7 @@ static int n8x0_mmc_get_cover_state(struct device *dev, int slot) · 321 unmodified lines
322	322
323	323	static void n8x0_mmc_callback(void *data, u8 card_mask)
324	324	{
	325	+#ifdef CONFIG_MMC_OMAP
325	326	int bit, *openp, index;
326	327
327	328	if (board_is_n800()) {
@@ -339,7 +340,6 @@ static void n8x0_mmc_callback(void *data, u8 card_mask) · 11 unmodified lines
339	340	else
340	341	*openp = 0;
341	342
342		−#ifdef CONFIG_MMC_OMAP
343	343	omap_mmc_notify_cover_event(mmc_device, index, *openp);
344	344	#else
345	345	pr_warn("MMC: notify cover event not available\n");

arch/arm/mach-pxa/pxa_cplds_irqs.c+6−1

@@ -121,8 +121,13 @@ static int cplds_probe(struct platform_device *pdev) · 120 unmodified lines
121	121	return fpga->irq;
122	122
123	123	base_irq = platform_get_irq(pdev, 1);
124		− if (base_irq < 0)
	124	+ if (base_irq < 0) {
125	125	base_irq = 0;
	126	+ } else {
	127	+ ret = devm_irq_alloc_descs(&pdev->dev, base_irq, base_irq, CPLDS_NB_IRQ, 0);
	128	+ if (ret < 0)
	129	+ return ret;
	130	+ }
126	131
127	132	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
128	133	fpga->base = devm_ioremap_resource(&pdev->dev, res);

arch/arm/tools/syscall.tbl+1−1

@@ -456,7 +456,7 @@ · 455 unmodified lines
456	456	440 common process_madvise sys_process_madvise
457	457	441 common epoll_pwait2 sys_epoll_pwait2
458	458	442 common mount_setattr sys_mount_setattr
459		−443 common quotactl_path sys_quotactl_path
	459	+# 443 reserved for quotactl_path
460	460	444 common landlock_create_ruleset sys_landlock_create_ruleset
461	461	445 common landlock_add_rule sys_landlock_add_rule
462	462	446 common landlock_restrict_self sys_landlock_restrict_self

arch/arm/xen/mm.c+7−13

@@ -135,24 +135,18 @@ void xen_destroy_contiguous_region(phys_addr_t pstart, unsigned int order) · 134 unmodified lines
135	135	return;
136	136	}
137	137
138		−int xen_swiotlb_detect(void)
139		−{
140		− if (!xen_domain())
141		− return 0;
142		− if (xen_feature(XENFEAT_direct_mapped))
143		− return 1;
144		− /* legacy case */
145		− if (!xen_feature(XENFEAT_not_direct_mapped) && xen_initial_domain())
146		− return 1;
147		− return 0;
148		−}
149		−
150	138	static int __init xen_mm_init(void)
151	139	{
152	140	struct gnttab_cache_flush cflush;
	141	+ int rc;
	142	+
153	143	if (!xen_swiotlb_detect())
154	144	return 0;
155		− xen_swiotlb_init();
	145	+
	146	+ rc = xen_swiotlb_init();
	147	+ /* we can work with the default swiotlb */
	148	+ if (rc < 0 && rc != -EEXIST)
	149	+ return rc;
156	150
157	151	cflush.op = 0;
158	152	cflush.a.dev_bus_addr = 0;

arch/arm64/Kbuild+1−2

@@ -1,6 +1,5 @@
1	1	# SPDX-License-Identifier: GPL-2.0-only
2		−obj-y += kernel/ mm/
3		−obj-$(CONFIG_NET) += net/
	2	+obj-y += kernel/ mm/ net/
4	3	obj-$(CONFIG_KVM) += kvm/
5	4	obj-$(CONFIG_XEN) += xen/
6	5	obj-$(CONFIG_CRYPTO) += crypto/

arch/arm64/Kconfig.platforms+1−0

@@ -165,6 +165,7 @@ config ARCH_MEDIATEK · 164 unmodified lines
165	165
166	166	config ARCH_MESON
167	167	bool "Amlogic Platforms"
	168	+ select COMMON_CLK
168	169	select MESON_IRQ_GPIO
169	170	help
170	171	This enables support for the arm64 based Amlogic SoCs

arch/arm64/Makefile+3−0

@@ -175,6 +175,9 @@ vdso_install: · 174 unmodified lines
175	175	$(if $(CONFIG_COMPAT_VDSO), \
176	176	$(Q)$(MAKE) $(build)=arch/arm64/kernel/vdso32 $@)
177	177
	178	+archprepare:
	179	+ $(Q)$(MAKE) $(build)=arch/arm64/tools kapi
	180	+
178	181	# We use MRPROPER_FILES and CLEAN_FILES now
179	182	archclean:
180	183	$(Q)$(MAKE) $(clean)=$(boot)

arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dts+2−1

@@ -46,7 +46,8 @@ · 45 unmodified lines
46	46	eee-broken-100tx;
47	47	qca,clk-out-frequency = <125000000>;
48	48	qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
49		− vddio-supply = <&vddh>;
	49	+ qca,keep-pll-enabled;
	50	+ vddio-supply = <&vddio>;
50	51
51	52	vddio: vddio-regulator {
52	53	regulator-name = "VDDIO";

arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts+2−3

@@ -31,11 +31,10 @@ · 30 unmodified lines
31	31	reg = <0x4>;
32	32	eee-broken-1000t;
33	33	eee-broken-100tx;
34		−
35	34	qca,clk-out-frequency = <125000000>;
36	35	qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
37		−
38		− vddio-supply = <&vddh>;
	36	+ qca,keep-pll-enabled;
	37	+ vddio-supply = <&vddio>;
39	38
40	39	vddio: vddio-regulator {
41	40	regulator-name = "VDDIO";

arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi+2−2

@@ -197,8 +197,8 @@ · 196 unmodified lines
197	197	ddr: memory-controller@1080000 {
198	198	compatible = "fsl,qoriq-memory-controller";
199	199	reg = <0x0 0x1080000 0x0 0x1000>;
200		− interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
201		− big-endian;
	200	+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	201	+ little-endian;
202	202	};
203	203
204	204	dcfg: syscon@1e00000 {

arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dts+5−5

@@ -88,11 +88,11 @@ · 87 unmodified lines
88	88	pinctrl-0 = <&pinctrl_codec2>;
89	89	reg = <0x18>;
90	90	#sound-dai-cells = <0>;
91		− HPVDD-supply = <&reg_3p3v>;
92		− SPRVDD-supply = <&reg_3p3v>;
93		− SPLVDD-supply = <&reg_3p3v>;
94		− AVDD-supply = <&reg_3p3v>;
95		− IOVDD-supply = <&reg_3p3v>;
	91	+ HPVDD-supply = <&reg_gen_3p3>;
	92	+ SPRVDD-supply = <&reg_gen_3p3>;
	93	+ SPLVDD-supply = <&reg_gen_3p3>;
	94	+ AVDD-supply = <&reg_gen_3p3>;
	95	+ IOVDD-supply = <&reg_gen_3p3>;
96	96	DVDD-supply = <&vgen4_reg>;
97	97	reset-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
98	98	};

arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi+7−16

@@ -45,8 +45,8 @@ · 44 unmodified lines
45	45	reg_12p0_main: regulator-12p0-main {
46	46	compatible = "regulator-fixed";
47	47	regulator-name = "12V_MAIN";
48		− regulator-min-microvolt = <5000000>;
49		− regulator-max-microvolt = <5000000>;
	48	+ regulator-min-microvolt = <12000000>;
	49	+ regulator-max-microvolt = <12000000>;
50	50	regulator-always-on;
51	51	};
52	52
@@ -77,15 +77,6 @@ · 24 unmodified lines
77	77	regulator-always-on;
78	78	};
79	79
80		− reg_3p3v: regulator-3p3v {
81		− compatible = "regulator-fixed";
82		− vin-supply = <&reg_3p3_main>;
83		− regulator-name = "GEN_3V3";
84		− regulator-min-microvolt = <3300000>;
85		− regulator-max-microvolt = <3300000>;
86		− regulator-always-on;
87		− };
88		−
89	80	reg_usdhc2_vmmc: regulator-vsd-3v3 {
90	81	pinctrl-names = "default";
91	82	pinctrl-0 = <&pinctrl_reg_usdhc2>;
@@ -415,11 +406,11 @@ · 323 unmodified lines
415	406	pinctrl-0 = <&pinctrl_codec1>;
416	407	reg = <0x18>;
417	408	#sound-dai-cells = <0>;
418		− HPVDD-supply = <&reg_3p3v>;
419		− SPRVDD-supply = <&reg_3p3v>;
420		− SPLVDD-supply = <&reg_3p3v>;
421		− AVDD-supply = <&reg_3p3v>;
422		− IOVDD-supply = <&reg_3p3v>;
	409	+ HPVDD-supply = <&reg_gen_3p3>;
	410	+ SPRVDD-supply = <&reg_gen_3p3>;
	411	+ SPLVDD-supply = <&reg_gen_3p3>;
	412	+ AVDD-supply = <&reg_gen_3p3>;
	413	+ IOVDD-supply = <&reg_gen_3p3>;
423	414	DVDD-supply = <&vgen4_reg>;
424	415	reset-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>;
425	416	};

arch/arm64/boot/dts/renesas/hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi+0−2

@@ -14,7 +14,6 @@ · 13 unmodified lines
14	14
15	15	ports {
16	16	port@0 {
17		− reg = <0>;
18	17	csi20_in: endpoint {
19	18	clock-lanes = <0>;
20	19	data-lanes = <1 2>;
@@ -29,7 +28,6 @@ · 8 unmodified lines
29	28
30	29	ports {
31	30	port@0 {
32		− reg = <0>;
33	31	csi40_in: endpoint {
34	32	clock-lanes = <0>;
35	33	data-lanes = <1 2>;

arch/arm64/boot/dts/renesas/r8a774a1.dtsi+8−0

@@ -2573,6 +2573,10 @@ · 2572 unmodified lines
2573	2573	#address-cells = <1>;
2574	2574	#size-cells = <0>;
2575	2575
	2576	+ port@0 {
	2577	+ reg = <0>;
	2578	+ };
	2579	+
2576	2580	port@1 {
2577	2581	#address-cells = <1>;
2578	2582	#size-cells = <0>;
@@ -2628,6 +2632,10 @@ · 49 unmodified lines
2628	2632	#address-cells = <1>;
2629	2633	#size-cells = <0>;
2630	2634
	2635	+ port@0 {
	2636	+ reg = <0>;
	2637	+ };
	2638	+
2631	2639	port@1 {
2632	2640	#address-cells = <1>;
2633	2641	#size-cells = <0>;

arch/arm64/boot/dts/renesas/r8a774b1.dtsi+8−0

@@ -2419,6 +2419,10 @@ · 2418 unmodified lines
2419	2419	#address-cells = <1>;
2420	2420	#size-cells = <0>;
2421	2421
	2422	+ port@0 {
	2423	+ reg = <0>;
	2424	+ };
	2425	+
2422	2426	port@1 {
2423	2427	#address-cells = <1>;
2424	2428	#size-cells = <0>;
@@ -2474,6 +2478,10 @@ · 49 unmodified lines
2474	2478	#address-cells = <1>;
2475	2479	#size-cells = <0>;
2476	2480
	2481	+ port@0 {
	2482	+ reg = <0>;
	2483	+ };
	2484	+
2477	2485	port@1 {
2478	2486	#address-cells = <1>;
2479	2487	#size-cells = <0>;

arch/arm64/boot/dts/renesas/r8a774c0-ek874-mipi-2.1.dts+1−1

@@ -33,7 +33,7 @@ · 32 unmodified lines
33	33	status = "okay";
34	34
35	35	ports {
36		− port {
	36	+ port@0 {
37	37	csi40_in: endpoint {
38	38	clock-lanes = <0>;
39	39	data-lanes = <1 2>;

arch/arm64/boot/dts/renesas/r8a774c0.dtsi+4−0

@@ -1823,6 +1823,10 @@ · 1822 unmodified lines
1823	1823	#address-cells = <1>;
1824	1824	#size-cells = <0>;
1825	1825
	1826	+ port@0 {
	1827	+ reg = <0>;
	1828	+ };
	1829	+
1826	1830	port@1 {
1827	1831	#address-cells = <1>;
1828	1832	#size-cells = <0>;

arch/arm64/boot/dts/renesas/r8a774e1.dtsi+8−0

@@ -2709,6 +2709,10 @@ · 2708 unmodified lines
2709	2709	#address-cells = <1>;
2710	2710	#size-cells = <0>;
2711	2711
	2712	+ port@0 {
	2713	+ reg = <0>;
	2714	+ };
	2715	+
2712	2716	port@1 {
2713	2717	#address-cells = <1>;
2714	2718	#size-cells = <0>;
@@ -2764,6 +2768,10 @@ · 49 unmodified lines
2764	2768	#address-cells = <1>;
2765	2769	#size-cells = <0>;
2766	2770
	2771	+ port@0 {
	2772	+ reg = <0>;
	2773	+ };
	2774	+
2767	2775	port@1 {
2768	2776	#address-cells = <1>;
2769	2777	#size-cells = <0>;

arch/arm64/boot/dts/renesas/r8a77950.dtsi+4−0

@@ -192,6 +192,10 @@ · 191 unmodified lines
192	192	#address-cells = <1>;
193	193	#size-cells = <0>;
194	194
	195	+ port@0 {
	196	+ reg = <0>;
	197	+ };
	198	+
195	199	port@1 {
196	200	#address-cells = <1>;
197	201	#size-cells = <0>;

arch/arm64/boot/dts/renesas/r8a77951.dtsi+12−0

@@ -3097,6 +3097,10 @@ · 3096 unmodified lines
3097	3097	#address-cells = <1>;
3098	3098	#size-cells = <0>;
3099	3099
	3100	+ port@0 {
	3101	+ reg = <0>;
	3102	+ };
	3103	+
3100	3104	port@1 {
3101	3105	#address-cells = <1>;
3102	3106	#size-cells = <0>;
@@ -3152,6 +3156,10 @@ · 49 unmodified lines
3152	3156	#address-cells = <1>;
3153	3157	#size-cells = <0>;
3154	3158
	3159	+ port@0 {
	3160	+ reg = <0>;
	3161	+ };
	3162	+
3155	3163	port@1 {
3156	3164	#address-cells = <1>;
3157	3165	#size-cells = <0>;
@@ -3191,6 +3199,10 @@ · 33 unmodified lines
3191	3199	#address-cells = <1>;
3192	3200	#size-cells = <0>;
3193	3201
	3202	+ port@0 {
	3203	+ reg = <0>;
	3204	+ };
	3205	+
3194	3206	port@1 {
3195	3207	#address-cells = <1>;
3196	3208	#size-cells = <0>;

arch/arm64/boot/dts/renesas/r8a77960.dtsi+8−0

@@ -2761,6 +2761,10 @@ · 2760 unmodified lines
2761	2761	#address-cells = <1>;
2762	2762	#size-cells = <0>;
2763	2763
	2764	+ port@0 {
	2765	+ reg = <0>;
	2766	+ };
	2767	+
2764	2768	port@1 {
2765	2769	#address-cells = <1>;
2766	2770	#size-cells = <0>;
@@ -2816,6 +2820,10 @@ · 49 unmodified lines
2816	2820	#address-cells = <1>;
2817	2821	#size-cells = <0>;
2818	2822
	2823	+ port@0 {
	2824	+ reg = <0>;
	2825	+ };
	2826	+
2819	2827	port@1 {
2820	2828	#address-cells = <1>;
2821	2829	#size-cells = <0>;

arch/arm64/boot/dts/renesas/r8a77961.dtsi+8−0

@@ -2499,6 +2499,10 @@ · 2498 unmodified lines
2499	2499	#address-cells = <1>;
2500	2500	#size-cells = <0>;
2501	2501
	2502	+ port@0 {
	2503	+ reg = <0>;
	2504	+ };
	2505	+
2502	2506	port@1 {
2503	2507	#address-cells = <1>;
2504	2508	#size-cells = <0>;
@@ -2554,6 +2558,10 @@ · 49 unmodified lines
2554	2558	#address-cells = <1>;
2555	2559	#size-cells = <0>;
2556	2560
	2561	+ port@0 {
	2562	+ reg = <0>;
	2563	+ };
	2564	+
2557	2565	port@1 {
2558	2566	#address-cells = <1>;
2559	2567	#size-cells = <0>;

arch/arm64/boot/dts/renesas/r8a77965.dtsi+8−0

@@ -2575,6 +2575,10 @@ · 2574 unmodified lines
2575	2575	#address-cells = <1>;
2576	2576	#size-cells = <0>;
2577	2577
	2578	+ port@0 {
	2579	+ reg = <0>;
	2580	+ };
	2581	+
2578	2582	port@1 {
2579	2583	#address-cells = <1>;
2580	2584	#size-cells = <0>;
@@ -2630,6 +2634,10 @@ · 49 unmodified lines
2630	2634	#address-cells = <1>;
2631	2635	#size-cells = <0>;
2632	2636
	2637	+ port@0 {
	2638	+ reg = <0>;
	2639	+ };
	2640	+
2633	2641	port@1 {
2634	2642	#address-cells = <1>;
2635	2643	#size-cells = <0>;

arch/arm64/boot/dts/renesas/r8a77970.dtsi+4−0

@@ -1106,6 +1106,10 @@ · 1105 unmodified lines
1106	1106	#address-cells = <1>;
1107	1107	#size-cells = <0>;
1108	1108
	1109	+ port@0 {
	1110	+ reg = <0>;
	1111	+ };
	1112	+
1109	1113	port@1 {
1110	1114	#address-cells = <1>;
1111	1115	#size-cells = <0>;

arch/arm64/boot/dts/renesas/r8a77980.dtsi+8−0

@@ -1439,6 +1439,10 @@ · 1438 unmodified lines
1439	1439	#address-cells = <1>;
1440	1440	#size-cells = <0>;
1441	1441
	1442	+ port@0 {
	1443	+ reg = <0>;
	1444	+ };
	1445	+
1442	1446	port@1 {
1443	1447	#address-cells = <1>;
1444	1448	#size-cells = <0>;
@@ -1478,6 +1482,10 @@ · 33 unmodified lines
1478	1482	#address-cells = <1>;
1479	1483	#size-cells = <0>;
1480	1484
	1485	+ port@0 {
	1486	+ reg = <0>;
	1487	+ };
	1488	+
1481	1489	port@1 {
1482	1490	#address-cells = <1>;
1483	1491	#size-cells = <0>;

arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts+0−2

@@ -298,8 +298,6 @@ · 297 unmodified lines
298	298
299	299	ports {
300	300	port@0 {
301		− reg = <0>;
302		−
303	301	csi40_in: endpoint {
304	302	clock-lanes = <0>;
305	303	data-lanes = <1 2>;

arch/arm64/boot/dts/renesas/r8a77990.dtsi+4−0

@@ -1970,6 +1970,10 @@ · 1969 unmodified lines
1970	1970	#address-cells = <1>;
1971	1971	#size-cells = <0>;
1972	1972
	1973	+ port@0 {
	1974	+ reg = <0>;
	1975	+ };
	1976	+
1973	1977	port@1 {
1974	1978	#address-cells = <1>;
1975	1979	#size-cells = <0>;

arch/arm64/boot/dts/renesas/salvator-common.dtsi+0−3

@@ -349,7 +349,6 @@ · 348 unmodified lines
349	349
350	350	ports {
351	351	port@0 {
352		− reg = <0>;
353	352	csi20_in: endpoint {
354	353	clock-lanes = <0>;
355	354	data-lanes = <1>;
@@ -364,8 +363,6 @@ · 8 unmodified lines
364	363
365	364	ports {
366	365	port@0 {
367		− reg = <0>;
368		−
369	366	csi40_in: endpoint {
370	367	clock-lanes = <0>;
371	368	data-lanes = <1 2 3 4>;

arch/arm64/boot/dts/ti/k3-am64-main.dtsi+6−5

@@ -42,12 +42,12 @@ · 41 unmodified lines
42	42	};
43	43	};
44	44
45		− dmss: dmss {
	45	+ dmss: bus@48000000 {
46	46	compatible = "simple-mfd";
47	47	#address-cells = <2>;
48	48	#size-cells = <2>;
49	49	dma-ranges;
50		− ranges;
	50	+ ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
51	51
52	52	ti,sci-dev-id = <25>;
53	53
@@ -134,7 +134,7 @@ · 80 unmodified lines
134	134	};
135	135	};
136	136
137		− dmsc: dmsc@44043000 {
	137	+ dmsc: system-controller@44043000 {
138	138	compatible = "ti,k2g-sci";
139	139	ti,host-id = <12>;
140	140	mbox-names = "rx", "tx";
@@ -148,7 +148,7 @@ · 7 unmodified lines
148	148	#power-domain-cells = <2>;
149	149	};
150	150
151		− k3_clks: clocks {
	151	+ k3_clks: clock-controller {
152	152	compatible = "ti,k2g-sci-clk";
153	153	#clock-cells = <2>;
154	154	};
@@ -373,8 +373,9 @@ · 218 unmodified lines
373	373	clocks = <&k3_clks 145 0>;
374	374	};
375	375
376		− main_gpio_intr: interrupt-controller0 {
	376	+ main_gpio_intr: interrupt-controller@a00000 {
377	377	compatible = "ti,sci-intr";
	378	+ reg = <0x00 0x00a00000 0x00 0x800>;
378	379	ti,intr-trigger-type = <1>;
379	380	interrupt-controller;
380	381	interrupt-parent = <&gic500>;

arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi+2−1

@@ -74,8 +74,9 @@ · 73 unmodified lines
74	74	clocks = <&k3_clks 148 0>;
75	75	};
76	76
77		− mcu_gpio_intr: interrupt-controller1 {
	77	+ mcu_gpio_intr: interrupt-controller@4210000 {
78	78	compatible = "ti,sci-intr";
	79	+ reg = <0x00 0x04210000 0x00 0x200>;
79	80	ti,intr-trigger-type = <1>;
80	81	interrupt-controller;
81	82	interrupt-parent = <&gic500>;

arch/arm64/boot/dts/ti/k3-am65-main.dtsi+6−4

@@ -433,8 +433,9 @@ · 432 unmodified lines
433	433	#phy-cells = <0>;
434	434	};
435	435
436		− intr_main_gpio: interrupt-controller0 {
	436	+ intr_main_gpio: interrupt-controller@a00000 {
437	437	compatible = "ti,sci-intr";
	438	+ reg = <0x0 0x00a00000 0x0 0x400>;
438	439	ti,intr-trigger-type = <1>;
439	440	interrupt-controller;
440	441	interrupt-parent = <&gic500>;
@@ -444,18 +445,19 @@ · 3 unmodified lines
444	445	ti,interrupt-ranges = <0 392 32>;
445	446	};
446	447
447		− main-navss {
	448	+ main_navss: bus@30800000 {
448	449	compatible = "simple-mfd";
449	450	#address-cells = <2>;
450	451	#size-cells = <2>;
451		− ranges;
	452	+ ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0xbc00000>;
452	453	dma-coherent;
453	454	dma-ranges;
454	455
455	456	ti,sci-dev-id = <118>;
456	457
457		− intr_main_navss: interrupt-controller1 {
	458	+ intr_main_navss: interrupt-controller@310e0000 {
458	459	compatible = "ti,sci-intr";
	460	+ reg = <0x0 0x310e0000 0x0 0x2000>;
459	461	ti,intr-trigger-type = <4>;
460	462	interrupt-controller;
461	463	interrupt-parent = <&gic500>;

arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi+2−2

@@ -116,11 +116,11 @@ · 115 unmodified lines
116	116	};
117	117	};
118	118
119		− mcu-navss {
	119	+ mcu_navss: bus@28380000 {
120	120	compatible = "simple-mfd";
121	121	#address-cells = <2>;
122	122	#size-cells = <2>;
123		− ranges;
	123	+ ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
124	124	dma-coherent;
125	125	dma-ranges;
126	126

arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi+7−6

@@ -6,24 +6,24 @@ · 5 unmodified lines
6	6	*/
7	7
8	8	&cbass_wakeup {
9		− dmsc: dmsc {
	9	+ dmsc: system-controller@44083000 {
10	10	compatible = "ti,am654-sci";
11	11	ti,host-id = <12>;
12		− #address-cells = <1>;
13		− #size-cells = <1>;
14		− ranges;
15	12
16	13	mbox-names = "rx", "tx";
17	14
18	15	mboxes= <&secure_proxy_main 11>,
19	16	<&secure_proxy_main 13>;
20	17
	18	+ reg-names = "debug_messages";
	19	+ reg = <0x44083000 0x1000>;
	20	+
21	21	k3_pds: power-controller {
22	22	compatible = "ti,sci-pm-domain";
23	23	#power-domain-cells = <2>;
24	24	};
25	25
26		− k3_clks: clocks {
	26	+ k3_clks: clock-controller {
27	27	compatible = "ti,k2g-sci-clk";
28	28	#clock-cells = <2>;
29	29	};
@@ -69,8 +69,9 @@ · 39 unmodified lines
69	69	power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>;
70	70	};
71	71
72		− intr_wkup_gpio: interrupt-controller2 {
	72	+ intr_wkup_gpio: interrupt-controller@42200000 {
73	73	compatible = "ti,sci-intr";
	74	+ reg = <0x42200000 0x200>;
74	75	ti,intr-trigger-type = <1>;
75	76	interrupt-controller;
76	77	interrupt-parent = <&gic500>;

arch/arm64/boot/dts/ti/k3-am654-base-board.dts+0−31

@@ -85,12 +85,6 @@ · 84 unmodified lines
85	85	gpios = <&wkup_gpio0 27 GPIO_ACTIVE_LOW>;
86	86	};
87	87	};
88		−
89		− clk_ov5640_fixed: clock {
90		− compatible = "fixed-clock";
91		− #clock-cells = <0>;
92		− clock-frequency = <24000000>;
93		− };
94	88	};
95	89
96	90	&wkup_pmx0 {
@@ -287,23 +281,6 @@ · 190 unmodified lines
287	281	pinctrl-names = "default";
288	282	pinctrl-0 = <&main_i2c1_pins_default>;
289	283	clock-frequency = <400000>;
290		−
291		− ov5640: camera@3c {
292		− compatible = "ovti,ov5640";
293		− reg = <0x3c>;
294		−
295		− clocks = <&clk_ov5640_fixed>;
296		− clock-names = "xclk";
297		−
298		− port {
299		− csi2_cam0: endpoint {
300		− remote-endpoint = <&csi2_phy0>;
301		− clock-lanes = <0>;
302		− data-lanes = <1 2>;
303		− };
304		− };
305		− };
306		−
307	284	};
308	285
309	286	&main_i2c2 {
@@ -496,14 +473,6 @@ · 186 unmodified lines
496	473	};
497	474	};
498	475
499		−&csi2_0 {
500		− csi2_phy0: endpoint {
501		− remote-endpoint = <&csi2_cam0>;
502		− clock-lanes = <0>;
503		− data-lanes = <1 2>;
504		− };
505		−};
506		−
507	476	&mcu_cpsw {
508	477	pinctrl-names = "default";
509	478	pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;

arch/arm64/boot/dts/ti/k3-j7200-main.dtsi+6−2

@@ -68,8 +68,9 @@ · 67 unmodified lines
68	68	};
69	69	};
70	70
71		− main_gpio_intr: interrupt-controller0 {
	71	+ main_gpio_intr: interrupt-controller@a00000 {
72	72	compatible = "ti,sci-intr";
	73	+ reg = <0x00 0x00a00000 0x00 0x800>;
73	74	ti,intr-trigger-type = <1>;
74	75	interrupt-controller;
75	76	interrupt-parent = <&gic500>;
@@ -85,9 +86,12 @@ · 9 unmodified lines
85	86	#size-cells = <2>;
86	87	ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
87	88	ti,sci-dev-id = <199>;
	89	+ dma-coherent;
	90	+ dma-ranges;
88	91
89		− main_navss_intr: interrupt-controller1 {
	92	+ main_navss_intr: interrupt-controller@310e0000 {
90	93	compatible = "ti,sci-intr";
	94	+ reg = <0x00 0x310e0000 0x00 0x4000>;
91	95	ti,intr-trigger-type = <4>;
92	96	interrupt-controller;
93	97	interrupt-parent = <&gic500>;

arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi+4−3

@@ -6,7 +6,7 @@ · 5 unmodified lines
6	6	*/
7	7
8	8	&cbass_mcu_wakeup {
9		− dmsc: dmsc@44083000 {
	9	+ dmsc: system-controller@44083000 {
10	10	compatible = "ti,k2g-sci";
11	11	ti,host-id = <12>;
12	12
@@ -23,7 +23,7 @@ · 10 unmodified lines
23	23	#power-domain-cells = <2>;
24	24	};
25	25
26		− k3_clks: clocks {
	26	+ k3_clks: clock-controller {
27	27	compatible = "ti,k2g-sci-clk";
28	28	#clock-cells = <2>;
29	29	};
@@ -96,8 +96,9 @@ · 66 unmodified lines
96	96	clock-names = "fclk";
97	97	};
98	98
99		− wkup_gpio_intr: interrupt-controller2 {
	99	+ wkup_gpio_intr: interrupt-controller@42200000 {
100	100	compatible = "ti,sci-intr";
	101	+ reg = <0x00 0x42200000 0x00 0x400>;
101	102	ti,intr-trigger-type = <1>;
102	103	interrupt-controller;
103	104	interrupt-parent = <&gic500>;

arch/arm64/boot/dts/ti/k3-j721e-main.dtsi+6−4

@@ -76,8 +76,9 @@ · 75 unmodified lines
76	76	};
77	77	};
78	78
79		− main_gpio_intr: interrupt-controller0 {
	79	+ main_gpio_intr: interrupt-controller@a00000 {
80	80	compatible = "ti,sci-intr";
	81	+ reg = <0x00 0x00a00000 0x00 0x800>;
81	82	ti,intr-trigger-type = <1>;
82	83	interrupt-controller;
83	84	interrupt-parent = <&gic500>;
@@ -87,18 +88,19 @@ · 3 unmodified lines
87	88	ti,interrupt-ranges = <8 392 56>;
88	89	};
89	90
90		− main-navss {
	91	+ main_navss: bus@30000000 {
91	92	compatible = "simple-mfd";
92	93	#address-cells = <2>;
93	94	#size-cells = <2>;
94		− ranges;
	95	+ ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
95	96	dma-coherent;
96	97	dma-ranges;
97	98
98	99	ti,sci-dev-id = <199>;
99	100
100		− main_navss_intr: interrupt-controller1 {
	101	+ main_navss_intr: interrupt-controller@310e0000 {
101	102	compatible = "ti,sci-intr";
	103	+ reg = <0x0 0x310e0000 0x0 0x4000>;
102	104	ti,intr-trigger-type = <4>;
103	105	interrupt-controller;
104	106	interrupt-parent = <&gic500>;

arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi+6−5

@@ -6,7 +6,7 @@ · 5 unmodified lines
6	6	*/
7	7
8	8	&cbass_mcu_wakeup {
9		− dmsc: dmsc@44083000 {
	9	+ dmsc: system-controller@44083000 {
10	10	compatible = "ti,k2g-sci";
11	11	ti,host-id = <12>;
12	12
@@ -23,7 +23,7 @@ · 10 unmodified lines
23	23	#power-domain-cells = <2>;
24	24	};
25	25
26		− k3_clks: clocks {
	26	+ k3_clks: clock-controller {
27	27	compatible = "ti,k2g-sci-clk";
28	28	#clock-cells = <2>;
29	29	};
@@ -96,8 +96,9 @@ · 66 unmodified lines
96	96	clock-names = "fclk";
97	97	};
98	98
99		− wkup_gpio_intr: interrupt-controller2 {
	99	+ wkup_gpio_intr: interrupt-controller@42200000 {
100	100	compatible = "ti,sci-intr";
	101	+ reg = <0x00 0x42200000 0x00 0x400>;
101	102	ti,intr-trigger-type = <1>;
102	103	interrupt-controller;
103	104	interrupt-parent = <&gic500>;
@@ -249,11 +250,11 @@ · 145 unmodified lines
249	250	};
250	251	};
251	252
252		− mcu-navss {
	253	+ mcu_navss: bus@28380000 {
253	254	compatible = "simple-mfd";
254	255	#address-cells = <2>;
255	256	#size-cells = <2>;
256		− ranges;
	257	+ ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
257	258	dma-coherent;
258	259	dma-ranges;
259	260

arch/arm64/include/asm/Kbuild+2−0

@@ -5,3 +5,5 @@ generic-y += qrwlock.h · 4 unmodified lines
5	5	generic-y += qspinlock.h
6	6	generic-y += set_memory.h
7	7	generic-y += user.h
	8	+
	9	+generated-y += cpucaps.h

arch/arm64/include/asm/barrier.h+1−1

@@ -74,7 +74,7 @@ static inline unsigned long array_index_mask_nospec(unsigned long idx, · 73 unmodified lines
74	74	* This insanity brought to you by speculative system register reads,
75	75	* out-of-order memory accesses, sequence locks and Thomas Gleixner.
76	76	*
77		− * http://lists.infradead.org/pipermail/linux-arm-kernel/2019-February/631195.html
	77	+ * https://lore.kernel.org/r/alpine.DEB.2.21.1902081950260.1662@nanos.tec.linutronix.de/
78	78	*/
79	79	#define arch_counter_enforce_ordering(val) do { \
80	80	u64 tmp, _val = (val); \

arch/arm64/include/asm/cpucaps.h+0−74

@@ -1,74 +0,0 @@
1		−/* SPDX-License-Identifier: GPL-2.0-only */
2		−/*
3		− * arch/arm64/include/asm/cpucaps.h
4		− *
5		− * Copyright (C) 2016 ARM Ltd.
6		− */
7		−#ifndef __ASM_CPUCAPS_H
8		−#define __ASM_CPUCAPS_H
9		−
10		−#define ARM64_WORKAROUND_CLEAN_CACHE 0
11		−#define ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE 1
12		−#define ARM64_WORKAROUND_845719 2
13		−#define ARM64_HAS_SYSREG_GIC_CPUIF 3
14		−#define ARM64_HAS_PAN 4
15		−#define ARM64_HAS_LSE_ATOMICS 5
16		−#define ARM64_WORKAROUND_CAVIUM_23154 6
17		−#define ARM64_WORKAROUND_834220 7
18		−#define ARM64_HAS_NO_HW_PREFETCH 8
19		−#define ARM64_HAS_VIRT_HOST_EXTN 11
20		−#define ARM64_WORKAROUND_CAVIUM_27456 12
21		−#define ARM64_HAS_32BIT_EL0 13
22		−#define ARM64_SPECTRE_V3A 14
23		−#define ARM64_HAS_CNP 15
24		−#define ARM64_HAS_NO_FPSIMD 16
25		−#define ARM64_WORKAROUND_REPEAT_TLBI 17
26		−#define ARM64_WORKAROUND_QCOM_FALKOR_E1003 18
27		−#define ARM64_WORKAROUND_858921 19
28		−#define ARM64_WORKAROUND_CAVIUM_30115 20
29		−#define ARM64_HAS_DCPOP 21
30		−#define ARM64_SVE 22
31		−#define ARM64_UNMAP_KERNEL_AT_EL0 23
32		−#define ARM64_SPECTRE_V2 24
33		−#define ARM64_HAS_RAS_EXTN 25
34		−#define ARM64_WORKAROUND_843419 26
35		−#define ARM64_HAS_CACHE_IDC 27
36		−#define ARM64_HAS_CACHE_DIC 28
37		−#define ARM64_HW_DBM 29
38		−#define ARM64_SPECTRE_V4 30
39		−#define ARM64_MISMATCHED_CACHE_TYPE 31
40		−#define ARM64_HAS_STAGE2_FWB 32
41		−#define ARM64_HAS_CRC32 33
42		−#define ARM64_SSBS 34
43		−#define ARM64_WORKAROUND_1418040 35
44		−#define ARM64_HAS_SB 36
45		−#define ARM64_WORKAROUND_SPECULATIVE_AT 37
46		−#define ARM64_HAS_ADDRESS_AUTH_ARCH 38
47		−#define ARM64_HAS_ADDRESS_AUTH_IMP_DEF 39
48		−#define ARM64_HAS_GENERIC_AUTH_ARCH 40
49		−#define ARM64_HAS_GENERIC_AUTH_IMP_DEF 41
50		−#define ARM64_HAS_IRQ_PRIO_MASKING 42
51		−#define ARM64_HAS_DCPODP 43
52		−#define ARM64_WORKAROUND_1463225 44
53		−#define ARM64_WORKAROUND_CAVIUM_TX2_219_TVM 45
54		−#define ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM 46
55		−#define ARM64_WORKAROUND_1542419 47
56		−#define ARM64_HAS_E0PD 48
57		−#define ARM64_HAS_RNG 49
58		−#define ARM64_HAS_AMU_EXTN 50
59		−#define ARM64_HAS_ADDRESS_AUTH 51
60		−#define ARM64_HAS_GENERIC_AUTH 52
61		−#define ARM64_HAS_32BIT_EL1 53
62		−#define ARM64_BTI 54
63		−#define ARM64_HAS_ARMv8_4_TTL 55
64		−#define ARM64_HAS_TLB_RANGE 56
65		−#define ARM64_MTE 57
66		−#define ARM64_WORKAROUND_1508412 58
67		−#define ARM64_HAS_LDAPR 59
68		−#define ARM64_KVM_PROTECTED_MODE 60
69		−#define ARM64_WORKAROUND_NVIDIA_CARMEL_CNP 61
70		−#define ARM64_HAS_EPAN 62
71		−
72		−#define ARM64_NCAPS 63
73		−
74		−#endif /* __ASM_CPUCAPS_H */

arch/arm64/include/asm/kvm_asm.h+3−0

@@ -63,6 +63,7 @@ · 62 unmodified lines
63	63	#define __KVM_HOST_SMCCC_FUNC___pkvm_cpu_set_vector 18
64	64	#define __KVM_HOST_SMCCC_FUNC___pkvm_prot_finalize 19
65	65	#define __KVM_HOST_SMCCC_FUNC___pkvm_mark_hyp 20
	66	+#define __KVM_HOST_SMCCC_FUNC___kvm_adjust_pc 21
66	67
67	68	#ifndef __ASSEMBLY__
68	69
@@ -201,6 +202,8 @@ extern void __kvm_timer_set_cntvoff(u64 cntvoff); · 132 unmodified lines
201	202
202	203	extern int __kvm_vcpu_run(struct kvm_vcpu *vcpu);
203	204
	205	+extern void __kvm_adjust_pc(struct kvm_vcpu *vcpu);
	206	+
204	207	extern u64 __vgic_v3_get_gic_config(void);
205	208	extern u64 __vgic_v3_read_vmcr(void);
206	209	extern void __vgic_v3_write_vmcr(u32 vmcr);

arch/arm64/include/asm/kvm_emulate.h+5−0

@@ -463,4 +463,9 @@ static __always_inline void kvm_incr_pc(struct kvm_vcpu *vcpu) · 462 unmodified lines
463	463	vcpu->arch.flags \|= KVM_ARM64_INCREMENT_PC;
464	464	}
465	465
	466	+static inline bool vcpu_has_feature(struct kvm_vcpu *vcpu, int feature)
	467	+{
	468	+ return test_bit(feature, vcpu->arch.features);
	469	+}
	470	+
466	471	#endif /* __ARM64_KVM_EMULATE_H__ */

arch/arm64/include/asm/unistd32.h+1−2

@@ -893,8 +893,7 @@ __SYSCALL(__NR_process_madvise, sys_process_madvise) · 892 unmodified lines
893	893	__SYSCALL(__NR_epoll_pwait2, compat_sys_epoll_pwait2)
894	894	#define __NR_mount_setattr 442
895	895	__SYSCALL(__NR_mount_setattr, sys_mount_setattr)
896		−#define __NR_quotactl_path 443
897		−__SYSCALL(__NR_quotactl_path, sys_quotactl_path)
	896	+/* 443 is reserved for quotactl_path */
898	897	#define __NR_landlock_create_ruleset 444
899	898	__SYSCALL(__NR_landlock_create_ruleset, sys_landlock_create_ruleset)
900	899	#define __NR_landlock_add_rule 445

arch/arm64/kvm/arm.c+17−3

@@ -720,11 +720,13 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) · 719 unmodified lines
720	720	return ret;
721	721	}
722	722
723		− if (run->immediate_exit)
724		− return -EINTR;
725		−
726	723	vcpu_load(vcpu);
727	724
	725	+ if (run->immediate_exit) {
	726	+ ret = -EINTR;
	727	+ goto out;
	728	+ }
	729	+
728	730	kvm_sigset_activate(vcpu);
729	731
730	732	ret = 1;
@@ -897,6 +899,18 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) · 166 unmodified lines
897	899
898	900	kvm_sigset_deactivate(vcpu);
899	901
	902	+out:
	903	+ /*
	904	+ * In the unlikely event that we are returning to userspace
	905	+ * with pending exceptions or PC adjustment, commit these
	906	+ * adjustments in order to give userspace a consistent view of
	907	+ * the vcpu state. Note that this relies on __kvm_adjust_pc()
	908	+ * being preempt-safe on VHE.
	909	+ */
	910	+ if (unlikely(vcpu->arch.flags & (KVM_ARM64_PENDING_EXCEPTION \|
	911	+ KVM_ARM64_INCREMENT_PC)))
	912	+ kvm_call_hyp(__kvm_adjust_pc, vcpu);
	913	+
900	914	vcpu_put(vcpu);
901	915	return ret;
902	916	}

arch/arm64/kvm/hyp/exception.c+17−1

@@ -296,7 +296,7 @@ static void enter_exception32(struct kvm_vcpu *vcpu, u32 mode, u32 vect_offset) · 295 unmodified lines
296	296	*vcpu_pc(vcpu) = vect_offset;
297	297	}
298	298
299		−void kvm_inject_exception(struct kvm_vcpu *vcpu)
	299	+static void kvm_inject_exception(struct kvm_vcpu *vcpu)
300	300	{
301	301	if (vcpu_el1_is_32bit(vcpu)) {
302	302	switch (vcpu->arch.flags & KVM_ARM64_EXCEPT_MASK) {
@@ -329,3 +329,19 @@ void kvm_inject_exception(struct kvm_vcpu *vcpu) · 26 unmodified lines
329	329	}
330	330	}
331	331	}
	332	+
	333	+/*
	334	+ * Adjust the guest PC (and potentially exception state) depending on
	335	+ * flags provided by the emulation code.
	336	+ */
	337	+void __kvm_adjust_pc(struct kvm_vcpu *vcpu)
	338	+{
	339	+ if (vcpu->arch.flags & KVM_ARM64_PENDING_EXCEPTION) {
	340	+ kvm_inject_exception(vcpu);
	341	+ vcpu->arch.flags &= ~(KVM_ARM64_PENDING_EXCEPTION \|
	342	+ KVM_ARM64_EXCEPT_MASK);
	343	+ } else if (vcpu->arch.flags & KVM_ARM64_INCREMENT_PC) {
	344	+ kvm_skip_instr(vcpu);
	345	+ vcpu->arch.flags &= ~KVM_ARM64_INCREMENT_PC;
	346	+ }
	347	+}

arch/arm64/kvm/hyp/include/hyp/adjust_pc.h+0−18

@@ -13,8 +13,6 @@ · 12 unmodified lines
13	13	#include <asm/kvm_emulate.h>
14	14	#include <asm/kvm_host.h>
15	15
16		−void kvm_inject_exception(struct kvm_vcpu *vcpu);
17		−
18	16	static inline void kvm_skip_instr(struct kvm_vcpu *vcpu)
19	17	{
20	18	if (vcpu_mode_is_32bit(vcpu)) {
@@ -43,22 +41,6 @@ static inline void __kvm_skip_instr(struct kvm_vcpu *vcpu) · 22 unmodified lines
43	41	write_sysreg_el2(*vcpu_pc(vcpu), SYS_ELR);
44	42	}
45	43
46		−/*
47		− * Adjust the guest PC on entry, depending on flags provided by EL1
48		− * for the purpose of emulation (MMIO, sysreg) or exception injection.
49		− */
50		−static inline void __adjust_pc(struct kvm_vcpu *vcpu)
51		−{
52		− if (vcpu->arch.flags & KVM_ARM64_PENDING_EXCEPTION) {
53		− kvm_inject_exception(vcpu);
54		− vcpu->arch.flags &= ~(KVM_ARM64_PENDING_EXCEPTION \|
55		− KVM_ARM64_EXCEPT_MASK);
56		− } else if (vcpu->arch.flags & KVM_ARM64_INCREMENT_PC) {
57		− kvm_skip_instr(vcpu);
58		− vcpu->arch.flags &= ~KVM_ARM64_INCREMENT_PC;
59		− }
60		−}
61		−
62	44	/*
63	45	* Skip an instruction while host sysregs are live.
64	46	* Assumes host is always 64-bit.

arch/arm64/kvm/hyp/nvhe/hyp-main.c+8−0

@@ -28,6 +28,13 @@ static void handle___kvm_vcpu_run(struct kvm_cpu_context *host_ctxt) · 27 unmodified lines
28	28	cpu_reg(host_ctxt, 1) = __kvm_vcpu_run(kern_hyp_va(vcpu));
29	29	}
30	30
	31	+static void handle___kvm_adjust_pc(struct kvm_cpu_context *host_ctxt)
	32	+{
	33	+ DECLARE_REG(struct kvm_vcpu *, vcpu, host_ctxt, 1);
	34	+
	35	+ __kvm_adjust_pc(kern_hyp_va(vcpu));
	36	+}
	37	+
31	38	static void handle___kvm_flush_vm_context(struct kvm_cpu_context *host_ctxt)
32	39	{
33	40	__kvm_flush_vm_context();
@@ -170,6 +177,7 @@ typedef void (hcall_t)(struct kvm_cpu_context ); · 136 unmodified lines
170	177
171	178	static const hcall_t host_hcall[] = {
172	179	HANDLE_FUNC(__kvm_vcpu_run),
	180	+ HANDLE_FUNC(__kvm_adjust_pc),
173	181	HANDLE_FUNC(__kvm_flush_vm_context),
174	182	HANDLE_FUNC(__kvm_tlb_flush_vmid_ipa),
175	183	HANDLE_FUNC(__kvm_tlb_flush_vmid),

arch/arm64/kvm/hyp/nvhe/mem_protect.c+2−2

@@ -23,8 +23,8 @@ · 22 unmodified lines
23	23	extern unsigned long hyp_nr_cpus;
24	24	struct host_kvm host_kvm;
25	25
26		−struct hyp_pool host_s2_mem;
27		−struct hyp_pool host_s2_dev;
	26	+static struct hyp_pool host_s2_mem;
	27	+static struct hyp_pool host_s2_dev;
28	28
29	29	/*
30	30	* Copies of the host's CPU features registers holding sanitized values.

arch/arm64/kvm/hyp/nvhe/setup.c+1−1

@@ -17,7 +17,6 @@ · 16 unmodified lines
17	17	#include <nvhe/trap_handler.h>
18	18
19	19	struct hyp_pool hpool;
20		−struct kvm_pgtable_mm_ops pkvm_pgtable_mm_ops;
21	20	unsigned long hyp_nr_cpus;
22	21
23	22	#define hyp_percpu_size ((unsigned long)__per_cpu_end - \
@@ -27,6 +26,7 @@ static void *vmemmap_base; · 3 unmodified lines
27	26	static void *hyp_pgt_base;
28	27	static void *host_s2_mem_pgt_base;
29	28	static void *host_s2_dev_pgt_base;
	29	+static struct kvm_pgtable_mm_ops pkvm_pgtable_mm_ops;
30	30
31	31	static int divide_memory_pool(void *virt, unsigned long size)
32	32	{

arch/arm64/kvm/hyp/nvhe/switch.c+1−2

@@ -4,7 +4,6 @@ · 3 unmodified lines
4	4	* Author: Marc Zyngier <marc.zyngier@arm.com>
5	5	*/
6	6
7		−#include <hyp/adjust_pc.h>
8	7	#include <hyp/switch.h>
9	8	#include <hyp/sysreg-sr.h>
10	9
@@ -201,7 +200,7 @@ int __kvm_vcpu_run(struct kvm_vcpu *vcpu) · 190 unmodified lines
201	200	*/
202	201	__debug_save_host_buffers_nvhe(vcpu);
203	202
204		− __adjust_pc(vcpu);
	203	+ __kvm_adjust_pc(vcpu);
205	204
206	205	/*
207	206	* We must restore the 32-bit state before the sysregs, thanks

arch/arm64/kvm/hyp/vhe/switch.c+1−2

@@ -4,7 +4,6 @@ · 3 unmodified lines
4	4	* Author: Marc Zyngier <marc.zyngier@arm.com>
5	5	*/
6	6
7		−#include <hyp/adjust_pc.h>
8	7	#include <hyp/switch.h>
9	8
10	9	#include <linux/arm-smccc.h>
@@ -132,7 +131,7 @@ static int __kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu) · 121 unmodified lines
132	131	__load_guest_stage2(vcpu->arch.hw_mmu);
133	132	__activate_traps(vcpu);
134	133
135		− __adjust_pc(vcpu);
	134	+ __kvm_adjust_pc(vcpu);
136	135
137	136	sysreg_restore_guest_state_vhe(guest_ctxt);
138	137	__debug_switch_to_guest(vcpu);

arch/arm64/kvm/mmu.c+6−6

@@ -1156,13 +1156,13 @@ out_unlock: · 1155 unmodified lines
1156	1156	bool kvm_unmap_gfn_range(struct kvm kvm, struct kvm_gfn_range range)
1157	1157	{
1158	1158	if (!kvm->arch.mmu.pgt)
1159		− return 0;
	1159	+ return false;
1160	1160
1161	1161	__unmap_stage2_range(&kvm->arch.mmu, range->start << PAGE_SHIFT,
1162	1162	(range->end - range->start) << PAGE_SHIFT,
1163	1163	range->may_block);
1164	1164
1165		− return 0;
	1165	+ return false;
1166	1166	}
1167	1167
1168	1168	bool kvm_set_spte_gfn(struct kvm kvm, struct kvm_gfn_range range)
@@ -1170,7 +1170,7 @@ bool kvm_set_spte_gfn(struct kvm kvm, struct kvm_gfn_range range) · 1 unmodified line
1170	1170	kvm_pfn_t pfn = pte_pfn(range->pte);
1171	1171
1172	1172	if (!kvm->arch.mmu.pgt)
1173		− return 0;
	1173	+ return false;
1174	1174
1175	1175	WARN_ON(range->end - range->start != 1);
1176	1176
@@ -1190,7 +1190,7 @@ bool kvm_set_spte_gfn(struct kvm kvm, struct kvm_gfn_range range) · 13 unmodified lines
1190	1190	PAGE_SIZE, __pfn_to_phys(pfn),
1191	1191	KVM_PGTABLE_PROT_R, NULL);
1192	1192
1193		− return 0;
	1193	+ return false;
1194	1194	}
1195	1195
1196	1196	bool kvm_age_gfn(struct kvm kvm, struct kvm_gfn_range range)
@@ -1200,7 +1200,7 @@ bool kvm_age_gfn(struct kvm kvm, struct kvm_gfn_range range) · 3 unmodified lines
1200	1200	pte_t pte;
1201	1201
1202	1202	if (!kvm->arch.mmu.pgt)
1203		− return 0;
	1203	+ return false;
1204	1204
1205	1205	WARN_ON(size != PAGE_SIZE && size != PMD_SIZE && size != PUD_SIZE);
1206	1206
@@ -1213,7 +1213,7 @@ bool kvm_age_gfn(struct kvm kvm, struct kvm_gfn_range range) · 6 unmodified lines
1213	1213	bool kvm_test_age_gfn(struct kvm kvm, struct kvm_gfn_range range)
1214	1214	{
1215	1215	if (!kvm->arch.mmu.pgt)
1216		− return 0;
	1216	+ return false;
1217	1217
1218	1218	return kvm_pgtable_stage2_is_young(kvm->arch.mmu.pgt,
1219	1219	range->start << PAGE_SHIFT);

arch/arm64/kvm/reset.c+24−4

@@ -166,6 +166,25 @@ static int kvm_vcpu_enable_ptrauth(struct kvm_vcpu *vcpu) · 165 unmodified lines
166	166	return 0;
167	167	}
168	168
	169	+static bool vcpu_allowed_register_width(struct kvm_vcpu *vcpu)
	170	+{
	171	+ struct kvm_vcpu *tmp;
	172	+ bool is32bit;
	173	+ int i;
	174	+
	175	+ is32bit = vcpu_has_feature(vcpu, KVM_ARM_VCPU_EL1_32BIT);
	176	+ if (!cpus_have_const_cap(ARM64_HAS_32BIT_EL1) && is32bit)
	177	+ return false;
	178	+
	179	+ /* Check that the vcpus are either all 32bit or all 64bit */
	180	+ kvm_for_each_vcpu(i, tmp, vcpu->kvm) {
	181	+ if (vcpu_has_feature(tmp, KVM_ARM_VCPU_EL1_32BIT) != is32bit)
	182	+ return false;
	183	+ }
	184	+
	185	+ return true;
	186	+}
	187	+
169	188	/**
170	189	* kvm_reset_vcpu - sets core registers and sys_regs to reset value
171	190	* @vcpu: The VCPU pointer
@@ -217,13 +236,14 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu) · 45 unmodified lines
217	236	}
218	237	}
219	238
	239	+ if (!vcpu_allowed_register_width(vcpu)) {
	240	+ ret = -EINVAL;
	241	+ goto out;
	242	+ }
	243	+
220	244	switch (vcpu->arch.target) {
221	245	default:
222	246	if (test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features)) {
223		− if (!cpus_have_const_cap(ARM64_HAS_32BIT_EL1)) {
224		− ret = -EINVAL;
225		− goto out;
226		− }
227	247	pstate = VCPU_RESET_PSTATE_SVC;
228	248	} else {
229	249	pstate = VCPU_RESET_PSTATE_EL1;

arch/arm64/kvm/sys_regs.c+21−21

@@ -399,14 +399,14 @@ static bool trap_bvr(struct kvm_vcpu *vcpu, · 398 unmodified lines
399	399	struct sys_reg_params *p,
400	400	const struct sys_reg_desc *rd)
401	401	{
402		− u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
	402	+ u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm];
403	403
404	404	if (p->is_write)
405	405	reg_to_dbg(vcpu, p, rd, dbg_reg);
406	406	else
407	407	dbg_to_reg(vcpu, p, rd, dbg_reg);
408	408
409		− trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
	409	+ trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg);
410	410
411	411	return true;
412	412	}
@@ -414,7 +414,7 @@ static bool trap_bvr(struct kvm_vcpu *vcpu, · 1 unmodified line
414	414	static int set_bvr(struct kvm_vcpu vcpu, const struct sys_reg_desc rd,
415	415	const struct kvm_one_reg reg, void __user uaddr)
416	416	{
417		− __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
	417	+ __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm];
418	418
419	419	if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
420	420	return -EFAULT;
@@ -424,7 +424,7 @@ static int set_bvr(struct kvm_vcpu vcpu, const struct sys_reg_desc rd, · 3 unmodified lines
424	424	static int get_bvr(struct kvm_vcpu vcpu, const struct sys_reg_desc rd,
425	425	const struct kvm_one_reg reg, void __user uaddr)
426	426	{
427		− __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
	427	+ __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm];
428	428
429	429	if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
430	430	return -EFAULT;
@@ -434,21 +434,21 @@ static int get_bvr(struct kvm_vcpu vcpu, const struct sys_reg_desc rd, · 3 unmodified lines
434	434	static void reset_bvr(struct kvm_vcpu *vcpu,
435	435	const struct sys_reg_desc *rd)
436	436	{
437		− vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg] = rd->val;
	437	+ vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = rd->val;
438	438	}
439	439
440	440	static bool trap_bcr(struct kvm_vcpu *vcpu,
441	441	struct sys_reg_params *p,
442	442	const struct sys_reg_desc *rd)
443	443	{
444		− u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
	444	+ u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm];
445	445
446	446	if (p->is_write)
447	447	reg_to_dbg(vcpu, p, rd, dbg_reg);
448	448	else
449	449	dbg_to_reg(vcpu, p, rd, dbg_reg);
450	450
451		− trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
	451	+ trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg);
452	452
453	453	return true;
454	454	}
@@ -456,7 +456,7 @@ static bool trap_bcr(struct kvm_vcpu *vcpu, · 1 unmodified line
456	456	static int set_bcr(struct kvm_vcpu vcpu, const struct sys_reg_desc rd,
457	457	const struct kvm_one_reg reg, void __user uaddr)
458	458	{
459		− __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
	459	+ __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm];
460	460
461	461	if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
462	462	return -EFAULT;
@@ -467,7 +467,7 @@ static int set_bcr(struct kvm_vcpu vcpu, const struct sys_reg_desc rd, · 4 unmodified lines
467	467	static int get_bcr(struct kvm_vcpu vcpu, const struct sys_reg_desc rd,
468	468	const struct kvm_one_reg reg, void __user uaddr)
469	469	{
470		− __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
	470	+ __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm];
471	471
472	472	if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
473	473	return -EFAULT;
@@ -477,22 +477,22 @@ static int get_bcr(struct kvm_vcpu vcpu, const struct sys_reg_desc rd, · 3 unmodified lines
477	477	static void reset_bcr(struct kvm_vcpu *vcpu,
478	478	const struct sys_reg_desc *rd)
479	479	{
480		− vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg] = rd->val;
	480	+ vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = rd->val;
481	481	}
482	482
483	483	static bool trap_wvr(struct kvm_vcpu *vcpu,
484	484	struct sys_reg_params *p,
485	485	const struct sys_reg_desc *rd)
486	486	{
487		− u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
	487	+ u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm];
488	488
489	489	if (p->is_write)
490	490	reg_to_dbg(vcpu, p, rd, dbg_reg);
491	491	else
492	492	dbg_to_reg(vcpu, p, rd, dbg_reg);
493	493
494		− trace_trap_reg(__func__, rd->reg, p->is_write,
495		− vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]);
	494	+ trace_trap_reg(__func__, rd->CRm, p->is_write,
	495	+ vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]);
496	496
497	497	return true;
498	498	}
@@ -500,7 +500,7 @@ static bool trap_wvr(struct kvm_vcpu *vcpu, · 1 unmodified line
500	500	static int set_wvr(struct kvm_vcpu vcpu, const struct sys_reg_desc rd,
501	501	const struct kvm_one_reg reg, void __user uaddr)
502	502	{
503		− __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
	503	+ __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm];
504	504
505	505	if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
506	506	return -EFAULT;
@@ -510,7 +510,7 @@ static int set_wvr(struct kvm_vcpu vcpu, const struct sys_reg_desc rd, · 3 unmodified lines
510	510	static int get_wvr(struct kvm_vcpu vcpu, const struct sys_reg_desc rd,
511	511	const struct kvm_one_reg reg, void __user uaddr)
512	512	{
513		− __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
	513	+ __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm];
514	514
515	515	if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
516	516	return -EFAULT;
@@ -520,21 +520,21 @@ static int get_wvr(struct kvm_vcpu vcpu, const struct sys_reg_desc rd, · 3 unmodified lines
520	520	static void reset_wvr(struct kvm_vcpu *vcpu,
521	521	const struct sys_reg_desc *rd)
522	522	{
523		− vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg] = rd->val;
	523	+ vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = rd->val;
524	524	}
525	525
526	526	static bool trap_wcr(struct kvm_vcpu *vcpu,
527	527	struct sys_reg_params *p,
528	528	const struct sys_reg_desc *rd)
529	529	{
530		− u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
	530	+ u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm];
531	531
532	532	if (p->is_write)
533	533	reg_to_dbg(vcpu, p, rd, dbg_reg);
534	534	else
535	535	dbg_to_reg(vcpu, p, rd, dbg_reg);
536	536
537		− trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
	537	+ trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg);
538	538
539	539	return true;
540	540	}
@@ -542,7 +542,7 @@ static bool trap_wcr(struct kvm_vcpu *vcpu, · 1 unmodified line
542	542	static int set_wcr(struct kvm_vcpu vcpu, const struct sys_reg_desc rd,
543	543	const struct kvm_one_reg reg, void __user uaddr)
544	544	{
545		− __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
	545	+ __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm];
546	546
547	547	if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
548	548	return -EFAULT;
@@ -552,7 +552,7 @@ static int set_wcr(struct kvm_vcpu vcpu, const struct sys_reg_desc rd, · 3 unmodified lines
552	552	static int get_wcr(struct kvm_vcpu vcpu, const struct sys_reg_desc rd,
553	553	const struct kvm_one_reg reg, void __user uaddr)
554	554	{
555		− __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
	555	+ __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm];
556	556
557	557	if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
558	558	return -EFAULT;
@@ -562,7 +562,7 @@ static int get_wcr(struct kvm_vcpu vcpu, const struct sys_reg_desc rd, · 3 unmodified lines
562	562	static void reset_wcr(struct kvm_vcpu *vcpu,
563	563	const struct sys_reg_desc *rd)
564	564	{
565		− vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg] = rd->val;
	565	+ vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = rd->val;
566	566	}
567	567
568	568	static void reset_amair_el1(struct kvm_vcpu vcpu, const struct sys_reg_desc r)

arch/arm64/mm/flush.c+3−1

@@ -55,8 +55,10 @@ void __sync_icache_dcache(pte_t pte) · 54 unmodified lines
55	55	{
56	56	struct page *page = pte_page(pte);
57	57
58		− if (!test_and_set_bit(PG_dcache_clean, &page->flags))
	58	+ if (!test_bit(PG_dcache_clean, &page->flags)) {
59	59	sync_icache_aliases(page_address(page), page_size(page));
	60	+ set_bit(PG_dcache_clean, &page->flags);
	61	+ }
60	62	}
61	63	EXPORT_SYMBOL_GPL(__sync_icache_dcache);
62	64

arch/arm64/mm/init.c+2−1

@@ -43,6 +43,7 @@ · 42 unmodified lines
43	43	#include <linux/sizes.h>
44	44	#include <asm/tlb.h>
45	45	#include <asm/alternative.h>
	46	+#include <asm/xen/swiotlb-xen.h>
46	47
47	48	/*
48	49	* We need to be able to catch inadvertent references to memstart_addr
@@ -482,7 +483,7 @@ void __init mem_init(void) · 433 unmodified lines
482	483	if (swiotlb_force == SWIOTLB_FORCE \|\|
483	484	max_pfn > PFN_DOWN(arm64_dma_phys_limit))
484	485	swiotlb_init(1);
485		− else
	486	+ else if (!xen_swiotlb_detect())
486	487	swiotlb_force = SWIOTLB_NO_FORCE;
487	488
488	489	set_max_mapnr(max_pfn - PHYS_PFN_OFFSET);

arch/arm64/mm/mmu.c+2−1

@@ -515,7 +515,8 @@ static void __init map_mem(pgd_t *pgdp) · 514 unmodified lines
515	515	*/
516	516	BUILD_BUG_ON(pgd_index(direct_map_end - 1) == pgd_index(direct_map_end));
517	517
518		− if (rodata_full \|\| crash_mem_map \|\| debug_pagealloc_enabled())
	518	+ if (rodata_full \|\| crash_mem_map \|\| debug_pagealloc_enabled() \|\|
	519	+ IS_ENABLED(CONFIG_KFENCE))
519	520	flags \|= NO_BLOCK_MAPPINGS \| NO_CONT_MAPPINGS;
520	521
521	522	/*

arch/arm64/mm/proc.S+12−0

@@ -447,6 +447,18 @@ SYM_FUNC_START(__cpu_setup) · 446 unmodified lines
447	447	mov x10, #(SYS_GCR_EL1_RRND \| SYS_GCR_EL1_EXCL_MASK)
448	448	msr_s SYS_GCR_EL1, x10
449	449
	450	+ /*
	451	+ * If GCR_EL1.RRND=1 is implemented the same way as RRND=0, then
	452	+ * RGSR_EL1.SEED must be non-zero for IRG to produce
	453	+ * pseudorandom numbers. As RGSR_EL1 is UNKNOWN out of reset, we
	454	+ * must initialize it.
	455	+ */
	456	+ mrs x10, CNTVCT_EL0
	457	+ ands x10, x10, #SYS_RGSR_EL1_SEED_MASK
	458	+ csinc x10, x10, xzr, ne
	459	+ lsl x10, x10, #SYS_RGSR_EL1_SEED_SHIFT
	460	+ msr_s SYS_RGSR_EL1, x10
	461	+
450	462	/* clear any pending tag check faults in TFSR_EL1 /
451	463	msr_s SYS_TFSR_EL1, xzr
452	464	msr_s SYS_TFSRE0_EL1, xzr

arch/arm64/tools/Makefile+22−0

@@ -0,0 +1,22 @@
	1	+# SPDX-License-Identifier: GPL-2.0
	2	+
	3	+gen := arch/$(ARCH)/include/generated
	4	+kapi := $(gen)/asm
	5	+
	6	+kapi-hdrs-y := $(kapi)/cpucaps.h
	7	+
	8	+targets += $(addprefix ../../../,$(gen-y) $(kapi-hdrs-y))
	9	+
	10	+PHONY += kapi
	11	+
	12	+kapi: $(kapi-hdrs-y) $(gen-y)
	13	+
	14	+# Create output directory if not already present
	15	+_dummy := $(shell [ -d '$(kapi)' ] \|\| mkdir -p '$(kapi)')
	16	+
	17	+quiet_cmd_gen_cpucaps = GEN $@
	18	+ cmd_gen_cpucaps = mkdir -p $(dir $@) && \
	19	+ $(AWK) -f $(filter-out $(PHONY),$^) > $@
	20	+
	21	+$(kapi)/cpucaps.h: $(src)/gen-cpucaps.awk $(src)/cpucaps FORCE
	22	+ $(call if_changed,gen_cpucaps)

arch/arm64/tools/cpucaps+65−0

@@ -0,0 +1,65 @@
	1	+# SPDX-License-Identifier: GPL-2.0
	2	+#
	3	+# Internal CPU capabilities constants, keep this list sorted
	4	+
	5	+BTI
	6	+HAS_32BIT_EL0
	7	+HAS_32BIT_EL1
	8	+HAS_ADDRESS_AUTH
	9	+HAS_ADDRESS_AUTH_ARCH
	10	+HAS_ADDRESS_AUTH_IMP_DEF
	11	+HAS_AMU_EXTN
	12	+HAS_ARMv8_4_TTL
	13	+HAS_CACHE_DIC
	14	+HAS_CACHE_IDC
	15	+HAS_CNP
	16	+HAS_CRC32
	17	+HAS_DCPODP
	18	+HAS_DCPOP
	19	+HAS_E0PD
	20	+HAS_EPAN
	21	+HAS_GENERIC_AUTH
	22	+HAS_GENERIC_AUTH_ARCH
	23	+HAS_GENERIC_AUTH_IMP_DEF
	24	+HAS_IRQ_PRIO_MASKING
	25	+HAS_LDAPR
	26	+HAS_LSE_ATOMICS
	27	+HAS_NO_FPSIMD
	28	+HAS_NO_HW_PREFETCH
	29	+HAS_PAN
	30	+HAS_RAS_EXTN
	31	+HAS_RNG
	32	+HAS_SB
	33	+HAS_STAGE2_FWB
	34	+HAS_SYSREG_GIC_CPUIF
	35	+HAS_TLB_RANGE
	36	+HAS_VIRT_HOST_EXTN
	37	+HW_DBM
	38	+KVM_PROTECTED_MODE
	39	+MISMATCHED_CACHE_TYPE
	40	+MTE
	41	+SPECTRE_V2
	42	+SPECTRE_V3A
	43	+SPECTRE_V4
	44	+SSBS
	45	+SVE
	46	+UNMAP_KERNEL_AT_EL0
	47	+WORKAROUND_834220
	48	+WORKAROUND_843419
	49	+WORKAROUND_845719
	50	+WORKAROUND_858921
	51	+WORKAROUND_1418040
	52	+WORKAROUND_1463225
	53	+WORKAROUND_1508412
	54	+WORKAROUND_1542419
	55	+WORKAROUND_CAVIUM_23154
	56	+WORKAROUND_CAVIUM_27456
	57	+WORKAROUND_CAVIUM_30115
	58	+WORKAROUND_CAVIUM_TX2_219_PRFM
	59	+WORKAROUND_CAVIUM_TX2_219_TVM
	60	+WORKAROUND_CLEAN_CACHE
	61	+WORKAROUND_DEVICE_LOAD_ACQUIRE
	62	+WORKAROUND_NVIDIA_CARMEL_CNP
	63	+WORKAROUND_QCOM_FALKOR_E1003
	64	+WORKAROUND_REPEAT_TLBI
	65	+WORKAROUND_SPECULATIVE_AT

arch/arm64/tools/gen-cpucaps.awk+40−0

@@ -0,0 +1,40 @@
	1	+#!/bin/awk -f
	2	+# SPDX-License-Identifier: GPL-2.0
	3	+# gen-cpucaps.awk: arm64 cpucaps header generator
	4	+#
	5	+# Usage: awk -f gen-cpucaps.awk cpucaps.txt
	6	+
	7	+# Log an error and terminate
	8	+function fatal(msg) {
	9	+ print "Error at line " NR ": " msg > "/dev/stderr"
	10	+ exit 1
	11	+}
	12	+
	13	+# skip blank lines and comment lines
	14	+/^$/ { next }
	15	+/^#/ { next }
	16	+
	17	+BEGIN {
	18	+ print "#ifndef __ASM_CPUCAPS_H"
	19	+ print "#define __ASM_CPUCAPS_H"
	20	+ print ""
	21	+ print "/* Generated file - do not edit */"
	22	+ cap_num = 0
	23	+ print ""
	24	+}
	25	+
	26	+/^[vA-Z0-9_]+$/ {
	27	+ printf("#define ARM64_%-30s\t%d\n", $0, cap_num++)
	28	+ next
	29	+}
	30	+
	31	+END {
	32	+ printf("#define ARM64_NCAPS\t\t\t\t%d\n", cap_num)
	33	+ print ""
	34	+ print "#endif /* __ASM_CPUCAPS_H */"
	35	+}
	36	+
	37	+# Any lines not handled by previous rules are unexpected
	38	+{
	39	+ fatal("unhandled statement")
	40	+}

arch/ia64/kernel/syscalls/syscall.tbl+1−1

@@ -363,7 +363,7 @@ · 362 unmodified lines
363	363	440 common process_madvise sys_process_madvise
364	364	441 common epoll_pwait2 sys_epoll_pwait2
365	365	442 common mount_setattr sys_mount_setattr
366		−443 common quotactl_path sys_quotactl_path
	366	+# 443 reserved for quotactl_path
367	367	444 common landlock_create_ruleset sys_landlock_create_ruleset
368	368	445 common landlock_add_rule sys_landlock_add_rule
369	369	446 common landlock_restrict_self sys_landlock_restrict_self

arch/m68k/kernel/signal.c+2−1

@@ -623,7 +623,8 @@ static inline void siginfo_build_tests(void) · 622 unmodified lines
623	623	BUILD_BUG_ON(offsetof(siginfo_t, si_pkey) != 0x12);
624	624
625	625	/* _sigfault._perf */
626		− BUILD_BUG_ON(offsetof(siginfo_t, si_perf) != 0x10);
	626	+ BUILD_BUG_ON(offsetof(siginfo_t, si_perf_data) != 0x10);
	627	+ BUILD_BUG_ON(offsetof(siginfo_t, si_perf_type) != 0x14);
627	628
628	629	/* _sigpoll */
629	630	BUILD_BUG_ON(offsetof(siginfo_t, si_band) != 0x0c);

arch/m68k/kernel/syscalls/syscall.tbl+1−1

@@ -442,7 +442,7 @@ · 441 unmodified lines
442	442	440 common process_madvise sys_process_madvise
443	443	441 common epoll_pwait2 sys_epoll_pwait2
444	444	442 common mount_setattr sys_mount_setattr
445		−443 common quotactl_path sys_quotactl_path
	445	+# 443 reserved for quotactl_path
446	446	444 common landlock_create_ruleset sys_landlock_create_ruleset
447	447	445 common landlock_add_rule sys_landlock_add_rule
448	448	446 common landlock_restrict_self sys_landlock_restrict_self

arch/microblaze/kernel/syscalls/syscall.tbl+1−1

@@ -448,7 +448,7 @@ · 447 unmodified lines
448	448	440 common process_madvise sys_process_madvise
449	449	441 common epoll_pwait2 sys_epoll_pwait2
450	450	442 common mount_setattr sys_mount_setattr
451		−443 common quotactl_path sys_quotactl_path
	451	+# 443 reserved for quotactl_path
452	452	444 common landlock_create_ruleset sys_landlock_create_ruleset
453	453	445 common landlock_add_rule sys_landlock_add_rule
454	454	446 common landlock_restrict_self sys_landlock_restrict_self

arch/mips/alchemy/board-xxs1500.c+1−0

@@ -18,6 +18,7 @@ · 17 unmodified lines
18	18	#include <asm/reboot.h>
19	19	#include <asm/setup.h>
20	20	#include <asm/mach-au1x00/au1000.h>
	21	+#include <asm/mach-au1x00/gpio-au1000.h>
21	22	#include <prom.h>
22	23
23	24	const char *get_system_type(void)

arch/mips/include/asm/mips-boards/launch.h+5−0

@@ -3,6 +3,9 @@ · 2 unmodified lines
3	3	*
4	4	*/
5	5
	6	+#ifndef _ASM_MIPS_BOARDS_LAUNCH_H
	7	+#define _ASM_MIPS_BOARDS_LAUNCH_H
	8	+
6	9	#ifndef _ASSEMBLER_
7	10
8	11	struct cpulaunch {
@@ -34,3 +37,5 @@ struct cpulaunch { · 25 unmodified lines
34	37
35	38	/* Polling period in count cycles for secondary CPU's */
36	39	#define LAUNCHPERIOD 10000
	40	+
	41	+#endif /* _ASM_MIPS_BOARDS_LAUNCH_H */

arch/mips/kernel/syscalls/syscall_n32.tbl+1−1

@@ -381,7 +381,7 @@ · 380 unmodified lines
381	381	440 n32 process_madvise sys_process_madvise
382	382	441 n32 epoll_pwait2 compat_sys_epoll_pwait2
383	383	442 n32 mount_setattr sys_mount_setattr
384		−443 n32 quotactl_path sys_quotactl_path
	384	+# 443 reserved for quotactl_path
385	385	444 n32 landlock_create_ruleset sys_landlock_create_ruleset
386	386	445 n32 landlock_add_rule sys_landlock_add_rule
387	387	446 n32 landlock_restrict_self sys_landlock_restrict_self

arch/mips/kernel/syscalls/syscall_n64.tbl+1−1

@@ -357,7 +357,7 @@ · 356 unmodified lines
357	357	440 n64 process_madvise sys_process_madvise
358	358	441 n64 epoll_pwait2 sys_epoll_pwait2
359	359	442 n64 mount_setattr sys_mount_setattr
360		−443 n64 quotactl_path sys_quotactl_path
	360	+# 443 reserved for quotactl_path
361	361	444 n64 landlock_create_ruleset sys_landlock_create_ruleset
362	362	445 n64 landlock_add_rule sys_landlock_add_rule
363	363	446 n64 landlock_restrict_self sys_landlock_restrict_self

arch/mips/kernel/syscalls/syscall_o32.tbl+1−1

@@ -430,7 +430,7 @@ · 429 unmodified lines
430	430	440 o32 process_madvise sys_process_madvise
431	431	441 o32 epoll_pwait2 sys_epoll_pwait2 compat_sys_epoll_pwait2
432	432	442 o32 mount_setattr sys_mount_setattr
433		−443 o32 quotactl_path sys_quotactl_path
	433	+# 443 reserved for quotactl_path
434	434	444 o32 landlock_create_ruleset sys_landlock_create_ruleset
435	435	445 o32 landlock_add_rule sys_landlock_add_rule
436	436	446 o32 landlock_restrict_self sys_landlock_restrict_self

arch/mips/lib/mips-atomic.c+6−6

@@ -37,7 +37,7 @@ · 36 unmodified lines
37	37	*/
38	38	notrace void arch_local_irq_disable(void)
39	39	{
40		− preempt_disable();
	40	+ preempt_disable_notrace();
41	41
42	42	__asm__ __volatile__(
43	43	" .set push \n"
@@ -53,7 +53,7 @@ notrace void arch_local_irq_disable(void) · 9 unmodified lines
53	53	: /* no inputs */
54	54	: "memory");
55	55
56		− preempt_enable();
	56	+ preempt_enable_notrace();
57	57	}
58	58	EXPORT_SYMBOL(arch_local_irq_disable);
59	59
@@ -61,7 +61,7 @@ notrace unsigned long arch_local_irq_save(void) · 1 unmodified line
61	61	{
62	62	unsigned long flags;
63	63
64		− preempt_disable();
	64	+ preempt_disable_notrace();
65	65
66	66	__asm__ __volatile__(
67	67	" .set push \n"
@@ -78,7 +78,7 @@ notrace unsigned long arch_local_irq_save(void) · 10 unmodified lines
78	78	: /* no inputs */
79	79	: "memory");
80	80
81		− preempt_enable();
	81	+ preempt_enable_notrace();
82	82
83	83	return flags;
84	84	}
@@ -88,7 +88,7 @@ notrace void arch_local_irq_restore(unsigned long flags) · 3 unmodified lines
88	88	{
89	89	unsigned long __tmp1;
90	90
91		− preempt_disable();
	91	+ preempt_disable_notrace();
92	92
93	93	__asm__ __volatile__(
94	94	" .set push \n"
@@ -106,7 +106,7 @@ notrace void arch_local_irq_restore(unsigned long flags) · 11 unmodified lines
106	106	: "0" (flags)
107	107	: "memory");
108	108
109		− preempt_enable();
	109	+ preempt_enable_notrace();
110	110	}
111	111	EXPORT_SYMBOL(arch_local_irq_restore);
112	112

arch/mips/mm/cache.c+14−16

@@ -158,31 +158,29 @@ unsigned long _page_cachable_default; · 157 unmodified lines
158	158	EXPORT_SYMBOL(_page_cachable_default);
159	159
160	160	#define PM(p) __pgprot(_page_cachable_default \| (p))
161		−#define PVA(p) PM(_PAGE_VALID \| _PAGE_ACCESSED \| (p))
162	161
163	162	static inline void setup_protection_map(void)
164	163	{
165	164	protection_map[0] = PM(_PAGE_PRESENT \| _PAGE_NO_EXEC \| _PAGE_NO_READ);
166		− protection_map[1] = PVA(_PAGE_PRESENT \| _PAGE_NO_EXEC);
167		− protection_map[2] = PVA(_PAGE_PRESENT \| _PAGE_NO_EXEC \| _PAGE_NO_READ);
168		− protection_map[3] = PVA(_PAGE_PRESENT \| _PAGE_NO_EXEC);
169		− protection_map[4] = PVA(_PAGE_PRESENT);
170		− protection_map[5] = PVA(_PAGE_PRESENT);
171		− protection_map[6] = PVA(_PAGE_PRESENT);
172		− protection_map[7] = PVA(_PAGE_PRESENT);
	165	+ protection_map[1] = PM(_PAGE_PRESENT \| _PAGE_NO_EXEC);
	166	+ protection_map[2] = PM(_PAGE_PRESENT \| _PAGE_NO_EXEC \| _PAGE_NO_READ);
	167	+ protection_map[3] = PM(_PAGE_PRESENT \| _PAGE_NO_EXEC);
	168	+ protection_map[4] = PM(_PAGE_PRESENT);
	169	+ protection_map[5] = PM(_PAGE_PRESENT);
	170	+ protection_map[6] = PM(_PAGE_PRESENT);
	171	+ protection_map[7] = PM(_PAGE_PRESENT);
173	172
174	173	protection_map[8] = PM(_PAGE_PRESENT \| _PAGE_NO_EXEC \| _PAGE_NO_READ);
175		− protection_map[9] = PVA(_PAGE_PRESENT \| _PAGE_NO_EXEC);
176		− protection_map[10] = PVA(_PAGE_PRESENT \| _PAGE_NO_EXEC \| _PAGE_WRITE \|
	174	+ protection_map[9] = PM(_PAGE_PRESENT \| _PAGE_NO_EXEC);
	175	+ protection_map[10] = PM(_PAGE_PRESENT \| _PAGE_NO_EXEC \| _PAGE_WRITE \|
177	176	_PAGE_NO_READ);
178		− protection_map[11] = PVA(_PAGE_PRESENT \| _PAGE_NO_EXEC \| _PAGE_WRITE);
179		− protection_map[12] = PVA(_PAGE_PRESENT);
180		− protection_map[13] = PVA(_PAGE_PRESENT);
181		− protection_map[14] = PVA(_PAGE_PRESENT);
182		− protection_map[15] = PVA(_PAGE_PRESENT);
	177	+ protection_map[11] = PM(_PAGE_PRESENT \| _PAGE_NO_EXEC \| _PAGE_WRITE);
	178	+ protection_map[12] = PM(_PAGE_PRESENT);
	179	+ protection_map[13] = PM(_PAGE_PRESENT);
	180	+ protection_map[14] = PM(_PAGE_PRESENT \| _PAGE_WRITE);
	181	+ protection_map[15] = PM(_PAGE_PRESENT \| _PAGE_WRITE);
183	182	}
184	183
185		−#undef _PVA
186	184	#undef PM
187	185
188	186	void cpu_cache_init(void)

arch/mips/ralink/of.c+2−0

@@ -8,6 +8,7 @@ · 7 unmodified lines
8	8
9	9	#include <linux/io.h>
10	10	#include <linux/clk.h>
	11	+#include <linux/export.h>
11	12	#include <linux/init.h>
12	13	#include <linux/sizes.h>
13	14	#include <linux/of_fdt.h>
@@ -25,6 +26,7 @@ · 11 unmodified lines
25	26
26	27	__iomem void *rt_sysc_membase;
27	28	__iomem void *rt_memc_membase;
	29	+EXPORT_SYMBOL_GPL(rt_sysc_membase);
28	30
29	31	__iomem void plat_of_remap_node(const char node)
30	32	{

arch/openrisc/include/asm/barrier.h+9−0

@@ -0,0 +1,9 @@
	1	+/* SPDX-License-Identifier: GPL-2.0 */
	2	+#ifndef __ASM_BARRIER_H
	3	+#define __ASM_BARRIER_H
	4	+
	5	+#define mb() asm volatile ("l.msync" ::: "memory")
	6	+
	7	+#include <asm-generic/barrier.h>
	8	+
	9	+#endif /* __ASM_BARRIER_H */

arch/openrisc/kernel/setup.c+2−0

@@ -278,6 +278,8 @@ void calibrate_delay(void) · 277 unmodified lines
278	278	pr_cont("%lu.%02lu BogoMIPS (lpj=%lu)\n",
279	279	loops_per_jiffy / (500000 / HZ),
280	280	(loops_per_jiffy / (5000 / HZ)) % 100, loops_per_jiffy);
	281	+
	282	+ of_node_put(cpu);
281	283	}
282	284
283	285	void __init setup_arch(char **cmdline_p)

arch/openrisc/mm/init.c+1−5

@@ -75,7 +75,6 @@ static void __init map_ram(void) · 74 unmodified lines
75	75	/* These mark extents of read-only kernel pages...
76	76	* ...from vmlinux.lds.S
77	77	*/
78		− struct memblock_region *region;
79	78
80	79	v = PAGE_OFFSET;
81	80
@@ -121,7 +120,7 @@ static void __init map_ram(void) · 39 unmodified lines
121	120	}
122	121
123	122	printk(KERN_INFO "%s: Memory: 0x%x-0x%x\n", __func__,
124		− region->base, region->base + region->size);
	123	+ start, end);
125	124	}
126	125	}
127	126
@@ -129,7 +128,6 @@ void __init paging_init(void) · 1 unmodified line
129	128	{
130	129	extern void tlb_init(void);
131	130
132		− unsigned long end;
133	131	int i;
134	132
135	133	printk(KERN_INFO "Setting up paging and PTEs.\n");
@@ -145,8 +143,6 @@ void __init paging_init(void) · 9 unmodified lines
145	143	*/
146	144	current_pgd[smp_processor_id()] = init_mm.pgd;
147	145
148		− end = (unsigned long)__va(max_low_pfn * PAGE_SIZE);
149		−
150	146	map_ram();
151	147
152	148	zone_sizes_init();

arch/parisc/kernel/syscalls/syscall.tbl+1−1

@@ -440,7 +440,7 @@ · 439 unmodified lines
440	440	440 common process_madvise sys_process_madvise
441	441	441 common epoll_pwait2 sys_epoll_pwait2 compat_sys_epoll_pwait2
442	442	442 common mount_setattr sys_mount_setattr
443		−443 common quotactl_path sys_quotactl_path
	443	+# 443 reserved for quotactl_path
444	444	444 common landlock_create_ruleset sys_landlock_create_ruleset
445	445	445 common landlock_add_rule sys_landlock_add_rule
446	446	446 common landlock_restrict_self sys_landlock_restrict_self

arch/powerpc/boot/dts/fsl/p1010si-post.dtsi+8−0

@@ -122,7 +122,15 @@ · 121 unmodified lines
122	122	};
123	123
124	124	/include/ "pq3-i2c-0.dtsi"
	125	+ i2c@3000 {
	126	+ fsl,i2c-erratum-a004447;
	127	+ };
	128	+
125	129	/include/ "pq3-i2c-1.dtsi"
	130	+ i2c@3100 {
	131	+ fsl,i2c-erratum-a004447;
	132	+ };
	133	+
126	134	/include/ "pq3-duart-0.dtsi"
127	135	/include/ "pq3-espi-0.dtsi"
128	136	spi0: spi@7000 {

arch/powerpc/boot/dts/fsl/p2041si-post.dtsi+16−0

@@ -371,7 +371,23 @@ · 370 unmodified lines
371	371	};
372	372
373	373	/include/ "qoriq-i2c-0.dtsi"
	374	+ i2c@118000 {
	375	+ fsl,i2c-erratum-a004447;
	376	+ };
	377	+
	378	+ i2c@118100 {
	379	+ fsl,i2c-erratum-a004447;
	380	+ };
	381	+
374	382	/include/ "qoriq-i2c-1.dtsi"
	383	+ i2c@119000 {
	384	+ fsl,i2c-erratum-a004447;
	385	+ };
	386	+
	387	+ i2c@119100 {
	388	+ fsl,i2c-erratum-a004447;
	389	+ };
	390	+
375	391	/include/ "qoriq-duart-0.dtsi"
376	392	/include/ "qoriq-duart-1.dtsi"
377	393	/include/ "qoriq-gpio-0.dtsi"

arch/powerpc/include/asm/hvcall.h+3−0

@@ -448,6 +448,9 @@ · 447 unmodified lines
448	448	*/
449	449	long plpar_hcall_norets(unsigned long opcode, ...);
450	450
	451	+/* Variant which does not do hcall tracing */
	452	+long plpar_hcall_norets_notrace(unsigned long opcode, ...);
	453	+
451	454	/**
452	455	* plpar_hcall: - Make a pseries hypervisor call
453	456	* @opcode: The hypervisor call to make.

arch/powerpc/include/asm/interrupt.h+7−2

@@ -153,8 +153,6 @@ static inline void interrupt_enter_prepare(struct pt_regs *regs, struct interrup · 152 unmodified lines
153	153	*/
154	154	static inline void interrupt_exit_prepare(struct pt_regs regs, struct interrupt_state state)
155	155	{
156		− if (user_mode(regs))
157		− kuep_unlock();
158	156	}
159	157
160	158	static inline void interrupt_async_enter_prepare(struct pt_regs regs, struct interrupt_state state)
@@ -222,6 +220,13 @@ static inline void interrupt_nmi_enter_prepare(struct pt_regs *regs, struct inte · 61 unmodified lines
222	220	local_paca->irq_soft_mask = IRQS_ALL_DISABLED;
223	221	local_paca->irq_happened \|= PACA_IRQ_HARD_DIS;
224	222
	223	+ if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) && !(regs->msr & MSR_PR) &&
	224	+ regs->nip < (unsigned long)__end_interrupts) {
	225	+ // Kernel code running below __end_interrupts is
	226	+ // implicitly soft-masked.
	227	+ regs->softe = IRQS_ALL_DISABLED;
	228	+ }
	229	+
225	230	/* Don't do any per-CPU operations until interrupt state is fixed */
226	231
227	232	if (nmi_disables_ftrace(regs)) {

arch/powerpc/include/asm/jump_label.h+1−1

@@ -50,7 +50,7 @@ l_yes: · 49 unmodified lines
50	50	1098: nop; \
51	51	.pushsection __jump_table, "aw"; \
52	52	.long 1098b - ., LABEL - .; \
53		− FTR_ENTRY_LONG KEY; \
	53	+ FTR_ENTRY_LONG KEY - .; \
54	54	.popsection
55	55	#endif
56	56

arch/powerpc/include/asm/kvm_host.h+1−0

@@ -51,6 +51,7 @@ · 50 unmodified lines
51	51	/* PPC-specific vcpu->requests bit members */
52	52	#define KVM_REQ_WATCHDOG KVM_ARCH_REQ(0)
53	53	#define KVM_REQ_EPR_EXIT KVM_ARCH_REQ(1)
	54	+#define KVM_REQ_PENDING_TIMER KVM_ARCH_REQ(2)
54	55
55	56	#include <linux/mmu_notifier.h>
56	57

arch/powerpc/include/asm/paravirt.h+19−3

@@ -28,19 +28,35 @@ static inline u32 yield_count_of(int cpu) · 27 unmodified lines
28	28	return be32_to_cpu(yield_count);
29	29	}
30	30
	31	+/*
	32	+ * Spinlock code confers and prods, so don't trace the hcalls because the
	33	+ * tracing code takes spinlocks which can cause recursion deadlocks.
	34	+ *
	35	+ * These calls are made while the lock is not held: the lock slowpath yields if
	36	+ * it can not acquire the lock, and unlock slow path might prod if a waiter has
	37	+ * yielded). So this may not be a problem for simple spin locks because the
	38	+ * tracing does not technically recurse on the lock, but we avoid it anyway.
	39	+ *
	40	+ * However the queued spin lock contended path is more strictly ordered: the
	41	+ * H_CONFER hcall is made after the task has queued itself on the lock, so then
	42	+ * recursing on that lock will cause the task to then queue up again behind the
	43	+ * first instance (or worse: queued spinlocks use tricks that assume a context
	44	+ * never waits on more than one spinlock, so such recursion may cause random
	45	+ * corruption in the lock code).
	46	+ */
31	47	static inline void yield_to_preempted(int cpu, u32 yield_count)
32	48	{
33		− plpar_hcall_norets(H_CONFER, get_hard_smp_processor_id(cpu), yield_count);
	49	+ plpar_hcall_norets_notrace(H_CONFER, get_hard_smp_processor_id(cpu), yield_count);
34	50	}
35	51
36	52	static inline void prod_cpu(int cpu)
37	53	{
38		− plpar_hcall_norets(H_PROD, get_hard_smp_processor_id(cpu));
	54	+ plpar_hcall_norets_notrace(H_PROD, get_hard_smp_processor_id(cpu));
39	55	}
40	56
41	57	static inline void yield_to_any(void)
42	58	{
43		− plpar_hcall_norets(H_CONFER, -1, 0);
	59	+ plpar_hcall_norets_notrace(H_CONFER, -1, 0);
44	60	}
45	61	#else
46	62	static inline bool is_shared_processor(void)

arch/powerpc/include/asm/plpar_wrappers.h+5−1

@@ -28,7 +28,11 @@ static inline void set_cede_latency_hint(u8 latency_hint) · 27 unmodified lines
28	28
29	29	static inline long cede_processor(void)
30	30	{
31		− return plpar_hcall_norets(H_CEDE);
	31	+ /*
	32	+ * We cannot call tracepoints inside RCU idle regions which
	33	+ * means we must not trace H_CEDE.
	34	+ */
	35	+ return plpar_hcall_norets_notrace(H_CEDE);
32	36	}
33	37
34	38	static inline long extended_cede_processor(unsigned long latency_hint)

arch/powerpc/include/asm/pte-walk.h+29−0

@@ -31,6 +31,35 @@ static inline pte_t find_init_mm_pte(unsigned long ea, unsigned hshift) · 30 unmodified lines
31	31	pgd_t *pgdir = init_mm.pgd;
32	32	return __find_linux_pte(pgdir, ea, NULL, hshift);
33	33	}
	34	+
	35	+/*
	36	+ * Convert a kernel vmap virtual address (vmalloc or ioremap space) to a
	37	+ * physical address, without taking locks. This can be used in real-mode.
	38	+ */
	39	+static inline phys_addr_t ppc_find_vmap_phys(unsigned long addr)
	40	+{
	41	+ pte_t *ptep;
	42	+ phys_addr_t pa;
	43	+ int hugepage_shift;
	44	+
	45	+ /*
	46	+ * init_mm does not free page tables, and does not do THP. It may
	47	+ * have huge pages from huge vmalloc / ioremap etc.
	48	+ */
	49	+ ptep = find_init_mm_pte(addr, &hugepage_shift);
	50	+ if (WARN_ON(!ptep))
	51	+ return 0;
	52	+
	53	+ pa = PFN_PHYS(pte_pfn(*ptep));
	54	+
	55	+ if (!hugepage_shift)
	56	+ hugepage_shift = PAGE_SHIFT;
	57	+
	58	+ pa \|= addr & ((1ul << hugepage_shift) - 1);
	59	+
	60	+ return pa;
	61	+}
	62	+
34	63	/*
35	64	* This is what we should always use. Any other lockless page table lookup needs
36	65	* careful audit against THP split.

arch/powerpc/include/asm/ptrace.h+26−19

@@ -19,6 +19,7 @@ · 18 unmodified lines
19	19	#ifndef _ASM_POWERPC_PTRACE_H
20	20	#define _ASM_POWERPC_PTRACE_H
21	21
	22	+#include <linux/err.h>
22	23	#include <uapi/asm/ptrace.h>
23	24	#include <asm/asm-const.h>
24	25
@@ -152,25 +153,6 @@ extern unsigned long profile_pc(struct pt_regs *regs); · 127 unmodified lines
152	153	long do_syscall_trace_enter(struct pt_regs *regs);
153	154	void do_syscall_trace_leave(struct pt_regs *regs);
154	155
155		−#define kernel_stack_pointer(regs) ((regs)->gpr[1])
156		−static inline int is_syscall_success(struct pt_regs *regs)
157		−{
158		− return !(regs->ccr & 0x10000000);
159		−}
160		−
161		−static inline long regs_return_value(struct pt_regs *regs)
162		−{
163		− if (is_syscall_success(regs))
164		− return regs->gpr[3];
165		− else
166		− return -regs->gpr[3];
167		−}
168		−
169		−static inline void regs_set_return_value(struct pt_regs *regs, unsigned long rc)
170		−{
171		− regs->gpr[3] = rc;
172		−}
173		−
174	156	#ifdef __powerpc64__
175	157	#define user_mode(regs) ((((regs)->msr) >> MSR_PR_LG) & 0x1)
176	158	#else
@@ -235,6 +217,31 @@ static __always_inline void set_trap_norestart(struct pt_regs *regs) · 58 unmodified lines
235	217	regs->trap \|= 0x1;
236	218	}
237	219
	220	+#define kernel_stack_pointer(regs) ((regs)->gpr[1])
	221	+static inline int is_syscall_success(struct pt_regs *regs)
	222	+{
	223	+ if (trap_is_scv(regs))
	224	+ return !IS_ERR_VALUE((unsigned long)regs->gpr[3]);
	225	+ else
	226	+ return !(regs->ccr & 0x10000000);
	227	+}
	228	+
	229	+static inline long regs_return_value(struct pt_regs *regs)
	230	+{
	231	+ if (trap_is_scv(regs))
	232	+ return regs->gpr[3];
	233	+
	234	+ if (is_syscall_success(regs))
	235	+ return regs->gpr[3];
	236	+ else
	237	+ return -regs->gpr[3];
	238	+}
	239	+
	240	+static inline void regs_set_return_value(struct pt_regs *regs, unsigned long rc)
	241	+{
	242	+ regs->gpr[3] = rc;
	243	+}
	244	+
238	245	#define arch_has_single_step() (1)
239	246	#define arch_has_block_step() (true)
240	247	#define ARCH_HAS_USER_SINGLE_STEP_REPORT

arch/powerpc/include/asm/syscall.h+26−16

@@ -41,11 +41,17 @@ static inline void syscall_rollback(struct task_struct *task, · 40 unmodified lines
41	41	static inline long syscall_get_error(struct task_struct *task,
42	42	struct pt_regs *regs)
43	43	{
44		− /*
45		− * If the system call failed,
46		− * regs->gpr[3] contains a positive ERRORCODE.
47		− */
48		− return (regs->ccr & 0x10000000UL) ? -regs->gpr[3] : 0;
	44	+ if (trap_is_scv(regs)) {
	45	+ unsigned long error = regs->gpr[3];
	46	+
	47	+ return IS_ERR_VALUE(error) ? error : 0;
	48	+ } else {
	49	+ /*
	50	+ * If the system call failed,
	51	+ * regs->gpr[3] contains a positive ERRORCODE.
	52	+ */
	53	+ return (regs->ccr & 0x10000000UL) ? -regs->gpr[3] : 0;
	54	+ }
49	55	}
50	56
51	57	static inline long syscall_get_return_value(struct task_struct *task,
@@ -58,18 +64,22 @@ static inline void syscall_set_return_value(struct task_struct *task, · 6 unmodified lines
58	64	struct pt_regs *regs,
59	65	int error, long val)
60	66	{
61		− /*
62		− * In the general case it's not obvious that we must deal with CCR
63		− * here, as the syscall exit path will also do that for us. However
64		− * there are some places, eg. the signal code, which check ccr to
65		− * decide if the value in r3 is actually an error.
66		− */
67		− if (error) {
68		− regs->ccr \|= 0x10000000L;
69		− regs->gpr[3] = error;
	67	+ if (trap_is_scv(regs)) {
	68	+ regs->gpr[3] = (long) error ?: val;
70	69	} else {
71		− regs->ccr &= ~0x10000000L;
72		− regs->gpr[3] = val;
	70	+ /*
	71	+ * In the general case it's not obvious that we must deal with
	72	+ * CCR here, as the syscall exit path will also do that for us.
	73	+ * However there are some places, eg. the signal code, which
	74	+ * check ccr to decide if the value in r3 is actually an error.
	75	+ */
	76	+ if (error) {
	77	+ regs->ccr \|= 0x10000000L;
	78	+ regs->gpr[3] = error;
	79	+ } else {
	80	+ regs->ccr &= ~0x10000000L;
	81	+ regs->gpr[3] = val;
	82	+ }
73	83	}
74	84	}
75	85

arch/powerpc/include/asm/uaccess.h+1−1

@@ -157,7 +157,7 @@ do { \ · 156 unmodified lines
157	157	"2: lwz%X1 %L0, %L1\n" \
158	158	EX_TABLE(1b, %l2) \
159	159	EX_TABLE(2b, %l2) \
160		− : "=r" (x) \
	160	+ : "=&r" (x) \
161	161	: "m" (*addr) \
162	162	: \
163	163	: label)

arch/powerpc/kernel/eeh.c+1−22

@@ -346,28 +346,7 @@ void eeh_slot_error_detail(struct eeh_pe *pe, int severity) · 345 unmodified lines
346	346	*/
347	347	static inline unsigned long eeh_token_to_phys(unsigned long token)
348	348	{
349		− pte_t *ptep;
350		− unsigned long pa;
351		− int hugepage_shift;
352		−
353		− /*
354		− * We won't find hugepages here(this is iomem). Hence we are not
355		− * worried about _PAGE_SPLITTING/collapse. Also we will not hit
356		− * page table free, because of init_mm.
357		− */
358		− ptep = find_init_mm_pte(token, &hugepage_shift);
359		− if (!ptep)
360		− return token;
361		−
362		− pa = pte_pfn(*ptep);
363		−
364		− /* On radix we can do hugepage mappings for io, so handle that */
365		− if (!hugepage_shift)
366		− hugepage_shift = PAGE_SHIFT;
367		−
368		− pa <<= PAGE_SHIFT;
369		− pa \|= token & ((1ul << hugepage_shift) - 1);
370		− return pa;
	349	+ return ppc_find_vmap_phys(token);
371	350	}
372	351
373	352	/*

arch/powerpc/kernel/exceptions-64e.S+24−14

@@ -340,6 +340,12 @@ ret_from_mc_except: · 339 unmodified lines
340	340	andi. r10,r10,IRQS_DISABLED; /* yes -> go out of line */ \
341	341	bne masked_interrupt_book3e_##n
342	342
	343	+/*
	344	+ * Additional regs must be re-loaded from paca before EXCEPTION_COMMON* is
	345	+ * called, because that does SAVE_NVGPRS which must see the original register
	346	+ * values, otherwise the scratch values might be restored when exiting the
	347	+ * interrupt.
	348	+ */
343	349	#define PROLOG_ADDITION_2REGS_GEN(n) \
344	350	std r14,PACA_EXGEN+EX_R14(r13); \
345	351	std r15,PACA_EXGEN+EX_R15(r13)
@@ -535,6 +541,10 @@ __end_interrupts: · 189 unmodified lines
535	541	PROLOG_ADDITION_2REGS)
536	542	mfspr r14,SPRN_DEAR
537	543	mfspr r15,SPRN_ESR
	544	+ std r14,_DAR(r1)
	545	+ std r15,_DSISR(r1)
	546	+ ld r14,PACA_EXGEN+EX_R14(r13)
	547	+ ld r15,PACA_EXGEN+EX_R15(r13)
538	548	EXCEPTION_COMMON(0x300)
539	549	b storage_fault_common
540	550
@@ -544,6 +554,10 @@ __end_interrupts: · 3 unmodified lines
544	554	PROLOG_ADDITION_2REGS)
545	555	li r15,0
546	556	mr r14,r10
	557	+ std r14,_DAR(r1)
	558	+ std r15,_DSISR(r1)
	559	+ ld r14,PACA_EXGEN+EX_R14(r13)
	560	+ ld r15,PACA_EXGEN+EX_R15(r13)
547	561	EXCEPTION_COMMON(0x400)
548	562	b storage_fault_common
549	563
@@ -557,6 +571,10 @@ __end_interrupts: · 7 unmodified lines
557	571	PROLOG_ADDITION_2REGS)
558	572	mfspr r14,SPRN_DEAR
559	573	mfspr r15,SPRN_ESR
	574	+ std r14,_DAR(r1)
	575	+ std r15,_DSISR(r1)
	576	+ ld r14,PACA_EXGEN+EX_R14(r13)
	577	+ ld r15,PACA_EXGEN+EX_R15(r13)
560	578	EXCEPTION_COMMON(0x600)
561	579	b alignment_more /* no room, go out of line */
562	580
@@ -565,10 +583,10 @@ __end_interrupts: · 2 unmodified lines
565	583	NORMAL_EXCEPTION_PROLOG(0x700, BOOKE_INTERRUPT_PROGRAM,
566	584	PROLOG_ADDITION_1REG)
567	585	mfspr r14,SPRN_ESR
568		− EXCEPTION_COMMON(0x700)
569	586	std r14,_DSISR(r1)
570		− addi r3,r1,STACK_FRAME_OVERHEAD
571	587	ld r14,PACA_EXGEN+EX_R14(r13)
	588	+ EXCEPTION_COMMON(0x700)
	589	+ addi r3,r1,STACK_FRAME_OVERHEAD
572	590	bl program_check_exception
573	591	REST_NVGPRS(r1)
574	592	b interrupt_return
@@ -725,11 +743,11 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) · 150 unmodified lines
725	743	* normal exception
726	744	*/
727	745	mfspr r14,SPRN_DBSR
728		− EXCEPTION_COMMON_CRIT(0xd00)
729	746	std r14,_DSISR(r1)
730		− addi r3,r1,STACK_FRAME_OVERHEAD
731	747	ld r14,PACA_EXCRIT+EX_R14(r13)
732	748	ld r15,PACA_EXCRIT+EX_R15(r13)
	749	+ EXCEPTION_COMMON_CRIT(0xd00)
	750	+ addi r3,r1,STACK_FRAME_OVERHEAD
733	751	bl DebugException
734	752	REST_NVGPRS(r1)
735	753	b interrupt_return
@@ -796,11 +814,11 @@ kernel_dbg_exc: · 60 unmodified lines
796	814	* normal exception
797	815	*/
798	816	mfspr r14,SPRN_DBSR
799		− EXCEPTION_COMMON_DBG(0xd08)
800	817	std r14,_DSISR(r1)
801		− addi r3,r1,STACK_FRAME_OVERHEAD
802	818	ld r14,PACA_EXDBG+EX_R14(r13)
803	819	ld r15,PACA_EXDBG+EX_R15(r13)
	820	+ EXCEPTION_COMMON_DBG(0xd08)
	821	+ addi r3,r1,STACK_FRAME_OVERHEAD
804	822	bl DebugException
805	823	REST_NVGPRS(r1)
806	824	b interrupt_return
@@ -931,11 +949,7 @@ masked_interrupt_book3e_0x2c0: · 124 unmodified lines
931	949	* original values stashed away in the PACA
932	950	*/
933	951	storage_fault_common:
934		− std r14,_DAR(r1)
935		− std r15,_DSISR(r1)
936	952	addi r3,r1,STACK_FRAME_OVERHEAD
937		− ld r14,PACA_EXGEN+EX_R14(r13)
938		− ld r15,PACA_EXGEN+EX_R15(r13)
939	953	bl do_page_fault
940	954	b interrupt_return
941	955
@@ -944,11 +958,7 @@ storage_fault_common: · 2 unmodified lines
944	958	* continues here.
945	959	*/
946	960	alignment_more:
947		− std r14,_DAR(r1)
948		− std r15,_DSISR(r1)
949	961	addi r3,r1,STACK_FRAME_OVERHEAD
950		− ld r14,PACA_EXGEN+EX_R14(r13)
951		− ld r15,PACA_EXGEN+EX_R15(r13)
952	962	bl alignment_exception
953	963	REST_NVGPRS(r1)
954	964	b interrupt_return

arch/powerpc/kernel/interrupt.c+1−3

@@ -34,9 +34,6 @@ notrace long system_call_exception(long r3, long r4, long r5, · 33 unmodified lines
34	34	syscall_fn f;
35	35
36	36	kuep_lock();
37		−#ifdef CONFIG_PPC32
38		− kuap_save_and_lock(regs);
39		−#endif
40	37
41	38	regs->orig_gpr3 = r3;
42	39
@@ -427,6 +424,7 @@ again: · 384 unmodified lines
427	424
428	425	/* Restore user access locks last */
429	426	kuap_user_restore(regs);
	427	+ kuep_unlock();
430	428
431	429	return ret;
432	430	}

arch/powerpc/kernel/io-workarounds.c+3−13

@@ -55,7 +55,6 @@ static struct iowa_bus *iowa_pci_find(unsigned long vaddr, unsigned long paddr) · 54 unmodified lines
55	55	#ifdef CONFIG_PPC_INDIRECT_MMIO
56	56	struct iowa_bus *iowa_mem_find_bus(const PCI_IO_ADDR addr)
57	57	{
58		− unsigned hugepage_shift;
59	58	struct iowa_bus *bus;
60	59	int token;
61	60
@@ -65,22 +64,13 @@ struct iowa_bus *iowa_mem_find_bus(const PCI_IO_ADDR addr) · 3 unmodified lines
65	64	bus = &iowa_busses[token - 1];
66	65	else {
67	66	unsigned long vaddr, paddr;
68		− pte_t *ptep;
69	67
70	68	vaddr = (unsigned long)PCI_FIX_ADDR(addr);
71	69	if (vaddr < PHB_IO_BASE \|\| vaddr >= PHB_IO_END)
72	70	return NULL;
73		− /*
74		− * We won't find huge pages here (iomem). Also can't hit
75		− * a page table free due to init_mm
76		− */
77		− ptep = find_init_mm_pte(vaddr, &hugepage_shift);
78		− if (ptep == NULL)
79		− paddr = 0;
80		− else {
81		− WARN_ON(hugepage_shift);
82		− paddr = pte_pfn(*ptep) << PAGE_SHIFT;
83		− }
	71	+
	72	+ paddr = ppc_find_vmap_phys(vaddr);
	73	+
84	74	bus = iowa_pci_find(vaddr, paddr);
85	75
86	76	if (bus == NULL)

arch/powerpc/kernel/iommu.c+5−6

@@ -898,7 +898,6 @@ void iommu_alloc_coherent(struct device dev, struct iommu_table *tbl, · 897 unmodified lines
898	898	unsigned int order;
899	899	unsigned int nio_pages, io_order;
900	900	struct page *page;
901		− size_t size_io = size;
902	901
903	902	size = PAGE_ALIGN(size);
904	903	order = get_order(size);
@@ -925,9 +924,8 @@ void iommu_alloc_coherent(struct device dev, struct iommu_table *tbl, · 20 unmodified lines
925	924	memset(ret, 0, size);
926	925
927	926	/* Set up tces to cover the allocated range */
928		− size_io = IOMMU_PAGE_ALIGN(size_io, tbl);
929		− nio_pages = size_io >> tbl->it_page_shift;
930		− io_order = get_iommu_order(size_io, tbl);
	927	+ nio_pages = size >> tbl->it_page_shift;
	928	+ io_order = get_iommu_order(size, tbl);
931	929	mapping = iommu_alloc(dev, tbl, ret, nio_pages, DMA_BIDIRECTIONAL,
932	930	mask >> tbl->it_page_shift, io_order, 0);
933	931	if (mapping == DMA_MAPPING_ERROR) {
@@ -942,9 +940,10 @@ void iommu_free_coherent(struct iommu_table *tbl, size_t size, · 8 unmodified lines
942	940	void *vaddr, dma_addr_t dma_handle)
943	941	{
944	942	if (tbl) {
945		− size_t size_io = IOMMU_PAGE_ALIGN(size, tbl);
946		− unsigned int nio_pages = size_io >> tbl->it_page_shift;
	943	+ unsigned int nio_pages;
947	944
	945	+ size = PAGE_ALIGN(size);
	946	+ nio_pages = size >> tbl->it_page_shift;
948	947	iommu_free(tbl, dma_handle, nio_pages);
949	948	size = PAGE_ALIGN(size);
950	949	free_pages((unsigned long)vaddr, get_order(size));

arch/powerpc/kernel/kprobes.c+2−2

@@ -108,7 +108,6 @@ int arch_prepare_kprobe(struct kprobe *p) · 107 unmodified lines
108	108	int ret = 0;
109	109	struct kprobe *prev;
110	110	struct ppc_inst insn = ppc_inst_read((struct ppc_inst *)p->addr);
111		− struct ppc_inst prefix = ppc_inst_read((struct ppc_inst *)(p->addr - 1));
112	111
113	112	if ((unsigned long)p->addr & 0x03) {
114	113	printk("Attempt to register kprobe at an unaligned address\n");
@@ -116,7 +115,8 @@ int arch_prepare_kprobe(struct kprobe *p) · 1 unmodified line
116	115	} else if (IS_MTMSRD(insn) \|\| IS_RFID(insn) \|\| IS_RFI(insn)) {
117	116	printk("Cannot register a kprobe on rfi/rfid or mtmsr[d]\n");
118	117	ret = -EINVAL;
119		− } else if (ppc_inst_prefixed(prefix)) {
	118	+ } else if ((unsigned long)p->addr & ~PAGE_MASK &&
	119	+ ppc_inst_prefixed(ppc_inst_read((struct ppc_inst *)(p->addr - 1)))) {
120	120	printk("Cannot register a kprobe on the second word of prefixed instruction\n");
121	121	ret = -EINVAL;
122	122	}

arch/powerpc/kernel/legacy_serial.c+5−2

@@ -356,13 +356,16 @@ static void __init setup_legacy_serial_console(int console) · 355 unmodified lines
356	356
357	357	static int __init ioremap_legacy_serial_console(void)
358	358	{
359		− struct legacy_serial_info *info = &legacy_serial_infos[legacy_serial_console];
360		− struct plat_serial8250_port *port = &legacy_serial_ports[legacy_serial_console];
	359	+ struct plat_serial8250_port *port;
	360	+ struct legacy_serial_info *info;
361	361	void __iomem *vaddr;
362	362
363	363	if (legacy_serial_console < 0)
364	364	return 0;
365	365
	366	+ info = &legacy_serial_infos[legacy_serial_console];
	367	+ port = &legacy_serial_ports[legacy_serial_console];
	368	+
366	369	if (!info->early_addr)
367	370	return 0;
368	371

arch/powerpc/kernel/setup_64.c+2−2

@@ -369,11 +369,11 @@ void __init early_setup(unsigned long dt_ptr) · 368 unmodified lines
369	369	apply_feature_fixups();
370	370	setup_feature_keys();
371	371
372		− early_ioremap_setup();
373		−
374	372	/* Initialize the hash table or TLB handling */
375	373	early_init_mmu();
376	374
	375	+ early_ioremap_setup();
	376	+
377	377	/*
378	378	* After firmware and early platform setup code has set things up,
379	379	* we note the SPR values for configurable control/performance

arch/powerpc/kernel/signal.h+2−2

@@ -166,9 +166,9 @@ copy_ckfpr_from_user(struct task_struct task, void __user from) · 165 unmodified lines
166	166	}
167	167	#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
168	168	#else
169		−#define unsafe_copy_fpr_to_user(to, task, label) do { } while (0)
	169	+#define unsafe_copy_fpr_to_user(to, task, label) do { if (0) goto label;} while (0)
170	170
171		−#define unsafe_copy_fpr_from_user(task, from, label) do { } while (0)
	171	+#define unsafe_copy_fpr_from_user(task, from, label) do { if (0) goto label;} while (0)
172	172
173	173	static inline unsigned long
174	174	copy_fpr_to_user(void __user to, struct task_struct task)

arch/powerpc/kernel/signal_64.c+4−5

@@ -902,6 +902,10 @@ int handle_rt_signal64(struct ksignal ksig, sigset_t set, · 901 unmodified lines
902	902	unsafe_copy_to_user(&frame->uc.uc_sigmask, set, sizeof(*set), badframe_block);
903	903	user_write_access_end();
904	904
	905	+ /* Save the siginfo outside of the unsafe block. */
	906	+ if (copy_siginfo_to_user(&frame->info, &ksig->info))
	907	+ goto badframe;
	908	+
905	909	/* Make sure signal handler doesn't get spurious FP exceptions */
906	910	tsk->thread.fp_state.fpscr = 0;
907	911
@@ -915,11 +919,6 @@ int handle_rt_signal64(struct ksignal ksig, sigset_t set, · 7 unmodified lines
915	919	regs->nip = (unsigned long) &frame->tramp[0];
916	920	}
917	921
918		−
919		− /* Save the siginfo outside of the unsafe block. */
920		− if (copy_siginfo_to_user(&frame->info, &ksig->info))
921		− goto badframe;
922		−
923	922	/* Allocate a dummy caller frame for the signal handler. */
924	923	newsp = ((unsigned long)frame) - __SIGNAL_FRAMESIZE;
925	924	err \|= put_user(regs->gpr[1], (unsigned long __user *)newsp);

arch/powerpc/kernel/syscalls/syscall.tbl+1−1

@@ -522,7 +522,7 @@ · 521 unmodified lines
522	522	440 common process_madvise sys_process_madvise
523	523	441 common epoll_pwait2 sys_epoll_pwait2 compat_sys_epoll_pwait2
524	524	442 common mount_setattr sys_mount_setattr
525		−443 common quotactl_path sys_quotactl_path
	525	+# 443 reserved for quotactl_path
526	526	444 common landlock_create_ruleset sys_landlock_create_ruleset
527	527	445 common landlock_add_rule sys_landlock_add_rule
528	528	446 common landlock_restrict_self sys_landlock_restrict_self

arch/powerpc/kvm/book3s_64_mmu_hv.c+1−1

@@ -840,7 +840,7 @@ bool kvm_unmap_gfn_range_hv(struct kvm kvm, struct kvm_gfn_range range) · 839 unmodified lines
840	840	kvm_unmap_radix(kvm, range->slot, gfn);
841	841	} else {
842	842	for (gfn = range->start; gfn < range->end; gfn++)
843		− kvm_unmap_rmapp(kvm, range->slot, range->start);
	843	+ kvm_unmap_rmapp(kvm, range->slot, gfn);
844	844	}
845	845
846	846	return false;

arch/powerpc/kvm/book3s_hv.c+1−2

@@ -3936,7 +3936,7 @@ static void kvmppc_vcore_blocked(struct kvmppc_vcore *vc) · 3935 unmodified lines
3936	3936	break;
3937	3937	}
3938	3938	cur = ktime_get();
3939		− } while (single_task_running() && ktime_before(cur, stop));
	3939	+ } while (kvm_vcpu_can_poll(cur, stop));
3940	3940
3941	3941	spin_lock(&vc->lock);
3942	3942	vc->vcore_state = VCORE_INACTIVE;
@@ -4455,7 +4455,6 @@ static int kvmppc_vcpu_run_hv(struct kvm_vcpu *vcpu) · 512 unmodified lines
4455	4455	mtspr(SPRN_EBBRR, ebb_regs[1]);
4456	4456	mtspr(SPRN_BESCR, ebb_regs[2]);
4457	4457	mtspr(SPRN_TAR, user_tar);
4458		− mtspr(SPRN_FSCR, current->thread.fscr);
4459	4458	}
4460	4459	mtspr(SPRN_VRSAVE, user_vrsave);
4461	4460

arch/powerpc/kvm/book3s_hv_rm_mmu.c+2−13

@@ -23,20 +23,9 @@ · 22 unmodified lines
23	23	#include <asm/pte-walk.h>
24	24
25	25	/* Translate address of a vmalloc'd thing to a linear map address */
26		−static void real_vmalloc_addr(void x)
	26	+static void real_vmalloc_addr(void addr)
27	27	{
28		− unsigned long addr = (unsigned long) x;
29		− pte_t *p;
30		− /*
31		− * assume we don't have huge pages in vmalloc space...
32		− * So don't worry about THP collapse/split. Called
33		− * Only in realmode with MSR_EE = 0, hence won't need irq_save/restore.
34		− */
35		− p = find_init_mm_pte(addr, NULL);
36		− if (!p \|\| !pte_present(*p))
37		− return NULL;
38		− addr = (pte_pfn(*p) << PAGE_SHIFT) \| (addr & ~PAGE_MASK);
39		− return __va(addr);
	28	+ return __va(ppc_find_vmap_phys((unsigned long)addr));
40	29	}
41	30
42	31	/* Return 1 if we need to do a global tlbie, 0 if we can use tlbiel */

arch/powerpc/kvm/book3s_hv_rmhandlers.S+7−0

@@ -59,6 +59,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300) · 58 unmodified lines
59	59	#define STACK_SLOT_UAMOR (SFS-88)
60	60	#define STACK_SLOT_DAWR1 (SFS-96)
61	61	#define STACK_SLOT_DAWRX1 (SFS-104)
	62	+#define STACK_SLOT_FSCR (SFS-112)
62	63	/* the following is used by the P9 short path */
63	64	#define STACK_SLOT_NVGPRS (SFS-152) /* 18 gprs */
64	65
@@ -686,6 +687,8 @@ BEGIN_FTR_SECTION · 621 unmodified lines
686	687	std r6, STACK_SLOT_DAWR0(r1)
687	688	std r7, STACK_SLOT_DAWRX0(r1)
688	689	std r8, STACK_SLOT_IAMR(r1)
	690	+ mfspr r5, SPRN_FSCR
	691	+ std r5, STACK_SLOT_FSCR(r1)
689	692	END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
690	693	BEGIN_FTR_SECTION
691	694	mfspr r6, SPRN_DAWR1
@@ -1663,6 +1666,10 @@ FTR_SECTION_ELSE · 971 unmodified lines
1663	1666	ld r7, STACK_SLOT_HFSCR(r1)
1664	1667	mtspr SPRN_HFSCR, r7
1665	1668	ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300)
	1669	+BEGIN_FTR_SECTION
	1670	+ ld r5, STACK_SLOT_FSCR(r1)
	1671	+ mtspr SPRN_FSCR, r5
	1672	+END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1666	1673	/*
1667	1674	* Restore various registers to 0, where non-zero values
1668	1675	* set by the guest could disrupt the host.

arch/powerpc/lib/feature-fixups.c+85−29

@@ -14,6 +14,7 @@ · 13 unmodified lines
14	14	#include <linux/string.h>
15	15	#include <linux/init.h>
16	16	#include <linux/sched/mm.h>
	17	+#include <linux/stop_machine.h>
17	18	#include <asm/cputable.h>
18	19	#include <asm/code-patching.h>
19	20	#include <asm/page.h>
@@ -149,17 +150,17 @@ static void do_stf_entry_barrier_fixups(enum stf_barrier_type types) · 129 unmodified lines
149	150
150	151	pr_devel("patching dest %lx\n", (unsigned long)dest);
151	152
152		− patch_instruction((struct ppc_inst *)dest, ppc_inst(instrs[0]));
153		−
154		− if (types & STF_BARRIER_FALLBACK)
	153	+ // See comment in do_entry_flush_fixups() RE order of patching
	154	+ if (types & STF_BARRIER_FALLBACK) {
	155	+ patch_instruction((struct ppc_inst *)dest, ppc_inst(instrs[0]));
	156	+ patch_instruction((struct ppc_inst *)(dest + 2), ppc_inst(instrs[2]));
155	157	patch_branch((struct ppc_inst *)(dest + 1),
156		− (unsigned long)&stf_barrier_fallback,
157		− BRANCH_SET_LINK);
158		− else
159		− patch_instruction((struct ppc_inst *)(dest + 1),
160		− ppc_inst(instrs[1]));
161		−
162		− patch_instruction((struct ppc_inst *)(dest + 2), ppc_inst(instrs[2]));
	158	+ (unsigned long)&stf_barrier_fallback, BRANCH_SET_LINK);
	159	+ } else {
	160	+ patch_instruction((struct ppc_inst *)(dest + 1), ppc_inst(instrs[1]));
	161	+ patch_instruction((struct ppc_inst *)(dest + 2), ppc_inst(instrs[2]));
	162	+ patch_instruction((struct ppc_inst *)dest, ppc_inst(instrs[0]));
	163	+ }
163	164	}
164	165
165	166	printk(KERN_DEBUG "stf-barrier: patched %d entry locations (%s barrier)\n", i,
@@ -227,11 +228,25 @@ static void do_stf_exit_barrier_fixups(enum stf_barrier_type types) · 61 unmodified lines
227	228	: "unknown");
228	229	}
229	230
	231	+static int __do_stf_barrier_fixups(void *data)
	232	+{
	233	+ enum stf_barrier_type *types = data;
	234	+
	235	+ do_stf_entry_barrier_fixups(*types);
	236	+ do_stf_exit_barrier_fixups(*types);
	237	+
	238	+ return 0;
	239	+}
230	240
231	241	void do_stf_barrier_fixups(enum stf_barrier_type types)
232	242	{
233		− do_stf_entry_barrier_fixups(types);
234		− do_stf_exit_barrier_fixups(types);
	243	+ /*
	244	+ * The call to the fallback entry flush, and the fallback/sync-ori exit
	245	+ * flush can not be safely patched in/out while other CPUs are executing
	246	+ * them. So call __do_stf_barrier_fixups() on one CPU while all other CPUs
	247	+ * spin in the stop machine core with interrupts hard disabled.
	248	+ */
	249	+ stop_machine(__do_stf_barrier_fixups, &types, NULL);
235	250	}
236	251
237	252	void do_uaccess_flush_fixups(enum l1d_flush_type types)
@@ -284,8 +299,9 @@ void do_uaccess_flush_fixups(enum l1d_flush_type types) · 46 unmodified lines
284	299	: "unknown");
285	300	}
286	301
287		−void do_entry_flush_fixups(enum l1d_flush_type types)
	302	+static int __do_entry_flush_fixups(void *data)
288	303	{
	304	+ enum l1d_flush_type types = (enum l1d_flush_type )data;
289	305	unsigned int instrs[3], *dest;
290	306	long start, end;
291	307	int i;
@@ -309,6 +325,31 @@ void do_entry_flush_fixups(enum l1d_flush_type types) · 17 unmodified lines
309	325	if (types & L1D_FLUSH_MTTRIG)
310	326	instrs[i++] = 0x7c12dba6; /* mtspr TRIG2,r0 (SPR #882) */
311	327
	328	+ /*
	329	+ * If we're patching in or out the fallback flush we need to be careful about the
	330	+ * order in which we patch instructions. That's because it's possible we could
	331	+ * take a page fault after patching one instruction, so the sequence of
	332	+ * instructions must be safe even in a half patched state.
	333	+ *
	334	+ * To make that work, when patching in the fallback flush we patch in this order:
	335	+ * - the mflr (dest)
	336	+ * - the mtlr (dest + 2)
	337	+ * - the branch (dest + 1)
	338	+ *
	339	+ * That ensures the sequence is safe to execute at any point. In contrast if we
	340	+ * patch the mtlr last, it's possible we could return from the branch and not
	341	+ * restore LR, leading to a crash later.
	342	+ *
	343	+ * When patching out the fallback flush (either with nops or another flush type),
	344	+ * we patch in this order:
	345	+ * - the branch (dest + 1)
	346	+ * - the mtlr (dest + 2)
	347	+ * - the mflr (dest)
	348	+ *
	349	+ * Note we are protected by stop_machine() from other CPUs executing the code in a
	350	+ * semi-patched state.
	351	+ */
	352	+
312	353	start = PTRRELOC(&__start___entry_flush_fixup);
313	354	end = PTRRELOC(&__stop___entry_flush_fixup);
314	355	for (i = 0; start < end; start++, i++) {
@@ -316,15 +357,16 @@ void do_entry_flush_fixups(enum l1d_flush_type types) · 1 unmodified line
316	357
317	358	pr_devel("patching dest %lx\n", (unsigned long)dest);
318	359
319		− patch_instruction((struct ppc_inst *)dest, ppc_inst(instrs[0]));
320		−
321		− if (types == L1D_FLUSH_FALLBACK)
322		− patch_branch((struct ppc_inst *)(dest + 1), (unsigned long)&entry_flush_fallback,
323		− BRANCH_SET_LINK);
324		− else
	360	+ if (types == L1D_FLUSH_FALLBACK) {
	361	+ patch_instruction((struct ppc_inst *)dest, ppc_inst(instrs[0]));
	362	+ patch_instruction((struct ppc_inst *)(dest + 2), ppc_inst(instrs[2]));
	363	+ patch_branch((struct ppc_inst *)(dest + 1),
	364	+ (unsigned long)&entry_flush_fallback, BRANCH_SET_LINK);
	365	+ } else {
325	366	patch_instruction((struct ppc_inst *)(dest + 1), ppc_inst(instrs[1]));
326		−
327		− patch_instruction((struct ppc_inst *)(dest + 2), ppc_inst(instrs[2]));
	367	+ patch_instruction((struct ppc_inst *)(dest + 2), ppc_inst(instrs[2]));
	368	+ patch_instruction((struct ppc_inst *)dest, ppc_inst(instrs[0]));
	369	+ }
328	370	}
329	371
330	372	start = PTRRELOC(&__start___scv_entry_flush_fixup);
@@ -334,15 +376,16 @@ void do_entry_flush_fixups(enum l1d_flush_type types) · 3 unmodified lines
334	376
335	377	pr_devel("patching dest %lx\n", (unsigned long)dest);
336	378
337		− patch_instruction((struct ppc_inst *)dest, ppc_inst(instrs[0]));
338		−
339		− if (types == L1D_FLUSH_FALLBACK)
340		− patch_branch((struct ppc_inst *)(dest + 1), (unsigned long)&scv_entry_flush_fallback,
341		− BRANCH_SET_LINK);
342		− else
	379	+ if (types == L1D_FLUSH_FALLBACK) {
	380	+ patch_instruction((struct ppc_inst *)dest, ppc_inst(instrs[0]));
	381	+ patch_instruction((struct ppc_inst *)(dest + 2), ppc_inst(instrs[2]));
	382	+ patch_branch((struct ppc_inst *)(dest + 1),
	383	+ (unsigned long)&scv_entry_flush_fallback, BRANCH_SET_LINK);
	384	+ } else {
343	385	patch_instruction((struct ppc_inst *)(dest + 1), ppc_inst(instrs[1]));
344		−
345		− patch_instruction((struct ppc_inst *)(dest + 2), ppc_inst(instrs[2]));
	386	+ patch_instruction((struct ppc_inst *)(dest + 2), ppc_inst(instrs[2]));
	387	+ patch_instruction((struct ppc_inst *)dest, ppc_inst(instrs[0]));
	388	+ }
346	389	}
347	390
348	391
@@ -354,6 +397,19 @@ void do_entry_flush_fixups(enum l1d_flush_type types) · 5 unmodified lines
354	397	: "ori type" :
355	398	(types & L1D_FLUSH_MTTRIG) ? "mttrig type"
356	399	: "unknown");
	400	+
	401	+ return 0;
	402	+}
	403	+
	404	+void do_entry_flush_fixups(enum l1d_flush_type types)
	405	+{
	406	+ /*
	407	+ * The call to the fallback flush can not be safely patched in/out while
	408	+ * other CPUs are executing it. So call __do_entry_flush_fixups() on one
	409	+ * CPU while all other CPUs spin in the stop machine core with interrupts
	410	+ * hard disabled.
	411	+ */
	412	+ stop_machine(__do_entry_flush_fixups, &types, NULL);
357	413	}
358	414
359	415	void do_rfi_flush_fixups(enum l1d_flush_type types)

arch/powerpc/mm/mem.c+1−0

@@ -20,6 +20,7 @@ · 19 unmodified lines
20	20	#include <asm/machdep.h>
21	21	#include <asm/rtas.h>
22	22	#include <asm/kasan.h>
	23	+#include <asm/sparsemem.h>
23	24	#include <asm/svm.h>
24	25
25	26	#include <mm/mmu_decl.h>

arch/powerpc/perf/core-book3s.c+1−1

@@ -2254,7 +2254,7 @@ unsigned long perf_instruction_pointer(struct pt_regs *regs) · 2253 unmodified lines
2254	2254	bool use_siar = regs_use_siar(regs);
2255	2255	unsigned long siar = mfspr(SPRN_SIAR);
2256	2256
2257		− if (ppmu->flags & PPMU_P10_DD1) {
	2257	+ if (ppmu && (ppmu->flags & PPMU_P10_DD1)) {
2258	2258	if (siar)
2259	2259	return siar;
2260	2260	else

arch/powerpc/platforms/pseries/hvCall.S+10−0

@@ -102,6 +102,16 @@ END_FTR_SECTION(0, 1); \ · 101 unmodified lines
102	102	#define HCALL_BRANCH(LABEL)
103	103	#endif
104	104
	105	+_GLOBAL_TOC(plpar_hcall_norets_notrace)
	106	+ HMT_MEDIUM
	107	+
	108	+ mfcr r0
	109	+ stw r0,8(r1)
	110	+ HVSC /* invoke the hypervisor */
	111	+ lwz r0,8(r1)
	112	+ mtcrf 0xff,r0
	113	+ blr /* return r3 = status */
	114	+
105	115	_GLOBAL_TOC(plpar_hcall_norets)
106	116	HMT_MEDIUM
107	117

arch/powerpc/platforms/pseries/lpar.c+12−17

@@ -1829,30 +1829,28 @@ void hcall_tracepoint_unregfunc(void) · 1828 unmodified lines
1829	1829	#endif
1830	1830
1831	1831	/*
1832		− * Since the tracing code might execute hcalls we need to guard against
1833		− * recursion. One example of this are spinlocks calling H_YIELD on
1834		− * shared processor partitions.
	1832	+ * Keep track of hcall tracing depth and prevent recursion. Warn if any is
	1833	+ * detected because it may indicate a problem. This will not catch all
	1834	+ * problems with tracing code making hcalls, because the tracing might have
	1835	+ * been invoked from a non-hcall, so the first hcall could recurse into it
	1836	+ * without warning here, but this better than nothing.
	1837	+ *
	1838	+ * Hcalls with specific problems being traced should use the _notrace
	1839	+ * plpar_hcall variants.
1835	1840	*/
1836	1841	static DEFINE_PER_CPU(unsigned int, hcall_trace_depth);
1837	1842
1838	1843
1839		−void __trace_hcall_entry(unsigned long opcode, unsigned long *args)
	1844	+notrace void __trace_hcall_entry(unsigned long opcode, unsigned long *args)
1840	1845	{
1841	1846	unsigned long flags;
1842	1847	unsigned int *depth;
1843	1848
1844		− /*
1845		− * We cannot call tracepoints inside RCU idle regions which
1846		− * means we must not trace H_CEDE.
1847		− */
1848		− if (opcode == H_CEDE)
1849		− return;
1850		−
1851	1849	local_irq_save(flags);
1852	1850
1853	1851	depth = this_cpu_ptr(&hcall_trace_depth);
1854	1852
1855		− if (*depth)
	1853	+ if (WARN_ON_ONCE(*depth))
1856	1854	goto out;
1857	1855
1858	1856	(*depth)++;
@@ -1864,19 +1862,16 @@ out: · 5 unmodified lines
1864	1862	local_irq_restore(flags);
1865	1863	}
1866	1864
1867		−void __trace_hcall_exit(long opcode, long retval, unsigned long *retbuf)
	1865	+notrace void __trace_hcall_exit(long opcode, long retval, unsigned long *retbuf)
1868	1866	{
1869	1867	unsigned long flags;
1870	1868	unsigned int *depth;
1871	1869
1872		− if (opcode == H_CEDE)
1873		− return;
1874		−
1875	1870	local_irq_save(flags);
1876	1871
1877	1872	depth = this_cpu_ptr(&hcall_trace_depth);
1878	1873
1879		− if (*depth)
	1874	+ if (depth) / Don't warn again on the way out */
1880	1875	goto out;
1881	1876
1882	1877	(*depth)++;

arch/riscv/Kconfig+10−9

@@ -34,6 +34,7 @@ config RISCV · 33 unmodified lines
34	34	select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
35	35	select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT
36	36	select ARCH_SUPPORTS_HUGETLBFS if MMU
	37	+ select ARCH_USE_MEMTEST
37	38	select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
38	39	select ARCH_WANT_FRAME_POINTERS
39	40	select ARCH_WANT_HUGE_PMD_SHARE if 64BIT
@@ -60,11 +61,11 @@ config RISCV · 20 unmodified lines
60	61	select GENERIC_TIME_VSYSCALL if MMU && 64BIT
61	62	select HANDLE_DOMAIN_IRQ
62	63	select HAVE_ARCH_AUDITSYSCALL
63		− select HAVE_ARCH_JUMP_LABEL
64		− select HAVE_ARCH_JUMP_LABEL_RELATIVE
	64	+ select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
	65	+ select HAVE_ARCH_JUMP_LABEL_RELATIVE if !XIP_KERNEL
65	66	select HAVE_ARCH_KASAN if MMU && 64BIT
66	67	select HAVE_ARCH_KASAN_VMALLOC if MMU && 64BIT
67		− select HAVE_ARCH_KGDB
	68	+ select HAVE_ARCH_KGDB if !XIP_KERNEL
68	69	select HAVE_ARCH_KGDB_QXFER_PKT
69	70	select HAVE_ARCH_MMAP_RND_BITS if MMU
70	71	select HAVE_ARCH_SECCOMP_FILTER
@@ -79,9 +80,9 @@ config RISCV · 8 unmodified lines
79	80	select HAVE_GCC_PLUGINS
80	81	select HAVE_GENERIC_VDSO if MMU && 64BIT
81	82	select HAVE_IRQ_TIME_ACCOUNTING
82		− select HAVE_KPROBES
83		− select HAVE_KPROBES_ON_FTRACE
84		− select HAVE_KRETPROBES
	83	+ select HAVE_KPROBES if !XIP_KERNEL
	84	+ select HAVE_KPROBES_ON_FTRACE if !XIP_KERNEL
	85	+ select HAVE_KRETPROBES if !XIP_KERNEL
85	86	select HAVE_PCI
86	87	select HAVE_PERF_EVENTS
87	88	select HAVE_PERF_REGS
@@ -230,11 +231,11 @@ config ARCH_RV64I · 142 unmodified lines
230	231	bool "RV64I"
231	232	select 64BIT
232	233	select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 && GCC_VERSION >= 50000
233		− select HAVE_DYNAMIC_FTRACE if MMU && $(cc-option,-fpatchable-function-entry=8)
	234	+ select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && MMU && $(cc-option,-fpatchable-function-entry=8)
234	235	select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
235		− select HAVE_FTRACE_MCOUNT_RECORD
	236	+ select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
236	237	select HAVE_FUNCTION_GRAPH_TRACER
237		− select HAVE_FUNCTION_TRACER
	238	+ select HAVE_FUNCTION_TRACER if !XIP_KERNEL
238	239	select SWIOTLB if MMU
239	240
240	241	endchoice

arch/riscv/Kconfig.socs+1−0

@@ -14,6 +14,7 @@ config SOC_SIFIVE · 13 unmodified lines
14	14	select CLK_SIFIVE
15	15	select CLK_SIFIVE_PRCI
16	16	select SIFIVE_PLIC
	17	+ select RISCV_ERRATA_ALTERNATIVE
17	18	select ERRATA_SIFIVE
18	19	help
19	20	This enables support for SiFive SoC platform hardware.

arch/riscv/Makefile+10−1

@@ -16,7 +16,7 @@ ifeq ($(CONFIG_DYNAMIC_FTRACE),y) · 15 unmodified lines
16	16	CC_FLAGS_FTRACE := -fpatchable-function-entry=8
17	17	endif
18	18
19		−ifeq ($(CONFIG_64BIT)$(CONFIG_CMODEL_MEDLOW),yy)
	19	+ifeq ($(CONFIG_CMODEL_MEDLOW),y)
20	20	KBUILD_CFLAGS_MODULE += -mcmodel=medany
21	21	endif
22	22
@@ -38,6 +38,15 @@ else · 15 unmodified lines
38	38	KBUILD_LDFLAGS += -melf32lriscv
39	39	endif
40	40
	41	+ifeq ($(CONFIG_LD_IS_LLD),y)
	42	+ KBUILD_CFLAGS += -mno-relax
	43	+ KBUILD_AFLAGS += -mno-relax
	44	+ifneq ($(LLVM_IAS),1)
	45	+ KBUILD_CFLAGS += -Wa,-mno-relax
	46	+ KBUILD_AFLAGS += -Wa,-mno-relax
	47	+endif
	48	+endif
	49	+
41	50	# ISA string setting
42	51	riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima
43	52	riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima

arch/riscv/boot/dts/microchip/Makefile+1−0

@@ -1,2 +1,3 @@
1	1	# SPDX-License-Identifier: GPL-2.0
2	2	dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-mpfs-icicle-kit.dtb
	3	+obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))

arch/riscv/boot/dts/sifive/Makefile+1−0

@@ -1,3 +1,4 @@
1	1	# SPDX-License-Identifier: GPL-2.0
2	2	dtb-$(CONFIG_SOC_SIFIVE) += hifive-unleashed-a00.dtb \
3	3	hifive-unmatched-a00.dtb
	4	+obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))

arch/riscv/boot/dts/sifive/fu740-c000.dtsi+1−1

@@ -273,7 +273,7 @@ · 272 unmodified lines
273	273	cache-size = <2097152>;
274	274	cache-unified;
275	275	interrupt-parent = <&plic0>;
276		− interrupts = <19 20 21 22>;
	276	+ interrupts = <19 21 22 20>;
277	277	reg = <0x0 0x2010000 0x0 0x1000>;
278	278	};
279	279	gpio: gpio@10060000 {

arch/riscv/errata/sifive/Makefile+1−1

@@ -1,2 +1,2 @@
1		−obj-y += errata_cip_453.o
	1	+obj-$(CONFIG_ERRATA_SIFIVE_CIP_453) += errata_cip_453.o
2	2	obj-y += errata.o

arch/riscv/include/asm/alternative-macros.h+2−2

@@ -51,7 +51,7 @@ · 50 unmodified lines
51	51	REG_ASM " " newlen "\n" \
52	52	".word " errata_id "\n"
53	53
54		−#define ALT_NEW_CONSTENT(vendor_id, errata_id, enable, new_c) \
	54	+#define ALT_NEW_CONTENT(vendor_id, errata_id, enable, new_c) \
55	55	".if " __stringify(enable) " == 1\n" \
56	56	".pushsection .alternative, \"a\"\n" \
57	57	ALT_ENTRY("886b", "888f", __stringify(vendor_id), __stringify(errata_id), "889f - 888f") \
@@ -69,7 +69,7 @@ · 11 unmodified lines
69	69	"886 :\n" \
70	70	old_c "\n" \
71	71	"887 :\n" \
72		− ALT_NEW_CONSTENT(vendor_id, errata_id, enable, new_c)
	72	+ ALT_NEW_CONTENT(vendor_id, errata_id, enable, new_c)
73	73
74	74	#define _ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, CONFIG_k) \
75	75	__ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, IS_ENABLED(CONFIG_k))

arch/riscv/include/asm/kexec.h+2−2

@@ -42,8 +42,8 @@ struct kimage_arch { · 41 unmodified lines
42	42	unsigned long fdt_addr;
43	43	};
44	44
45		−const extern unsigned char riscv_kexec_relocate[];
46		−const extern unsigned int riscv_kexec_relocate_size;
	45	+extern const unsigned char riscv_kexec_relocate[];
	46	+extern const unsigned int riscv_kexec_relocate_size;
47	47
48	48	typedef void (*riscv_kexec_method)(unsigned long first_ind_entry,
49	49	unsigned long jump_addr,

arch/riscv/include/asm/pgtable.h+2−3

@@ -30,9 +30,8 @@ · 29 unmodified lines
30	30
31	31	#define BPF_JIT_REGION_SIZE (SZ_128M)
32	32	#ifdef CONFIG_64BIT
33		−/* KASLR should leave at least 128MB for BPF after the kernel */
34		−#define BPF_JIT_REGION_START PFN_ALIGN((unsigned long)&_end)
35		−#define BPF_JIT_REGION_END (BPF_JIT_REGION_START + BPF_JIT_REGION_SIZE)
	33	+#define BPF_JIT_REGION_START (BPF_JIT_REGION_END - BPF_JIT_REGION_SIZE)
	34	+#define BPF_JIT_REGION_END (MODULES_END)
36	35	#else
37	36	#define BPF_JIT_REGION_START (PAGE_OFFSET - BPF_JIT_REGION_SIZE)
38	37	#define BPF_JIT_REGION_END (VMALLOC_END)

arch/riscv/kernel/machine_kexec.c+6−5

@@ -14,8 +14,9 @@ · 13 unmodified lines
14	14	#include <asm/set_memory.h> /* For set_memory_x() */
15	15	#include <linux/compiler.h> /* For unreachable() */
16	16	#include <linux/cpu.h> /* For cpu_down() */
	17	+#include <linux/reboot.h>
17	18
18		−/**
	19	+/*
19	20	* kexec_image_info - Print received image details
20	21	*/
21	22	static void
@@ -39,7 +40,7 @@ kexec_image_info(const struct kimage *image) · 17 unmodified lines
39	40	}
40	41	}
41	42
42		−/**
	43	+/*
43	44	* machine_kexec_prepare - Initialize kexec
44	45	*
45	46	* This function is called from do_kexec_load, when the user has
@@ -100,7 +101,7 @@ machine_kexec_prepare(struct kimage *image) · 54 unmodified lines
100	101	}
101	102
102	103
103		−/**
	104	+/*
104	105	* machine_kexec_cleanup - Cleanup any leftovers from
105	106	* machine_kexec_prepare
106	107	*
@@ -135,7 +136,7 @@ void machine_shutdown(void) · 28 unmodified lines
135	136	#endif
136	137	}
137	138
138		−/**
	139	+/*
139	140	* machine_crash_shutdown - Prepare to kexec after a kernel crash
140	141	*
141	142	* This function is called by crash_kexec just before machine_kexec
@@ -151,7 +152,7 @@ machine_crash_shutdown(struct pt_regs *regs) · 9 unmodified lines
151	152	pr_info("Starting crashdump kernel...\n");
152	153	}
153	154
154		−/**
	155	+/*
155	156	* machine_kexec - Jump to the loaded kimage
156	157	*
157	158	* This function is called by kernel_kexec which is called by the

arch/riscv/kernel/probes/kprobes.c+2−0

@@ -84,6 +84,7 @@ int __kprobes arch_prepare_kprobe(struct kprobe *p) · 83 unmodified lines
84	84	return 0;
85	85	}
86	86
	87	+#ifdef CONFIG_MMU
87	88	void *alloc_insn_page(void)
88	89	{
89	90	return __vmalloc_node_range(PAGE_SIZE, 1, VMALLOC_START, VMALLOC_END,
@@ -91,6 +92,7 @@ void *alloc_insn_page(void) · 1 unmodified line
91	92	VM_FLUSH_RESET_PERMS, NUMA_NO_NODE,
92	93	__builtin_return_address(0));
93	94	}
	95	+#endif
94	96
95	97	/* install breakpoint in text */
96	98	void __kprobes arch_arm_kprobe(struct kprobe *p)

arch/riscv/kernel/setup.c+2−2

@@ -231,13 +231,13 @@ static void __init init_resources(void) · 230 unmodified lines
231	231
232	232	/* Clean-up any unused pre-allocated resources */
233	233	mem_res_sz = (num_resources - res_idx + 1) * sizeof(*mem_res);
234		− memblock_free((phys_addr_t) mem_res, mem_res_sz);
	234	+ memblock_free(__pa(mem_res), mem_res_sz);
235	235	return;
236	236
237	237	error:
238	238	/* Better an empty resource tree than an inconsistent one */
239	239	release_child_resources(&iomem_resource);
240		− memblock_free((phys_addr_t) mem_res, mem_res_sz);
	240	+ memblock_free(__pa(mem_res), mem_res_sz);
241	241	}
242	242
243	243

arch/riscv/kernel/stacktrace.c+7−7

@@ -27,10 +27,10 @@ void notrace walk_stackframe(struct task_struct task, struct pt_regs regs, · 26 unmodified lines
27	27	fp = frame_pointer(regs);
28	28	sp = user_stack_pointer(regs);
29	29	pc = instruction_pointer(regs);
30		− } else if (task == NULL \|\| task == current) {
31		− fp = (unsigned long)__builtin_frame_address(0);
32		− sp = sp_in_global;
33		− pc = (unsigned long)walk_stackframe;
	30	+ } else if (task == current) {
	31	+ fp = (unsigned long)__builtin_frame_address(1);
	32	+ sp = (unsigned long)__builtin_frame_address(0);
	33	+ pc = (unsigned long)__builtin_return_address(0);
34	34	} else {
35	35	/* task blocked in __switch_to */
36	36	fp = task->thread.s[0];
@@ -106,15 +106,15 @@ static bool print_trace_address(void *arg, unsigned long pc) · 69 unmodified lines
106	106	return true;
107	107	}
108	108
109		−void dump_backtrace(struct pt_regs regs, struct task_struct task,
	109	+noinline void dump_backtrace(struct pt_regs regs, struct task_struct task,
110	110	const char *loglvl)
111	111	{
112		− pr_cont("%sCall Trace:\n", loglvl);
113	112	walk_stackframe(task, regs, print_trace_address, (void *)loglvl);
114	113	}
115	114
116	115	void show_stack(struct task_struct task, unsigned long sp, const char *loglvl)
117	116	{
	117	+ pr_cont("%sCall Trace:\n", loglvl);
118	118	dump_backtrace(NULL, task, loglvl);
119	119	}
120	120
@@ -139,7 +139,7 @@ unsigned long get_wchan(struct task_struct *task) · 18 unmodified lines
139	139
140	140	#ifdef CONFIG_STACKTRACE
141	141
142		−void arch_stack_walk(stack_trace_consume_fn consume_entry, void *cookie,
	142	+noinline void arch_stack_walk(stack_trace_consume_fn consume_entry, void *cookie,
143	143	struct task_struct task, struct pt_regs regs)
144	144	{
145	145	walk_stackframe(task, regs, consume_entry, cookie);

arch/riscv/kernel/traps.c+9−4

@@ -86,8 +86,13 @@ static void do_trap_error(struct pt_regs *regs, int signo, int code, · 85 unmodified lines
86	86	}
87	87	}
88	88
	89	+#if defined (CONFIG_XIP_KERNEL) && defined (CONFIG_RISCV_ERRATA_ALTERNATIVE)
	90	+#define __trap_section __section(".xip.traps")
	91	+#else
	92	+#define __trap_section
	93	+#endif
89	94	#define DO_ERROR_INFO(name, signo, code, str) \
90		−asmlinkage __visible void name(struct pt_regs *regs) \
	95	+asmlinkage __visible __trap_section void name(struct pt_regs *regs) \
91	96	{ \
92	97	do_trap_error(regs, signo, code, regs->epc, "Oops - " str); \
93	98	}
@@ -111,7 +116,7 @@ DO_ERROR_INFO(do_trap_store_misaligned, · 17 unmodified lines
111	116	int handle_misaligned_load(struct pt_regs *regs);
112	117	int handle_misaligned_store(struct pt_regs *regs);
113	118
114		−asmlinkage void do_trap_load_misaligned(struct pt_regs *regs)
	119	+asmlinkage void __trap_section do_trap_load_misaligned(struct pt_regs *regs)
115	120	{
116	121	if (!handle_misaligned_load(regs))
117	122	return;
@@ -119,7 +124,7 @@ asmlinkage void do_trap_load_misaligned(struct pt_regs *regs) · 1 unmodified line
119	124	"Oops - load address misaligned");
120	125	}
121	126
122		−asmlinkage void do_trap_store_misaligned(struct pt_regs *regs)
	127	+asmlinkage void __trap_section do_trap_store_misaligned(struct pt_regs *regs)
123	128	{
124	129	if (!handle_misaligned_store(regs))
125	130	return;
@@ -146,7 +151,7 @@ static inline unsigned long get_break_insn_length(unsigned long pc) · 20 unmodified lines
146	151	return GET_INSN_LENGTH(insn);
147	152	}
148	153
149		−asmlinkage __visible void do_trap_break(struct pt_regs *regs)
	154	+asmlinkage __visible __trap_section void do_trap_break(struct pt_regs *regs)
150	155	{
151	156	#ifdef CONFIG_KPROBES
152	157	if (kprobe_single_step_handler(regs))

arch/riscv/kernel/vmlinux-xip.lds.S+14−1

@@ -99,9 +99,22 @@ SECTIONS · 98 unmodified lines
99	99	}
100	100	PERCPU_SECTION(L1_CACHE_BYTES)
101	101
102		− . = ALIGN(PAGE_SIZE);
	102	+ . = ALIGN(8);
	103	+ .alternative : {
	104	+ __alt_start = .;
	105	+ *(.alternative)
	106	+ __alt_end = .;
	107	+ }
103	108	__init_end = .;
104	109
	110	+ . = ALIGN(16);
	111	+ .xip.traps : {
	112	+ __xip_traps_start = .;
	113	+ *(.xip.traps)
	114	+ __xip_traps_end = .;
	115	+ }
	116	+
	117	+ . = ALIGN(PAGE_SIZE);
105	118	.sdata : {
106	119	__global_pointer$ = . + 0x800;
107	120	(.sdata)

arch/riscv/mm/init.c+6−2

@@ -746,14 +746,18 @@ void __init protect_kernel_text_data(void) · 745 unmodified lines
746	746	unsigned long init_data_start = (unsigned long)__init_data_begin;
747	747	unsigned long rodata_start = (unsigned long)__start_rodata;
748	748	unsigned long data_start = (unsigned long)_data;
749		− unsigned long max_low = (unsigned long)(__va(PFN_PHYS(max_low_pfn)));
	749	+#if defined(CONFIG_64BIT) && defined(CONFIG_MMU)
	750	+ unsigned long end_va = kernel_virt_addr + load_sz;
	751	+#else
	752	+ unsigned long end_va = (unsigned long)(__va(PFN_PHYS(max_low_pfn)));
	753	+#endif
750	754
751	755	set_memory_ro(text_start, (init_text_start - text_start) >> PAGE_SHIFT);
752	756	set_memory_ro(init_text_start, (init_data_start - init_text_start) >> PAGE_SHIFT);
753	757	set_memory_nx(init_data_start, (rodata_start - init_data_start) >> PAGE_SHIFT);
754	758	/* rodata section is marked readonly in mark_rodata_ro */
755	759	set_memory_nx(rodata_start, (data_start - rodata_start) >> PAGE_SHIFT);
756		− set_memory_nx(data_start, (max_low - data_start) >> PAGE_SHIFT);
	760	+ set_memory_nx(data_start, (end_va - data_start) >> PAGE_SHIFT);
757	761	}
758	762
759	763	void mark_rodata_ro(void)

arch/riscv/mm/kasan_init.c+5−5

@@ -169,7 +169,7 @@ static void __init kasan_shallow_populate(void start, void end) · 168 unmodified lines
169	169
170	170	void __init kasan_init(void)
171	171	{
172		− phys_addr_t _start, _end;
	172	+ phys_addr_t p_start, p_end;
173	173	u64 i;
174	174
175	175	/*
@@ -189,9 +189,9 @@ void __init kasan_init(void) · 13 unmodified lines
189	189	(void )kasan_mem_to_shadow((void )VMALLOC_END));
190	190
191	191	/* Populate the linear mapping */
192		− for_each_mem_range(i, &_start, &_end) {
193		− void start = (void )__va(_start);
194		− void end = (void )__va(_end);
	192	+ for_each_mem_range(i, &p_start, &p_end) {
	193	+ void start = (void )__va(p_start);
	194	+ void end = (void )__va(p_end);
195	195
196	196	if (start >= end)
197	197	break;
@@ -201,7 +201,7 @@ void __init kasan_init(void) · 3 unmodified lines
201	201
202	202	/* Populate kernel, BPF, modules mapping */
203	203	kasan_populate(kasan_mem_to_shadow((const void *)MODULES_VADDR),
204		− kasan_mem_to_shadow((const void *)BPF_JIT_REGION_END));
	204	+ kasan_mem_to_shadow((const void *)MODULES_VADDR + SZ_2G));
205	205
206	206	for (i = 0; i < PTRS_PER_PTE; i++)
207	207	set_pte(&kasan_early_shadow_pte[i],

arch/s390/kernel/entry.S+2−2

@@ -651,9 +651,9 @@ ENDPROC(stack_overflow) · 650 unmodified lines
651	651	.Lcleanup_sie_mcck:
652	652	larl %r13,.Lsie_entry
653	653	slgr %r9,%r13
654		− larl %r13,.Lsie_skip
	654	+ lghi %r13,.Lsie_skip - .Lsie_entry
655	655	clgr %r9,%r13
656		− jh .Lcleanup_sie_int
	656	+ jhe .Lcleanup_sie_int
657	657	oi __LC_CPU_FLAGS+7, _CIF_MCCK_GUEST
658	658	.Lcleanup_sie_int:
659	659	BPENTER __SF_SIE_FLAGS(%r15),(_TIF_ISOLATE_BP\|_TIF_ISOLATE_BP_GUEST)

arch/s390/kernel/syscalls/syscall.tbl+1−1

@@ -445,7 +445,7 @@ · 444 unmodified lines
445	445	440 common process_madvise sys_process_madvise sys_process_madvise
446	446	441 common epoll_pwait2 sys_epoll_pwait2 compat_sys_epoll_pwait2
447	447	442 common mount_setattr sys_mount_setattr sys_mount_setattr
448		−443 common quotactl_path sys_quotactl_path sys_quotactl_path
	448	+# 443 reserved for quotactl_path
449	449	444 common landlock_create_ruleset sys_landlock_create_ruleset sys_landlock_create_ruleset
450	450	445 common landlock_add_rule sys_landlock_add_rule sys_landlock_add_rule
451	451	446 common landlock_restrict_self sys_landlock_restrict_self sys_landlock_restrict_self

arch/sh/kernel/syscalls/syscall.tbl+1−1

@@ -445,7 +445,7 @@ · 444 unmodified lines
445	445	440 common process_madvise sys_process_madvise
446	446	441 common epoll_pwait2 sys_epoll_pwait2
447	447	442 common mount_setattr sys_mount_setattr
448		−443 common quotactl_path sys_quotactl_path
	448	+# 443 reserved for quotactl_path
449	449	444 common landlock_create_ruleset sys_landlock_create_ruleset
450	450	445 common landlock_add_rule sys_landlock_add_rule
451	451	446 common landlock_restrict_self sys_landlock_restrict_self

arch/sh/kernel/traps.c+0−1

@@ -180,7 +180,6 @@ static inline void arch_ftrace_nmi_exit(void) { } · 179 unmodified lines
180	180
181	181	BUILD_TRAP_HANDLER(nmi)
182	182	{
183		− unsigned int cpu = smp_processor_id();
184	183	TRAP_HANDLER_DECL;
185	184
186	185	arch_ftrace_nmi_enter();

arch/sparc/kernel/syscalls/syscall.tbl+1−1

@@ -488,7 +488,7 @@ · 487 unmodified lines
488	488	440 common process_madvise sys_process_madvise
489	489	441 common epoll_pwait2 sys_epoll_pwait2 compat_sys_epoll_pwait2
490	490	442 common mount_setattr sys_mount_setattr
491		−443 common quotactl_path sys_quotactl_path
	491	+# 443 reserved for quotactl_path
492	492	444 common landlock_create_ruleset sys_landlock_create_ruleset
493	493	445 common landlock_add_rule sys_landlock_add_rule
494	494	446 common landlock_restrict_self sys_landlock_restrict_self

arch/x86/Makefile+7−6

@@ -178,11 +178,6 @@ ifeq ($(ACCUMULATE_OUTGOING_ARGS), 1) · 177 unmodified lines
178	178	KBUILD_CFLAGS += $(call cc-option,-maccumulate-outgoing-args,)
179	179	endif
180	180
181		−ifdef CONFIG_LTO_CLANG
182		−KBUILD_LDFLAGS += -plugin-opt=-code-model=kernel \
183		− -plugin-opt=-stack-alignment=$(if $(CONFIG_X86_32),4,8)
184		−endif
185		−
186	181	# Workaround for a gcc prelease that unfortunately was shipped in a suse release
187	182	KBUILD_CFLAGS += -Wno-sign-compare
188	183	#
@@ -202,7 +197,13 @@ ifdef CONFIG_RETPOLINE · 13 unmodified lines
202	197	endif
203	198	endif
204	199
205		−KBUILD_LDFLAGS := -m elf_$(UTS_MACHINE)
	200	+KBUILD_LDFLAGS += -m elf_$(UTS_MACHINE)
	201	+
	202	+ifdef CONFIG_LTO_CLANG
	203	+ifeq ($(shell test $(CONFIG_LLD_VERSION) -lt 130000; echo $$?),0)
	204	+KBUILD_LDFLAGS += -plugin-opt=-stack-alignment=$(if $(CONFIG_X86_32),4,8)
	205	+endif
	206	+endif
206	207
207	208	ifdef CONFIG_X86_NEED_RELOCS
208	209	LDFLAGS_vmlinux := --emit-relocs --discard-none

arch/x86/boot/compressed/Makefile+4−3

@@ -30,6 +30,7 @@ targets := vmlinux vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 vmlinux.bin.lzma \ · 29 unmodified lines
30	30
31	31	KBUILD_CFLAGS := -m$(BITS) -O2
32	32	KBUILD_CFLAGS += -fno-strict-aliasing -fPIE
	33	+KBUILD_CFLAGS += -Wundef
33	34	KBUILD_CFLAGS += -DDISABLE_BRANCH_PROFILING
34	35	cflags-$(CONFIG_X86_32) := -march=i386
35	36	cflags-$(CONFIG_X86_64) := -mcmodel=small -mno-red-zone
@@ -48,10 +49,10 @@ KBUILD_CFLAGS += $(call as-option,-Wa$(comma)-mrelax-relocations=no) · 12 unmodified lines
48	49	KBUILD_CFLAGS += -include $(srctree)/include/linux/hidden.h
49	50	KBUILD_CFLAGS += $(CLANG_FLAGS)
50	51
51		−# sev-es.c indirectly inludes inat-table.h which is generated during
	52	+# sev.c indirectly inludes inat-table.h which is generated during
52	53	# compilation and stored in $(objtree). Add the directory to the includes so
53	54	# that the compiler finds it even with out-of-tree builds (make O=/some/path).
54		−CFLAGS_sev-es.o += -I$(objtree)/arch/x86/lib/
	55	+CFLAGS_sev.o += -I$(objtree)/arch/x86/lib/
55	56
56	57	KBUILD_AFLAGS := $(KBUILD_CFLAGS) -D__ASSEMBLY__
57	58	GCOV_PROFILE := n
@@ -93,7 +94,7 @@ ifdef CONFIG_X86_64 · 35 unmodified lines
93	94	vmlinux-objs-y += $(obj)/idt_64.o $(obj)/idt_handlers_64.o
94	95	vmlinux-objs-y += $(obj)/mem_encrypt.o
95	96	vmlinux-objs-y += $(obj)/pgtable_64.o
96		− vmlinux-objs-$(CONFIG_AMD_MEM_ENCRYPT) += $(obj)/sev-es.o
	97	+ vmlinux-objs-$(CONFIG_AMD_MEM_ENCRYPT) += $(obj)/sev.o
97	98	endif
98	99
99	100	vmlinux-objs-$(CONFIG_ACPI) += $(obj)/acpi.o

arch/x86/boot/compressed/misc.c+1−1

@@ -172,7 +172,7 @@ void __puthex(unsigned long value) · 171 unmodified lines
172	172	}
173	173	}
174	174
175		−#if CONFIG_X86_NEED_RELOCS
	175	+#ifdef CONFIG_X86_NEED_RELOCS
176	176	static void handle_relocations(void *output, unsigned long output_len,
177	177	unsigned long virt_addr)
178	178	{

arch/x86/boot/compressed/misc.h+1−1

@@ -79,7 +79,7 @@ struct mem_vector { · 78 unmodified lines
79	79	u64 size;
80	80	};
81	81
82		−#if CONFIG_RANDOMIZE_BASE
	82	+#ifdef CONFIG_RANDOMIZE_BASE
83	83	/* kaslr.c */
84	84	void choose_random_location(unsigned long input,
85	85	unsigned long input_size,

arch/x86/boot/compressed/sev.crenamed from arch/x86/boot/compressed/sev-es.c+2−2

@@ -13,7 +13,7 @@ · 12 unmodified lines
13	13	#include "misc.h"
14	14
15	15	#include <asm/pgtable_types.h>
16		−#include <asm/sev-es.h>
	16	+#include <asm/sev.h>
17	17	#include <asm/trapnr.h>
18	18	#include <asm/trap_pf.h>
19	19	#include <asm/msr-index.h>
@@ -117,7 +117,7 @@ static enum es_result vc_read_mem(struct es_em_ctxt *ctxt, · 97 unmodified lines
117	117	#include "../../lib/insn.c"
118	118
119	119	/* Include code for early handlers */
120		−#include "../../kernel/sev-es-shared.c"
	120	+#include "../../kernel/sev-shared.c"
121	121
122	122	static bool early_setup_sev_es(void)
123	123	{

arch/x86/entry/syscalls/syscall_32.tbl+1−1

@@ -447,7 +447,7 @@ · 446 unmodified lines
447	447	440 i386 process_madvise sys_process_madvise
448	448	441 i386 epoll_pwait2 sys_epoll_pwait2 compat_sys_epoll_pwait2
449	449	442 i386 mount_setattr sys_mount_setattr
450		−443 i386 quotactl_path sys_quotactl_path
	450	+# 443 reserved for quotactl_path
451	451	444 i386 landlock_create_ruleset sys_landlock_create_ruleset
452	452	445 i386 landlock_add_rule sys_landlock_add_rule
453	453	446 i386 landlock_restrict_self sys_landlock_restrict_self

arch/x86/entry/syscalls/syscall_64.tbl+1−1

@@ -364,7 +364,7 @@ · 363 unmodified lines
364	364	440 common process_madvise sys_process_madvise
365	365	441 common epoll_pwait2 sys_epoll_pwait2
366	366	442 common mount_setattr sys_mount_setattr
367		−443 common quotactl_path sys_quotactl_path
	367	+# 443 reserved for quotactl_path
368	368	444 common landlock_create_ruleset sys_landlock_create_ruleset
369	369	445 common landlock_add_rule sys_landlock_add_rule
370	370	446 common landlock_restrict_self sys_landlock_restrict_self

arch/x86/events/core.c+4−2

@@ -396,10 +396,12 @@ int x86_reserve_hardware(void) · 395 unmodified lines
396	396	if (!atomic_inc_not_zero(&pmc_refcount)) {
397	397	mutex_lock(&pmc_reserve_mutex);
398	398	if (atomic_read(&pmc_refcount) == 0) {
399		− if (!reserve_pmc_hardware())
	399	+ if (!reserve_pmc_hardware()) {
400	400	err = -EBUSY;
401		− else
	401	+ } else {
402	402	reserve_ds_buffers();
	403	+ reserve_lbr_buffers();
	404	+ }
403	405	}
404	406	if (!err)
405	407	atomic_inc(&pmc_refcount);

arch/x86/events/intel/core.c+1−1

@@ -6253,7 +6253,7 @@ __init int intel_pmu_init(void) · 6252 unmodified lines
6253	6253	* Check all LBT MSR here.
6254	6254	* Disable LBR access if any LBR MSRs can not be accessed.
6255	6255	*/
6256		− if (x86_pmu.lbr_nr && !check_msr(x86_pmu.lbr_tos, 0x3UL))
	6256	+ if (x86_pmu.lbr_tos && !check_msr(x86_pmu.lbr_tos, 0x3UL))
6257	6257	x86_pmu.lbr_nr = 0;
6258	6258	for (i = 0; i < x86_pmu.lbr_nr; i++) {
6259	6259	if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) &&

arch/x86/events/intel/lbr.c+20−6

@@ -658,7 +658,6 @@ static inline bool branch_user_callstack(unsigned br_sel) · 657 unmodified lines
658	658
659	659	void intel_pmu_lbr_add(struct perf_event *event)
660	660	{
661		− struct kmem_cache *kmem_cache = event->pmu->task_ctx_cache;
662	661	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
663	662
664	663	if (!x86_pmu.lbr_nr)
@@ -696,11 +695,6 @@ void intel_pmu_lbr_add(struct perf_event *event) · 31 unmodified lines
696	695	perf_sched_cb_inc(event->ctx->pmu);
697	696	if (!cpuc->lbr_users++ && !event->total_time_running)
698	697	intel_pmu_lbr_reset();
699		−
700		− if (static_cpu_has(X86_FEATURE_ARCH_LBR) &&
701		− kmem_cache && !cpuc->lbr_xsave &&
702		− (cpuc->lbr_users != cpuc->lbr_pebs_users))
703		− cpuc->lbr_xsave = kmem_cache_alloc(kmem_cache, GFP_KERNEL);
704	698	}
705	699
706	700	void release_lbr_buffers(void)
@@ -722,6 +716,26 @@ void release_lbr_buffers(void) · 15 unmodified lines
722	716	}
723	717	}
724	718
	719	+void reserve_lbr_buffers(void)
	720	+{
	721	+ struct kmem_cache *kmem_cache;
	722	+ struct cpu_hw_events *cpuc;
	723	+ int cpu;
	724	+
	725	+ if (!static_cpu_has(X86_FEATURE_ARCH_LBR))
	726	+ return;
	727	+
	728	+ for_each_possible_cpu(cpu) {
	729	+ cpuc = per_cpu_ptr(&cpu_hw_events, cpu);
	730	+ kmem_cache = x86_get_pmu(cpu)->task_ctx_cache;
	731	+ if (!kmem_cache \|\| cpuc->lbr_xsave)
	732	+ continue;
	733	+
	734	+ cpuc->lbr_xsave = kmem_cache_alloc_node(kmem_cache, GFP_KERNEL,
	735	+ cpu_to_node(cpu));
	736	+ }
	737	+}
	738	+
725	739	void intel_pmu_lbr_del(struct perf_event *event)
726	740	{
727	741	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);

arch/x86/events/intel/uncore_snbep.c+6−3

@@ -1406,6 +1406,8 @@ static int snbep_pci2phy_map_init(int devid, int nodeid_loc, int idmap_loc, bool · 1405 unmodified lines
1406	1406	die_id = i;
1407	1407	else
1408	1408	die_id = topology_phys_to_logical_pkg(i);
	1409	+ if (die_id < 0)
	1410	+ die_id = -ENODEV;
1409	1411	map->pbus_to_dieid[bus] = die_id;
1410	1412	break;
1411	1413	}
@@ -1452,14 +1454,14 @@ static int snbep_pci2phy_map_init(int devid, int nodeid_loc, int idmap_loc, bool · 40 unmodified lines
1452	1454	i = -1;
1453	1455	if (reverse) {
1454	1456	for (bus = 255; bus >= 0; bus--) {
1455		− if (map->pbus_to_dieid[bus] >= 0)
	1457	+ if (map->pbus_to_dieid[bus] != -1)
1456	1458	i = map->pbus_to_dieid[bus];
1457	1459	else
1458	1460	map->pbus_to_dieid[bus] = i;
1459	1461	}
1460	1462	} else {
1461	1463	for (bus = 0; bus <= 255; bus++) {
1462		− if (map->pbus_to_dieid[bus] >= 0)
	1464	+ if (map->pbus_to_dieid[bus] != -1)
1463	1465	i = map->pbus_to_dieid[bus];
1464	1466	else
1465	1467	map->pbus_to_dieid[bus] = i;
@@ -5097,9 +5099,10 @@ static struct intel_uncore_type icx_uncore_m2m = { · 3631 unmodified lines
5097	5099	.perf_ctr = SNR_M2M_PCI_PMON_CTR0,
5098	5100	.event_ctl = SNR_M2M_PCI_PMON_CTL0,
5099	5101	.event_mask = SNBEP_PMON_RAW_EVENT_MASK,
	5102	+ .event_mask_ext = SNR_M2M_PCI_PMON_UMASK_EXT,
5100	5103	.box_ctl = SNR_M2M_PCI_PMON_BOX_CTL,
5101	5104	.ops = &snr_m2m_uncore_pci_ops,
5102		− .format_group = &skx_uncore_format_group,
	5105	+ .format_group = &snr_m2m_uncore_format_group,
5103	5106	};
5104	5107
5105	5108	static struct attribute *icx_upi_uncore_formats_attr[] = {

arch/x86/events/perf_event.h+6−0

@@ -1244,6 +1244,8 @@ void reserve_ds_buffers(void); · 1243 unmodified lines
1244	1244
1245	1245	void release_lbr_buffers(void);
1246	1246
	1247	+void reserve_lbr_buffers(void);
	1248	+
1247	1249	extern struct event_constraint bts_constraint;
1248	1250	extern struct event_constraint vlbr_constraint;
1249	1251
@@ -1393,6 +1395,10 @@ static inline void release_lbr_buffers(void) · 143 unmodified lines
1393	1395	{
1394	1396	}
1395	1397
	1398	+static inline void reserve_lbr_buffers(void)
	1399	+{
	1400	+}
	1401	+
1396	1402	static inline int intel_pmu_init(void)
1397	1403	{
1398	1404	return 0;

arch/x86/include/asm/apic.h+1−0

@@ -174,6 +174,7 @@ static inline int apic_is_clustered_box(void) · 173 unmodified lines
174	174	extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask);
175	175	extern void lapic_assign_system_vectors(void);
176	176	extern void lapic_assign_legacy_vector(unsigned int isairq, bool replace);
	177	+extern void lapic_update_legacy_vectors(void);
177	178	extern void lapic_online(void);
178	179	extern void lapic_offline(void);
179	180	extern bool apic_needs_pit(void);

arch/x86/include/asm/disabled-features.h+2−5

@@ -56,11 +56,8 @@ · 55 unmodified lines
56	56	# define DISABLE_PTI (1 << (X86_FEATURE_PTI & 31))
57	57	#endif
58	58
59		−#ifdef CONFIG_IOMMU_SUPPORT
60		−# define DISABLE_ENQCMD 0
61		−#else
62		−# define DISABLE_ENQCMD (1 << (X86_FEATURE_ENQCMD & 31))
63		−#endif
	59	+/* Force disable because it's broken beyond repair */
	60	+#define DISABLE_ENQCMD (1 << (X86_FEATURE_ENQCMD & 31))
64	61
65	62	#ifdef CONFIG_X86_SGX
66	63	# define DISABLE_SGX 0

arch/x86/include/asm/fpu/api.h+1−5

@@ -106,10 +106,6 @@ extern int cpu_has_xfeatures(u64 xfeatures_mask, const char **feature_name); · 105 unmodified lines
106	106	*/
107	107	#define PASID_DISABLED 0
108	108
109		−#ifdef CONFIG_IOMMU_SUPPORT
110		−/* Update current's PASID MSR/state by mm's PASID. */
111		−void update_pasid(void);
112		−#else
113	109	static inline void update_pasid(void) { }
114		−#endif
	110	+
115	111	#endif /* _ASM_X86_FPU_API_H */

arch/x86/include/asm/fpu/internal.h+10−10

@@ -578,19 +578,19 @@ static inline void switch_fpu_finish(struct fpu *new_fpu) · 577 unmodified lines
578	578	* PKRU state is switched eagerly because it needs to be valid before we
579	579	* return to userland e.g. for a copy_to_user() operation.
580	580	*/
581		− if (current->mm) {
	581	+ if (!(current->flags & PF_KTHREAD)) {
	582	+ /*
	583	+ * If the PKRU bit in xsave.header.xfeatures is not set,
	584	+ * then the PKRU component was in init state, which means
	585	+ * XRSTOR will set PKRU to 0. If the bit is not set then
	586	+ * get_xsave_addr() will return NULL because the PKRU value
	587	+ * in memory is not valid. This means pkru_val has to be
	588	+ * set to 0 and not to init_pkru_value.
	589	+ */
582	590	pk = get_xsave_addr(&new_fpu->state.xsave, XFEATURE_PKRU);
583		− if (pk)
584		− pkru_val = pk->pkru;
	591	+ pkru_val = pk ? pk->pkru : 0;
585	592	}
586	593	__write_pkru(pkru_val);
587		−
588		− /*
589		− * Expensive PASID MSR write will be avoided in update_pasid() because
590		− * TIF_NEED_FPU_LOAD was set. And the PASID state won't be updated
591		− * unless it's different from mm->pasid to reduce overhead.
592		− */
593		− update_pasid();
594	594	}
595	595
596	596	#endif /* _ASM_X86_FPU_INTERNAL_H */

arch/x86/include/asm/kvm-x86-ops.h+1−0

@@ -99,6 +99,7 @@ KVM_X86_OP_NULL(post_block) · 98 unmodified lines
99	99	KVM_X86_OP_NULL(vcpu_blocking)
100	100	KVM_X86_OP_NULL(vcpu_unblocking)
101	101	KVM_X86_OP_NULL(update_pi_irte)
	102	+KVM_X86_OP_NULL(start_assignment)
102	103	KVM_X86_OP_NULL(apicv_post_state_restore)
103	104	KVM_X86_OP_NULL(dy_apicv_has_pending_interrupt)
104	105	KVM_X86_OP_NULL(set_hv_timer)

arch/x86/include/asm/kvm_host.h+13−3

@@ -113,6 +113,7 @@ · 112 unmodified lines
113	113	#define VALID_PAGE(x) ((x) != INVALID_PAGE)
114	114
115	115	#define UNMAPPED_GVA (~(gpa_t)0)
	116	+#define INVALID_GPA (~(gpa_t)0)
116	117
117	118	/* KVM Hugepage definitions for x86 */
118	119	#define KVM_MAX_HUGEPAGE_LEVEL PG_LEVEL_1G
@@ -199,6 +200,7 @@ enum x86_intercept_stage; · 80 unmodified lines
199	200
200	201	#define KVM_NR_DB_REGS 4
201	202
	203	+#define DR6_BUS_LOCK (1 << 11)
202	204	#define DR6_BD (1 << 13)
203	205	#define DR6_BS (1 << 14)
204	206	#define DR6_BT (1 << 15)
@@ -212,7 +214,7 @@ enum x86_intercept_stage; · 7 unmodified lines
212	214	* DR6_ACTIVE_LOW is also used as the init/reset value for DR6.
213	215	*/
214	216	#define DR6_ACTIVE_LOW 0xffff0ff0
215		−#define DR6_VOLATILE 0x0001e00f
	217	+#define DR6_VOLATILE 0x0001e80f
216	218	#define DR6_FIXED_1 (DR6_ACTIVE_LOW & ~DR6_VOLATILE)
217	219
218	220	#define DR7_BP_EN_MASK 0x000000ff
@@ -407,7 +409,7 @@ struct kvm_mmu { · 188 unmodified lines
407	409	u32 pkru_mask;
408	410
409	411	u64 *pae_root;
410		− u64 *lm_root;
	412	+ u64 *pml4_root;
411	413
412	414	/*
413	415	* check zero bits on shadow page table entries, these
@@ -1350,6 +1352,7 @@ struct kvm_x86_ops { · 936 unmodified lines
1350	1352
1351	1353	int (update_pi_irte)(struct kvm kvm, unsigned int host_irq,
1352	1354	uint32_t guest_irq, bool set);
	1355	+ void (start_assignment)(struct kvm kvm);
1353	1356	void (apicv_post_state_restore)(struct kvm_vcpu vcpu);
1354	1357	bool (dy_apicv_has_pending_interrupt)(struct kvm_vcpu vcpu);
1355	1358
@@ -1417,6 +1420,7 @@ struct kvm_arch_async_pf { · 61 unmodified lines
1417	1420	bool direct_map;
1418	1421	};
1419	1422
	1423	+extern u32 __read_mostly kvm_nr_uret_msrs;
1420	1424	extern u64 __read_mostly host_efer;
1421	1425	extern bool __read_mostly allow_smaller_maxphyaddr;
1422	1426	extern struct kvm_x86_ops kvm_x86_ops;
@@ -1775,9 +1779,15 @@ int kvm_pv_send_ipi(struct kvm *kvm, unsigned long ipi_bitmap_low, · 352 unmodified lines
1775	1779	unsigned long ipi_bitmap_high, u32 min,
1776	1780	unsigned long icr, int op_64_bit);
1777	1781
1778		−void kvm_define_user_return_msr(unsigned index, u32 msr);
	1782	+int kvm_add_user_return_msr(u32 msr);
	1783	+int kvm_find_user_return_msr(u32 msr);
1779	1784	int kvm_set_user_return_msr(unsigned index, u64 val, u64 mask);
1780	1785
	1786	+static inline bool kvm_is_supported_user_return_msr(u32 msr)
	1787	+{
	1788	+ return kvm_find_user_return_msr(msr) >= 0;
	1789	+}
	1790	+
1781	1791	u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc);
1782	1792	u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc);
1783	1793

arch/x86/include/asm/kvm_para.h+2−8

@@ -7,8 +7,6 @@ · 6 unmodified lines
7	7	#include <linux/interrupt.h>
8	8	#include <uapi/asm/kvm_para.h>
9	9
10		−extern void kvmclock_init(void);
11		−
12	10	#ifdef CONFIG_KVM_GUEST
13	11	bool kvm_check_and_clear_guest_paused(void);
14	12	#else
@@ -86,13 +84,14 @@ static inline long kvm_hypercall4(unsigned int nr, unsigned long p1, · 71 unmodified lines
86	84	}
87	85
88	86	#ifdef CONFIG_KVM_GUEST
	87	+void kvmclock_init(void);
	88	+void kvmclock_disable(void);
89	89	bool kvm_para_available(void);
90	90	unsigned int kvm_arch_para_features(void);
91	91	unsigned int kvm_arch_para_hints(void);
92	92	void kvm_async_pf_task_wait_schedule(u32 token);
93	93	void kvm_async_pf_task_wake(u32 token);
94	94	u32 kvm_read_and_reset_apf_flags(void);
95		−void kvm_disable_steal_time(void);
96	95	bool __kvm_handle_async_pf(struct pt_regs *regs, u32 token);
97	96
98	97	DECLARE_STATIC_KEY_FALSE(kvm_async_pf_enabled);
@@ -137,11 +136,6 @@ static inline u32 kvm_read_and_reset_apf_flags(void) · 38 unmodified lines
137	136	return 0;
138	137	}
139	138
140		−static inline void kvm_disable_steal_time(void)
141		−{
142		− return;
143		−}
144		−
145	139	static __always_inline bool kvm_handle_async_pf(struct pt_regs *regs, u32 token)
146	140	{
147	141	return false;

arch/x86/include/asm/msr-index.h+3−3

@@ -537,9 +537,9 @@ · 536 unmodified lines
537	537	/* K8 MSRs */
538	538	#define MSR_K8_TOP_MEM1 0xc001001a
539	539	#define MSR_K8_TOP_MEM2 0xc001001d
540		−#define MSR_K8_SYSCFG 0xc0010010
541		−#define MSR_K8_SYSCFG_MEM_ENCRYPT_BIT 23
542		−#define MSR_K8_SYSCFG_MEM_ENCRYPT BIT_ULL(MSR_K8_SYSCFG_MEM_ENCRYPT_BIT)
	540	+#define MSR_AMD64_SYSCFG 0xc0010010
	541	+#define MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT 23
	542	+#define MSR_AMD64_SYSCFG_MEM_ENCRYPT BIT_ULL(MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT)
543	543	#define MSR_K8_INT_PENDING_MSG 0xc0010055
544	544	/* C1E active bits in int pending message */
545	545	#define K8_INTP_C1E_ACTIVE_MASK 0x18000000

arch/x86/include/asm/processor.h+2−0

@@ -787,8 +787,10 @@ DECLARE_PER_CPU(u64, msr_misc_features_shadow); · 786 unmodified lines
787	787
788	788	#ifdef CONFIG_CPU_SUP_AMD
789	789	extern u32 amd_get_nodes_per_socket(void);
	790	+extern u32 amd_get_highest_perf(void);
790	791	#else
791	792	static inline u32 amd_get_nodes_per_socket(void) { return 0; }
	793	+static inline u32 amd_get_highest_perf(void) { return 0; }
792	794	#endif
793	795
794	796	static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves)

arch/x86/include/asm/sev-common.h+62−0

@@ -0,0 +1,62 @@
	1	+/* SPDX-License-Identifier: GPL-2.0 */
	2	+/*
	3	+ * AMD SEV header common between the guest and the hypervisor.
	4	+ *
	5	+ * Author: Brijesh Singh <brijesh.singh@amd.com>
	6	+ */
	7	+
	8	+#ifndef __ASM_X86_SEV_COMMON_H
	9	+#define __ASM_X86_SEV_COMMON_H
	10	+
	11	+#define GHCB_MSR_INFO_POS 0
	12	+#define GHCB_MSR_INFO_MASK (BIT_ULL(12) - 1)
	13	+
	14	+#define GHCB_MSR_SEV_INFO_RESP 0x001
	15	+#define GHCB_MSR_SEV_INFO_REQ 0x002
	16	+#define GHCB_MSR_VER_MAX_POS 48
	17	+#define GHCB_MSR_VER_MAX_MASK 0xffff
	18	+#define GHCB_MSR_VER_MIN_POS 32
	19	+#define GHCB_MSR_VER_MIN_MASK 0xffff
	20	+#define GHCB_MSR_CBIT_POS 24
	21	+#define GHCB_MSR_CBIT_MASK 0xff
	22	+#define GHCB_MSR_SEV_INFO(_max, _min, _cbit) \
	23	+ ((((_max) & GHCB_MSR_VER_MAX_MASK) << GHCB_MSR_VER_MAX_POS) \| \
	24	+ (((_min) & GHCB_MSR_VER_MIN_MASK) << GHCB_MSR_VER_MIN_POS) \| \
	25	+ (((_cbit) & GHCB_MSR_CBIT_MASK) << GHCB_MSR_CBIT_POS) \| \
	26	+ GHCB_MSR_SEV_INFO_RESP)
	27	+#define GHCB_MSR_INFO(v) ((v) & 0xfffUL)
	28	+#define GHCB_MSR_PROTO_MAX(v) (((v) >> GHCB_MSR_VER_MAX_POS) & GHCB_MSR_VER_MAX_MASK)
	29	+#define GHCB_MSR_PROTO_MIN(v) (((v) >> GHCB_MSR_VER_MIN_POS) & GHCB_MSR_VER_MIN_MASK)
	30	+
	31	+#define GHCB_MSR_CPUID_REQ 0x004
	32	+#define GHCB_MSR_CPUID_RESP 0x005
	33	+#define GHCB_MSR_CPUID_FUNC_POS 32
	34	+#define GHCB_MSR_CPUID_FUNC_MASK 0xffffffff
	35	+#define GHCB_MSR_CPUID_VALUE_POS 32
	36	+#define GHCB_MSR_CPUID_VALUE_MASK 0xffffffff
	37	+#define GHCB_MSR_CPUID_REG_POS 30
	38	+#define GHCB_MSR_CPUID_REG_MASK 0x3
	39	+#define GHCB_CPUID_REQ_EAX 0
	40	+#define GHCB_CPUID_REQ_EBX 1
	41	+#define GHCB_CPUID_REQ_ECX 2
	42	+#define GHCB_CPUID_REQ_EDX 3
	43	+#define GHCB_CPUID_REQ(fn, reg) \
	44	+ (GHCB_MSR_CPUID_REQ \| \
	45	+ (((unsigned long)reg & GHCB_MSR_CPUID_REG_MASK) << GHCB_MSR_CPUID_REG_POS) \| \
	46	+ (((unsigned long)fn) << GHCB_MSR_CPUID_FUNC_POS))
	47	+
	48	+#define GHCB_MSR_TERM_REQ 0x100
	49	+#define GHCB_MSR_TERM_REASON_SET_POS 12
	50	+#define GHCB_MSR_TERM_REASON_SET_MASK 0xf
	51	+#define GHCB_MSR_TERM_REASON_POS 16
	52	+#define GHCB_MSR_TERM_REASON_MASK 0xff
	53	+#define GHCB_SEV_TERM_REASON(reason_set, reason_val) \
	54	+ (((((u64)reason_set) & GHCB_MSR_TERM_REASON_SET_MASK) << GHCB_MSR_TERM_REASON_SET_POS) \| \
	55	+ ((((u64)reason_val) & GHCB_MSR_TERM_REASON_MASK) << GHCB_MSR_TERM_REASON_POS))
	56	+
	57	+#define GHCB_SEV_ES_REASON_GENERAL_REQUEST 0
	58	+#define GHCB_SEV_ES_REASON_PROTOCOL_UNSUPPORTED 1
	59	+
	60	+#define GHCB_RESP_CODE(v) ((v) & GHCB_MSR_INFO_MASK)
	61	+
	62	+#endif

arch/x86/include/asm/sev.hrenamed from arch/x86/include/asm/sev-es.h+4−26

@@ -10,34 +10,12 @@ · 9 unmodified lines
10	10
11	11	#include <linux/types.h>
12	12	#include <asm/insn.h>
	13	+#include <asm/sev-common.h>
13	14
14		−#define GHCB_SEV_INFO 0x001UL
15		−#define GHCB_SEV_INFO_REQ 0x002UL
16		−#define GHCB_INFO(v) ((v) & 0xfffUL)
17		−#define GHCB_PROTO_MAX(v) (((v) >> 48) & 0xffffUL)
18		−#define GHCB_PROTO_MIN(v) (((v) >> 32) & 0xffffUL)
19		−#define GHCB_PROTO_OUR 0x0001UL
20		−#define GHCB_SEV_CPUID_REQ 0x004UL
21		−#define GHCB_CPUID_REQ_EAX 0
22		−#define GHCB_CPUID_REQ_EBX 1
23		−#define GHCB_CPUID_REQ_ECX 2
24		−#define GHCB_CPUID_REQ_EDX 3
25		−#define GHCB_CPUID_REQ(fn, reg) (GHCB_SEV_CPUID_REQ \| \
26		− (((unsigned long)reg & 3) << 30) \| \
27		− (((unsigned long)fn) << 32))
	15	+#define GHCB_PROTO_OUR 0x0001UL
	16	+#define GHCB_PROTOCOL_MAX 1ULL
	17	+#define GHCB_DEFAULT_USAGE 0ULL
28	18
29		−#define GHCB_PROTOCOL_MAX 0x0001UL
30		−#define GHCB_DEFAULT_USAGE 0x0000UL
31		−
32		−#define GHCB_SEV_CPUID_RESP 0x005UL
33		−#define GHCB_SEV_TERMINATE 0x100UL
34		−#define GHCB_SEV_TERMINATE_REASON(reason_set, reason_val) \
35		− (((((u64)reason_set) & 0x7) << 12) \| \
36		− ((((u64)reason_val) & 0xff) << 16))
37		−#define GHCB_SEV_ES_REASON_GENERAL_REQUEST 0
38		−#define GHCB_SEV_ES_REASON_PROTOCOL_UNSUPPORTED 1
39		−
40		−#define GHCB_SEV_GHCB_RESP_CODE(v) ((v) & 0xfff)
41	19	#define VMGEXIT() { asm volatile("rep; vmmcall\n\r"); }
42	20
43	21	enum es_result {

arch/x86/include/asm/thermal.h+3−1

@@ -3,11 +3,13 @@ · 2 unmodified lines
3	3	#define _ASM_X86_THERMAL_H
4	4
5	5	#ifdef CONFIG_X86_THERMAL_VECTOR
	6	+void therm_lvt_init(void);
6	7	void intel_init_thermal(struct cpuinfo_x86 *c);
7	8	bool x86_thermal_enabled(void);
8	9	void intel_thermal_interrupt(void);
9	10	#else
10		−static inline void intel_init_thermal(struct cpuinfo_x86 *c) { }
	11	+static inline void therm_lvt_init(void) { }
	12	+static inline void intel_init_thermal(struct cpuinfo_x86 *c) { }
11	13	#endif
12	14
13	15	#endif /* _ASM_X86_THERMAL_H */

arch/x86/include/asm/vdso/clocksource.h+2−0

@@ -7,4 +7,6 @@ · 6 unmodified lines
7	7	VDSO_CLOCKMODE_PVCLOCK, \
8	8	VDSO_CLOCKMODE_HVCLOCK
9	9
	10	+#define HAVE_VDSO_CLOCKMODE_HVCLOCK
	11	+
10	12	#endif /* __ASM_VDSO_CLOCKSOURCE_H */

arch/x86/include/uapi/asm/kvm.h+2−0

@@ -437,6 +437,8 @@ struct kvm_vmx_nested_state_hdr { · 436 unmodified lines
437	437	__u16 flags;
438	438	} smm;
439	439
	440	+ __u16 pad;
	441	+
440	442	__u32 flags;
441	443	__u64 preemption_timer_deadline;
442	444	};

arch/x86/kernel/Makefile+3−3

@@ -20,7 +20,7 @@ CFLAGS_REMOVE_kvmclock.o = -pg · 19 unmodified lines
20	20	CFLAGS_REMOVE_ftrace.o = -pg
21	21	CFLAGS_REMOVE_early_printk.o = -pg
22	22	CFLAGS_REMOVE_head64.o = -pg
23		−CFLAGS_REMOVE_sev-es.o = -pg
	23	+CFLAGS_REMOVE_sev.o = -pg
24	24	endif
25	25
26	26	KASAN_SANITIZE_head$(BITS).o := n
@@ -28,7 +28,7 @@ KASAN_SANITIZE_dumpstack.o := n · 1 unmodified line
28	28	KASAN_SANITIZE_dumpstack_$(BITS).o := n
29	29	KASAN_SANITIZE_stacktrace.o := n
30	30	KASAN_SANITIZE_paravirt.o := n
31		−KASAN_SANITIZE_sev-es.o := n
	31	+KASAN_SANITIZE_sev.o := n
32	32
33	33	# With some compiler versions the generated code results in boot hangs, caused
34	34	# by several compilation units. To be safe, disable all instrumentation.
@@ -148,7 +148,7 @@ obj-$(CONFIG_UNWINDER_ORC) += unwind_orc.o · 113 unmodified lines
148	148	obj-$(CONFIG_UNWINDER_FRAME_POINTER) += unwind_frame.o
149	149	obj-$(CONFIG_UNWINDER_GUESS) += unwind_guess.o
150	150
151		−obj-$(CONFIG_AMD_MEM_ENCRYPT) += sev-es.o
	151	+obj-$(CONFIG_AMD_MEM_ENCRYPT) += sev.o
152	152	###
153	153	# 64 bit specific files
154	154	ifeq ($(CONFIG_X86_64),y)

arch/x86/kernel/alternative.c+46−18

@@ -182,42 +182,70 @@ done: · 181 unmodified lines
182	182	n_dspl, (unsigned long)orig_insn + n_dspl + repl_len);
183	183	}
184	184
	185	+/*
	186	+ * optimize_nops_range() - Optimize a sequence of single byte NOPs (0x90)
	187	+ *
	188	+ * @instr: instruction byte stream
	189	+ * @instrlen: length of the above
	190	+ * @off: offset within @instr where the first NOP has been detected
	191	+ *
	192	+ * Return: number of NOPs found (and replaced).
	193	+ */
	194	+static __always_inline int optimize_nops_range(u8 *instr, u8 instrlen, int off)
	195	+{
	196	+ unsigned long flags;
	197	+ int i = off, nnops;
	198	+
	199	+ while (i < instrlen) {
	200	+ if (instr[i] != 0x90)
	201	+ break;
	202	+
	203	+ i++;
	204	+ }
	205	+
	206	+ nnops = i - off;
	207	+
	208	+ if (nnops <= 1)
	209	+ return nnops;
	210	+
	211	+ local_irq_save(flags);
	212	+ add_nops(instr + off, nnops);
	213	+ local_irq_restore(flags);
	214	+
	215	+ DUMP_BYTES(instr, instrlen, "%px: [%d:%d) optimized NOPs: ", instr, off, i);
	216	+
	217	+ return nnops;
	218	+}
	219	+
185	220	/*
186	221	* "noinline" to cause control flow change and thus invalidate I$ and
187	222	* cause refetch after modification.
188	223	*/
189	224	static void __init_or_module noinline optimize_nops(struct alt_instr a, u8 instr)
190	225	{
191		− unsigned long flags;
192	226	struct insn insn;
193		− int nop, i = 0;
	227	+ int i = 0;
194	228
195	229	/*
196		− * Jump over the non-NOP insns, the remaining bytes must be single-byte
197		− * NOPs, optimize them.
	230	+ * Jump over the non-NOP insns and optimize single-byte NOPs into bigger
	231	+ * ones.
198	232	*/
199	233	for (;;) {
200	234	if (insn_decode_kernel(&insn, &instr[i]))
201	235	return;
202	236
	237	+ /*
	238	+ * See if this and any potentially following NOPs can be
	239	+ * optimized.
	240	+ */
203	241	if (insn.length == 1 && insn.opcode.bytes[0] == 0x90)
204		− break;
205		−
206		− if ((i += insn.length) >= a->instrlen)
207		− return;
208		− }
	242	+ i += optimize_nops_range(instr, a->instrlen, i);
	243	+ else
	244	+ i += insn.length;
209	245
210		− for (nop = i; i < a->instrlen; i++) {
211		− if (WARN_ONCE(instr[i] != 0x90, "Not a NOP at 0x%px\n", &instr[i]))
	246	+ if (i >= a->instrlen)
212	247	return;
213	248	}
214		−
215		− local_irq_save(flags);
216		− add_nops(instr + nop, i - nop);
217		− local_irq_restore(flags);
218		−
219		− DUMP_BYTES(instr, a->instrlen, "%px: [%d:%d) optimized NOPs: ",
220		− instr, nop, a->instrlen);
221	249	}
222	250
223	251	/*

arch/x86/kernel/apic/apic.c+1−0

@@ -2604,6 +2604,7 @@ static void __init apic_bsp_setup(bool upmode) · 2603 unmodified lines
2604	2604	end_local_APIC_setup();
2605	2605	irq_remap_enable_fault_handling();
2606	2606	setup_IO_APIC();
	2607	+ lapic_update_legacy_vectors();
2607	2608	}
2608	2609
2609	2610	#ifdef CONFIG_UP_LATE_INIT

arch/x86/kernel/apic/vector.c+20−0

@@ -738,6 +738,26 @@ void lapic_assign_legacy_vector(unsigned int irq, bool replace) · 737 unmodified lines
738	738	irq_matrix_assign_system(vector_matrix, ISA_IRQ_VECTOR(irq), replace);
739	739	}
740	740
	741	+void __init lapic_update_legacy_vectors(void)
	742	+{
	743	+ unsigned int i;
	744	+
	745	+ if (IS_ENABLED(CONFIG_X86_IO_APIC) && nr_ioapics > 0)
	746	+ return;
	747	+
	748	+ /*
	749	+ * If the IO/APIC is disabled via config, kernel command line or
	750	+ * lack of enumeration then all legacy interrupts are routed
	751	+ * through the PIC. Make sure that they are marked as legacy
	752	+ * vectors. PIC_CASCADE_IRQ has already been marked in
	753	+ * lapic_assign_system_vectors().
	754	+ */
	755	+ for (i = 0; i < nr_legacy_irqs(); i++) {
	756	+ if (i != PIC_CASCADE_IR)
	757	+ lapic_assign_legacy_vector(i, true);
	758	+ }
	759	+}
	760	+
741	761	void __init lapic_assign_system_vectors(void)
742	762	{
743	763	unsigned int i, vector = 0;

arch/x86/kernel/cpu/amd.c+18−2

@@ -593,8 +593,8 @@ static void early_detect_mem_encrypt(struct cpuinfo_x86 *c) · 592 unmodified lines
593	593	*/
594	594	if (cpu_has(c, X86_FEATURE_SME) \|\| cpu_has(c, X86_FEATURE_SEV)) {
595	595	/* Check if memory encryption is enabled */
596		− rdmsrl(MSR_K8_SYSCFG, msr);
597		− if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
	596	+ rdmsrl(MSR_AMD64_SYSCFG, msr);
	597	+ if (!(msr & MSR_AMD64_SYSCFG_MEM_ENCRYPT))
598	598	goto clear_all;
599	599
600	600	/*
@@ -1165,3 +1165,19 @@ void set_dr_addr_mask(unsigned long mask, int dr) · 564 unmodified lines
1165	1165	break;
1166	1166	}
1167	1167	}
	1168	+
	1169	+u32 amd_get_highest_perf(void)
	1170	+{
	1171	+ struct cpuinfo_x86 *c = &boot_cpu_data;
	1172	+
	1173	+ if (c->x86 == 0x17 && ((c->x86_model >= 0x30 && c->x86_model < 0x40) \|\|
	1174	+ (c->x86_model >= 0x70 && c->x86_model < 0x80)))
	1175	+ return 166;
	1176	+
	1177	+ if (c->x86 == 0x19 && ((c->x86_model >= 0x20 && c->x86_model < 0x30) \|\|
	1178	+ (c->x86_model >= 0x40 && c->x86_model < 0x70)))
	1179	+ return 166;
	1180	+
	1181	+ return 255;
	1182	+}
	1183	+EXPORT_SYMBOL_GPL(amd_get_highest_perf);

arch/x86/kernel/cpu/mtrr/cleanup.c+1−1

@@ -836,7 +836,7 @@ int __init amd_special_default_mtrr(void) · 835 unmodified lines
836	836	if (boot_cpu_data.x86 < 0xf)
837	837	return 0;
838	838	/* In case some hypervisor doesn't pass SYSCFG through: */
839		− if (rdmsr_safe(MSR_K8_SYSCFG, &l, &h) < 0)
	839	+ if (rdmsr_safe(MSR_AMD64_SYSCFG, &l, &h) < 0)
840	840	return 0;
841	841	/*
842	842	* Memory between 4GB and top of mem is forced WB by this magic bit.

arch/x86/kernel/cpu/mtrr/generic.c+2−2

@@ -53,13 +53,13 @@ static inline void k8_check_syscfg_dram_mod_en(void) · 52 unmodified lines
53	53	(boot_cpu_data.x86 >= 0x0f)))
54	54	return;
55	55
56		− rdmsr(MSR_K8_SYSCFG, lo, hi);
	56	+ rdmsr(MSR_AMD64_SYSCFG, lo, hi);
57	57	if (lo & K8_MTRRFIXRANGE_DRAM_MODIFY) {
58	58	pr_err(FW_WARN "MTRR: CPU %u: SYSCFG[MtrrFixDramModEn]"
59	59	" not cleared by BIOS, clearing this bit\n",
60	60	smp_processor_id());
61	61	lo &= ~K8_MTRRFIXRANGE_DRAM_MODIFY;
62		− mtrr_wrmsr(MSR_K8_SYSCFG, lo, hi);
	62	+ mtrr_wrmsr(MSR_AMD64_SYSCFG, lo, hi);
63	63	}
64	64	}
65	65

arch/x86/kernel/cpu/perfctr-watchdog.c+2−2

@@ -63,7 +63,7 @@ static inline unsigned int nmi_perfctr_msr_to_bit(unsigned int msr) · 62 unmodified lines
63	63	case 15:
64	64	return msr - MSR_P4_BPU_PERFCTR0;
65	65	}
66		− fallthrough;
	66	+ break;
67	67	case X86_VENDOR_ZHAOXIN:
68	68	case X86_VENDOR_CENTAUR:
69	69	return msr - MSR_ARCH_PERFMON_PERFCTR0;
@@ -96,7 +96,7 @@ static inline unsigned int nmi_evntsel_msr_to_bit(unsigned int msr) · 26 unmodified lines
96	96	case 15:
97	97	return msr - MSR_P4_BSU_ESCR0;
98	98	}
99		− fallthrough;
	99	+ break;
100	100	case X86_VENDOR_ZHAOXIN:
101	101	case X86_VENDOR_CENTAUR:
102	102	return msr - MSR_ARCH_PERFMON_EVENTSEL0;

arch/x86/kernel/cpu/sgx/virt.c+1−0

@@ -212,6 +212,7 @@ static int sgx_vepc_release(struct inode inode, struct file file) · 211 unmodified lines
212	212	list_splice_tail(&secs_pages, &zombie_secs_pages);
213	213	mutex_unlock(&zombie_secs_pages_lock);
214	214
	215	+ xa_destroy(&vepc->page_array);
215	216	kfree(vepc);
216	217
217	218	return 0;

arch/x86/kernel/fpu/signal.c+35−19

@@ -307,13 +307,17 @@ static int __fpu__restore_sig(void __user buf, void __user buf_fx, int size) · 306 unmodified lines
307	307	return 0;
308	308	}
309	309
310		− if (!access_ok(buf, size))
311		− return -EACCES;
	310	+ if (!access_ok(buf, size)) {
	311	+ ret = -EACCES;
	312	+ goto out;
	313	+ }
312	314
313		− if (!static_cpu_has(X86_FEATURE_FPU))
314		− return fpregs_soft_set(current, NULL,
315		− 0, sizeof(struct user_i387_ia32_struct),
316		− NULL, buf) != 0;
	315	+ if (!static_cpu_has(X86_FEATURE_FPU)) {
	316	+ ret = fpregs_soft_set(current, NULL, 0,
	317	+ sizeof(struct user_i387_ia32_struct),
	318	+ NULL, buf);
	319	+ goto out;
	320	+ }
317	321
318	322	if (use_xsave()) {
319	323	struct _fpx_sw_bytes fx_sw_user;
@@ -369,6 +373,25 @@ static int __fpu__restore_sig(void __user buf, void __user buf_fx, int size) · 49 unmodified lines
369	373	fpregs_unlock();
370	374	return 0;
371	375	}
	376	+
	377	+ /*
	378	+ * The above did an FPU restore operation, restricted to
	379	+ * the user portion of the registers, and failed, but the
	380	+ * microcode might have modified the FPU registers
	381	+ * nevertheless.
	382	+ *
	383	+ * If the FPU registers do not belong to current, then
	384	+ * invalidate the FPU register state otherwise the task might
	385	+ * preempt current and return to user space with corrupted
	386	+ * FPU registers.
	387	+ *
	388	+ * In case current owns the FPU registers then no further
	389	+ * action is required. The fixup below will handle it
	390	+ * correctly.
	391	+ */
	392	+ if (test_thread_flag(TIF_NEED_FPU_LOAD))
	393	+ __cpu_invalidate_fpregs_state();
	394	+
372	395	fpregs_unlock();
373	396	} else {
374	397	/*
@@ -377,7 +400,7 @@ static int __fpu__restore_sig(void __user buf, void __user buf_fx, int size) · 2 unmodified lines
377	400	*/
378	401	ret = __copy_from_user(&env, buf, sizeof(env));
379	402	if (ret)
380		− goto err_out;
	403	+ goto out;
381	404	envp = &env;
382	405	}
383	406
@@ -405,16 +428,9 @@ static int __fpu__restore_sig(void __user buf, void __user buf_fx, int size) · 21 unmodified lines
405	428	if (use_xsave() && !fx_only) {
406	429	u64 init_bv = xfeatures_mask_user() & ~user_xfeatures;
407	430
408		− if (using_compacted_format()) {
409		− ret = copy_user_to_xstate(&fpu->state.xsave, buf_fx);
410		− } else {
411		− ret = __copy_from_user(&fpu->state.xsave, buf_fx, state_size);
412		−
413		− if (!ret && state_size > offsetof(struct xregs_state, header))
414		− ret = validate_user_xstate_header(&fpu->state.xsave.header);
415		− }
	431	+ ret = copy_user_to_xstate(&fpu->state.xsave, buf_fx);
416	432	if (ret)
417		− goto err_out;
	433	+ goto out;
418	434
419	435	sanitize_restored_user_xstate(&fpu->state, envp, user_xfeatures,
420	436	fx_only);
@@ -434,7 +450,7 @@ static int __fpu__restore_sig(void __user buf, void __user buf_fx, int size) · 13 unmodified lines
434	450	ret = __copy_from_user(&fpu->state.fxsave, buf_fx, state_size);
435	451	if (ret) {
436	452	ret = -EFAULT;
437		− goto err_out;
	453	+ goto out;
438	454	}
439	455
440	456	sanitize_restored_user_xstate(&fpu->state, envp, user_xfeatures,
@@ -452,7 +468,7 @@ static int __fpu__restore_sig(void __user buf, void __user buf_fx, int size) · 11 unmodified lines
452	468	} else {
453	469	ret = __copy_from_user(&fpu->state.fsave, buf_fx, state_size);
454	470	if (ret)
455		− goto err_out;
	471	+ goto out;
456	472
457	473	fpregs_lock();
458	474	ret = copy_kernel_to_fregs_err(&fpu->state.fsave);
@@ -463,7 +479,7 @@ static int __fpu__restore_sig(void __user buf, void __user buf_fx, int size) · 4 unmodified lines
463	479	fpregs_deactivate(fpu);
464	480	fpregs_unlock();
465	481
466		−err_out:
	482	+out:
467	483	if (ret)
468	484	fpu__clear_user_states(fpu);
469	485	return ret;

arch/x86/kernel/fpu/xstate.c+0−57

@@ -1402,60 +1402,3 @@ int proc_pid_arch_status(struct seq_file m, struct pid_namespace ns, · 1401 unmodified lines
1402	1402	return 0;
1403	1403	}
1404	1404	#endif /* CONFIG_PROC_PID_ARCH_STATUS */
1405		−
1406		−#ifdef CONFIG_IOMMU_SUPPORT
1407		−void update_pasid(void)
1408		−{
1409		− u64 pasid_state;
1410		− u32 pasid;
1411		−
1412		− if (!cpu_feature_enabled(X86_FEATURE_ENQCMD))
1413		− return;
1414		−
1415		− if (!current->mm)
1416		− return;
1417		−
1418		− pasid = READ_ONCE(current->mm->pasid);
1419		− /* Set the valid bit in the PASID MSR/state only for valid pasid. */
1420		− pasid_state = pasid == PASID_DISABLED ?
1421		− pasid : pasid \| MSR_IA32_PASID_VALID;
1422		−
1423		− /*
1424		− * No need to hold fregs_lock() since the task's fpstate won't
1425		− * be changed by others (e.g. ptrace) while the task is being
1426		− * switched to or is in IPI.
1427		− */
1428		− if (!test_thread_flag(TIF_NEED_FPU_LOAD)) {
1429		− /* The MSR is active and can be directly updated. */
1430		− wrmsrl(MSR_IA32_PASID, pasid_state);
1431		− } else {
1432		− struct fpu *fpu = &current->thread.fpu;
1433		− struct ia32_pasid_state *ppasid_state;
1434		− struct xregs_state *xsave;
1435		−
1436		− /*
1437		− * The CPU's xstate registers are not currently active. Just
1438		− * update the PASID state in the memory buffer here. The
1439		− * PASID MSR will be loaded when returning to user mode.
1440		− */
1441		− xsave = &fpu->state.xsave;
1442		− xsave->header.xfeatures \|= XFEATURE_MASK_PASID;
1443		− ppasid_state = get_xsave_addr(xsave, XFEATURE_PASID);
1444		− /*
1445		− * Since XFEATURE_MASK_PASID is set in xfeatures, ppasid_state
1446		− * won't be NULL and no need to check its value.
1447		− *
1448		− * Only update the task's PASID state when it's different
1449		− * from the mm's pasid.
1450		− */
1451		− if (ppasid_state->pasid != pasid_state) {
1452		− /*
1453		− * Invalid fpregs so that state restoring will pick up
1454		− * the PASID state.
1455		− */
1456		− __fpu_invalidate_fpregs_state(fpu);
1457		− ppasid_state->pasid = pasid_state;
1458		− }
1459		− }
1460		−}
1461		−#endif /* CONFIG_IOMMU_SUPPORT */

arch/x86/kernel/head64.c+1−1

@@ -39,7 +39,7 @@ · 38 unmodified lines
39	39	#include <asm/realmode.h>
40	40	#include <asm/extable.h>
41	41	#include <asm/trapnr.h>
42		−#include <asm/sev-es.h>
	42	+#include <asm/sev.h>
43	43
44	44	/*
45	45	* Manage page tables very early on.

arch/x86/kernel/kvm.c+83−46

@@ -26,6 +26,7 @@ · 25 unmodified lines
26	26	#include <linux/kprobes.h>
27	27	#include <linux/nmi.h>
28	28	#include <linux/swait.h>
	29	+#include <linux/syscore_ops.h>
29	30	#include <asm/timer.h>
30	31	#include <asm/cpu.h>
31	32	#include <asm/traps.h>
@@ -37,6 +38,7 @@ · 5 unmodified lines
37	38	#include <asm/tlb.h>
38	39	#include <asm/cpuidle_haltpoll.h>
39	40	#include <asm/ptrace.h>
	41	+#include <asm/reboot.h>
40	42	#include <asm/svm.h>
41	43
42	44	DEFINE_STATIC_KEY_FALSE(kvm_async_pf_enabled);
@@ -345,7 +347,7 @@ static void kvm_guest_cpu_init(void) · 302 unmodified lines
345	347
346	348	wrmsrl(MSR_KVM_ASYNC_PF_EN, pa);
347	349	__this_cpu_write(apf_reason.enabled, 1);
348		− pr_info("KVM setup async PF for cpu %d\n", smp_processor_id());
	350	+ pr_info("setup async PF for cpu %d\n", smp_processor_id());
349	351	}
350	352
351	353	if (kvm_para_has_feature(KVM_FEATURE_PV_EOI)) {
@@ -371,34 +373,17 @@ static void kvm_pv_disable_apf(void) · 19 unmodified lines
371	373	wrmsrl(MSR_KVM_ASYNC_PF_EN, 0);
372	374	__this_cpu_write(apf_reason.enabled, 0);
373	375
374		− pr_info("Unregister pv shared memory for cpu %d\n", smp_processor_id());
	376	+ pr_info("disable async PF for cpu %d\n", smp_processor_id());
375	377	}
376	378
377		−static void kvm_pv_guest_cpu_reboot(void *unused)
	379	+static void kvm_disable_steal_time(void)
378	380	{
379		− /*
380		− * We disable PV EOI before we load a new kernel by kexec,
381		− * since MSR_KVM_PV_EOI_EN stores a pointer into old kernel's memory.
382		− * New kernel can re-enable when it boots.
383		− */
384		− if (kvm_para_has_feature(KVM_FEATURE_PV_EOI))
385		− wrmsrl(MSR_KVM_PV_EOI_EN, 0);
386		− kvm_pv_disable_apf();
387		− kvm_disable_steal_time();
388		−}
	381	+ if (!has_steal_clock)
	382	+ return;
389	383
390		−static int kvm_pv_reboot_notify(struct notifier_block *nb,
391		− unsigned long code, void *unused)
392		−{
393		− if (code == SYS_RESTART)
394		− on_each_cpu(kvm_pv_guest_cpu_reboot, NULL, 1);
395		− return NOTIFY_DONE;
	384	+ wrmsr(MSR_KVM_STEAL_TIME, 0, 0);
396	385	}
397	386
398		−static struct notifier_block kvm_pv_reboot_nb = {
399		− .notifier_call = kvm_pv_reboot_notify,
400		−};
401		−
402	387	static u64 kvm_steal_clock(int cpu)
403	388	{
404	389	u64 steal;
@@ -416,14 +401,6 @@ static u64 kvm_steal_clock(int cpu) · 11 unmodified lines
416	401	return steal;
417	402	}
418	403
419		−void kvm_disable_steal_time(void)
420		−{
421		− if (!has_steal_clock)
422		− return;
423		−
424		− wrmsr(MSR_KVM_STEAL_TIME, 0, 0);
425		−}
426		−
427	404	static inline void __set_percpu_decrypted(void *ptr, unsigned long size)
428	405	{
429	406	early_set_memory_decrypted((unsigned long) ptr, size);
@@ -451,6 +428,27 @@ static void __init sev_map_percpu_data(void) · 21 unmodified lines
451	428	}
452	429	}
453	430
	431	+static void kvm_guest_cpu_offline(bool shutdown)
	432	+{
	433	+ kvm_disable_steal_time();
	434	+ if (kvm_para_has_feature(KVM_FEATURE_PV_EOI))
	435	+ wrmsrl(MSR_KVM_PV_EOI_EN, 0);
	436	+ kvm_pv_disable_apf();
	437	+ if (!shutdown)
	438	+ apf_task_wake_all();
	439	+ kvmclock_disable();
	440	+}
	441	+
	442	+static int kvm_cpu_online(unsigned int cpu)
	443	+{
	444	+ unsigned long flags;
	445	+
	446	+ local_irq_save(flags);
	447	+ kvm_guest_cpu_init();
	448	+ local_irq_restore(flags);
	449	+ return 0;
	450	+}
	451	+
454	452	#ifdef CONFIG_SMP
455	453
456	454	static DEFINE_PER_CPU(cpumask_var_t, __pv_cpu_mask);
@@ -635,31 +633,64 @@ static void __init kvm_smp_prepare_boot_cpu(void) · 178 unmodified lines
635	633	kvm_spinlock_init();
636	634	}
637	635
638		−static void kvm_guest_cpu_offline(void)
	636	+static int kvm_cpu_down_prepare(unsigned int cpu)
639	637	{
640		− kvm_disable_steal_time();
641		− if (kvm_para_has_feature(KVM_FEATURE_PV_EOI))
642		− wrmsrl(MSR_KVM_PV_EOI_EN, 0);
643		− kvm_pv_disable_apf();
644		− apf_task_wake_all();
	638	+ unsigned long flags;
	639	+
	640	+ local_irq_save(flags);
	641	+ kvm_guest_cpu_offline(false);
	642	+ local_irq_restore(flags);
	643	+ return 0;
645	644	}
646	645
647		−static int kvm_cpu_online(unsigned int cpu)
	646	+#endif
	647	+
	648	+static int kvm_suspend(void)
648	649	{
649		− local_irq_disable();
650		− kvm_guest_cpu_init();
651		− local_irq_enable();
	650	+ kvm_guest_cpu_offline(false);
	651	+
652	652	return 0;
653	653	}
654	654
655		−static int kvm_cpu_down_prepare(unsigned int cpu)
	655	+static void kvm_resume(void)
656	656	{
657		− local_irq_disable();
658		− kvm_guest_cpu_offline();
659		− local_irq_enable();
660		− return 0;
	657	+ kvm_cpu_online(raw_smp_processor_id());
	658	+}
	659	+
	660	+static struct syscore_ops kvm_syscore_ops = {
	661	+ .suspend = kvm_suspend,
	662	+ .resume = kvm_resume,
	663	+};
	664	+
	665	+static void kvm_pv_guest_cpu_reboot(void *unused)
	666	+{
	667	+ kvm_guest_cpu_offline(true);
	668	+}
	669	+
	670	+static int kvm_pv_reboot_notify(struct notifier_block *nb,
	671	+ unsigned long code, void *unused)
	672	+{
	673	+ if (code == SYS_RESTART)
	674	+ on_each_cpu(kvm_pv_guest_cpu_reboot, NULL, 1);
	675	+ return NOTIFY_DONE;
661	676	}
662	677
	678	+static struct notifier_block kvm_pv_reboot_nb = {
	679	+ .notifier_call = kvm_pv_reboot_notify,
	680	+};
	681	+
	682	+/*
	683	+ * After a PV feature is registered, the host will keep writing to the
	684	+ * registered memory location. If the guest happens to shutdown, this memory
	685	+ * won't be valid. In cases like kexec, in which you install a new kernel, this
	686	+ * means a random memory location will be kept being written.
	687	+ */
	688	+#ifdef CONFIG_KEXEC_CORE
	689	+static void kvm_crash_shutdown(struct pt_regs *regs)
	690	+{
	691	+ kvm_guest_cpu_offline(true);
	692	+ native_machine_crash_shutdown(regs);
	693	+}
663	694	#endif
664	695
665	696	static void __init kvm_guest_init(void)
@@ -704,6 +735,12 @@ static void __init kvm_guest_init(void) · 38 unmodified lines
704	735	kvm_guest_cpu_init();
705	736	#endif
706	737
	738	+#ifdef CONFIG_KEXEC_CORE
	739	+ machine_ops.crash_shutdown = kvm_crash_shutdown;
	740	+#endif
	741	+
	742	+ register_syscore_ops(&kvm_syscore_ops);
	743	+
707	744	/*
708	745	* Hard lockup detection is enabled by default. Disable it, as guests
709	746	* can get false positives too easily, for example if the host is

arch/x86/kernel/kvmclock.c+1−25

@@ -20,7 +20,6 @@ · 19 unmodified lines
20	20	#include <asm/hypervisor.h>
21	21	#include <asm/mem_encrypt.h>
22	22	#include <asm/x86_init.h>
23		−#include <asm/reboot.h>
24	23	#include <asm/kvmclock.h>
25	24
26	25	static int kvmclock __initdata = 1;
@@ -203,28 +202,9 @@ static void kvm_setup_secondary_clock(void) · 176 unmodified lines
203	202	}
204	203	#endif
205	204
206		−/*
207		− * After the clock is registered, the host will keep writing to the
208		− * registered memory location. If the guest happens to shutdown, this memory
209		− * won't be valid. In cases like kexec, in which you install a new kernel, this
210		− * means a random memory location will be kept being written. So before any
211		− * kind of shutdown from our side, we unregister the clock by writing anything
212		− * that does not have the 'enable' bit set in the msr
213		− */
214		−#ifdef CONFIG_KEXEC_CORE
215		−static void kvm_crash_shutdown(struct pt_regs *regs)
216		−{
217		− native_write_msr(msr_kvm_system_time, 0, 0);
218		− kvm_disable_steal_time();
219		− native_machine_crash_shutdown(regs);
220		−}
221		−#endif
222		−
223		−static void kvm_shutdown(void)
	205	+void kvmclock_disable(void)
224	206	{
225	207	native_write_msr(msr_kvm_system_time, 0, 0);
226		− kvm_disable_steal_time();
227		− native_machine_shutdown();
228	208	}
229	209
230	210	static void __init kvmclock_init_mem(void)
@@ -351,10 +331,6 @@ void __init kvmclock_init(void) · 120 unmodified lines
351	331	#endif
352	332	x86_platform.save_sched_clock_state = kvm_save_sched_clock_state;
353	333	x86_platform.restore_sched_clock_state = kvm_restore_sched_clock_state;
354		− machine_ops.shutdown = kvm_shutdown;
355		−#ifdef CONFIG_KEXEC_CORE
356		− machine_ops.crash_shutdown = kvm_crash_shutdown;
357		−#endif
358	334	kvm_get_preset_lpj();
359	335
360	336	/*

arch/x86/kernel/mmconf-fam10h_64.c+1−1

@@ -95,7 +95,7 @@ static void get_fam10h_pci_mmconf_base(void) · 94 unmodified lines
95	95	return;
96	96
97	97	/* SYS_CFG */
98		− address = MSR_K8_SYSCFG;
	98	+ address = MSR_AMD64_SYSCFG;
99	99	rdmsrl(address, val);
100	100
101	101	/* TOP_MEM2 is not enabled? */

arch/x86/kernel/nmi.c+1−1

@@ -33,7 +33,7 @@ · 32 unmodified lines
33	33	#include <asm/reboot.h>
34	34	#include <asm/cache.h>
35	35	#include <asm/nospec-branch.h>
36		−#include <asm/sev-es.h>
	36	+#include <asm/sev.h>
37	37
38	38	#define CREATE_TRACE_POINTS
39	39	#include <trace/events/nmi.h>

arch/x86/kernel/setup.c+30−14

@@ -44,6 +44,7 @@ · 43 unmodified lines
44	44	#include <asm/pci-direct.h>
45	45	#include <asm/prom.h>
46	46	#include <asm/proto.h>
	47	+#include <asm/thermal.h>
47	48	#include <asm/unwind.h>
48	49	#include <asm/vsyscall.h>
49	50	#include <linux/vmalloc.h>
@@ -637,11 +638,11 @@ static void __init trim_snb_memory(void) · 587 unmodified lines
637	638	* them from accessing certain memory ranges, namely anything below
638	639	* 1M and in the pages listed in bad_pages[] above.
639	640	*
640		− * To avoid these pages being ever accessed by SNB gfx devices
641		− * reserve all memory below the 1 MB mark and bad_pages that have
642		− * not already been reserved at boot time.
	641	+ * To avoid these pages being ever accessed by SNB gfx devices reserve
	642	+ * bad_pages that have not already been reserved at boot time.
	643	+ * All memory below the 1 MB mark is anyway reserved later during
	644	+ * setup_arch(), so there is no need to reserve it here.
643	645	*/
644		− memblock_reserve(0, 1<<20);
645	646
646	647	for (i = 0; i < ARRAY_SIZE(bad_pages); i++) {
647	648	if (memblock_reserve(bad_pages[i], PAGE_SIZE))
@@ -733,14 +734,14 @@ static void __init early_reserve_memory(void) · 85 unmodified lines
733	734	* The first 4Kb of memory is a BIOS owned area, but generally it is
734	735	* not listed as such in the E820 table.
735	736	*
736		− * Reserve the first memory page and typically some additional
737		− * memory (64KiB by default) since some BIOSes are known to corrupt
738		− * low memory. See the Kconfig help text for X86_RESERVE_LOW.
	737	+ * Reserve the first 64K of memory since some BIOSes are known to
	738	+ * corrupt low memory. After the real mode trampoline is allocated the
	739	+ * rest of the memory below 640k is reserved.
739	740	*
740	741	* In addition, make sure page 0 is always reserved because on
741	742	* systems with L1TF its contents can be leaked to user processes.
742	743	*/
743		− memblock_reserve(0, ALIGN(reserve_low, PAGE_SIZE));
	744	+ memblock_reserve(0, SZ_64K);
744	745
745	746	early_reserve_initrd();
746	747
@@ -751,6 +752,7 @@ static void __init early_reserve_memory(void) · 4 unmodified lines
751	752
752	753	reserve_ibft_region();
753	754	reserve_bios_regions();
	755	+ trim_snb_memory();
754	756	}
755	757
756	758	/*
@@ -1081,14 +1083,20 @@ void __init setup_arch(char **cmdline_p) · 324 unmodified lines
1081	1083	(max_pfn_mapped<<PAGE_SHIFT) - 1);
1082	1084	#endif
1083	1085
1084		− reserve_real_mode();
1085		−
1086	1086	/*
1087		− * Reserving memory causing GPU hangs on Sandy Bridge integrated
1088		− * graphics devices should be done after we allocated memory under
1089		− * 1M for the real mode trampoline.
	1087	+ * Find free memory for the real mode trampoline and place it
	1088	+ * there.
	1089	+ * If there is not enough free memory under 1M, on EFI-enabled
	1090	+ * systems there will be additional attempt to reclaim the memory
	1091	+ * for the real mode trampoline at efi_free_boot_services().
	1092	+ *
	1093	+ * Unconditionally reserve the entire first 1M of RAM because
	1094	+ * BIOSes are know to corrupt low memory and several
	1095	+ * hundred kilobytes are not worth complex detection what memory gets
	1096	+ * clobbered. Moreover, on machines with SandyBridge graphics or in
	1097	+ * setups that use crashkernel the entire 1M is reserved anyway.
1090	1098	*/
1091		− trim_snb_memory();
	1099	+ reserve_real_mode();
1092	1100
1093	1101	init_mem_mapping();
1094	1102
@@ -1226,6 +1234,14 @@ void __init setup_arch(char **cmdline_p) · 131 unmodified lines
1226	1234
1227	1235	x86_init.timers.wallclock_init();
1228	1236
	1237	+ /*
	1238	+ * This needs to run before setup_local_APIC() which soft-disables the
	1239	+ * local APIC temporarily and that masks the thermal LVT interrupt,
	1240	+ * leading to softlockups on machines which have configured SMI
	1241	+ * interrupt delivery.
	1242	+ */
	1243	+ therm_lvt_init();
	1244	+
1229	1245	mcheck_init();
1230	1246
1231	1247	register_refined_jiffies(CLOCK_TICK_RATE);

arch/x86/kernel/sev-shared.crenamed from arch/x86/kernel/sev-es-shared.c+11−10

@@ -26,13 +26,13 @@ static bool __init sev_es_check_cpu_features(void) · 25 unmodified lines
26	26
27	27	static void __noreturn sev_es_terminate(unsigned int reason)
28	28	{
29		− u64 val = GHCB_SEV_TERMINATE;
	29	+ u64 val = GHCB_MSR_TERM_REQ;
30	30
31	31	/*
32	32	* Tell the hypervisor what went wrong - only reason-set 0 is
33	33	* currently supported.
34	34	*/
35		− val \|= GHCB_SEV_TERMINATE_REASON(0, reason);
	35	+ val \|= GHCB_SEV_TERM_REASON(0, reason);
36	36
37	37	/* Request Guest Termination from Hypvervisor */
38	38	sev_es_wr_ghcb_msr(val);
@@ -47,15 +47,15 @@ static bool sev_es_negotiate_protocol(void) · 8 unmodified lines
47	47	u64 val;
48	48
49	49	/* Do the GHCB protocol version negotiation */
50		− sev_es_wr_ghcb_msr(GHCB_SEV_INFO_REQ);
	50	+ sev_es_wr_ghcb_msr(GHCB_MSR_SEV_INFO_REQ);
51	51	VMGEXIT();
52	52	val = sev_es_rd_ghcb_msr();
53	53
54		− if (GHCB_INFO(val) != GHCB_SEV_INFO)
	54	+ if (GHCB_MSR_INFO(val) != GHCB_MSR_SEV_INFO_RESP)
55	55	return false;
56	56
57		− if (GHCB_PROTO_MAX(val) < GHCB_PROTO_OUR \|\|
58		− GHCB_PROTO_MIN(val) > GHCB_PROTO_OUR)
	57	+ if (GHCB_MSR_PROTO_MAX(val) < GHCB_PROTO_OUR \|\|
	58	+ GHCB_MSR_PROTO_MIN(val) > GHCB_PROTO_OUR)
59	59	return false;
60	60
61	61	return true;
@@ -63,6 +63,7 @@ static bool sev_es_negotiate_protocol(void) · 1 unmodified line
63	63
64	64	static __always_inline void vc_ghcb_invalidate(struct ghcb *ghcb)
65	65	{
	66	+ ghcb->save.sw_exit_code = 0;
66	67	memset(ghcb->save.valid_bitmap, 0, sizeof(ghcb->save.valid_bitmap));
67	68	}
68	69
@@ -153,28 +154,28 @@ void __init do_vc_no_ghcb(struct pt_regs *regs, unsigned long exit_code) · 84 unmodified lines
153	154	sev_es_wr_ghcb_msr(GHCB_CPUID_REQ(fn, GHCB_CPUID_REQ_EAX));
154	155	VMGEXIT();
155	156	val = sev_es_rd_ghcb_msr();
156		− if (GHCB_SEV_GHCB_RESP_CODE(val) != GHCB_SEV_CPUID_RESP)
	157	+ if (GHCB_RESP_CODE(val) != GHCB_MSR_CPUID_RESP)
157	158	goto fail;
158	159	regs->ax = val >> 32;
159	160
160	161	sev_es_wr_ghcb_msr(GHCB_CPUID_REQ(fn, GHCB_CPUID_REQ_EBX));
161	162	VMGEXIT();
162	163	val = sev_es_rd_ghcb_msr();
163		− if (GHCB_SEV_GHCB_RESP_CODE(val) != GHCB_SEV_CPUID_RESP)
	164	+ if (GHCB_RESP_CODE(val) != GHCB_MSR_CPUID_RESP)
164	165	goto fail;
165	166	regs->bx = val >> 32;
166	167
167	168	sev_es_wr_ghcb_msr(GHCB_CPUID_REQ(fn, GHCB_CPUID_REQ_ECX));
168	169	VMGEXIT();
169	170	val = sev_es_rd_ghcb_msr();
170		− if (GHCB_SEV_GHCB_RESP_CODE(val) != GHCB_SEV_CPUID_RESP)
	171	+ if (GHCB_RESP_CODE(val) != GHCB_MSR_CPUID_RESP)
171	172	goto fail;
172	173	regs->cx = val >> 32;
173	174
174	175	sev_es_wr_ghcb_msr(GHCB_CPUID_REQ(fn, GHCB_CPUID_REQ_EDX));
175	176	VMGEXIT();
176	177	val = sev_es_rd_ghcb_msr();
177		− if (GHCB_SEV_GHCB_RESP_CODE(val) != GHCB_SEV_CPUID_RESP)
	178	+ if (GHCB_RESP_CODE(val) != GHCB_MSR_CPUID_RESP)
178	179	goto fail;
179	180	regs->dx = val >> 32;
180	181

arch/x86/kernel/sev.crenamed from arch/x86/kernel/sev-es.c+87−53

@@ -22,7 +22,7 @@ · 21 unmodified lines
22	22
23	23	#include <asm/cpu_entry_area.h>
24	24	#include <asm/stacktrace.h>
25		−#include <asm/sev-es.h>
	25	+#include <asm/sev.h>
26	26	#include <asm/insn-eval.h>
27	27	#include <asm/fpu/internal.h>
28	28	#include <asm/processor.h>
@@ -203,8 +203,18 @@ static __always_inline struct ghcb sev_es_get_ghcb(struct ghcb_state state) · 174 unmodified lines
203	203	if (unlikely(data->ghcb_active)) {
204	204	/* GHCB is already in use - save its contents */
205	205
206		− if (unlikely(data->backup_ghcb_active))
207		− return NULL;
	206	+ if (unlikely(data->backup_ghcb_active)) {
	207	+ /*
	208	+ * Backup-GHCB is also already in use. There is no way
	209	+ * to continue here so just kill the machine. To make
	210	+ * panic() work, mark GHCBs inactive so that messages
	211	+ * can be printed out.
	212	+ */
	213	+ data->ghcb_active = false;
	214	+ data->backup_ghcb_active = false;
	215	+
	216	+ panic("Unable to handle #VC exception! GHCB and Backup GHCB are already in use");
	217	+ }
208	218
209	219	/* Mark backup_ghcb active before writing to it */
210	220	data->backup_ghcb_active = true;
@@ -221,24 +231,6 @@ static __always_inline struct ghcb sev_es_get_ghcb(struct ghcb_state state) · 10 unmodified lines
221	231	return ghcb;
222	232	}
223	233
224		−static __always_inline void sev_es_put_ghcb(struct ghcb_state *state)
225		−{
226		− struct sev_es_runtime_data *data;
227		− struct ghcb *ghcb;
228		−
229		− data = this_cpu_read(runtime_data);
230		− ghcb = &data->ghcb_page;
231		−
232		− if (state->ghcb) {
233		− /* Restore GHCB from Backup */
234		− ghcb = state->ghcb;
235		− data->backup_ghcb_active = false;
236		− state->ghcb = NULL;
237		− } else {
238		− data->ghcb_active = false;
239		− }
240		−}
241		−
242	234	/* Needed in vc_early_forward_exception */
243	235	void do_early_exception(struct pt_regs *regs, int trapnr);
244	236
@@ -323,31 +315,44 @@ static enum es_result vc_write_mem(struct es_em_ctxt *ctxt, · 78 unmodified lines
323	315	u16 d2;
324	316	u8 d1;
325	317
326		− /* If instruction ran in kernel mode and the I/O buffer is in kernel space */
327		− if (!user_mode(ctxt->regs) && !access_ok(target, size)) {
328		− memcpy(dst, buf, size);
329		− return ES_OK;
330		− }
331		−
	318	+ /*
	319	+ * This function uses __put_user() independent of whether kernel or user
	320	+ * memory is accessed. This works fine because __put_user() does no
	321	+ * sanity checks of the pointer being accessed. All that it does is
	322	+ * to report when the access failed.
	323	+ *
	324	+ * Also, this function runs in atomic context, so __put_user() is not
	325	+ * allowed to sleep. The page-fault handler detects that it is running
	326	+ * in atomic context and will not try to take mmap_sem and handle the
	327	+ * fault, so additional pagefault_enable()/disable() calls are not
	328	+ * needed.
	329	+ *
	330	+ * The access can't be done via copy_to_user() here because
	331	+ * vc_write_mem() must not use string instructions to access unsafe
	332	+ * memory. The reason is that MOVS is emulated by the #VC handler by
	333	+ * splitting the move up into a read and a write and taking a nested #VC
	334	+ * exception on whatever of them is the MMIO access. Using string
	335	+ * instructions here would cause infinite nesting.
	336	+ */
332	337	switch (size) {
333	338	case 1:
334	339	memcpy(&d1, buf, 1);
335		− if (put_user(d1, target))
	340	+ if (__put_user(d1, target))
336	341	goto fault;
337	342	break;
338	343	case 2:
339	344	memcpy(&d2, buf, 2);
340		− if (put_user(d2, target))
	345	+ if (__put_user(d2, target))
341	346	goto fault;
342	347	break;
343	348	case 4:
344	349	memcpy(&d4, buf, 4);
345		− if (put_user(d4, target))
	350	+ if (__put_user(d4, target))
346	351	goto fault;
347	352	break;
348	353	case 8:
349	354	memcpy(&d8, buf, 8);
350		− if (put_user(d8, target))
	355	+ if (__put_user(d8, target))
351	356	goto fault;
352	357	break;
353	358	default:
@@ -378,30 +383,43 @@ static enum es_result vc_read_mem(struct es_em_ctxt *ctxt, · 24 unmodified lines
378	383	u16 d2;
379	384	u8 d1;
380	385
381		− /* If instruction ran in kernel mode and the I/O buffer is in kernel space */
382		− if (!user_mode(ctxt->regs) && !access_ok(s, size)) {
383		− memcpy(buf, src, size);
384		− return ES_OK;
385		− }
386		−
	386	+ /*
	387	+ * This function uses __get_user() independent of whether kernel or user
	388	+ * memory is accessed. This works fine because __get_user() does no
	389	+ * sanity checks of the pointer being accessed. All that it does is
	390	+ * to report when the access failed.
	391	+ *
	392	+ * Also, this function runs in atomic context, so __get_user() is not
	393	+ * allowed to sleep. The page-fault handler detects that it is running
	394	+ * in atomic context and will not try to take mmap_sem and handle the
	395	+ * fault, so additional pagefault_enable()/disable() calls are not
	396	+ * needed.
	397	+ *
	398	+ * The access can't be done via copy_from_user() here because
	399	+ * vc_read_mem() must not use string instructions to access unsafe
	400	+ * memory. The reason is that MOVS is emulated by the #VC handler by
	401	+ * splitting the move up into a read and a write and taking a nested #VC
	402	+ * exception on whatever of them is the MMIO access. Using string
	403	+ * instructions here would cause infinite nesting.
	404	+ */
387	405	switch (size) {
388	406	case 1:
389		− if (get_user(d1, s))
	407	+ if (__get_user(d1, s))
390	408	goto fault;
391	409	memcpy(buf, &d1, 1);
392	410	break;
393	411	case 2:
394		− if (get_user(d2, s))
	412	+ if (__get_user(d2, s))
395	413	goto fault;
396	414	memcpy(buf, &d2, 2);
397	415	break;
398	416	case 4:
399		− if (get_user(d4, s))
	417	+ if (__get_user(d4, s))
400	418	goto fault;
401	419	memcpy(buf, &d4, 4);
402	420	break;
403	421	case 8:
404		− if (get_user(d8, s))
	422	+ if (__get_user(d8, s))
405	423	goto fault;
406	424	memcpy(buf, &d8, 8);
407	425	break;
@@ -459,7 +477,30 @@ static enum es_result vc_slow_virt_to_phys(struct ghcb *ghcb, struct es_em_ctxt · 51 unmodified lines
459	477	}
460	478
461	479	/* Include code shared with pre-decompression boot stage */
462		−#include "sev-es-shared.c"
	480	+#include "sev-shared.c"
	481	+
	482	+static __always_inline void sev_es_put_ghcb(struct ghcb_state *state)
	483	+{
	484	+ struct sev_es_runtime_data *data;
	485	+ struct ghcb *ghcb;
	486	+
	487	+ data = this_cpu_read(runtime_data);
	488	+ ghcb = &data->ghcb_page;
	489	+
	490	+ if (state->ghcb) {
	491	+ /* Restore GHCB from Backup */
	492	+ ghcb = state->ghcb;
	493	+ data->backup_ghcb_active = false;
	494	+ state->ghcb = NULL;
	495	+ } else {
	496	+ /*
	497	+ * Invalidate the GHCB so a VMGEXIT instruction issued
	498	+ * from userspace won't appear to be valid.
	499	+ */
	500	+ vc_ghcb_invalidate(ghcb);
	501	+ data->ghcb_active = false;
	502	+ }
	503	+}
463	504
464	505	void noinstr __sev_es_nmi_complete(void)
465	506	{
@@ -1255,6 +1296,10 @@ static __always_inline void vc_forward_exception(struct es_em_ctxt *ctxt) · 789 unmodified lines
1255	1296	case X86_TRAP_UD:
1256	1297	exc_invalid_op(ctxt->regs);
1257	1298	break;
	1299	+ case X86_TRAP_PF:
	1300	+ write_cr2(ctxt->fi.cr2);
	1301	+ exc_page_fault(ctxt->regs, error_code);
	1302	+ break;
1258	1303	case X86_TRAP_AC:
1259	1304	exc_alignment_check(ctxt->regs, error_code);
1260	1305	break;
@@ -1284,7 +1329,6 @@ static __always_inline bool on_vc_fallback_stack(struct pt_regs *regs) · 23 unmodified lines
1284	1329	*/
1285	1330	DEFINE_IDTENTRY_VC_SAFE_STACK(exc_vmm_communication)
1286	1331	{
1287		− struct sev_es_runtime_data *data = this_cpu_read(runtime_data);
1288	1332	irqentry_state_t irq_state;
1289	1333	struct ghcb_state state;
1290	1334	struct es_em_ctxt ctxt;
@@ -1310,16 +1354,6 @@ DEFINE_IDTENTRY_VC_SAFE_STACK(exc_vmm_communication) · 19 unmodified lines
1310	1354	*/
1311	1355
1312	1356	ghcb = sev_es_get_ghcb(&state);
1313		− if (!ghcb) {
1314		− /*
1315		− * Mark GHCBs inactive so that panic() is able to print the
1316		− * message.
1317		− */
1318		− data->ghcb_active = false;
1319		− data->backup_ghcb_active = false;
1320		−
1321		− panic("Unable to handle #VC exception! GHCB and Backup GHCB are already in use");
1322		− }
1323	1357
1324	1358	vc_ghcb_invalidate(ghcb);
1325	1359	result = vc_init_em_ctxt(&ctxt, regs, error_code);

arch/x86/kernel/signal_compat.c+7−2

@@ -127,6 +127,9 @@ static inline void signal_compat_build_tests(void) · 126 unmodified lines
127	127	BUILD_BUG_ON(offsetof(siginfo_t, si_addr) != 0x10);
128	128	BUILD_BUG_ON(offsetof(compat_siginfo_t, si_addr) != 0x0C);
129	129
	130	+ BUILD_BUG_ON(offsetof(siginfo_t, si_trapno) != 0x18);
	131	+ BUILD_BUG_ON(offsetof(compat_siginfo_t, si_trapno) != 0x10);
	132	+
130	133	BUILD_BUG_ON(offsetof(siginfo_t, si_addr_lsb) != 0x18);
131	134	BUILD_BUG_ON(offsetof(compat_siginfo_t, si_addr_lsb) != 0x10);
132	135
@@ -138,8 +141,10 @@ static inline void signal_compat_build_tests(void) · 5 unmodified lines
138	141	BUILD_BUG_ON(offsetof(siginfo_t, si_pkey) != 0x20);
139	142	BUILD_BUG_ON(offsetof(compat_siginfo_t, si_pkey) != 0x14);
140	143
141		− BUILD_BUG_ON(offsetof(siginfo_t, si_perf) != 0x18);
142		− BUILD_BUG_ON(offsetof(compat_siginfo_t, si_perf) != 0x10);
	144	+ BUILD_BUG_ON(offsetof(siginfo_t, si_perf_data) != 0x18);
	145	+ BUILD_BUG_ON(offsetof(siginfo_t, si_perf_type) != 0x20);
	146	+ BUILD_BUG_ON(offsetof(compat_siginfo_t, si_perf_data) != 0x10);
	147	+ BUILD_BUG_ON(offsetof(compat_siginfo_t, si_perf_type) != 0x14);
143	148
144	149	CHECK_CSI_OFFSET(_sigpoll);
145	150	CHECK_CSI_SIZE (_sigpoll, 2*sizeof(int));

arch/x86/kernel/smpboot.c+1−1

@@ -2043,7 +2043,7 @@ static bool amd_set_max_freq_ratio(void) · 2042 unmodified lines
2043	2043	return false;
2044	2044	}
2045	2045
2046		− highest_perf = perf_caps.highest_perf;
	2046	+ highest_perf = amd_get_highest_perf();
2047	2047	nominal_perf = perf_caps.nominal_perf;
2048	2048
2049	2049	if (!highest_perf \|\| !nominal_perf) {

arch/x86/kvm/cpuid.c+19−2

@@ -458,7 +458,7 @@ void kvm_set_cpu_caps(void) · 457 unmodified lines
458	458	F(AVX512_VPOPCNTDQ) \| F(UMIP) \| F(AVX512_VBMI2) \| F(GFNI) \|
459	459	F(VAES) \| F(VPCLMULQDQ) \| F(AVX512_VNNI) \| F(AVX512_BITALG) \|
460	460	F(CLDEMOTE) \| F(MOVDIRI) \| F(MOVDIR64B) \| 0 /WAITPKG/ \|
461		− F(SGX_LC)
	461	+ F(SGX_LC) \| F(BUS_LOCK_DETECT)
462	462	);
463	463	/* Set LA57 based on hardware capability. */
464	464	if (cpuid_ecx(7) & F(LA57))
@@ -567,6 +567,21 @@ void kvm_set_cpu_caps(void) · 102 unmodified lines
567	567	F(ACE2) \| F(ACE2_EN) \| F(PHE) \| F(PHE_EN) \|
568	568	F(PMM) \| F(PMM_EN)
569	569	);
	570	+
	571	+ /*
	572	+ * Hide RDTSCP and RDPID if either feature is reported as supported but
	573	+ * probing MSR_TSC_AUX failed. This is purely a sanity check and
	574	+ * should never happen, but the guest will likely crash if RDTSCP or
	575	+ * RDPID is misreported, and KVM has botched MSR_TSC_AUX emulation in
	576	+ * the past. For example, the sanity check may fire if this instance of
	577	+ * KVM is running as L1 on top of an older, broken KVM.
	578	+ */
	579	+ if (WARN_ON((kvm_cpu_cap_has(X86_FEATURE_RDTSCP) \|\|
	580	+ kvm_cpu_cap_has(X86_FEATURE_RDPID)) &&
	581	+ !kvm_is_supported_user_return_msr(MSR_TSC_AUX))) {
	582	+ kvm_cpu_cap_clear(X86_FEATURE_RDTSCP);
	583	+ kvm_cpu_cap_clear(X86_FEATURE_RDPID);
	584	+ }
570	585	}
571	586	EXPORT_SYMBOL_GPL(kvm_set_cpu_caps);
572	587
@@ -637,8 +652,10 @@ static int __do_cpuid_func_emulated(struct kvm_cpuid_array *array, u32 func) · 64 unmodified lines
637	652	case 7:
638	653	entry->flags \|= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
639	654	entry->eax = 0;
640		− entry->ecx = F(RDPID);
	655	+ if (kvm_cpu_cap_has(X86_FEATURE_RDTSCP))
	656	+ entry->ecx = F(RDPID);
641	657	++array->nent;
	658	+ break;
642	659	default:
643	660	break;
644	661	}

arch/x86/kvm/emulate.c+4−3

@@ -4502,7 +4502,7 @@ static const struct opcode group8[] = { · 4501 unmodified lines
4502	4502	* from the register case of group9.
4503	4503	*/
4504	4504	static const struct gprefix pfx_0f_c7_7 = {
4505		− N, N, N, II(DstMem \| ModRM \| Op3264 \| EmulateOnUD, em_rdpid, rdtscp),
	4505	+ N, N, N, II(DstMem \| ModRM \| Op3264 \| EmulateOnUD, em_rdpid, rdpid),
4506	4506	};
4507	4507
4508	4508
@@ -5111,7 +5111,7 @@ done: · 602 unmodified lines
5111	5111	return rc;
5112	5112	}
5113	5113
5114		−int x86_decode_insn(struct x86_emulate_ctxt ctxt, void insn, int insn_len)
	5114	+int x86_decode_insn(struct x86_emulate_ctxt ctxt, void insn, int insn_len, int emulation_type)
5115	5115	{
5116	5116	int rc = X86EMUL_CONTINUE;
5117	5117	int mode = ctxt->mode;
@@ -5322,7 +5322,8 @@ done_prefixes: · 204 unmodified lines
5322	5322
5323	5323	ctxt->execute = opcode.u.execute;
5324	5324
5325		− if (unlikely(ctxt->ud) && likely(!(ctxt->d & EmulateOnUD)))
	5325	+ if (unlikely(emulation_type & EMULTYPE_TRAP_UD) &&
	5326	+ likely(!(ctxt->d & EmulateOnUD)))
5326	5327	return EMULATION_FAILED;
5327	5328
5328	5329	if (unlikely(ctxt->d &

arch/x86/kvm/hyperv.c+8−0

@@ -1172,6 +1172,7 @@ void kvm_hv_invalidate_tsc_page(struct kvm *kvm) · 1171 unmodified lines
1172	1172	{
1173	1173	struct kvm_hv *hv = to_kvm_hv(kvm);
1174	1174	u64 gfn;
	1175	+ int idx;
1175	1176
1176	1177	if (hv->hv_tsc_page_status == HV_TSC_PAGE_BROKEN \|\|
1177	1178	hv->hv_tsc_page_status == HV_TSC_PAGE_UNSET \|\|
@@ -1190,9 +1191,16 @@ void kvm_hv_invalidate_tsc_page(struct kvm *kvm) · 12 unmodified lines
1190	1191	gfn = hv->hv_tsc_page >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
1191	1192
1192	1193	hv->tsc_ref.tsc_sequence = 0;
	1194	+
	1195	+ /*
	1196	+ * Take the srcu lock as memslots will be accessed to check the gfn
	1197	+ * cache generation against the memslots generation.
	1198	+ */
	1199	+ idx = srcu_read_lock(&kvm->srcu);
1193	1200	if (kvm_write_guest(kvm, gfn_to_gpa(gfn),
1194	1201	&hv->tsc_ref, sizeof(hv->tsc_ref.tsc_sequence)))
1195	1202	hv->hv_tsc_page_status = HV_TSC_PAGE_BROKEN;
	1203	+ srcu_read_unlock(&kvm->srcu, idx);
1196	1204
1197	1205	out_unlock:
1198	1206	mutex_unlock(&hv->hv_lock);

arch/x86/kvm/kvm_emulate.h+2−2

@@ -314,7 +314,6 @@ struct x86_emulate_ctxt { · 313 unmodified lines
314	314	int interruptibility;
315	315
316	316	bool perm_ok; /* do not check permissions if true */
317		− bool ud; /* inject an #UD if host doesn't support insn */
318	317	bool tf; /* TF value before instruction (after for syscall/sysret) */
319	318
320	319	bool have_exception;
@@ -468,6 +467,7 @@ enum x86_intercept { · 147 unmodified lines
468	467	x86_intercept_clgi,
469	468	x86_intercept_skinit,
470	469	x86_intercept_rdtscp,
	470	+ x86_intercept_rdpid,
471	471	x86_intercept_icebp,
472	472	x86_intercept_wbinvd,
473	473	x86_intercept_monitor,
@@ -490,7 +490,7 @@ enum x86_intercept { · 16 unmodified lines
490	490	#define X86EMUL_MODE_HOST X86EMUL_MODE_PROT64
491	491	#endif
492	492
493		−int x86_decode_insn(struct x86_emulate_ctxt ctxt, void insn, int insn_len);
	493	+int x86_decode_insn(struct x86_emulate_ctxt ctxt, void insn, int insn_len, int emulation_type);
494	494	bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt);
495	495	#define EMULATION_FAILED -1
496	496	#define EMULATION_OK 0

arch/x86/kvm/lapic.c+27−11

@@ -1410,6 +1410,9 @@ int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len, · 1409 unmodified lines
1410	1410	if (!apic_x2apic_mode(apic))
1411	1411	valid_reg_mask \|= APIC_REG_MASK(APIC_ARBPRI);
1412	1412
	1413	+ if (alignment + len > 4)
	1414	+ return 1;
	1415	+
1413	1416	if (offset > 0x3f0 \|\| !(valid_reg_mask & APIC_REG_MASK(offset)))
1414	1417	return 1;
1415	1418
@@ -1494,6 +1497,15 @@ static void limit_periodic_timer_frequency(struct kvm_lapic *apic) · 78 unmodified lines
1494	1497
1495	1498	static void cancel_hv_timer(struct kvm_lapic *apic);
1496	1499
	1500	+static void cancel_apic_timer(struct kvm_lapic *apic)
	1501	+{
	1502	+ hrtimer_cancel(&apic->lapic_timer.timer);
	1503	+ preempt_disable();
	1504	+ if (apic->lapic_timer.hv_timer_in_use)
	1505	+ cancel_hv_timer(apic);
	1506	+ preempt_enable();
	1507	+}
	1508	+
1497	1509	static void apic_update_lvtt(struct kvm_lapic *apic)
1498	1510	{
1499	1511	u32 timer_mode = kvm_lapic_get_reg(apic, APIC_LVTT) &
@@ -1502,11 +1514,7 @@ static void apic_update_lvtt(struct kvm_lapic *apic) · 2 unmodified lines
1502	1514	if (apic->lapic_timer.timer_mode != timer_mode) {
1503	1515	if (apic_lvtt_tscdeadline(apic) != (timer_mode ==
1504	1516	APIC_LVT_TIMER_TSCDEADLINE)) {
1505		− hrtimer_cancel(&apic->lapic_timer.timer);
1506		− preempt_disable();
1507		− if (apic->lapic_timer.hv_timer_in_use)
1508		− cancel_hv_timer(apic);
1509		− preempt_enable();
	1517	+ cancel_apic_timer(apic);
1510	1518	kvm_lapic_set_reg(apic, APIC_TMICT, 0);
1511	1519	apic->lapic_timer.period = 0;
1512	1520	apic->lapic_timer.tscdeadline = 0;
@@ -1598,11 +1606,19 @@ static void __kvm_wait_lapic_expire(struct kvm_vcpu *vcpu) · 85 unmodified lines
1598	1606	guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1599	1607	apic->lapic_timer.advance_expire_delta = guest_tsc - tsc_deadline;
1600	1608
	1609	+ if (lapic_timer_advance_dynamic) {
	1610	+ adjust_lapic_timer_advance(vcpu, apic->lapic_timer.advance_expire_delta);
	1611	+ /*
	1612	+ * If the timer fired early, reread the TSC to account for the
	1613	+ * overhead of the above adjustment to avoid waiting longer
	1614	+ * than is necessary.
	1615	+ */
	1616	+ if (guest_tsc < tsc_deadline)
	1617	+ guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
	1618	+ }
	1619	+
1601	1620	if (guest_tsc < tsc_deadline)
1602	1621	__wait_lapic_expire(vcpu, tsc_deadline - guest_tsc);
1603		−
1604		− if (lapic_timer_advance_dynamic)
1605		− adjust_lapic_timer_advance(vcpu, apic->lapic_timer.advance_expire_delta);
1606	1622	}
1607	1623
1608	1624	void kvm_wait_lapic_expire(struct kvm_vcpu *vcpu)
@@ -1661,7 +1677,7 @@ static void apic_timer_expired(struct kvm_lapic *apic, bool from_timer_fn) · 52 unmodified lines
1661	1677	}
1662	1678
1663	1679	atomic_inc(&apic->lapic_timer.pending);
1664		− kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
	1680	+ kvm_make_request(KVM_REQ_UNBLOCK, vcpu);
1665	1681	if (from_timer_fn)
1666	1682	kvm_vcpu_kick(vcpu);
1667	1683	}
@@ -1913,8 +1929,8 @@ void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu) · 245 unmodified lines
1913	1929	if (!apic->lapic_timer.hv_timer_in_use)
1914	1930	goto out;
1915	1931	WARN_ON(rcuwait_active(&vcpu->wait));
1916		− cancel_hv_timer(apic);
1917	1932	apic_timer_expired(apic, false);
	1933	+ cancel_hv_timer(apic);
1918	1934
1919	1935	if (apic_lvtt_period(apic) && apic->lapic_timer.period) {
1920	1936	advance_periodic_target_expiration(apic);
@@ -2084,7 +2100,7 @@ int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val) · 163 unmodified lines
2084	2100	if (apic_lvtt_tscdeadline(apic))
2085	2101	break;
2086	2102
2087		− hrtimer_cancel(&apic->lapic_timer.timer);
	2103	+ cancel_apic_timer(apic);
2088	2104	kvm_lapic_set_reg(apic, APIC_TMICT, val);
2089	2105	start_apic_timer(apic);
2090	2106	break;

arch/x86/kvm/mmu/mmu.c+35−11

@@ -3310,12 +3310,12 @@ static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu) · 3309 unmodified lines
3310	3310	if (mmu->shadow_root_level == PT64_ROOT_4LEVEL) {
3311	3311	pm_mask \|= PT_ACCESSED_MASK \| PT_WRITABLE_MASK \| PT_USER_MASK;
3312	3312
3313		− if (WARN_ON_ONCE(!mmu->lm_root)) {
	3313	+ if (WARN_ON_ONCE(!mmu->pml4_root)) {
3314	3314	r = -EIO;
3315	3315	goto out_unlock;
3316	3316	}
3317	3317
3318		− mmu->lm_root[0] = __pa(mmu->pae_root) \| pm_mask;
	3318	+ mmu->pml4_root[0] = __pa(mmu->pae_root) \| pm_mask;
3319	3319	}
3320	3320
3321	3321	for (i = 0; i < 4; ++i) {
@@ -3335,7 +3335,7 @@ static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu) · 13 unmodified lines
3335	3335	}
3336	3336
3337	3337	if (mmu->shadow_root_level == PT64_ROOT_4LEVEL)
3338		− mmu->root_hpa = __pa(mmu->lm_root);
	3338	+ mmu->root_hpa = __pa(mmu->pml4_root);
3339	3339	else
3340	3340	mmu->root_hpa = __pa(mmu->pae_root);
3341	3341
@@ -3350,7 +3350,7 @@ out_unlock: · 8 unmodified lines
3350	3350	static int mmu_alloc_special_roots(struct kvm_vcpu *vcpu)
3351	3351	{
3352	3352	struct kvm_mmu *mmu = vcpu->arch.mmu;
3353		− u64 lm_root, pae_root;
	3353	+ u64 pml4_root, pae_root;
3354	3354
3355	3355	/*
3356	3356	* When shadowing 32-bit or PAE NPT with 64-bit NPT, the PML4 and PDP
@@ -3369,14 +3369,14 @@ static int mmu_alloc_special_roots(struct kvm_vcpu *vcpu) · 12 unmodified lines
3369	3369	if (WARN_ON_ONCE(mmu->shadow_root_level != PT64_ROOT_4LEVEL))
3370	3370	return -EIO;
3371	3371
3372		− if (mmu->pae_root && mmu->lm_root)
	3372	+ if (mmu->pae_root && mmu->pml4_root)
3373	3373	return 0;
3374	3374
3375	3375	/*
3376	3376	* The special roots should always be allocated in concert. Yell and
3377	3377	* bail if KVM ends up in a state where only one of the roots is valid.
3378	3378	*/
3379		− if (WARN_ON_ONCE(!tdp_enabled \|\| mmu->pae_root \|\| mmu->lm_root))
	3379	+ if (WARN_ON_ONCE(!tdp_enabled \|\| mmu->pae_root \|\| mmu->pml4_root))
3380	3380	return -EIO;
3381	3381
3382	3382	/*
@@ -3387,14 +3387,14 @@ static int mmu_alloc_special_roots(struct kvm_vcpu *vcpu) · 4 unmodified lines
3387	3387	if (!pae_root)
3388	3388	return -ENOMEM;
3389	3389
3390		− lm_root = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT);
3391		− if (!lm_root) {
	3390	+ pml4_root = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT);
	3391	+ if (!pml4_root) {
3392	3392	free_page((unsigned long)pae_root);
3393	3393	return -ENOMEM;
3394	3394	}
3395	3395
3396	3396	mmu->pae_root = pae_root;
3397		− mmu->lm_root = lm_root;
	3397	+ mmu->pml4_root = pml4_root;
3398	3398
3399	3399	return 0;
3400	3400	}
@@ -4739,9 +4739,33 @@ static void init_kvm_softmmu(struct kvm_vcpu *vcpu) · 1338 unmodified lines
4739	4739	context->inject_page_fault = kvm_inject_page_fault;
4740	4740	}
4741	4741
	4742	+static union kvm_mmu_role kvm_calc_nested_mmu_role(struct kvm_vcpu *vcpu)
	4743	+{
	4744	+ union kvm_mmu_role role = kvm_calc_shadow_root_page_role_common(vcpu, false);
	4745	+
	4746	+ /*
	4747	+ * Nested MMUs are used only for walking L2's gva->gpa, they never have
	4748	+ * shadow pages of their own and so "direct" has no meaning. Set it
	4749	+ * to "true" to try to detect bogus usage of the nested MMU.
	4750	+ */
	4751	+ role.base.direct = true;
	4752	+
	4753	+ if (!is_paging(vcpu))
	4754	+ role.base.level = 0;
	4755	+ else if (is_long_mode(vcpu))
	4756	+ role.base.level = is_la57_mode(vcpu) ? PT64_ROOT_5LEVEL :
	4757	+ PT64_ROOT_4LEVEL;
	4758	+ else if (is_pae(vcpu))
	4759	+ role.base.level = PT32E_ROOT_LEVEL;
	4760	+ else
	4761	+ role.base.level = PT32_ROOT_LEVEL;
	4762	+
	4763	+ return role;
	4764	+}
	4765	+
4742	4766	static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
4743	4767	{
4744		− union kvm_mmu_role new_role = kvm_calc_mmu_role_common(vcpu, false);
	4768	+ union kvm_mmu_role new_role = kvm_calc_nested_mmu_role(vcpu);
4745	4769	struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
4746	4770
4747	4771	if (new_role.as_u64 == g_context->mmu_role.as_u64)
@@ -5261,7 +5285,7 @@ static void free_mmu_pages(struct kvm_mmu *mmu) · 513 unmodified lines
5261	5285	if (!tdp_enabled && mmu->pae_root)
5262	5286	set_memory_encrypted((unsigned long)mmu->pae_root, 1);
5263	5287	free_page((unsigned long)mmu->pae_root);
5264		− free_page((unsigned long)mmu->lm_root);
	5288	+ free_page((unsigned long)mmu->pml4_root);
5265	5289	}
5266	5290
5267	5291	static int __kvm_mmu_create(struct kvm_vcpu vcpu, struct kvm_mmu mmu)

arch/x86/kvm/mmu/paging_tmpl.h+9−5

@@ -90,8 +90,8 @@ struct guest_walker { · 89 unmodified lines
90	90	gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
91	91	pt_element_t __user *ptep_user[PT_MAX_FULL_LEVELS];
92	92	bool pte_writable[PT_MAX_FULL_LEVELS];
93		− unsigned pt_access;
94		− unsigned pte_access;
	93	+ unsigned int pt_access[PT_MAX_FULL_LEVELS];
	94	+ unsigned int pte_access;
95	95	gfn_t gfn;
96	96	struct x86_exception fault;
97	97	};
@@ -418,13 +418,15 @@ retry_walk: · 320 unmodified lines
418	418	}
419	419
420	420	walker->ptes[walker->level - 1] = pte;
	421	+
	422	+ /* Convert to ACC__MASK flags for struct guest_walker. /
	423	+ walker->pt_access[walker->level - 1] = FNAME(gpte_access)(pt_access ^ walk_nx_mask);
421	424	} while (!is_last_gpte(mmu, walker->level, pte));
422	425
423	426	pte_pkey = FNAME(gpte_pkeys)(vcpu, pte);
424	427	accessed_dirty = have_ad ? pte_access & PT_GUEST_ACCESSED_MASK : 0;
425	428
426	429	/* Convert to ACC__MASK flags for struct guest_walker. /
427		− walker->pt_access = FNAME(gpte_access)(pt_access ^ walk_nx_mask);
428	430	walker->pte_access = FNAME(gpte_access)(pte_access ^ walk_nx_mask);
429	431	errcode = permission_fault(vcpu, mmu, walker->pte_access, pte_pkey, access);
430	432	if (unlikely(errcode))
@@ -463,7 +465,8 @@ retry_walk: · 32 unmodified lines
463	465	}
464	466
465	467	pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
466		− __func__, (u64)pte, walker->pte_access, walker->pt_access);
	468	+ __func__, (u64)pte, walker->pte_access,
	469	+ walker->pt_access[walker->level - 1]);
467	470	return 1;
468	471
469	472	error:
@@ -643,7 +646,7 @@ static int FNAME(fetch)(struct kvm_vcpu *vcpu, gpa_t addr, · 173 unmodified lines
643	646	bool huge_page_disallowed = exec && nx_huge_page_workaround_enabled;
644	647	struct kvm_mmu_page *sp = NULL;
645	648	struct kvm_shadow_walk_iterator it;
646		− unsigned direct_access, access = gw->pt_access;
	649	+ unsigned int direct_access, access;
647	650	int top_level, level, req_level, ret;
648	651	gfn_t base_gfn = gw->gfn;
649	652
@@ -675,6 +678,7 @@ static int FNAME(fetch)(struct kvm_vcpu *vcpu, gpa_t addr, · 25 unmodified lines
675	678	sp = NULL;
676	679	if (!is_shadow_present_pte(*it.sptep)) {
677	680	table_gfn = gw->table_gfn[it.level - 2];
	681	+ access = gw->pt_access[it.level - 2];
678	682	sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1,
679	683	false, access);
680	684	}

arch/x86/kvm/mmu/tdp_mmu.c+19−4

@@ -388,7 +388,7 @@ static void handle_removed_tdp_mmu_page(struct kvm *kvm, tdp_ptep_t pt, · 387 unmodified lines
388	388	}
389	389
390	390	/**
391		− * handle_changed_spte - handle bookkeeping associated with an SPTE change
	391	+ * __handle_changed_spte - handle bookkeeping associated with an SPTE change
392	392	* @kvm: kvm instance
393	393	* @as_id: the address space of the paging structure the SPTE was a part of
394	394	* @gfn: the base GFN that was mapped by the SPTE
@@ -444,6 +444,13 @@ static void __handle_changed_spte(struct kvm *kvm, int as_id, gfn_t gfn, · 49 unmodified lines
444	444
445	445	trace_kvm_tdp_mmu_spte_changed(as_id, gfn, level, old_spte, new_spte);
446	446
	447	+ if (is_large_pte(old_spte) != is_large_pte(new_spte)) {
	448	+ if (is_large_pte(old_spte))
	449	+ atomic64_sub(1, (atomic64_t*)&kvm->stat.lpages);
	450	+ else
	451	+ atomic64_add(1, (atomic64_t*)&kvm->stat.lpages);
	452	+ }
	453	+
447	454	/*
448	455	* The only times a SPTE should be changed from a non-present to
449	456	* non-present state is when an MMIO entry is installed/modified/
@@ -1009,6 +1016,14 @@ int kvm_tdp_mmu_map(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code, · 559 unmodified lines
1009	1016	}
1010	1017
1011	1018	if (!is_shadow_present_pte(iter.old_spte)) {
	1019	+ /*
	1020	+ * If SPTE has been forzen by another thread, just
	1021	+ * give up and retry, avoiding unnecessary page table
	1022	+ * allocation and free.
	1023	+ */
	1024	+ if (is_removed_spte(iter.old_spte))
	1025	+ break;
	1026	+
1012	1027	sp = alloc_tdp_mmu_page(vcpu, iter.gfn, iter.level);
1013	1028	child_pt = sp->spt;
1014	1029
@@ -1177,9 +1192,9 @@ bool kvm_tdp_mmu_set_spte_gfn(struct kvm kvm, struct kvm_gfn_range range) · 162 unmodified lines
1177	1192	}
1178	1193
1179	1194	/*
1180		− * Remove write access from all the SPTEs mapping GFNs [start, end). If
1181		− * skip_4k is set, SPTEs that map 4k pages, will not be write-protected.
1182		− * Returns true if an SPTE has been changed and the TLBs need to be flushed.
	1195	+ * Remove write access from all SPTEs at or above min_level that map GFNs
	1196	+ * [start, end). Returns true if an SPTE has been changed and the TLBs need to
	1197	+ * be flushed.
1183	1198	*/
1184	1199	static bool wrprot_gfn_range(struct kvm kvm, struct kvm_mmu_page root,
1185	1200	gfn_t start, gfn_t end, int min_level)

arch/x86/kvm/svm/avic.c+5−7

@@ -28,10 +28,8 @@ · 27 unmodified lines
28	28	#include "svm.h"
29	29
30	30	/* enable / disable AVIC */
31		−int avic;
32		−#ifdef CONFIG_X86_LOCAL_APIC
33		−module_param(avic, int, S_IRUGO);
34		−#endif
	31	+bool avic;
	32	+module_param(avic, bool, S_IRUGO);
35	33
36	34	#define SVM_AVIC_DOORBELL 0xc001011b
37	35
@@ -223,7 +221,7 @@ static u64 avic_get_physical_id_entry(struct kvm_vcpu vcpu, · 185 unmodified lines
223	221	return &avic_physical_id_table[index];
224	222	}
225	223
226		−/**
	224	+/*
227	225	* Note:
228	226	* AVIC hardware walks the nested page table to check permissions,
229	227	* but does not use the SPA address specified in the leaf page
@@ -766,7 +764,7 @@ out: · 536 unmodified lines
766	764	return ret;
767	765	}
768	766
769		−/**
	767	+/*
770	768	* Note:
771	769	* The HW cannot support posting multicast/broadcast
772	770	* interrupts to a vCPU. So, we still use legacy interrupt
@@ -1007,7 +1005,7 @@ void avic_vcpu_put(struct kvm_vcpu *vcpu) · 234 unmodified lines
1007	1005	WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
1008	1006	}
1009	1007
1010		−/**
	1008	+/*
1011	1009	* This function is called during VCPU halt/unhalt.
1012	1010	*/
1013	1011	static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run)

arch/x86/kvm/svm/nested.c+19−4

@@ -764,7 +764,6 @@ int nested_svm_vmexit(struct vcpu_svm *svm) · 763 unmodified lines
764	764	nested_svm_copy_common_state(svm->nested.vmcb02.ptr, svm->vmcb01.ptr);
765	765
766	766	svm_switch_vmcb(svm, &svm->vmcb01);
767		− WARN_ON_ONCE(svm->vmcb->control.exit_code != SVM_EXIT_VMRUN);
768	767
769	768	/*
770	769	* On vmexit the GIF is set to false and
@@ -872,6 +871,15 @@ void svm_free_nested(struct vcpu_svm *svm) · 101 unmodified lines
872	871	__free_page(virt_to_page(svm->nested.vmcb02.ptr));
873	872	svm->nested.vmcb02.ptr = NULL;
874	873
	874	+ /*
	875	+ * When last_vmcb12_gpa matches the current vmcb12 gpa,
	876	+ * some vmcb12 fields are not loaded if they are marked clean
	877	+ * in the vmcb12, since in this case they are up to date already.
	878	+ *
	879	+ * When the vmcb02 is freed, this optimization becomes invalid.
	880	+ */
	881	+ svm->nested.last_vmcb12_gpa = INVALID_GPA;
	882	+
875	883	svm->nested.initialized = false;
876	884	}
877	885
@@ -884,9 +892,11 @@ void svm_leave_nested(struct vcpu_svm *svm) · 6 unmodified lines
884	892
885	893	if (is_guest_mode(vcpu)) {
886	894	svm->nested.nested_run_pending = 0;
	895	+ svm->nested.vmcb12_gpa = INVALID_GPA;
	896	+
887	897	leave_guest_mode(vcpu);
888	898
889		− svm_switch_vmcb(svm, &svm->nested.vmcb02);
	899	+ svm_switch_vmcb(svm, &svm->vmcb01);
890	900
891	901	nested_svm_uninit_mmu_context(vcpu);
892	902	vmcb_mark_all_dirty(svm->vmcb);
@@ -1298,12 +1308,17 @@ static int svm_set_nested_state(struct kvm_vcpu *vcpu, · 405 unmodified lines
1298	1308	* L2 registers if needed are moved from the current VMCB to VMCB02.
1299	1309	*/
1300	1310
	1311	+ if (is_guest_mode(vcpu))
	1312	+ svm_leave_nested(svm);
	1313	+ else
	1314	+ svm->nested.vmcb02.ptr->save = svm->vmcb01.ptr->save;
	1315	+
	1316	+ svm_set_gif(svm, !!(kvm_state->flags & KVM_STATE_NESTED_GIF_SET));
	1317	+
1301	1318	svm->nested.nested_run_pending =
1302	1319	!!(kvm_state->flags & KVM_STATE_NESTED_RUN_PENDING);
1303	1320
1304	1321	svm->nested.vmcb12_gpa = kvm_state->hdr.svm.vmcb_pa;
1305		− if (svm->current_vmcb == &svm->vmcb01)
1306		− svm->nested.vmcb02.ptr->save = svm->vmcb01.ptr->save;
1307	1322
1308	1323	svm->vmcb01.ptr->save.es = save->es;
1309	1324	svm->vmcb01.ptr->save.cs = save->cs;

arch/x86/kvm/svm/sev.c+31−27

@@ -199,9 +199,19 @@ static void sev_asid_free(struct kvm_sev_info *sev) · 198 unmodified lines
199	199	sev->misc_cg = NULL;
200	200	}
201	201
202		−static void sev_unbind_asid(struct kvm *kvm, unsigned int handle)
	202	+static void sev_decommission(unsigned int handle)
203	203	{
204	204	struct sev_data_decommission decommission;
	205	+
	206	+ if (!handle)
	207	+ return;
	208	+
	209	+ decommission.handle = handle;
	210	+ sev_guest_decommission(&decommission, NULL);
	211	+}
	212	+
	213	+static void sev_unbind_asid(struct kvm *kvm, unsigned int handle)
	214	+{
205	215	struct sev_data_deactivate deactivate;
206	216
207	217	if (!handle)
@@ -214,9 +224,7 @@ static void sev_unbind_asid(struct kvm *kvm, unsigned int handle) · 6 unmodified lines
214	224	sev_guest_deactivate(&deactivate, NULL);
215	225	up_read(&sev_deactivate_lock);
216	226
217		− /* decommission handle */
218		− decommission.handle = handle;
219		− sev_guest_decommission(&decommission, NULL);
	227	+ sev_decommission(handle);
220	228	}
221	229
222	230	static int sev_guest_init(struct kvm kvm, struct kvm_sev_cmd argp)
@@ -341,8 +349,10 @@ static int sev_launch_start(struct kvm kvm, struct kvm_sev_cmd argp) · 118 unmodified lines
341	349
342	350	/* Bind ASID to this guest */
343	351	ret = sev_bind_asid(kvm, start.handle, error);
344		− if (ret)
	352	+ if (ret) {
	353	+ sev_decommission(start.handle);
345	354	goto e_free_session;
	355	+ }
346	356
347	357	/* return handle to userspace */
348	358	params.handle = start.handle;
@@ -763,7 +773,7 @@ static int __sev_dbg_decrypt(struct kvm *kvm, unsigned long src_paddr, · 414 unmodified lines
763	773	}
764	774
765	775	static int __sev_dbg_decrypt_user(struct kvm *kvm, unsigned long paddr,
766		− unsigned long __user dst_uaddr,
	776	+ void __user *dst_uaddr,
767	777	unsigned long dst_paddr,
768	778	int size, int *err)
769	779	{
@@ -787,8 +797,7 @@ static int __sev_dbg_decrypt_user(struct kvm *kvm, unsigned long paddr, · 17 unmodified lines
787	797
788	798	if (tpage) {
789	799	offset = paddr & 15;
790		− if (copy_to_user((void __user *)(uintptr_t)dst_uaddr,
791		− page_address(tpage) + offset, size))
	800	+ if (copy_to_user(dst_uaddr, page_address(tpage) + offset, size))
792	801	ret = -EFAULT;
793	802	}
794	803
@@ -800,9 +809,9 @@ e_free: · 5 unmodified lines
800	809	}
801	810
802	811	static int __sev_dbg_encrypt_user(struct kvm *kvm, unsigned long paddr,
803		− unsigned long __user vaddr,
	812	+ void __user *vaddr,
804	813	unsigned long dst_paddr,
805		− unsigned long __user dst_vaddr,
	814	+ void __user *dst_vaddr,
806	815	int size, int *error)
807	816	{
808	817	struct page *src_tpage = NULL;
@@ -810,13 +819,12 @@ static int __sev_dbg_encrypt_user(struct kvm *kvm, unsigned long paddr, · 1 unmodified line
810	819	int ret, len = size;
811	820
812	821	/* If source buffer is not aligned then use an intermediate buffer */
813		− if (!IS_ALIGNED(vaddr, 16)) {
	822	+ if (!IS_ALIGNED((unsigned long)vaddr, 16)) {
814	823	src_tpage = alloc_page(GFP_KERNEL);
815	824	if (!src_tpage)
816	825	return -ENOMEM;
817	826
818		− if (copy_from_user(page_address(src_tpage),
819		− (void __user *)(uintptr_t)vaddr, size)) {
	827	+ if (copy_from_user(page_address(src_tpage), vaddr, size)) {
820	828	__free_page(src_tpage);
821	829	return -EFAULT;
822	830	}
@@ -830,7 +838,7 @@ static int __sev_dbg_encrypt_user(struct kvm *kvm, unsigned long paddr, · 7 unmodified lines
830	838	* - copy the source buffer in an intermediate buffer
831	839	* - use the intermediate buffer as source buffer
832	840	*/
833		− if (!IS_ALIGNED(dst_vaddr, 16) \|\| !IS_ALIGNED(size, 16)) {
	841	+ if (!IS_ALIGNED((unsigned long)dst_vaddr, 16) \|\| !IS_ALIGNED(size, 16)) {
834	842	int dst_offset;
835	843
836	844	dst_tpage = alloc_page(GFP_KERNEL);
@@ -855,7 +863,7 @@ static int __sev_dbg_encrypt_user(struct kvm *kvm, unsigned long paddr, · 18 unmodified lines
855	863	page_address(src_tpage), size);
856	864	else {
857	865	if (copy_from_user(page_address(dst_tpage) + dst_offset,
858		− (void __user *)(uintptr_t)vaddr, size)) {
	866	+ vaddr, size)) {
859	867	ret = -EFAULT;
860	868	goto e_free;
861	869	}
@@ -935,15 +943,15 @@ static int sev_dbg_crypt(struct kvm kvm, struct kvm_sev_cmd argp, bool dec) · 73 unmodified lines
935	943	if (dec)
936	944	ret = __sev_dbg_decrypt_user(kvm,
937	945	__sme_page_pa(src_p[0]) + s_off,
938		− dst_vaddr,
	946	+ (void __user *)dst_vaddr,
939	947	__sme_page_pa(dst_p[0]) + d_off,
940	948	len, &argp->error);
941	949	else
942	950	ret = __sev_dbg_encrypt_user(kvm,
943	951	__sme_page_pa(src_p[0]) + s_off,
944		− vaddr,
	952	+ (void __user *)vaddr,
945	953	__sme_page_pa(dst_p[0]) + d_off,
946		− dst_vaddr,
	954	+ (void __user *)dst_vaddr,
947	955	len, &argp->error);
948	956
949	957	sev_unpin_memory(kvm, src_p, n);
@@ -1105,10 +1113,9 @@ __sev_send_start_query_session_length(struct kvm kvm, struct kvm_sev_cmd argp, · 155 unmodified lines
1105	1113	struct sev_data_send_start data;
1106	1114	int ret;
1107	1115
	1116	+ memset(&data, 0, sizeof(data));
1108	1117	data.handle = sev->handle;
1109	1118	ret = sev_issue_cmd(kvm, SEV_CMD_SEND_START, &data, &argp->error);
1110		− if (ret < 0)
1111		− return ret;
1112	1119
1113	1120	params->session_len = data.session_len;
1114	1121	if (copy_to_user((void __user *)(uintptr_t)argp->data, params,
@@ -1217,10 +1224,9 @@ __sev_send_update_data_query_lengths(struct kvm kvm, struct kvm_sev_cmd argp, · 102 unmodified lines
1217	1224	struct sev_data_send_update_data data;
1218	1225	int ret;
1219	1226
	1227	+ memset(&data, 0, sizeof(data));
1220	1228	data.handle = sev->handle;
1221	1229	ret = sev_issue_cmd(kvm, SEV_CMD_SEND_UPDATE_DATA, &data, &argp->error);
1222		− if (ret < 0)
1223		− return ret;
1224	1230
1225	1231	params->hdr_len = data.hdr_len;
1226	1232	params->trans_len = data.trans_len;
@@ -1764,7 +1770,8 @@ e_mirror_unlock: · 537 unmodified lines
1764	1770	e_source_unlock:
1765	1771	mutex_unlock(&source_kvm->lock);
1766	1772	e_source_put:
1767		− fput(source_kvm_file);
	1773	+ if (source_kvm_file)
	1774	+ fput(source_kvm_file);
1768	1775	return ret;
1769	1776	}
1770	1777
@@ -2198,7 +2205,7 @@ vmgexit_err: · 427 unmodified lines
2198	2205	return -EINVAL;
2199	2206	}
2200	2207
2201		−static void pre_sev_es_run(struct vcpu_svm *svm)
	2208	+void sev_es_unmap_ghcb(struct vcpu_svm *svm)
2202	2209	{
2203	2210	if (!svm->ghcb)
2204	2211	return;
@@ -2234,9 +2241,6 @@ void pre_sev_run(struct vcpu_svm *svm, int cpu) · 29 unmodified lines
2234	2241	struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2235	2242	int asid = sev_get_asid(svm->vcpu.kvm);
2236	2243
2237		− /* Perform any SEV-ES pre-run actions */
2238		− pre_sev_es_run(svm);
2239		−
2240	2244	/* Assign the asid allocated with this SEV guest */
2241	2245	svm->asid = asid;
2242	2246

arch/x86/kvm/svm/svm.c+31−39

@@ -212,7 +212,7 @@ DEFINE_PER_CPU(struct svm_cpu_data *, svm_data); · 211 unmodified lines
212	212	* RDTSCP and RDPID are not used in the kernel, specifically to allow KVM to
213	213	* defer the restoration of TSC_AUX until the CPU returns to userspace.
214	214	*/
215		−#define TSC_AUX_URET_SLOT 0
	215	+static int tsc_aux_uret_slot __read_mostly = -1;
216	216
217	217	static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
218	218
@@ -447,6 +447,11 @@ static int has_svm(void) · 228 unmodified lines
447	447	return 0;
448	448	}
449	449
	450	+ if (pgtable_l5_enabled()) {
	451	+ pr_info("KVM doesn't yet support 5-level paging on AMD SVM\n");
	452	+ return 0;
	453	+ }
	454	+
450	455	return 1;
451	456	}
452	457
@@ -858,8 +863,8 @@ static __init void svm_adjust_mmio_mask(void) · 405 unmodified lines
858	863	return;
859	864
860	865	/* If memory encryption is not enabled, use existing mask */
861		− rdmsrl(MSR_K8_SYSCFG, msr);
862		− if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
	866	+ rdmsrl(MSR_AMD64_SYSCFG, msr);
	867	+ if (!(msr & MSR_AMD64_SYSCFG_MEM_ENCRYPT))
863	868	return;
864	869
865	870	enc_bit = cpuid_ebx(0x8000001f) & 0x3f;
@@ -959,8 +964,7 @@ static __init int svm_hardware_setup(void) · 93 unmodified lines
959	964	kvm_tsc_scaling_ratio_frac_bits = 32;
960	965	}
961	966
962		− if (boot_cpu_has(X86_FEATURE_RDTSCP))
963		− kvm_define_user_return_msr(TSC_AUX_URET_SLOT, MSR_TSC_AUX);
	967	+ tsc_aux_uret_slot = kvm_add_user_return_msr(MSR_TSC_AUX);
964	968
965	969	/* Check for pause filtering support */
966	970	if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
@@ -1006,9 +1010,7 @@ static __init int svm_hardware_setup(void) · 39 unmodified lines
1006	1010	}
1007	1011
1008	1012	if (avic) {
1009		− if (!npt_enabled \|\|
1010		− !boot_cpu_has(X86_FEATURE_AVIC) \|\|
1011		− !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
	1013	+ if (!npt_enabled \|\| !boot_cpu_has(X86_FEATURE_AVIC)) {
1012	1014	avic = false;
1013	1015	} else {
1014	1016	pr_info("AVIC enabled\n");
@@ -1100,7 +1102,9 @@ static u64 svm_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) · 85 unmodified lines
1100	1102	return svm->vmcb->control.tsc_offset;
1101	1103	}
1102	1104
1103		−static void svm_check_invpcid(struct vcpu_svm *svm)
	1105	+/* Evaluate instruction intercepts that depend on guest CPUID features. */
	1106	+static void svm_recalc_instruction_intercepts(struct kvm_vcpu *vcpu,
	1107	+ struct vcpu_svm *svm)
1104	1108	{
1105	1109	/*
1106	1110	* Intercept INVPCID if shadow paging is enabled to sync/free shadow
@@ -1113,6 +1117,13 @@ static void svm_check_invpcid(struct vcpu_svm *svm) · 6 unmodified lines
1113	1117	else
1114	1118	svm_clr_intercept(svm, INTERCEPT_INVPCID);
1115	1119	}
	1120	+
	1121	+ if (kvm_cpu_cap_has(X86_FEATURE_RDTSCP)) {
	1122	+ if (guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
	1123	+ svm_clr_intercept(svm, INTERCEPT_RDTSCP);
	1124	+ else
	1125	+ svm_set_intercept(svm, INTERCEPT_RDTSCP);
	1126	+ }
1116	1127	}
1117	1128
1118	1129	static void init_vmcb(struct kvm_vcpu *vcpu)
@@ -1235,8 +1246,8 @@ static void init_vmcb(struct kvm_vcpu *vcpu) · 116 unmodified lines
1235	1246	svm->current_vmcb->asid_generation = 0;
1236	1247	svm->asid = 0;
1237	1248
1238		− svm->nested.vmcb12_gpa = 0;
1239		− svm->nested.last_vmcb12_gpa = 0;
	1249	+ svm->nested.vmcb12_gpa = INVALID_GPA;
	1250	+ svm->nested.last_vmcb12_gpa = INVALID_GPA;
1240	1251	vcpu->arch.hflags = 0;
1241	1252
1242	1253	if (!kvm_pause_in_guest(vcpu->kvm)) {
@@ -1248,7 +1259,7 @@ static void init_vmcb(struct kvm_vcpu *vcpu) · 5 unmodified lines
1248	1259	svm_clr_intercept(svm, INTERCEPT_PAUSE);
1249	1260	}
1250	1261
1251		− svm_check_invpcid(svm);
	1262	+ svm_recalc_instruction_intercepts(vcpu, svm);
1252	1263
1253	1264	/*
1254	1265	* If the host supports V_SPEC_CTRL then disable the interception
@@ -1424,6 +1435,9 @@ static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu) · 169 unmodified lines
1424	1435	struct vcpu_svm *svm = to_svm(vcpu);
1425	1436	struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
1426	1437
	1438	+ if (sev_es_guest(vcpu->kvm))
	1439	+ sev_es_unmap_ghcb(svm);
	1440	+
1427	1441	if (svm->guest_state_loaded)
1428	1442	return;
1429	1443
@@ -1445,8 +1459,8 @@ static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu) · 15 unmodified lines
1445	1459	}
1446	1460	}
1447	1461
1448		− if (static_cpu_has(X86_FEATURE_RDTSCP))
1449		− kvm_set_user_return_msr(TSC_AUX_URET_SLOT, svm->tsc_aux, -1ull);
	1462	+ if (likely(tsc_aux_uret_slot >= 0))
	1463	+ kvm_set_user_return_msr(tsc_aux_uret_slot, svm->tsc_aux, -1ull);
1450	1464
1451	1465	svm->guest_state_loaded = true;
1452	1466	}
@@ -2655,11 +2669,6 @@ static int svm_get_msr(struct kvm_vcpu vcpu, struct msr_data msr_info) · 1202 unmodified lines
2655	2669	msr_info->data \|= (u64)svm->sysenter_esp_hi << 32;
2656	2670	break;
2657	2671	case MSR_TSC_AUX:
2658		− if (!boot_cpu_has(X86_FEATURE_RDTSCP))
2659		− return 1;
2660		− if (!msr_info->host_initiated &&
2661		− !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
2662		− return 1;
2663	2672	msr_info->data = svm->tsc_aux;
2664	2673	break;
2665	2674	/*
@@ -2876,30 +2885,13 @@ static int svm_set_msr(struct kvm_vcpu vcpu, struct msr_data msr) · 210 unmodified lines
2876	2885	svm->sysenter_esp_hi = guest_cpuid_is_intel(vcpu) ? (data >> 32) : 0;
2877	2886	break;
2878	2887	case MSR_TSC_AUX:
2879		− if (!boot_cpu_has(X86_FEATURE_RDTSCP))
2880		− return 1;
2881		−
2882		− if (!msr->host_initiated &&
2883		− !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
2884		− return 1;
2885		−
2886		− /*
2887		− * Per Intel's SDM, bits 63:32 are reserved, but AMD's APM has
2888		− * incomplete and conflicting architectural behavior. Current
2889		− * AMD CPUs completely ignore bits 63:32, i.e. they aren't
2890		− * reserved and always read as zeros. Emulate AMD CPU behavior
2891		− * to avoid explosions if the vCPU is migrated from an AMD host
2892		− * to an Intel host.
2893		− */
2894		− data = (u32)data;
2895		−
2896	2888	/*
2897	2889	* TSC_AUX is usually changed only during boot and never read
2898	2890	* directly. Intercept TSC_AUX instead of exposing it to the
2899	2891	* guest via direct_access_msrs, and switch it via user return.
2900	2892	*/
2901	2893	preempt_disable();
2902		− r = kvm_set_user_return_msr(TSC_AUX_URET_SLOT, data, -1ull);
	2894	+ r = kvm_set_user_return_msr(tsc_aux_uret_slot, data, -1ull);
2903	2895	preempt_enable();
2904	2896	if (r)
2905	2897	return 1;
@@ -3084,6 +3076,7 @@ static int (const svm_exit_handlers[])(struct kvm_vcpu vcpu) = { · 178 unmodified lines
3084	3076	[SVM_EXIT_STGI] = stgi_interception,
3085	3077	[SVM_EXIT_CLGI] = clgi_interception,
3086	3078	[SVM_EXIT_SKINIT] = skinit_interception,
	3079	+ [SVM_EXIT_RDTSCP] = kvm_handle_invalid_op,
3087	3080	[SVM_EXIT_WBINVD] = kvm_emulate_wbinvd,
3088	3081	[SVM_EXIT_MONITOR] = kvm_emulate_monitor,
3089	3082	[SVM_EXIT_MWAIT] = kvm_emulate_mwait,
@@ -3972,8 +3965,7 @@ static void svm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu) · 882 unmodified lines
3972	3965	svm->nrips_enabled = kvm_cpu_cap_has(X86_FEATURE_NRIPS) &&
3973	3966	guest_cpuid_has(vcpu, X86_FEATURE_NRIPS);
3974	3967
3975		− /* Check again if INVPCID interception if required */
3976		− svm_check_invpcid(svm);
	3968	+ svm_recalc_instruction_intercepts(vcpu, svm);
3977	3969
3978	3970	/* For sev guests, the memory encryption bit is not reserved in CR3. */
3979	3971	if (sev_guest(vcpu->kvm)) {

arch/x86/kvm/svm/svm.h+6−35

@@ -20,6 +20,7 @@ · 19 unmodified lines
20	20	#include <linux/bits.h>
21	21
22	22	#include <asm/svm.h>
	23	+#include <asm/sev-common.h>
23	24
24	25	#define __sme_page_pa(x) __sme_set(page_to_pfn(x) << PAGE_SHIFT)
25	26
@@ -479,7 +480,7 @@ extern struct kvm_x86_nested_ops svm_nested_ops; · 453 unmodified lines
479	480
480	481	#define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL
481	482
482		−extern int avic;
	483	+extern bool avic;
483	484
484	485	static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
485	486	{
@@ -525,40 +526,9 @@ void svm_vcpu_unblocking(struct kvm_vcpu *vcpu); · 39 unmodified lines
525	526
526	527	/* sev.c */
527	528
528		−#define GHCB_VERSION_MAX 1ULL
529		−#define GHCB_VERSION_MIN 1ULL
530		−
531		−#define GHCB_MSR_INFO_POS 0
532		−#define GHCB_MSR_INFO_MASK (BIT_ULL(12) - 1)
533		−
534		−#define GHCB_MSR_SEV_INFO_RESP 0x001
535		−#define GHCB_MSR_SEV_INFO_REQ 0x002
536		−#define GHCB_MSR_VER_MAX_POS 48
537		−#define GHCB_MSR_VER_MAX_MASK 0xffff
538		−#define GHCB_MSR_VER_MIN_POS 32
539		−#define GHCB_MSR_VER_MIN_MASK 0xffff
540		−#define GHCB_MSR_CBIT_POS 24
541		−#define GHCB_MSR_CBIT_MASK 0xff
542		−#define GHCB_MSR_SEV_INFO(_max, _min, _cbit) \
543		− ((((_max) & GHCB_MSR_VER_MAX_MASK) << GHCB_MSR_VER_MAX_POS) \| \
544		− (((_min) & GHCB_MSR_VER_MIN_MASK) << GHCB_MSR_VER_MIN_POS) \| \
545		− (((_cbit) & GHCB_MSR_CBIT_MASK) << GHCB_MSR_CBIT_POS) \| \
546		− GHCB_MSR_SEV_INFO_RESP)
547		−
548		−#define GHCB_MSR_CPUID_REQ 0x004
549		−#define GHCB_MSR_CPUID_RESP 0x005
550		−#define GHCB_MSR_CPUID_FUNC_POS 32
551		−#define GHCB_MSR_CPUID_FUNC_MASK 0xffffffff
552		−#define GHCB_MSR_CPUID_VALUE_POS 32
553		−#define GHCB_MSR_CPUID_VALUE_MASK 0xffffffff
554		−#define GHCB_MSR_CPUID_REG_POS 30
555		−#define GHCB_MSR_CPUID_REG_MASK 0x3
556		−
557		−#define GHCB_MSR_TERM_REQ 0x100
558		−#define GHCB_MSR_TERM_REASON_SET_POS 12
559		−#define GHCB_MSR_TERM_REASON_SET_MASK 0xf
560		−#define GHCB_MSR_TERM_REASON_POS 16
561		−#define GHCB_MSR_TERM_REASON_MASK 0xff
	529	+#define GHCB_VERSION_MAX 1ULL
	530	+#define GHCB_VERSION_MIN 1ULL
	531	+
562	532
563	533	extern unsigned int max_sev_asid;
564	534
@@ -581,6 +551,7 @@ void sev_es_init_vmcb(struct vcpu_svm *svm); · 16 unmodified lines
581	551	void sev_es_create_vcpu(struct vcpu_svm *svm);
582	552	void sev_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector);
583	553	void sev_es_prepare_guest_switch(struct vcpu_svm *svm, unsigned int cpu);
	554	+void sev_es_unmap_ghcb(struct vcpu_svm *svm);
584	555
585	556	/* vmenter.S */
586	557

arch/x86/kvm/trace.h+3−3

@@ -1550,16 +1550,16 @@ TRACE_EVENT(kvm_nested_vmenter_failed, · 1549 unmodified lines
1550	1550	TP_ARGS(msg, err),
1551	1551
1552	1552	TP_STRUCT__entry(
1553		− __field(const char *, msg)
	1553	+ __string(msg, msg)
1554	1554	__field(u32, err)
1555	1555	),
1556	1556
1557	1557	TP_fast_assign(
1558		− __entry->msg = msg;
	1558	+ __assign_str(msg, msg);
1559	1559	__entry->err = err;
1560	1560	),
1561	1561
1562		− TP_printk("%s%s", __entry->msg, !__entry->err ? "" :
	1562	+ TP_printk("%s%s", __get_str(msg), !__entry->err ? "" :
1563	1563	__print_symbolic(__entry->err, VMX_VMENTER_INSTRUCTION_ERRORS))
1564	1564	);
1565	1565

arch/x86/kvm/vmx/capabilities.h+4−2

@@ -90,8 +90,7 @@ static inline bool cpu_has_vmx_preemption_timer(void) · 89 unmodified lines
90	90
91	91	static inline bool cpu_has_vmx_posted_intr(void)
92	92	{
93		− return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
94		− vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
	93	+ return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
95	94	}
96	95
97	96	static inline bool cpu_has_load_ia32_efer(void)
@@ -398,6 +397,9 @@ static inline u64 vmx_supported_debugctl(void) · 300 unmodified lines
398	397	{
399	398	u64 debugctl = 0;
400	399
	400	+ if (boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT))
	401	+ debugctl \|= DEBUGCTLMSR_BUS_LOCK_DETECT;
	402	+
401	403	if (vmx_get_perf_capabilities() & PMU_CAP_LBR_FMT)
402	404	debugctl \|= DEBUGCTLMSR_LBR_MASK;
403	405

arch/x86/kvm/vmx/nested.c+19−10

@@ -3098,15 +3098,8 @@ static bool nested_get_evmcs_page(struct kvm_vcpu *vcpu) · 3097 unmodified lines
3098	3098	nested_vmx_handle_enlightened_vmptrld(vcpu, false);
3099	3099
3100	3100	if (evmptrld_status == EVMPTRLD_VMFAIL \|\|
3101		− evmptrld_status == EVMPTRLD_ERROR) {
3102		− pr_debug_ratelimited("%s: enlightened vmptrld failed\n",
3103		− __func__);
3104		− vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3105		− vcpu->run->internal.suberror =
3106		− KVM_INTERNAL_ERROR_EMULATION;
3107		− vcpu->run->internal.ndata = 0;
	3101	+ evmptrld_status == EVMPTRLD_ERROR)
3108	3102	return false;
3109		− }
3110	3103	}
3111	3104
3112	3105	return true;
@@ -3194,8 +3187,16 @@ static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu) · 81 unmodified lines
3194	3187
3195	3188	static bool vmx_get_nested_state_pages(struct kvm_vcpu *vcpu)
3196	3189	{
3197		− if (!nested_get_evmcs_page(vcpu))
	3190	+ if (!nested_get_evmcs_page(vcpu)) {
	3191	+ pr_debug_ratelimited("%s: enlightened vmptrld failed\n",
	3192	+ __func__);
	3193	+ vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
	3194	+ vcpu->run->internal.suberror =
	3195	+ KVM_INTERNAL_ERROR_EMULATION;
	3196	+ vcpu->run->internal.ndata = 0;
	3197	+
3198	3198	return false;
	3199	+ }
3199	3200
3200	3201	if (is_guest_mode(vcpu) && !nested_get_vmcs12_pages(vcpu))
3201	3202	return false;
@@ -4435,7 +4436,15 @@ void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 vm_exit_reason, · 1233 unmodified lines
4435	4436	/* Similarly, triple faults in L2 should never escape. */
4436	4437	WARN_ON_ONCE(kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu));
4437	4438
4438		− kvm_clear_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu);
	4439	+ if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) {
	4440	+ /*
	4441	+ * KVM_REQ_GET_NESTED_STATE_PAGES is also used to map
	4442	+ * Enlightened VMCS after migration and we still need to
	4443	+ * do that when something is forcing L2->L1 exit prior to
	4444	+ * the first L2 run.
	4445	+ */
	4446	+ (void)nested_get_evmcs_page(vcpu);
	4447	+ }
4439	4448
4440	4449	/* Service the TLB flush request for L2 before switching to L1. */
4441	4450	if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu))

arch/x86/kvm/vmx/posted_intr.c+14−0

@@ -237,6 +237,20 @@ bool pi_has_pending_interrupt(struct kvm_vcpu *vcpu) · 236 unmodified lines
237	237	}
238	238
239	239
	240	+/*
	241	+ * Bail out of the block loop if the VM has an assigned
	242	+ * device, but the blocking vCPU didn't reconfigure the
	243	+ * PI.NV to the wakeup vector, i.e. the assigned device
	244	+ * came along after the initial check in pi_pre_block().
	245	+ */
	246	+void vmx_pi_start_assignment(struct kvm *kvm)
	247	+{
	248	+ if (!irq_remapping_cap(IRQ_POSTING_CAP))
	249	+ return;
	250	+
	251	+ kvm_make_all_cpus_request(kvm, KVM_REQ_UNBLOCK);
	252	+}
	253	+
240	254	/*
241	255	* pi_update_irte - set IRTE for Posted-Interrupts
242	256	*

arch/x86/kvm/vmx/posted_intr.h+1−0

@@ -95,5 +95,6 @@ void __init pi_init_cpu(int cpu); · 94 unmodified lines
95	95	bool pi_has_pending_interrupt(struct kvm_vcpu *vcpu);
96	96	int pi_update_irte(struct kvm *kvm, unsigned int host_irq, uint32_t guest_irq,
97	97	bool set);
	98	+void vmx_pi_start_assignment(struct kvm *kvm);
98	99
99	100	#endif /* __KVM_X86_VMX_POSTED_INTR_H */

arch/x86/kvm/vmx/vmx.c+114−113

@@ -455,21 +455,6 @@ static inline void vmx_segment_cache_clear(struct vcpu_vmx *vmx) · 454 unmodified lines
455	455
456	456	static unsigned long host_idt_base;
457	457
458		−/*
459		− * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm
460		− * will emulate SYSCALL in legacy mode if the vendor string in guest
461		− * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To
462		− * support this emulation, IA32_STAR must always be included in
463		− * vmx_uret_msrs_list[], even in i386 builds.
464		− */
465		−static const u32 vmx_uret_msrs_list[] = {
466		−#ifdef CONFIG_X86_64
467		− MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
468		−#endif
469		− MSR_EFER, MSR_TSC_AUX, MSR_STAR,
470		− MSR_IA32_TSX_CTRL,
471		−};
472		−
473	458	#if IS_ENABLED(CONFIG_HYPERV)
474	459	static bool __read_mostly enlightened_vmcs = true;
475	460	module_param(enlightened_vmcs, bool, 0444);
@@ -697,21 +682,11 @@ static bool is_valid_passthrough_msr(u32 msr) · 221 unmodified lines
697	682	return r;
698	683	}
699	684
700		−static inline int __vmx_find_uret_msr(struct vcpu_vmx *vmx, u32 msr)
701		−{
702		− int i;
703		−
704		− for (i = 0; i < vmx->nr_uret_msrs; ++i)
705		− if (vmx_uret_msrs_list[vmx->guest_uret_msrs[i].slot] == msr)
706		− return i;
707		− return -1;
708		−}
709		−
710	685	struct vmx_uret_msr vmx_find_uret_msr(struct vcpu_vmx vmx, u32 msr)
711	686	{
712	687	int i;
713	688
714		− i = __vmx_find_uret_msr(vmx, msr);
	689	+ i = kvm_find_user_return_msr(msr);
715	690	if (i >= 0)
716	691	return &vmx->guest_uret_msrs[i];
717	692	return NULL;
@@ -720,13 +695,14 @@ struct vmx_uret_msr vmx_find_uret_msr(struct vcpu_vmx vmx, u32 msr) · 2 unmodified lines
720	695	static int vmx_set_guest_uret_msr(struct vcpu_vmx *vmx,
721	696	struct vmx_uret_msr *msr, u64 data)
722	697	{
	698	+ unsigned int slot = msr - vmx->guest_uret_msrs;
723	699	int ret = 0;
724	700
725	701	u64 old_msr_data = msr->data;
726	702	msr->data = data;
727		− if (msr - vmx->guest_uret_msrs < vmx->nr_active_uret_msrs) {
	703	+ if (msr->load_into_hardware) {
728	704	preempt_disable();
729		− ret = kvm_set_user_return_msr(msr->slot, msr->data, msr->mask);
	705	+ ret = kvm_set_user_return_msr(slot, msr->data, msr->mask);
730	706	preempt_enable();
731	707	if (ret)
732	708	msr->data = old_msr_data;
@@ -1078,7 +1054,7 @@ static bool update_transition_efer(struct vcpu_vmx *vmx) · 345 unmodified lines
1078	1054	return false;
1079	1055	}
1080	1056
1081		− i = __vmx_find_uret_msr(vmx, MSR_EFER);
	1057	+ i = kvm_find_user_return_msr(MSR_EFER);
1082	1058	if (i < 0)
1083	1059	return false;
1084	1060
@@ -1240,11 +1216,14 @@ void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu) · 155 unmodified lines
1240	1216	*/
1241	1217	if (!vmx->guest_uret_msrs_loaded) {
1242	1218	vmx->guest_uret_msrs_loaded = true;
1243		− for (i = 0; i < vmx->nr_active_uret_msrs; ++i)
1244		− kvm_set_user_return_msr(vmx->guest_uret_msrs[i].slot,
	1219	+ for (i = 0; i < kvm_nr_uret_msrs; ++i) {
	1220	+ if (!vmx->guest_uret_msrs[i].load_into_hardware)
	1221	+ continue;
	1222	+
	1223	+ kvm_set_user_return_msr(i,
1245	1224	vmx->guest_uret_msrs[i].data,
1246	1225	vmx->guest_uret_msrs[i].mask);
1247		−
	1226	+ }
1248	1227	}
1249	1228
1250	1229	if (vmx->nested.need_vmcs12_to_shadow_sync)
@@ -1751,19 +1730,16 @@ static void vmx_queue_exception(struct kvm_vcpu *vcpu) · 500 unmodified lines
1751	1730	vmx_clear_hlt(vcpu);
1752	1731	}
1753	1732
1754		−static void vmx_setup_uret_msr(struct vcpu_vmx *vmx, unsigned int msr)
	1733	+static void vmx_setup_uret_msr(struct vcpu_vmx *vmx, unsigned int msr,
	1734	+ bool load_into_hardware)
1755	1735	{
1756		− struct vmx_uret_msr tmp;
1757		− int from, to;
	1736	+ struct vmx_uret_msr *uret_msr;
1758	1737
1759		− from = __vmx_find_uret_msr(vmx, msr);
1760		− if (from < 0)
	1738	+ uret_msr = vmx_find_uret_msr(vmx, msr);
	1739	+ if (!uret_msr)
1761	1740	return;
1762		− to = vmx->nr_active_uret_msrs++;
1763	1741
1764		− tmp = vmx->guest_uret_msrs[to];
1765		− vmx->guest_uret_msrs[to] = vmx->guest_uret_msrs[from];
1766		− vmx->guest_uret_msrs[from] = tmp;
	1742	+ uret_msr->load_into_hardware = load_into_hardware;
1767	1743	}
1768	1744
1769	1745	/*
@@ -1773,29 +1749,42 @@ static void vmx_setup_uret_msr(struct vcpu_vmx *vmx, unsigned int msr) · 3 unmodified lines
1773	1749	*/
1774	1750	static void setup_msrs(struct vcpu_vmx *vmx)
1775	1751	{
1776		− vmx->guest_uret_msrs_loaded = false;
1777		− vmx->nr_active_uret_msrs = 0;
1778	1752	#ifdef CONFIG_X86_64
	1753	+ bool load_syscall_msrs;
	1754	+
1779	1755	/*
1780	1756	* The SYSCALL MSRs are only needed on long mode guests, and only
1781	1757	* when EFER.SCE is set.
1782	1758	*/
1783		− if (is_long_mode(&vmx->vcpu) && (vmx->vcpu.arch.efer & EFER_SCE)) {
1784		− vmx_setup_uret_msr(vmx, MSR_STAR);
1785		− vmx_setup_uret_msr(vmx, MSR_LSTAR);
1786		− vmx_setup_uret_msr(vmx, MSR_SYSCALL_MASK);
1787		− }
	1759	+ load_syscall_msrs = is_long_mode(&vmx->vcpu) &&
	1760	+ (vmx->vcpu.arch.efer & EFER_SCE);
	1761	+
	1762	+ vmx_setup_uret_msr(vmx, MSR_STAR, load_syscall_msrs);
	1763	+ vmx_setup_uret_msr(vmx, MSR_LSTAR, load_syscall_msrs);
	1764	+ vmx_setup_uret_msr(vmx, MSR_SYSCALL_MASK, load_syscall_msrs);
1788	1765	#endif
1789		− if (update_transition_efer(vmx))
1790		− vmx_setup_uret_msr(vmx, MSR_EFER);
	1766	+ vmx_setup_uret_msr(vmx, MSR_EFER, update_transition_efer(vmx));
1791	1767
1792		− if (guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
1793		− vmx_setup_uret_msr(vmx, MSR_TSC_AUX);
	1768	+ vmx_setup_uret_msr(vmx, MSR_TSC_AUX,
	1769	+ guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP) \|\|
	1770	+ guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDPID));
1794	1771
1795		− vmx_setup_uret_msr(vmx, MSR_IA32_TSX_CTRL);
	1772	+ /*
	1773	+ * hle=0, rtm=0, tsx_ctrl=1 can be found with some combinations of new
	1774	+ * kernel and old userspace. If those guests run on a tsx=off host, do
	1775	+ * allow guests to use TSX_CTRL, but don't change the value in hardware
	1776	+ * so that TSX remains always disabled.
	1777	+ */
	1778	+ vmx_setup_uret_msr(vmx, MSR_IA32_TSX_CTRL, boot_cpu_has(X86_FEATURE_RTM));
1796	1779
1797	1780	if (cpu_has_vmx_msr_bitmap())
1798	1781	vmx_update_msr_bitmap(&vmx->vcpu);
	1782	+
	1783	+ /*
	1784	+ * The set of MSRs to load may have changed, reload MSRs before the
	1785	+ * next VM-Enter.
	1786	+ */
	1787	+ vmx->guest_uret_msrs_loaded = false;
1799	1788	}
1800	1789
1801	1790	static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
@@ -1993,11 +1982,6 @@ static int vmx_get_msr(struct kvm_vcpu vcpu, struct msr_data msr_info) · 191 unmodified lines
1993	1982	else
1994	1983	msr_info->data = vmx->pt_desc.guest.addr_a[index / 2];
1995	1984	break;
1996		− case MSR_TSC_AUX:
1997		− if (!msr_info->host_initiated &&
1998		− !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
1999		− return 1;
2000		− goto find_uret_msr;
2001	1985	case MSR_IA32_DEBUGCTLMSR:
2002	1986	msr_info->data = vmcs_read64(GUEST_IA32_DEBUGCTL);
2003	1987	break;
@@ -2031,6 +2015,9 @@ static u64 vcpu_supported_debugctl(struct kvm_vcpu *vcpu) · 27 unmodified lines
2031	2015	if (!intel_pmu_lbr_is_enabled(vcpu))
2032	2016	debugctl &= ~DEBUGCTLMSR_LBR_MASK;
2033	2017
	2018	+ if (!guest_cpuid_has(vcpu, X86_FEATURE_BUS_LOCK_DETECT))
	2019	+ debugctl &= ~DEBUGCTLMSR_BUS_LOCK_DETECT;
	2020	+
2034	2021	return debugctl;
2035	2022	}
2036	2023
@@ -2313,14 +2300,6 @@ static int vmx_set_msr(struct kvm_vcpu vcpu, struct msr_data msr_info) · 276 unmodified lines
2313	2300	else
2314	2301	vmx->pt_desc.guest.addr_a[index / 2] = data;
2315	2302	break;
2316		− case MSR_TSC_AUX:
2317		− if (!msr_info->host_initiated &&
2318		− !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
2319		− return 1;
2320		− /* Check reserved bit, higher 32 bits should be zero */
2321		− if ((data >> 32) != 0)
2322		− return 1;
2323		− goto find_uret_msr;
2324	2303	case MSR_IA32_PERF_CAPABILITIES:
2325	2304	if (data && !vcpu_to_pmu(vcpu)->version)
2326	2305	return 1;
@@ -4369,7 +4348,23 @@ static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx) · 2042 unmodified lines
4369	4348	xsaves_enabled, false);
4370	4349	}
4371	4350
4372		− vmx_adjust_sec_exec_feature(vmx, &exec_control, rdtscp, RDTSCP);
	4351	+ /*
	4352	+ * RDPID is also gated by ENABLE_RDTSCP, turn on the control if either
	4353	+ * feature is exposed to the guest. This creates a virtualization hole
	4354	+ * if both are supported in hardware but only one is exposed to the
	4355	+ * guest, but letting the guest execute RDTSCP or RDPID when either one
	4356	+ * is advertised is preferable to emulating the advertised instruction
	4357	+ * in KVM on #UD, and obviously better than incorrectly injecting #UD.
	4358	+ */
	4359	+ if (cpu_has_vmx_rdtscp()) {
	4360	+ bool rdpid_or_rdtscp_enabled =
	4361	+ guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) \|\|
	4362	+ guest_cpuid_has(vcpu, X86_FEATURE_RDPID);
	4363	+
	4364	+ vmx_adjust_secondary_exec_control(vmx, &exec_control,
	4365	+ SECONDARY_EXEC_ENABLE_RDTSCP,
	4366	+ rdpid_or_rdtscp_enabled, false);
	4367	+ }
4373	4368	vmx_adjust_sec_exec_feature(vmx, &exec_control, invpcid, INVPCID);
4374	4369
4375	4370	vmx_adjust_sec_exec_exiting(vmx, &exec_control, rdrand, RDRAND);
@@ -4848,7 +4843,7 @@ static int handle_exception_nmi(struct kvm_vcpu *vcpu) · 472 unmodified lines
4848	4843	struct vcpu_vmx *vmx = to_vmx(vcpu);
4849	4844	struct kvm_run *kvm_run = vcpu->run;
4850	4845	u32 intr_info, ex_no, error_code;
4851		− unsigned long cr2, rip, dr6;
	4846	+ unsigned long cr2, dr6;
4852	4847	u32 vect_info;
4853	4848
4854	4849	vect_info = vmx->idt_vectoring_info;
@@ -4938,8 +4933,7 @@ static int handle_exception_nmi(struct kvm_vcpu *vcpu) · 83 unmodified lines
4938	4933	vmx->vcpu.arch.event_exit_inst_len =
4939	4934	vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4940	4935	kvm_run->exit_reason = KVM_EXIT_DEBUG;
4941		− rip = kvm_rip_read(vcpu);
4942		− kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
	4936	+ kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu);
4943	4937	kvm_run->debug.arch.exception = ex_no;
4944	4938	break;
4945	4939	case AC_VECTOR:
@@ -6253,6 +6247,7 @@ void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu) · 1307 unmodified lines
6253	6247	switch (kvm_get_apic_mode(vcpu)) {
6254	6248	case LAPIC_MODE_INVALID:
6255	6249	WARN_ONCE(true, "Invalid local APIC state");
	6250	+ break;
6256	6251	case LAPIC_MODE_DISABLED:
6257	6252	break;
6258	6253	case LAPIC_MODE_XAPIC:
@@ -6855,6 +6850,7 @@ static void vmx_free_vcpu(struct kvm_vcpu *vcpu) · 596 unmodified lines
6855	6850
6856	6851	static int vmx_create_vcpu(struct kvm_vcpu *vcpu)
6857	6852	{
	6853	+ struct vmx_uret_msr *tsx_ctrl;
6858	6854	struct vcpu_vmx *vmx;
6859	6855	int i, cpu, err;
6860	6856
@@ -6877,43 +6873,19 @@ static int vmx_create_vcpu(struct kvm_vcpu *vcpu) · 16 unmodified lines
6877	6873	goto free_vpid;
6878	6874	}
6879	6875
6880		− BUILD_BUG_ON(ARRAY_SIZE(vmx_uret_msrs_list) != MAX_NR_USER_RETURN_MSRS);
6881		−
6882		− for (i = 0; i < ARRAY_SIZE(vmx_uret_msrs_list); ++i) {
6883		− u32 index = vmx_uret_msrs_list[i];
6884		− u32 data_low, data_high;
6885		− int j = vmx->nr_uret_msrs;
6886		−
6887		− if (rdmsr_safe(index, &data_low, &data_high) < 0)
6888		− continue;
6889		− if (wrmsr_safe(index, data_low, data_high) < 0)
6890		− continue;
6891		−
6892		− vmx->guest_uret_msrs[j].slot = i;
6893		− vmx->guest_uret_msrs[j].data = 0;
6894		− switch (index) {
6895		− case MSR_IA32_TSX_CTRL:
6896		− /*
6897		− * TSX_CTRL_CPUID_CLEAR is handled in the CPUID
6898		− * interception. Keep the host value unchanged to avoid
6899		− * changing CPUID bits under the host kernel's feet.
6900		− *
6901		− * hle=0, rtm=0, tsx_ctrl=1 can be found with some
6902		− * combinations of new kernel and old userspace. If
6903		− * those guests run on a tsx=off host, do allow guests
6904		− * to use TSX_CTRL, but do not change the value on the
6905		− * host so that TSX remains always disabled.
6906		− */
6907		− if (boot_cpu_has(X86_FEATURE_RTM))
6908		− vmx->guest_uret_msrs[j].mask = ~(u64)TSX_CTRL_CPUID_CLEAR;
6909		− else
6910		− vmx->guest_uret_msrs[j].mask = 0;
6911		− break;
6912		− default:
6913		− vmx->guest_uret_msrs[j].mask = -1ull;
6914		− break;
6915		− }
6916		− ++vmx->nr_uret_msrs;
	6876	+ for (i = 0; i < kvm_nr_uret_msrs; ++i) {
	6877	+ vmx->guest_uret_msrs[i].data = 0;
	6878	+ vmx->guest_uret_msrs[i].mask = -1ull;
	6879	+ }
	6880	+ if (boot_cpu_has(X86_FEATURE_RTM)) {
	6881	+ /*
	6882	+ * TSX_CTRL_CPUID_CLEAR is handled in the CPUID interception.
	6883	+ * Keep the host value unchanged to avoid changing CPUID bits
	6884	+ * under the host kernel's feet.
	6885	+ */
	6886	+ tsx_ctrl = vmx_find_uret_msr(vmx, MSR_IA32_TSX_CTRL);
	6887	+ if (tsx_ctrl)
	6888	+ vmx->guest_uret_msrs[i].mask = ~(u64)TSX_CTRL_CPUID_CLEAR;
6917	6889	}
6918	6890
6919	6891	err = alloc_loaded_vmcs(&vmx->vmcs01);
@@ -7344,9 +7316,11 @@ static __init void vmx_set_cpu_caps(void) · 424 unmodified lines
7344	7316	if (!cpu_has_vmx_xsaves())
7345	7317	kvm_cpu_cap_clear(X86_FEATURE_XSAVES);
7346	7318
7347		− /* CPUID 0x80000001 */
7348		− if (!cpu_has_vmx_rdtscp())
	7319	+ /* CPUID 0x80000001 and 0x7 (RDPID) */
	7320	+ if (!cpu_has_vmx_rdtscp()) {
7349	7321	kvm_cpu_cap_clear(X86_FEATURE_RDTSCP);
	7322	+ kvm_cpu_cap_clear(X86_FEATURE_RDPID);
	7323	+ }
7350	7324
7351	7325	if (cpu_has_vmx_waitpkg())
7352	7326	kvm_cpu_cap_check_and_set(X86_FEATURE_WAITPKG);
@@ -7402,8 +7376,9 @@ static int vmx_check_intercept(struct kvm_vcpu *vcpu, · 49 unmodified lines
7402	7376	/*
7403	7377	* RDPID causes #UD if disabled through secondary execution controls.
7404	7378	* Because it is marked as EmulateOnUD, we need to intercept it here.
	7379	+ * Note, RDPID is hidden behind ENABLE_RDTSCP.
7405	7380	*/
7406		− case x86_intercept_rdtscp:
	7381	+ case x86_intercept_rdpid:
7407	7382	if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_RDTSCP)) {
7408	7383	exception->vector = UD_VECTOR;
7409	7384	exception->error_code_valid = false;
@@ -7746,6 +7721,7 @@ static struct kvm_x86_ops vmx_x86_ops __initdata = { · 336 unmodified lines
7746	7721	.nested_ops = &vmx_nested_ops,
7747	7722
7748	7723	.update_pi_irte = pi_update_irte,
	7724	+ .start_assignment = vmx_pi_start_assignment,
7749	7725
7750	7726	#ifdef CONFIG_X86_64
7751	7727	.set_hv_timer = vmx_set_hv_timer,
@@ -7769,17 +7745,42 @@ static struct kvm_x86_ops vmx_x86_ops __initdata = { · 17 unmodified lines
7769	7745	.vcpu_deliver_sipi_vector = kvm_vcpu_deliver_sipi_vector,
7770	7746	};
7771	7747
	7748	+static __init void vmx_setup_user_return_msrs(void)
	7749	+{
	7750	+
	7751	+ /*
	7752	+ * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm
	7753	+ * will emulate SYSCALL in legacy mode if the vendor string in guest
	7754	+ * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To
	7755	+ * support this emulation, MSR_STAR is included in the list for i386,
	7756	+ * but is never loaded into hardware. MSR_CSTAR is also never loaded
	7757	+ * into hardware and is here purely for emulation purposes.
	7758	+ */
	7759	+ const u32 vmx_uret_msrs_list[] = {
	7760	+ #ifdef CONFIG_X86_64
	7761	+ MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
	7762	+ #endif
	7763	+ MSR_EFER, MSR_TSC_AUX, MSR_STAR,
	7764	+ MSR_IA32_TSX_CTRL,
	7765	+ };
	7766	+ int i;
	7767	+
	7768	+ BUILD_BUG_ON(ARRAY_SIZE(vmx_uret_msrs_list) != MAX_NR_USER_RETURN_MSRS);
	7769	+
	7770	+ for (i = 0; i < ARRAY_SIZE(vmx_uret_msrs_list); ++i)
	7771	+ kvm_add_user_return_msr(vmx_uret_msrs_list[i]);
	7772	+}
	7773	+
7772	7774	static __init int hardware_setup(void)
7773	7775	{
7774	7776	unsigned long host_bndcfgs;
7775	7777	struct desc_ptr dt;
7776		− int r, i, ept_lpage_level;
	7778	+ int r, ept_lpage_level;
7777	7779
7778	7780	store_idt(&dt);
7779	7781	host_idt_base = dt.address;
7780	7782
7781		− for (i = 0; i < ARRAY_SIZE(vmx_uret_msrs_list); ++i)
7782		− kvm_define_user_return_msr(i, vmx_uret_msrs_list[i]);
	7783	+ vmx_setup_user_return_msrs();
7783	7784
7784	7785	if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0)
7785	7786	return -EIO;

arch/x86/kvm/vmx/vmx.h+10−2

@@ -36,7 +36,7 @@ struct vmx_msrs { · 35 unmodified lines
36	36	};
37	37
38	38	struct vmx_uret_msr {
39		− unsigned int slot; /* The MSR's slot in kvm_user_return_msrs. */
	39	+ bool load_into_hardware;
40	40	u64 data;
41	41	u64 mask;
42	42	};
@@ -245,8 +245,16 @@ struct vcpu_vmx { · 202 unmodified lines
245	245	u32 idt_vectoring_info;
246	246	ulong rflags;
247	247
	248	+ /*
	249	+ * User return MSRs are always emulated when enabled in the guest, but
	250	+ * only loaded into hardware when necessary, e.g. SYSCALL #UDs outside
	251	+ * of 64-bit mode or if EFER.SCE=1, thus the SYSCALL MSRs don't need to
	252	+ * be loaded into hardware if those conditions aren't met.
	253	+ * nr_active_uret_msrs tracks the number of MSRs that need to be loaded
	254	+ * into hardware when running the guest. guest_uret_msrs[] is resorted
	255	+ * whenever the number of "active" uret MSRs is modified.
	256	+ */
248	257	struct vmx_uret_msr guest_uret_msrs[MAX_NR_USER_RETURN_MSRS];
249		− int nr_uret_msrs;
250	258	int nr_active_uret_msrs;
251	259	bool guest_uret_msrs_loaded;
252	260	#ifdef CONFIG_X86_64

arch/x86/kvm/x86.c+150−57

@@ -184,11 +184,6 @@ module_param(pi_inject_timer, bint, S_IRUGO \| S_IWUSR); · 183 unmodified lines
184	184	*/
185	185	#define KVM_MAX_NR_USER_RETURN_MSRS 16
186	186
187		−struct kvm_user_return_msrs_global {
188		− int nr;
189		− u32 msrs[KVM_MAX_NR_USER_RETURN_MSRS];
190		−};
191		−
192	187	struct kvm_user_return_msrs {
193	188	struct user_return_notifier urn;
194	189	bool registered;
@@ -198,7 +193,9 @@ struct kvm_user_return_msrs { · 3 unmodified lines
198	193	} values[KVM_MAX_NR_USER_RETURN_MSRS];
199	194	};
200	195
201		−static struct kvm_user_return_msrs_global __read_mostly user_return_msrs_global;
	196	+u32 __read_mostly kvm_nr_uret_msrs;
	197	+EXPORT_SYMBOL_GPL(kvm_nr_uret_msrs);
	198	+static u32 __read_mostly kvm_uret_msrs_list[KVM_MAX_NR_USER_RETURN_MSRS];
202	199	static struct kvm_user_return_msrs __percpu *user_return_msrs;
203	200
204	201	#define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP \| XFEATURE_MASK_SSE \
@@ -330,23 +327,53 @@ static void kvm_on_user_return(struct user_return_notifier *urn) · 125 unmodified lines
330	327	user_return_notifier_unregister(urn);
331	328	}
332	329	local_irq_restore(flags);
333		− for (slot = 0; slot < user_return_msrs_global.nr; ++slot) {
	330	+ for (slot = 0; slot < kvm_nr_uret_msrs; ++slot) {
334	331	values = &msrs->values[slot];
335	332	if (values->host != values->curr) {
336		− wrmsrl(user_return_msrs_global.msrs[slot], values->host);
	333	+ wrmsrl(kvm_uret_msrs_list[slot], values->host);
337	334	values->curr = values->host;
338	335	}
339	336	}
340	337	}
341	338
342		−void kvm_define_user_return_msr(unsigned slot, u32 msr)
	339	+static int kvm_probe_user_return_msr(u32 msr)
	340	+{
	341	+ u64 val;
	342	+ int ret;
	343	+
	344	+ preempt_disable();
	345	+ ret = rdmsrl_safe(msr, &val);
	346	+ if (ret)
	347	+ goto out;
	348	+ ret = wrmsrl_safe(msr, val);
	349	+out:
	350	+ preempt_enable();
	351	+ return ret;
	352	+}
	353	+
	354	+int kvm_add_user_return_msr(u32 msr)
343	355	{
344		− BUG_ON(slot >= KVM_MAX_NR_USER_RETURN_MSRS);
345		− user_return_msrs_global.msrs[slot] = msr;
346		− if (slot >= user_return_msrs_global.nr)
347		− user_return_msrs_global.nr = slot + 1;
	356	+ BUG_ON(kvm_nr_uret_msrs >= KVM_MAX_NR_USER_RETURN_MSRS);
	357	+
	358	+ if (kvm_probe_user_return_msr(msr))
	359	+ return -1;
	360	+
	361	+ kvm_uret_msrs_list[kvm_nr_uret_msrs] = msr;
	362	+ return kvm_nr_uret_msrs++;
	363	+}
	364	+EXPORT_SYMBOL_GPL(kvm_add_user_return_msr);
	365	+
	366	+int kvm_find_user_return_msr(u32 msr)
	367	+{
	368	+ int i;
	369	+
	370	+ for (i = 0; i < kvm_nr_uret_msrs; ++i) {
	371	+ if (kvm_uret_msrs_list[i] == msr)
	372	+ return i;
	373	+ }
	374	+ return -1;
348	375	}
349		−EXPORT_SYMBOL_GPL(kvm_define_user_return_msr);
	376	+EXPORT_SYMBOL_GPL(kvm_find_user_return_msr);
350	377
351	378	static void kvm_user_return_msr_cpu_online(void)
352	379	{
@@ -355,8 +382,8 @@ static void kvm_user_return_msr_cpu_online(void) · 2 unmodified lines
355	382	u64 value;
356	383	int i;
357	384
358		− for (i = 0; i < user_return_msrs_global.nr; ++i) {
359		− rdmsrl_safe(user_return_msrs_global.msrs[i], &value);
	385	+ for (i = 0; i < kvm_nr_uret_msrs; ++i) {
	386	+ rdmsrl_safe(kvm_uret_msrs_list[i], &value);
360	387	msrs->values[i].host = value;
361	388	msrs->values[i].curr = value;
362	389	}
@@ -371,7 +398,7 @@ int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask) · 8 unmodified lines
371	398	value = (value & mask) \| (msrs->values[slot].host & ~mask);
372	399	if (value == msrs->values[slot].curr)
373	400	return 0;
374		− err = wrmsrl_safe(user_return_msrs_global.msrs[slot], value);
	401	+ err = wrmsrl_safe(kvm_uret_msrs_list[slot], value);
375	402	if (err)
376	403	return 1;
377	404
@@ -1149,6 +1176,9 @@ static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) · 771 unmodified lines
1149	1176
1150	1177	if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1151	1178	fixed \|= DR6_RTM;
	1179	+
	1180	+ if (!guest_cpuid_has(vcpu, X86_FEATURE_BUS_LOCK_DETECT))
	1181	+ fixed \|= DR6_BUS_LOCK;
1152	1182	return fixed;
1153	1183	}
1154	1184
@@ -1615,6 +1645,30 @@ static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data, · 460 unmodified lines
1615	1645	* invokes 64-bit SYSENTER.
1616	1646	*/
1617	1647	data = get_canonical(data, vcpu_virt_addr_bits(vcpu));
	1648	+ break;
	1649	+ case MSR_TSC_AUX:
	1650	+ if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX))
	1651	+ return 1;
	1652	+
	1653	+ if (!host_initiated &&
	1654	+ !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) &&
	1655	+ !guest_cpuid_has(vcpu, X86_FEATURE_RDPID))
	1656	+ return 1;
	1657	+
	1658	+ /*
	1659	+ * Per Intel's SDM, bits 63:32 are reserved, but AMD's APM has
	1660	+ * incomplete and conflicting architectural behavior. Current
	1661	+ * AMD CPUs completely ignore bits 63:32, i.e. they aren't
	1662	+ * reserved and always read as zeros. Enforce Intel's reserved
	1663	+ * bits check if and only if the guest CPU is Intel, and clear
	1664	+ * the bits in all other cases. This ensures cross-vendor
	1665	+ * migration will provide consistent behavior for the guest.
	1666	+ */
	1667	+ if (guest_cpuid_is_intel(vcpu) && (data >> 32) != 0)
	1668	+ return 1;
	1669	+
	1670	+ data = (u32)data;
	1671	+ break;
1618	1672	}
1619	1673
1620	1674	msr.data = data;
@@ -1651,6 +1705,18 @@ int __kvm_get_msr(struct kvm_vcpu vcpu, u32 index, u64 data, · 30 unmodified lines
1651	1705	if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ))
1652	1706	return KVM_MSR_RET_FILTERED;
1653	1707
	1708	+ switch (index) {
	1709	+ case MSR_TSC_AUX:
	1710	+ if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX))
	1711	+ return 1;
	1712	+
	1713	+ if (!host_initiated &&
	1714	+ !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) &&
	1715	+ !guest_cpuid_has(vcpu, X86_FEATURE_RDPID))
	1716	+ return 1;
	1717	+ break;
	1718	+ }
	1719	+
1654	1720	msr.index = index;
1655	1721	msr.host_initiated = host_initiated;
1656	1722
@@ -3006,6 +3072,19 @@ static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu) · 1349 unmodified lines
3006	3072	static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu)
3007	3073	{
3008	3074	++vcpu->stat.tlb_flush;
	3075	+
	3076	+ if (!tdp_enabled) {
	3077	+ /*
	3078	+ * A TLB flush on behalf of the guest is equivalent to
	3079	+ * INVPCID(all), toggling CR4.PGE, etc., which requires
	3080	+ * a forced sync of the shadow page tables. Unload the
	3081	+ * entire MMU here and the subsequent load will sync the
	3082	+ * shadow page tables, and also flush the TLB.
	3083	+ */
	3084	+ kvm_mmu_unload(vcpu);
	3085	+ return;
	3086	+ }
	3087	+
3009	3088	static_call(kvm_x86_tlb_flush_guest)(vcpu);
3010	3089	}
3011	3090
@@ -3035,10 +3114,14 @@ static void record_steal_time(struct kvm_vcpu *vcpu) · 23 unmodified lines
3035	3114	* expensive IPIs.
3036	3115	*/
3037	3116	if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) {
	3117	+ u8 st_preempted = xchg(&st->preempted, 0);
	3118	+
3038	3119	trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
3039		− st->preempted & KVM_VCPU_FLUSH_TLB);
3040		− if (xchg(&st->preempted, 0) & KVM_VCPU_FLUSH_TLB)
	3120	+ st_preempted & KVM_VCPU_FLUSH_TLB);
	3121	+ if (st_preempted & KVM_VCPU_FLUSH_TLB)
3041	3122	kvm_vcpu_flush_tlb_guest(vcpu);
	3123	+ } else {
	3124	+ st->preempted = 0;
3042	3125	}
3043	3126
3044	3127	vcpu->arch.st.preempted = 0;
@@ -3402,7 +3485,7 @@ int kvm_get_msr_common(struct kvm_vcpu vcpu, struct msr_data msr_info) · 357 unmodified lines
3402	3485	case MSR_IA32_LASTBRANCHTOIP:
3403	3486	case MSR_IA32_LASTINTFROMIP:
3404	3487	case MSR_IA32_LASTINTTOIP:
3405		− case MSR_K8_SYSCFG:
	3488	+ case MSR_AMD64_SYSCFG:
3406	3489	case MSR_K8_TSEG_ADDR:
3407	3490	case MSR_K8_TSEG_MASK:
3408	3491	case MSR_VM_HSAVE_PA:
@@ -5468,14 +5551,18 @@ static void kvm_free_msr_filter(struct kvm_x86_msr_filter *msr_filter) · 2059 unmodified lines
5468	5551	static int kvm_add_msr_filter(struct kvm_x86_msr_filter *msr_filter,
5469	5552	struct kvm_msr_filter_range *user_range)
5470	5553	{
5471		− struct msr_bitmap_range range;
5472	5554	unsigned long *bitmap = NULL;
5473	5555	size_t bitmap_size;
5474		− int r;
5475	5556
5476	5557	if (!user_range->nmsrs)
5477	5558	return 0;
5478	5559
	5560	+ if (user_range->flags & ~(KVM_MSR_FILTER_READ \| KVM_MSR_FILTER_WRITE))
	5561	+ return -EINVAL;
	5562	+
	5563	+ if (!user_range->flags)
	5564	+ return -EINVAL;
	5565	+
5479	5566	bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long);
5480	5567	if (!bitmap_size \|\| bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE)
5481	5568	return -EINVAL;
@@ -5484,31 +5571,15 @@ static int kvm_add_msr_filter(struct kvm_x86_msr_filter *msr_filter, · 2 unmodified lines
5484	5571	if (IS_ERR(bitmap))
5485	5572	return PTR_ERR(bitmap);
5486	5573
5487		− range = (struct msr_bitmap_range) {
	5574	+ msr_filter->ranges[msr_filter->count] = (struct msr_bitmap_range) {
5488	5575	.flags = user_range->flags,
5489	5576	.base = user_range->base,
5490	5577	.nmsrs = user_range->nmsrs,
5491	5578	.bitmap = bitmap,
5492	5579	};
5493	5580
5494		− if (range.flags & ~(KVM_MSR_FILTER_READ \| KVM_MSR_FILTER_WRITE)) {
5495		− r = -EINVAL;
5496		− goto err;
5497		− }
5498		−
5499		− if (!range.flags) {
5500		− r = -EINVAL;
5501		− goto err;
5502		− }
5503		−
5504		− /* Everything ok, add this range identifier. */
5505		− msr_filter->ranges[msr_filter->count] = range;
5506	5581	msr_filter->count++;
5507		−
5508	5582	return 0;
5509		−err:
5510		− kfree(bitmap);
5511		− return r;
5512	5583	}
5513	5584
5514	5585	static int kvm_vm_ioctl_set_msr_filter(struct kvm kvm, void __user argp)
@@ -5937,7 +6008,8 @@ static void kvm_init_msr_list(void) · 422 unmodified lines
5937	6008	continue;
5938	6009	break;
5939	6010	case MSR_TSC_AUX:
5940		− if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP))
	6011	+ if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP) &&
	6012	+ !kvm_cpu_cap_has(X86_FEATURE_RDPID))
5941	6013	continue;
5942	6014	break;
5943	6015	case MSR_IA32_UMWAIT_CONTROL:
@@ -7034,7 +7106,10 @@ static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt) · 1090 unmodified lines
7034	7106
7035	7107	static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
7036	7108	{
7037		− emul_to_vcpu(ctxt)->arch.hflags = emul_flags;
	7109	+ struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
	7110	+
	7111	+ vcpu->arch.hflags = emul_flags;
	7112	+ kvm_mmu_reset_context(vcpu);
7038	7113	}
7039	7114
7040	7115	static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt,
@@ -7171,6 +7246,11 @@ static void init_emulate_ctxt(struct kvm_vcpu *vcpu) · 130 unmodified lines
7171	7246	BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
7172	7247	BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
7173	7248
	7249	+ ctxt->interruptibility = 0;
	7250	+ ctxt->have_exception = false;
	7251	+ ctxt->exception.vector = -1;
	7252	+ ctxt->perm_ok = false;
	7253	+
7174	7254	init_decode_cache(ctxt);
7175	7255	vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
7176	7256	}
@@ -7506,14 +7586,7 @@ int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type, · 329 unmodified lines
7506	7586	kvm_vcpu_check_breakpoint(vcpu, &r))
7507	7587	return r;
7508	7588
7509		− ctxt->interruptibility = 0;
7510		− ctxt->have_exception = false;
7511		− ctxt->exception.vector = -1;
7512		− ctxt->perm_ok = false;
7513		−
7514		− ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
7515		−
7516		− r = x86_decode_insn(ctxt, insn, insn_len);
	7589	+ r = x86_decode_insn(ctxt, insn, insn_len, emulation_type);
7517	7590
7518	7591	trace_kvm_emulate_insn_start(vcpu);
7519	7592	++vcpu->stat.insn_emulation;
@@ -8039,6 +8112,18 @@ static void pvclock_gtod_update_fn(struct work_struct *work) · 519 unmodified lines
8039	8112
8040	8113	static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
8041	8114
	8115	+/*
	8116	+ * Indirection to move queue_work() out of the tk_core.seq write held
	8117	+ * region to prevent possible deadlocks against time accessors which
	8118	+ * are invoked with work related locks held.
	8119	+ */
	8120	+static void pvclock_irq_work_fn(struct irq_work *w)
	8121	+{
	8122	+ queue_work(system_long_wq, &pvclock_gtod_work);
	8123	+}
	8124	+
	8125	+static DEFINE_IRQ_WORK(pvclock_irq_work, pvclock_irq_work_fn);
	8126	+
8042	8127	/*
8043	8128	* Notification about pvclock gtod data update.
8044	8129	*/
@@ -8050,13 +8135,14 @@ static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, · 5 unmodified lines
8050	8135
8051	8136	update_pvclock_gtod(tk);
8052	8137
8053		− /* disable master clock if host does not trust, or does not
8054		− * use, TSC based clocksource.
	8138	+ /*
	8139	+ * Disable master clock if host does not trust, or does not use,
	8140	+ * TSC based clocksource. Delegate queue_work() to irq_work as
	8141	+ * this is invoked with tk_core.seq write held.
8055	8142	*/
8056	8143	if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
8057	8144	atomic_read(&kvm_guest_has_master_clock) != 0)
8058		− queue_work(system_long_wq, &pvclock_gtod_work);
8059		−
	8145	+ irq_work_queue(&pvclock_irq_work);
8060	8146	return 0;
8061	8147	}
8062	8148
@@ -8118,6 +8204,7 @@ int kvm_arch_init(void *opaque) · 55 unmodified lines
8118	8204	printk(KERN_ERR "kvm: failed to allocate percpu kvm_user_return_msrs\n");
8119	8205	goto out_free_x86_emulator_cache;
8120	8206	}
	8207	+ kvm_nr_uret_msrs = 0;
8121	8208
8122	8209	r = kvm_mmu_module_init();
8123	8210	if (r)
@@ -8168,10 +8255,13 @@ void kvm_arch_exit(void) · 44 unmodified lines
8168	8255	cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
8169	8256	#ifdef CONFIG_X86_64
8170	8257	pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
	8258	+ irq_work_sync(&pvclock_irq_work);
	8259	+ cancel_work_sync(&pvclock_gtod_work);
8171	8260	#endif
8172	8261	kvm_x86_ops.hardware_enable = NULL;
8173	8262	kvm_mmu_module_exit();
8174	8263	free_percpu(user_return_msrs);
	8264	+ kmem_cache_destroy(x86_emulator_cache);
8175	8265	kmem_cache_destroy(x86_fpu_cache);
8176	8266	#ifdef CONFIG_KVM_XEN
8177	8267	static_key_deferred_flush(&kvm_xen_enabled);
@@ -8289,6 +8379,9 @@ static void kvm_sched_yield(struct kvm_vcpu *vcpu, unsigned long dest_id) · 111 unmodified lines
8289	8379
8290	8380	vcpu->stat.directed_yield_attempted++;
8291	8381
	8382	+ if (single_task_running())
	8383	+ goto no_yield;
	8384	+
8292	8385	rcu_read_lock();
8293	8386	map = rcu_dereference(vcpu->kvm->arch.apic_map);
8294	8387
@@ -9425,7 +9518,7 @@ static int vcpu_run(struct kvm_vcpu *vcpu) · 1130 unmodified lines
9425	9518	if (r <= 0)
9426	9519	break;
9427	9520
9428		− kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
	9521	+ kvm_clear_request(KVM_REQ_UNBLOCK, vcpu);
9429	9522	if (kvm_cpu_has_pending_timer(vcpu))
9430	9523	kvm_inject_pending_timer_irqs(vcpu);
9431	9524
@@ -10044,8 +10137,7 @@ int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, · 612 unmodified lines
10044	10137	kvm_update_dr7(vcpu);
10045	10138
10046	10139	if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
10047		− vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
10048		− get_segment_base(vcpu, VCPU_SREG_CS);
	10140	+ vcpu->arch.singlestep_rip = kvm_get_linear_rip(vcpu);
10049	10141
10050	10142	/*
10051	10143	* Trigger an rflags update that will inject or remove the trace
@@ -11428,7 +11520,8 @@ bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu) · 1376 unmodified lines
11428	11520
11429	11521	void kvm_arch_start_assignment(struct kvm *kvm)
11430	11522	{
11431		− atomic_inc(&kvm->arch.assigned_device_count);
	11523	+ if (atomic_inc_return(&kvm->arch.assigned_device_count) == 1)
	11524	+ static_call_cond(kvm_x86_start_assignment)(kvm);
11432	11525	}
11433	11526	EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
11434	11527

arch/x86/mm/extable.c+1−1

@@ -5,7 +5,7 @@ · 4 unmodified lines
5	5	#include <xen/xen.h>
6	6
7	7	#include <asm/fpu/internal.h>
8		−#include <asm/sev-es.h>
	8	+#include <asm/sev.h>
9	9	#include <asm/traps.h>
10	10	#include <asm/kdebug.h>
11	11

arch/x86/mm/fault.c+2−2

@@ -836,8 +836,8 @@ __bad_area_nosemaphore(struct pt_regs *regs, unsigned long error_code, · 835 unmodified lines
836	836
837	837	if (si_code == SEGV_PKUERR)
838	838	force_sig_pkuerr((void __user *)address, pkey);
839		−
840		− force_sig_fault(SIGSEGV, si_code, (void __user *)address);
	839	+ else
	840	+ force_sig_fault(SIGSEGV, si_code, (void __user *)address);
841	841
842	842	local_irq_disable();
843	843	}

arch/x86/mm/ioremap.c+3−1

@@ -118,7 +118,9 @@ static void __ioremap_check_other(resource_size_t addr, struct ioremap_desc *des · 117 unmodified lines
118	118	if (!IS_ENABLED(CONFIG_EFI))
119	119	return;
120	120
121		− if (efi_mem_type(addr) == EFI_RUNTIME_SERVICES_DATA)
	121	+ if (efi_mem_type(addr) == EFI_RUNTIME_SERVICES_DATA \|\|
	122	+ (efi_mem_type(addr) == EFI_BOOT_SERVICES_DATA &&
	123	+ efi_mem_attributes(addr) & EFI_MEMORY_RUNTIME))
122	124	desc->flags \|= IORES_MAP_ENCRYPTED;
123	125	}
124	126

arch/x86/mm/mem_encrypt_identity.c+9−8

@@ -504,10 +504,6 @@ void __init sme_enable(struct boot_params *bp) · 503 unmodified lines
504	504	#define AMD_SME_BIT BIT(0)
505	505	#define AMD_SEV_BIT BIT(1)
506	506
507		− /* Check the SEV MSR whether SEV or SME is enabled */
508		− sev_status = __rdmsr(MSR_AMD64_SEV);
509		− feature_mask = (sev_status & MSR_AMD64_SEV_ENABLED) ? AMD_SEV_BIT : AMD_SME_BIT;
510		−
511	507	/*
512	508	* Check for the SME/SEV feature:
513	509	* CPUID Fn8000_001F[EAX]
@@ -519,17 +515,22 @@ void __init sme_enable(struct boot_params *bp) · 5 unmodified lines
519	515	eax = 0x8000001f;
520	516	ecx = 0;
521	517	native_cpuid(&eax, &ebx, &ecx, &edx);
522		− if (!(eax & feature_mask))
	518	+ /* Check whether SEV or SME is supported */
	519	+ if (!(eax & (AMD_SEV_BIT \| AMD_SME_BIT)))
523	520	return;
524	521
525	522	me_mask = 1UL << (ebx & 0x3f);
526	523
	524	+ /* Check the SEV MSR whether SEV or SME is enabled */
	525	+ sev_status = __rdmsr(MSR_AMD64_SEV);
	526	+ feature_mask = (sev_status & MSR_AMD64_SEV_ENABLED) ? AMD_SEV_BIT : AMD_SME_BIT;
	527	+
527	528	/* Check if memory encryption is enabled */
528	529	if (feature_mask == AMD_SME_BIT) {
529	530	/*
530	531	* No SME if Hypervisor bit is set. This check is here to
531	532	* prevent a guest from trying to enable SME. For running as a
532		− * KVM guest the MSR_K8_SYSCFG will be sufficient, but there
	533	+ * KVM guest the MSR_AMD64_SYSCFG will be sufficient, but there
533	534	* might be other hypervisors which emulate that MSR as non-zero
534	535	* or even pass it through to the guest.
535	536	* A malicious hypervisor can still trick a guest into this
@@ -542,8 +543,8 @@ void __init sme_enable(struct boot_params *bp) · 6 unmodified lines
542	543	return;
543	544
544	545	/* For SME, check the SYSCFG MSR */
545		− msr = __rdmsr(MSR_K8_SYSCFG);
546		− if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
	546	+ msr = __rdmsr(MSR_AMD64_SYSCFG);
	547	+ if (!(msr & MSR_AMD64_SYSCFG_MEM_ENCRYPT))
547	548	return;
548	549	} else {
549	550	/* SEV state cannot be controlled by a command line option */

arch/x86/mm/numa.c+7−1

@@ -254,7 +254,13 @@ int __init numa_cleanup_meminfo(struct numa_meminfo *mi) · 253 unmodified lines
254	254
255	255	/* make sure all non-reserved blocks are inside the limits */
256	256	bi->start = max(bi->start, low);
257		− bi->end = min(bi->end, high);
	257	+
	258	+ /* preserve info for non-RAM areas above 'max_pfn': */
	259	+ if (bi->end > high) {
	260	+ numa_add_memblk_to(bi->nid, high, bi->end,
	261	+ &numa_reserved_meminfo);
	262	+ bi->end = high;
	263	+ }
258	264
259	265	/* and there's no empty block */
260	266	if (bi->start >= bi->end)

arch/x86/pci/amd_bus.c+1−1

@@ -284,7 +284,7 @@ static int __init early_root_info_init(void) · 283 unmodified lines
284	284
285	285	/* need to take out [4G, TOM2) for RAM*/
286	286	/* SYS_CFG */
287		− address = MSR_K8_SYSCFG;
	287	+ address = MSR_AMD64_SYSCFG;
288	288	rdmsrl(address, val);
289	289	/* TOP_MEM2 is enabled? */
290	290	if (val & (1<<21)) {

arch/x86/pci/fixup.c+44−0

@@ -779,4 +779,48 @@ DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x1571, pci_amd_enable_64bit_bar); · 778 unmodified lines
779	779	DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x15b1, pci_amd_enable_64bit_bar);
780	780	DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x1601, pci_amd_enable_64bit_bar);
781	781
	782	+#define RS690_LOWER_TOP_OF_DRAM2 0x30
	783	+#define RS690_LOWER_TOP_OF_DRAM2_VALID 0x1
	784	+#define RS690_UPPER_TOP_OF_DRAM2 0x31
	785	+#define RS690_HTIU_NB_INDEX 0xA8
	786	+#define RS690_HTIU_NB_INDEX_WR_ENABLE 0x100
	787	+#define RS690_HTIU_NB_DATA 0xAC
	788	+
	789	+/*
	790	+ * Some BIOS implementations support RAM above 4GB, but do not configure the
	791	+ * PCI host to respond to bus master accesses for these addresses. These
	792	+ * implementations set the TOP_OF_DRAM_SLOT1 register correctly, so PCI DMA
	793	+ * works as expected for addresses below 4GB.
	794	+ *
	795	+ * Reference: "AMD RS690 ASIC Family Register Reference Guide" (pg. 2-57)
	796	+ * https://www.amd.com/system/files/TechDocs/43372_rs690_rrg_3.00o.pdf
	797	+ */
	798	+static void rs690_fix_64bit_dma(struct pci_dev *pdev)
	799	+{
	800	+ u32 val = 0;
	801	+ phys_addr_t top_of_dram = __pa(high_memory - 1) + 1;
	802	+
	803	+ if (top_of_dram <= (1ULL << 32))
	804	+ return;
	805	+
	806	+ pci_write_config_dword(pdev, RS690_HTIU_NB_INDEX,
	807	+ RS690_LOWER_TOP_OF_DRAM2);
	808	+ pci_read_config_dword(pdev, RS690_HTIU_NB_DATA, &val);
	809	+
	810	+ if (val)
	811	+ return;
	812	+
	813	+ pci_info(pdev, "Adjusting top of DRAM to %pa for 64-bit DMA support\n", &top_of_dram);
	814	+
	815	+ pci_write_config_dword(pdev, RS690_HTIU_NB_INDEX,
	816	+ RS690_UPPER_TOP_OF_DRAM2 \| RS690_HTIU_NB_INDEX_WR_ENABLE);
	817	+ pci_write_config_dword(pdev, RS690_HTIU_NB_DATA, top_of_dram >> 32);
	818	+
	819	+ pci_write_config_dword(pdev, RS690_HTIU_NB_INDEX,
	820	+ RS690_LOWER_TOP_OF_DRAM2 \| RS690_HTIU_NB_INDEX_WR_ENABLE);
	821	+ pci_write_config_dword(pdev, RS690_HTIU_NB_DATA,
	822	+ top_of_dram \| RS690_LOWER_TOP_OF_DRAM2_VALID);
	823	+}
	824	+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7910, rs690_fix_64bit_dma);
	825	+
782	826	#endif

arch/x86/platform/efi/efi_64.c+1−1

@@ -47,7 +47,7 @@ · 46 unmodified lines
47	47	#include <asm/realmode.h>
48	48	#include <asm/time.h>
49	49	#include <asm/pgalloc.h>
50		−#include <asm/sev-es.h>
	50	+#include <asm/sev.h>
51	51
52	52	/*
53	53	* We allocate runtime services regions top-down, starting from -4G, i.e.

arch/x86/platform/efi/quirks.c+12−0

@@ -450,6 +450,18 @@ void __init efi_free_boot_services(void) · 449 unmodified lines
450	450	size -= rm_size;
451	451	}
452	452
	453	+ /*
	454	+ * Don't free memory under 1M for two reasons:
	455	+ * - BIOS might clobber it
	456	+ * - Crash kernel needs it to be reserved
	457	+ */
	458	+ if (start + size < SZ_1M)
	459	+ continue;
	460	+ if (start < SZ_1M) {
	461	+ size -= (SZ_1M - start);
	462	+ start = SZ_1M;
	463	+ }
	464	+
453	465	memblock_free_late(start, size);
454	466	}
455	467

arch/x86/realmode/init.c+9−7

@@ -9,7 +9,7 @@ · 8 unmodified lines
9	9	#include <asm/realmode.h>
10	10	#include <asm/tlbflush.h>
11	11	#include <asm/crash.h>
12		−#include <asm/sev-es.h>
	12	+#include <asm/sev.h>
13	13
14	14	struct real_mode_header *real_mode_header;
15	15	u32 *trampoline_cr4_features;
@@ -29,14 +29,16 @@ void __init reserve_real_mode(void) · 13 unmodified lines
29	29
30	30	/* Has to be under 1M so we can execute real-mode AP code. */
31	31	mem = memblock_find_in_range(0, 1<<20, size, PAGE_SIZE);
32		− if (!mem) {
	32	+ if (!mem)
33	33	pr_info("No sub-1M memory is available for the trampoline\n");
34		− return;
35		− }
	34	+ else
	35	+ set_real_mode_mem(mem);
36	36
37		− memblock_reserve(mem, size);
38		− set_real_mode_mem(mem);
39		− crash_reserve_low_1M();
	37	+ /*
	38	+ * Unconditionally reserve the entire fisrt 1M, see comment in
	39	+ * setup_arch().
	40	+ */
	41	+ memblock_reserve(0, SZ_1M);
40	42	}
41	43
42	44	static void sme_sev_setup_real_mode(struct trampoline_header *th)

arch/x86/realmode/rm/trampoline_64.S+2−2

@@ -123,9 +123,9 @@ SYM_CODE_START(startup_32) · 122 unmodified lines
123	123	*/
124	124	btl $TH_FLAGS_SME_ACTIVE_BIT, pa_tr_flags
125	125	jnc .Ldone
126		− movl $MSR_K8_SYSCFG, %ecx
	126	+ movl $MSR_AMD64_SYSCFG, %ecx
127	127	rdmsr
128		− bts $MSR_K8_SYSCFG_MEM_ENCRYPT_BIT, %eax
	128	+ bts $MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT, %eax
129	129	jc .Ldone
130	130
131	131	/*

arch/x86/xen/enlighten_pv.c+4−4

@@ -1273,16 +1273,16 @@ asmlinkage __visible void __init xen_start_kernel(void) · 1272 unmodified lines
1273	1273	/* Get mfn list */
1274	1274	xen_build_dynamic_phys_to_machine();
1275	1275
	1276	+ /* Work out if we support NX */
	1277	+ get_cpu_cap(&boot_cpu_data);
	1278	+ x86_configure_nx();
	1279	+
1276	1280	/*
1277	1281	* Set up kernel GDT and segment registers, mainly so that
1278	1282	* -fstack-protector code can be executed.
1279	1283	*/
1280	1284	xen_setup_gdt(0);
1281	1285
1282		− /* Work out if we support NX */
1283		− get_cpu_cap(&boot_cpu_data);
1284		− x86_configure_nx();
1285		−
1286	1286	/* Determine virtual and physical address sizes */
1287	1287	get_cpu_address_sizes(&boot_cpu_data);
1288	1288

arch/xtensa/kernel/syscalls/syscall.tbl+1−1

@@ -413,7 +413,7 @@ · 412 unmodified lines
413	413	440 common process_madvise sys_process_madvise
414	414	441 common epoll_pwait2 sys_epoll_pwait2
415	415	442 common mount_setattr sys_mount_setattr
416		−443 common quotactl_path sys_quotactl_path
	416	+# 443 reserved for quotactl_path
417	417	444 common landlock_create_ruleset sys_landlock_create_ruleset
418	418	445 common landlock_add_rule sys_landlock_add_rule
419	419	446 common landlock_restrict_self sys_landlock_restrict_self

block/bfq-iosched.c+30−4

@@ -372,9 +372,38 @@ struct bfq_queue bic_to_bfqq(struct bfq_io_cq bic, bool is_sync) · 371 unmodified lines
372	372	return bic->bfqq[is_sync];
373	373	}
374	374
	375	+static void bfq_put_stable_ref(struct bfq_queue *bfqq);
	376	+
375	377	void bic_set_bfqq(struct bfq_io_cq bic, struct bfq_queue bfqq, bool is_sync)
376	378	{
	379	+ /*
	380	+ * If bfqq != NULL, then a non-stable queue merge between
	381	+ * bic->bfqq and bfqq is happening here. This causes troubles
	382	+ * in the following case: bic->bfqq has also been scheduled
	383	+ * for a possible stable merge with bic->stable_merge_bfqq,
	384	+ * and bic->stable_merge_bfqq == bfqq happens to
	385	+ * hold. Troubles occur because bfqq may then undergo a split,
	386	+ * thereby becoming eligible for a stable merge. Yet, if
	387	+ * bic->stable_merge_bfqq points exactly to bfqq, then bfqq
	388	+ * would be stably merged with itself. To avoid this anomaly,
	389	+ * we cancel the stable merge if
	390	+ * bic->stable_merge_bfqq == bfqq.
	391	+ */
377	392	bic->bfqq[is_sync] = bfqq;
	393	+
	394	+ if (bfqq && bic->stable_merge_bfqq == bfqq) {
	395	+ /*
	396	+ * Actually, these same instructions are executed also
	397	+ * in bfq_setup_cooperator, in case of abort or actual
	398	+ * execution of a stable merge. We could avoid
	399	+ * repeating these instructions there too, but if we
	400	+ * did so, we would nest even more complexity in this
	401	+ * function.
	402	+ */
	403	+ bfq_put_stable_ref(bic->stable_merge_bfqq);
	404	+
	405	+ bic->stable_merge_bfqq = NULL;
	406	+ }
378	407	}
379	408
380	409	struct bfq_data bic_to_bfqd(struct bfq_io_cq bic)
@@ -2263,10 +2292,9 @@ static void bfq_remove_request(struct request_queue *q, · 1882 unmodified lines
2263	2292
2264	2293	}
2265	2294
2266		−static bool bfq_bio_merge(struct blk_mq_hw_ctx hctx, struct bio bio,
	2295	+static bool bfq_bio_merge(struct request_queue q, struct bio bio,
2267	2296	unsigned int nr_segs)
2268	2297	{
2269		− struct request_queue *q = hctx->queue;
2270	2298	struct bfq_data *bfqd = q->elevator->elevator_data;
2271	2299	struct request *free = NULL;
2272	2300	/*
@@ -2631,8 +2659,6 @@ static bool bfq_may_be_close_cooperator(struct bfq_queue *bfqq, · 358 unmodified lines
2631	2659	static bool idling_boosts_thr_without_issues(struct bfq_data *bfqd,
2632	2660	struct bfq_queue *bfqq);
2633	2661
2634		−static void bfq_put_stable_ref(struct bfq_queue *bfqq);
2635		−
2636	2662	/*
2637	2663	* Attempt to schedule a merge of bfqq with the currently in-service
2638	2664	* queue or with a close queue among the scheduled queues. Return

block/blk-iocost.c+12−2

@@ -1069,7 +1069,17 @@ static void __propagate_weights(struct ioc_gq *iocg, u32 active, u32 inuse, · 1068 unmodified lines
1069	1069
1070	1070	lockdep_assert_held(&ioc->lock);
1071	1071
1072		− inuse = clamp_t(u32, inuse, 1, active);
	1072	+ /*
	1073	+ * For an active leaf node, its inuse shouldn't be zero or exceed
	1074	+ * @active. An active internal node's inuse is solely determined by the
	1075	+ * inuse to active ratio of its children regardless of @inuse.
	1076	+ */
	1077	+ if (list_empty(&iocg->active_list) && iocg->child_active_sum) {
	1078	+ inuse = DIV64_U64_ROUND_UP(active * iocg->child_inuse_sum,
	1079	+ iocg->child_active_sum);
	1080	+ } else {
	1081	+ inuse = clamp_t(u32, inuse, 1, active);
	1082	+ }
1073	1083
1074	1084	iocg->last_inuse = iocg->inuse;
1075	1085	if (save)
@@ -1086,7 +1096,7 @@ static void __propagate_weights(struct ioc_gq *iocg, u32 active, u32 inuse, · 10 unmodified lines
1086	1096	/* update the level sums */
1087	1097	parent->child_active_sum += (s32)(active - child->active);
1088	1098	parent->child_inuse_sum += (s32)(inuse - child->inuse);
1089		− /* apply the udpates */
	1099	+ /* apply the updates */
1090	1100	child->active = active;
1091	1101	child->inuse = inuse;
1092	1102

block/blk-mq-sched.c+5−3

@@ -358,14 +358,16 @@ bool __blk_mq_sched_bio_merge(struct request_queue q, struct bio bio, · 357 unmodified lines
358	358	unsigned int nr_segs)
359	359	{
360	360	struct elevator_queue *e = q->elevator;
361		− struct blk_mq_ctx *ctx = blk_mq_get_ctx(q);
362		− struct blk_mq_hw_ctx *hctx = blk_mq_map_queue(q, bio->bi_opf, ctx);
	361	+ struct blk_mq_ctx *ctx;
	362	+ struct blk_mq_hw_ctx *hctx;
363	363	bool ret = false;
364	364	enum hctx_type type;
365	365
366	366	if (e && e->type->ops.bio_merge)
367		− return e->type->ops.bio_merge(hctx, bio, nr_segs);
	367	+ return e->type->ops.bio_merge(q, bio, nr_segs);
368	368
	369	+ ctx = blk_mq_get_ctx(q);
	370	+ hctx = blk_mq_map_queue(q, bio->bi_opf, ctx);
369	371	type = hctx->type;
370	372	if (!(hctx->flags & BLK_MQ_F_SHOULD_MERGE) \|\|
371	373	list_empty_careful(&ctx->rq_lists[type]))

block/blk-mq.c+7−4

@@ -2232,8 +2232,9 @@ blk_qc_t blk_mq_submit_bio(struct bio *bio) · 2231 unmodified lines
2232	2232	/* Bypass scheduler for flush requests */
2233	2233	blk_insert_flush(rq);
2234	2234	blk_mq_run_hw_queue(data.hctx, true);
2235		− } else if (plug && (q->nr_hw_queues == 1 \|\| q->mq_ops->commit_rqs \|\|
2236		− !blk_queue_nonrot(q))) {
	2235	+ } else if (plug && (q->nr_hw_queues == 1 \|\|
	2236	+ blk_mq_is_sbitmap_shared(rq->mq_hctx->flags) \|\|
	2237	+ q->mq_ops->commit_rqs \|\| !blk_queue_nonrot(q))) {
2237	2238	/*
2238	2239	* Use plugging if we have a ->commit_rqs() hook as well, as
2239	2240	* we know the driver uses bd->last in a smart fashion.
@@ -3285,10 +3286,12 @@ EXPORT_SYMBOL(blk_mq_init_allocated_queue); · 1045 unmodified lines
3285	3286	/* tags can _not_ be used after returning from blk_mq_exit_queue */
3286	3287	void blk_mq_exit_queue(struct request_queue *q)
3287	3288	{
3288		− struct blk_mq_tag_set *set = q->tag_set;
	3289	+ struct blk_mq_tag_set *set = q->tag_set;
3289	3290
3290		− blk_mq_del_queue_tag_set(q);
	3291	+ /* Checks hctx->flags & BLK_MQ_F_TAG_QUEUE_SHARED. */
3291	3292	blk_mq_exit_hw_queues(q, set, set->nr_hw_queues);
	3293	+ /* May clear BLK_MQ_F_TAG_QUEUE_SHARED in hctx->flags. */
	3294	+ blk_mq_del_queue_tag_set(q);
3292	3295	}
3293	3296
3294	3297	static int __blk_mq_alloc_rq_maps(struct blk_mq_tag_set *set)

block/genhd.c+1−10

@@ -29,8 +29,6 @@ · 28 unmodified lines
29	29
30	30	static struct kobject *block_depr;
31	31
32		−DECLARE_RWSEM(bdev_lookup_sem);
33		−
34	32	/* for extended dynamic devt allocation, currently only one major is used */
35	33	#define NR_EXT_DEVT (1 << MINORBITS)
36	34	static DEFINE_IDA(ext_devt_ida);
@@ -609,13 +607,8 @@ void del_gendisk(struct gendisk *disk) · 572 unmodified lines
609	607	blk_integrity_del(disk);
610	608	disk_del_events(disk);
611	609
612		− /*
613		− * Block lookups of the disk until all bdevs are unhashed and the
614		− * disk is marked as dead (GENHD_FL_UP cleared).
615		− */
616		− down_write(&bdev_lookup_sem);
617		−
618	610	mutex_lock(&disk->part0->bd_mutex);
	611	+ disk->flags &= ~GENHD_FL_UP;
619	612	blk_drop_partitions(disk);
620	613	mutex_unlock(&disk->part0->bd_mutex);
621	614
@@ -629,8 +622,6 @@ void del_gendisk(struct gendisk *disk) · 7 unmodified lines
629	622	remove_inode_hash(disk->part0->bd_inode);
630	623
631	624	set_capacity(disk, 0);
632		− disk->flags &= ~GENHD_FL_UP;
633		− up_write(&bdev_lookup_sem);
634	625
635	626	if (!(disk->flags & GENHD_FL_HIDDEN)) {
636	627	sysfs_remove_link(&disk_to_dev(disk)->kobj, "bdi");

block/kyber-iosched.c+3−2

@@ -561,11 +561,12 @@ static void kyber_limit_depth(unsigned int op, struct blk_mq_alloc_data *data) · 560 unmodified lines
561	561	}
562	562	}
563	563
564		−static bool kyber_bio_merge(struct blk_mq_hw_ctx hctx, struct bio bio,
	564	+static bool kyber_bio_merge(struct request_queue q, struct bio bio,
565	565	unsigned int nr_segs)
566	566	{
	567	+ struct blk_mq_ctx *ctx = blk_mq_get_ctx(q);
	568	+ struct blk_mq_hw_ctx *hctx = blk_mq_map_queue(q, bio->bi_opf, ctx);
567	569	struct kyber_hctx_data *khd = hctx->sched_data;
568		− struct blk_mq_ctx *ctx = blk_mq_get_ctx(hctx->queue);
569	570	struct kyber_ctx_queue *kcq = &khd->kcqs[ctx->index_hw[hctx->type]];
570	571	unsigned int sched_domain = kyber_sched_domain(bio->bi_opf);
571	572	struct list_head *rq_list = &kcq->rq_list[sched_domain];

block/mq-deadline.c+1−2

@@ -461,10 +461,9 @@ static int dd_request_merge(struct request_queue q, struct request *rq, · 460 unmodified lines
461	461	return ELEVATOR_NO_MERGE;
462	462	}
463	463
464		−static bool dd_bio_merge(struct blk_mq_hw_ctx hctx, struct bio bio,
	464	+static bool dd_bio_merge(struct request_queue q, struct bio bio,
465	465	unsigned int nr_segs)
466	466	{
467		− struct request_queue *q = hctx->queue;
468	467	struct deadline_data *dd = q->elevator->elevator_data;
469	468	struct request *free = NULL;
470	469	bool ret;

block/partitions/efi.c+1−1

@@ -682,7 +682,7 @@ static void utf16_le_to_7bit(const __le16 in, unsigned int size, u8 out) · 681 unmodified lines
682	682	}
683	683
684	684	/**
685		− * efi_partition(struct parsed_partitions *state)
	685	+ * efi_partition - scan for GPT partitions
686	686	* @state: disk parsed partitions
687	687	*
688	688	* Description: called from check.c, if the disk contains GPT

crypto/async_tx/async_xor.c+2−1

@@ -233,7 +233,8 @@ async_xor_offs(struct page *dest, unsigned int offset, · 232 unmodified lines
233	233	if (submit->flags & ASYNC_TX_XOR_DROP_DST) {
234	234	src_cnt--;
235	235	src_list++;
236		− src_offs++;
	236	+ if (src_offs)
	237	+ src_offs++;
237	238	}
238	239
239	240	/* wait for any prerequisite operations */

drivers/acpi/acpi_apd.c+1−0

@@ -226,6 +226,7 @@ static const struct acpi_device_id acpi_apd_device_ids[] = { · 225 unmodified lines
226	226	{ "AMDI0010", APD_ADDR(wt_i2c_desc) },
227	227	{ "AMD0020", APD_ADDR(cz_uart_desc) },
228	228	{ "AMDI0020", APD_ADDR(cz_uart_desc) },
	229	+ { "AMDI0022", APD_ADDR(cz_uart_desc) },
229	230	{ "AMD0030", },
230	231	{ "AMD0040", APD_ADDR(fch_misc_desc)},
231	232	{ "HYGO0010", APD_ADDR(wt_i2c_desc) },

drivers/acpi/acpica/utdelete.c+8−0

@@ -285,6 +285,14 @@ static void acpi_ut_delete_internal_obj(union acpi_operand_object *object) · 284 unmodified lines
285	285	}
286	286	break;
287	287
	288	+ case ACPI_TYPE_LOCAL_ADDRESS_HANDLER:
	289	+
	290	+ ACPI_DEBUG_PRINT((ACPI_DB_ALLOCATIONS,
	291	+ "***** Address handler %p\n", object));
	292	+
	293	+ acpi_os_delete_mutex(object->address_space.context_mutex);
	294	+ break;
	295	+
288	296	default:
289	297
290	298	break;

drivers/acpi/bus.c+8−19

@@ -330,32 +330,21 @@ static void acpi_bus_osc_negotiate_platform_control(void) · 329 unmodified lines
330	330	if (ACPI_FAILURE(acpi_run_osc(handle, &context)))
331	331	return;
332	332
333		− capbuf_ret = context.ret.pointer;
334		− if (context.ret.length <= OSC_SUPPORT_DWORD) {
335		− kfree(context.ret.pointer);
336		− return;
337		− }
	333	+ kfree(context.ret.pointer);
338	334
339		− /*
340		− * Now run _OSC again with query flag clear and with the caps
341		− * supported by both the OS and the platform.
342		− */
	335	+ /* Now run _OSC again with query flag clear */
343	336	capbuf[OSC_QUERY_DWORD] = 0;
344		− capbuf[OSC_SUPPORT_DWORD] = capbuf_ret[OSC_SUPPORT_DWORD];
345		− kfree(context.ret.pointer);
346	337
347	338	if (ACPI_FAILURE(acpi_run_osc(handle, &context)))
348	339	return;
349	340
350	341	capbuf_ret = context.ret.pointer;
351		− if (context.ret.length > OSC_SUPPORT_DWORD) {
352		− osc_sb_apei_support_acked =
353		− capbuf_ret[OSC_SUPPORT_DWORD] & OSC_SB_APEI_SUPPORT;
354		− osc_pc_lpi_support_confirmed =
355		− capbuf_ret[OSC_SUPPORT_DWORD] & OSC_SB_PCLPI_SUPPORT;
356		− osc_sb_native_usb4_support_confirmed =
357		− capbuf_ret[OSC_SUPPORT_DWORD] & OSC_SB_NATIVE_USB4_SUPPORT;
358		− }
	342	+ osc_sb_apei_support_acked =
	343	+ capbuf_ret[OSC_SUPPORT_DWORD] & OSC_SB_APEI_SUPPORT;
	344	+ osc_pc_lpi_support_confirmed =
	345	+ capbuf_ret[OSC_SUPPORT_DWORD] & OSC_SB_PCLPI_SUPPORT;
	346	+ osc_sb_native_usb4_support_confirmed =
	347	+ capbuf_ret[OSC_SUPPORT_DWORD] & OSC_SB_NATIVE_USB4_SUPPORT;
359	348
360	349	kfree(context.ret.pointer);
361	350	}

drivers/acpi/device_pm.c+1−0

@@ -1313,6 +1313,7 @@ int acpi_dev_pm_attach(struct device *dev, bool power_on) · 1312 unmodified lines
1313	1313	{"PNP0C0B", }, /* Generic ACPI fan */
1314	1314	{"INT3404", }, /* Fan */
1315	1315	{"INTC1044", }, /* Fan for Tiger Lake generation */
	1316	+ {"INTC1048", }, /* Fan for Alder Lake generation */
1316	1317	{}
1317	1318	};
1318	1319	struct acpi_device *adev = ACPI_COMPANION(dev);

drivers/acpi/internal.h+2−1

@@ -134,7 +134,7 @@ int acpi_power_init(void); · 133 unmodified lines
134	134	void acpi_power_resources_list_free(struct list_head *list);
135	135	int acpi_extract_power_resources(union acpi_object *package, unsigned int start,
136	136	struct list_head *list);
137		−int acpi_add_power_resource(acpi_handle handle);
	137	+struct acpi_device *acpi_add_power_resource(acpi_handle handle);
138	138	void acpi_power_add_remove_device(struct acpi_device *adev, bool add);
139	139	int acpi_power_wakeup_list_init(struct list_head list, int system_level);
140	140	int acpi_device_sleep_wake(struct acpi_device *dev,
@@ -142,6 +142,7 @@ int acpi_device_sleep_wake(struct acpi_device *dev, · 1 unmodified line
142	142	int acpi_power_get_inferred_state(struct acpi_device device, int state);
143	143	int acpi_power_on_resources(struct acpi_device *device, int state);
144	144	int acpi_power_transition(struct acpi_device *device, int state);
	145	+void acpi_turn_off_unused_power_resources(bool init);
145	146
146	147	/* --------------------------------------------------------------------------
147	148	Device Power Management

drivers/acpi/nfit/core.c+11−4

@@ -686,6 +686,13 @@ int nfit_spa_type(struct acpi_nfit_system_address *spa) · 685 unmodified lines
686	686	return -1;
687	687	}
688	688
	689	+static size_t sizeof_spa(struct acpi_nfit_system_address *spa)
	690	+{
	691	+ if (spa->flags & ACPI_NFIT_LOCATION_COOKIE_VALID)
	692	+ return sizeof(*spa);
	693	+ return sizeof(*spa) - 8;
	694	+}
	695	+
689	696	static bool add_spa(struct acpi_nfit_desc *acpi_desc,
690	697	struct nfit_table_prev *prev,
691	698	struct acpi_nfit_system_address *spa)
@@ -693,22 +700,22 @@ static bool add_spa(struct acpi_nfit_desc *acpi_desc, · 1 unmodified line
693	700	struct device *dev = acpi_desc->dev;
694	701	struct nfit_spa *nfit_spa;
695	702
696		− if (spa->header.length != sizeof(*spa))
	703	+ if (spa->header.length != sizeof_spa(spa))
697	704	return false;
698	705
699	706	list_for_each_entry(nfit_spa, &prev->spas, list) {
700		− if (memcmp(nfit_spa->spa, spa, sizeof(*spa)) == 0) {
	707	+ if (memcmp(nfit_spa->spa, spa, sizeof_spa(spa)) == 0) {
701	708	list_move_tail(&nfit_spa->list, &acpi_desc->spas);
702	709	return true;
703	710	}
704	711	}
705	712
706		− nfit_spa = devm_kzalloc(dev, sizeof(nfit_spa) + sizeof(spa),
	713	+ nfit_spa = devm_kzalloc(dev, sizeof(*nfit_spa) + sizeof_spa(spa),
707	714	GFP_KERNEL);
708	715	if (!nfit_spa)
709	716	return false;
710	717	INIT_LIST_HEAD(&nfit_spa->list);
711		− memcpy(nfit_spa->spa, spa, sizeof(*spa));
	718	+ memcpy(nfit_spa->spa, spa, sizeof_spa(spa));
712	719	list_add_tail(&nfit_spa->list, &acpi_desc->spas);
713	720	dev_dbg(dev, "spa index: %d type: %s\n",
714	721	spa->range_index,

drivers/acpi/power.c+47−14

@@ -52,6 +52,7 @@ struct acpi_power_resource { · 51 unmodified lines
52	52	u32 system_level;
53	53	u32 order;
54	54	unsigned int ref_count;
	55	+ unsigned int users;
55	56	bool wakeup_enabled;
56	57	struct mutex resource_lock;
57	58	struct list_head dependents;
@@ -147,6 +148,7 @@ int acpi_extract_power_resources(union acpi_object *package, unsigned int start, · 89 unmodified lines
147	148
148	149	for (i = start; i < package->package.count; i++) {
149	150	union acpi_object *element = &package->package.elements[i];
	151	+ struct acpi_device *rdev;
150	152	acpi_handle rhandle;
151	153
152	154	if (element->type != ACPI_TYPE_LOCAL_REFERENCE) {
@@ -163,13 +165,16 @@ int acpi_extract_power_resources(union acpi_object *package, unsigned int start, · 10 unmodified lines
163	165	if (acpi_power_resource_is_dup(package, start, i))
164	166	continue;
165	167
166		− err = acpi_add_power_resource(rhandle);
167		− if (err)
	168	+ rdev = acpi_add_power_resource(rhandle);
	169	+ if (!rdev) {
	170	+ err = -ENODEV;
168	171	break;
169		−
	172	+ }
170	173	err = acpi_power_resources_list_add(rhandle, list);
171	174	if (err)
172	175	break;
	176	+
	177	+ to_power_resource(rdev)->users++;
173	178	}
174	179	if (err)
175	180	acpi_power_resources_list_free(list);
@@ -907,7 +912,7 @@ static void acpi_power_add_resource_to_list(struct acpi_power_resource *resource · 731 unmodified lines
907	912	mutex_unlock(&power_resource_list_lock);
908	913	}
909	914
910		−int acpi_add_power_resource(acpi_handle handle)
	915	+struct acpi_device *acpi_add_power_resource(acpi_handle handle)
911	916	{
912	917	struct acpi_power_resource *resource;
913	918	struct acpi_device *device = NULL;
@@ -918,11 +923,11 @@ int acpi_add_power_resource(acpi_handle handle) · 4 unmodified lines
918	923
919	924	acpi_bus_get_device(handle, &device);
920	925	if (device)
921		− return 0;
	926	+ return device;
922	927
923	928	resource = kzalloc(sizeof(*resource), GFP_KERNEL);
924	929	if (!resource)
925		− return -ENOMEM;
	930	+ return NULL;
926	931
927	932	device = &resource->device;
928	933	acpi_init_device_object(device, handle, ACPI_BUS_TYPE_POWER);
@@ -959,11 +964,11 @@ int acpi_add_power_resource(acpi_handle handle) · 30 unmodified lines
959	964
960	965	acpi_power_add_resource_to_list(resource);
961	966	acpi_device_add_finalize(device);
962		− return 0;
	967	+ return device;
963	968
964	969	err:
965	970	acpi_release_power_resource(&device->dev);
966		− return result;
	971	+ return NULL;
967	972	}
968	973
969	974	#ifdef CONFIG_ACPI_SLEEP
@@ -995,8 +1000,40 @@ void acpi_resume_power_resources(void) · 25 unmodified lines
995	1000
996	1001	mutex_unlock(&power_resource_list_lock);
997	1002	}
	1003	+#endif
	1004	+
	1005	+static void acpi_power_turn_off_if_unused(struct acpi_power_resource *resource,
	1006	+ bool init)
	1007	+{
	1008	+ if (resource->ref_count > 0)
	1009	+ return;
	1010	+
	1011	+ if (init) {
	1012	+ if (resource->users > 0)
	1013	+ return;
	1014	+ } else {
	1015	+ int result, state;
	1016	+
	1017	+ result = acpi_power_get_state(resource->device.handle, &state);
	1018	+ if (result \|\| state == ACPI_POWER_RESOURCE_STATE_OFF)
	1019	+ return;
	1020	+ }
	1021	+
	1022	+ dev_info(&resource->device.dev, "Turning OFF\n");
	1023	+ __acpi_power_off(resource);
	1024	+}
998	1025
999		−void acpi_turn_off_unused_power_resources(void)
	1026	+/**
	1027	+ * acpi_turn_off_unused_power_resources - Turn off power resources not in use.
	1028	+ * @init: Control switch.
	1029	+ *
	1030	+ * If @ainit is set, unconditionally turn off all of the ACPI power resources
	1031	+ * without any users.
	1032	+ *
	1033	+ * Otherwise, turn off all ACPI power resources without active references (that
	1034	+ * is, the ones that should be "off" at the moment) that are "on".
	1035	+ */
	1036	+void acpi_turn_off_unused_power_resources(bool init)
1000	1037	{
1001	1038	struct acpi_power_resource *resource;
1002	1039
@@ -1005,14 +1042,10 @@ void acpi_turn_off_unused_power_resources(void) · 2 unmodified lines
1005	1042	list_for_each_entry_reverse(resource, &acpi_power_resource_list, list_node) {
1006	1043	mutex_lock(&resource->resource_lock);
1007	1044
1008		− if (!resource->ref_count) {
1009		− dev_info(&resource->device.dev, "Turning OFF\n");
1010		− __acpi_power_off(resource);
1011		− }
	1045	+ acpi_power_turn_off_if_unused(resource, init);
1012	1046
1013	1047	mutex_unlock(&resource->resource_lock);
1014	1048	}
1015	1049
1016	1050	mutex_unlock(&power_resource_list_lock);
1017	1051	}
1018		−#endif

drivers/acpi/scan.c+3−0

@@ -700,6 +700,7 @@ int acpi_device_add(struct acpi_device *device, · 699 unmodified lines
700	700
701	701	result = acpi_device_set_name(device, acpi_device_bus_id);
702	702	if (result) {
	703	+ kfree_const(acpi_device_bus_id->bus_id);
703	704	kfree(acpi_device_bus_id);
704	705	goto err_unlock;
705	706	}
@@ -2359,6 +2360,8 @@ int __init acpi_scan_init(void) · 1653 unmodified lines
2359	2360	}
2360	2361	}
2361	2362
	2363	+ acpi_turn_off_unused_power_resources(true);
	2364	+
2362	2365	acpi_scan_initialized = true;
2363	2366
2364	2367	out:

drivers/acpi/sleep.c+2−4

@@ -504,7 +504,7 @@ static void acpi_pm_start(u32 acpi_state) · 503 unmodified lines
504	504	*/
505	505	static void acpi_pm_end(void)
506	506	{
507		− acpi_turn_off_unused_power_resources();
	507	+ acpi_turn_off_unused_power_resources(false);
508	508	acpi_scan_lock_release();
509	509	/*
510	510	* This is necessary in case acpi_pm_finish() is not called during a
@@ -1009,10 +1009,8 @@ static void acpi_sleep_hibernate_setup(void) · 498 unmodified lines
1009	1009	return;
1010	1010
1011	1011	acpi_get_table(ACPI_SIG_FACS, 1, (struct acpi_table_header **)&facs);
1012		− if (facs) {
	1012	+ if (facs)
1013	1013	s4_hardware_signature = facs->hardware_signature;
1014		− acpi_put_table((struct acpi_table_header *)facs);
1015		− }
1016	1014	}
1017	1015	#else /* !CONFIG_HIBERNATION */
1018	1016	static inline void acpi_sleep_hibernate_setup(void) {}

drivers/acpi/sleep.h+0−1

@@ -8,7 +8,6 @@ extern struct list_head acpi_wakeup_device_list; · 7 unmodified lines
8	8	extern struct mutex acpi_device_lock;
9	9
10	10	extern void acpi_resume_power_resources(void);
11		−extern void acpi_turn_off_unused_power_resources(void);
12	11
13	12	static inline acpi_status acpi_set_waking_vector(u32 wakeup_address)
14	13	{

drivers/android/binder.c+1−1

@@ -4918,7 +4918,7 @@ static long binder_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) · 4917 unmodified lines
4918	4918	uint32_t enable;
4919	4919
4920	4920	if (copy_from_user(&enable, ubuf, sizeof(enable))) {
4921		− ret = -EINVAL;
	4921	+ ret = -EFAULT;
4922	4922	goto err;
4923	4923	}
4924	4924	binder_inner_proc_lock(proc);

drivers/base/core.c+38−33

@@ -150,7 +150,7 @@ void fwnode_links_purge(struct fwnode_handle *fwnode) · 149 unmodified lines
150	150	fwnode_links_purge_consumers(fwnode);
151	151	}
152	152
153		−static void fw_devlink_purge_absent_suppliers(struct fwnode_handle *fwnode)
	153	+void fw_devlink_purge_absent_suppliers(struct fwnode_handle *fwnode)
154	154	{
155	155	struct fwnode_handle *child;
156	156
@@ -164,6 +164,7 @@ static void fw_devlink_purge_absent_suppliers(struct fwnode_handle *fwnode) · 7 unmodified lines
164	164	fwnode_for_each_available_child_node(fwnode, child)
165	165	fw_devlink_purge_absent_suppliers(child);
166	166	}
	167	+EXPORT_SYMBOL_GPL(fw_devlink_purge_absent_suppliers);
167	168
168	169	#ifdef CONFIG_SRCU
169	170	static DEFINE_MUTEX(device_links_lock);
@@ -193,6 +194,17 @@ int device_links_read_lock_held(void) · 23 unmodified lines
193	194	{
194	195	return srcu_read_lock_held(&device_links_srcu);
195	196	}
	197	+
	198	+static void device_link_synchronize_removal(void)
	199	+{
	200	+ synchronize_srcu(&device_links_srcu);
	201	+}
	202	+
	203	+static void device_link_remove_from_lists(struct device_link *link)
	204	+{
	205	+ list_del_rcu(&link->s_node);
	206	+ list_del_rcu(&link->c_node);
	207	+}
196	208	#else /* !CONFIG_SRCU */
197	209	static DECLARE_RWSEM(device_links_lock);
198	210
@@ -223,6 +235,16 @@ int device_links_read_lock_held(void) · 24 unmodified lines
223	235	return lockdep_is_held(&device_links_lock);
224	236	}
225	237	#endif
	238	+
	239	+static inline void device_link_synchronize_removal(void)
	240	+{
	241	+}
	242	+
	243	+static void device_link_remove_from_lists(struct device_link *link)
	244	+{
	245	+ list_del(&link->s_node);
	246	+ list_del(&link->c_node);
	247	+}
226	248	#endif /* !CONFIG_SRCU */
227	249
228	250	static bool device_is_ancestor(struct device dev, struct device target)
@@ -444,8 +466,13 @@ static struct attribute *devlink_attrs[] = { · 215 unmodified lines
444	466	};
445	467	ATTRIBUTE_GROUPS(devlink);
446	468
447		−static void device_link_free(struct device_link *link)
	469	+static void device_link_release_fn(struct work_struct *work)
448	470	{
	471	+ struct device_link *link = container_of(work, struct device_link, rm_work);
	472	+
	473	+ /* Ensure that all references to the link object have been dropped. */
	474	+ device_link_synchronize_removal();
	475	+
449	476	while (refcount_dec_not_one(&link->rpm_active))
450	477	pm_runtime_put(link->supplier);
451	478
@@ -454,24 +481,19 @@ static void device_link_free(struct device_link *link) · 2 unmodified lines
454	481	kfree(link);
455	482	}
456	483
457		−#ifdef CONFIG_SRCU
458		−static void __device_link_free_srcu(struct rcu_head *rhead)
459		−{
460		− device_link_free(container_of(rhead, struct device_link, rcu_head));
461		−}
462		−
463	484	static void devlink_dev_release(struct device *dev)
464	485	{
465	486	struct device_link *link = to_devlink(dev);
466	487
467		− call_srcu(&device_links_srcu, &link->rcu_head, __device_link_free_srcu);
468		−}
469		−#else
470		−static void devlink_dev_release(struct device *dev)
471		−{
472		− device_link_free(to_devlink(dev));
	488	+ INIT_WORK(&link->rm_work, device_link_release_fn);
	489	+ /*
	490	+ * It may take a while to complete this work because of the SRCU
	491	+ * synchronization in device_link_release_fn() and if the consumer or
	492	+ * supplier devices get deleted when it runs, so put it into the "long"
	493	+ * workqueue.
	494	+ */
	495	+ queue_work(system_long_wq, &link->rm_work);
473	496	}
474		−#endif
475	497
476	498	static struct class devlink_class = {
477	499	.name = "devlink",
@@ -845,7 +867,6 @@ out: · 367 unmodified lines
845	867	}
846	868	EXPORT_SYMBOL_GPL(device_link_add);
847	869
848		−#ifdef CONFIG_SRCU
849	870	static void __device_link_del(struct kref *kref)
850	871	{
851	872	struct device_link *link = container_of(kref, struct device_link, kref);
@@ -855,25 +876,9 @@ static void __device_link_del(struct kref *kref) · 3 unmodified lines
855	876
856	877	pm_runtime_drop_link(link);
857	878
858		− list_del_rcu(&link->s_node);
859		− list_del_rcu(&link->c_node);
860		− device_unregister(&link->link_dev);
861		−}
862		−#else /* !CONFIG_SRCU */
863		−static void __device_link_del(struct kref *kref)
864		−{
865		− struct device_link *link = container_of(kref, struct device_link, kref);
866		−
867		− dev_info(link->consumer, "Dropping the link to %s\n",
868		− dev_name(link->supplier));
869		−
870		− pm_runtime_drop_link(link);
871		−
872		− list_del(&link->s_node);
873		− list_del(&link->c_node);
	879	+ device_link_remove_from_lists(link);
874	880	device_unregister(&link->link_dev);
875	881	}
876		−#endif /* !CONFIG_SRCU */
877	882
878	883	static void device_link_put_kref(struct device_link *link)
879	884	{

drivers/base/memory.c+3−3

@@ -218,14 +218,14 @@ static int memory_block_offline(struct memory_block *mem) · 217 unmodified lines
218	218	struct zone *zone;
219	219	int ret;
220	220
221		− zone = page_zone(pfn_to_page(start_pfn));
222		−
223	221	/*
224	222	* Unaccount before offlining, such that unpopulated zone and kthreads
225	223	* can properly be torn down in offline_pages().
226	224	*/
227		− if (nr_vmemmap_pages)
	225	+ if (nr_vmemmap_pages) {
	226	+ zone = page_zone(pfn_to_page(start_pfn));
228	227	adjust_present_page_count(zone, -nr_vmemmap_pages);
	228	+ }
229	229
230	230	ret = offline_pages(start_pfn + nr_vmemmap_pages,
231	231	nr_pages - nr_vmemmap_pages);

drivers/base/power/runtime.c+7−3

@@ -1637,6 +1637,7 @@ void pm_runtime_init(struct device *dev) · 1636 unmodified lines
1637	1637	dev->power.request_pending = false;
1638	1638	dev->power.request = RPM_REQ_NONE;
1639	1639	dev->power.deferred_resume = false;
	1640	+ dev->power.needs_force_resume = 0;
1640	1641	INIT_WORK(&dev->power.work, pm_runtime_work);
1641	1642
1642	1643	dev->power.timer_expires = 0;
@@ -1804,10 +1805,12 @@ int pm_runtime_force_suspend(struct device *dev) · 161 unmodified lines
1804	1805	* its parent, but set its status to RPM_SUSPENDED anyway in case this
1805	1806	* function will be called again for it in the meantime.
1806	1807	*/
1807		− if (pm_runtime_need_not_resume(dev))
	1808	+ if (pm_runtime_need_not_resume(dev)) {
1808	1809	pm_runtime_set_suspended(dev);
1809		− else
	1810	+ } else {
1810	1811	__update_runtime_status(dev, RPM_SUSPENDED);
	1812	+ dev->power.needs_force_resume = 1;
	1813	+ }
1811	1814
1812	1815	return 0;
1813	1816
@@ -1834,7 +1837,7 @@ int pm_runtime_force_resume(struct device *dev) · 20 unmodified lines
1834	1837	int (callback)(struct device );
1835	1838	int ret = 0;
1836	1839
1837		− if (!pm_runtime_status_suspended(dev) \|\| pm_runtime_need_not_resume(dev))
	1840	+ if (!pm_runtime_status_suspended(dev) \|\| !dev->power.needs_force_resume)
1838	1841	goto out;
1839	1842
1840	1843	/*
@@ -1853,6 +1856,7 @@ int pm_runtime_force_resume(struct device *dev) · 12 unmodified lines
1853	1856
1854	1857	pm_runtime_mark_last_busy(dev);
1855	1858	out:
	1859	+ dev->power.needs_force_resume = 0;
1856	1860	pm_runtime_enable(dev);
1857	1861	return ret;
1858	1862	}

drivers/block/loop.c+7−18

@@ -1879,29 +1879,18 @@ static int lo_compat_ioctl(struct block_device *bdev, fmode_t mode, · 1878 unmodified lines
1879	1879
1880	1880	static int lo_open(struct block_device *bdev, fmode_t mode)
1881	1881	{
1882		− struct loop_device *lo;
	1882	+ struct loop_device *lo = bdev->bd_disk->private_data;
1883	1883	int err;
1884	1884
1885		− /*
1886		− * take loop_ctl_mutex to protect lo pointer from race with
1887		− * loop_control_ioctl(LOOP_CTL_REMOVE), however, to reduce contention
1888		− * release it prior to updating lo->lo_refcnt.
1889		− */
1890		− err = mutex_lock_killable(&loop_ctl_mutex);
1891		− if (err)
1892		− return err;
1893		− lo = bdev->bd_disk->private_data;
1894		− if (!lo) {
1895		− mutex_unlock(&loop_ctl_mutex);
1896		− return -ENXIO;
1897		− }
1898	1885	err = mutex_lock_killable(&lo->lo_mutex);
1899		− mutex_unlock(&loop_ctl_mutex);
1900	1886	if (err)
1901	1887	return err;
1902		− atomic_inc(&lo->lo_refcnt);
	1888	+ if (lo->lo_state == Lo_deleting)
	1889	+ err = -ENXIO;
	1890	+ else
	1891	+ atomic_inc(&lo->lo_refcnt);
1903	1892	mutex_unlock(&lo->lo_mutex);
1904		− return 0;
	1893	+ return err;
1905	1894	}
1906	1895
1907	1896	static void lo_release(struct gendisk *disk, fmode_t mode)
@@ -2285,7 +2274,7 @@ static long loop_control_ioctl(struct file *file, unsigned int cmd, · 377 unmodified lines
2285	2274	mutex_unlock(&lo->lo_mutex);
2286	2275	break;
2287	2276	}
2288		− lo->lo_disk->private_data = NULL;
	2277	+ lo->lo_state = Lo_deleting;
2289	2278	mutex_unlock(&lo->lo_mutex);
2290	2279	idr_remove(&loop_index_idr, lo->lo_number);
2291	2280	loop_remove(lo);

drivers/block/loop.h+1−0

@@ -22,6 +22,7 @@ enum { · 21 unmodified lines
22	22	Lo_unbound,
23	23	Lo_bound,
24	24	Lo_rundown,
	25	+ Lo_deleting,
25	26	};
26	27
27	28	struct loop_func_table;

drivers/block/nbd.c+5−5

@@ -1980,7 +1980,8 @@ static void nbd_disconnect_and_put(struct nbd_device *nbd) · 1979 unmodified lines
1980	1980	* config ref and try to destroy the workqueue from inside the work
1981	1981	* queue.
1982	1982	*/
1983		− flush_workqueue(nbd->recv_workq);
	1983	+ if (nbd->recv_workq)
	1984	+ flush_workqueue(nbd->recv_workq);
1984	1985	if (test_and_clear_bit(NBD_RT_HAS_CONFIG_REF,
1985	1986	&nbd->config->runtime_flags))
1986	1987	nbd_config_put(nbd);
@@ -2014,12 +2015,11 @@ static int nbd_genl_disconnect(struct sk_buff skb, struct genl_info info) · 27 unmodified lines
2014	2015	return -EINVAL;
2015	2016	}
2016	2017	mutex_unlock(&nbd_index_mutex);
2017		− if (!refcount_inc_not_zero(&nbd->config_refs)) {
2018		− nbd_put(nbd);
2019		− return 0;
2020		− }
	2018	+ if (!refcount_inc_not_zero(&nbd->config_refs))
	2019	+ goto put_nbd;
2021	2020	nbd_disconnect_and_put(nbd);
2022	2021	nbd_config_put(nbd);
	2022	+put_nbd:
2023	2023	nbd_put(nbd);
2024	2024	return 0;
2025	2025	}

drivers/bluetooth/btusb.c+23−2

@@ -388,6 +388,8 @@ static const struct usb_device_id blacklist_table[] = { · 387 unmodified lines
388	388	/* Realtek 8822CE Bluetooth devices */
389	389	{ USB_DEVICE(0x0bda, 0xb00c), .driver_info = BTUSB_REALTEK \|
390	390	BTUSB_WIDEBAND_SPEECH },
	391	+ { USB_DEVICE(0x0bda, 0xc822), .driver_info = BTUSB_REALTEK \|
	392	+ BTUSB_WIDEBAND_SPEECH },
391	393
392	394	/* Realtek 8852AE Bluetooth devices */
393	395	{ USB_DEVICE(0x0bda, 0xc852), .driver_info = BTUSB_REALTEK \|
@@ -2527,10 +2529,17 @@ static int btusb_intel_download_firmware_newgen(struct hci_dev *hdev, · 2133 unmodified lines
2527	2529	}
2528	2530
2529	2531	btusb_setup_intel_newgen_get_fw_name(ver, fwname, sizeof(fwname), "sfi");
2530		− err = request_firmware(&fw, fwname, &hdev->dev);
	2532	+ err = firmware_request_nowarn(&fw, fwname, &hdev->dev);
2531	2533	if (err < 0) {
	2534	+ if (!test_bit(BTUSB_BOOTLOADER, &data->flags)) {
	2535	+ /* Firmware has already been loaded */
	2536	+ set_bit(BTUSB_FIRMWARE_LOADED, &data->flags);
	2537	+ return 0;
	2538	+ }
	2539	+
2532	2540	bt_dev_err(hdev, "Failed to load Intel firmware file %s (%d)",
2533	2541	fwname, err);
	2542	+
2534	2543	return err;
2535	2544	}
2536	2545
@@ -2680,12 +2689,24 @@ download: · 143 unmodified lines
2680	2689	err = btusb_setup_intel_new_get_fw_name(ver, params, fwname,
2681	2690	sizeof(fwname), "sfi");
2682	2691	if (err < 0) {
	2692	+ if (!test_bit(BTUSB_BOOTLOADER, &data->flags)) {
	2693	+ /* Firmware has already been loaded */
	2694	+ set_bit(BTUSB_FIRMWARE_LOADED, &data->flags);
	2695	+ return 0;
	2696	+ }
	2697	+
2683	2698	bt_dev_err(hdev, "Unsupported Intel firmware naming");
2684	2699	return -EINVAL;
2685	2700	}
2686	2701
2687		− err = request_firmware(&fw, fwname, &hdev->dev);
	2702	+ err = firmware_request_nowarn(&fw, fwname, &hdev->dev);
2688	2703	if (err < 0) {
	2704	+ if (!test_bit(BTUSB_BOOTLOADER, &data->flags)) {
	2705	+ /* Firmware has already been loaded */
	2706	+ set_bit(BTUSB_FIRMWARE_LOADED, &data->flags);
	2707	+ return 0;
	2708	+ }
	2709	+
2689	2710	bt_dev_err(hdev, "Failed to load Intel firmware file %s (%d)",
2690	2711	fwname, err);
2691	2712	return err;

drivers/bus/mhi/pci_generic.c+38−4

@@ -311,8 +311,8 @@ static const struct mhi_channel_config mhi_foxconn_sdx55_channels[] = { · 310 unmodified lines
311	311	MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1),
312	312	MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0),
313	313	MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0),
314		− MHI_CHANNEL_CONFIG_UL(32, "AT", 32, 0),
315		− MHI_CHANNEL_CONFIG_DL(33, "AT", 32, 0),
	314	+ MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0),
	315	+ MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0),
316	316	MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2),
317	317	MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3),
318	318	};
@@ -708,7 +708,7 @@ static void mhi_pci_remove(struct pci_dev *pdev) · 389 unmodified lines
708	708	struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev);
709	709	struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
710	710
711		− del_timer(&mhi_pdev->health_check_timer);
	711	+ del_timer_sync(&mhi_pdev->health_check_timer);
712	712	cancel_work_sync(&mhi_pdev->recovery_work);
713	713
714	714	if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) {
@@ -935,9 +935,43 @@ static int __maybe_unused mhi_pci_resume(struct device *dev) · 220 unmodified lines
935	935	return ret;
936	936	}
937	937
	938	+static int __maybe_unused mhi_pci_freeze(struct device *dev)
	939	+{
	940	+ struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev);
	941	+ struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
	942	+
	943	+ /* We want to stop all operations, hibernation does not guarantee that
	944	+ * device will be in the same state as before freezing, especially if
	945	+ * the intermediate restore kernel reinitializes MHI device with new
	946	+ * context.
	947	+ */
	948	+ if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) {
	949	+ mhi_power_down(mhi_cntrl, false);
	950	+ mhi_unprepare_after_power_down(mhi_cntrl);
	951	+ }
	952	+
	953	+ return 0;
	954	+}
	955	+
	956	+static int __maybe_unused mhi_pci_restore(struct device *dev)
	957	+{
	958	+ struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev);
	959	+
	960	+ /* Reinitialize the device */
	961	+ queue_work(system_long_wq, &mhi_pdev->recovery_work);
	962	+
	963	+ return 0;
	964	+}
	965	+
938	966	static const struct dev_pm_ops mhi_pci_pm_ops = {
939	967	SET_RUNTIME_PM_OPS(mhi_pci_runtime_suspend, mhi_pci_runtime_resume, NULL)
940		− SET_SYSTEM_SLEEP_PM_OPS(mhi_pci_suspend, mhi_pci_resume)
	968	+#ifdef CONFIG_PM_SLEEP
	969	+ .suspend = mhi_pci_suspend,
	970	+ .resume = mhi_pci_resume,
	971	+ .freeze = mhi_pci_freeze,
	972	+ .thaw = mhi_pci_restore,
	973	+ .restore = mhi_pci_restore,
	974	+#endif
941	975	};
942	976
943	977	static struct pci_driver mhi_pci_driver = {

drivers/bus/ti-sysc.c+54−6

@@ -1334,6 +1334,34 @@ err_allow_idle: · 1333 unmodified lines
1334	1334	return error;
1335	1335	}
1336	1336
	1337	+static int sysc_reinit_module(struct sysc *ddata, bool leave_enabled)
	1338	+{
	1339	+ struct device *dev = ddata->dev;
	1340	+ int error;
	1341	+
	1342	+ /* Disable target module if it is enabled */
	1343	+ if (ddata->enabled) {
	1344	+ error = sysc_runtime_suspend(dev);
	1345	+ if (error)
	1346	+ dev_warn(dev, "reinit suspend failed: %i\n", error);
	1347	+ }
	1348	+
	1349	+ /* Enable target module */
	1350	+ error = sysc_runtime_resume(dev);
	1351	+ if (error)
	1352	+ dev_warn(dev, "reinit resume failed: %i\n", error);
	1353	+
	1354	+ if (leave_enabled)
	1355	+ return error;
	1356	+
	1357	+ /* Disable target module if no leave_enabled was set */
	1358	+ error = sysc_runtime_suspend(dev);
	1359	+ if (error)
	1360	+ dev_warn(dev, "reinit suspend failed: %i\n", error);
	1361	+
	1362	+ return error;
	1363	+}
	1364	+
1337	1365	static int __maybe_unused sysc_noirq_suspend(struct device *dev)
1338	1366	{
1339	1367	struct sysc *ddata;
@@ -1344,12 +1372,18 @@ static int __maybe_unused sysc_noirq_suspend(struct device *dev) · 4 unmodified lines
1344	1372	(SYSC_QUIRK_LEGACY_IDLE \| SYSC_QUIRK_NO_IDLE))
1345	1373	return 0;
1346	1374
1347		− return pm_runtime_force_suspend(dev);
	1375	+ if (!ddata->enabled)
	1376	+ return 0;
	1377	+
	1378	+ ddata->needs_resume = 1;
	1379	+
	1380	+ return sysc_runtime_suspend(dev);
1348	1381	}
1349	1382
1350	1383	static int __maybe_unused sysc_noirq_resume(struct device *dev)
1351	1384	{
1352	1385	struct sysc *ddata;
	1386	+ int error = 0;
1353	1387
1354	1388	ddata = dev_get_drvdata(dev);
1355	1389
@@ -1357,7 +1391,19 @@ static int __maybe_unused sysc_noirq_resume(struct device *dev) · 1 unmodified line
1357	1391	(SYSC_QUIRK_LEGACY_IDLE \| SYSC_QUIRK_NO_IDLE))
1358	1392	return 0;
1359	1393
1360		− return pm_runtime_force_resume(dev);
	1394	+ if (ddata->cfg.quirks & SYSC_QUIRK_REINIT_ON_RESUME) {
	1395	+ error = sysc_reinit_module(ddata, ddata->needs_resume);
	1396	+ if (error)
	1397	+ dev_warn(dev, "noirq_resume failed: %i\n", error);
	1398	+ } else if (ddata->needs_resume) {
	1399	+ error = sysc_runtime_resume(dev);
	1400	+ if (error)
	1401	+ dev_warn(dev, "noirq_resume failed: %i\n", error);
	1402	+ }
	1403	+
	1404	+ ddata->needs_resume = 0;
	1405	+
	1406	+ return error;
1361	1407	}
1362	1408
1363	1409	static const struct dev_pm_ops sysc_pm_ops = {
@@ -1408,9 +1454,9 @@ static const struct sysc_revision_quirk sysc_revision_quirks[] = { · 44 unmodified lines
1408	1454	SYSC_QUIRK_SWSUP_SIDLE \| SYSC_QUIRK_LEGACY_IDLE),
1409	1455	/* Uarts on omap4 and later */
1410	1456	SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff,
1411		− SYSC_QUIRK_SWSUP_SIDLE_ACT \| SYSC_QUIRK_LEGACY_IDLE),
	1457	+ SYSC_QUIRK_SWSUP_SIDLE \| SYSC_QUIRK_LEGACY_IDLE),
1412	1458	SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff,
1413		− SYSC_QUIRK_SWSUP_SIDLE_ACT \| SYSC_QUIRK_LEGACY_IDLE),
	1459	+ SYSC_QUIRK_SWSUP_SIDLE \| SYSC_QUIRK_LEGACY_IDLE),
1414	1460
1415	1461	/* Quirks that need to be set based on the module address */
1416	1462	SYSC_QUIRK("mcpdm", 0x40132000, 0, 0x10, -ENODEV, 0x50000800, 0xffffffff,
@@ -1459,6 +1505,8 @@ static const struct sysc_revision_quirk sysc_revision_quirks[] = { · 42 unmodified lines
1459	1505	SYSC_QUIRK_SWSUP_SIDLE \| SYSC_QUIRK_SWSUP_MSTANDBY),
1460	1506	SYSC_QUIRK("tptc", 0, 0, -ENODEV, -ENODEV, 0x40007c00, 0xffffffff,
1461	1507	SYSC_QUIRK_SWSUP_SIDLE \| SYSC_QUIRK_SWSUP_MSTANDBY),
	1508	+ SYSC_QUIRK("sata", 0, 0xfc, 0x1100, -ENODEV, 0x5e412000, 0xffffffff,
	1509	+ SYSC_QUIRK_SWSUP_SIDLE \| SYSC_QUIRK_SWSUP_MSTANDBY),
1462	1510	SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff,
1463	1511	SYSC_QUIRK_SWSUP_SIDLE \| SYSC_QUIRK_SWSUP_MSTANDBY),
1464	1512	SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -ENODEV, 0x50700101, 0xffffffff,
@@ -1466,7 +1514,8 @@ static const struct sysc_revision_quirk sysc_revision_quirks[] = { · 1 unmodified line
1466	1514	SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050,
1467	1515	0xffffffff, SYSC_QUIRK_SWSUP_SIDLE \| SYSC_QUIRK_SWSUP_MSTANDBY),
1468	1516	SYSC_QUIRK("usb_otg_hs", 0, 0, 0x10, -ENODEV, 0x4ea2080d, 0xffffffff,
1469		− SYSC_QUIRK_SWSUP_SIDLE \| SYSC_QUIRK_SWSUP_MSTANDBY),
	1517	+ SYSC_QUIRK_SWSUP_SIDLE \| SYSC_QUIRK_SWSUP_MSTANDBY \|
	1518	+ SYSC_QUIRK_REINIT_ON_RESUME),
1470	1519	SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
1471	1520	SYSC_MODULE_QUIRK_WDT),
1472	1521	/* PRUSS on am3, am4 and am5 */
@@ -1524,7 +1573,6 @@ static const struct sysc_revision_quirk sysc_revision_quirks[] = { · 51 unmodified lines
1524	1573	SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000400, 0xffffffff, 0),
1525	1574	SYSC_QUIRK("rfbi", 0x4832a800, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1526	1575	SYSC_QUIRK("rfbi", 0x58002000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1527		− SYSC_QUIRK("sata", 0, 0xfc, 0x1100, -ENODEV, 0x5e412000, 0xffffffff, 0),
1528	1576	SYSC_QUIRK("scm", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0),
1529	1577	SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4e8b0100, 0xffffffff, 0),
1530	1578	SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4f000100, 0xffffffff, 0),

drivers/cdrom/gdrom.c+10−3

@@ -744,6 +744,13 @@ static const struct blk_mq_ops gdrom_mq_ops = { · 743 unmodified lines
744	744	static int probe_gdrom(struct platform_device *devptr)
745	745	{
746	746	int err;
	747	+
	748	+ /*
	749	+ * Ensure our "one" device is initialized properly in case of previous
	750	+ * usages of it
	751	+ */
	752	+ memset(&gd, 0, sizeof(gd));
	753	+
747	754	/* Start the device */
748	755	if (gdrom_execute_diagnostic() != 1) {
749	756	pr_warn("ATA Probe for GDROM failed\n");
@@ -830,6 +837,8 @@ static int remove_gdrom(struct platform_device *devptr) · 80 unmodified lines
830	837	if (gdrom_major)
831	838	unregister_blkdev(gdrom_major, GDROM_DEV_NAME);
832	839	unregister_cdrom(gd.cd_info);
	840	+ kfree(gd.cd_info);
	841	+ kfree(gd.toc);
833	842
834	843	return 0;
835	844	}
@@ -845,7 +854,7 @@ static struct platform_driver gdrom_driver = { · 9 unmodified lines
845	854	static int __init init_gdrom(void)
846	855	{
847	856	int rc;
848		− gd.toc = NULL;
	857	+
849	858	rc = platform_driver_register(&gdrom_driver);
850	859	if (rc)
851	860	return rc;
@@ -861,8 +870,6 @@ static void __exit exit_gdrom(void) · 9 unmodified lines
861	870	{
862	871	platform_device_unregister(pd);
863	872	platform_driver_unregister(&gdrom_driver);
864		− kfree(gd.toc);
865		− kfree(gd.cd_info);
866	873	}
867	874
868	875	module_init(init_gdrom);

drivers/char/hpet.c+2−0

@@ -984,6 +984,8 @@ static acpi_status hpet_resources(struct acpi_resource res, void data) · 983 unmodified lines
984	984	hdp->hd_phys_address = fixmem32->address;
985	985	hdp->hd_address = ioremap(fixmem32->address,
986	986	HPET_RANGE_SIZE);
	987	+ if (!hdp->hd_address)
	988	+ return AE_ERROR;
987	989
988	990	if (hpet_is_known(hdp)) {
989	991	iounmap(hdp->hd_address);

drivers/char/tpm/tpm2-cmd.c+1−0

@@ -656,6 +656,7 @@ int tpm2_get_cc_attrs_tbl(struct tpm_chip *chip) · 655 unmodified lines
656	656
657	657	if (nr_commands !=
658	658	be32_to_cpup((__be32 *)&buf.data[TPM_HEADER_SIZE + 5])) {
	659	+ rc = -EFAULT;
659	660	tpm_buf_destroy(&buf);
660	661	goto out;
661	662	}

drivers/char/tpm/tpm_tis_core.c+14−8

@@ -709,16 +709,14 @@ static int tpm_tis_gen_interrupt(struct tpm_chip *chip) · 708 unmodified lines
709	709	cap_t cap;
710	710	int ret;
711	711
712		− /* TPM 2.0 */
713		− if (chip->flags & TPM_CHIP_FLAG_TPM2)
714		− return tpm2_get_tpm_pt(chip, 0x100, &cap2, desc);
715		−
716		− /* TPM 1.2 */
717	712	ret = request_locality(chip, 0);
718	713	if (ret < 0)
719	714	return ret;
720	715
721		− ret = tpm1_getcap(chip, TPM_CAP_PROP_TIS_TIMEOUT, &cap, desc, 0);
	716	+ if (chip->flags & TPM_CHIP_FLAG_TPM2)
	717	+ ret = tpm2_get_tpm_pt(chip, 0x100, &cap2, desc);
	718	+ else
	719	+ ret = tpm1_getcap(chip, TPM_CAP_PROP_TIS_TIMEOUT, &cap, desc, 0);
722	720
723	721	release_locality(chip, 0);
724	722
@@ -1127,12 +1125,20 @@ int tpm_tis_resume(struct device *dev) · 402 unmodified lines
1127	1125	if (ret)
1128	1126	return ret;
1129	1127
1130		− /* TPM 1.2 requires self-test on resume. This function actually returns
	1128	+ /*
	1129	+ * TPM 1.2 requires self-test on resume. This function actually returns
1131	1130	* an error code but for unknown reason it isn't handled.
1132	1131	*/
1133		− if (!(chip->flags & TPM_CHIP_FLAG_TPM2))
	1132	+ if (!(chip->flags & TPM_CHIP_FLAG_TPM2)) {
	1133	+ ret = request_locality(chip, 0);
	1134	+ if (ret < 0)
	1135	+ return ret;
	1136	+
1134	1137	tpm1_do_selftest(chip);
1135	1138
	1139	+ release_locality(chip, 0);
	1140	+ }
	1141	+
1136	1142	return 0;
1137	1143	}
1138	1144	EXPORT_SYMBOL_GPL(tpm_tis_resume);

drivers/clk/clk.c+9−0

@@ -4540,6 +4540,9 @@ int of_clk_add_provider(struct device_node *np, · 4539 unmodified lines
4540	4540	struct of_clk_provider *cp;
4541	4541	int ret;
4542	4542
	4543	+ if (!np)
	4544	+ return 0;
	4545	+
4543	4546	cp = kzalloc(sizeof(*cp), GFP_KERNEL);
4544	4547	if (!cp)
4545	4548	return -ENOMEM;
@@ -4579,6 +4582,9 @@ int of_clk_add_hw_provider(struct device_node *np, · 33 unmodified lines
4579	4582	struct of_clk_provider *cp;
4580	4583	int ret;
4581	4584
	4585	+ if (!np)
	4586	+ return 0;
	4587	+
4582	4588	cp = kzalloc(sizeof(*cp), GFP_KERNEL);
4583	4589	if (!cp)
4584	4590	return -ENOMEM;
@@ -4676,6 +4682,9 @@ void of_clk_del_provider(struct device_node *np) · 91 unmodified lines
4676	4682	{
4677	4683	struct of_clk_provider *cp;
4678	4684
	4685	+ if (!np)
	4686	+ return;
	4687	+
4679	4688	mutex_lock(&of_clk_mutex);
4680	4689	list_for_each_entry(cp, &of_clk_providers, link) {
4681	4690	if (cp->node == np) {

drivers/clocksource/hyperv_timer.c+2−2

@@ -419,7 +419,7 @@ static void resume_hv_clock_tsc(struct clocksource *arg) · 418 unmodified lines
419	419	hv_set_register(HV_REGISTER_REFERENCE_TSC, tsc_msr);
420	420	}
421	421
422		−#ifdef VDSO_CLOCKMODE_HVCLOCK
	422	+#ifdef HAVE_VDSO_CLOCKMODE_HVCLOCK
423	423	static int hv_cs_enable(struct clocksource *cs)
424	424	{
425	425	vclocks_set_used(VDSO_CLOCKMODE_HVCLOCK);
@@ -435,7 +435,7 @@ static struct clocksource hyperv_cs_tsc = { · 9 unmodified lines
435	435	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
436	436	.suspend= suspend_hv_clock_tsc,
437	437	.resume = resume_hv_clock_tsc,
438		−#ifdef VDSO_CLOCKMODE_HVCLOCK
	438	+#ifdef HAVE_VDSO_CLOCKMODE_HVCLOCK
439	439	.enable = hv_cs_enable,
440	440	.vdso_clock_mode = VDSO_CLOCKMODE_HVCLOCK,
441	441	#else

drivers/cpufreq/Kconfig.arm+0−10

@@ -19,16 +19,6 @@ config ACPI_CPPC_CPUFREQ · 18 unmodified lines
19	19
20	20	If in doubt, say N.
21	21
22		−config ACPI_CPPC_CPUFREQ_FIE
23		− bool "Frequency Invariance support for CPPC cpufreq driver"
24		− depends on ACPI_CPPC_CPUFREQ && GENERIC_ARCH_TOPOLOGY
25		− default y
26		− help
27		− This extends frequency invariance support in the CPPC cpufreq driver,
28		− by using CPPC delivered and reference performance counters.
29		−
30		− If in doubt, say N.
31		−
32	22	config ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM
33	23	tristate "Allwinner nvmem based SUN50I CPUFreq driver"
34	24	depends on ARCH_SUNXI

drivers/cpufreq/acpi-cpufreq.c+5−1

@@ -646,7 +646,11 @@ static u64 get_max_boost_ratio(unsigned int cpu) · 645 unmodified lines
646	646	return 0;
647	647	}
648	648
649		− highest_perf = perf_caps.highest_perf;
	649	+ if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
	650	+ highest_perf = amd_get_highest_perf();
	651	+ else
	652	+ highest_perf = perf_caps.highest_perf;
	653	+
650	654	nominal_perf = perf_caps.nominal_perf;
651	655
652	656	if (!highest_perf \|\| !nominal_perf) {

drivers/cpufreq/cppc_cpufreq.c+12−233

@@ -10,18 +10,14 @@ · 9 unmodified lines
10	10
11	11	#define pr_fmt(fmt) "CPPC Cpufreq:" fmt
12	12
13		−#include <linux/arch_topology.h>
14	13	#include <linux/kernel.h>
15	14	#include <linux/module.h>
16	15	#include <linux/delay.h>
17	16	#include <linux/cpu.h>
18	17	#include <linux/cpufreq.h>
19	18	#include <linux/dmi.h>
20		−#include <linux/irq_work.h>
21		−#include <linux/kthread.h>
22	19	#include <linux/time.h>
23	20	#include <linux/vmalloc.h>
24		−#include <uapi/linux/sched/types.h>
25	21
26	22	#include <asm/unaligned.h>
27	23
@@ -61,204 +57,6 @@ static struct cppc_workaround_oem_info wa_info[] = { · 33 unmodified lines
61	57	}
62	58	};
63	59
64		−#ifdef CONFIG_ACPI_CPPC_CPUFREQ_FIE
65		−
66		−/* Frequency invariance support */
67		−struct cppc_freq_invariance {
68		− int cpu;
69		− struct irq_work irq_work;
70		− struct kthread_work work;
71		− struct cppc_perf_fb_ctrs prev_perf_fb_ctrs;
72		− struct cppc_cpudata *cpu_data;
73		−};
74		−
75		−static DEFINE_PER_CPU(struct cppc_freq_invariance, cppc_freq_inv);
76		−static struct kthread_worker *kworker_fie;
77		−static bool fie_disabled;
78		−
79		−static struct cpufreq_driver cppc_cpufreq_driver;
80		−static unsigned int hisi_cppc_cpufreq_get_rate(unsigned int cpu);
81		−static int cppc_perf_from_fbctrs(struct cppc_cpudata *cpu_data,
82		− struct cppc_perf_fb_ctrs fb_ctrs_t0,
83		− struct cppc_perf_fb_ctrs fb_ctrs_t1);
84		−
85		−/**
86		− * cppc_scale_freq_workfn - CPPC arch_freq_scale updater for frequency invariance
87		− * @work: The work item.
88		− *
89		− * The CPPC driver register itself with the topology core to provide its own
90		− * implementation (cppc_scale_freq_tick()) of topology_scale_freq_tick() which
91		− * gets called by the scheduler on every tick.
92		− *
93		− * Note that the arch specific counters have higher priority than CPPC counters,
94		− * if available, though the CPPC driver doesn't need to have any special
95		− * handling for that.
96		− *
97		− * On an invocation of cppc_scale_freq_tick(), we schedule an irq work (since we
98		− * reach here from hard-irq context), which then schedules a normal work item
99		− * and cppc_scale_freq_workfn() updates the per_cpu arch_freq_scale variable
100		− * based on the counter updates since the last tick.
101		− */
102		−static void cppc_scale_freq_workfn(struct kthread_work *work)
103		−{
104		− struct cppc_freq_invariance *cppc_fi;
105		− struct cppc_perf_fb_ctrs fb_ctrs = {0};
106		− struct cppc_cpudata *cpu_data;
107		− unsigned long local_freq_scale;
108		− u64 perf;
109		−
110		− cppc_fi = container_of(work, struct cppc_freq_invariance, work);
111		− cpu_data = cppc_fi->cpu_data;
112		−
113		− if (cppc_get_perf_ctrs(cppc_fi->cpu, &fb_ctrs)) {
114		− pr_warn("%s: failed to read perf counters\n", __func__);
115		− return;
116		− }
117		−
118		− cppc_fi->prev_perf_fb_ctrs = fb_ctrs;
119		− perf = cppc_perf_from_fbctrs(cpu_data, cppc_fi->prev_perf_fb_ctrs,
120		− fb_ctrs);
121		−
122		− perf <<= SCHED_CAPACITY_SHIFT;
123		− local_freq_scale = div64_u64(perf, cpu_data->perf_caps.highest_perf);
124		− if (WARN_ON(local_freq_scale > 1024))
125		− local_freq_scale = 1024;
126		−
127		− per_cpu(arch_freq_scale, cppc_fi->cpu) = local_freq_scale;
128		−}
129		−
130		−static void cppc_irq_work(struct irq_work *irq_work)
131		−{
132		− struct cppc_freq_invariance *cppc_fi;
133		−
134		− cppc_fi = container_of(irq_work, struct cppc_freq_invariance, irq_work);
135		− kthread_queue_work(kworker_fie, &cppc_fi->work);
136		−}
137		−
138		−static void cppc_scale_freq_tick(void)
139		−{
140		− struct cppc_freq_invariance *cppc_fi = &per_cpu(cppc_freq_inv, smp_processor_id());
141		−
142		− /*
143		− * cppc_get_perf_ctrs() can potentially sleep, call that from the right
144		− * context.
145		− */
146		− irq_work_queue(&cppc_fi->irq_work);
147		−}
148		−
149		−static struct scale_freq_data cppc_sftd = {
150		− .source = SCALE_FREQ_SOURCE_CPPC,
151		− .set_freq_scale = cppc_scale_freq_tick,
152		−};
153		−
154		−static void cppc_freq_invariance_policy_init(struct cpufreq_policy *policy,
155		− struct cppc_cpudata *cpu_data)
156		−{
157		− struct cppc_perf_fb_ctrs fb_ctrs = {0};
158		− struct cppc_freq_invariance *cppc_fi;
159		− int i, ret;
160		−
161		− if (cppc_cpufreq_driver.get == hisi_cppc_cpufreq_get_rate)
162		− return;
163		−
164		− if (fie_disabled)
165		− return;
166		−
167		− for_each_cpu(i, policy->cpus) {
168		− cppc_fi = &per_cpu(cppc_freq_inv, i);
169		− cppc_fi->cpu = i;
170		− cppc_fi->cpu_data = cpu_data;
171		− kthread_init_work(&cppc_fi->work, cppc_scale_freq_workfn);
172		− init_irq_work(&cppc_fi->irq_work, cppc_irq_work);
173		−
174		− ret = cppc_get_perf_ctrs(i, &fb_ctrs);
175		− if (ret) {
176		− pr_warn("%s: failed to read perf counters: %d\n",
177		− __func__, ret);
178		− fie_disabled = true;
179		− } else {
180		− cppc_fi->prev_perf_fb_ctrs = fb_ctrs;
181		− }
182		− }
183		−}
184		−
185		−static void __init cppc_freq_invariance_init(void)
186		−{
187		− struct sched_attr attr = {
188		− .size = sizeof(struct sched_attr),
189		− .sched_policy = SCHED_DEADLINE,
190		− .sched_nice = 0,
191		− .sched_priority = 0,
192		− /*
193		− * Fake (unused) bandwidth; workaround to "fix"
194		− * priority inheritance.
195		− */
196		− .sched_runtime = 1000000,
197		− .sched_deadline = 10000000,
198		− .sched_period = 10000000,
199		− };
200		− int ret;
201		−
202		− if (cppc_cpufreq_driver.get == hisi_cppc_cpufreq_get_rate)
203		− return;
204		−
205		− if (fie_disabled)
206		− return;
207		−
208		− kworker_fie = kthread_create_worker(0, "cppc_fie");
209		− if (IS_ERR(kworker_fie))
210		− return;
211		−
212		− ret = sched_setattr_nocheck(kworker_fie->task, &attr);
213		− if (ret) {
214		− pr_warn("%s: failed to set SCHED_DEADLINE: %d\n", __func__,
215		− ret);
216		− kthread_destroy_worker(kworker_fie);
217		− return;
218		− }
219		−
220		− /* Register for freq-invariance */
221		− topology_set_scale_freq_source(&cppc_sftd, cpu_present_mask);
222		−}
223		−
224		−static void cppc_freq_invariance_exit(void)
225		−{
226		− struct cppc_freq_invariance *cppc_fi;
227		− int i;
228		−
229		− if (cppc_cpufreq_driver.get == hisi_cppc_cpufreq_get_rate)
230		− return;
231		−
232		− if (fie_disabled)
233		− return;
234		−
235		− topology_clear_scale_freq_source(SCALE_FREQ_SOURCE_CPPC, cpu_present_mask);
236		−
237		− for_each_possible_cpu(i) {
238		− cppc_fi = &per_cpu(cppc_freq_inv, i);
239		− irq_work_sync(&cppc_fi->irq_work);
240		− }
241		−
242		− kthread_destroy_worker(kworker_fie);
243		− kworker_fie = NULL;
244		−}
245		−
246		−#else
247		−static inline void
248		−cppc_freq_invariance_policy_init(struct cpufreq_policy *policy,
249		− struct cppc_cpudata *cpu_data)
250		−{
251		−}
252		−
253		−static inline void cppc_freq_invariance_init(void)
254		−{
255		−}
256		−
257		−static inline void cppc_freq_invariance_exit(void)
258		−{
259		−}
260		−#endif /* CONFIG_ACPI_CPPC_CPUFREQ_FIE */
261		−
262	60	/* Callback function used to retrieve the max frequency from DMI */
263	61	static void cppc_find_dmi_mhz(const struct dmi_header dm, void private)
264	62	{
@@ -547,12 +345,9 @@ static int cppc_cpufreq_cpu_init(struct cpufreq_policy *policy) · 282 unmodified lines
547	345	cpu_data->perf_ctrls.desired_perf = caps->highest_perf;
548	346
549	347	ret = cppc_set_perf(cpu, &cpu_data->perf_ctrls);
550		− if (ret) {
	348	+ if (ret)
551	349	pr_debug("Err setting perf value:%d on CPU:%d. ret:%d\n",
552	350	caps->highest_perf, cpu, ret);
553		− } else {
554		− cppc_freq_invariance_policy_init(policy, cpu_data);
555		− }
556	351
557	352	return ret;
558	353	}
@@ -565,12 +360,12 @@ static inline u64 get_delta(u64 t1, u64 t0) · 6 unmodified lines
565	360	return (u32)t1 - (u32)t0;
566	361	}
567	362
568		−static int cppc_perf_from_fbctrs(struct cppc_cpudata *cpu_data,
569		− struct cppc_perf_fb_ctrs fb_ctrs_t0,
570		− struct cppc_perf_fb_ctrs fb_ctrs_t1)
	363	+static int cppc_get_rate_from_fbctrs(struct cppc_cpudata *cpu_data,
	364	+ struct cppc_perf_fb_ctrs fb_ctrs_t0,
	365	+ struct cppc_perf_fb_ctrs fb_ctrs_t1)
571	366	{
572	367	u64 delta_reference, delta_delivered;
573		− u64 reference_perf;
	368	+ u64 reference_perf, delivered_perf;
574	369
575	370	reference_perf = fb_ctrs_t0.reference_perf;
576	371
@@ -579,21 +374,12 @@ static int cppc_perf_from_fbctrs(struct cppc_cpudata *cpu_data, · 2 unmodified lines
579	374	delta_delivered = get_delta(fb_ctrs_t1.delivered,
580	375	fb_ctrs_t0.delivered);
581	376
582		− /* Check to avoid divide-by zero and invalid delivered_perf */
583		− if (!delta_reference \|\| !delta_delivered)
584		− return cpu_data->perf_ctrls.desired_perf;
585		−
586		− return (reference_perf * delta_delivered) / delta_reference;
587		−}
588		−
589		−static int cppc_get_rate_from_fbctrs(struct cppc_cpudata *cpu_data,
590		− struct cppc_perf_fb_ctrs fb_ctrs_t0,
591		− struct cppc_perf_fb_ctrs fb_ctrs_t1)
592		−{
593		− u64 delivered_perf;
594		−
595		− delivered_perf = cppc_perf_from_fbctrs(cpu_data, fb_ctrs_t0,
596		− fb_ctrs_t1);
	377	+ /* Check to avoid divide-by zero */
	378	+ if (delta_reference \|\| delta_delivered)
	379	+ delivered_perf = (reference_perf * delta_delivered) /
	380	+ delta_reference;
	381	+ else
	382	+ delivered_perf = cpu_data->perf_ctrls.desired_perf;
597	383
598	384	return cppc_cpufreq_perf_to_khz(cpu_data, delivered_perf);
599	385	}
@@ -718,8 +504,6 @@ static void cppc_check_hisi_workaround(void) · 118 unmodified lines
718	504
719	505	static int __init cppc_cpufreq_init(void)
720	506	{
721		− int ret;
722		−
723	507	if ((acpi_disabled) \|\| !acpi_cpc_valid())
724	508	return -ENODEV;
725	509
@@ -727,11 +511,7 @@ static int __init cppc_cpufreq_init(void) · 1 unmodified line
727	511
728	512	cppc_check_hisi_workaround();
729	513
730		− ret = cpufreq_register_driver(&cppc_cpufreq_driver);
731		− if (!ret)
732		− cppc_freq_invariance_init();
733		−
734		− return ret;
	514	+ return cpufreq_register_driver(&cppc_cpufreq_driver);
735	515	}
736	516
737	517	static inline void free_cpu_data(void)
@@ -748,7 +528,6 @@ static inline void free_cpu_data(void) · 10 unmodified lines
748	528
749	529	static void __exit cppc_cpufreq_exit(void)
750	530	{
751		− cppc_freq_invariance_exit();
752	531	cpufreq_unregister_driver(&cppc_cpufreq_driver);
753	532
754	533	free_cpu_data();

drivers/cpufreq/intel_pstate.c+13−1

@@ -3033,6 +3033,14 @@ static const struct x86_cpu_id hwp_support_ids[] __initconst = { · 3032 unmodified lines
3033	3033	{}
3034	3034	};
3035	3035
	3036	+static bool intel_pstate_hwp_is_enabled(void)
	3037	+{
	3038	+ u64 value;
	3039	+
	3040	+ rdmsrl(MSR_PM_ENABLE, value);
	3041	+ return !!(value & 0x1);
	3042	+}
	3043	+
3036	3044	static int __init intel_pstate_init(void)
3037	3045	{
3038	3046	const struct x86_cpu_id *id;
@@ -3051,8 +3059,12 @@ static int __init intel_pstate_init(void) · 12 unmodified lines
3051	3059	* Avoid enabling HWP for processors without EPP support,
3052	3060	* because that means incomplete HWP implementation which is a
3053	3061	* corner case and supporting it is generally problematic.
	3062	+ *
	3063	+ * If HWP is enabled already, though, there is no choice but to
	3064	+ * deal with it.
3054	3065	*/
3055		− if (!no_hwp && boot_cpu_has(X86_FEATURE_HWP_EPP)) {
	3066	+ if ((!no_hwp && boot_cpu_has(X86_FEATURE_HWP_EPP)) \|\|
	3067	+ intel_pstate_hwp_is_enabled()) {
3056	3068	hwp_active++;
3057	3069	hwp_mode_bdw = id->driver_data;
3058	3070	intel_pstate.attr = hwp_cpufreq_attrs;

drivers/crypto/cavium/nitrox/nitrox_main.c+0−1

@@ -442,7 +442,6 @@ static int nitrox_probe(struct pci_dev *pdev, · 441 unmodified lines
442	442	err = pci_request_mem_regions(pdev, nitrox_driver_name);
443	443	if (err) {
444	444	pci_disable_device(pdev);
445		− dev_err(&pdev->dev, "Failed to request mem regions!\n");
446	445	return err;
447	446	}
448	447	pci_set_master(pdev);

drivers/dma-buf/dma-buf.c+5−5

@@ -760,7 +760,7 @@ dma_buf_dynamic_attach(struct dma_buf dmabuf, struct device dev, · 759 unmodified lines
760	760
761	761	if (dma_buf_is_dynamic(attach->dmabuf)) {
762	762	dma_resv_lock(attach->dmabuf->resv, NULL);
763		− ret = dma_buf_pin(attach);
	763	+ ret = dmabuf->ops->pin(attach);
764	764	if (ret)
765	765	goto err_unlock;
766	766	}
@@ -786,7 +786,7 @@ err_attach: · 19 unmodified lines
786	786
787	787	err_unpin:
788	788	if (dma_buf_is_dynamic(attach->dmabuf))
789		− dma_buf_unpin(attach);
	789	+ dmabuf->ops->unpin(attach);
790	790
791	791	err_unlock:
792	792	if (dma_buf_is_dynamic(attach->dmabuf))
@@ -843,7 +843,7 @@ void dma_buf_detach(struct dma_buf dmabuf, struct dma_buf_attachment attach) · 50 unmodified lines
843	843	__unmap_dma_buf(attach, attach->sgt, attach->dir);
844	844
845	845	if (dma_buf_is_dynamic(attach->dmabuf)) {
846		− dma_buf_unpin(attach);
	846	+ dmabuf->ops->unpin(attach);
847	847	dma_resv_unlock(attach->dmabuf->resv);
848	848	}
849	849	}
@@ -956,7 +956,7 @@ struct sg_table dma_buf_map_attachment(struct dma_buf_attachment attach, · 106 unmodified lines
956	956	if (dma_buf_is_dynamic(attach->dmabuf)) {
957	957	dma_resv_assert_held(attach->dmabuf->resv);
958	958	if (!IS_ENABLED(CONFIG_DMABUF_MOVE_NOTIFY)) {
959		− r = dma_buf_pin(attach);
	959	+ r = attach->dmabuf->ops->pin(attach);
960	960	if (r)
961	961	return ERR_PTR(r);
962	962	}
@@ -968,7 +968,7 @@ struct sg_table dma_buf_map_attachment(struct dma_buf_attachment attach, · 5 unmodified lines
968	968
969	969	if (IS_ERR(sg_table) && dma_buf_is_dynamic(attach->dmabuf) &&
970	970	!IS_ENABLED(CONFIG_DMABUF_MOVE_NOTIFY))
971		− dma_buf_unpin(attach);
	971	+ attach->dmabuf->ops->unpin(attach);
972	972
973	973	if (!IS_ERR(sg_table) && attach->dmabuf->ops->cache_sgt_mapping) {
974	974	attach->sgt = sg_table;

drivers/dma/Kconfig+2−0

@@ -59,6 +59,7 @@ config DMA_OF · 58 unmodified lines
59	59	#devices
60	60	config ALTERA_MSGDMA
61	61	tristate "Altera / Intel mSGDMA Engine"
	62	+ depends on HAS_IOMEM
62	63	select DMA_ENGINE
63	64	help
64	65	Enable support for Altera / Intel mSGDMA controller.
@@ -701,6 +702,7 @@ config XILINX_ZYNQMP_DMA · 636 unmodified lines
701	702
702	703	config XILINX_ZYNQMP_DPDMA
703	704	tristate "Xilinx DPDMA Engine"
	705	+ depends on HAS_IOMEM && OF
704	706	select DMA_ENGINE
705	707	select DMA_VIRTUAL_CHANNELS
706	708	help

drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c+3−0

@@ -332,6 +332,7 @@ static int __cold dpaa2_qdma_setup(struct fsl_mc_device *ls_dev) · 331 unmodified lines
332	332	}
333	333
334	334	if (priv->dpdmai_attr.version.major > DPDMAI_VER_MAJOR) {
	335	+ err = -EINVAL;
335	336	dev_err(dev, "DPDMAI major version mismatch\n"
336	337	"Found %u.%u, supported version is %u.%u\n",
337	338	priv->dpdmai_attr.version.major,
@@ -341,6 +342,7 @@ static int __cold dpaa2_qdma_setup(struct fsl_mc_device *ls_dev) · 3 unmodified lines
341	342	}
342	343
343	344	if (priv->dpdmai_attr.version.minor > DPDMAI_VER_MINOR) {
	345	+ err = -EINVAL;
344	346	dev_err(dev, "DPDMAI minor version mismatch\n"
345	347	"Found %u.%u, supported version is %u.%u\n",
346	348	priv->dpdmai_attr.version.major,
@@ -475,6 +477,7 @@ static int __cold dpaa2_qdma_dpio_setup(struct dpaa2_qdma_priv *priv) · 128 unmodified lines
475	477	ppriv->store =
476	478	dpaa2_io_store_create(DPAA2_QDMA_STORE_SIZE, dev);
477	479	if (!ppriv->store) {
	480	+ err = -ENOMEM;
478	481	dev_err(dev, "dpaa2_io_store_create() failed\n");
479	482	goto err_store;
480	483	}

drivers/dma/idxd/cdev.c+1−0

@@ -110,6 +110,7 @@ static int idxd_cdev_open(struct inode inode, struct file filp) · 109 unmodified lines
110	110	pasid = iommu_sva_get_pasid(sva);
111	111	if (pasid == IOMMU_PASID_INVALID) {
112	112	iommu_sva_unbind_device(sva);
	113	+ rc = -EINVAL;
113	114	goto failed;
114	115	}
115	116

drivers/dma/idxd/init.c+62−5

@@ -168,6 +168,32 @@ static int idxd_setup_interrupts(struct idxd_device *idxd) · 167 unmodified lines
168	168	return rc;
169	169	}
170	170
	171	+static void idxd_cleanup_interrupts(struct idxd_device *idxd)
	172	+{
	173	+ struct pci_dev *pdev = idxd->pdev;
	174	+ struct idxd_irq_entry *irq_entry;
	175	+ int i, msixcnt;
	176	+
	177	+ msixcnt = pci_msix_vec_count(pdev);
	178	+ if (msixcnt <= 0)
	179	+ return;
	180	+
	181	+ irq_entry = &idxd->irq_entries[0];
	182	+ free_irq(irq_entry->vector, irq_entry);
	183	+
	184	+ for (i = 1; i < msixcnt; i++) {
	185	+
	186	+ irq_entry = &idxd->irq_entries[i];
	187	+ if (idxd->hw.cmd_cap & BIT(IDXD_CMD_RELEASE_INT_HANDLE))
	188	+ idxd_device_release_int_handle(idxd, idxd->int_handles[i],
	189	+ IDXD_IRQ_MSIX);
	190	+ free_irq(irq_entry->vector, irq_entry);
	191	+ }
	192	+
	193	+ idxd_mask_error_interrupts(idxd);
	194	+ pci_free_irq_vectors(pdev);
	195	+}
	196	+
171	197	static int idxd_setup_wqs(struct idxd_device *idxd)
172	198	{
173	199	struct device *dev = &idxd->pdev->dev;
@@ -242,6 +268,7 @@ static int idxd_setup_engines(struct idxd_device *idxd) · 68 unmodified lines
242	268	engine->idxd = idxd;
243	269	device_initialize(&engine->conf_dev);
244	270	engine->conf_dev.parent = &idxd->conf_dev;
	271	+ engine->conf_dev.bus = &dsa_bus_type;
245	272	engine->conf_dev.type = &idxd_engine_device_type;
246	273	rc = dev_set_name(&engine->conf_dev, "engine%d.%d", idxd->id, engine->id);
247	274	if (rc < 0) {
@@ -303,6 +330,19 @@ static int idxd_setup_groups(struct idxd_device *idxd) · 55 unmodified lines
303	330	return rc;
304	331	}
305	332
	333	+static void idxd_cleanup_internals(struct idxd_device *idxd)
	334	+{
	335	+ int i;
	336	+
	337	+ for (i = 0; i < idxd->max_groups; i++)
	338	+ put_device(&idxd->groups[i]->conf_dev);
	339	+ for (i = 0; i < idxd->max_engines; i++)
	340	+ put_device(&idxd->engines[i]->conf_dev);
	341	+ for (i = 0; i < idxd->max_wqs; i++)
	342	+ put_device(&idxd->wqs[i]->conf_dev);
	343	+ destroy_workqueue(idxd->wq);
	344	+}
	345	+
306	346	static int idxd_setup_internals(struct idxd_device *idxd)
307	347	{
308	348	struct device *dev = &idxd->pdev->dev;
@@ -531,12 +571,12 @@ static int idxd_probe(struct idxd_device *idxd) · 222 unmodified lines
531	571	dev_dbg(dev, "Loading RO device config\n");
532	572	rc = idxd_device_load_config(idxd);
533	573	if (rc < 0)
534		− goto err;
	574	+ goto err_config;
535	575	}
536	576
537	577	rc = idxd_setup_interrupts(idxd);
538	578	if (rc)
539		− goto err;
	579	+ goto err_config;
540	580
541	581	dev_dbg(dev, "IDXD interrupt setup complete.\n");
542	582
@@ -549,6 +589,8 @@ static int idxd_probe(struct idxd_device *idxd) · 6 unmodified lines
549	589	dev_dbg(dev, "IDXD device %d probed successfully\n", idxd->id);
550	590	return 0;
551	591
	592	+ err_config:
	593	+ idxd_cleanup_internals(idxd);
552	594	err:
553	595	if (device_pasid_enabled(idxd))
554	596	idxd_disable_system_pasid(idxd);
@@ -556,6 +598,18 @@ static int idxd_probe(struct idxd_device *idxd) · 1 unmodified line
556	598	return rc;
557	599	}
558	600
	601	+static void idxd_cleanup(struct idxd_device *idxd)
	602	+{
	603	+ struct device *dev = &idxd->pdev->dev;
	604	+
	605	+ perfmon_pmu_remove(idxd);
	606	+ idxd_cleanup_interrupts(idxd);
	607	+ idxd_cleanup_internals(idxd);
	608	+ if (device_pasid_enabled(idxd))
	609	+ idxd_disable_system_pasid(idxd);
	610	+ iommu_dev_disable_feature(dev, IOMMU_DEV_FEAT_SVA);
	611	+}
	612	+
559	613	static int idxd_pci_probe(struct pci_dev pdev, const struct pci_device_id id)
560	614	{
561	615	struct device *dev = &pdev->dev;
@@ -608,7 +662,7 @@ static int idxd_pci_probe(struct pci_dev pdev, const struct pci_device_id id) · 46 unmodified lines
608	662	rc = idxd_register_devices(idxd);
609	663	if (rc) {
610	664	dev_err(dev, "IDXD sysfs setup failed\n");
611		− goto err;
	665	+ goto err_dev_register;
612	666	}
613	667
614	668	idxd->state = IDXD_DEV_CONF_READY;
@@ -618,6 +672,8 @@ static int idxd_pci_probe(struct pci_dev pdev, const struct pci_device_id id) · 3 unmodified lines
618	672
619	673	return 0;
620	674
	675	+ err_dev_register:
	676	+ idxd_cleanup(idxd);
621	677	err:
622	678	pci_iounmap(pdev, idxd->reg_base);
623	679	err_iomap:
@@ -745,12 +801,12 @@ static int __init idxd_init_module(void) · 121 unmodified lines
745	801	* If the CPU does not support MOVDIR64B or ENQCMDS, there's no point in
746	802	* enumerating the device. We can not utilize it.
747	803	*/
748		− if (!boot_cpu_has(X86_FEATURE_MOVDIR64B)) {
	804	+ if (!cpu_feature_enabled(X86_FEATURE_MOVDIR64B)) {
749	805	pr_warn("idxd driver failed to load without MOVDIR64B.\n");
750	806	return -ENODEV;
751	807	}
752	808
753		− if (!boot_cpu_has(X86_FEATURE_ENQCMD))
	809	+ if (!cpu_feature_enabled(X86_FEATURE_ENQCMD))
754	810	pr_warn("Platform does not have ENQCMD(S) support.\n");
755	811	else
756	812	support_enqcmd = true;
@@ -787,6 +843,7 @@ module_init(idxd_init_module); · 30 unmodified lines
787	843
788	844	static void __exit idxd_exit_module(void)
789	845	{
	846	+ idxd_unregister_driver();
790	847	pci_unregister_driver(&idxd_pci_driver);
791	848	idxd_cdev_remove();
792	849	idxd_unregister_bus_type();

drivers/dma/ipu/ipu_irq.c+1−1

@@ -230,7 +230,7 @@ out: · 229 unmodified lines
230	230	}
231	231
232	232	/**
233		− * ipu_irq_map() - map an IPU interrupt source to an IRQ number
	233	+ * ipu_irq_unmap() - unmap an IPU interrupt source
234	234	* @source: interrupt source bit position (see ipu_irq_map())
235	235	* @return: 0 or negative error code
236	236	*/

drivers/dma/mediatek/mtk-uart-apdma.c+14−13

@@ -131,10 +131,7 @@ static unsigned int mtk_uart_apdma_read(struct mtk_chan *c, unsigned int reg) · 130 unmodified lines
131	131
132	132	static void mtk_uart_apdma_desc_free(struct virt_dma_desc *vd)
133	133	{
134		− struct dma_chan *chan = vd->tx.chan;
135		− struct mtk_chan *c = to_mtk_uart_apdma_chan(chan);
136		−
137		− kfree(c->desc);
	134	+ kfree(container_of(vd, struct mtk_uart_apdma_desc, vd));
138	135	}
139	136
140	137	static void mtk_uart_apdma_start_tx(struct mtk_chan *c)
@@ -207,14 +204,9 @@ static void mtk_uart_apdma_start_rx(struct mtk_chan *c) · 66 unmodified lines
207	204
208	205	static void mtk_uart_apdma_tx_handler(struct mtk_chan *c)
209	206	{
210		− struct mtk_uart_apdma_desc *d = c->desc;
211		−
212	207	mtk_uart_apdma_write(c, VFF_INT_FLAG, VFF_TX_INT_CLR_B);
213	208	mtk_uart_apdma_write(c, VFF_INT_EN, VFF_INT_EN_CLR_B);
214	209	mtk_uart_apdma_write(c, VFF_EN, VFF_EN_CLR_B);
215		−
216		− list_del(&d->vd.node);
217		− vchan_cookie_complete(&d->vd);
218	210	}
219	211
220	212	static void mtk_uart_apdma_rx_handler(struct mtk_chan *c)
@@ -245,9 +237,17 @@ static void mtk_uart_apdma_rx_handler(struct mtk_chan *c) · 24 unmodified lines
245	237
246	238	c->rx_status = d->avail_len - cnt;
247	239	mtk_uart_apdma_write(c, VFF_RPT, wg);
	240	+}
248	241
249		− list_del(&d->vd.node);
250		− vchan_cookie_complete(&d->vd);
	242	+static void mtk_uart_apdma_chan_complete_handler(struct mtk_chan *c)
	243	+{
	244	+ struct mtk_uart_apdma_desc *d = c->desc;
	245	+
	246	+ if (d) {
	247	+ list_del(&d->vd.node);
	248	+ vchan_cookie_complete(&d->vd);
	249	+ c->desc = NULL;
	250	+ }
251	251	}
252	252
253	253	static irqreturn_t mtk_uart_apdma_irq_handler(int irq, void *dev_id)
@@ -261,6 +261,7 @@ static irqreturn_t mtk_uart_apdma_irq_handler(int irq, void *dev_id) · 7 unmodified lines
261	261	mtk_uart_apdma_rx_handler(c);
262	262	else if (c->dir == DMA_MEM_TO_DEV)
263	263	mtk_uart_apdma_tx_handler(c);
	264	+ mtk_uart_apdma_chan_complete_handler(c);
264	265	spin_unlock_irqrestore(&c->vc.lock, flags);
265	266
266	267	return IRQ_HANDLED;
@@ -348,7 +349,7 @@ static struct dma_async_tx_descriptor *mtk_uart_apdma_prep_slave_sg · 81 unmodified lines
348	349	return NULL;
349	350
350	351	/* Now allocate and setup the descriptor */
351		− d = kzalloc(sizeof(*d), GFP_ATOMIC);
	352	+ d = kzalloc(sizeof(*d), GFP_NOWAIT);
352	353	if (!d)
353	354	return NULL;
354	355
@@ -366,7 +367,7 @@ static void mtk_uart_apdma_issue_pending(struct dma_chan *chan) · 11 unmodified lines
366	367	unsigned long flags;
367	368
368	369	spin_lock_irqsave(&c->vc.lock, flags);
369		− if (vchan_issue_pending(&c->vc)) {
	370	+ if (vchan_issue_pending(&c->vc) && !c->desc) {
370	371	vd = vchan_next_desc(&c->vc);
371	372	c->desc = to_mtk_uart_apdma_desc(&vd->tx);
372	373

drivers/dma/pl330.c+4−2

@@ -2694,13 +2694,15 @@ static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic( · 2693 unmodified lines
2694	2694	for (i = 0; i < len / period_len; i++) {
2695	2695	desc = pl330_get_desc(pch);
2696	2696	if (!desc) {
	2697	+ unsigned long iflags;
	2698	+
2697	2699	dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
2698	2700	__func__, __LINE__);
2699	2701
2700	2702	if (!first)
2701	2703	return NULL;
2702	2704
2703		− spin_lock_irqsave(&pl330->pool_lock, flags);
	2705	+ spin_lock_irqsave(&pl330->pool_lock, iflags);
2704	2706
2705	2707	while (!list_empty(&first->node)) {
2706	2708	desc = list_entry(first->node.next,
@@ -2710,7 +2712,7 @@ static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic( · 3 unmodified lines
2710	2712
2711	2713	list_move_tail(&first->node, &pl330->desc_pool);
2712	2714
2713		− spin_unlock_irqrestore(&pl330->pool_lock, flags);
	2715	+ spin_unlock_irqrestore(&pl330->pool_lock, iflags);
2714	2716
2715	2717	return NULL;
2716	2718	}

drivers/dma/qcom/Kconfig+1−0

@@ -33,6 +33,7 @@ config QCOM_GPI_DMA · 32 unmodified lines
33	33
34	34	config QCOM_HIDMA_MGMT
35	35	tristate "Qualcomm Technologies HIDMA Management support"
	36	+ depends on HAS_IOMEM
36	37	select DMA_ENGINE
37	38	help
38	39	Enable support for the Qualcomm Technologies HIDMA Management.

drivers/dma/qcom/hidma_mgmt.c+16−1

@@ -418,8 +418,23 @@ static int __init hidma_mgmt_init(void) · 417 unmodified lines
418	418	hidma_mgmt_of_populate_channels(child);
419	419	}
420	420	#endif
421		− return platform_driver_register(&hidma_mgmt_driver);
	421	+ /*
	422	+ * We do not check for return value here, as it is assumed that
	423	+ * platform_driver_register must not fail. The reason for this is that
	424	+ * the (potential) hidma_mgmt_of_populate_channels calls above are not
	425	+ * cleaned up if it does fail, and to do this work is quite
	426	+ * complicated. In particular, various calls of of_address_to_resource,
	427	+ * of_irq_to_resource, platform_device_register_full, of_dma_configure,
	428	+ * and of_msi_configure which then call other functions and so on, must
	429	+ * be cleaned up - this is not a trivial exercise.
	430	+ *
	431	+ * Currently, this module is not intended to be unloaded, and there is
	432	+ * no module_exit function defined which does the needed cleanup. For
	433	+ * this reason, we have to assume success here.
	434	+ */
	435	+ platform_driver_register(&hidma_mgmt_driver);
422	436
	437	+ return 0;
423	438	}
424	439	module_init(hidma_mgmt_init);
425	440	MODULE_LICENSE("GPL v2");

drivers/dma/sf-pdma/Kconfig+1−0

@@ -1,5 +1,6 @@
1	1	config SF_PDMA
2	2	tristate "Sifive PDMA controller driver"
	3	+ depends on HAS_IOMEM
3	4	select DMA_ENGINE
4	5	select DMA_VIRTUAL_CHANNELS
5	6	help

drivers/dma/sh/rcar-dmac.c+1−1

@@ -1913,7 +1913,7 @@ static int rcar_dmac_probe(struct platform_device *pdev) · 1912 unmodified lines
1913	1913
1914	1914	/* Enable runtime PM and initialize the device. */
1915	1915	pm_runtime_enable(&pdev->dev);
1916		− ret = pm_runtime_get_sync(&pdev->dev);
	1916	+ ret = pm_runtime_resume_and_get(&pdev->dev);
1917	1917	if (ret < 0) {
1918	1918	dev_err(&pdev->dev, "runtime PM get sync failed (%d)\n", ret);
1919	1919	return ret;

drivers/dma/ste_dma40.c+3−0

@@ -3675,6 +3675,9 @@ static int __init d40_probe(struct platform_device *pdev) · 3674 unmodified lines
3675	3675
3676	3676	kfree(base->lcla_pool.base_unaligned);
3677	3677
	3678	+ if (base->lcpa_base)
	3679	+ iounmap(base->lcpa_base);
	3680	+
3678	3681	if (base->phy_lcpa)
3679	3682	release_mem_region(base->phy_lcpa,
3680	3683	base->lcpa_size);

drivers/dma/stm32-mdma.c+2−2

@@ -1452,7 +1452,7 @@ static int stm32_mdma_alloc_chan_resources(struct dma_chan *c) · 1451 unmodified lines
1452	1452	return -ENOMEM;
1453	1453	}
1454	1454
1455		− ret = pm_runtime_get_sync(dmadev->ddev.dev);
	1455	+ ret = pm_runtime_resume_and_get(dmadev->ddev.dev);
1456	1456	if (ret < 0)
1457	1457	return ret;
1458	1458
@@ -1718,7 +1718,7 @@ static int stm32_mdma_pm_suspend(struct device *dev) · 259 unmodified lines
1718	1718	u32 ccr, id;
1719	1719	int ret;
1720	1720
1721		− ret = pm_runtime_get_sync(dev);
	1721	+ ret = pm_runtime_resume_and_get(dev);
1722	1722	if (ret < 0)
1723	1723	return ret;
1724	1724

drivers/dma/xilinx/xilinx_dpdma.c+28−3

@@ -113,6 +113,7 @@ · 112 unmodified lines
113	113	#define XILINX_DPDMA_CH_VDO 0x020
114	114	#define XILINX_DPDMA_CH_PYLD_SZ 0x024
115	115	#define XILINX_DPDMA_CH_DESC_ID 0x028
	116	+#define XILINX_DPDMA_CH_DESC_ID_MASK GENMASK(15, 0)
116	117
117	118	/* DPDMA descriptor fields */
118	119	#define XILINX_DPDMA_DESC_CONTROL_PREEMBLE 0xa5
@@ -866,7 +867,8 @@ static void xilinx_dpdma_chan_queue_transfer(struct xilinx_dpdma_chan *chan) · 747 unmodified lines
866	867	* will be used, but it should be enough.
867	868	*/
868	869	list_for_each_entry(sw_desc, &desc->descriptors, node)
869		− sw_desc->hw.desc_id = desc->vdesc.tx.cookie;
	870	+ sw_desc->hw.desc_id = desc->vdesc.tx.cookie
	871	+ & XILINX_DPDMA_CH_DESC_ID_MASK;
870	872
871	873	sw_desc = list_first_entry(&desc->descriptors,
872	874	struct xilinx_dpdma_sw_desc, node);
@@ -1086,7 +1088,8 @@ static void xilinx_dpdma_chan_vsync_irq(struct xilinx_dpdma_chan *chan) · 213 unmodified lines
1086	1088	if (!chan->running \|\| !pending)
1087	1089	goto out;
1088	1090
1089		− desc_id = dpdma_read(chan->reg, XILINX_DPDMA_CH_DESC_ID);
	1091	+ desc_id = dpdma_read(chan->reg, XILINX_DPDMA_CH_DESC_ID)
	1092	+ & XILINX_DPDMA_CH_DESC_ID_MASK;
1090	1093
1091	1094	/* If the retrigger raced with vsync, retry at the next frame. */
1092	1095	sw_desc = list_first_entry(&pending->descriptors,
@@ -1459,7 +1462,7 @@ static void xilinx_dpdma_enable_irq(struct xilinx_dpdma_device *xdev) · 366 unmodified lines
1459	1462	*/
1460	1463	static void xilinx_dpdma_disable_irq(struct xilinx_dpdma_device *xdev)
1461	1464	{
1462		− dpdma_write(xdev->reg, XILINX_DPDMA_IDS, XILINX_DPDMA_INTR_ERR_ALL);
	1465	+ dpdma_write(xdev->reg, XILINX_DPDMA_IDS, XILINX_DPDMA_INTR_ALL);
1463	1466	dpdma_write(xdev->reg, XILINX_DPDMA_EIDS, XILINX_DPDMA_EINTR_ALL);
1464	1467	}
1465	1468
@@ -1596,6 +1599,26 @@ static struct dma_chan of_dma_xilinx_xlate(struct of_phandle_args dma_spec, · 130 unmodified lines
1596	1599	return dma_get_slave_channel(&xdev->chan[chan_id]->vchan.chan);
1597	1600	}
1598	1601
	1602	+static void dpdma_hw_init(struct xilinx_dpdma_device *xdev)
	1603	+{
	1604	+ unsigned int i;
	1605	+ void __iomem *reg;
	1606	+
	1607	+ /* Disable all interrupts */
	1608	+ xilinx_dpdma_disable_irq(xdev);
	1609	+
	1610	+ /* Stop all channels */
	1611	+ for (i = 0; i < ARRAY_SIZE(xdev->chan); i++) {
	1612	+ reg = xdev->reg + XILINX_DPDMA_CH_BASE
	1613	+ + XILINX_DPDMA_CH_OFFSET * i;
	1614	+ dpdma_clr(reg, XILINX_DPDMA_CH_CNTL, XILINX_DPDMA_CH_CNTL_ENABLE);
	1615	+ }
	1616	+
	1617	+ /* Clear the interrupt status registers */
	1618	+ dpdma_write(xdev->reg, XILINX_DPDMA_ISR, XILINX_DPDMA_INTR_ALL);
	1619	+ dpdma_write(xdev->reg, XILINX_DPDMA_EISR, XILINX_DPDMA_EINTR_ALL);
	1620	+}
	1621	+
1599	1622	static int xilinx_dpdma_probe(struct platform_device *pdev)
1600	1623	{
1601	1624	struct xilinx_dpdma_device *xdev;
@@ -1622,6 +1645,8 @@ static int xilinx_dpdma_probe(struct platform_device *pdev) · 20 unmodified lines
1622	1645	if (IS_ERR(xdev->reg))
1623	1646	return PTR_ERR(xdev->reg);
1624	1647
	1648	+ dpdma_hw_init(xdev);
	1649	+
1625	1650	xdev->irq = platform_get_irq(pdev, 0);
1626	1651	if (xdev->irq < 0) {
1627	1652	dev_err(xdev->dev, "failed to get platform irq\n");

drivers/dma/xilinx/zynqmp_dma.c+1−1

@@ -468,7 +468,7 @@ static int zynqmp_dma_alloc_chan_resources(struct dma_chan *dchan) · 467 unmodified lines
468	468	struct zynqmp_dma_desc_sw *desc;
469	469	int i, ret;
470	470
471		− ret = pm_runtime_get_sync(chan->dev);
	471	+ ret = pm_runtime_resume_and_get(chan->dev);
472	472	if (ret < 0)
473	473	return ret;
474	474

drivers/edac/amd64_edac.c+1−1

@@ -3083,7 +3083,7 @@ static void read_mc_regs(struct amd64_pvt *pvt) · 3082 unmodified lines
3083	3083	edac_dbg(0, " TOP_MEM: 0x%016llx\n", pvt->top_mem);
3084	3084
3085	3085	/* Check first whether TOP_MEM2 is enabled: */
3086		− rdmsrl(MSR_K8_SYSCFG, msr_val);
	3086	+ rdmsrl(MSR_AMD64_SYSCFG, msr_val);
3087	3087	if (msr_val & BIT(21)) {
3088	3088	rdmsrl(MSR_K8_TOP_MEM2, pvt->top_mem2);
3089	3089	edac_dbg(0, " TOP_MEM2: 0x%016llx\n", pvt->top_mem2);

drivers/firmware/arm_scmi/notify.h+0−2

@@ -79,8 +79,6 @@ struct scmi_protocol_events { · 78 unmodified lines
79	79
80	80	int scmi_notification_init(struct scmi_handle *handle);
81	81	void scmi_notification_exit(struct scmi_handle *handle);
82		−
83		−struct scmi_protocol_handle;
84	82	int scmi_register_protocol_events(const struct scmi_handle *handle, u8 proto_id,
85	83	const struct scmi_protocol_handle *ph,
86	84	const struct scmi_protocol_events *ee);

drivers/firmware/arm_scpi.c+3−1

@@ -552,8 +552,10 @@ static unsigned long scpi_clk_get_val(u16 clk_id) · 551 unmodified lines
552	552
553	553	ret = scpi_send_message(CMD_GET_CLOCK_VALUE, &le_clk_id,
554	554	sizeof(le_clk_id), &rate, sizeof(rate));
	555	+ if (ret)
	556	+ return 0;
555	557
556		− return ret ? ret : le32_to_cpu(rate);
	558	+ return le32_to_cpu(rate);
557	559	}
558	560
559	561	static int scpi_clk_set_val(u16 clk_id, unsigned long rate)

drivers/firmware/efi/cper.c+1−3

@@ -276,8 +276,7 @@ static int cper_dimm_err_location(struct cper_mem_err_compact mem, char msg) · 275 unmodified lines
276	276	if (!msg \|\| !(mem->validation_bits & CPER_MEM_VALID_MODULE_HANDLE))
277	277	return 0;
278	278
279		− n = 0;
280		− len = CPER_REC_LEN - 1;
	279	+ len = CPER_REC_LEN;
281	280	dmi_memdev_name(mem->mem_dev_handle, &bank, &device);
282	281	if (bank && device)
283	282	n = snprintf(msg, len, "DIMM location: %s %s ", bank, device);
@@ -286,7 +285,6 @@ static int cper_dimm_err_location(struct cper_mem_err_compact mem, char msg) · 2 unmodified lines
286	285	"DIMM location: not present. DMI handle: 0x%.4x ",
287	286	mem->mem_dev_handle);
288	287
289		− msg[n] = '\0';
290	288	return n;
291	289	}
292	290

drivers/firmware/efi/fdtparams.c+3−0

@@ -98,6 +98,9 @@ u64 __init efi_get_fdt_params(struct efi_memory_map_data *mm) · 97 unmodified lines
98	98	BUILD_BUG_ON(ARRAY_SIZE(target) != ARRAY_SIZE(name));
99	99	BUILD_BUG_ON(ARRAY_SIZE(target) != ARRAY_SIZE(dt_params[0].params));
100	100
	101	+ if (!fdt)
	102	+ return 0;
	103	+
101	104	for (i = 0; i < ARRAY_SIZE(dt_params); i++) {
102	105	node = fdt_path_offset(fdt, dt_params[i].path);
103	106	if (node < 0)

drivers/firmware/efi/libstub/file.c+1−1

@@ -103,7 +103,7 @@ static int find_file_option(const efi_char16_t *cmdline, int cmdline_len, · 102 unmodified lines
103	103	return 0;
104	104
105	105	/* Skip any leading slashes */
106		− while (cmdline[i] == L'/' \|\| cmdline[i] == L'\\')
	106	+ while (i < cmdline_len && (cmdline[i] == L'/' \|\| cmdline[i] == L'\\'))
107	107	i++;
108	108
109	109	while (--result_len > 0 && i < cmdline_len) {

drivers/firmware/efi/memattr.c+0−5

@@ -67,11 +67,6 @@ static bool entry_is_valid(const efi_memory_desc_t in, efi_memory_desc_t out) · 66 unmodified lines
67	67	return false;
68	68	}
69	69
70		− if (!(in->attribute & (EFI_MEMORY_RO \| EFI_MEMORY_XP))) {
71		− pr_warn("Entry attributes invalid: RO and XP bits both cleared\n");
72		− return false;
73		− }
74		−
75	70	if (PAGE_SIZE > EFI_PAGE_SIZE &&
76	71	(!PAGE_ALIGNED(in->phys_addr) \|\|
77	72	!PAGE_ALIGNED(in->num_pages << EFI_PAGE_SHIFT))) {

drivers/gpio/gpio-cadence.c+1−0

@@ -278,6 +278,7 @@ static const struct of_device_id cdns_of_ids[] = { · 277 unmodified lines
278	278	{ .compatible = "cdns,gpio-r1p02" },
279	279	{ /* sentinel */ },
280	280	};
	281	+MODULE_DEVICE_TABLE(of, cdns_of_ids);
281	282
282	283	static struct platform_driver cdns_gpio_driver = {
283	284	.driver = {

drivers/gpio/gpio-tegra186.c+0−11

@@ -444,16 +444,6 @@ static int tegra186_irq_set_wake(struct irq_data *data, unsigned int on) · 443 unmodified lines
444	444	return 0;
445	445	}
446	446
447		−static int tegra186_irq_set_affinity(struct irq_data *data,
448		− const struct cpumask *dest,
449		− bool force)
450		−{
451		− if (data->parent_data)
452		− return irq_chip_set_affinity_parent(data, dest, force);
453		−
454		− return -EINVAL;
455		−}
456		−
457	447	static void tegra186_gpio_irq(struct irq_desc *desc)
458	448	{
459	449	struct tegra_gpio *gpio = irq_desc_get_handler_data(desc);
@@ -700,7 +690,6 @@ static int tegra186_gpio_probe(struct platform_device *pdev) · 240 unmodified lines
700	690	gpio->intc.irq_unmask = tegra186_irq_unmask;
701	691	gpio->intc.irq_set_type = tegra186_irq_set_type;
702	692	gpio->intc.irq_set_wake = tegra186_irq_set_wake;
703		− gpio->intc.irq_set_affinity = tegra186_irq_set_affinity;
704	693
705	694	irq = &gpio->gpio.irq;
706	695	irq->chip = &gpio->intc;

drivers/gpio/gpio-wcd934x.c+1−1

@@ -7,7 +7,7 @@ · 6 unmodified lines
7	7	#include <linux/slab.h>
8	8	#include <linux/of_device.h>
9	9
10		−#define WCD_PIN_MASK(p) BIT(p - 1)
	10	+#define WCD_PIN_MASK(p) BIT(p)
11	11	#define WCD_REG_DIR_CTL_OFFSET 0x42
12	12	#define WCD_REG_VAL_CTL_OFFSET 0x43
13	13	#define WCD934X_NPINS 5

drivers/gpio/gpio-xilinx.c+1−1

@@ -542,7 +542,7 @@ static void xgpio_irqhandler(struct irq_desc *desc) · 541 unmodified lines
542	542	}
543	543
544	544	/**
545		− * xgpio_of_probe - Probe method for the GPIO device.
	545	+ * xgpio_probe - Probe method for the GPIO device.
546	546	* @pdev: pointer to the platform device
547	547	*
548	548	* Return:

drivers/gpu/drm/amd/amdgpu/amdgpu.h+1−0

@@ -1006,6 +1006,7 @@ struct amdgpu_device { · 1005 unmodified lines
1006	1006	struct amdgpu_df df;
1007	1007
1008	1008	struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
	1009	+ uint32_t harvest_ip_mask;
1009	1010	int num_ip_blocks;
1010	1011	struct mutex mn_lock;
1011	1012	DECLARE_HASHTABLE(mn_hash, 7);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c+6−6

@@ -156,16 +156,16 @@ static uint32_t get_sdma_rlc_reg_offset(struct amdgpu_device *adev, · 155 unmodified lines
156	156	mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;
157	157	break;
158	158	case 1:
159		− sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA1, 0,
	159	+ sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,
160	160	mmSDMA1_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;
161	161	break;
162	162	case 2:
163		− sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA2, 0,
164		− mmSDMA2_RLC0_RB_CNTL) - mmSDMA2_RLC0_RB_CNTL;
	163	+ sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,
	164	+ mmSDMA2_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;
165	165	break;
166	166	case 3:
167		− sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA3, 0,
168		− mmSDMA3_RLC0_RB_CNTL) - mmSDMA2_RLC0_RB_CNTL;
	167	+ sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,
	168	+ mmSDMA3_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;
169	169	break;
170	170	}
171	171
@@ -450,7 +450,7 @@ static int hqd_sdma_dump_v10_3(struct kgd_dev *kgd, · 278 unmodified lines
450	450	engine_id, queue_id);
451	451	uint32_t i = 0, reg;
452	452	#undef HQD_N_REGS
453		−#define HQD_N_REGS (19+6+7+10)
	453	+#define HQD_N_REGS (19+6+7+12)
454	454
455	455	dump = kmalloc(HQD_N_REGS2*sizeof(uint32_t), GFP_KERNEL);
456	456	if (*dump == NULL)

drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c+0−16

@@ -337,7 +337,6 @@ static int amdgpu_ctx_query2(struct amdgpu_device *adev, · 336 unmodified lines
337	337	{
338	338	struct amdgpu_ctx *ctx;
339	339	struct amdgpu_ctx_mgr *mgr;
340		− unsigned long ras_counter;
341	340
342	341	if (!fpriv)
343	342	return -EINVAL;
@@ -362,21 +361,6 @@ static int amdgpu_ctx_query2(struct amdgpu_device *adev, · 18 unmodified lines
362	361	if (atomic_read(&ctx->guilty))
363	362	out->state.flags \|= AMDGPU_CTX_QUERY2_FLAGS_GUILTY;
364	363
365		− /query ue count/
366		− ras_counter = amdgpu_ras_query_error_count(adev, false);
367		− /ras counter is monotonic increasing/
368		− if (ras_counter != ctx->ras_counter_ue) {
369		− out->state.flags \|= AMDGPU_CTX_QUERY2_FLAGS_RAS_UE;
370		− ctx->ras_counter_ue = ras_counter;
371		− }
372		−
373		− /query ce count/
374		− ras_counter = amdgpu_ras_query_error_count(adev, true);
375		− if (ras_counter != ctx->ras_counter_ce) {
376		− out->state.flags \|= AMDGPU_CTX_QUERY2_FLAGS_RAS_CE;
377		− ctx->ras_counter_ce = ras_counter;
378		− }
379		−
380	364	mutex_unlock(&mgr->lock);
381	365	return 0;
382	366	}

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c+17−3

@@ -1683,6 +1683,19 @@ int amdgpu_device_ip_block_add(struct amdgpu_device *adev, · 1682 unmodified lines
1683	1683	if (!ip_block_version)
1684	1684	return -EINVAL;
1685	1685
	1686	+ switch (ip_block_version->type) {
	1687	+ case AMD_IP_BLOCK_TYPE_VCN:
	1688	+ if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK)
	1689	+ return 0;
	1690	+ break;
	1691	+ case AMD_IP_BLOCK_TYPE_JPEG:
	1692	+ if (adev->harvest_ip_mask & AMD_HARVEST_IP_JPEG_MASK)
	1693	+ return 0;
	1694	+ break;
	1695	+ default:
	1696	+ break;
	1697	+ }
	1698	+
1686	1699	DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks,
1687	1700	ip_block_version->funcs->name);
1688	1701
@@ -3105,13 +3118,14 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type) · 1416 unmodified lines
3105	3118	*/
3106	3119	bool amdgpu_device_has_dc_support(struct amdgpu_device *adev)
3107	3120	{
3108		− if (amdgpu_sriov_vf(adev) \|\| adev->enable_virtual_display)
	3121	+ if (amdgpu_sriov_vf(adev) \|\|
	3122	+ adev->enable_virtual_display \|\|
	3123	+ (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK))
3109	3124	return false;
3110	3125
3111	3126	return amdgpu_device_asic_has_dc_support(adev->asic_type);
3112	3127	}
3113	3128
3114		−
3115	3129	static void amdgpu_device_xgmi_reset_func(struct work_struct *__work)
3116	3130	{
3117	3131	struct amdgpu_device *adev =
@@ -3276,6 +3290,7 @@ int amdgpu_device_init(struct amdgpu_device *adev, · 158 unmodified lines
3276	3290	adev->vm_manager.vm_pte_funcs = NULL;
3277	3291	adev->vm_manager.vm_pte_num_scheds = 0;
3278	3292	adev->gmc.gmc_funcs = NULL;
	3293	+ adev->harvest_ip_mask = 0x0;
3279	3294	adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
3280	3295	bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
3281	3296
@@ -4466,7 +4481,6 @@ out: · 1184 unmodified lines
4466	4481	r = amdgpu_ib_ring_tests(tmp_adev);
4467	4482	if (r) {
4468	4483	dev_err(tmp_adev->dev, "ib ring test failed (%d).\n", r);
4469		− r = amdgpu_device_ip_suspend(tmp_adev);
4470	4484	need_full_reset = true;
4471	4485	r = -EAGAIN;
4472	4486	goto end;

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c+28−0

@@ -373,6 +373,34 @@ int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id, · 372 unmodified lines
373	373	return -EINVAL;
374	374	}
375	375
	376	+void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev)
	377	+{
	378	+ struct binary_header *bhdr;
	379	+ struct harvest_table *harvest_info;
	380	+ int i;
	381	+
	382	+ bhdr = (struct binary_header *)adev->mman.discovery_bin;
	383	+ harvest_info = (struct harvest_table *)(adev->mman.discovery_bin +
	384	+ le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset));
	385	+
	386	+ for (i = 0; i < 32; i++) {
	387	+ if (le32_to_cpu(harvest_info->list[i].hw_id) == 0)
	388	+ break;
	389	+
	390	+ switch (le32_to_cpu(harvest_info->list[i].hw_id)) {
	391	+ case VCN_HWID:
	392	+ adev->harvest_ip_mask \|= AMD_HARVEST_IP_VCN_MASK;
	393	+ adev->harvest_ip_mask \|= AMD_HARVEST_IP_JPEG_MASK;
	394	+ break;
	395	+ case DMU_HWID:
	396	+ adev->harvest_ip_mask \|= AMD_HARVEST_IP_DMU_MASK;
	397	+ break;
	398	+ default:
	399	+ break;
	400	+ }
	401	+ }
	402	+}
	403	+
376	404	int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)
377	405	{
378	406	struct binary_header *bhdr;

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h+1−0

@@ -29,6 +29,7 @@ · 28 unmodified lines
29	29
30	30	void amdgpu_discovery_fini(struct amdgpu_device *adev);
31	31	int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev);
	32	+void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev);
32	33	int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id,
33	34	int major, int minor, int *revision);
34	35	int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev);

drivers/gpu/drm/amd/amdgpu/amdgpu_display.c+2−2

@@ -1057,7 +1057,7 @@ int amdgpu_display_gem_fb_init(struct drm_device *dev, · 1056 unmodified lines
1057	1057
1058	1058	return 0;
1059	1059	err:
1060		− drm_err(dev, "Failed to init gem fb: %d\n", ret);
	1060	+ drm_dbg_kms(dev, "Failed to init gem fb: %d\n", ret);
1061	1061	rfb->base.obj[0] = NULL;
1062	1062	return ret;
1063	1063	}
@@ -1094,7 +1094,7 @@ int amdgpu_display_gem_fb_verify_and_init( · 30 unmodified lines
1094	1094
1095	1095	return 0;
1096	1096	err:
1097		− drm_err(dev, "Failed to verify and init gem fb: %d\n", ret);
	1097	+ drm_dbg_kms(dev, "Failed to verify and init gem fb: %d\n", ret);
1098	1098	rfb->base.obj[0] = NULL;
1099	1099	return ret;
1100	1100	}

drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c+3−0

@@ -288,10 +288,13 @@ out: · 287 unmodified lines
288	288	static int amdgpu_fbdev_destroy(struct drm_device dev, struct amdgpu_fbdev rfbdev)
289	289	{
290	290	struct amdgpu_framebuffer *rfb = &rfbdev->rfb;
	291	+ int i;
291	292
292	293	drm_fb_helper_unregister_fbi(&rfbdev->helper);
293	294
294	295	if (rfb->base.obj[0]) {
	296	+ for (i = 0; i < rfb->base.format->num_planes; i++)
	297	+ drm_gem_object_put(rfb->base.obj[0]);
295	298	amdgpufb_destroy_pinned_object(rfb->base.obj[0]);
296	299	rfb->base.obj[0] = NULL;
297	300	drm_framebuffer_unregister_private(&rfb->base);

drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c+23−19

@@ -101,7 +101,8 @@ static int amdgpu_fru_read_eeprom(struct amdgpu_device *adev, uint32_t addrptr, · 100 unmodified lines
101	101	int amdgpu_fru_get_product_info(struct amdgpu_device *adev)
102	102	{
103	103	unsigned char buff[34];
104		− int addrptr = 0, size = 0;
	104	+ int addrptr, size;
	105	+ int len;
105	106
106	107	if (!is_fru_eeprom_supported(adev))
107	108	return 0;
@@ -109,7 +110,7 @@ int amdgpu_fru_get_product_info(struct amdgpu_device *adev) · 1 unmodified line
109	110	/* If algo exists, it means that the i2c_adapter's initialized */
110	111	if (!adev->pm.smu_i2c.algo) {
111	112	DRM_WARN("Cannot access FRU, EEPROM accessor not initialized");
112		− return 0;
	113	+ return -ENODEV;
113	114	}
114	115
115	116	/* There's a lot of repetition here. This is due to the FRU having
@@ -128,7 +129,7 @@ int amdgpu_fru_get_product_info(struct amdgpu_device *adev) · 12 unmodified lines
128	129	size = amdgpu_fru_read_eeprom(adev, addrptr, buff);
129	130	if (size < 1) {
130	131	DRM_ERROR("Failed to read FRU Manufacturer, ret:%d", size);
131		− return size;
	132	+ return -EINVAL;
132	133	}
133	134
134	135	/* Increment the addrptr by the size of the field, and 1 due to the
@@ -138,43 +139,45 @@ int amdgpu_fru_get_product_info(struct amdgpu_device *adev) · 3 unmodified lines
138	139	size = amdgpu_fru_read_eeprom(adev, addrptr, buff);
139	140	if (size < 1) {
140	141	DRM_ERROR("Failed to read FRU product name, ret:%d", size);
141		− return size;
	142	+ return -EINVAL;
142	143	}
143	144
	145	+ len = size;
144	146	/* Product name should only be 32 characters. Any more,
145	147	* and something could be wrong. Cap it at 32 to be safe
146	148	*/
147		− if (size > 32) {
	149	+ if (len >= sizeof(adev->product_name)) {
148	150	DRM_WARN("FRU Product Number is larger than 32 characters. This is likely a mistake");
149		− size = 32;
	151	+ len = sizeof(adev->product_name) - 1;
150	152	}
151	153	/* Start at 2 due to buff using fields 0 and 1 for the address */
152		− memcpy(adev->product_name, &buff[2], size);
153		− adev->product_name[size] = '\0';
	154	+ memcpy(adev->product_name, &buff[2], len);
	155	+ adev->product_name[len] = '\0';
154	156
155	157	addrptr += size + 1;
156	158	size = amdgpu_fru_read_eeprom(adev, addrptr, buff);
157	159	if (size < 1) {
158	160	DRM_ERROR("Failed to read FRU product number, ret:%d", size);
159		− return size;
	161	+ return -EINVAL;
160	162	}
161	163
	164	+ len = size;
162	165	/* Product number should only be 16 characters. Any more,
163	166	* and something could be wrong. Cap it at 16 to be safe
164	167	*/
165		− if (size > 16) {
	168	+ if (len >= sizeof(adev->product_number)) {
166	169	DRM_WARN("FRU Product Number is larger than 16 characters. This is likely a mistake");
167		− size = 16;
	170	+ len = sizeof(adev->product_number) - 1;
168	171	}
169		− memcpy(adev->product_number, &buff[2], size);
170		− adev->product_number[size] = '\0';
	172	+ memcpy(adev->product_number, &buff[2], len);
	173	+ adev->product_number[len] = '\0';
171	174
172	175	addrptr += size + 1;
173	176	size = amdgpu_fru_read_eeprom(adev, addrptr, buff);
174	177
175	178	if (size < 1) {
176	179	DRM_ERROR("Failed to read FRU product version, ret:%d", size);
177		− return size;
	180	+ return -EINVAL;
178	181	}
179	182
180	183	addrptr += size + 1;
@@ -182,18 +185,19 @@ int amdgpu_fru_get_product_info(struct amdgpu_device *adev) · 1 unmodified line
182	185
183	186	if (size < 1) {
184	187	DRM_ERROR("Failed to read FRU serial number, ret:%d", size);
185		− return size;
	188	+ return -EINVAL;
186	189	}
187	190
	191	+ len = size;
188	192	/* Serial number should only be 16 characters. Any more,
189	193	* and something could be wrong. Cap it at 16 to be safe
190	194	*/
191		− if (size > 16) {
	195	+ if (len >= sizeof(adev->serial)) {
192	196	DRM_WARN("FRU Serial Number is larger than 16 characters. This is likely a mistake");
193		− size = 16;
	197	+ len = sizeof(adev->serial) - 1;
194	198	}
195		− memcpy(adev->serial, &buff[2], size);
196		− adev->serial[size] = '\0';
	199	+ memcpy(adev->serial, &buff[2], len);
	200	+ adev->serial[len] = '\0';
197	201
198	202	return 0;
199	203	}

drivers/gpu/drm/amd/amdgpu/amdgpu_object.c+2−2

@@ -100,7 +100,7 @@ static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo) · 99 unmodified lines
100	100	kfree(ubo->metadata);
101	101	}
102	102
103		− kfree(bo);
	103	+ kvfree(bo);
104	104	}
105	105
106	106	/**
@@ -552,7 +552,7 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev, · 445 unmodified lines
552	552	BUG_ON(bp->bo_ptr_size < sizeof(struct amdgpu_bo));
553	553
554	554	*bo_ptr = NULL;
555		− bo = kzalloc(bp->bo_ptr_size, GFP_KERNEL);
	555	+ bo = kvzalloc(bp->bo_ptr_size, GFP_KERNEL);
556	556	if (bo == NULL)
557	557	return -ENOMEM;
558	558	drm_gem_private_object_init(adev_to_drm(adev), &bo->tbo.base, size);

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h+1−0

@@ -76,6 +76,7 @@ struct psp_ring · 75 unmodified lines
76	76	uint64_t ring_mem_mc_addr;
77	77	void *ring_mem_handle;
78	78	uint32_t ring_size;
	79	+ uint32_t ring_wptr;
79	80	};
80	81
81	82	/* More registers may will be supported */

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c+2−1

@@ -225,7 +225,7 @@ static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo, · 224 unmodified lines
225	225	*addr += mm_cur->start & ~PAGE_MASK;
226	226
227	227	num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
228		− num_bytes = num_pages * 8;
	228	+ num_bytes = num_pages * 8 * AMDGPU_GPU_PAGES_IN_CPU_PAGE;
229	229
230	230	r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes,
231	231	AMDGPU_IB_POOL_DELAYED, &job);
@@ -1210,6 +1210,7 @@ static void amdgpu_ttm_tt_unpopulate(struct ttm_device *bdev, · 978 unmodified lines
1210	1210	if (gtt && gtt->userptr) {
1211	1211	amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1212	1212	kfree(ttm->sg);
	1213	+ ttm->sg = NULL;
1213	1214	ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
1214	1215	return;
1215	1216	}

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c+30−8

@@ -173,6 +173,9 @@ · 172 unmodified lines
173	173	#define mmGC_THROTTLE_CTRL_Sienna_Cichlid 0x2030
174	174	#define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX 0
175	175
	176	+#define mmRLC_SPARE_INT_0_Sienna_Cichlid 0x4ca5
	177	+#define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX 1
	178	+
176	179	#define GFX_RLCG_GC_WRITE_OLD (0x8 << 28)
177	180	#define GFX_RLCG_GC_WRITE (0x0 << 28)
178	181	#define GFX_RLCG_GC_READ (0x1 << 28)
@@ -1395,9 +1398,10 @@ static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = · 1216 unmodified lines
1395	1398	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1396	1399	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1397	1400	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
1398		− SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
	1401	+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1399	1402	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1400	1403	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
	1404	+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044),
1401	1405	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1402	1406	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
1403	1407	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
@@ -1415,12 +1419,13 @@ static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = · 11 unmodified lines
1415	1419	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
1416	1420	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1417	1421	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
	1422	+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
1418	1423	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1419	1424	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1420	1425	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1421	1426	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1422	1427	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
1423		− SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000)
	1428	+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000)
1424	1429	};
1425	1430
1426	1431	static bool gfx_v10_is_rlcg_rw(struct amdgpu_device adev, u32 offset, uint32_t flag, bool write)
@@ -1478,8 +1483,15 @@ static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, uint32 · 51 unmodified lines
1478	1483	(adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG2) * 4;
1479	1484	scratch_reg3 = adev->rmmio +
1480	1485	(adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3) * 4;
1481		− spare_int = adev->rmmio +
1482		− (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT) * 4;
	1486	+
	1487	+ if (adev->asic_type >= CHIP_SIENNA_CICHLID) {
	1488	+ spare_int = adev->rmmio +
	1489	+ (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX]
	1490	+ + mmRLC_SPARE_INT_0_Sienna_Cichlid) * 4;
	1491	+ } else {
	1492	+ spare_int = adev->rmmio +
	1493	+ (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT) * 4;
	1494	+ }
1483	1495
1484	1496	grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL;
1485	1497	grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX;
@@ -6859,8 +6871,12 @@ static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring) · 5373 unmodified lines
6859	6871	if (ring->use_doorbell) {
6860	6872	WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
6861	6873	(adev->doorbell_index.kiq * 2) << 2);
	6874	+ /* If GC has entered CGPG, ringing doorbell > first page doesn't
	6875	+ * wakeup GC. Enlarge CP_MEC_DOORBELL_RANGE_UPPER to workaround
	6876	+ * this issue.
	6877	+ */
6862	6878	WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
6863		− (adev->doorbell_index.userqueue_end * 2) << 2);
	6879	+ (adev->doorbell.size - 4));
6864	6880	}
6865	6881
6866	6882	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
@@ -7347,9 +7363,15 @@ static int gfx_v10_0_hw_fini(void *handle) · 480 unmodified lines
7347	7363	if (amdgpu_sriov_vf(adev)) {
7348	7364	gfx_v10_0_cp_gfx_enable(adev, false);
7349	7365	/* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
7350		− tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
7351		− tmp &= 0xffffff00;
7352		− WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
	7366	+ if (adev->asic_type >= CHIP_SIENNA_CICHLID) {
	7367	+ tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
	7368	+ tmp &= 0xffffff00;
	7369	+ WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
	7370	+ } else {
	7371	+ tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
	7372	+ tmp &= 0xffffff00;
	7373	+ WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
	7374	+ }
7353	7375
7354	7376	return 0;
7355	7377	}

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c+12−4

@@ -3673,8 +3673,12 @@ static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring) · 3672 unmodified lines
3673	3673	if (ring->use_doorbell) {
3674	3674	WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
3675	3675	(adev->doorbell_index.kiq * 2) << 2);
	3676	+ /* If GC has entered CGPG, ringing doorbell > first page doesn't
	3677	+ * wakeup GC. Enlarge CP_MEC_DOORBELL_RANGE_UPPER to workaround
	3678	+ * this issue.
	3679	+ */
3676	3680	WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
3677		− (adev->doorbell_index.userqueue_end * 2) << 2);
	3681	+ (adev->doorbell.size - 4));
3678	3682	}
3679	3683
3680	3684	WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
@@ -4943,7 +4947,7 @@ static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev, · 1262 unmodified lines
4943	4947	amdgpu_gfx_rlc_enter_safe_mode(adev);
4944	4948
4945	4949	/* Enable 3D CGCG/CGLS */
4946		− if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
	4950	+ if (enable) {
4947	4951	/* write cmd to clear cgcg/cgls ov */
4948	4952	def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4949	4953	/* unset CGCG override */
@@ -4955,8 +4959,12 @@ static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev, · 5 unmodified lines
4955	4959	/* enable 3Dcgcg FSM(0x0000363f) */
4956	4960	def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
4957	4961
4958		− data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) \|
4959		− RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
	4962	+ if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
	4963	+ data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) \|
	4964	+ RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
	4965	+ else
	4966	+ data = 0x0 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT;
	4967	+
4960	4968	if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
4961	4969	data \|= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) \|
4962	4970	RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;

drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c+2−0

@@ -172,6 +172,8 @@ static int jpeg_v2_0_hw_fini(void *handle) · 171 unmodified lines
172	172	{
173	173	struct amdgpu_device adev = (struct amdgpu_device )handle;
174	174
	175	+ cancel_delayed_work_sync(&adev->vcn.idle_work);
	176	+
175	177	if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
176	178	RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS))
177	179	jpeg_v2_0_set_powergating_state(adev, AMD_PG_STATE_GATE);

drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c+2−4

@@ -187,19 +187,17 @@ static int jpeg_v2_5_hw_init(void *handle) · 186 unmodified lines
187	187	static int jpeg_v2_5_hw_fini(void *handle)
188	188	{
189	189	struct amdgpu_device adev = (struct amdgpu_device )handle;
190		− struct amdgpu_ring *ring;
191	190	int i;
192	191
	192	+ cancel_delayed_work_sync(&adev->vcn.idle_work);
	193	+
193	194	for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
194	195	if (adev->jpeg.harvest_config & (1 << i))
195	196	continue;
196	197
197		− ring = &adev->jpeg.inst[i].ring_dec;
198	198	if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
199	199	RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS))
200	200	jpeg_v2_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
201		−
202		− ring->sched.ready = false;
203	201	}
204	202
205	203	return 0;

drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c+2−4

@@ -159,15 +159,13 @@ static int jpeg_v3_0_hw_init(void *handle) · 158 unmodified lines
159	159	static int jpeg_v3_0_hw_fini(void *handle)
160	160	{
161	161	struct amdgpu_device adev = (struct amdgpu_device )handle;
162		− struct amdgpu_ring *ring;
163	162
164		− ring = &adev->jpeg.inst->ring_dec;
	163	+ cancel_delayed_work_sync(&adev->vcn.idle_work);
	164	+
165	165	if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
166	166	RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS))
167	167	jpeg_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
168	168
169		− ring->sched.ready = false;
170		−
171	169	return 0;
172	170	}
173	171

drivers/gpu/drm/amd/amdgpu/nv.c+23−15

@@ -623,6 +623,16 @@ static const struct amdgpu_ip_block_version nv_common_ip_block = · 622 unmodified lines
623	623	.funcs = &nv_common_ip_funcs,
624	624	};
625	625
	626	+static bool nv_is_headless_sku(struct pci_dev *pdev)
	627	+{
	628	+ if ((pdev->device == 0x731E &&
	629	+ (pdev->revision == 0xC6 \|\| pdev->revision == 0xC7)) \|\|
	630	+ (pdev->device == 0x7340 && pdev->revision == 0xC9) \|\|
	631	+ (pdev->device == 0x7360 && pdev->revision == 0xC7))
	632	+ return true;
	633	+ return false;
	634	+}
	635	+
626	636	static int nv_reg_base_init(struct amdgpu_device *adev)
627	637	{
628	638	int r;
@@ -635,6 +645,12 @@ static int nv_reg_base_init(struct amdgpu_device *adev) · 6 unmodified lines
635	645	goto legacy_init;
636	646	}
637	647
	648	+ amdgpu_discovery_harvest_ip(adev);
	649	+ if (nv_is_headless_sku(adev->pdev)) {
	650	+ adev->harvest_ip_mask \|= AMD_HARVEST_IP_VCN_MASK;
	651	+ adev->harvest_ip_mask \|= AMD_HARVEST_IP_JPEG_MASK;
	652	+ }
	653	+
638	654	return 0;
639	655	}
640	656
@@ -671,16 +687,6 @@ void nv_set_virt_ops(struct amdgpu_device *adev) · 30 unmodified lines
671	687	adev->virt.ops = &xgpu_nv_virt_ops;
672	688	}
673	689
674		−static bool nv_is_headless_sku(struct pci_dev *pdev)
675		−{
676		− if ((pdev->device == 0x731E &&
677		− (pdev->revision == 0xC6 \|\| pdev->revision == 0xC7)) \|\|
678		− (pdev->device == 0x7340 && pdev->revision == 0xC9) \|\|
679		− (pdev->device == 0x7360 && pdev->revision == 0xC7))
680		− return true;
681		− return false;
682		−}
683		−
684	690	int nv_set_ip_blocks(struct amdgpu_device *adev)
685	691	{
686	692	int r;
@@ -728,8 +734,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev) · 41 unmodified lines
728	734	if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
729	735	!amdgpu_sriov_vf(adev))
730	736	amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
731		− if (!nv_is_headless_sku(adev->pdev))
732		− amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
	737	+ amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
733	738	amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
734	739	if (adev->enable_mes)
735	740	amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
@@ -752,8 +757,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev) · 16 unmodified lines
752	757	if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
753	758	!amdgpu_sriov_vf(adev))
754	759	amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
755		− if (!nv_is_headless_sku(adev->pdev))
756		− amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
	760	+ amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
757	761	if (!amdgpu_sriov_vf(adev))
758	762	amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
759	763	break;
@@ -777,7 +781,6 @@ int nv_set_ip_blocks(struct amdgpu_device *adev) · 17 unmodified lines
777	781	amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
778	782	if (!amdgpu_sriov_vf(adev))
779	783	amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
780		−
781	784	if (adev->enable_mes)
782	785	amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
783	786	break;
@@ -1149,6 +1152,11 @@ static int nv_common_early_init(void *handle) · 365 unmodified lines
1149	1152	return -EINVAL;
1150	1153	}
1151	1154
	1155	+ if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK)
	1156	+ adev->pg_flags &= ~(AMD_PG_SUPPORT_VCN \|
	1157	+ AMD_PG_SUPPORT_VCN_DPG \|
	1158	+ AMD_PG_SUPPORT_JPEG);
	1159	+
1152	1160	if (amdgpu_sriov_vf(adev)) {
1153	1161	amdgpu_virt_init_setting(adev);
1154	1162	xgpu_nv_mailbox_set_irq_funcs(adev);

drivers/gpu/drm/amd/amdgpu/psp_v11_0.c+2−1

@@ -720,7 +720,7 @@ static uint32_t psp_v11_0_ring_get_wptr(struct psp_context *psp) · 719 unmodified lines
720	720	struct amdgpu_device *adev = psp->adev;
721	721
722	722	if (amdgpu_sriov_vf(adev))
723		− data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
	723	+ data = psp->km_ring.ring_wptr;
724	724	else
725	725	data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
726	726
@@ -734,6 +734,7 @@ static void psp_v11_0_ring_set_wptr(struct psp_context *psp, uint32_t value) · 7 unmodified lines
734	734	if (amdgpu_sriov_vf(adev)) {
735	735	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);
736	736	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
	737	+ psp->km_ring.ring_wptr = value;
737	738	} else
738	739	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
739	740	}

drivers/gpu/drm/amd/amdgpu/psp_v3_1.c+2−1

@@ -379,7 +379,7 @@ static uint32_t psp_v3_1_ring_get_wptr(struct psp_context *psp) · 378 unmodified lines
379	379	struct amdgpu_device *adev = psp->adev;
380	380
381	381	if (amdgpu_sriov_vf(adev))
382		− data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
	382	+ data = psp->km_ring.ring_wptr;
383	383	else
384	384	data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
385	385	return data;
@@ -394,6 +394,7 @@ static void psp_v3_1_ring_set_wptr(struct psp_context *psp, uint32_t value) · 8 unmodified lines
394	394	/* send interrupt to PSP for SRIOV ring write pointer update */
395	395	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
396	396	GFX_CTRL_CMD_ID_CONSUME_CMD);
	397	+ psp->km_ring.ring_wptr = value;
397	398	} else
398	399	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
399	400	}

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c+4−0

@@ -123,6 +123,10 @@ static const struct soc15_reg_golden golden_settings_sdma_nv14[] = { · 122 unmodified lines
123	123
124	124	static const struct soc15_reg_golden golden_settings_sdma_nv12[] = {
125	125	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
	126	+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
	127	+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
	128	+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
	129	+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
126	130	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
127	131	};
128	132

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c+0−5

@@ -497,11 +497,6 @@ static void sdma_v5_2_gfx_stop(struct amdgpu_device *adev) · 496 unmodified lines
497	497	ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
498	498	WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
499	499	}
500		−
501		− sdma0->sched.ready = false;
502		− sdma1->sched.ready = false;
503		− sdma2->sched.ready = false;
504		− sdma3->sched.ready = false;
505	500	}
506	501
507	502	/**

drivers/gpu/drm/amd/amdgpu/soc15.c+3−3

@@ -302,6 +302,7 @@ static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode, · 301 unmodified lines
302	302	*codecs = &rv_video_codecs_decode;
303	303	return 0;
304	304	case CHIP_ARCTURUS:
	305	+ case CHIP_ALDEBARAN:
305	306	case CHIP_RENOIR:
306	307	if (encode)
307	308	*codecs = &vega_video_codecs_encode;
@@ -1392,7 +1393,6 @@ static int soc15_common_early_init(void *handle) · 1084 unmodified lines
1392	1393	adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG \|
1393	1394	AMD_CG_SUPPORT_GFX_MGLS \|
1394	1395	AMD_CG_SUPPORT_GFX_CP_LS \|
1395		− AMD_CG_SUPPORT_GFX_3D_CGCG \|
1396	1396	AMD_CG_SUPPORT_GFX_3D_CGLS \|
1397	1397	AMD_CG_SUPPORT_GFX_CGCG \|
1398	1398	AMD_CG_SUPPORT_GFX_CGLS \|
@@ -1401,7 +1401,8 @@ static int soc15_common_early_init(void *handle) · 2 unmodified lines
1401	1401	AMD_CG_SUPPORT_MC_MGCG \|
1402	1402	AMD_CG_SUPPORT_MC_LS \|
1403	1403	AMD_CG_SUPPORT_SDMA_MGCG \|
1404		− AMD_CG_SUPPORT_SDMA_LS;
	1404	+ AMD_CG_SUPPORT_SDMA_LS \|
	1405	+ AMD_CG_SUPPORT_VCN_MGCG;
1405	1406
1406	1407	adev->pg_flags = AMD_PG_SUPPORT_SDMA \|
1407	1408	AMD_PG_SUPPORT_MMHUB \|
@@ -1411,7 +1412,6 @@ static int soc15_common_early_init(void *handle) · 3 unmodified lines
1411	1412	AMD_CG_SUPPORT_GFX_MGLS \|
1412	1413	AMD_CG_SUPPORT_GFX_RLC_LS \|
1413	1414	AMD_CG_SUPPORT_GFX_CP_LS \|
1414		− AMD_CG_SUPPORT_GFX_3D_CGCG \|
1415	1415	AMD_CG_SUPPORT_GFX_3D_CGLS \|
1416	1416	AMD_CG_SUPPORT_GFX_CGCG \|
1417	1417	AMD_CG_SUPPORT_GFX_CGLS \|

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c+1−0

@@ -357,6 +357,7 @@ static int uvd_v6_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) · 356 unmodified lines
357	357
358	358	error:
359	359	dma_fence_put(fence);
	360	+ amdgpu_bo_unpin(bo);
360	361	amdgpu_bo_unreserve(bo);
361	362	amdgpu_bo_unref(&bo);
362	363	return r;

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c+14−5

@@ -231,9 +231,13 @@ static int vcn_v1_0_hw_fini(void *handle) · 230 unmodified lines
231	231	{
232	232	struct amdgpu_device adev = (struct amdgpu_device )handle;
233	233
	234	+ cancel_delayed_work_sync(&adev->vcn.idle_work);
	235	+
234	236	if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) \|\|
235		− RREG32_SOC15(VCN, 0, mmUVD_STATUS))
	237	+ (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
	238	+ RREG32_SOC15(VCN, 0, mmUVD_STATUS))) {
236	239	vcn_v1_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
	240	+ }
237	241
238	242	return 0;
239	243	}
@@ -1119,10 +1123,10 @@ static int vcn_v1_0_stop_spg_mode(struct amdgpu_device *adev) · 879 unmodified lines
1119	1123	UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
1120	1124	SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp);
1121	1125
1122		− /* put VCPU into reset */
1123		− WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1124		− UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
1125		− ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
	1126	+ /* stall UMC channel */
	1127	+ WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2),
	1128	+ UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
	1129	+ ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1126	1130
1127	1131	tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK \|
1128	1132	UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
@@ -1141,6 +1145,11 @@ static int vcn_v1_0_stop_spg_mode(struct amdgpu_device *adev) · 12 unmodified lines
1141	1145	UVD_SOFT_RESET__LMI_SOFT_RESET_MASK,
1142	1146	~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK);
1143	1147
	1148	+ /* put VCPU into reset */
	1149	+ WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
	1150	+ UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
	1151	+ ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
	1152	+
1144	1153	WREG32_SOC15(UVD, 0, mmUVD_STATUS, 0);
1145	1154
1146	1155	vcn_v1_0_enable_clock_gating(adev);

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c+2−0

@@ -262,6 +262,8 @@ static int vcn_v2_0_hw_fini(void *handle) · 261 unmodified lines
262	262	{
263	263	struct amdgpu_device adev = (struct amdgpu_device )handle;
264	264
	265	+ cancel_delayed_work_sync(&adev->vcn.idle_work);
	266	+
265	267	if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) \|\|
266	268	(adev->vcn.cur_state != AMD_PG_STATE_GATE &&
267	269	RREG32_SOC15(VCN, 0, mmUVD_STATUS)))

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c+2−0

@@ -321,6 +321,8 @@ static int vcn_v2_5_hw_fini(void *handle) · 320 unmodified lines
321	321	struct amdgpu_device adev = (struct amdgpu_device )handle;
322	322	int i;
323	323
	324	+ cancel_delayed_work_sync(&adev->vcn.idle_work);
	325	+
324	326	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
325	327	if (adev->vcn.harvest_config & (1 << i))
326	328	continue;

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c+3−10

@@ -372,15 +372,14 @@ done: · 371 unmodified lines
372	372	static int vcn_v3_0_hw_fini(void *handle)
373	373	{
374	374	struct amdgpu_device adev = (struct amdgpu_device )handle;
375		− struct amdgpu_ring *ring;
376		− int i, j;
	375	+ int i;
	376	+
	377	+ cancel_delayed_work_sync(&adev->vcn.idle_work);
377	378
378	379	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
379	380	if (adev->vcn.harvest_config & (1 << i))
380	381	continue;
381	382
382		− ring = &adev->vcn.inst[i].ring_dec;
383		−
384	383	if (!amdgpu_sriov_vf(adev)) {
385	384	if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) \|\|
386	385	(adev->vcn.cur_state != AMD_PG_STATE_GATE &&
@@ -388,12 +387,6 @@ static int vcn_v3_0_hw_fini(void *handle) · 1 unmodified line
388	387	vcn_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
389	388	}
390	389	}
391		− ring->sched.ready = false;
392		−
393		− for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
394		− ring = &adev->vcn.inst[i].ring_enc[j];
395		− ring->sched.ready = false;
396		− }
397	390	}
398	391
399	392	return 0;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c+19−11

@@ -925,7 +925,8 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev) · 924 unmodified lines
925	925	abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
926	926	}
927	927
928		− adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
	928	+ if (!adev->dm.dc->ctx->dmub_srv)
	929	+ adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
929	930	if (!adev->dm.dc->ctx->dmub_srv) {
930	931	DRM_ERROR("Couldn't allocate DC DMUB server!\n");
931	932	return -ENOMEM;
@@ -1954,7 +1955,6 @@ static int dm_suspend(void *handle) · 1022 unmodified lines
1954	1955
1955	1956	amdgpu_dm_irq_suspend(adev);
1956	1957
1957		−
1958	1958	dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
1959	1959
1960	1960	return 0;
@@ -5500,7 +5500,8 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, · 3539 unmodified lines
5500	5500	struct drm_display_mode saved_mode;
5501	5501	struct drm_display_mode *freesync_mode = NULL;
5502	5502	bool native_mode_found = false;
5503		− bool recalculate_timing = dm_state ? (dm_state->scaling != RMX_OFF) : false;
	5503	+ bool recalculate_timing = false;
	5504	+ bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
5504	5505	int mode_refresh;
5505	5506	int preferred_refresh = 0;
5506	5507	#if defined(CONFIG_DRM_AMD_DC_DCN)
@@ -5563,7 +5564,7 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, · 56 unmodified lines
5563	5564	*/
5564	5565	DRM_DEBUG_DRIVER("No preferred mode found\n");
5565	5566	} else {
5566		− recalculate_timing \|= amdgpu_freesync_vid_mode &&
	5567	+ recalculate_timing = amdgpu_freesync_vid_mode &&
5567	5568	is_freesync_video_mode(&mode, aconnector);
5568	5569	if (recalculate_timing) {
5569	5570	freesync_mode = get_highest_refresh_rate_mode(aconnector, false);
@@ -5571,11 +5572,10 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, · 1 unmodified line
5571	5572	mode = *freesync_mode;
5572	5573	} else {
5573	5574	decide_crtc_timing_for_drm_display_mode(
5574		− &mode, preferred_mode,
5575		− dm_state ? (dm_state->scaling != RMX_OFF) : false);
5576		− }
	5575	+ &mode, preferred_mode, scale);
5577	5576
5578		− preferred_refresh = drm_mode_vrefresh(preferred_mode);
	5577	+ preferred_refresh = drm_mode_vrefresh(preferred_mode);
	5578	+ }
5579	5579	}
5580	5580
5581	5581	if (recalculate_timing)
@@ -5587,7 +5587,7 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, · 5 unmodified lines
5587	5587	* If scaling is enabled and refresh rate didn't change
5588	5588	* we copy the vic and polarities of the old timings
5589	5589	*/
5590		− if (!recalculate_timing \|\| mode_refresh != preferred_refresh)
	5590	+ if (!scale \|\| mode_refresh != preferred_refresh)
5591	5591	fill_stream_properties_from_drm_display_mode(
5592	5592	stream, &mode, &aconnector->base, con_state, NULL,
5593	5593	requested_bpc);
@@ -9854,7 +9854,7 @@ static int dm_check_crtc_cursor(struct drm_atomic_state *state, · 4260 unmodified lines
9854	9854
9855	9855	if (cursor_scale_w != primary_scale_w \|\|
9856	9856	cursor_scale_h != primary_scale_h) {
9857		− DRM_DEBUG_ATOMIC("Cursor plane scaling doesn't match primary plane\n");
	9857	+ drm_dbg_atomic(crtc->dev, "Cursor plane scaling doesn't match primary plane\n");
9858	9858	return -EINVAL;
9859	9859	}
9860	9860
@@ -9891,7 +9891,7 @@ static int validate_overlay(struct drm_atomic_state *state) · 30 unmodified lines
9891	9891	int i;
9892	9892	struct drm_plane *plane;
9893	9893	struct drm_plane_state old_plane_state, new_plane_state;
9894		− struct drm_plane_state primary_state, overlay_state = NULL;
	9894	+ struct drm_plane_state primary_state, cursor_state, *overlay_state = NULL;
9895	9895
9896	9896	/* Check if primary plane is contained inside overlay */
9897	9897	for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
@@ -9921,6 +9921,14 @@ static int validate_overlay(struct drm_atomic_state *state) · 23 unmodified lines
9921	9921	if (!primary_state->crtc)
9922	9922	return 0;
9923	9923
	9924	+ /* check if cursor plane is enabled */
	9925	+ cursor_state = drm_atomic_get_plane_state(state, overlay_state->crtc->cursor);
	9926	+ if (IS_ERR(cursor_state))
	9927	+ return PTR_ERR(cursor_state);
	9928	+
	9929	+ if (drm_atomic_plane_disabling(plane->state, cursor_state))
	9930	+ return 0;
	9931	+
9924	9932	/* Perform the bounds check to ensure the overlay plane covers the primary */
9925	9933	if (primary_state->crtc_x < overlay_state->crtc_x \|\|
9926	9934	primary_state->crtc_y < overlay_state->crtc_y \|\|

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c+1−0

@@ -650,6 +650,7 @@ struct hdcp_workqueue hdcp_create_workqueue(struct amdgpu_device adev, struct · 649 unmodified lines
650	650
651	651	/* File created at /sys/class/drm/card0/device/hdcp_srm*/
652	652	hdcp_work[0].attr = data_attr;
	653	+ sysfs_bin_attr_init(&hdcp_work[0].attr);
653	654
654	655	if (sysfs_create_bin_file(&adev->dev->kobj, &hdcp_work[0].attr))
655	656	DRM_WARN("Failed to create device file hdcp_srm");

drivers/gpu/drm/amd/display/dc/core/dc_link.c+18−0

@@ -1076,6 +1076,24 @@ static bool dc_link_detect_helper(struct dc_link *link, · 1075 unmodified lines
1076	1076	dc_is_dvi_signal(link->connector_signal)) {
1077	1077	if (prev_sink)
1078	1078	dc_sink_release(prev_sink);
	1079	+ link_disconnect_sink(link);
	1080	+
	1081	+ return false;
	1082	+ }
	1083	+ /*
	1084	+ * Abort detection for DP connectors if we have
	1085	+ * no EDID and connector is active converter
	1086	+ * as there are no display downstream
	1087	+ *
	1088	+ */
	1089	+ if (dc_is_dp_sst_signal(link->connector_signal) &&
	1090	+ (link->dpcd_caps.dongle_type ==
	1091	+ DISPLAY_DONGLE_DP_VGA_CONVERTER \|\|
	1092	+ link->dpcd_caps.dongle_type ==
	1093	+ DISPLAY_DONGLE_DP_DVI_CONVERTER)) {
	1094	+ if (prev_sink)
	1095	+ dc_sink_release(prev_sink);
	1096	+ link_disconnect_sink(link);
1079	1097
1080	1098	return false;
1081	1099	}

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c+1−1

@@ -3236,7 +3236,7 @@ static noinline bool dcn20_validate_bandwidth_fp(struct dc *dc, · 3235 unmodified lines
3236	3236	voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
3237	3237	dummy_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
3238	3238
3239		− if (voltage_supported && dummy_pstate_supported) {
	3239	+ if (voltage_supported && (dummy_pstate_supported \|\| !(context->stream_count))) {
3240	3240	context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
3241	3241	goto restore_dml_state;
3242	3242	}

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c+4−3

@@ -826,10 +826,11 @@ static const struct dc_plane_cap plane_cap = { · 825 unmodified lines
826	826	.fp16 = 16000
827	827	},
828	828
	829	+ /* 6:1 downscaling ratio: 1000/6 = 166.666 */
829	830	.max_downscale_factor = {
830		− .argb8888 = 600,
831		− .nv12 = 600,
832		− .fp16 = 600
	831	+ .argb8888 = 167,
	832	+ .nv12 = 167,
	833	+ .fp16 = 167
833	834	}
834	835	};
835	836

drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c+4−3

@@ -843,10 +843,11 @@ static const struct dc_plane_cap plane_cap = { · 842 unmodified lines
843	843	.fp16 = 16000
844	844	},
845	845
	846	+ /* 6:1 downscaling ratio: 1000/6 = 166.666 */
846	847	.max_downscale_factor = {
847		− .argb8888 = 600,
848		− .nv12 = 600,
849		− .fp16 = 600
	848	+ .argb8888 = 167,
	849	+ .nv12 = 167,
	850	+ .fp16 = 167
850	851	},
851	852	64,
852	853	64

drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c+4−3

@@ -284,10 +284,11 @@ static const struct dc_plane_cap plane_cap = { · 283 unmodified lines
284	284	.nv12 = 16000,
285	285	.fp16 = 16000
286	286	},
	287	+ /* 6:1 downscaling ratio: 1000/6 = 166.666 */
287	288	.max_downscale_factor = {
288		− .argb8888 = 600,
289		− .nv12 = 600,
290		− .fp16 = 600
	289	+ .argb8888 = 167,
	290	+ .nv12 = 167,
	291	+ .fp16 = 167
291	292	},
292	293	16,
293	294	16

drivers/gpu/drm/amd/include/amd_shared.h+6−0

@@ -216,6 +216,12 @@ enum PP_FEATURE_MASK { · 215 unmodified lines
216	216	PP_GFX_DCS_MASK = 0x80000,
217	217	};
218	218
	219	+enum amd_harvest_ip_mask {
	220	+ AMD_HARVEST_IP_VCN_MASK = 0x1,
	221	+ AMD_HARVEST_IP_JPEG_MASK = 0x2,
	222	+ AMD_HARVEST_IP_DMU_MASK = 0x4,
	223	+};
	224	+
219	225	enum DC_FEATURE_MASK {
220	226	DC_FBC_MASK = 0x1,
221	227	DC_MULTI_MON_PP_MCLK_SWITCH_MASK = 0x2,

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c+1−0

@@ -810,6 +810,7 @@ static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, · 809 unmodified lines
810	810	break;
811	811	case AMD_DPM_FORCED_LEVEL_MANUAL:
812	812	data->fine_grain_enabled = 1;
	813	+ break;
813	814	case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
814	815	default:
815	816	break;

drivers/gpu/drm/amd/pm/powerplay/si_dpm.c+88−86

@@ -4817,70 +4817,70 @@ static int si_populate_smc_initial_state(struct amdgpu_device *adev, · 4816 unmodified lines
4817	4817	u32 reg;
4818	4818	int ret;
4819	4819
4820		− table->initialState.levels[0].mclk.vDLL_CNTL =
	4820	+ table->initialState.level.mclk.vDLL_CNTL =
4821	4821	cpu_to_be32(si_pi->clock_registers.dll_cntl);
4822		− table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
	4822	+ table->initialState.level.mclk.vMCLK_PWRMGT_CNTL =
4823	4823	cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4824		− table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
	4824	+ table->initialState.level.mclk.vMPLL_AD_FUNC_CNTL =
4825	4825	cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4826		− table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
	4826	+ table->initialState.level.mclk.vMPLL_DQ_FUNC_CNTL =
4827	4827	cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4828		− table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =
	4828	+ table->initialState.level.mclk.vMPLL_FUNC_CNTL =
4829	4829	cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4830		− table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
	4830	+ table->initialState.level.mclk.vMPLL_FUNC_CNTL_1 =
4831	4831	cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4832		− table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
	4832	+ table->initialState.level.mclk.vMPLL_FUNC_CNTL_2 =
4833	4833	cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4834		− table->initialState.levels[0].mclk.vMPLL_SS =
	4834	+ table->initialState.level.mclk.vMPLL_SS =
4835	4835	cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4836		− table->initialState.levels[0].mclk.vMPLL_SS2 =
	4836	+ table->initialState.level.mclk.vMPLL_SS2 =
4837	4837	cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4838	4838
4839		− table->initialState.levels[0].mclk.mclk_value =
	4839	+ table->initialState.level.mclk.mclk_value =
4840	4840	cpu_to_be32(initial_state->performance_levels[0].mclk);
4841	4841
4842		− table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
	4842	+ table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL =
4843	4843	cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4844		− table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
	4844	+ table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_2 =
4845	4845	cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4846		− table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
	4846	+ table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_3 =
4847	4847	cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4848		− table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
	4848	+ table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_4 =
4849	4849	cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4850		− table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
	4850	+ table->initialState.level.sclk.vCG_SPLL_SPREAD_SPECTRUM =
4851	4851	cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4852		− table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
	4852	+ table->initialState.level.sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
4853	4853	cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4854	4854
4855		− table->initialState.levels[0].sclk.sclk_value =
	4855	+ table->initialState.level.sclk.sclk_value =
4856	4856	cpu_to_be32(initial_state->performance_levels[0].sclk);
4857	4857
4858		− table->initialState.levels[0].arbRefreshState =
	4858	+ table->initialState.level.arbRefreshState =
4859	4859	SISLANDS_INITIAL_STATE_ARB_INDEX;
4860	4860
4861		− table->initialState.levels[0].ACIndex = 0;
	4861	+ table->initialState.level.ACIndex = 0;
4862	4862
4863	4863	ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
4864	4864	initial_state->performance_levels[0].vddc,
4865		− &table->initialState.levels[0].vddc);
	4865	+ &table->initialState.level.vddc);
4866	4866
4867	4867	if (!ret) {
4868	4868	u16 std_vddc;
4869	4869
4870	4870	ret = si_get_std_voltage_value(adev,
4871		− &table->initialState.levels[0].vddc,
	4871	+ &table->initialState.level.vddc,
4872	4872	&std_vddc);
4873	4873	if (!ret)
4874	4874	si_populate_std_voltage_value(adev, std_vddc,
4875		− table->initialState.levels[0].vddc.index,
4876		− &table->initialState.levels[0].std_vddc);
	4875	+ table->initialState.level.vddc.index,
	4876	+ &table->initialState.level.std_vddc);
4877	4877	}
4878	4878
4879	4879	if (eg_pi->vddci_control)
4880	4880	si_populate_voltage_value(adev,
4881	4881	&eg_pi->vddci_voltage_table,
4882	4882	initial_state->performance_levels[0].vddci,
4883		− &table->initialState.levels[0].vddci);
	4883	+ &table->initialState.level.vddci);
4884	4884
4885	4885	if (si_pi->vddc_phase_shed_control)
4886	4886	si_populate_phase_shedding_value(adev,
@@ -4888,41 +4888,41 @@ static int si_populate_smc_initial_state(struct amdgpu_device *adev, · 1 unmodified line
4888	4888	initial_state->performance_levels[0].vddc,
4889	4889	initial_state->performance_levels[0].sclk,
4890	4890	initial_state->performance_levels[0].mclk,
4891		− &table->initialState.levels[0].vddc);
	4891	+ &table->initialState.level.vddc);
4892	4892
4893		− si_populate_initial_mvdd_value(adev, &table->initialState.levels[0].mvdd);
	4893	+ si_populate_initial_mvdd_value(adev, &table->initialState.level.mvdd);
4894	4894
4895	4895	reg = CG_R(0xffff) \| CG_L(0);
4896		− table->initialState.levels[0].aT = cpu_to_be32(reg);
4897		− table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
4898		− table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
	4896	+ table->initialState.level.aT = cpu_to_be32(reg);
	4897	+ table->initialState.level.bSP = cpu_to_be32(pi->dsp);
	4898	+ table->initialState.level.gen2PCIE = (u8)si_pi->boot_pcie_gen;
4899	4899
4900	4900	if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
4901		− table->initialState.levels[0].strobeMode =
	4901	+ table->initialState.level.strobeMode =
4902	4902	si_get_strobe_mode_settings(adev,
4903	4903	initial_state->performance_levels[0].mclk);
4904	4904
4905	4905	if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4906		− table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG \| SISLANDS_SMC_MC_EDC_WR_FLAG;
	4906	+ table->initialState.level.mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG \| SISLANDS_SMC_MC_EDC_WR_FLAG;
4907	4907	else
4908		− table->initialState.levels[0].mcFlags = 0;
	4908	+ table->initialState.level.mcFlags = 0;
4909	4909	}
4910	4910
4911	4911	table->initialState.levelCount = 1;
4912	4912
4913	4913	table->initialState.flags \|= PPSMC_SWSTATE_FLAG_DC;
4914	4914
4915		− table->initialState.levels[0].dpm2.MaxPS = 0;
4916		− table->initialState.levels[0].dpm2.NearTDPDec = 0;
4917		− table->initialState.levels[0].dpm2.AboveSafeInc = 0;
4918		− table->initialState.levels[0].dpm2.BelowSafeInc = 0;
4919		− table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;
	4915	+ table->initialState.level.dpm2.MaxPS = 0;
	4916	+ table->initialState.level.dpm2.NearTDPDec = 0;
	4917	+ table->initialState.level.dpm2.AboveSafeInc = 0;
	4918	+ table->initialState.level.dpm2.BelowSafeInc = 0;
	4919	+ table->initialState.level.dpm2.PwrEfficiencyRatio = 0;
4920	4920
4921	4921	reg = MIN_POWER_MASK \| MAX_POWER_MASK;
4922		− table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
	4922	+ table->initialState.level.SQPowerThrottle = cpu_to_be32(reg);
4923	4923
4924	4924	reg = MAX_POWER_DELTA_MASK \| STI_SIZE_MASK \| LTI_RATIO_MASK;
4925		− table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
	4925	+ table->initialState.level.SQPowerThrottle_2 = cpu_to_be32(reg);
4926	4926
4927	4927	return 0;
4928	4928	}
@@ -4953,18 +4953,18 @@ static int si_populate_smc_acpi_state(struct amdgpu_device *adev, · 24 unmodified lines
4953	4953
4954	4954	if (pi->acpi_vddc) {
4955	4955	ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
4956		− pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
	4956	+ pi->acpi_vddc, &table->ACPIState.level.vddc);
4957	4957	if (!ret) {
4958	4958	u16 std_vddc;
4959	4959
4960	4960	ret = si_get_std_voltage_value(adev,
4961		− &table->ACPIState.levels[0].vddc, &std_vddc);
	4961	+ &table->ACPIState.level.vddc, &std_vddc);
4962	4962	if (!ret)
4963	4963	si_populate_std_voltage_value(adev, std_vddc,
4964		− table->ACPIState.levels[0].vddc.index,
4965		− &table->ACPIState.levels[0].std_vddc);
	4964	+ table->ACPIState.level.vddc.index,
	4965	+ &table->ACPIState.level.std_vddc);
4966	4966	}
4967		− table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;
	4967	+ table->ACPIState.level.gen2PCIE = si_pi->acpi_pcie_gen;
4968	4968
4969	4969	if (si_pi->vddc_phase_shed_control) {
4970	4970	si_populate_phase_shedding_value(adev,
@@ -4972,23 +4972,23 @@ static int si_populate_smc_acpi_state(struct amdgpu_device *adev, · 1 unmodified line
4972	4972	pi->acpi_vddc,
4973	4973	0,
4974	4974	0,
4975		− &table->ACPIState.levels[0].vddc);
	4975	+ &table->ACPIState.level.vddc);
4976	4976	}
4977	4977	} else {
4978	4978	ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
4979		− pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);
	4979	+ pi->min_vddc_in_table, &table->ACPIState.level.vddc);
4980	4980	if (!ret) {
4981	4981	u16 std_vddc;
4982	4982
4983	4983	ret = si_get_std_voltage_value(adev,
4984		− &table->ACPIState.levels[0].vddc, &std_vddc);
	4984	+ &table->ACPIState.level.vddc, &std_vddc);
4985	4985
4986	4986	if (!ret)
4987	4987	si_populate_std_voltage_value(adev, std_vddc,
4988		− table->ACPIState.levels[0].vddc.index,
4989		− &table->ACPIState.levels[0].std_vddc);
	4988	+ table->ACPIState.level.vddc.index,
	4989	+ &table->ACPIState.level.std_vddc);
4990	4990	}
4991		− table->ACPIState.levels[0].gen2PCIE =
	4991	+ table->ACPIState.level.gen2PCIE =
4992	4992	(u8)amdgpu_get_pcie_gen_support(adev,
4993	4993	si_pi->sys_pcie_mask,
4994	4994	si_pi->boot_pcie_gen,
@@ -5000,14 +5000,14 @@ static int si_populate_smc_acpi_state(struct amdgpu_device *adev, · 5 unmodified lines
5000	5000	pi->min_vddc_in_table,
5001	5001	0,
5002	5002	0,
5003		− &table->ACPIState.levels[0].vddc);
	5003	+ &table->ACPIState.level.vddc);
5004	5004	}
5005	5005
5006	5006	if (pi->acpi_vddc) {
5007	5007	if (eg_pi->acpi_vddci)
5008	5008	si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table,
5009	5009	eg_pi->acpi_vddci,
5010		− &table->ACPIState.levels[0].vddci);
	5010	+ &table->ACPIState.level.vddci);
5011	5011	}
5012	5012
5013	5013	mclk_pwrmgt_cntl \|= MRDCK0_RESET \| MRDCK1_RESET;
@@ -5018,59 +5018,59 @@ static int si_populate_smc_acpi_state(struct amdgpu_device *adev, · 4 unmodified lines
5018	5018	spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
5019	5019	spll_func_cntl_2 \|= SCLK_MUX_SEL(4);
5020	5020
5021		− table->ACPIState.levels[0].mclk.vDLL_CNTL =
	5021	+ table->ACPIState.level.mclk.vDLL_CNTL =
5022	5022	cpu_to_be32(dll_cntl);
5023		− table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
	5023	+ table->ACPIState.level.mclk.vMCLK_PWRMGT_CNTL =
5024	5024	cpu_to_be32(mclk_pwrmgt_cntl);
5025		− table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
	5025	+ table->ACPIState.level.mclk.vMPLL_AD_FUNC_CNTL =
5026	5026	cpu_to_be32(mpll_ad_func_cntl);
5027		− table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
	5027	+ table->ACPIState.level.mclk.vMPLL_DQ_FUNC_CNTL =
5028	5028	cpu_to_be32(mpll_dq_func_cntl);
5029		− table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =
	5029	+ table->ACPIState.level.mclk.vMPLL_FUNC_CNTL =
5030	5030	cpu_to_be32(mpll_func_cntl);
5031		− table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
	5031	+ table->ACPIState.level.mclk.vMPLL_FUNC_CNTL_1 =
5032	5032	cpu_to_be32(mpll_func_cntl_1);
5033		− table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
	5033	+ table->ACPIState.level.mclk.vMPLL_FUNC_CNTL_2 =
5034	5034	cpu_to_be32(mpll_func_cntl_2);
5035		− table->ACPIState.levels[0].mclk.vMPLL_SS =
	5035	+ table->ACPIState.level.mclk.vMPLL_SS =
5036	5036	cpu_to_be32(si_pi->clock_registers.mpll_ss1);
5037		− table->ACPIState.levels[0].mclk.vMPLL_SS2 =
	5037	+ table->ACPIState.level.mclk.vMPLL_SS2 =
5038	5038	cpu_to_be32(si_pi->clock_registers.mpll_ss2);
5039	5039
5040		− table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
	5040	+ table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL =
5041	5041	cpu_to_be32(spll_func_cntl);
5042		− table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
	5042	+ table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_2 =
5043	5043	cpu_to_be32(spll_func_cntl_2);
5044		− table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
	5044	+ table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_3 =
5045	5045	cpu_to_be32(spll_func_cntl_3);
5046		− table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
	5046	+ table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_4 =
5047	5047	cpu_to_be32(spll_func_cntl_4);
5048	5048
5049		− table->ACPIState.levels[0].mclk.mclk_value = 0;
5050		− table->ACPIState.levels[0].sclk.sclk_value = 0;
	5049	+ table->ACPIState.level.mclk.mclk_value = 0;
	5050	+ table->ACPIState.level.sclk.sclk_value = 0;
5051	5051
5052		− si_populate_mvdd_value(adev, 0, &table->ACPIState.levels[0].mvdd);
	5052	+ si_populate_mvdd_value(adev, 0, &table->ACPIState.level.mvdd);
5053	5053
5054	5054	if (eg_pi->dynamic_ac_timing)
5055		− table->ACPIState.levels[0].ACIndex = 0;
	5055	+ table->ACPIState.level.ACIndex = 0;
5056	5056
5057		− table->ACPIState.levels[0].dpm2.MaxPS = 0;
5058		− table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
5059		− table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
5060		− table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
5061		− table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;
	5057	+ table->ACPIState.level.dpm2.MaxPS = 0;
	5058	+ table->ACPIState.level.dpm2.NearTDPDec = 0;
	5059	+ table->ACPIState.level.dpm2.AboveSafeInc = 0;
	5060	+ table->ACPIState.level.dpm2.BelowSafeInc = 0;
	5061	+ table->ACPIState.level.dpm2.PwrEfficiencyRatio = 0;
5062	5062
5063	5063	reg = MIN_POWER_MASK \| MAX_POWER_MASK;
5064		− table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
	5064	+ table->ACPIState.level.SQPowerThrottle = cpu_to_be32(reg);
5065	5065
5066	5066	reg = MAX_POWER_DELTA_MASK \| STI_SIZE_MASK \| LTI_RATIO_MASK;
5067		− table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
	5067	+ table->ACPIState.level.SQPowerThrottle_2 = cpu_to_be32(reg);
5068	5068
5069	5069	return 0;
5070	5070	}
5071	5071
5072	5072	static int si_populate_ulv_state(struct amdgpu_device *adev,
5073		− SISLANDS_SMC_SWSTATE *state)
	5073	+ struct SISLANDS_SMC_SWSTATE_SINGLE *state)
5074	5074	{
5075	5075	struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5076	5076	struct si_power_info *si_pi = si_get_pi(adev);
@@ -5079,19 +5079,19 @@ static int si_populate_ulv_state(struct amdgpu_device *adev, · 2 unmodified lines
5079	5079	int ret;
5080	5080
5081	5081	ret = si_convert_power_level_to_smc(adev, &ulv->pl,
5082		− &state->levels[0]);
	5082	+ &state->level);
5083	5083	if (!ret) {
5084	5084	if (eg_pi->sclk_deep_sleep) {
5085	5085	if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5086		− state->levels[0].stateFlags \|= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
	5086	+ state->level.stateFlags \|= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5087	5087	else
5088		− state->levels[0].stateFlags \|= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
	5088	+ state->level.stateFlags \|= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5089	5089	}
5090	5090	if (ulv->one_pcie_lane_in_ulv)
5091	5091	state->flags \|= PPSMC_SWSTATE_FLAG_PCIE_X1;
5092		− state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
5093		− state->levels[0].ACIndex = 1;
5094		− state->levels[0].std_vddc = state->levels[0].vddc;
	5092	+ state->level.arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
	5093	+ state->level.ACIndex = 1;
	5094	+ state->level.std_vddc = state->level.vddc;
5095	5095	state->levelCount = 1;
5096	5096
5097	5097	state->flags \|= PPSMC_SWSTATE_FLAG_DC;
@@ -5190,7 +5190,9 @@ static int si_init_smc_table(struct amdgpu_device *adev) · 92 unmodified lines
5190	5190	if (ret)
5191	5191	return ret;
5192	5192
5193		− table->driverState = table->initialState;
	5193	+ table->driverState.flags = table->initialState.flags;
	5194	+ table->driverState.levelCount = table->initialState.levelCount;
	5195	+ table->driverState.levels[0] = table->initialState.level;
5194	5196
5195	5197	ret = si_do_program_memory_timing_parameters(adev, amdgpu_boot_state,
5196	5198	SISLANDS_INITIAL_STATE_ARB_INDEX);
@@ -5737,8 +5739,8 @@ static int si_upload_ulv_state(struct amdgpu_device *adev) · 540 unmodified lines
5737	5739	if (ulv->supported && ulv->pl.vddc) {
5738	5740	u32 address = si_pi->state_table_start +
5739	5741	offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5740		− SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;
5741		− u32 state_size = sizeof(SISLANDS_SMC_SWSTATE);
	5742	+ struct SISLANDS_SMC_SWSTATE_SINGLE *smc_state = &si_pi->smc_statetable.ULVState;
	5743	+ u32 state_size = sizeof(struct SISLANDS_SMC_SWSTATE_SINGLE);
5742	5744
5743	5745	memset(smc_state, 0, state_size);
5744	5746

drivers/gpu/drm/amd/pm/powerplay/sislands_smc.h+21−13

@@ -191,6 +191,14 @@ struct SISLANDS_SMC_SWSTATE · 190 unmodified lines
191	191
192	192	typedef struct SISLANDS_SMC_SWSTATE SISLANDS_SMC_SWSTATE;
193	193
	194	+struct SISLANDS_SMC_SWSTATE_SINGLE {
	195	+ uint8_t flags;
	196	+ uint8_t levelCount;
	197	+ uint8_t padding2;
	198	+ uint8_t padding3;
	199	+ SISLANDS_SMC_HW_PERFORMANCE_LEVEL level;
	200	+};
	201	+
194	202	#define SISLANDS_SMC_VOLTAGEMASK_VDDC 0
195	203	#define SISLANDS_SMC_VOLTAGEMASK_MVDD 1
196	204	#define SISLANDS_SMC_VOLTAGEMASK_VDDCI 2
@@ -208,19 +216,19 @@ typedef struct SISLANDS_SMC_VOLTAGEMASKTABLE SISLANDS_SMC_VOLTAGEMASKTABLE; · 11 unmodified lines
208	216
209	217	struct SISLANDS_SMC_STATETABLE
210	218	{
211		− uint8_t thermalProtectType;
212		− uint8_t systemFlags;
213		− uint8_t maxVDDCIndexInPPTable;
214		− uint8_t extraFlags;
215		− uint32_t lowSMIO[SISLANDS_MAX_NO_VREG_STEPS];
216		− SISLANDS_SMC_VOLTAGEMASKTABLE voltageMaskTable;
217		− SISLANDS_SMC_VOLTAGEMASKTABLE phaseMaskTable;
218		− PP_SIslands_DPM2Parameters dpm2Params;
219		− SISLANDS_SMC_SWSTATE initialState;
220		− SISLANDS_SMC_SWSTATE ACPIState;
221		− SISLANDS_SMC_SWSTATE ULVState;
222		− SISLANDS_SMC_SWSTATE driverState;
223		− SISLANDS_SMC_HW_PERFORMANCE_LEVEL dpmLevels[SISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1];
	219	+ uint8_t thermalProtectType;
	220	+ uint8_t systemFlags;
	221	+ uint8_t maxVDDCIndexInPPTable;
	222	+ uint8_t extraFlags;
	223	+ uint32_t lowSMIO[SISLANDS_MAX_NO_VREG_STEPS];
	224	+ SISLANDS_SMC_VOLTAGEMASKTABLE voltageMaskTable;
	225	+ SISLANDS_SMC_VOLTAGEMASKTABLE phaseMaskTable;
	226	+ PP_SIslands_DPM2Parameters dpm2Params;
	227	+ struct SISLANDS_SMC_SWSTATE_SINGLE initialState;
	228	+ struct SISLANDS_SMC_SWSTATE_SINGLE ACPIState;
	229	+ struct SISLANDS_SMC_SWSTATE_SINGLE ULVState;
	230	+ SISLANDS_SMC_SWSTATE driverState;
	231	+ SISLANDS_SMC_HW_PERFORMANCE_LEVEL dpmLevels[SISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE];
224	232	};
225	233
226	234	typedef struct SISLANDS_SMC_STATETABLE SISLANDS_SMC_STATETABLE;

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c+9−0

@@ -2925,6 +2925,8 @@ static ssize_t navi1x_get_gpu_metrics(struct smu_context *smu, · 2924 unmodified lines
2925	2925
2926	2926	static int navi10_enable_mgpu_fan_boost(struct smu_context *smu)
2927	2927	{
	2928	+ struct smu_table_context *table_context = &smu->smu_table;
	2929	+ PPTable_t *smc_pptable = table_context->driver_pptable;
2928	2930	struct amdgpu_device *adev = smu->adev;
2929	2931	uint32_t param = 0;
2930	2932
@@ -2932,6 +2934,13 @@ static int navi10_enable_mgpu_fan_boost(struct smu_context *smu) · 1 unmodified line
2932	2934	if (adev->asic_type == CHIP_NAVI12)
2933	2935	return 0;
2934	2936
	2937	+ /*
	2938	+ * Skip the MGpuFanBoost setting for those ASICs
	2939	+ * which do not support it
	2940	+ */
	2941	+ if (!smc_pptable->MGpuFanBoostLimitRpm)
	2942	+ return 0;
	2943	+
2935	2944	/* Workaround for WS SKU */
2936	2945	if (adev->pdev->device == 0x7312 &&
2937	2946	adev->pdev->revision == 0)

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c+10−0

@@ -3027,6 +3027,16 @@ static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu, · 3026 unmodified lines
3027	3027
3028	3028	static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu)
3029	3029	{
	3030	+ struct smu_table_context *table_context = &smu->smu_table;
	3031	+ PPTable_t *smc_pptable = table_context->driver_pptable;
	3032	+
	3033	+ /*
	3034	+ * Skip the MGpuFanBoost setting for those ASICs
	3035	+ * which do not support it
	3036	+ */
	3037	+ if (!smc_pptable->MGpuFanBoostLimitRpm)
	3038	+ return 0;
	3039	+
3030	3040	return smu_cmn_send_smc_msg_with_param(smu,
3031	3041	SMU_MSG_SetMGpuFanBoostLimitRpm,
3032	3042	0,

drivers/gpu/drm/drm_auth.c+2−1

@@ -314,9 +314,10 @@ int drm_master_open(struct drm_file *file_priv) · 313 unmodified lines
314	314	void drm_master_release(struct drm_file *file_priv)
315	315	{
316	316	struct drm_device *dev = file_priv->minor->dev;
317		− struct drm_master *master = file_priv->master;
	317	+ struct drm_master *master;
318	318
319	319	mutex_lock(&dev->master_mutex);
	320	+ master = file_priv->master;
320	321	if (file_priv->magic)
321	322	idr_remove(&file_priv->master->magic_map, file_priv->magic);
322	323

drivers/gpu/drm/drm_ioctl.c+5−4

@@ -118,17 +118,18 @@ int drm_getunique(struct drm_device dev, void data, · 117 unmodified lines
118	118	struct drm_file *file_priv)
119	119	{
120	120	struct drm_unique *u = data;
121		− struct drm_master *master = file_priv->master;
	121	+ struct drm_master *master;
122	122
123		− mutex_lock(&master->dev->master_mutex);
	123	+ mutex_lock(&dev->master_mutex);
	124	+ master = file_priv->master;
124	125	if (u->unique_len >= master->unique_len) {
125	126	if (copy_to_user(u->unique, master->unique, master->unique_len)) {
126		− mutex_unlock(&master->dev->master_mutex);
	127	+ mutex_unlock(&dev->master_mutex);
127	128	return -EFAULT;
128	129	}
129	130	}
130	131	u->unique_len = master->unique_len;
131		− mutex_unlock(&master->dev->master_mutex);
	132	+ mutex_unlock(&dev->master_mutex);
132	133
133	134	return 0;
134	135	}

drivers/gpu/drm/exynos/exynos5433_drm_decon.c+1−3

@@ -815,10 +815,8 @@ static int exynos5433_decon_probe(struct platform_device *pdev) · 814 unmodified lines
815	815
816	816	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
817	817	ctx->addr = devm_ioremap_resource(dev, res);
818		− if (IS_ERR(ctx->addr)) {
819		− dev_err(dev, "ioremap failed\n");
	818	+ if (IS_ERR(ctx->addr))
820	819	return PTR_ERR(ctx->addr);
821		− }
822	820
823	821	ret = decon_conf_irq(ctx, "vsync", decon_irq_handler, 0);
824	822	if (ret < 0)

drivers/gpu/drm/exynos/exynos_drm_dsi.c+1−3

@@ -1786,10 +1786,8 @@ static int exynos_dsi_probe(struct platform_device *pdev) · 1785 unmodified lines
1786	1786
1787	1787	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1788	1788	dsi->reg_base = devm_ioremap_resource(dev, res);
1789		− if (IS_ERR(dsi->reg_base)) {
1790		− dev_err(dev, "failed to remap io region\n");
	1789	+ if (IS_ERR(dsi->reg_base))
1791	1790	return PTR_ERR(dsi->reg_base);
1792		− }
1793	1791
1794	1792	dsi->phy = devm_phy_get(dev, "dsim");
1795	1793	if (IS_ERR(dsi->phy)) {

drivers/gpu/drm/exynos/exynos_drm_fimd.c+1−1

@@ -723,7 +723,7 @@ static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win) · 722 unmodified lines
723	723	}
724	724
725	725	/**
726		− * shadow_protect_win() - disable updating values from shadow registers at vsync
	726	+ * fimd_shadow_protect_win() - disable updating values from shadow registers at vsync
727	727	*
728	728	* @ctx: local driver data
729	729	* @win: window to protect registers for

drivers/gpu/drm/i915/Kconfig+0−2

@@ -20,7 +20,6 @@ config DRM_I915 · 19 unmodified lines
20	20	select INPUT if ACPI
21	21	select ACPI_VIDEO if ACPI
22	22	select ACPI_BUTTON if ACPI
23		− select IO_MAPPING
24	23	select SYNC_FILE
25	24	select IOSF_MBI
26	25	select CRC32
@@ -102,7 +101,6 @@ config DRM_I915_GVT · 75 unmodified lines
102	101	bool "Enable Intel GVT-g graphics virtualization host support"
103	102	depends on DRM_I915
104	103	depends on 64BIT
105		− depends on VFIO_MDEV=y \|\| VFIO_MDEV=DRM_I915
106	104	default n
107	105	help
108	106	Choose this option if you want to enable Intel GVT-g graphics

drivers/gpu/drm/i915/display/intel_dp.c+6−55

@@ -1095,44 +1095,6 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, · 1094 unmodified lines
1095	1095	return -EINVAL;
1096	1096	}
1097	1097
1098		−/* Optimize link config in order: max bpp, min lanes, min clock */
1099		−static int
1100		−intel_dp_compute_link_config_fast(struct intel_dp *intel_dp,
1101		− struct intel_crtc_state *pipe_config,
1102		− const struct link_config_limits *limits)
1103		−{
1104		− const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1105		− int bpp, clock, lane_count;
1106		− int mode_rate, link_clock, link_avail;
1107		−
1108		− for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1109		− int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
1110		−
1111		− mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1112		− output_bpp);
1113		−
1114		− for (lane_count = limits->min_lane_count;
1115		− lane_count <= limits->max_lane_count;
1116		− lane_count <<= 1) {
1117		− for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
1118		− link_clock = intel_dp->common_rates[clock];
1119		− link_avail = intel_dp_max_data_rate(link_clock,
1120		− lane_count);
1121		−
1122		− if (mode_rate <= link_avail) {
1123		− pipe_config->lane_count = lane_count;
1124		− pipe_config->pipe_bpp = bpp;
1125		− pipe_config->port_clock = link_clock;
1126		−
1127		− return 0;
1128		− }
1129		− }
1130		− }
1131		− }
1132		−
1133		− return -EINVAL;
1134		−}
1135		−
1136	1098	static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
1137	1099	{
1138	1100	int i, num_bpc;
@@ -1382,22 +1344,11 @@ intel_dp_compute_link_config(struct intel_encoder *encoder, · 243 unmodified lines
1382	1344	intel_dp_can_bigjoiner(intel_dp))
1383	1345	pipe_config->bigjoiner = true;
1384	1346
1385		− if (intel_dp_is_edp(intel_dp))
1386		− /*
1387		− * Optimize for fast and narrow. eDP 1.3 section 3.3 and eDP 1.4
1388		− * section A.1: "It is recommended that the minimum number of
1389		− * lanes be used, using the minimum link rate allowed for that
1390		− * lane configuration."
1391		− *
1392		− * Note that we fall back to the max clock and lane count for eDP
1393		− * panels that fail with the fast optimal settings (see
1394		− * intel_dp->use_max_params), in which case the fast vs. wide
1395		− * choice doesn't matter.
1396		− */
1397		− ret = intel_dp_compute_link_config_fast(intel_dp, pipe_config, &limits);
1398		− else
1399		− /* Optimize for slow and wide. */
1400		− ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits);
	1347	+ /*
	1348	+ * Optimize for slow and wide for everything, because there are some
	1349	+ * eDP 1.3 and 1.4 panels don't work well with fast and narrow.
	1350	+ */
	1351	+ ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits);
1401	1352
1402	1353	/* enable compression if the mode doesn't fit available BW */
1403	1354	drm_dbg_kms(&i915->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en);
@@ -2160,7 +2111,7 @@ void intel_dp_check_frl_training(struct intel_dp *intel_dp) · 756 unmodified lines
2160	2111	* -PCON supports SRC_CTL_MODE (VESA DP2.0-HDMI2.1 PCON Spec Draft-1 Sec-7)
2161	2112	* -sink is HDMI2.1
2162	2113	*/
2163		− if (!(intel_dp->dpcd[2] & DP_PCON_SOURCE_CTL_MODE) \|\|
	2114	+ if (!(intel_dp->downstream_ports[2] & DP_PCON_SOURCE_CTL_MODE) \|\|
2164	2115	!intel_dp_is_hdmi_2_1_sink(intel_dp) \|\|
2165	2116	intel_dp->frl.is_trained)
2166	2117	return;

drivers/gpu/drm/i915/display/intel_dp_link_training.c+33−38

@@ -128,49 +128,13 @@ intel_dp_set_lttpr_transparent_mode(struct intel_dp *intel_dp, bool enable) · 127 unmodified lines
128	128	return drm_dp_dpcd_write(&intel_dp->aux, DP_PHY_REPEATER_MODE, &val, 1) == 1;
129	129	}
130	130
131		−/**
132		− * intel_dp_init_lttpr_and_dprx_caps - detect LTTPR and DPRX caps, init the LTTPR link training mode
133		− * @intel_dp: Intel DP struct
134		− *
135		− * Read the LTTPR common and DPRX capabilities and switch to non-transparent
136		− * link training mode if any is detected and read the PHY capabilities for all
137		− * detected LTTPRs. In case of an LTTPR detection error or if the number of
138		− * LTTPRs is more than is supported (8), fall back to the no-LTTPR,
139		− * transparent mode link training mode.
140		− *
141		− * Returns:
142		− * >0 if LTTPRs were detected and the non-transparent LT mode was set. The
143		− * DPRX capabilities are read out.
144		− * 0 if no LTTPRs or more than 8 LTTPRs were detected or in case of a
145		− * detection failure and the transparent LT mode was set. The DPRX
146		− * capabilities are read out.
147		− * <0 Reading out the DPRX capabilities failed.
148		− */
149		−int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp)
	131	+static int intel_dp_init_lttpr(struct intel_dp *intel_dp)
150	132	{
151	133	int lttpr_count;
152		− bool ret;
153	134	int i;
154	135
155		− ret = intel_dp_read_lttpr_common_caps(intel_dp);
156		−
157		− /* The DPTX shall read the DPRX caps after LTTPR detection. */
158		− if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd)) {
159		− intel_dp_reset_lttpr_common_caps(intel_dp);
160		− return -EIO;
161		− }
162		−
163		− if (!ret)
164		− return 0;
165		−
166		− /*
167		− * The 0xF0000-0xF02FF range is only valid if the DPCD revision is
168		− * at least 1.4.
169		− */
170		− if (intel_dp->dpcd[DP_DPCD_REV] < 0x14) {
171		− intel_dp_reset_lttpr_common_caps(intel_dp);
	136	+ if (!intel_dp_read_lttpr_common_caps(intel_dp))
172	137	return 0;
173		− }
174	138
175	139	lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);
176	140	/*
@@ -211,6 +175,37 @@ int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp) · 34 unmodified lines
211	175
212	176	return lttpr_count;
213	177	}
	178	+
	179	+/**
	180	+ * intel_dp_init_lttpr_and_dprx_caps - detect LTTPR and DPRX caps, init the LTTPR link training mode
	181	+ * @intel_dp: Intel DP struct
	182	+ *
	183	+ * Read the LTTPR common and DPRX capabilities and switch to non-transparent
	184	+ * link training mode if any is detected and read the PHY capabilities for all
	185	+ * detected LTTPRs. In case of an LTTPR detection error or if the number of
	186	+ * LTTPRs is more than is supported (8), fall back to the no-LTTPR,
	187	+ * transparent mode link training mode.
	188	+ *
	189	+ * Returns:
	190	+ * >0 if LTTPRs were detected and the non-transparent LT mode was set. The
	191	+ * DPRX capabilities are read out.
	192	+ * 0 if no LTTPRs or more than 8 LTTPRs were detected or in case of a
	193	+ * detection failure and the transparent LT mode was set. The DPRX
	194	+ * capabilities are read out.
	195	+ * <0 Reading out the DPRX capabilities failed.
	196	+ */
	197	+int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp)
	198	+{
	199	+ int lttpr_count = intel_dp_init_lttpr(intel_dp);
	200	+
	201	+ /* The DPTX shall read the DPRX caps after LTTPR detection. */
	202	+ if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd)) {
	203	+ intel_dp_reset_lttpr_common_caps(intel_dp);
	204	+ return -EIO;
	205	+ }
	206	+
	207	+ return lttpr_count;
	208	+}
214	209	EXPORT_SYMBOL(intel_dp_init_lttpr_and_dprx_caps);
215	210
216	211	static u8 dp_voltage_max(u8 preemph)

drivers/gpu/drm/i915/display/intel_overlay.c+1−1

@@ -383,7 +383,7 @@ static void intel_overlay_off_tail(struct intel_overlay *overlay) · 382 unmodified lines
383	383	i830_overlay_clock_gating(dev_priv, true);
384	384	}
385	385
386		−static void
	386	+__i915_active_call static void
387	387	intel_overlay_last_flip_retire(struct i915_active *active)
388	388	{
389	389	struct intel_overlay *overlay =

drivers/gpu/drm/i915/gem/i915_gem_mman.c+6−5

@@ -189,7 +189,7 @@ compute_partial_view(const struct drm_i915_gem_object *obj, · 188 unmodified lines
189	189	struct i915_ggtt_view view;
190	190
191	191	if (i915_gem_object_is_tiled(obj))
192		− chunk = roundup(chunk, tile_row_pages(obj));
	192	+ chunk = roundup(chunk, tile_row_pages(obj) ?: 1);
193	193
194	194	view.type = I915_GGTT_VIEW_PARTIAL;
195	195	view.partial.offset = rounddown(page_offset, chunk);
@@ -367,10 +367,11 @@ retry: · 171 unmodified lines
367	367	goto err_unpin;
368	368
369	369	/* Finally, remap it using the new GTT offset */
370		− ret = io_mapping_map_user(&ggtt->iomap, area, area->vm_start +
371		− (vma->ggtt_view.partial.offset << PAGE_SHIFT),
372		− (ggtt->gmadr.start + vma->node.start) >> PAGE_SHIFT,
373		− min_t(u64, vma->size, area->vm_end - area->vm_start));
	370	+ ret = remap_io_mapping(area,
	371	+ area->vm_start + (vma->ggtt_view.partial.offset << PAGE_SHIFT),
	372	+ (ggtt->gmadr.start + vma->node.start) >> PAGE_SHIFT,
	373	+ min_t(u64, vma->size, area->vm_end - area->vm_start),
	374	+ &ggtt->iomap);
374	375	if (ret)
375	376	goto err_fence;
376	377

drivers/gpu/drm/i915/gem/i915_gem_pages.c+2−0

@@ -63,6 +63,8 @@ void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj, · 62 unmodified lines
63	63	i915->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
64	64	GEM_BUG_ON(i915_gem_object_has_tiling_quirk(obj));
65	65	i915_gem_object_set_tiling_quirk(obj);
	66	+ GEM_BUG_ON(!list_empty(&obj->mm.link));
	67	+ atomic_inc(&obj->mm.shrink_pin);
66	68	shrinkable = false;
67	69	}
68	70

drivers/gpu/drm/i915/gt/gen7_renderclear.c+4−1

@@ -397,7 +397,10 @@ static void emit_batch(struct i915_vma * const vma, · 396 unmodified lines
397	397	gen7_emit_pipeline_invalidate(&cmds);
398	398	batch_add(&cmds, MI_LOAD_REGISTER_IMM(2));
399	399	batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_0_GEN7));
400		− batch_add(&cmds, 0xffff0000);
	400	+ batch_add(&cmds, 0xffff0000 \|
	401	+ ((IS_IVB_GT1(i915) \|\| IS_VALLEYVIEW(i915)) ?
	402	+ HIZ_RAW_STALL_OPT_DISABLE :
	403	+ 0));
401	404	batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_1));
402	405	batch_add(&cmds, 0xffff0000 \| PIXEL_SUBSPAN_COLLECT_OPT_DISABLE);
403	406	gen7_emit_pipeline_invalidate(&cmds);

drivers/gpu/drm/i915/gt/gen8_ppgtt.c+0−1

@@ -641,7 +641,6 @@ static int gen8_preallocate_top_level_pdp(struct i915_ppgtt *ppgtt) · 640 unmodified lines
641	641
642	642	err = pin_pt_dma(vm, pde->pt.base);
643	643	if (err) {
644		− i915_gem_object_put(pde->pt.base);
645	644	free_pd(vm, pde);
646	645	return err;
647	646	}

drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c+2−2

@@ -653,8 +653,8 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt) · 652 unmodified lines
653	653	* banks of memory are paired and unswizzled on the
654	654	* uneven portion, so leave that as unknown.
655	655	*/
656		− if (intel_uncore_read(uncore, C0DRB3) ==
657		− intel_uncore_read(uncore, C1DRB3)) {
	656	+ if (intel_uncore_read16(uncore, C0DRB3) ==
	657	+ intel_uncore_read16(uncore, C1DRB3)) {
658	658	swizzle_x = I915_BIT_6_SWIZZLE_9_10;
659	659	swizzle_y = I915_BIT_6_SWIZZLE_9;
660	660	}

drivers/gpu/drm/i915/gvt/gvt.c+2−122

@@ -46,118 +46,6 @@ static const char * const supported_hypervisors[] = { · 45 unmodified lines
46	46	[INTEL_GVT_HYPERVISOR_KVM] = "KVM",
47	47	};
48	48
49		−static struct intel_vgpu_type *
50		−intel_gvt_find_vgpu_type(struct intel_gvt *gvt, unsigned int type_group_id)
51		−{
52		− if (WARN_ON(type_group_id >= gvt->num_types))
53		− return NULL;
54		− return &gvt->types[type_group_id];
55		−}
56		−
57		−static ssize_t available_instances_show(struct mdev_type *mtype,
58		− struct mdev_type_attribute *attr,
59		− char *buf)
60		−{
61		− struct intel_vgpu_type *type;
62		− unsigned int num = 0;
63		− void *gvt = kdev_to_i915(mtype_get_parent_dev(mtype))->gvt;
64		−
65		− type = intel_gvt_find_vgpu_type(gvt, mtype_get_type_group_id(mtype));
66		− if (!type)
67		− num = 0;
68		− else
69		− num = type->avail_instance;
70		−
71		− return sprintf(buf, "%u\n", num);
72		−}
73		−
74		−static ssize_t device_api_show(struct mdev_type *mtype,
75		− struct mdev_type_attribute attr, char buf)
76		−{
77		− return sprintf(buf, "%s\n", VFIO_DEVICE_API_PCI_STRING);
78		−}
79		−
80		−static ssize_t description_show(struct mdev_type *mtype,
81		− struct mdev_type_attribute attr, char buf)
82		−{
83		− struct intel_vgpu_type *type;
84		− void *gvt = kdev_to_i915(mtype_get_parent_dev(mtype))->gvt;
85		−
86		− type = intel_gvt_find_vgpu_type(gvt, mtype_get_type_group_id(mtype));
87		− if (!type)
88		− return 0;
89		−
90		− return sprintf(buf, "low_gm_size: %dMB\nhigh_gm_size: %dMB\n"
91		− "fence: %d\nresolution: %s\n"
92		− "weight: %d\n",
93		− BYTES_TO_MB(type->low_gm_size),
94		− BYTES_TO_MB(type->high_gm_size),
95		− type->fence, vgpu_edid_str(type->resolution),
96		− type->weight);
97		−}
98		−
99		−static MDEV_TYPE_ATTR_RO(available_instances);
100		−static MDEV_TYPE_ATTR_RO(device_api);
101		−static MDEV_TYPE_ATTR_RO(description);
102		−
103		−static struct attribute *gvt_type_attrs[] = {
104		− &mdev_type_attr_available_instances.attr,
105		− &mdev_type_attr_device_api.attr,
106		− &mdev_type_attr_description.attr,
107		− NULL,
108		−};
109		−
110		−static struct attribute_group *gvt_vgpu_type_groups[] = {
111		− [0 ... NR_MAX_INTEL_VGPU_TYPES - 1] = NULL,
112		−};
113		−
114		−static bool intel_get_gvt_attrs(struct attribute_group ***intel_vgpu_type_groups)
115		−{
116		− *intel_vgpu_type_groups = gvt_vgpu_type_groups;
117		− return true;
118		−}
119		−
120		−static int intel_gvt_init_vgpu_type_groups(struct intel_gvt *gvt)
121		−{
122		− int i, j;
123		− struct intel_vgpu_type *type;
124		− struct attribute_group *group;
125		−
126		− for (i = 0; i < gvt->num_types; i++) {
127		− type = &gvt->types[i];
128		−
129		− group = kzalloc(sizeof(struct attribute_group), GFP_KERNEL);
130		− if (WARN_ON(!group))
131		− goto unwind;
132		−
133		− group->name = type->name;
134		− group->attrs = gvt_type_attrs;
135		− gvt_vgpu_type_groups[i] = group;
136		− }
137		−
138		− return 0;
139		−
140		−unwind:
141		− for (j = 0; j < i; j++) {
142		− group = gvt_vgpu_type_groups[j];
143		− kfree(group);
144		− }
145		−
146		− return -ENOMEM;
147		−}
148		−
149		−static void intel_gvt_cleanup_vgpu_type_groups(struct intel_gvt *gvt)
150		−{
151		− int i;
152		− struct attribute_group *group;
153		−
154		− for (i = 0; i < gvt->num_types; i++) {
155		− group = gvt_vgpu_type_groups[i];
156		− gvt_vgpu_type_groups[i] = NULL;
157		− kfree(group);
158		− }
159		−}
160		−
161	49	static const struct intel_gvt_ops intel_gvt_ops = {
162	50	.emulate_cfg_read = intel_vgpu_emulate_cfg_read,
163	51	.emulate_cfg_write = intel_vgpu_emulate_cfg_write,
@@ -169,8 +57,6 @@ static const struct intel_gvt_ops intel_gvt_ops = { · 5 unmodified lines
169	57	.vgpu_reset = intel_gvt_reset_vgpu,
170	58	.vgpu_activate = intel_gvt_activate_vgpu,
171	59	.vgpu_deactivate = intel_gvt_deactivate_vgpu,
172		− .gvt_find_vgpu_type = intel_gvt_find_vgpu_type,
173		− .get_gvt_attrs = intel_get_gvt_attrs,
174	60	.vgpu_query_plane = intel_vgpu_query_plane,
175	61	.vgpu_get_dmabuf = intel_vgpu_get_dmabuf,
176	62	.write_protect_handler = intel_vgpu_page_track_handler,
@@ -274,7 +160,6 @@ void intel_gvt_clean_device(struct drm_i915_private *i915) · 97 unmodified lines
274	160	return;
275	161
276	162	intel_gvt_destroy_idle_vgpu(gvt->idle_vgpu);
277		− intel_gvt_cleanup_vgpu_type_groups(gvt);
278	163	intel_gvt_clean_vgpu_types(gvt);
279	164
280	165	intel_gvt_debugfs_clean(gvt);
@@ -363,12 +248,6 @@ int intel_gvt_init_device(struct drm_i915_private *i915) · 82 unmodified lines
363	248	if (ret)
364	249	goto out_clean_thread;
365	250
366		− ret = intel_gvt_init_vgpu_type_groups(gvt);
367		− if (ret) {
368		− gvt_err("failed to init vgpu type groups: %d\n", ret);
369		− goto out_clean_types;
370		− }
371		−
372	251	vgpu = intel_gvt_create_idle_vgpu(gvt);
373	252	if (IS_ERR(vgpu)) {
374	253	ret = PTR_ERR(vgpu);
@@ -454,7 +333,8 @@ EXPORT_SYMBOL_GPL(intel_gvt_register_hypervisor); · 79 unmodified lines
454	333	void
455	334	intel_gvt_unregister_hypervisor(void)
456	335	{
457		− intel_gvt_hypervisor_host_exit(intel_gvt_host.dev);
	336	+ void gvt = (void )kdev_to_i915(intel_gvt_host.dev)->gvt;
	337	+ intel_gvt_hypervisor_host_exit(intel_gvt_host.dev, gvt);
458	338	module_put(THIS_MODULE);
459	339	}
460	340	EXPORT_SYMBOL_GPL(intel_gvt_unregister_hypervisor);

drivers/gpu/drm/i915/gvt/gvt.h+0−3

@@ -574,9 +574,6 @@ struct intel_gvt_ops { · 573 unmodified lines
574	574	void (vgpu_reset)(struct intel_vgpu );
575	575	void (vgpu_activate)(struct intel_vgpu );
576	576	void (vgpu_deactivate)(struct intel_vgpu );
577		− struct intel_vgpu_type (gvt_find_vgpu_type)(
578		− struct intel_gvt *gvt, unsigned int type_group_id);
579		− bool (get_gvt_attrs)(struct attribute_group **intel_vgpu_type_groups);
580	577	int (vgpu_query_plane)(struct intel_vgpu vgpu, void *);
581	578	int (vgpu_get_dmabuf)(struct intel_vgpu vgpu, unsigned int);
582	579	int (write_protect_handler)(struct intel_vgpu , u64, void *,

drivers/gpu/drm/i915/gvt/hypercall.h+1−1

@@ -49,7 +49,7 @@ enum hypervisor_type { · 48 unmodified lines
49	49	struct intel_gvt_mpt {
50	50	enum hypervisor_type type;
51	51	int (host_init)(struct device dev, void gvt, const void ops);
52		− void (host_exit)(struct device dev);
	52	+ void (host_exit)(struct device dev, void *gvt);
53	53	int (attach_vgpu)(void vgpu, unsigned long *handle);
54	54	void (detach_vgpu)(void vgpu);
55	55	int (*inject_msi)(unsigned long handle, u32 addr, u16 data);

drivers/gpu/drm/i915/gvt/kvmgt.c+113−9

@@ -144,6 +144,104 @@ static inline bool handle_valid(unsigned long handle) · 143 unmodified lines
144	144	return !!(handle & ~0xff);
145	145	}
146	146
	147	+static ssize_t available_instances_show(struct mdev_type *mtype,
	148	+ struct mdev_type_attribute *attr,
	149	+ char *buf)
	150	+{
	151	+ struct intel_vgpu_type *type;
	152	+ unsigned int num = 0;
	153	+ struct intel_gvt *gvt = kdev_to_i915(mtype_get_parent_dev(mtype))->gvt;
	154	+
	155	+ type = &gvt->types[mtype_get_type_group_id(mtype)];
	156	+ if (!type)
	157	+ num = 0;
	158	+ else
	159	+ num = type->avail_instance;
	160	+
	161	+ return sprintf(buf, "%u\n", num);
	162	+}
	163	+
	164	+static ssize_t device_api_show(struct mdev_type *mtype,
	165	+ struct mdev_type_attribute attr, char buf)
	166	+{
	167	+ return sprintf(buf, "%s\n", VFIO_DEVICE_API_PCI_STRING);
	168	+}
	169	+
	170	+static ssize_t description_show(struct mdev_type *mtype,
	171	+ struct mdev_type_attribute attr, char buf)
	172	+{
	173	+ struct intel_vgpu_type *type;
	174	+ struct intel_gvt *gvt = kdev_to_i915(mtype_get_parent_dev(mtype))->gvt;
	175	+
	176	+ type = &gvt->types[mtype_get_type_group_id(mtype)];
	177	+ if (!type)
	178	+ return 0;
	179	+
	180	+ return sprintf(buf, "low_gm_size: %dMB\nhigh_gm_size: %dMB\n"
	181	+ "fence: %d\nresolution: %s\n"
	182	+ "weight: %d\n",
	183	+ BYTES_TO_MB(type->low_gm_size),
	184	+ BYTES_TO_MB(type->high_gm_size),
	185	+ type->fence, vgpu_edid_str(type->resolution),
	186	+ type->weight);
	187	+}
	188	+
	189	+static MDEV_TYPE_ATTR_RO(available_instances);
	190	+static MDEV_TYPE_ATTR_RO(device_api);
	191	+static MDEV_TYPE_ATTR_RO(description);
	192	+
	193	+static struct attribute *gvt_type_attrs[] = {
	194	+ &mdev_type_attr_available_instances.attr,
	195	+ &mdev_type_attr_device_api.attr,
	196	+ &mdev_type_attr_description.attr,
	197	+ NULL,
	198	+};
	199	+
	200	+static struct attribute_group *gvt_vgpu_type_groups[] = {
	201	+ [0 ... NR_MAX_INTEL_VGPU_TYPES - 1] = NULL,
	202	+};
	203	+
	204	+static int intel_gvt_init_vgpu_type_groups(struct intel_gvt *gvt)
	205	+{
	206	+ int i, j;
	207	+ struct intel_vgpu_type *type;
	208	+ struct attribute_group *group;
	209	+
	210	+ for (i = 0; i < gvt->num_types; i++) {
	211	+ type = &gvt->types[i];
	212	+
	213	+ group = kzalloc(sizeof(struct attribute_group), GFP_KERNEL);
	214	+ if (!group)
	215	+ goto unwind;
	216	+
	217	+ group->name = type->name;
	218	+ group->attrs = gvt_type_attrs;
	219	+ gvt_vgpu_type_groups[i] = group;
	220	+ }
	221	+
	222	+ return 0;
	223	+
	224	+unwind:
	225	+ for (j = 0; j < i; j++) {
	226	+ group = gvt_vgpu_type_groups[j];
	227	+ kfree(group);
	228	+ }
	229	+
	230	+ return -ENOMEM;
	231	+}
	232	+
	233	+static void intel_gvt_cleanup_vgpu_type_groups(struct intel_gvt *gvt)
	234	+{
	235	+ int i;
	236	+ struct attribute_group *group;
	237	+
	238	+ for (i = 0; i < gvt->num_types; i++) {
	239	+ group = gvt_vgpu_type_groups[i];
	240	+ gvt_vgpu_type_groups[i] = NULL;
	241	+ kfree(group);
	242	+ }
	243	+}
	244	+
147	245	static int kvmgt_guest_init(struct mdev_device *mdev);
148	246	static void intel_vgpu_release_work(struct work_struct *work);
149	247	static bool kvmgt_guest_exit(struct kvmgt_guest_info *info);
@@ -694,14 +792,13 @@ static int intel_vgpu_create(struct mdev_device *mdev) · 544 unmodified lines
694	792	struct intel_vgpu *vgpu = NULL;
695	793	struct intel_vgpu_type *type;
696	794	struct device *pdev;
697		− void *gvt;
	795	+ struct intel_gvt *gvt;
698	796	int ret;
699	797
700	798	pdev = mdev_parent_dev(mdev);
701	799	gvt = kdev_to_i915(pdev)->gvt;
702	800
703		− type = intel_gvt_ops->gvt_find_vgpu_type(gvt,
704		− mdev_get_type_group_id(mdev));
	801	+ type = &gvt->types[mdev_get_type_group_id(mdev)];
705	802	if (!type) {
706	803	ret = -EINVAL;
707	804	goto out;
@@ -1667,19 +1764,26 @@ static struct mdev_parent_ops intel_vgpu_ops = { · 959 unmodified lines
1667	1764
1668	1765	static int kvmgt_host_init(struct device dev, void gvt, const void *ops)
1669	1766	{
1670		− struct attribute_group **kvm_vgpu_type_groups;
	1767	+ int ret;
	1768	+
	1769	+ ret = intel_gvt_init_vgpu_type_groups((struct intel_gvt *)gvt);
	1770	+ if (ret)
	1771	+ return ret;
1671	1772
1672	1773	intel_gvt_ops = ops;
1673		− if (!intel_gvt_ops->get_gvt_attrs(&kvm_vgpu_type_groups))
1674		− return -EFAULT;
1675		− intel_vgpu_ops.supported_type_groups = kvm_vgpu_type_groups;
	1774	+ intel_vgpu_ops.supported_type_groups = gvt_vgpu_type_groups;
1676	1775
1677		− return mdev_register_device(dev, &intel_vgpu_ops);
	1776	+ ret = mdev_register_device(dev, &intel_vgpu_ops);
	1777	+ if (ret)
	1778	+ intel_gvt_cleanup_vgpu_type_groups((struct intel_gvt *)gvt);
	1779	+
	1780	+ return ret;
1678	1781	}
1679	1782
1680		−static void kvmgt_host_exit(struct device *dev)
	1783	+static void kvmgt_host_exit(struct device dev, void gvt)
1681	1784	{
1682	1785	mdev_unregister_device(dev);
	1786	+ intel_gvt_cleanup_vgpu_type_groups((struct intel_gvt *)gvt);
1683	1787	}
1684	1788
1685	1789	static int kvmgt_page_track_add(unsigned long handle, u64 gfn)

drivers/gpu/drm/i915/gvt/mpt.h+2−2

@@ -63,13 +63,13 @@ static inline int intel_gvt_hypervisor_host_init(struct device *dev, · 62 unmodified lines
63	63	/**
64	64	* intel_gvt_hypervisor_host_exit - exit GVT-g host side
65	65	*/
66		−static inline void intel_gvt_hypervisor_host_exit(struct device *dev)
	66	+static inline void intel_gvt_hypervisor_host_exit(struct device dev, void gvt)
67	67	{
68	68	/* optional to provide */
69	69	if (!intel_gvt_host.mpt->host_exit)
70	70	return;
71	71
72		− intel_gvt_host.mpt->host_exit(dev);
	72	+ intel_gvt_host.mpt->host_exit(dev, gvt);
73	73	}
74	74
75	75	/**

drivers/gpu/drm/i915/i915_active.c+2−1

@@ -1156,7 +1156,8 @@ static int auto_active(struct i915_active *ref) · 1155 unmodified lines
1156	1156	return 0;
1157	1157	}
1158	1158
1159		−static void auto_retire(struct i915_active *ref)
	1159	+__i915_active_call static void
	1160	+auto_retire(struct i915_active *ref)
1160	1161	{
1161	1162	i915_active_put(ref);
1162	1163	}

drivers/gpu/drm/i915/i915_drv.h+3−0

@@ -1905,6 +1905,9 @@ int i915_reg_read_ioctl(struct drm_device dev, void data, · 1904 unmodified lines
1905	1905	struct drm_file *file);
1906	1906
1907	1907	/* i915_mm.c */
	1908	+int remap_io_mapping(struct vm_area_struct *vma,
	1909	+ unsigned long addr, unsigned long pfn, unsigned long size,
	1910	+ struct io_mapping *iomap);
1908	1911	int remap_io_sg(struct vm_area_struct *vma,
1909	1912	unsigned long addr, unsigned long size,
1910	1913	struct scatterlist *sgl, resource_size_t iobase);

drivers/gpu/drm/i915/i915_gem.c+5−6

@@ -999,12 +999,11 @@ i915_gem_madvise_ioctl(struct drm_device dev, void data, · 998 unmodified lines
999	999	obj->mm.madv = args->madv;
1000	1000
1001	1001	if (i915_gem_object_has_pages(obj)) {
1002		− struct list_head *list;
	1002	+ unsigned long flags;
1003	1003
1004		− if (i915_gem_object_is_shrinkable(obj)) {
1005		− unsigned long flags;
1006		−
1007		− spin_lock_irqsave(&i915->mm.obj_lock, flags);
	1004	+ spin_lock_irqsave(&i915->mm.obj_lock, flags);
	1005	+ if (!list_empty(&obj->mm.link)) {
	1006	+ struct list_head *list;
1008	1007
1009	1008	if (obj->mm.madv != I915_MADV_WILLNEED)
1010	1009	list = &i915->mm.purge_list;
@@ -1012,8 +1011,8 @@ i915_gem_madvise_ioctl(struct drm_device dev, void data, · 1 unmodified line
1012	1011	list = &i915->mm.shrink_list;
1013	1012	list_move_tail(&obj->mm.link, list);
1014	1013
1015		− spin_unlock_irqrestore(&i915->mm.obj_lock, flags);
1016	1014	}
	1015	+ spin_unlock_irqrestore(&i915->mm.obj_lock, flags);
1017	1016	}
1018	1017
1019	1018	/* if the object is no longer attached, discard its backing storage */

drivers/gpu/drm/i915/i915_mm.c+94−23

@@ -28,10 +28,90 @@ · 27 unmodified lines
28	28
29	29	#include "i915_drv.h"
30	30
31		−#define EXPECTED_FLAGS (VM_PFNMAP \| VM_DONTEXPAND \| VM_DONTDUMP)
	31	+struct remap_pfn {
	32	+ struct mm_struct *mm;
	33	+ unsigned long pfn;
	34	+ pgprot_t prot;
	35	+
	36	+ struct sgt_iter sgt;
	37	+ resource_size_t iobase;
	38	+};
	39	+
	40	+static int remap_pfn(pte_t pte, unsigned long addr, void data)
	41	+{
	42	+ struct remap_pfn *r = data;
	43	+
	44	+ /* Special PTE are not associated with any struct page */
	45	+ set_pte_at(r->mm, addr, pte, pte_mkspecial(pfn_pte(r->pfn, r->prot)));
	46	+ r->pfn++;
	47	+
	48	+ return 0;
	49	+}
32	50
33	51	#define use_dma(io) ((io) != -1)
34	52
	53	+static inline unsigned long sgt_pfn(const struct remap_pfn *r)
	54	+{
	55	+ if (use_dma(r->iobase))
	56	+ return (r->sgt.dma + r->sgt.curr + r->iobase) >> PAGE_SHIFT;
	57	+ else
	58	+ return r->sgt.pfn + (r->sgt.curr >> PAGE_SHIFT);
	59	+}
	60	+
	61	+static int remap_sg(pte_t pte, unsigned long addr, void data)
	62	+{
	63	+ struct remap_pfn *r = data;
	64	+
	65	+ if (GEM_WARN_ON(!r->sgt.sgp))
	66	+ return -EINVAL;
	67	+
	68	+ /* Special PTE are not associated with any struct page */
	69	+ set_pte_at(r->mm, addr, pte,
	70	+ pte_mkspecial(pfn_pte(sgt_pfn(r), r->prot)));
	71	+ r->pfn++; /* track insertions in case we need to unwind later */
	72	+
	73	+ r->sgt.curr += PAGE_SIZE;
	74	+ if (r->sgt.curr >= r->sgt.max)
	75	+ r->sgt = __sgt_iter(__sg_next(r->sgt.sgp), use_dma(r->iobase));
	76	+
	77	+ return 0;
	78	+}
	79	+
	80	+/**
	81	+ * remap_io_mapping - remap an IO mapping to userspace
	82	+ * @vma: user vma to map to
	83	+ * @addr: target user address to start at
	84	+ * @pfn: physical address of kernel memory
	85	+ * @size: size of map area
	86	+ * @iomap: the source io_mapping
	87	+ *
	88	+ * Note: this is only safe if the mm semaphore is held when called.
	89	+ */
	90	+int remap_io_mapping(struct vm_area_struct *vma,
	91	+ unsigned long addr, unsigned long pfn, unsigned long size,
	92	+ struct io_mapping *iomap)
	93	+{
	94	+ struct remap_pfn r;
	95	+ int err;
	96	+
	97	+#define EXPECTED_FLAGS (VM_PFNMAP \| VM_DONTEXPAND \| VM_DONTDUMP)
	98	+ GEM_BUG_ON((vma->vm_flags & EXPECTED_FLAGS) != EXPECTED_FLAGS);
	99	+
	100	+ /* We rely on prevalidation of the io-mapping to skip track_pfn(). */
	101	+ r.mm = vma->vm_mm;
	102	+ r.pfn = pfn;
	103	+ r.prot = __pgprot((pgprot_val(iomap->prot) & _PAGE_CACHE_MASK) \|
	104	+ (pgprot_val(vma->vm_page_prot) & ~_PAGE_CACHE_MASK));
	105	+
	106	+ err = apply_to_page_range(r.mm, addr, size, remap_pfn, &r);
	107	+ if (unlikely(err)) {
	108	+ zap_vma_ptes(vma, addr, (r.pfn - pfn) << PAGE_SHIFT);
	109	+ return err;
	110	+ }
	111	+
	112	+ return 0;
	113	+}
	114	+
35	115	/**
36	116	* remap_io_sg - remap an IO mapping to userspace
37	117	* @vma: user vma to map to
@@ -46,7 +126,12 @@ int remap_io_sg(struct vm_area_struct *vma, · 8 unmodified lines
46	126	unsigned long addr, unsigned long size,
47	127	struct scatterlist *sgl, resource_size_t iobase)
48	128	{
49		− unsigned long pfn, len, remapped = 0;
	129	+ struct remap_pfn r = {
	130	+ .mm = vma->vm_mm,
	131	+ .prot = vma->vm_page_prot,
	132	+ .sgt = __sgt_iter(sgl, use_dma(iobase)),
	133	+ .iobase = iobase,
	134	+ };
50	135	int err;
51	136
52	137	/* We rely on prevalidation of the io-mapping to skip track_pfn(). */
@@ -55,25 +140,11 @@ int remap_io_sg(struct vm_area_struct *vma, · 2 unmodified lines
55	140	if (!use_dma(iobase))
56	141	flush_cache_range(vma, addr, size);
57	142
58		− do {
59		− if (use_dma(iobase)) {
60		− if (!sg_dma_len(sgl))
61		− break;
62		− pfn = (sg_dma_address(sgl) + iobase) >> PAGE_SHIFT;
63		− len = sg_dma_len(sgl);
64		− } else {
65		− pfn = page_to_pfn(sg_page(sgl));
66		− len = sgl->length;
67		− }
68		−
69		− err = remap_pfn_range(vma, addr + remapped, pfn, len,
70		− vma->vm_page_prot);
71		− if (err)
72		− break;
73		− remapped += len;
74		− } while ((sgl = __sg_next(sgl)));
75		−
76		− if (err)
77		− zap_vma_ptes(vma, addr, remapped);
78		− return err;
	143	+ err = apply_to_page_range(r.mm, addr, size, remap_sg, &r);
	144	+ if (unlikely(err)) {
	145	+ zap_vma_ptes(vma, addr, r.pfn << PAGE_SHIFT);
	146	+ return err;
	147	+ }
	148	+
	149	+ return 0;
79	150	}

drivers/gpu/drm/i915/selftests/i915_request.c+2−2

@@ -1592,8 +1592,8 @@ static int live_breadcrumbs_smoketest(void *arg) · 1591 unmodified lines
1592	1592
1593	1593	for (n = 0; n < smoke[0].ncontexts; n++) {
1594	1594	smoke[0].contexts[n] = live_context(i915, file);
1595		− if (!smoke[0].contexts[n]) {
1596		− ret = -ENOMEM;
	1595	+ if (IS_ERR(smoke[0].contexts[n])) {
	1596	+ ret = PTR_ERR(smoke[0].contexts[n]);
1597	1597	goto out_contexts;
1598	1598	}
1599	1599	}

drivers/gpu/drm/mcde/mcde_dsi.c+1−1

@@ -577,7 +577,7 @@ static void mcde_dsi_setup_video_mode(struct mcde_dsi *d, · 576 unmodified lines
577	577	* porches and sync.
578	578	*/
579	579	/* (ps/s) / (pixels/s) = ps/pixels */
580		− pclk = DIV_ROUND_UP_ULL(1000000000000, mode->clock);
	580	+ pclk = DIV_ROUND_UP_ULL(1000000000000, (mode->clock * 1000));
581	581	dev_dbg(d->dev, "picoseconds between two pixels: %llu\n",
582	582	pclk);
583	583

drivers/gpu/drm/meson/meson_drv.c+5−4

@@ -485,11 +485,12 @@ static int meson_probe_remote(struct platform_device *pdev, · 484 unmodified lines
485	485	static void meson_drv_shutdown(struct platform_device *pdev)
486	486	{
487	487	struct meson_drm *priv = dev_get_drvdata(&pdev->dev);
488		− struct drm_device *drm = priv->drm;
489	488
490		− DRM_DEBUG_DRIVER("\n");
491		− drm_kms_helper_poll_fini(drm);
492		− drm_atomic_helper_shutdown(drm);
	489	+ if (!priv)
	490	+ return;
	491	+
	492	+ drm_kms_helper_poll_fini(priv->drm);
	493	+ drm_atomic_helper_shutdown(priv->drm);
493	494	}
494	495
495	496	static int meson_drv_probe(struct platform_device *pdev)

drivers/gpu/drm/msm/adreno/a6xx_gpu.c+119−45

@@ -157,7 +157,7 @@ static void a6xx_submit(struct msm_gpu gpu, struct msm_gem_submit submit) · 156 unmodified lines
157	157	* GPU registers so we need to add 0x1a800 to the register value on A630
158	158	* to get the right value from PM4.
159	159	*/
160		− get_stats_counter(ring, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L + 0x1a800,
	160	+ get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO,
161	161	rbmemptr_stats(ring, index, alwayson_start));
162	162
163	163	/* Invalidate CCU depth and color */
@@ -187,7 +187,7 @@ static void a6xx_submit(struct msm_gpu gpu, struct msm_gem_submit submit) · 23 unmodified lines
187	187
188	188	get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP_0_LO,
189	189	rbmemptr_stats(ring, index, cpcycles_end));
190		− get_stats_counter(ring, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L + 0x1a800,
	190	+ get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO,
191	191	rbmemptr_stats(ring, index, alwayson_end));
192	192
193	193	/* Write the fence to the scratch register */
@@ -206,8 +206,8 @@ static void a6xx_submit(struct msm_gpu gpu, struct msm_gem_submit submit) · 12 unmodified lines
206	206	OUT_RING(ring, submit->seqno);
207	207
208	208	trace_msm_gpu_submit_flush(submit,
209		− gmu_read64(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L,
210		− REG_A6XX_GMU_ALWAYS_ON_COUNTER_H));
	209	+ gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO,
	210	+ REG_A6XX_CP_ALWAYS_ON_COUNTER_HI));
211	211
212	212	a6xx_flush(gpu, ring);
213	213	}
@@ -462,6 +462,113 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) · 248 unmodified lines
462	462	gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? clock_cntl_on : 0);
463	463	}
464	464
	465	+/* For a615, a616, a618, A619, a630, a640 and a680 */
	466	+static const u32 a6xx_protect[] = {
	467	+ A6XX_PROTECT_RDONLY(0x00000, 0x04ff),
	468	+ A6XX_PROTECT_RDONLY(0x00501, 0x0005),
	469	+ A6XX_PROTECT_RDONLY(0x0050b, 0x02f4),
	470	+ A6XX_PROTECT_NORDWR(0x0050e, 0x0000),
	471	+ A6XX_PROTECT_NORDWR(0x00510, 0x0000),
	472	+ A6XX_PROTECT_NORDWR(0x00534, 0x0000),
	473	+ A6XX_PROTECT_NORDWR(0x00800, 0x0082),
	474	+ A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
	475	+ A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
	476	+ A6XX_PROTECT_RDONLY(0x008de, 0x00ae),
	477	+ A6XX_PROTECT_NORDWR(0x00900, 0x004d),
	478	+ A6XX_PROTECT_NORDWR(0x0098d, 0x0272),
	479	+ A6XX_PROTECT_NORDWR(0x00e00, 0x0001),
	480	+ A6XX_PROTECT_NORDWR(0x00e03, 0x000c),
	481	+ A6XX_PROTECT_NORDWR(0x03c00, 0x00c3),
	482	+ A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff),
	483	+ A6XX_PROTECT_NORDWR(0x08630, 0x01cf),
	484	+ A6XX_PROTECT_NORDWR(0x08e00, 0x0000),
	485	+ A6XX_PROTECT_NORDWR(0x08e08, 0x0000),
	486	+ A6XX_PROTECT_NORDWR(0x08e50, 0x001f),
	487	+ A6XX_PROTECT_NORDWR(0x09624, 0x01db),
	488	+ A6XX_PROTECT_NORDWR(0x09e70, 0x0001),
	489	+ A6XX_PROTECT_NORDWR(0x09e78, 0x0187),
	490	+ A6XX_PROTECT_NORDWR(0x0a630, 0x01cf),
	491	+ A6XX_PROTECT_NORDWR(0x0ae02, 0x0000),
	492	+ A6XX_PROTECT_NORDWR(0x0ae50, 0x032f),
	493	+ A6XX_PROTECT_NORDWR(0x0b604, 0x0000),
	494	+ A6XX_PROTECT_NORDWR(0x0be02, 0x0001),
	495	+ A6XX_PROTECT_NORDWR(0x0be20, 0x17df),
	496	+ A6XX_PROTECT_NORDWR(0x0f000, 0x0bff),
	497	+ A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
	498	+ A6XX_PROTECT_NORDWR(0x11c00, 0x0000), /* note: infinite range */
	499	+};
	500	+
	501	+/* These are for a620 and a650 */
	502	+static const u32 a650_protect[] = {
	503	+ A6XX_PROTECT_RDONLY(0x00000, 0x04ff),
	504	+ A6XX_PROTECT_RDONLY(0x00501, 0x0005),
	505	+ A6XX_PROTECT_RDONLY(0x0050b, 0x02f4),
	506	+ A6XX_PROTECT_NORDWR(0x0050e, 0x0000),
	507	+ A6XX_PROTECT_NORDWR(0x00510, 0x0000),
	508	+ A6XX_PROTECT_NORDWR(0x00534, 0x0000),
	509	+ A6XX_PROTECT_NORDWR(0x00800, 0x0082),
	510	+ A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
	511	+ A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
	512	+ A6XX_PROTECT_RDONLY(0x008de, 0x00ae),
	513	+ A6XX_PROTECT_NORDWR(0x00900, 0x004d),
	514	+ A6XX_PROTECT_NORDWR(0x0098d, 0x0272),
	515	+ A6XX_PROTECT_NORDWR(0x00e00, 0x0001),
	516	+ A6XX_PROTECT_NORDWR(0x00e03, 0x000c),
	517	+ A6XX_PROTECT_NORDWR(0x03c00, 0x00c3),
	518	+ A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff),
	519	+ A6XX_PROTECT_NORDWR(0x08630, 0x01cf),
	520	+ A6XX_PROTECT_NORDWR(0x08e00, 0x0000),
	521	+ A6XX_PROTECT_NORDWR(0x08e08, 0x0000),
	522	+ A6XX_PROTECT_NORDWR(0x08e50, 0x001f),
	523	+ A6XX_PROTECT_NORDWR(0x08e80, 0x027f),
	524	+ A6XX_PROTECT_NORDWR(0x09624, 0x01db),
	525	+ A6XX_PROTECT_NORDWR(0x09e60, 0x0011),
	526	+ A6XX_PROTECT_NORDWR(0x09e78, 0x0187),
	527	+ A6XX_PROTECT_NORDWR(0x0a630, 0x01cf),
	528	+ A6XX_PROTECT_NORDWR(0x0ae02, 0x0000),
	529	+ A6XX_PROTECT_NORDWR(0x0ae50, 0x032f),
	530	+ A6XX_PROTECT_NORDWR(0x0b604, 0x0000),
	531	+ A6XX_PROTECT_NORDWR(0x0b608, 0x0007),
	532	+ A6XX_PROTECT_NORDWR(0x0be02, 0x0001),
	533	+ A6XX_PROTECT_NORDWR(0x0be20, 0x17df),
	534	+ A6XX_PROTECT_NORDWR(0x0f000, 0x0bff),
	535	+ A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
	536	+ A6XX_PROTECT_NORDWR(0x18400, 0x1fff),
	537	+ A6XX_PROTECT_NORDWR(0x1a800, 0x1fff),
	538	+ A6XX_PROTECT_NORDWR(0x1f400, 0x0443),
	539	+ A6XX_PROTECT_RDONLY(0x1f844, 0x007b),
	540	+ A6XX_PROTECT_NORDWR(0x1f887, 0x001b),
	541	+ A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */
	542	+};
	543	+
	544	+static void a6xx_set_cp_protect(struct msm_gpu *gpu)
	545	+{
	546	+ struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
	547	+ const u32 *regs = a6xx_protect;
	548	+ unsigned i, count = ARRAY_SIZE(a6xx_protect), count_max = 32;
	549	+
	550	+ BUILD_BUG_ON(ARRAY_SIZE(a6xx_protect) > 32);
	551	+ BUILD_BUG_ON(ARRAY_SIZE(a650_protect) > 48);
	552	+
	553	+ if (adreno_is_a650(adreno_gpu)) {
	554	+ regs = a650_protect;
	555	+ count = ARRAY_SIZE(a650_protect);
	556	+ count_max = 48;
	557	+ }
	558	+
	559	+ /*
	560	+ * Enable access protection to privileged registers, fault on an access
	561	+ * protect violation and select the last span to protect from the start
	562	+ * address all the way to the end of the register address space
	563	+ */
	564	+ gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, BIT(0) \| BIT(1) \| BIT(3));
	565	+
	566	+ for (i = 0; i < count - 1; i++)
	567	+ gpu_write(gpu, REG_A6XX_CP_PROTECT(i), regs[i]);
	568	+ /* last CP_PROTECT to have "infinite" length on the last entry */
	569	+ gpu_write(gpu, REG_A6XX_CP_PROTECT(count_max - 1), regs[i]);
	570	+}
	571	+
465	572	static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
466	573	{
467	574	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
@@ -489,7 +596,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) · 21 unmodified lines
489	596	rgb565_predicator << 11 \| amsbc << 4 \| lower_bit << 1);
490	597	gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, lower_bit << 1);
491	598	gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL,
492		− uavflagprd_inv >> 4 \| lower_bit << 1);
	599	+ uavflagprd_inv << 4 \| lower_bit << 1);
493	600	gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, lower_bit << 21);
494	601	}
495	602
@@ -776,41 +883,7 @@ static int a6xx_hw_init(struct msm_gpu *gpu) · 280 unmodified lines
776	883	}
777	884
778	885	/* Protect registers from the CP */
779		− gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, 0x00000003);
780		−
781		− gpu_write(gpu, REG_A6XX_CP_PROTECT(0),
782		− A6XX_PROTECT_RDONLY(0x600, 0x51));
783		− gpu_write(gpu, REG_A6XX_CP_PROTECT(1), A6XX_PROTECT_RW(0xae50, 0x2));
784		− gpu_write(gpu, REG_A6XX_CP_PROTECT(2), A6XX_PROTECT_RW(0x9624, 0x13));
785		− gpu_write(gpu, REG_A6XX_CP_PROTECT(3), A6XX_PROTECT_RW(0x8630, 0x8));
786		− gpu_write(gpu, REG_A6XX_CP_PROTECT(4), A6XX_PROTECT_RW(0x9e70, 0x1));
787		− gpu_write(gpu, REG_A6XX_CP_PROTECT(5), A6XX_PROTECT_RW(0x9e78, 0x187));
788		− gpu_write(gpu, REG_A6XX_CP_PROTECT(6), A6XX_PROTECT_RW(0xf000, 0x810));
789		− gpu_write(gpu, REG_A6XX_CP_PROTECT(7),
790		− A6XX_PROTECT_RDONLY(0xfc00, 0x3));
791		− gpu_write(gpu, REG_A6XX_CP_PROTECT(8), A6XX_PROTECT_RW(0x50e, 0x0));
792		− gpu_write(gpu, REG_A6XX_CP_PROTECT(9), A6XX_PROTECT_RDONLY(0x50f, 0x0));
793		− gpu_write(gpu, REG_A6XX_CP_PROTECT(10), A6XX_PROTECT_RW(0x510, 0x0));
794		− gpu_write(gpu, REG_A6XX_CP_PROTECT(11),
795		− A6XX_PROTECT_RDONLY(0x0, 0x4f9));
796		− gpu_write(gpu, REG_A6XX_CP_PROTECT(12),
797		− A6XX_PROTECT_RDONLY(0x501, 0xa));
798		− gpu_write(gpu, REG_A6XX_CP_PROTECT(13),
799		− A6XX_PROTECT_RDONLY(0x511, 0x44));
800		− gpu_write(gpu, REG_A6XX_CP_PROTECT(14), A6XX_PROTECT_RW(0xe00, 0xe));
801		− gpu_write(gpu, REG_A6XX_CP_PROTECT(15), A6XX_PROTECT_RW(0x8e00, 0x0));
802		− gpu_write(gpu, REG_A6XX_CP_PROTECT(16), A6XX_PROTECT_RW(0x8e50, 0xf));
803		− gpu_write(gpu, REG_A6XX_CP_PROTECT(17), A6XX_PROTECT_RW(0xbe02, 0x0));
804		− gpu_write(gpu, REG_A6XX_CP_PROTECT(18),
805		− A6XX_PROTECT_RW(0xbe20, 0x11f3));
806		− gpu_write(gpu, REG_A6XX_CP_PROTECT(19), A6XX_PROTECT_RW(0x800, 0x82));
807		− gpu_write(gpu, REG_A6XX_CP_PROTECT(20), A6XX_PROTECT_RW(0x8a0, 0x8));
808		− gpu_write(gpu, REG_A6XX_CP_PROTECT(21), A6XX_PROTECT_RW(0x8ab, 0x19));
809		− gpu_write(gpu, REG_A6XX_CP_PROTECT(22), A6XX_PROTECT_RW(0x900, 0x4d));
810		− gpu_write(gpu, REG_A6XX_CP_PROTECT(23), A6XX_PROTECT_RW(0x98d, 0x76));
811		− gpu_write(gpu, REG_A6XX_CP_PROTECT(24),
812		− A6XX_PROTECT_RDONLY(0x980, 0x4));
813		− gpu_write(gpu, REG_A6XX_CP_PROTECT(25), A6XX_PROTECT_RW(0xa630, 0x0));
	886	+ a6xx_set_cp_protect(gpu);
814	887
815	888	/* Enable expanded apriv for targets that support it */
816	889	if (gpu->hw_apriv) {
@@ -1153,10 +1226,6 @@ static void a6xx_llc_slices_init(struct platform_device *pdev, · 336 unmodified lines
1153	1226	{
1154	1227	struct device_node *phandle;
1155	1228
1156		− a6xx_gpu->llc_mmio = msm_ioremap(pdev, "cx_mem", "gpu_cx");
1157		− if (IS_ERR(a6xx_gpu->llc_mmio))
1158		− return;
1159		−
1160	1229	/*
1161	1230	* There is a different programming path for targets with an mmu500
1162	1231	* attached, so detect if that is the case
@@ -1166,6 +1235,11 @@ static void a6xx_llc_slices_init(struct platform_device *pdev, · 3 unmodified lines
1166	1235	of_device_is_compatible(phandle, "arm,mmu-500"));
1167	1236	of_node_put(phandle);
1168	1237
	1238	+ if (a6xx_gpu->have_mmu500)
	1239	+ a6xx_gpu->llc_mmio = NULL;
	1240	+ else
	1241	+ a6xx_gpu->llc_mmio = msm_ioremap(pdev, "cx_mem", "gpu_cx");
	1242	+
1169	1243	a6xx_gpu->llc_slice = llcc_slice_getd(LLCC_GPU);
1170	1244	a6xx_gpu->htw_llc_slice = llcc_slice_getd(LLCC_GPUHTW);
1171	1245
@@ -1210,7 +1284,7 @@ static int a6xx_pm_suspend(struct msm_gpu *gpu) · 38 unmodified lines
1210	1284	if (ret)
1211	1285	return ret;
1212	1286
1213		− if (adreno_gpu->base.hw_apriv \|\| a6xx_gpu->has_whereami)
	1287	+ if (a6xx_gpu->shadow_bo)
1214	1288	for (i = 0; i < gpu->nr_rings; i++)
1215	1289	a6xx_gpu->shadow[i] = 0;
1216	1290

drivers/gpu/drm/msm/adreno/a6xx_gpu.h+1−1

@@ -44,7 +44,7 @@ struct a6xx_gpu { · 43 unmodified lines
44	44	* REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len
45	45	* registers starting at _reg.
46	46	*/
47		−#define A6XX_PROTECT_RW(_reg, _len) \
	47	+#define A6XX_PROTECT_NORDWR(_reg, _len) \
48	48	((1 << 31) \| \
49	49	(((_len) & 0x3FFF) << 18) \| ((_reg) & 0x3FFFF))
50	50

drivers/gpu/drm/msm/dp/dp_audio.c+1−0

@@ -527,6 +527,7 @@ int dp_audio_hw_params(struct device *dev, · 526 unmodified lines
527	527	dp_audio_setup_acr(audio);
528	528	dp_audio_safe_to_exit_level(audio);
529	529	dp_audio_enable(audio, true);
	530	+ dp_display_signal_audio_start(dp_display);
530	531	dp_display->audio_enabled = true;
531	532
532	533	end:

drivers/gpu/drm/msm/dp/dp_display.c+17−9

@@ -178,6 +178,15 @@ static int dp_del_event(struct dp_display_private *dp_priv, u32 event) · 177 unmodified lines
178	178	return 0;
179	179	}
180	180
	181	+void dp_display_signal_audio_start(struct msm_dp *dp_display)
	182	+{
	183	+ struct dp_display_private *dp;
	184	+
	185	+ dp = container_of(dp_display, struct dp_display_private, dp_display);
	186	+
	187	+ reinit_completion(&dp->audio_comp);
	188	+}
	189	+
181	190	void dp_display_signal_audio_complete(struct msm_dp *dp_display)
182	191	{
183	192	struct dp_display_private *dp;
@@ -586,10 +595,8 @@ static int dp_connect_pending_timeout(struct dp_display_private *dp, u32 data) · 402 unmodified lines
586	595	mutex_lock(&dp->event_mutex);
587	596
588	597	state = dp->hpd_state;
589		− if (state == ST_CONNECT_PENDING) {
590		− dp_display_enable(dp, 0);
	598	+ if (state == ST_CONNECT_PENDING)
591	599	dp->hpd_state = ST_CONNECTED;
592		− }
593	600
594	601	mutex_unlock(&dp->event_mutex);
595	602
@@ -651,7 +658,6 @@ static int dp_hpd_unplug_handle(struct dp_display_private *dp, u32 data) · 55 unmodified lines
651	658	dp_add_event(dp, EV_DISCONNECT_PENDING_TIMEOUT, 0, DP_TIMEOUT_5_SECOND);
652	659
653	660	/* signal the disconnect event early to ensure proper teardown */
654		− reinit_completion(&dp->audio_comp);
655	661	dp_display_handle_plugged_change(g_dp_display, false);
656	662
657	663	dp_catalog_hpd_config_intr(dp->catalog, DP_DP_HPD_PLUG_INT_MASK \|
@@ -669,10 +675,8 @@ static int dp_disconnect_pending_timeout(struct dp_display_private *dp, u32 data · 11 unmodified lines
669	675	mutex_lock(&dp->event_mutex);
670	676
671	677	state = dp->hpd_state;
672		− if (state == ST_DISCONNECT_PENDING) {
673		− dp_display_disable(dp, 0);
	678	+ if (state == ST_DISCONNECT_PENDING)
674	679	dp->hpd_state = ST_DISCONNECTED;
675		− }
676	680
677	681	mutex_unlock(&dp->event_mutex);
678	682
@@ -898,7 +902,6 @@ static int dp_display_disable(struct dp_display_private *dp, u32 data) · 219 unmodified lines
898	902	/* wait only if audio was enabled */
899	903	if (dp_display->audio_enabled) {
900	904	/* signal the disconnect event */
901		− reinit_completion(&dp->audio_comp);
902	905	dp_display_handle_plugged_change(dp_display, false);
903	906	if (!wait_for_completion_timeout(&dp->audio_comp,
904	907	HZ * 5))
@@ -1272,7 +1275,12 @@ static int dp_pm_resume(struct device *dev) · 367 unmodified lines
1272	1275
1273	1276	status = dp_catalog_link_is_connected(dp->catalog);
1274	1277
1275		− if (status)
	1278	+ /*
	1279	+ * can not declared display is connected unless
	1280	+ * HDMI cable is plugged in and sink_count of
	1281	+ * dongle become 1
	1282	+ */
	1283	+ if (status && dp->link->sink_count)
1276	1284	dp->dp_display.is_connected = true;
1277	1285	else
1278	1286	dp->dp_display.is_connected = false;

drivers/gpu/drm/msm/dp/dp_display.h+1−0

@@ -34,6 +34,7 @@ int dp_display_get_modes(struct msm_dp *dp_display, · 33 unmodified lines
34	34	int dp_display_request_irq(struct msm_dp *dp_display);
35	35	bool dp_display_check_video_test(struct msm_dp *dp_display);
36	36	int dp_display_get_test_bpp(struct msm_dp *dp_display);
	37	+void dp_display_signal_audio_start(struct msm_dp *dp_display);
37	38	void dp_display_signal_audio_complete(struct msm_dp *dp_display);
38	39
39	40	#endif /* _DP_DISPLAY_H_ */

drivers/gpu/drm/msm/dsi/phy/dsi_phy.c+1−1

@@ -843,7 +843,7 @@ int msm_dsi_phy_get_clk_provider(struct msm_dsi_phy *phy, · 842 unmodified lines
843	843	if (pixel_clk_provider)
844	844	*pixel_clk_provider = phy->provided_clocks->hws[DSI_PIXEL_PLL_CLK]->clk;
845	845
846		− return -EINVAL;
	846	+ return 0;
847	847	}
848	848
849	849	void msm_dsi_phy_pll_save_state(struct msm_dsi_phy *phy)

drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c+1−0

@@ -432,6 +432,7 @@ static unsigned long dsi_pll_10nm_vco_recalc_rate(struct clk_hw *hw, · 431 unmodified lines
432	432	pll_freq += div_u64(tmp64, multiplier);
433	433
434	434	vco_rate = pll_freq;
	435	+ pll_10nm->vco_current_rate = vco_rate;
435	436
436	437	DBG("DSI PLL%d returning vco rate = %lu, dec = %x, frac = %x",
437	438	pll_10nm->phy->id, (unsigned long)vco_rate, dec, frac);

drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c+4−0

@@ -405,6 +405,10 @@ static int pll_28nm_register(struct dsi_pll_28nm pll_28nm, struct clk_hw *prov · 404 unmodified lines
405	405	if (!vco_name)
406	406	return -ENOMEM;
407	407
	408	+ parent_name = devm_kzalloc(dev, 32, GFP_KERNEL);
	409	+ if (!parent_name)
	410	+ return -ENOMEM;
	411	+
408	412	clk_name = devm_kzalloc(dev, 32, GFP_KERNEL);
409	413	if (!clk_name)
410	414	return -ENOMEM;

drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c+1−0

@@ -460,6 +460,7 @@ static unsigned long dsi_pll_7nm_vco_recalc_rate(struct clk_hw *hw, · 459 unmodified lines
460	460	pll_freq += div_u64(tmp64, multiplier);
461	461
462	462	vco_rate = pll_freq;
	463	+ pll_7nm->vco_current_rate = vco_rate;
463	464
464	465	DBG("DSI PLL%d returning vco rate = %lu, dec = %x, frac = %x",
465	466	pll_7nm->phy->id, (unsigned long)vco_rate, dec, frac);

drivers/gpu/drm/msm/msm_drv.c+1−1

@@ -42,7 +42,7 @@ · 41 unmodified lines
42	42	* - 1.7.0 - Add MSM_PARAM_SUSPENDS to access suspend count
43	43	*/
44	44	#define MSM_VERSION_MAJOR 1
45		−#define MSM_VERSION_MINOR 6
	45	+#define MSM_VERSION_MINOR 7
46	46	#define MSM_VERSION_PATCHLEVEL 0
47	47
48	48	static const struct drm_mode_config_funcs mode_config_funcs = {

drivers/gpu/drm/msm/msm_gem.c+22−1

@@ -190,13 +190,25 @@ struct page *msm_gem_get_pages(struct drm_gem_object obj) · 189 unmodified lines
190	190	}
191	191
192	192	p = get_pages(obj);
	193	+
	194	+ if (!IS_ERR(p)) {
	195	+ msm_obj->pin_count++;
	196	+ update_inactive(msm_obj);
	197	+ }
	198	+
193	199	msm_gem_unlock(obj);
194	200	return p;
195	201	}
196	202
197	203	void msm_gem_put_pages(struct drm_gem_object *obj)
198	204	{
199		− /* when we start tracking the pin count, then do something here */
	205	+ struct msm_gem_object *msm_obj = to_msm_bo(obj);
	206	+
	207	+ msm_gem_lock(obj);
	208	+ msm_obj->pin_count--;
	209	+ GEM_WARN_ON(msm_obj->pin_count < 0);
	210	+ update_inactive(msm_obj);
	211	+ msm_gem_unlock(obj);
200	212	}
201	213
202	214	int msm_gem_mmap_obj(struct drm_gem_object *obj,
@@ -646,6 +658,8 @@ static void get_vaddr(struct drm_gem_object obj, unsigned madv) · 443 unmodified lines
646	658	ret = -ENOMEM;
647	659	goto fail;
648	660	}
	661	+
	662	+ update_inactive(msm_obj);
649	663	}
650	664
651	665	return msm_obj->vaddr;
@@ -1227,6 +1241,13 @@ static struct drm_gem_object _msm_gem_new(struct drm_device dev, · 575 unmodified lines
1227	1241
1228	1242	to_msm_bo(obj)->vram_node = &vma->node;
1229	1243
	1244	+ /* Call chain get_pages() -> update_inactive() tries to
	1245	+ * access msm_obj->mm_list, but it is not initialized yet.
	1246	+ * To avoid NULL pointer dereference error, initialize
	1247	+ * mm_list to be empty.
	1248	+ */
	1249	+ INIT_LIST_HEAD(&msm_obj->mm_list);
	1250	+
1230	1251	msm_gem_lock(obj);
1231	1252	pages = get_pages(obj);
1232	1253	msm_gem_unlock(obj);

drivers/gpu/drm/msm/msm_gem.h+2−2

@@ -221,7 +221,7 @@ static inline bool is_active(struct msm_gem_object *msm_obj) · 220 unmodified lines
221	221	/* imported/exported objects are not purgeable: */
222	222	static inline bool is_unpurgeable(struct msm_gem_object *msm_obj)
223	223	{
224		− return msm_obj->base.dma_buf && msm_obj->base.import_attach;
	224	+ return msm_obj->base.import_attach \|\| msm_obj->pin_count;
225	225	}
226	226
227	227	static inline bool is_purgeable(struct msm_gem_object *msm_obj)
@@ -271,7 +271,7 @@ static inline void mark_unpurgeable(struct msm_gem_object *msm_obj) · 43 unmodified lines
271	271
272	272	static inline bool is_unevictable(struct msm_gem_object *msm_obj)
273	273	{
274		− return is_unpurgeable(msm_obj) \|\| msm_obj->pin_count \|\| msm_obj->vaddr;
	274	+ return is_unpurgeable(msm_obj) \|\| msm_obj->vaddr;
275	275	}
276	276
277	277	static inline void mark_evictable(struct msm_gem_object *msm_obj)

drivers/gpu/drm/radeon/ni_dpm.c+73−71

@@ -1687,102 +1687,102 @@ static int ni_populate_smc_initial_state(struct radeon_device *rdev, · 1686 unmodified lines
1687	1687	u32 reg;
1688	1688	int ret;
1689	1689
1690		− table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
	1690	+ table->initialState.level.mclk.vMPLL_AD_FUNC_CNTL =
1691	1691	cpu_to_be32(ni_pi->clock_registers.mpll_ad_func_cntl);
1692		− table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL_2 =
	1692	+ table->initialState.level.mclk.vMPLL_AD_FUNC_CNTL_2 =
1693	1693	cpu_to_be32(ni_pi->clock_registers.mpll_ad_func_cntl_2);
1694		− table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
	1694	+ table->initialState.level.mclk.vMPLL_DQ_FUNC_CNTL =
1695	1695	cpu_to_be32(ni_pi->clock_registers.mpll_dq_func_cntl);
1696		− table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL_2 =
	1696	+ table->initialState.level.mclk.vMPLL_DQ_FUNC_CNTL_2 =
1697	1697	cpu_to_be32(ni_pi->clock_registers.mpll_dq_func_cntl_2);
1698		− table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
	1698	+ table->initialState.level.mclk.vMCLK_PWRMGT_CNTL =
1699	1699	cpu_to_be32(ni_pi->clock_registers.mclk_pwrmgt_cntl);
1700		− table->initialState.levels[0].mclk.vDLL_CNTL =
	1700	+ table->initialState.level.mclk.vDLL_CNTL =
1701	1701	cpu_to_be32(ni_pi->clock_registers.dll_cntl);
1702		− table->initialState.levels[0].mclk.vMPLL_SS =
	1702	+ table->initialState.level.mclk.vMPLL_SS =
1703	1703	cpu_to_be32(ni_pi->clock_registers.mpll_ss1);
1704		− table->initialState.levels[0].mclk.vMPLL_SS2 =
	1704	+ table->initialState.level.mclk.vMPLL_SS2 =
1705	1705	cpu_to_be32(ni_pi->clock_registers.mpll_ss2);
1706		− table->initialState.levels[0].mclk.mclk_value =
	1706	+ table->initialState.level.mclk.mclk_value =
1707	1707	cpu_to_be32(initial_state->performance_levels[0].mclk);
1708	1708
1709		− table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
	1709	+ table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL =
1710	1710	cpu_to_be32(ni_pi->clock_registers.cg_spll_func_cntl);
1711		− table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
	1711	+ table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_2 =
1712	1712	cpu_to_be32(ni_pi->clock_registers.cg_spll_func_cntl_2);
1713		− table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
	1713	+ table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_3 =
1714	1714	cpu_to_be32(ni_pi->clock_registers.cg_spll_func_cntl_3);
1715		− table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
	1715	+ table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_4 =
1716	1716	cpu_to_be32(ni_pi->clock_registers.cg_spll_func_cntl_4);
1717		− table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
	1717	+ table->initialState.level.sclk.vCG_SPLL_SPREAD_SPECTRUM =
1718	1718	cpu_to_be32(ni_pi->clock_registers.cg_spll_spread_spectrum);
1719		− table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
	1719	+ table->initialState.level.sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
1720	1720	cpu_to_be32(ni_pi->clock_registers.cg_spll_spread_spectrum_2);
1721		− table->initialState.levels[0].sclk.sclk_value =
	1721	+ table->initialState.level.sclk.sclk_value =
1722	1722	cpu_to_be32(initial_state->performance_levels[0].sclk);
1723		− table->initialState.levels[0].arbRefreshState =
	1723	+ table->initialState.level.arbRefreshState =
1724	1724	NISLANDS_INITIAL_STATE_ARB_INDEX;
1725	1725
1726		− table->initialState.levels[0].ACIndex = 0;
	1726	+ table->initialState.level.ACIndex = 0;
1727	1727
1728	1728	ret = ni_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
1729	1729	initial_state->performance_levels[0].vddc,
1730		− &table->initialState.levels[0].vddc);
	1730	+ &table->initialState.level.vddc);
1731	1731	if (!ret) {
1732	1732	u16 std_vddc;
1733	1733
1734	1734	ret = ni_get_std_voltage_value(rdev,
1735		− &table->initialState.levels[0].vddc,
	1735	+ &table->initialState.level.vddc,
1736	1736	&std_vddc);
1737	1737	if (!ret)
1738	1738	ni_populate_std_voltage_value(rdev, std_vddc,
1739		− table->initialState.levels[0].vddc.index,
1740		− &table->initialState.levels[0].std_vddc);
	1739	+ table->initialState.level.vddc.index,
	1740	+ &table->initialState.level.std_vddc);
1741	1741	}
1742	1742
1743	1743	if (eg_pi->vddci_control)
1744	1744	ni_populate_voltage_value(rdev,
1745	1745	&eg_pi->vddci_voltage_table,
1746	1746	initial_state->performance_levels[0].vddci,
1747		− &table->initialState.levels[0].vddci);
	1747	+ &table->initialState.level.vddci);
1748	1748
1749		− ni_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd);
	1749	+ ni_populate_initial_mvdd_value(rdev, &table->initialState.level.mvdd);
1750	1750
1751	1751	reg = CG_R(0xffff) \| CG_L(0);
1752		− table->initialState.levels[0].aT = cpu_to_be32(reg);
	1752	+ table->initialState.level.aT = cpu_to_be32(reg);
1753	1753
1754		− table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
	1754	+ table->initialState.level.bSP = cpu_to_be32(pi->dsp);
1755	1755
1756	1756	if (pi->boot_in_gen2)
1757		− table->initialState.levels[0].gen2PCIE = 1;
	1757	+ table->initialState.level.gen2PCIE = 1;
1758	1758	else
1759		− table->initialState.levels[0].gen2PCIE = 0;
	1759	+ table->initialState.level.gen2PCIE = 0;
1760	1760
1761	1761	if (pi->mem_gddr5) {
1762		− table->initialState.levels[0].strobeMode =
	1762	+ table->initialState.level.strobeMode =
1763	1763	cypress_get_strobe_mode_settings(rdev,
1764	1764	initial_state->performance_levels[0].mclk);
1765	1765
1766	1766	if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
1767		− table->initialState.levels[0].mcFlags = NISLANDS_SMC_MC_EDC_RD_FLAG \| NISLANDS_SMC_MC_EDC_WR_FLAG;
	1767	+ table->initialState.level.mcFlags = NISLANDS_SMC_MC_EDC_RD_FLAG \| NISLANDS_SMC_MC_EDC_WR_FLAG;
1768	1768	else
1769		− table->initialState.levels[0].mcFlags = 0;
	1769	+ table->initialState.level.mcFlags = 0;
1770	1770	}
1771	1771
1772	1772	table->initialState.levelCount = 1;
1773	1773
1774	1774	table->initialState.flags \|= PPSMC_SWSTATE_FLAG_DC;
1775	1775
1776		− table->initialState.levels[0].dpm2.MaxPS = 0;
1777		− table->initialState.levels[0].dpm2.NearTDPDec = 0;
1778		− table->initialState.levels[0].dpm2.AboveSafeInc = 0;
1779		− table->initialState.levels[0].dpm2.BelowSafeInc = 0;
	1776	+ table->initialState.level.dpm2.MaxPS = 0;
	1777	+ table->initialState.level.dpm2.NearTDPDec = 0;
	1778	+ table->initialState.level.dpm2.AboveSafeInc = 0;
	1779	+ table->initialState.level.dpm2.BelowSafeInc = 0;
1780	1780
1781	1781	reg = MIN_POWER_MASK \| MAX_POWER_MASK;
1782		− table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
	1782	+ table->initialState.level.SQPowerThrottle = cpu_to_be32(reg);
1783	1783
1784	1784	reg = MAX_POWER_DELTA_MASK \| STI_SIZE_MASK \| LTI_RATIO_MASK;
1785		− table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
	1785	+ table->initialState.level.SQPowerThrottle_2 = cpu_to_be32(reg);
1786	1786
1787	1787	return 0;
1788	1788	}
@@ -1813,43 +1813,43 @@ static int ni_populate_smc_acpi_state(struct radeon_device *rdev, · 24 unmodified lines
1813	1813	if (pi->acpi_vddc) {
1814	1814	ret = ni_populate_voltage_value(rdev,
1815	1815	&eg_pi->vddc_voltage_table,
1816		− pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
	1816	+ pi->acpi_vddc, &table->ACPIState.level.vddc);
1817	1817	if (!ret) {
1818	1818	u16 std_vddc;
1819	1819
1820	1820	ret = ni_get_std_voltage_value(rdev,
1821		− &table->ACPIState.levels[0].vddc, &std_vddc);
	1821	+ &table->ACPIState.level.vddc, &std_vddc);
1822	1822	if (!ret)
1823	1823	ni_populate_std_voltage_value(rdev, std_vddc,
1824		− table->ACPIState.levels[0].vddc.index,
1825		− &table->ACPIState.levels[0].std_vddc);
	1824	+ table->ACPIState.level.vddc.index,
	1825	+ &table->ACPIState.level.std_vddc);
1826	1826	}
1827	1827
1828	1828	if (pi->pcie_gen2) {
1829	1829	if (pi->acpi_pcie_gen2)
1830		− table->ACPIState.levels[0].gen2PCIE = 1;
	1830	+ table->ACPIState.level.gen2PCIE = 1;
1831	1831	else
1832		− table->ACPIState.levels[0].gen2PCIE = 0;
	1832	+ table->ACPIState.level.gen2PCIE = 0;
1833	1833	} else {
1834		− table->ACPIState.levels[0].gen2PCIE = 0;
	1834	+ table->ACPIState.level.gen2PCIE = 0;
1835	1835	}
1836	1836	} else {
1837	1837	ret = ni_populate_voltage_value(rdev,
1838	1838	&eg_pi->vddc_voltage_table,
1839	1839	pi->min_vddc_in_table,
1840		− &table->ACPIState.levels[0].vddc);
	1840	+ &table->ACPIState.level.vddc);
1841	1841	if (!ret) {
1842	1842	u16 std_vddc;
1843	1843
1844	1844	ret = ni_get_std_voltage_value(rdev,
1845		− &table->ACPIState.levels[0].vddc,
	1845	+ &table->ACPIState.level.vddc,
1846	1846	&std_vddc);
1847	1847	if (!ret)
1848	1848	ni_populate_std_voltage_value(rdev, std_vddc,
1849		− table->ACPIState.levels[0].vddc.index,
1850		− &table->ACPIState.levels[0].std_vddc);
	1849	+ table->ACPIState.level.vddc.index,
	1850	+ &table->ACPIState.level.std_vddc);
1851	1851	}
1852		− table->ACPIState.levels[0].gen2PCIE = 0;
	1852	+ table->ACPIState.level.gen2PCIE = 0;
1853	1853	}
1854	1854
1855	1855	if (eg_pi->acpi_vddci) {
@@ -1857,7 +1857,7 @@ static int ni_populate_smc_acpi_state(struct radeon_device *rdev, · 1 unmodified line
1857	1857	ni_populate_voltage_value(rdev,
1858	1858	&eg_pi->vddci_voltage_table,
1859	1859	eg_pi->acpi_vddci,
1860		− &table->ACPIState.levels[0].vddci);
	1860	+ &table->ACPIState.level.vddci);
1861	1861	}
1862	1862
1863	1863
@@ -1900,37 +1900,37 @@ static int ni_populate_smc_acpi_state(struct radeon_device *rdev, · 36 unmodified lines
1900	1900	spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
1901	1901	spll_func_cntl_2 \|= SCLK_MUX_SEL(4);
1902	1902
1903		− table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
1904		− table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2);
1905		− table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
1906		− table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2);
1907		− table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
1908		− table->ACPIState.levels[0].mclk.vDLL_CNTL = cpu_to_be32(dll_cntl);
	1903	+ table->ACPIState.level.mclk.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
	1904	+ table->ACPIState.level.mclk.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2);
	1905	+ table->ACPIState.level.mclk.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
	1906	+ table->ACPIState.level.mclk.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2);
	1907	+ table->ACPIState.level.mclk.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
	1908	+ table->ACPIState.level.mclk.vDLL_CNTL = cpu_to_be32(dll_cntl);
1909	1909
1910		− table->ACPIState.levels[0].mclk.mclk_value = 0;
	1910	+ table->ACPIState.level.mclk.mclk_value = 0;
1911	1911
1912		− table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
1913		− table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
1914		− table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
1915		− table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(spll_func_cntl_4);
	1912	+ table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
	1913	+ table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
	1914	+ table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
	1915	+ table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(spll_func_cntl_4);
1916	1916
1917		− table->ACPIState.levels[0].sclk.sclk_value = 0;
	1917	+ table->ACPIState.level.sclk.sclk_value = 0;
1918	1918
1919		− ni_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
	1919	+ ni_populate_mvdd_value(rdev, 0, &table->ACPIState.level.mvdd);
1920	1920
1921	1921	if (eg_pi->dynamic_ac_timing)
1922		− table->ACPIState.levels[0].ACIndex = 1;
	1922	+ table->ACPIState.level.ACIndex = 1;
1923	1923
1924		− table->ACPIState.levels[0].dpm2.MaxPS = 0;
1925		− table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
1926		− table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
1927		− table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
	1924	+ table->ACPIState.level.dpm2.MaxPS = 0;
	1925	+ table->ACPIState.level.dpm2.NearTDPDec = 0;
	1926	+ table->ACPIState.level.dpm2.AboveSafeInc = 0;
	1927	+ table->ACPIState.level.dpm2.BelowSafeInc = 0;
1928	1928
1929	1929	reg = MIN_POWER_MASK \| MAX_POWER_MASK;
1930		− table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
	1930	+ table->ACPIState.level.SQPowerThrottle = cpu_to_be32(reg);
1931	1931
1932	1932	reg = MAX_POWER_DELTA_MASK \| STI_SIZE_MASK \| LTI_RATIO_MASK;
1933		− table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
	1933	+ table->ACPIState.level.SQPowerThrottle_2 = cpu_to_be32(reg);
1934	1934
1935	1935	return 0;
1936	1936	}
@@ -1980,7 +1980,9 @@ static int ni_init_smc_table(struct radeon_device *rdev) · 43 unmodified lines
1980	1980	if (ret)
1981	1981	return ret;
1982	1982
1983		− table->driverState = table->initialState;
	1983	+ table->driverState.flags = table->initialState.flags;
	1984	+ table->driverState.levelCount = table->initialState.levelCount;
	1985	+ table->driverState.levels[0] = table->initialState.level;
1984	1986
1985	1987	table->ULVState = table->initialState;
1986	1988

drivers/gpu/drm/radeon/nislands_smc.h+21−13

@@ -143,6 +143,14 @@ struct NISLANDS_SMC_SWSTATE · 142 unmodified lines
143	143
144	144	typedef struct NISLANDS_SMC_SWSTATE NISLANDS_SMC_SWSTATE;
145	145
	146	+struct NISLANDS_SMC_SWSTATE_SINGLE {
	147	+ uint8_t flags;
	148	+ uint8_t levelCount;
	149	+ uint8_t padding2;
	150	+ uint8_t padding3;
	151	+ NISLANDS_SMC_HW_PERFORMANCE_LEVEL level;
	152	+};
	153	+
146	154	#define NISLANDS_SMC_VOLTAGEMASK_VDDC 0
147	155	#define NISLANDS_SMC_VOLTAGEMASK_MVDD 1
148	156	#define NISLANDS_SMC_VOLTAGEMASK_VDDCI 2
@@ -160,19 +168,19 @@ typedef struct NISLANDS_SMC_VOLTAGEMASKTABLE NISLANDS_SMC_VOLTAGEMASKTABLE; · 11 unmodified lines
160	168
161	169	struct NISLANDS_SMC_STATETABLE
162	170	{
163		− uint8_t thermalProtectType;
164		− uint8_t systemFlags;
165		− uint8_t maxVDDCIndexInPPTable;
166		− uint8_t extraFlags;
167		− uint8_t highSMIO[NISLANDS_MAX_NO_VREG_STEPS];
168		− uint32_t lowSMIO[NISLANDS_MAX_NO_VREG_STEPS];
169		− NISLANDS_SMC_VOLTAGEMASKTABLE voltageMaskTable;
170		− PP_NIslands_DPM2Parameters dpm2Params;
171		− NISLANDS_SMC_SWSTATE initialState;
172		− NISLANDS_SMC_SWSTATE ACPIState;
173		− NISLANDS_SMC_SWSTATE ULVState;
174		− NISLANDS_SMC_SWSTATE driverState;
175		− NISLANDS_SMC_HW_PERFORMANCE_LEVEL dpmLevels[NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1];
	171	+ uint8_t thermalProtectType;
	172	+ uint8_t systemFlags;
	173	+ uint8_t maxVDDCIndexInPPTable;
	174	+ uint8_t extraFlags;
	175	+ uint8_t highSMIO[NISLANDS_MAX_NO_VREG_STEPS];
	176	+ uint32_t lowSMIO[NISLANDS_MAX_NO_VREG_STEPS];
	177	+ NISLANDS_SMC_VOLTAGEMASKTABLE voltageMaskTable;
	178	+ PP_NIslands_DPM2Parameters dpm2Params;
	179	+ struct NISLANDS_SMC_SWSTATE_SINGLE initialState;
	180	+ struct NISLANDS_SMC_SWSTATE_SINGLE ACPIState;
	181	+ struct NISLANDS_SMC_SWSTATE_SINGLE ULVState;
	182	+ NISLANDS_SMC_SWSTATE driverState;
	183	+ NISLANDS_SMC_HW_PERFORMANCE_LEVEL dpmLevels[NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE];
176	184	};
177	185
178	186	typedef struct NISLANDS_SMC_STATETABLE NISLANDS_SMC_STATETABLE;

drivers/gpu/drm/radeon/radeon.h+1−0

@@ -1549,6 +1549,7 @@ struct radeon_dpm { · 1548 unmodified lines
1549	1549	void *priv;
1550	1550	u32 new_active_crtcs;
1551	1551	int new_active_crtc_count;
	1552	+ int high_pixelclock_count;
1552	1553	u32 current_active_crtcs;
1553	1554	int current_active_crtc_count;
1554	1555	bool single_display;

drivers/gpu/drm/radeon/radeon_gart.c+2−1

@@ -301,7 +301,8 @@ int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, · 300 unmodified lines
301	301	p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
302	302
303	303	for (i = 0; i < pages; i++, p++) {
304		− rdev->gart.pages[p] = pagelist[i];
	304	+ rdev->gart.pages[p] = pagelist ? pagelist[i] :
	305	+ rdev->dummy_page.page;
305	306	page_base = dma_addr[i];
306	307	for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
307	308	page_entry = radeon_gart_get_page_entry(page_base, flags);

drivers/gpu/drm/radeon/radeon_pm.c+8−0

@@ -1767,6 +1767,7 @@ static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev) · 1766 unmodified lines
1767	1767	struct drm_device *ddev = rdev->ddev;
1768	1768	struct drm_crtc *crtc;
1769	1769	struct radeon_crtc *radeon_crtc;
	1770	+ struct radeon_connector *radeon_connector;
1770	1771
1771	1772	if (!rdev->pm.dpm_enabled)
1772	1773	return;
@@ -1776,6 +1777,7 @@ static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev) · 3 unmodified lines
1776	1777	/* update active crtc counts */
1777	1778	rdev->pm.dpm.new_active_crtcs = 0;
1778	1779	rdev->pm.dpm.new_active_crtc_count = 0;
	1780	+ rdev->pm.dpm.high_pixelclock_count = 0;
1779	1781	if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
1780	1782	list_for_each_entry(crtc,
1781	1783	&ddev->mode_config.crtc_list, head) {
@@ -1783,6 +1785,12 @@ static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev) · 1 unmodified line
1783	1785	if (crtc->enabled) {
1784	1786	rdev->pm.dpm.new_active_crtcs \|= (1 << radeon_crtc->crtc_id);
1785	1787	rdev->pm.dpm.new_active_crtc_count++;
	1788	+ if (!radeon_crtc->connector)
	1789	+ continue;
	1790	+
	1791	+ radeon_connector = to_radeon_connector(radeon_crtc->connector);
	1792	+ if (radeon_connector->pixelclock_for_modeset > 297000)
	1793	+ rdev->pm.dpm.high_pixelclock_count++;
1786	1794	}
1787	1795	}
1788	1796	}

drivers/gpu/drm/radeon/radeon_uvd.c+2−2

@@ -286,7 +286,7 @@ int radeon_uvd_resume(struct radeon_device *rdev) · 285 unmodified lines
286	286	if (rdev->uvd.vcpu_bo == NULL)
287	287	return -EINVAL;
288	288
289		− memcpy(rdev->uvd.cpu_addr, rdev->uvd_fw->data, rdev->uvd_fw->size);
	289	+ memcpy_toio((void __iomem *)rdev->uvd.cpu_addr, rdev->uvd_fw->data, rdev->uvd_fw->size);
290	290
291	291	size = radeon_bo_size(rdev->uvd.vcpu_bo);
292	292	size -= rdev->uvd_fw->size;
@@ -294,7 +294,7 @@ int radeon_uvd_resume(struct radeon_device *rdev) · 1 unmodified line
294	294	ptr = rdev->uvd.cpu_addr;
295	295	ptr += rdev->uvd_fw->size;
296	296
297		− memset(ptr, 0, size);
	297	+ memset_io((void __iomem *)ptr, 0, size);
298	298
299	299	return 0;
300	300	}

drivers/gpu/drm/radeon/si_dpm.c+91−86

@@ -2979,6 +2979,9 @@ static void si_apply_state_adjust_rules(struct radeon_device *rdev, · 2978 unmodified lines
2979	2979	(rdev->pdev->device == 0x6605)) {
2980	2980	max_sclk = 75000;
2981	2981	}
	2982	+
	2983	+ if (rdev->pm.dpm.high_pixelclock_count > 1)
	2984	+ disable_sclk_switching = true;
2982	2985	}
2983	2986
2984	2987	if (rps->vce_active) {
@@ -4350,70 +4353,70 @@ static int si_populate_smc_initial_state(struct radeon_device *rdev, · 1365 unmodified lines
4350	4353	u32 reg;
4351	4354	int ret;
4352	4355
4353		− table->initialState.levels[0].mclk.vDLL_CNTL =
	4356	+ table->initialState.level.mclk.vDLL_CNTL =
4354	4357	cpu_to_be32(si_pi->clock_registers.dll_cntl);
4355		− table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
	4358	+ table->initialState.level.mclk.vMCLK_PWRMGT_CNTL =
4356	4359	cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4357		− table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
	4360	+ table->initialState.level.mclk.vMPLL_AD_FUNC_CNTL =
4358	4361	cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4359		− table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
	4362	+ table->initialState.level.mclk.vMPLL_DQ_FUNC_CNTL =
4360	4363	cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4361		− table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =
	4364	+ table->initialState.level.mclk.vMPLL_FUNC_CNTL =
4362	4365	cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4363		− table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
	4366	+ table->initialState.level.mclk.vMPLL_FUNC_CNTL_1 =
4364	4367	cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4365		− table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
	4368	+ table->initialState.level.mclk.vMPLL_FUNC_CNTL_2 =
4366	4369	cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4367		− table->initialState.levels[0].mclk.vMPLL_SS =
	4370	+ table->initialState.level.mclk.vMPLL_SS =
4368	4371	cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4369		− table->initialState.levels[0].mclk.vMPLL_SS2 =
	4372	+ table->initialState.level.mclk.vMPLL_SS2 =
4370	4373	cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4371	4374
4372		− table->initialState.levels[0].mclk.mclk_value =
	4375	+ table->initialState.level.mclk.mclk_value =
4373	4376	cpu_to_be32(initial_state->performance_levels[0].mclk);
4374	4377
4375		− table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
	4378	+ table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL =
4376	4379	cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4377		− table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
	4380	+ table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_2 =
4378	4381	cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4379		− table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
	4382	+ table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_3 =
4380	4383	cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4381		− table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
	4384	+ table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_4 =
4382	4385	cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4383		− table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
	4386	+ table->initialState.level.sclk.vCG_SPLL_SPREAD_SPECTRUM =
4384	4387	cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4385		− table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
	4388	+ table->initialState.level.sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
4386	4389	cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4387	4390
4388		− table->initialState.levels[0].sclk.sclk_value =
	4391	+ table->initialState.level.sclk.sclk_value =
4389	4392	cpu_to_be32(initial_state->performance_levels[0].sclk);
4390	4393
4391		− table->initialState.levels[0].arbRefreshState =
	4394	+ table->initialState.level.arbRefreshState =
4392	4395	SISLANDS_INITIAL_STATE_ARB_INDEX;
4393	4396
4394		− table->initialState.levels[0].ACIndex = 0;
	4397	+ table->initialState.level.ACIndex = 0;
4395	4398
4396	4399	ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4397	4400	initial_state->performance_levels[0].vddc,
4398		− &table->initialState.levels[0].vddc);
	4401	+ &table->initialState.level.vddc);
4399	4402
4400	4403	if (!ret) {
4401	4404	u16 std_vddc;
4402	4405
4403	4406	ret = si_get_std_voltage_value(rdev,
4404		− &table->initialState.levels[0].vddc,
	4407	+ &table->initialState.level.vddc,
4405	4408	&std_vddc);
4406	4409	if (!ret)
4407	4410	si_populate_std_voltage_value(rdev, std_vddc,
4408		− table->initialState.levels[0].vddc.index,
4409		− &table->initialState.levels[0].std_vddc);
	4411	+ table->initialState.level.vddc.index,
	4412	+ &table->initialState.level.std_vddc);
4410	4413	}
4411	4414
4412	4415	if (eg_pi->vddci_control)
4413	4416	si_populate_voltage_value(rdev,
4414	4417	&eg_pi->vddci_voltage_table,
4415	4418	initial_state->performance_levels[0].vddci,
4416		− &table->initialState.levels[0].vddci);
	4419	+ &table->initialState.level.vddci);
4417	4420
4418	4421	if (si_pi->vddc_phase_shed_control)
4419	4422	si_populate_phase_shedding_value(rdev,
@@ -4421,43 +4424,43 @@ static int si_populate_smc_initial_state(struct radeon_device *rdev, · 1 unmodified line
4421	4424	initial_state->performance_levels[0].vddc,
4422	4425	initial_state->performance_levels[0].sclk,
4423	4426	initial_state->performance_levels[0].mclk,
4424		− &table->initialState.levels[0].vddc);
	4427	+ &table->initialState.level.vddc);
4425	4428
4426		− si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd);
	4429	+ si_populate_initial_mvdd_value(rdev, &table->initialState.level.mvdd);
4427	4430
4428	4431	reg = CG_R(0xffff) \| CG_L(0);
4429		− table->initialState.levels[0].aT = cpu_to_be32(reg);
	4432	+ table->initialState.level.aT = cpu_to_be32(reg);
4430	4433
4431		− table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
	4434	+ table->initialState.level.bSP = cpu_to_be32(pi->dsp);
4432	4435
4433		− table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
	4436	+ table->initialState.level.gen2PCIE = (u8)si_pi->boot_pcie_gen;
4434	4437
4435	4438	if (pi->mem_gddr5) {
4436		− table->initialState.levels[0].strobeMode =
	4439	+ table->initialState.level.strobeMode =
4437	4440	si_get_strobe_mode_settings(rdev,
4438	4441	initial_state->performance_levels[0].mclk);
4439	4442
4440	4443	if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4441		− table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG \| SISLANDS_SMC_MC_EDC_WR_FLAG;
	4444	+ table->initialState.level.mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG \| SISLANDS_SMC_MC_EDC_WR_FLAG;
4442	4445	else
4443		− table->initialState.levels[0].mcFlags = 0;
	4446	+ table->initialState.level.mcFlags = 0;
4444	4447	}
4445	4448
4446	4449	table->initialState.levelCount = 1;
4447	4450
4448	4451	table->initialState.flags \|= PPSMC_SWSTATE_FLAG_DC;
4449	4452
4450		− table->initialState.levels[0].dpm2.MaxPS = 0;
4451		− table->initialState.levels[0].dpm2.NearTDPDec = 0;
4452		− table->initialState.levels[0].dpm2.AboveSafeInc = 0;
4453		− table->initialState.levels[0].dpm2.BelowSafeInc = 0;
4454		− table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;
	4453	+ table->initialState.level.dpm2.MaxPS = 0;
	4454	+ table->initialState.level.dpm2.NearTDPDec = 0;
	4455	+ table->initialState.level.dpm2.AboveSafeInc = 0;
	4456	+ table->initialState.level.dpm2.BelowSafeInc = 0;
	4457	+ table->initialState.level.dpm2.PwrEfficiencyRatio = 0;
4455	4458
4456	4459	reg = MIN_POWER_MASK \| MAX_POWER_MASK;
4457		− table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
	4460	+ table->initialState.level.SQPowerThrottle = cpu_to_be32(reg);
4458	4461
4459	4462	reg = MAX_POWER_DELTA_MASK \| STI_SIZE_MASK \| LTI_RATIO_MASK;
4460		− table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
	4463	+ table->initialState.level.SQPowerThrottle_2 = cpu_to_be32(reg);
4461	4464
4462	4465	return 0;
4463	4466	}
@@ -4488,18 +4491,18 @@ static int si_populate_smc_acpi_state(struct radeon_device *rdev, · 24 unmodified lines
4488	4491
4489	4492	if (pi->acpi_vddc) {
4490	4493	ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4491		− pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
	4494	+ pi->acpi_vddc, &table->ACPIState.level.vddc);
4492	4495	if (!ret) {
4493	4496	u16 std_vddc;
4494	4497
4495	4498	ret = si_get_std_voltage_value(rdev,
4496		− &table->ACPIState.levels[0].vddc, &std_vddc);
	4499	+ &table->ACPIState.level.vddc, &std_vddc);
4497	4500	if (!ret)
4498	4501	si_populate_std_voltage_value(rdev, std_vddc,
4499		− table->ACPIState.levels[0].vddc.index,
4500		− &table->ACPIState.levels[0].std_vddc);
	4502	+ table->ACPIState.level.vddc.index,
	4503	+ &table->ACPIState.level.std_vddc);
4501	4504	}
4502		− table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;
	4505	+ table->ACPIState.level.gen2PCIE = si_pi->acpi_pcie_gen;
4503	4506
4504	4507	if (si_pi->vddc_phase_shed_control) {
4505	4508	si_populate_phase_shedding_value(rdev,
@@ -4507,23 +4510,23 @@ static int si_populate_smc_acpi_state(struct radeon_device *rdev, · 1 unmodified line
4507	4510	pi->acpi_vddc,
4508	4511	0,
4509	4512	0,
4510		− &table->ACPIState.levels[0].vddc);
	4513	+ &table->ACPIState.level.vddc);
4511	4514	}
4512	4515	} else {
4513	4516	ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4514		− pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);
	4517	+ pi->min_vddc_in_table, &table->ACPIState.level.vddc);
4515	4518	if (!ret) {
4516	4519	u16 std_vddc;
4517	4520
4518	4521	ret = si_get_std_voltage_value(rdev,
4519		− &table->ACPIState.levels[0].vddc, &std_vddc);
	4522	+ &table->ACPIState.level.vddc, &std_vddc);
4520	4523
4521	4524	if (!ret)
4522	4525	si_populate_std_voltage_value(rdev, std_vddc,
4523		− table->ACPIState.levels[0].vddc.index,
4524		− &table->ACPIState.levels[0].std_vddc);
	4526	+ table->ACPIState.level.vddc.index,
	4527	+ &table->ACPIState.level.std_vddc);
4525	4528	}
4526		− table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev,
	4529	+ table->ACPIState.level.gen2PCIE = (u8)r600_get_pcie_gen_support(rdev,
4527	4530	si_pi->sys_pcie_mask,
4528	4531	si_pi->boot_pcie_gen,
4529	4532	RADEON_PCIE_GEN1);
@@ -4534,14 +4537,14 @@ static int si_populate_smc_acpi_state(struct radeon_device *rdev, · 4 unmodified lines
4534	4537	pi->min_vddc_in_table,
4535	4538	0,
4536	4539	0,
4537		− &table->ACPIState.levels[0].vddc);
	4540	+ &table->ACPIState.level.vddc);
4538	4541	}
4539	4542
4540	4543	if (pi->acpi_vddc) {
4541	4544	if (eg_pi->acpi_vddci)
4542	4545	si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
4543	4546	eg_pi->acpi_vddci,
4544		− &table->ACPIState.levels[0].vddci);
	4547	+ &table->ACPIState.level.vddci);
4545	4548	}
4546	4549
4547	4550	mclk_pwrmgt_cntl \|= MRDCK0_RESET \| MRDCK1_RESET;
@@ -4552,59 +4555,59 @@ static int si_populate_smc_acpi_state(struct radeon_device *rdev, · 4 unmodified lines
4552	4555	spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4553	4556	spll_func_cntl_2 \|= SCLK_MUX_SEL(4);
4554	4557
4555		− table->ACPIState.levels[0].mclk.vDLL_CNTL =
	4558	+ table->ACPIState.level.mclk.vDLL_CNTL =
4556	4559	cpu_to_be32(dll_cntl);
4557		− table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
	4560	+ table->ACPIState.level.mclk.vMCLK_PWRMGT_CNTL =
4558	4561	cpu_to_be32(mclk_pwrmgt_cntl);
4559		− table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
	4562	+ table->ACPIState.level.mclk.vMPLL_AD_FUNC_CNTL =
4560	4563	cpu_to_be32(mpll_ad_func_cntl);
4561		− table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
	4564	+ table->ACPIState.level.mclk.vMPLL_DQ_FUNC_CNTL =
4562	4565	cpu_to_be32(mpll_dq_func_cntl);
4563		− table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =
	4566	+ table->ACPIState.level.mclk.vMPLL_FUNC_CNTL =
4564	4567	cpu_to_be32(mpll_func_cntl);
4565		− table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
	4568	+ table->ACPIState.level.mclk.vMPLL_FUNC_CNTL_1 =
4566	4569	cpu_to_be32(mpll_func_cntl_1);
4567		− table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
	4570	+ table->ACPIState.level.mclk.vMPLL_FUNC_CNTL_2 =
4568	4571	cpu_to_be32(mpll_func_cntl_2);
4569		− table->ACPIState.levels[0].mclk.vMPLL_SS =
	4572	+ table->ACPIState.level.mclk.vMPLL_SS =
4570	4573	cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4571		− table->ACPIState.levels[0].mclk.vMPLL_SS2 =
	4574	+ table->ACPIState.level.mclk.vMPLL_SS2 =
4572	4575	cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4573	4576
4574		− table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
	4577	+ table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL =
4575	4578	cpu_to_be32(spll_func_cntl);
4576		− table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
	4579	+ table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_2 =
4577	4580	cpu_to_be32(spll_func_cntl_2);
4578		− table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
	4581	+ table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_3 =
4579	4582	cpu_to_be32(spll_func_cntl_3);
4580		− table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
	4583	+ table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_4 =
4581	4584	cpu_to_be32(spll_func_cntl_4);
4582	4585
4583		− table->ACPIState.levels[0].mclk.mclk_value = 0;
4584		− table->ACPIState.levels[0].sclk.sclk_value = 0;
	4586	+ table->ACPIState.level.mclk.mclk_value = 0;
	4587	+ table->ACPIState.level.sclk.sclk_value = 0;
4585	4588
4586		− si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
	4589	+ si_populate_mvdd_value(rdev, 0, &table->ACPIState.level.mvdd);
4587	4590
4588	4591	if (eg_pi->dynamic_ac_timing)
4589		− table->ACPIState.levels[0].ACIndex = 0;
	4592	+ table->ACPIState.level.ACIndex = 0;
4590	4593
4591		− table->ACPIState.levels[0].dpm2.MaxPS = 0;
4592		− table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
4593		− table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
4594		− table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
4595		− table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;
	4594	+ table->ACPIState.level.dpm2.MaxPS = 0;
	4595	+ table->ACPIState.level.dpm2.NearTDPDec = 0;
	4596	+ table->ACPIState.level.dpm2.AboveSafeInc = 0;
	4597	+ table->ACPIState.level.dpm2.BelowSafeInc = 0;
	4598	+ table->ACPIState.level.dpm2.PwrEfficiencyRatio = 0;
4596	4599
4597	4600	reg = MIN_POWER_MASK \| MAX_POWER_MASK;
4598		− table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
	4601	+ table->ACPIState.level.SQPowerThrottle = cpu_to_be32(reg);
4599	4602
4600	4603	reg = MAX_POWER_DELTA_MASK \| STI_SIZE_MASK \| LTI_RATIO_MASK;
4601		− table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
	4604	+ table->ACPIState.level.SQPowerThrottle_2 = cpu_to_be32(reg);
4602	4605
4603	4606	return 0;
4604	4607	}
4605	4608
4606	4609	static int si_populate_ulv_state(struct radeon_device *rdev,
4607		− SISLANDS_SMC_SWSTATE *state)
	4610	+ struct SISLANDS_SMC_SWSTATE_SINGLE *state)
4608	4611	{
4609	4612	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4610	4613	struct si_power_info *si_pi = si_get_pi(rdev);
@@ -4613,19 +4616,19 @@ static int si_populate_ulv_state(struct radeon_device *rdev, · 2 unmodified lines
4613	4616	int ret;
4614	4617
4615	4618	ret = si_convert_power_level_to_smc(rdev, &ulv->pl,
4616		− &state->levels[0]);
	4619	+ &state->level);
4617	4620	if (!ret) {
4618	4621	if (eg_pi->sclk_deep_sleep) {
4619	4622	if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
4620		− state->levels[0].stateFlags \|= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
	4623	+ state->level.stateFlags \|= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
4621	4624	else
4622		− state->levels[0].stateFlags \|= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
	4625	+ state->level.stateFlags \|= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
4623	4626	}
4624	4627	if (ulv->one_pcie_lane_in_ulv)
4625	4628	state->flags \|= PPSMC_SWSTATE_FLAG_PCIE_X1;
4626		− state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
4627		− state->levels[0].ACIndex = 1;
4628		− state->levels[0].std_vddc = state->levels[0].vddc;
	4629	+ state->level.arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
	4630	+ state->level.ACIndex = 1;
	4631	+ state->level.std_vddc = state->level.vddc;
4629	4632	state->levelCount = 1;
4630	4633
4631	4634	state->flags \|= PPSMC_SWSTATE_FLAG_DC;
@@ -4725,7 +4728,9 @@ static int si_init_smc_table(struct radeon_device *rdev) · 93 unmodified lines
4725	4728	if (ret)
4726	4729	return ret;
4727	4730
4728		− table->driverState = table->initialState;
	4731	+ table->driverState.flags = table->initialState.flags;
	4732	+ table->driverState.levelCount = table->initialState.levelCount;
	4733	+ table->driverState.levels[0] = table->initialState.level;
4729	4734
4730	4735	ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state,
4731	4736	SISLANDS_INITIAL_STATE_ARB_INDEX);
@@ -5275,8 +5280,8 @@ static int si_upload_ulv_state(struct radeon_device *rdev) · 543 unmodified lines
5275	5280	if (ulv->supported && ulv->pl.vddc) {
5276	5281	u32 address = si_pi->state_table_start +
5277	5282	offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5278		− SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;
5279		− u32 state_size = sizeof(SISLANDS_SMC_SWSTATE);
	5283	+ struct SISLANDS_SMC_SWSTATE_SINGLE *smc_state = &si_pi->smc_statetable.ULVState;
	5284	+ u32 state_size = sizeof(struct SISLANDS_SMC_SWSTATE_SINGLE);
5280	5285
5281	5286	memset(smc_state, 0, state_size);
5282	5287

drivers/gpu/drm/radeon/sislands_smc.h+21−13

@@ -191,6 +191,14 @@ struct SISLANDS_SMC_SWSTATE · 190 unmodified lines
191	191
192	192	typedef struct SISLANDS_SMC_SWSTATE SISLANDS_SMC_SWSTATE;
193	193
	194	+struct SISLANDS_SMC_SWSTATE_SINGLE {
	195	+ uint8_t flags;
	196	+ uint8_t levelCount;
	197	+ uint8_t padding2;
	198	+ uint8_t padding3;
	199	+ SISLANDS_SMC_HW_PERFORMANCE_LEVEL level;
	200	+};
	201	+
194	202	#define SISLANDS_SMC_VOLTAGEMASK_VDDC 0
195	203	#define SISLANDS_SMC_VOLTAGEMASK_MVDD 1
196	204	#define SISLANDS_SMC_VOLTAGEMASK_VDDCI 2
@@ -208,19 +216,19 @@ typedef struct SISLANDS_SMC_VOLTAGEMASKTABLE SISLANDS_SMC_VOLTAGEMASKTABLE; · 11 unmodified lines
208	216
209	217	struct SISLANDS_SMC_STATETABLE
210	218	{
211		− uint8_t thermalProtectType;
212		− uint8_t systemFlags;
213		− uint8_t maxVDDCIndexInPPTable;
214		− uint8_t extraFlags;
215		− uint32_t lowSMIO[SISLANDS_MAX_NO_VREG_STEPS];
216		− SISLANDS_SMC_VOLTAGEMASKTABLE voltageMaskTable;
217		− SISLANDS_SMC_VOLTAGEMASKTABLE phaseMaskTable;
218		− PP_SIslands_DPM2Parameters dpm2Params;
219		− SISLANDS_SMC_SWSTATE initialState;
220		− SISLANDS_SMC_SWSTATE ACPIState;
221		− SISLANDS_SMC_SWSTATE ULVState;
222		− SISLANDS_SMC_SWSTATE driverState;
223		− SISLANDS_SMC_HW_PERFORMANCE_LEVEL dpmLevels[SISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1];
	219	+ uint8_t thermalProtectType;
	220	+ uint8_t systemFlags;
	221	+ uint8_t maxVDDCIndexInPPTable;
	222	+ uint8_t extraFlags;
	223	+ uint32_t lowSMIO[SISLANDS_MAX_NO_VREG_STEPS];
	224	+ SISLANDS_SMC_VOLTAGEMASKTABLE voltageMaskTable;
	225	+ SISLANDS_SMC_VOLTAGEMASKTABLE phaseMaskTable;
	226	+ PP_SIslands_DPM2Parameters dpm2Params;
	227	+ struct SISLANDS_SMC_SWSTATE_SINGLE initialState;
	228	+ struct SISLANDS_SMC_SWSTATE_SINGLE ACPIState;
	229	+ struct SISLANDS_SMC_SWSTATE_SINGLE ULVState;
	230	+ SISLANDS_SMC_SWSTATE driverState;
	231	+ SISLANDS_SMC_HW_PERFORMANCE_LEVEL dpmLevels[SISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE];
224	232	};
225	233
226	234	typedef struct SISLANDS_SMC_STATETABLE SISLANDS_SMC_STATETABLE;

drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c+27−4

@@ -209,7 +209,7 @@ static int sun8i_dw_hdmi_bind(struct device dev, struct device master, · 208 unmodified lines
209	209	goto err_disable_clk_tmds;
210	210	}
211	211
212		− ret = sun8i_hdmi_phy_probe(hdmi, phy_node);
	212	+ ret = sun8i_hdmi_phy_get(hdmi, phy_node);
213	213	of_node_put(phy_node);
214	214	if (ret) {
215	215	dev_err(dev, "Couldn't get the HDMI PHY\n");
@@ -242,7 +242,6 @@ static int sun8i_dw_hdmi_bind(struct device dev, struct device master, · 26 unmodified lines
242	242
243	243	cleanup_encoder:
244	244	drm_encoder_cleanup(encoder);
245		− sun8i_hdmi_phy_remove(hdmi);
246	245	err_disable_clk_tmds:
247	246	clk_disable_unprepare(hdmi->clk_tmds);
248	247	err_assert_ctrl_reset:
@@ -263,7 +262,6 @@ static void sun8i_dw_hdmi_unbind(struct device dev, struct device master, · 14 unmodified lines
263	262	struct sun8i_dw_hdmi *hdmi = dev_get_drvdata(dev);
264	263
265	264	dw_hdmi_unbind(hdmi->hdmi);
266		− sun8i_hdmi_phy_remove(hdmi);
267	265	clk_disable_unprepare(hdmi->clk_tmds);
268	266	reset_control_assert(hdmi->rst_ctrl);
269	267	gpiod_set_value(hdmi->ddc_en, 0);
@@ -320,7 +318,32 @@ static struct platform_driver sun8i_dw_hdmi_pltfm_driver = { · 50 unmodified lines
320	318	.of_match_table = sun8i_dw_hdmi_dt_ids,
321	319	},
322	320	};
323		−module_platform_driver(sun8i_dw_hdmi_pltfm_driver);
	321	+
	322	+static int __init sun8i_dw_hdmi_init(void)
	323	+{
	324	+ int ret;
	325	+
	326	+ ret = platform_driver_register(&sun8i_dw_hdmi_pltfm_driver);
	327	+ if (ret)
	328	+ return ret;
	329	+
	330	+ ret = platform_driver_register(&sun8i_hdmi_phy_driver);
	331	+ if (ret) {
	332	+ platform_driver_unregister(&sun8i_dw_hdmi_pltfm_driver);
	333	+ return ret;
	334	+ }
	335	+
	336	+ return ret;
	337	+}
	338	+
	339	+static void __exit sun8i_dw_hdmi_exit(void)
	340	+{
	341	+ platform_driver_unregister(&sun8i_dw_hdmi_pltfm_driver);
	342	+ platform_driver_unregister(&sun8i_hdmi_phy_driver);
	343	+}
	344	+
	345	+module_init(sun8i_dw_hdmi_init);
	346	+module_exit(sun8i_dw_hdmi_exit);
324	347
325	348	MODULE_AUTHOR("Jernej Skrabec <jernej.skrabec@siol.net>");
326	349	MODULE_DESCRIPTION("Allwinner DW HDMI bridge");

drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h+3−2

@@ -195,14 +195,15 @@ struct sun8i_dw_hdmi { · 194 unmodified lines
195	195	struct gpio_desc *ddc_en;
196	196	};
197	197
	198	+extern struct platform_driver sun8i_hdmi_phy_driver;
	199	+
198	200	static inline struct sun8i_dw_hdmi *
199	201	encoder_to_sun8i_dw_hdmi(struct drm_encoder *encoder)
200	202	{
201	203	return container_of(encoder, struct sun8i_dw_hdmi, encoder);
202	204	}
203	205
204		−int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi hdmi, struct device_node node);
205		−void sun8i_hdmi_phy_remove(struct sun8i_dw_hdmi *hdmi);
	206	+int sun8i_hdmi_phy_get(struct sun8i_dw_hdmi hdmi, struct device_node node);
206	207
207	208	void sun8i_hdmi_phy_init(struct sun8i_hdmi_phy *phy);
208	209	void sun8i_hdmi_phy_set_ops(struct sun8i_hdmi_phy *phy,

drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c+36−5

@@ -5,6 +5,7 @@ · 4 unmodified lines
5	5
6	6	#include <linux/delay.h>
7	7	#include <linux/of_address.h>
	8	+#include <linux/of_platform.h>
8	9
9	10	#include "sun8i_dw_hdmi.h"
10	11
@@ -597,10 +598,30 @@ static const struct of_device_id sun8i_hdmi_phy_of_table[] = { · 586 unmodified lines
597	598	{ /* sentinel */ }
598	599	};
599	600
600		−int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi hdmi, struct device_node node)
	601	+int sun8i_hdmi_phy_get(struct sun8i_dw_hdmi hdmi, struct device_node node)
	602	+{
	603	+ struct platform_device *pdev = of_find_device_by_node(node);
	604	+ struct sun8i_hdmi_phy *phy;
	605	+
	606	+ if (!pdev)
	607	+ return -EPROBE_DEFER;
	608	+
	609	+ phy = platform_get_drvdata(pdev);
	610	+ if (!phy)
	611	+ return -EPROBE_DEFER;
	612	+
	613	+ hdmi->phy = phy;
	614	+
	615	+ put_device(&pdev->dev);
	616	+
	617	+ return 0;
	618	+}
	619	+
	620	+static int sun8i_hdmi_phy_probe(struct platform_device *pdev)
601	621	{
602	622	const struct of_device_id *match;
603		− struct device *dev = hdmi->dev;
	623	+ struct device *dev = &pdev->dev;
	624	+ struct device_node *node = dev->of_node;
604	625	struct sun8i_hdmi_phy *phy;
605	626	struct resource res;
606	627	void __iomem *regs;
@@ -704,7 +725,7 @@ int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi hdmi, struct device_node node) · 97 unmodified lines
704	725	clk_prepare_enable(phy->clk_phy);
705	726	}
706	727
707		− hdmi->phy = phy;
	728	+ platform_set_drvdata(pdev, phy);
708	729
709	730	return 0;
710	731
@@ -728,9 +749,9 @@ err_put_clk_bus: · 17 unmodified lines
728	749	return ret;
729	750	}
730	751
731		−void sun8i_hdmi_phy_remove(struct sun8i_dw_hdmi *hdmi)
	752	+static int sun8i_hdmi_phy_remove(struct platform_device *pdev)
732	753	{
733		− struct sun8i_hdmi_phy *phy = hdmi->phy;
	754	+ struct sun8i_hdmi_phy *phy = platform_get_drvdata(pdev);
734	755
735	756	clk_disable_unprepare(phy->clk_mod);
736	757	clk_disable_unprepare(phy->clk_bus);
@@ -744,4 +765,14 @@ void sun8i_hdmi_phy_remove(struct sun8i_dw_hdmi *hdmi) · 7 unmodified lines
744	765	clk_put(phy->clk_pll1);
745	766	clk_put(phy->clk_mod);
746	767	clk_put(phy->clk_bus);
	768	+ return 0;
747	769	}
	770	+
	771	+struct platform_driver sun8i_hdmi_phy_driver = {
	772	+ .probe = sun8i_hdmi_phy_probe,
	773	+ .remove = sun8i_hdmi_phy_remove,
	774	+ .driver = {
	775	+ .name = "sun8i-hdmi-phy",
	776	+ .of_match_table = sun8i_hdmi_phy_of_table,
	777	+ },
	778	+};

drivers/gpu/drm/tegra/drm.h+1−1

@@ -25,7 +25,7 @@ · 24 unmodified lines
25	25	#include "trace.h"
26	26
27	27	/* XXX move to include/uapi/drm/drm_fourcc.h? */
28		−#define DRM_FORMAT_MOD_NVIDIA_SECTOR_LAYOUT BIT(22)
	28	+#define DRM_FORMAT_MOD_NVIDIA_SECTOR_LAYOUT BIT_ULL(22)
29	29
30	30	struct reset_control;
31	31

drivers/gpu/drm/tegra/hub.c+1−1

@@ -510,7 +510,7 @@ static void tegra_shared_plane_atomic_update(struct drm_plane *plane, · 509 unmodified lines
510	510	* dGPU sector layout.
511	511	*/
512	512	if (tegra_plane_state->tiling.sector_layout == TEGRA_BO_SECTOR_LAYOUT_GPU)
513		− base \|= BIT(39);
	513	+ base \|= BIT_ULL(39);
514	514	#endif
515	515
516	516	tegra_plane_writel(p, tegra_plane_state->format, DC_WIN_COLOR_DEPTH);

drivers/gpu/drm/tegra/sor.c+42−28

@@ -3125,21 +3125,21 @@ static int tegra_sor_init(struct host1x_client *client) · 3124 unmodified lines
3125	3125	if (err < 0) {
3126	3126	dev_err(sor->dev, "failed to acquire SOR reset: %d\n",
3127	3127	err);
3128		− return err;
	3128	+ goto rpm_put;
3129	3129	}
3130	3130
3131	3131	err = reset_control_assert(sor->rst);
3132	3132	if (err < 0) {
3133	3133	dev_err(sor->dev, "failed to assert SOR reset: %d\n",
3134	3134	err);
3135		− return err;
	3135	+ goto rpm_put;
3136	3136	}
3137	3137	}
3138	3138
3139	3139	err = clk_prepare_enable(sor->clk);
3140	3140	if (err < 0) {
3141	3141	dev_err(sor->dev, "failed to enable clock: %d\n", err);
3142		− return err;
	3142	+ goto rpm_put;
3143	3143	}
3144	3144
3145	3145	usleep_range(1000, 3000);
@@ -3150,7 +3150,7 @@ static int tegra_sor_init(struct host1x_client *client) · 4 unmodified lines
3150	3150	dev_err(sor->dev, "failed to deassert SOR reset: %d\n",
3151	3151	err);
3152	3152	clk_disable_unprepare(sor->clk);
3153		− return err;
	3153	+ goto rpm_put;
3154	3154	}
3155	3155
3156	3156	reset_control_release(sor->rst);
@@ -3171,6 +3171,12 @@ static int tegra_sor_init(struct host1x_client *client) · 14 unmodified lines
3171	3171	}
3172	3172
3173	3173	return 0;
	3174	+
	3175	+rpm_put:
	3176	+ if (sor->rst)
	3177	+ pm_runtime_put(sor->dev);
	3178	+
	3179	+ return err;
3174	3180	}
3175	3181
3176	3182	static int tegra_sor_exit(struct host1x_client *client)
@@ -3739,12 +3745,8 @@ static int tegra_sor_probe(struct platform_device *pdev) · 562 unmodified lines
3739	3745	if (!sor->aux)
3740	3746	return -EPROBE_DEFER;
3741	3747
3742		− if (get_device(&sor->aux->ddc.dev)) {
3743		− if (try_module_get(sor->aux->ddc.owner))
3744		− sor->output.ddc = &sor->aux->ddc;
3745		− else
3746		− put_device(&sor->aux->ddc.dev);
3747		− }
	3748	+ if (get_device(sor->aux->dev))
	3749	+ sor->output.ddc = &sor->aux->ddc;
3748	3750	}
3749	3751
3750	3752	if (!sor->aux) {
@@ -3772,12 +3774,13 @@ static int tegra_sor_probe(struct platform_device *pdev) · 21 unmodified lines
3772	3774
3773	3775	err = tegra_sor_parse_dt(sor);
3774	3776	if (err < 0)
3775		− return err;
	3777	+ goto put_aux;
3776	3778
3777	3779	err = tegra_output_probe(&sor->output);
3778		− if (err < 0)
3779		− return dev_err_probe(&pdev->dev, err,
3780		− "failed to probe output\n");
	3780	+ if (err < 0) {
	3781	+ dev_err_probe(&pdev->dev, err, "failed to probe output\n");
	3782	+ goto put_aux;
	3783	+ }
3781	3784
3782	3785	if (sor->ops && sor->ops->probe) {
3783	3786	err = sor->ops->probe(sor);
@@ -3916,17 +3919,10 @@ static int tegra_sor_probe(struct platform_device *pdev) · 132 unmodified lines
3916	3919	platform_set_drvdata(pdev, sor);
3917	3920	pm_runtime_enable(&pdev->dev);
3918	3921
3919		− INIT_LIST_HEAD(&sor->client.list);
	3922	+ host1x_client_init(&sor->client);
3920	3923	sor->client.ops = &sor_client_ops;
3921	3924	sor->client.dev = &pdev->dev;
3922	3925
3923		− err = host1x_client_register(&sor->client);
3924		− if (err < 0) {
3925		− dev_err(&pdev->dev, "failed to register host1x client: %d\n",
3926		− err);
3927		− goto rpm_disable;
3928		− }
3929		−
3930	3926	/*
3931	3927	* On Tegra210 and earlier, provide our own implementation for the
3932	3928	* pad output clock.
@@ -3938,13 +3934,13 @@ static int tegra_sor_probe(struct platform_device *pdev) · 5 unmodified lines
3938	3934	sor->index);
3939	3935	if (!name) {
3940	3936	err = -ENOMEM;
3941		− goto unregister;
	3937	+ goto uninit;
3942	3938	}
3943	3939
3944	3940	err = host1x_client_resume(&sor->client);
3945	3941	if (err < 0) {
3946	3942	dev_err(sor->dev, "failed to resume: %d\n", err);
3947		− goto unregister;
	3943	+ goto uninit;
3948	3944	}
3949	3945
3950	3946	sor->clk_pad = tegra_clk_sor_pad_register(sor, name);
@@ -3955,17 +3951,30 @@ static int tegra_sor_probe(struct platform_device *pdev) · 4 unmodified lines
3955	3951	err = PTR_ERR(sor->clk_pad);
3956	3952	dev_err(sor->dev, "failed to register SOR pad clock: %d\n",
3957	3953	err);
3958		− goto unregister;
	3954	+ goto uninit;
	3955	+ }
	3956	+
	3957	+ err = __host1x_client_register(&sor->client);
	3958	+ if (err < 0) {
	3959	+ dev_err(&pdev->dev, "failed to register host1x client: %d\n",
	3960	+ err);
	3961	+ goto uninit;
3959	3962	}
3960	3963
3961	3964	return 0;
3962	3965
3963		−unregister:
3964		− host1x_client_unregister(&sor->client);
3965		−rpm_disable:
	3966	+uninit:
	3967	+ host1x_client_exit(&sor->client);
3966	3968	pm_runtime_disable(&pdev->dev);
3967	3969	remove:
	3970	+ if (sor->aux)
	3971	+ sor->output.ddc = NULL;
	3972	+
3968	3973	tegra_output_remove(&sor->output);
	3974	+put_aux:
	3975	+ if (sor->aux)
	3976	+ put_device(sor->aux->dev);
	3977	+
3969	3978	return err;
3970	3979	}
3971	3980
@@ -3983,6 +3992,11 @@ static int tegra_sor_remove(struct platform_device *pdev) · 11 unmodified lines
3983	3992
3984	3993	pm_runtime_disable(&pdev->dev);
3985	3994
	3995	+ if (sor->aux) {
	3996	+ put_device(sor->aux->dev);
	3997	+ sor->output.ddc = NULL;
	3998	+ }
	3999	+
3986	4000	tegra_output_remove(&sor->output);
3987	4001
3988	4002	return 0;

drivers/gpu/drm/ttm/ttm_bo.c+4−1

@@ -1172,7 +1172,10 @@ int ttm_bo_swapout(struct ttm_buffer_object bo, struct ttm_operation_ctx ctx, · 1171 unmodified lines
1172	1172	if (!ttm_bo_evict_swapout_allowable(bo, ctx, &locked, NULL))
1173	1173	return -EBUSY;
1174	1174
1175		− if (!ttm_bo_get_unless_zero(bo)) {
	1175	+ if (!bo->ttm \|\| !ttm_tt_is_populated(bo->ttm) \|\|
	1176	+ bo->ttm->page_flags & TTM_PAGE_FLAG_SG \|\|
	1177	+ bo->ttm->page_flags & TTM_PAGE_FLAG_SWAPPED \|\|
	1178	+ !ttm_bo_get_unless_zero(bo)) {
1176	1179	if (locked)
1177	1180	dma_resv_unlock(bo->base.resv);
1178	1181	return -EBUSY;

drivers/gpu/drm/ttm/ttm_device.c+1−7

@@ -143,14 +143,8 @@ int ttm_device_swapout(struct ttm_device bdev, struct ttm_operation_ctx ctx, · 142 unmodified lines
143	143
144	144	for (j = 0; j < TTM_MAX_BO_PRIORITY; ++j) {
145	145	list_for_each_entry(bo, &man->lru[j], lru) {
146		− uint32_t num_pages;
	146	+ uint32_t num_pages = PFN_UP(bo->base.size);
147	147
148		− if (!bo->ttm \|\|
149		− bo->ttm->page_flags & TTM_PAGE_FLAG_SG \|\|
150		− bo->ttm->page_flags & TTM_PAGE_FLAG_SWAPPED)
151		− continue;
152		−
153		− num_pages = bo->ttm->num_pages;
154	148	ret = ttm_bo_swapout(bo, ctx, gfp_flags);
155	149	/* ttm_bo_swapout has dropped the lru_lock */
156	150	if (!ret)

drivers/gpu/drm/vc4/vc4_kms.c+1−1

@@ -372,7 +372,7 @@ static void vc4_atomic_commit_tail(struct drm_atomic_state *state) · 371 unmodified lines
372	372	if (!old_hvs_state->fifo_state[channel].in_use)
373	373	continue;
374	374
375		− ret = drm_crtc_commit_wait(old_hvs_state->fifo_state[i].pending_commit);
	375	+ ret = drm_crtc_commit_wait(old_hvs_state->fifo_state[channel].pending_commit);
376	376	if (ret)
377	377	drm_err(dev, "Timed out waiting for commit\n");
378	378	}

drivers/gpu/drm/vc4/vc4_vec.c+0−6

@@ -197,12 +197,6 @@ struct vc4_vec_connector { · 196 unmodified lines
197	197	struct drm_encoder *encoder;
198	198	};
199	199
200		−static inline struct vc4_vec_connector *
201		−to_vc4_vec_connector(struct drm_connector *connector)
202		−{
203		− return container_of(connector, struct vc4_vec_connector, base);
204		−}
205		−
206	200	enum vc4_vec_tv_mode_id {
207	201	VC4_VEC_TV_MODE_NTSC,
208	202	VC4_VEC_TV_MODE_NTSC_J,

drivers/gpu/host1x/bus.c+24−6

@@ -735,6 +735,29 @@ void host1x_driver_unregister(struct host1x_driver *driver) · 734 unmodified lines
735	735	}
736	736	EXPORT_SYMBOL(host1x_driver_unregister);
737	737
	738	+/**
	739	+ * __host1x_client_init() - initialize a host1x client
	740	+ * @client: host1x client
	741	+ * @key: lock class key for the client-specific mutex
	742	+ */
	743	+void __host1x_client_init(struct host1x_client client, struct lock_class_key key)
	744	+{
	745	+ INIT_LIST_HEAD(&client->list);
	746	+ __mutex_init(&client->lock, "host1x client lock", key);
	747	+ client->usecount = 0;
	748	+}
	749	+EXPORT_SYMBOL(__host1x_client_init);
	750	+
	751	+/**
	752	+ * host1x_client_exit() - uninitialize a host1x client
	753	+ * @client: host1x client
	754	+ */
	755	+void host1x_client_exit(struct host1x_client *client)
	756	+{
	757	+ mutex_destroy(&client->lock);
	758	+}
	759	+EXPORT_SYMBOL(host1x_client_exit);
	760	+
738	761	/**
739	762	* __host1x_client_register() - register a host1x client
740	763	* @client: host1x client
@@ -747,16 +770,11 @@ EXPORT_SYMBOL(host1x_driver_unregister); · 6 unmodified lines
747	770	* device and call host1x_device_init(), which will in turn call each client's
748	771	* &host1x_client_ops.init implementation.
749	772	*/
750		−int __host1x_client_register(struct host1x_client *client,
751		− struct lock_class_key *key)
	773	+int __host1x_client_register(struct host1x_client *client)
752	774	{
753	775	struct host1x *host1x;
754	776	int err;
755	777
756		− INIT_LIST_HEAD(&client->list);
757		− __mutex_init(&client->lock, "host1x client lock", key);
758		− client->usecount = 0;
759		−
760	778	mutex_lock(&devices_lock);
761	779
762	780	list_for_each_entry(host1x, &devices, list) {

drivers/hid/Kconfig+17−2

@@ -93,11 +93,11 @@ menu "Special HID drivers" · 92 unmodified lines
93	93	depends on HID
94	94
95	95	config HID_A4TECH
96		− tristate "A4 tech mice"
	96	+ tristate "A4TECH mice"
97	97	depends on HID
98	98	default !EXPERT
99	99	help
100		− Support for A4 tech X5 and WOP-35 / Trust 450L mice.
	100	+ Support for some A4TECH mice with two scroll wheels.
101	101
102	102	config HID_ACCUTOUCH
103	103	tristate "Accutouch touch device"
@@ -922,6 +922,21 @@ config HID_SAMSUNG · 818 unmodified lines
922	922	help
923	923	Support for Samsung InfraRed remote control or keyboards.
924	924
	925	+config HID_SEMITEK
	926	+ tristate "Semitek USB keyboards"
	927	+ depends on HID
	928	+ help
	929	+ Support for Semitek USB keyboards that are not fully compliant
	930	+ with the HID standard.
	931	+
	932	+ There are many variants, including:
	933	+ - GK61, GK64, GK68, GK84, GK96, etc.
	934	+ - SK61, SK64, SK68, SK84, SK96, etc.
	935	+ - Dierya DK61/DK66
	936	+ - Tronsmart TK09R
	937	+ - Woo-dy
	938	+ - X-Bows Nature/Knight
	939	+
925	940	config HID_SONY
926	941	tristate "Sony PS2/3/4 accessories"
927	942	depends on USB_HID

drivers/hid/Makefile+1−0

@@ -106,6 +106,7 @@ obj-$(CONFIG_HID_ROCCAT) += hid-roccat.o hid-roccat-common.o \ · 105 unmodified lines
106	106	obj-$(CONFIG_HID_RMI) += hid-rmi.o
107	107	obj-$(CONFIG_HID_SAITEK) += hid-saitek.o
108	108	obj-$(CONFIG_HID_SAMSUNG) += hid-samsung.o
	109	+obj-$(CONFIG_HID_SEMITEK) += hid-semitek.o
109	110	obj-$(CONFIG_HID_SMARTJOYPLUS) += hid-sjoy.o
110	111	obj-$(CONFIG_HID_SONY) += hid-sony.o
111	112	obj-$(CONFIG_HID_SPEEDLINK) += hid-speedlink.o

drivers/hid/amd-sfh-hid/amd_sfh_client.c+10−9

@@ -88,6 +88,7 @@ static void amd_sfh_work(struct work_struct *work) · 87 unmodified lines
88	88	sensor_index = req_node->sensor_idx;
89	89	report_id = req_node->report_id;
90	90	node_type = req_node->report_type;
	91	+ kfree(req_node);
91	92
92	93	if (node_type == HID_FEATURE_REPORT) {
93	94	report_size = get_feature_report(sensor_index, report_id,
@@ -142,7 +143,7 @@ int amd_sfh_hid_client_init(struct amd_mp2_dev *privdata) · 48 unmodified lines
142	143	int rc, i;
143	144
144	145	dev = &privdata->pdev->dev;
145		− cl_data = kzalloc(sizeof(*cl_data), GFP_KERNEL);
	146	+ cl_data = devm_kzalloc(dev, sizeof(*cl_data), GFP_KERNEL);
146	147	if (!cl_data)
147	148	return -ENOMEM;
148	149
@@ -175,12 +176,12 @@ int amd_sfh_hid_client_init(struct amd_mp2_dev *privdata) · 26 unmodified lines
175	176	rc = -EINVAL;
176	177	goto cleanup;
177	178	}
178		− cl_data->feature_report[i] = kzalloc(feature_report_size, GFP_KERNEL);
	179	+ cl_data->feature_report[i] = devm_kzalloc(dev, feature_report_size, GFP_KERNEL);
179	180	if (!cl_data->feature_report[i]) {
180	181	rc = -ENOMEM;
181	182	goto cleanup;
182	183	}
183		− cl_data->input_report[i] = kzalloc(input_report_size, GFP_KERNEL);
	184	+ cl_data->input_report[i] = devm_kzalloc(dev, input_report_size, GFP_KERNEL);
184	185	if (!cl_data->input_report[i]) {
185	186	rc = -ENOMEM;
186	187	goto cleanup;
@@ -189,7 +190,8 @@ int amd_sfh_hid_client_init(struct amd_mp2_dev *privdata) · 2 unmodified lines
189	190	info.sensor_idx = cl_idx;
190	191	info.dma_address = cl_data->sensor_dma_addr[i];
191	192
192		− cl_data->report_descr[i] = kzalloc(cl_data->report_descr_sz[i], GFP_KERNEL);
	193	+ cl_data->report_descr[i] =
	194	+ devm_kzalloc(dev, cl_data->report_descr_sz[i], GFP_KERNEL);
193	195	if (!cl_data->report_descr[i]) {
194	196	rc = -ENOMEM;
195	197	goto cleanup;
@@ -214,11 +216,11 @@ cleanup: · 18 unmodified lines
214	216	cl_data->sensor_virt_addr[i],
215	217	cl_data->sensor_dma_addr[i]);
216	218	}
217		− kfree(cl_data->feature_report[i]);
218		− kfree(cl_data->input_report[i]);
219		− kfree(cl_data->report_descr[i]);
	219	+ devm_kfree(dev, cl_data->feature_report[i]);
	220	+ devm_kfree(dev, cl_data->input_report[i]);
	221	+ devm_kfree(dev, cl_data->report_descr[i]);
220	222	}
221		− kfree(cl_data);
	223	+ devm_kfree(dev, cl_data);
222	224	return rc;
223	225	}
224	226
@@ -241,6 +243,5 @@ int amd_sfh_hid_client_deinit(struct amd_mp2_dev *privdata) · 16 unmodified lines
241	243	cl_data->sensor_dma_addr[i]);
242	244	}
243	245	}
244		− kfree(cl_data);
245	246	return 0;
246	247	}

drivers/hid/amd-sfh-hid/amd_sfh_hid.c+0−3

@@ -162,9 +162,6 @@ void amdtp_hid_remove(struct amdtp_cl_data *cli_data) · 161 unmodified lines
162	162	int i;
163	163
164	164	for (i = 0; i < cli_data->num_hid_devices; ++i) {
165		− kfree(cli_data->feature_report[i]);
166		− kfree(cli_data->input_report[i]);
167		− kfree(cli_data->report_descr[i]);
168	165	if (cli_data->hid_sensor_hubs[i]) {
169	166	kfree(cli_data->hid_sensor_hubs[i]->driver_data);
170	167	hid_destroy_device(cli_data->hid_sensor_hubs[i]);

drivers/hid/hid-a4tech.c+2−0

@@ -147,6 +147,8 @@ static const struct hid_device_id a4_devices[] = { · 146 unmodified lines
147	147	.driver_data = A4_2WHEEL_MOUSE_HACK_B8 },
148	148	{ HID_USB_DEVICE(USB_VENDOR_ID_A4TECH, USB_DEVICE_ID_A4TECH_RP_649),
149	149	.driver_data = A4_2WHEEL_MOUSE_HACK_B8 },
	150	+ { HID_USB_DEVICE(USB_VENDOR_ID_A4TECH, USB_DEVICE_ID_A4TECH_NB_95),
	151	+ .driver_data = A4_2WHEEL_MOUSE_HACK_B8 },
150	152	{ }
151	153	};
152	154	MODULE_DEVICE_TABLE(hid, a4_devices);

drivers/hid/hid-asus.c+20−12

@@ -79,10 +79,9 @@ MODULE_DESCRIPTION("Asus HID Keyboard and TouchPad"); · 78 unmodified lines
79	79	#define QUIRK_T100_KEYBOARD BIT(6)
80	80	#define QUIRK_T100CHI BIT(7)
81	81	#define QUIRK_G752_KEYBOARD BIT(8)
82		−#define QUIRK_T101HA_DOCK BIT(9)
83		−#define QUIRK_T90CHI BIT(10)
84		−#define QUIRK_MEDION_E1239T BIT(11)
85		−#define QUIRK_ROG_NKEY_KEYBOARD BIT(12)
	82	+#define QUIRK_T90CHI BIT(9)
	83	+#define QUIRK_MEDION_E1239T BIT(10)
	84	+#define QUIRK_ROG_NKEY_KEYBOARD BIT(11)
86	85
87	86	#define I2C_KEYBOARD_QUIRKS (QUIRK_FIX_NOTEBOOK_REPORT \| \
88	87	QUIRK_NO_INIT_REPORTS \| \
@@ -335,7 +334,7 @@ static int asus_raw_event(struct hid_device *hdev, · 246 unmodified lines
335	334	if (drvdata->quirks & QUIRK_MEDION_E1239T)
336	335	return asus_e1239t_event(drvdata, data, size);
337	336
338		− if (drvdata->quirks & QUIRK_ROG_NKEY_KEYBOARD) {
	337	+ if (drvdata->quirks & QUIRK_USE_KBD_BACKLIGHT) {
339	338	/*
340	339	* Skip these report ID, the device emits a continuous stream associated
341	340	* with the AURA mode it is in which looks like an 'echo'.
@@ -355,6 +354,16 @@ static int asus_raw_event(struct hid_device *hdev, · 13 unmodified lines
355	354	return -1;
356	355	}
357	356	}
	357	+ if (drvdata->quirks & QUIRK_ROG_NKEY_KEYBOARD) {
	358	+ /*
	359	+ * G713 and G733 send these codes on some keypresses, depending on
	360	+ * the key pressed it can trigger a shutdown event if not caught.
	361	+ */
	362	+ if(data[0] == 0x02 && data[1] == 0x30) {
	363	+ return -1;
	364	+ }
	365	+ }
	366	+
358	367	}
359	368
360	369	return 0;
@@ -1072,11 +1081,6 @@ static int asus_probe(struct hid_device hdev, const struct hid_device_id id) · 711 unmodified lines
1072	1081	return ret;
1073	1082	}
1074	1083
1075		− /* use hid-multitouch for T101HA touchpad */
1076		− if (id->driver_data & QUIRK_T101HA_DOCK &&
1077		− hdev->collection->usage == HID_GD_MOUSE)
1078		− return -ENODEV;
1079		−
1080	1084	ret = hid_hw_start(hdev, HID_CONNECT_DEFAULT);
1081	1085	if (ret) {
1082	1086	hid_err(hdev, "Asus hw start failed: %d\n", ret);
@@ -1230,8 +1234,6 @@ static const struct hid_device_id asus_devices[] = { · 147 unmodified lines
1230	1234	{ HID_USB_DEVICE(USB_VENDOR_ID_ASUSTEK,
1231	1235	USB_DEVICE_ID_ASUSTEK_T100TAF_KEYBOARD),
1232	1236	QUIRK_T100_KEYBOARD \| QUIRK_NO_CONSUMER_USAGES },
1233		− { HID_USB_DEVICE(USB_VENDOR_ID_ASUSTEK,
1234		− USB_DEVICE_ID_ASUSTEK_T101HA_KEYBOARD), QUIRK_T101HA_DOCK },
1235	1237	{ HID_USB_DEVICE(USB_VENDOR_ID_CHICONY, USB_DEVICE_ID_ASUS_AK1D) },
1236	1238	{ HID_USB_DEVICE(USB_VENDOR_ID_TURBOX, USB_DEVICE_ID_ASUS_MD_5110) },
1237	1239	{ HID_USB_DEVICE(USB_VENDOR_ID_JESS, USB_DEVICE_ID_ASUS_MD_5112) },
@@ -1239,6 +1241,12 @@ static const struct hid_device_id asus_devices[] = { · 1 unmodified line
1239	1241	USB_DEVICE_ID_ASUSTEK_T100CHI_KEYBOARD), QUIRK_T100CHI },
1240	1242	{ HID_USB_DEVICE(USB_VENDOR_ID_ITE, USB_DEVICE_ID_ITE_MEDION_E1239T),
1241	1243	QUIRK_MEDION_E1239T },
	1244	+ /*
	1245	+ * Note bind to the HID_GROUP_GENERIC group, so that we only bind to the keyboard
	1246	+ * part, while letting hid-multitouch.c handle the touchpad.
	1247	+ */
	1248	+ { HID_DEVICE(BUS_USB, HID_GROUP_GENERIC,
	1249	+ USB_VENDOR_ID_ASUSTEK, USB_DEVICE_ID_ASUSTEK_T101HA_KEYBOARD) },
1242	1250	{ }
1243	1251	};
1244	1252	MODULE_DEVICE_TABLE(hid, asus_devices);

drivers/hid/hid-core.c+3−1

@@ -2005,6 +2005,9 @@ int hid_connect(struct hid_device *hdev, unsigned int connect_mask) · 2004 unmodified lines
2005	2005	case BUS_I2C:
2006	2006	bus = "I2C";
2007	2007	break;
	2008	+ case BUS_VIRTUAL:
	2009	+ bus = "VIRTUAL";
	2010	+ break;
2008	2011	default:
2009	2012	bus = "<UNKNOWN>";
2010	2013	}
@@ -2588,7 +2591,6 @@ int hid_check_keys_pressed(struct hid_device *hid) · 577 unmodified lines
2588	2591
2589	2592	return 0;
2590	2593	}
2591		−
2592	2594	EXPORT_SYMBOL_GPL(hid_check_keys_pressed);
2593	2595
2594	2596	static int __init hid_init(void)

drivers/hid/hid-debug.c+3−0

@@ -930,6 +930,9 @@ static const char *keys[KEY_MAX + 1] = { · 929 unmodified lines
930	930	[KEY_APPSELECT] = "AppSelect",
931	931	[KEY_SCREENSAVER] = "ScreenSaver",
932	932	[KEY_VOICECOMMAND] = "VoiceCommand",
	933	+ [KEY_ASSISTANT] = "Assistant",
	934	+ [KEY_KBD_LAYOUT_NEXT] = "KbdLayoutNext",
	935	+ [KEY_EMOJI_PICKER] = "EmojiPicker",
933	936	[KEY_BRIGHTNESS_MIN] = "BrightnessMin",
934	937	[KEY_BRIGHTNESS_MAX] = "BrightnessMax",
935	938	[KEY_BRIGHTNESS_AUTO] = "BrightnessAuto",

drivers/hid/hid-ft260.c+16−13

@@ -201,7 +201,7 @@ struct ft260_i2c_write_request_report { · 200 unmodified lines
201	201	u8 address; /* 7-bit I2C address */
202	202	u8 flag; /* I2C transaction condition */
203	203	u8 length; /* data payload length */
204		− u8 data[60]; /* data payload */
	204	+ u8 data[FT260_WR_DATA_MAX]; /* data payload */
205	205	} __packed;
206	206
207	207	struct ft260_i2c_read_request_report {
@@ -249,7 +249,10 @@ static int ft260_hid_feature_report_get(struct hid_device *hdev, · 41 unmodified lines
249	249
250	250	ret = hid_hw_raw_request(hdev, report_id, buf, len, HID_FEATURE_REPORT,
251	251	HID_REQ_GET_REPORT);
252		− memcpy(data, buf, len);
	252	+ if (likely(ret == len))
	253	+ memcpy(data, buf, len);
	254	+ else if (ret >= 0)
	255	+ ret = -EIO;
253	256	kfree(buf);
254	257	return ret;
255	258	}
@@ -298,7 +301,7 @@ static int ft260_xfer_status(struct ft260_device *dev) · 42 unmodified lines
298	301
299	302	ret = ft260_hid_feature_report_get(hdev, FT260_I2C_STATUS,
300	303	(u8 *)&report, sizeof(report));
301		− if (ret < 0) {
	304	+ if (unlikely(ret < 0)) {
302	305	hid_err(hdev, "failed to retrieve status: %d\n", ret);
303	306	return ret;
304	307	}
@@ -429,6 +432,9 @@ static int ft260_smbus_write(struct ft260_device *dev, u8 addr, u8 cmd, · 124 unmodified lines
429	432	struct ft260_i2c_write_request_report *rep =
430	433	(struct ft260_i2c_write_request_report *)dev->write_buf;
431	434
	435	+ if (data_len >= sizeof(rep->data))
	436	+ return -EINVAL;
	437	+
432	438	rep->address = addr;
433	439	rep->data[0] = cmd;
434	440	rep->length = data_len + 1;
@@ -721,10 +727,9 @@ static int ft260_get_system_config(struct hid_device *hdev, · 286 unmodified lines
721	727
722	728	ret = ft260_hid_feature_report_get(hdev, FT260_SYSTEM_SETTINGS,
723	729	(u8 *)cfg, len);
724		− if (ret != len) {
	730	+ if (ret < 0) {
725	731	hid_err(hdev, "failed to retrieve system status\n");
726		− if (ret >= 0)
727		− return -EIO;
	732	+ return ret;
728	733	}
729	734	return 0;
730	735	}
@@ -777,8 +782,8 @@ static int ft260_byte_show(struct hid_device hdev, int id, u8 cfg, int len, · 46 unmodified lines
777	782	int ret;
778	783
779	784	ret = ft260_hid_feature_report_get(hdev, id, cfg, len);
780		− if (ret != len && ret >= 0)
781		− return -EIO;
	785	+ if (ret < 0)
	786	+ return ret;
782	787
783	788	return scnprintf(buf, PAGE_SIZE, "%hi\n", *field);
784	789	}
@@ -789,8 +794,8 @@ static int ft260_word_show(struct hid_device hdev, int id, u8 cfg, int len, · 4 unmodified lines
789	794	int ret;
790	795
791	796	ret = ft260_hid_feature_report_get(hdev, id, cfg, len);
792		− if (ret != len && ret >= 0)
793		− return -EIO;
	797	+ if (ret < 0)
	798	+ return ret;
794	799
795	800	return scnprintf(buf, PAGE_SIZE, "%hi\n", le16_to_cpu(*field));
796	801	}
@@ -941,10 +946,8 @@ static int ft260_probe(struct hid_device hdev, const struct hid_device_id id) · 144 unmodified lines
941	946
942	947	ret = ft260_hid_feature_report_get(hdev, FT260_CHIP_VERSION,
943	948	(u8 *)&version, sizeof(version));
944		− if (ret != sizeof(version)) {
	949	+ if (ret < 0) {
945	950	hid_err(hdev, "failed to retrieve chip version\n");
946		− if (ret >= 0)
947		− ret = -EIO;
948	951	goto err_hid_close;
949	952	}
950	953

drivers/hid/hid-gt683r.c+1−0

@@ -54,6 +54,7 @@ static const struct hid_device_id gt683r_led_id[] = { · 53 unmodified lines
54	54	{ HID_USB_DEVICE(USB_VENDOR_ID_MSI, USB_DEVICE_ID_MSI_GT683R_LED_PANEL) },
55	55	{ }
56	56	};
	57	+MODULE_DEVICE_TABLE(hid, gt683r_led_id);
57	58
58	59	static void gt683r_brightness_set(struct led_classdev *led_cdev,
59	60	enum led_brightness brightness)

drivers/hid/hid-ids.h+7−2

@@ -26,6 +26,7 @@ · 25 unmodified lines
26	26	#define USB_DEVICE_ID_A4TECH_WCP32PU 0x0006
27	27	#define USB_DEVICE_ID_A4TECH_X5_005D 0x000a
28	28	#define USB_DEVICE_ID_A4TECH_RP_649 0x001a
	29	+#define USB_DEVICE_ID_A4TECH_NB_95 0x022b
29	30
30	31	#define USB_VENDOR_ID_AASHIMA 0x06d6
31	32	#define USB_DEVICE_ID_AASHIMA_GAMEPAD 0x0025
@@ -299,8 +300,6 @@ · 267 unmodified lines
299	300
300	301	#define USB_VENDOR_ID_CORSAIR 0x1b1c
301	302	#define USB_DEVICE_ID_CORSAIR_K90 0x1b02
302		−
303		−#define USB_VENDOR_ID_CORSAIR 0x1b1c
304	303	#define USB_DEVICE_ID_CORSAIR_K70R 0x1b09
305	304	#define USB_DEVICE_ID_CORSAIR_K95RGB 0x1b11
306	305	#define USB_DEVICE_ID_CORSAIR_M65RGB 0x1b12
@@ -751,6 +750,7 @@ · 444 unmodified lines
751	750	#define USB_DEVICE_ID_LENOVO_X1_COVER 0x6085
752	751	#define USB_DEVICE_ID_LENOVO_X1_TAB 0x60a3
753	752	#define USB_DEVICE_ID_LENOVO_X1_TAB3 0x60b5
	753	+#define USB_DEVICE_ID_LENOVO_OPTICAL_USB_MOUSE_600E 0x600e
754	754	#define USB_DEVICE_ID_LENOVO_PIXART_USB_MOUSE_608D 0x608d
755	755	#define USB_DEVICE_ID_LENOVO_PIXART_USB_MOUSE_6019 0x6019
756	756	#define USB_DEVICE_ID_LENOVO_PIXART_USB_MOUSE_602E 0x602e
@@ -1051,6 +1051,7 @@ · 294 unmodified lines
1051	1051	#define USB_DEVICE_ID_SAITEK_X52 0x075c
1052	1052	#define USB_DEVICE_ID_SAITEK_X52_2 0x0255
1053	1053	#define USB_DEVICE_ID_SAITEK_X52_PRO 0x0762
	1054	+#define USB_DEVICE_ID_SAITEK_X65 0x0b6a
1054	1055
1055	1056	#define USB_VENDOR_ID_SAMSUNG 0x0419
1056	1057	#define USB_DEVICE_ID_SAMSUNG_IR_REMOTE 0x0001
@@ -1060,6 +1061,9 @@ · 3 unmodified lines
1060	1061	#define USB_DEVICE_ID_SEMICO_USB_KEYKOARD 0x0023
1061	1062	#define USB_DEVICE_ID_SEMICO_USB_KEYKOARD2 0x0027
1062	1063
	1064	+#define USB_VENDOR_ID_SEMITEK 0x1ea7
	1065	+#define USB_DEVICE_ID_SEMITEK_KEYBOARD 0x0907
	1066	+
1063	1067	#define USB_VENDOR_ID_SENNHEISER 0x1395
1064	1068	#define USB_DEVICE_ID_SENNHEISER_BTD500USB 0x002c
1065	1069
@@ -1161,6 +1165,7 @@ · 95 unmodified lines
1161	1165	#define USB_DEVICE_ID_SYNAPTICS_DELL_K12A 0x2819
1162	1166	#define USB_DEVICE_ID_SYNAPTICS_ACER_SWITCH5_012 0x2968
1163	1167	#define USB_DEVICE_ID_SYNAPTICS_TP_V103 0x5710
	1168	+#define USB_DEVICE_ID_SYNAPTICS_DELL_K15A 0x6e21
1164	1169	#define USB_DEVICE_ID_SYNAPTICS_ACER_ONE_S1002 0x73f4
1165	1170	#define USB_DEVICE_ID_SYNAPTICS_ACER_ONE_S1003 0x73f5
1166	1171	#define USB_DEVICE_ID_SYNAPTICS_ACER_SWITCH5 0x81a7

drivers/hid/hid-input.c+3−0

@@ -964,6 +964,9 @@ static void hidinput_configure_usage(struct hid_input *hidinput, struct hid_fiel · 963 unmodified lines
964	964
965	965	case 0x0cd: map_key_clear(KEY_PLAYPAUSE); break;
966	966	case 0x0cf: map_key_clear(KEY_VOICECOMMAND); break;
	967	+
	968	+ case 0x0d9: map_key_clear(KEY_EMOJI_PICKER); break;
	969	+
967	970	case 0x0e0: map_abs_clear(ABS_VOLUME); break;
968	971	case 0x0e2: map_key_clear(KEY_MUTE); break;
969	972	case 0x0e5: map_key_clear(KEY_BASSBOOST); break;

drivers/hid/hid-logitech-hidpp.c+1−0

@@ -1263,6 +1263,7 @@ static int hidpp20_battery_map_status_voltage(u8 data[3], int *voltage, · 1262 unmodified lines
1263	1263	int status;
1264	1264
1265	1265	long flags = (long) data[2];
	1266	+ *level = POWER_SUPPLY_CAPACITY_LEVEL_UNKNOWN;
1266	1267
1267	1268	if (flags & 0x80)
1268	1269	switch (flags & 0x07) {

drivers/hid/hid-magicmouse.c+5−2

@@ -693,7 +693,7 @@ static int magicmouse_probe(struct hid_device *hdev, · 692 unmodified lines
693	693	if (id->vendor == USB_VENDOR_ID_APPLE &&
694	694	id->product == USB_DEVICE_ID_APPLE_MAGICTRACKPAD2 &&
695	695	hdev->type != HID_TYPE_USBMOUSE)
696		− return 0;
	696	+ return -ENODEV;
697	697
698	698	msc = devm_kzalloc(&hdev->dev, sizeof(*msc), GFP_KERNEL);
699	699	if (msc == NULL) {
@@ -779,7 +779,10 @@ err_stop_hw: · 79 unmodified lines
779	779	static void magicmouse_remove(struct hid_device *hdev)
780	780	{
781	781	struct magicmouse_sc *msc = hid_get_drvdata(hdev);
782		− cancel_delayed_work_sync(&msc->work);
	782	+
	783	+ if (msc)
	784	+ cancel_delayed_work_sync(&msc->work);
	785	+
783	786	hid_hw_stop(hdev);
784	787	}
785	788

drivers/hid/hid-multitouch.c+37−9

@@ -70,6 +70,7 @@ MODULE_LICENSE("GPL"); · 69 unmodified lines
70	70	#define MT_QUIRK_WIN8_PTP_BUTTONS BIT(18)
71	71	#define MT_QUIRK_SEPARATE_APP_REPORT BIT(19)
72	72	#define MT_QUIRK_FORCE_MULTI_INPUT BIT(20)
	73	+#define MT_QUIRK_DISABLE_WAKEUP BIT(21)
73	74
74	75	#define MT_INPUTMODE_TOUCHSCREEN 0x02
75	76	#define MT_INPUTMODE_TOUCHPAD 0x03
@@ -191,6 +192,7 @@ static void mt_post_parse(struct mt_device td, struct mt_application app); · 115 unmodified lines
191	192	#define MT_CLS_EXPORT_ALL_INPUTS 0x0013
192	193	/* reserved 0x0014 */
193	194	#define MT_CLS_WIN_8_FORCE_MULTI_INPUT 0x0015
	195	+#define MT_CLS_WIN_8_DISABLE_WAKEUP 0x0016
194	196
195	197	/* vendor specific classes */
196	198	#define MT_CLS_3M 0x0101
@@ -283,6 +285,15 @@ static const struct mt_class mt_classes[] = { · 86 unmodified lines
283	285	MT_QUIRK_WIN8_PTP_BUTTONS \|
284	286	MT_QUIRK_FORCE_MULTI_INPUT,
285	287	.export_all_inputs = true },
	288	+ { .name = MT_CLS_WIN_8_DISABLE_WAKEUP,
	289	+ .quirks = MT_QUIRK_ALWAYS_VALID \|
	290	+ MT_QUIRK_IGNORE_DUPLICATES \|
	291	+ MT_QUIRK_HOVERING \|
	292	+ MT_QUIRK_CONTACT_CNT_ACCURATE \|
	293	+ MT_QUIRK_STICKY_FINGERS \|
	294	+ MT_QUIRK_WIN8_PTP_BUTTONS \|
	295	+ MT_QUIRK_DISABLE_WAKEUP,
	296	+ .export_all_inputs = true },
286	297
287	298	/*
288	299	* vendor specific classes
@@ -604,9 +615,13 @@ static struct mt_report_data mt_allocate_report_data(struct mt_device td, · 315 unmodified lines
604	615	if (!(HID_MAIN_ITEM_VARIABLE & field->flags))
605	616	continue;
606	617
607		− for (n = 0; n < field->report_count; n++) {
608		− if (field->usage[n].hid == HID_DG_CONTACTID)
609		− rdata->is_mt_collection = true;
	618	+ if (field->logical == HID_DG_FINGER \|\| td->hdev->group != HID_GROUP_MULTITOUCH_WIN_8) {
	619	+ for (n = 0; n < field->report_count; n++) {
	620	+ if (field->usage[n].hid == HID_DG_CONTACTID) {
	621	+ rdata->is_mt_collection = true;
	622	+ break;
	623	+ }
	624	+ }
610	625	}
611	626	}
612	627
@@ -759,7 +774,8 @@ static int mt_touch_input_mapping(struct hid_device hdev, struct hid_input hi, · 146 unmodified lines
759	774	return 1;
760	775	case HID_DG_CONFIDENCE:
761	776	if ((cls->name == MT_CLS_WIN_8 \|\|
762		− cls->name == MT_CLS_WIN_8_FORCE_MULTI_INPUT) &&
	777	+ cls->name == MT_CLS_WIN_8_FORCE_MULTI_INPUT \|\|
	778	+ cls->name == MT_CLS_WIN_8_DISABLE_WAKEUP) &&
763	779	(field->application == HID_DG_TOUCHPAD \|\|
764	780	field->application == HID_DG_TOUCHSCREEN))
765	781	app->quirks \|= MT_QUIRK_CONFIDENCE;
@@ -1576,13 +1592,13 @@ static int mt_input_configured(struct hid_device hdev, struct hid_input hi) · 810 unmodified lines
1576	1592	/* we do not set suffix = "Touchscreen" */
1577	1593	hi->input->name = hdev->name;
1578	1594	break;
1579		− case HID_DG_STYLUS:
1580		− /* force BTN_STYLUS to allow tablet matching in udev */
1581		− __set_bit(BTN_STYLUS, hi->input->keybit);
1582		− break;
1583	1595	case HID_VD_ASUS_CUSTOM_MEDIA_KEYS:
1584	1596	suffix = "Custom Media Keys";
1585	1597	break;
	1598	+ case HID_DG_STYLUS:
	1599	+ /* force BTN_STYLUS to allow tablet matching in udev */
	1600	+ __set_bit(BTN_STYLUS, hi->input->keybit);
	1601	+ fallthrough;
1586	1602	case HID_DG_PEN:
1587	1603	suffix = "Stylus";
1588	1604	break;
@@ -1749,8 +1765,14 @@ static int mt_probe(struct hid_device hdev, const struct hid_device_id id) · 160 unmodified lines
1749	1765	#ifdef CONFIG_PM
1750	1766	static int mt_suspend(struct hid_device *hdev, pm_message_t state)
1751	1767	{
	1768	+ struct mt_device *td = hid_get_drvdata(hdev);
	1769	+
1752	1770	/* High latency is desirable for power savings during S3/S0ix */
1753		− mt_set_modes(hdev, HID_LATENCY_HIGH, true, true);
	1771	+ if (td->mtclass.quirks & MT_QUIRK_DISABLE_WAKEUP)
	1772	+ mt_set_modes(hdev, HID_LATENCY_HIGH, false, false);
	1773	+ else
	1774	+ mt_set_modes(hdev, HID_LATENCY_HIGH, true, true);
	1775	+
1754	1776	return 0;
1755	1777	}
1756	1778
@@ -1809,6 +1831,12 @@ static const struct hid_device_id mt_devices[] = { · 52 unmodified lines
1809	1831	MT_USB_DEVICE(USB_VENDOR_ID_ANTON,
1810	1832	USB_DEVICE_ID_ANTON_TOUCH_PAD) },
1811	1833
	1834	+ /* Asus T101HA */
	1835	+ { .driver_data = MT_CLS_WIN_8_DISABLE_WAKEUP,
	1836	+ HID_DEVICE(BUS_USB, HID_GROUP_MULTITOUCH_WIN_8,
	1837	+ USB_VENDOR_ID_ASUSTEK,
	1838	+ USB_DEVICE_ID_ASUSTEK_T101HA_KEYBOARD) },
	1839	+
1812	1840	/* Asus T304UA */
1813	1841	{ .driver_data = MT_CLS_ASUS,
1814	1842	HID_DEVICE(BUS_USB, HID_GROUP_MULTITOUCH_WIN_8,

drivers/hid/hid-quirks.c+4−0

@@ -110,6 +110,7 @@ static const struct hid_device_id hid_quirks[] = { · 109 unmodified lines
110	110	{ HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_KYE_PENSKETCH_M912), HID_QUIRK_MULTI_INPUT },
111	111	{ HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_KYE_EASYPEN_M406XE), HID_QUIRK_MULTI_INPUT },
112	112	{ HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_PIXART_USB_OPTICAL_MOUSE_ID2), HID_QUIRK_ALWAYS_POLL },
	113	+ { HID_USB_DEVICE(USB_VENDOR_ID_LENOVO, USB_DEVICE_ID_LENOVO_OPTICAL_USB_MOUSE_600E), HID_QUIRK_ALWAYS_POLL },
113	114	{ HID_USB_DEVICE(USB_VENDOR_ID_LENOVO, USB_DEVICE_ID_LENOVO_PIXART_USB_MOUSE_608D), HID_QUIRK_ALWAYS_POLL },
114	115	{ HID_USB_DEVICE(USB_VENDOR_ID_LENOVO, USB_DEVICE_ID_LENOVO_PIXART_USB_MOUSE_6019), HID_QUIRK_ALWAYS_POLL },
115	116	{ HID_USB_DEVICE(USB_VENDOR_ID_LENOVO, USB_DEVICE_ID_LENOVO_PIXART_USB_MOUSE_602E), HID_QUIRK_ALWAYS_POLL },
@@ -158,6 +159,7 @@ static const struct hid_device_id hid_quirks[] = { · 42 unmodified lines
158	159	{ HID_USB_DEVICE(USB_VENDOR_ID_SAITEK, USB_DEVICE_ID_SAITEK_X52), HID_QUIRK_INCREMENT_USAGE_ON_DUPLICATE },
159	160	{ HID_USB_DEVICE(USB_VENDOR_ID_SAITEK, USB_DEVICE_ID_SAITEK_X52_2), HID_QUIRK_INCREMENT_USAGE_ON_DUPLICATE },
160	161	{ HID_USB_DEVICE(USB_VENDOR_ID_SAITEK, USB_DEVICE_ID_SAITEK_X52_PRO), HID_QUIRK_INCREMENT_USAGE_ON_DUPLICATE },
	162	+ { HID_USB_DEVICE(USB_VENDOR_ID_SAITEK, USB_DEVICE_ID_SAITEK_X65), HID_QUIRK_INCREMENT_USAGE_ON_DUPLICATE },
161	163	{ HID_USB_DEVICE(USB_VENDOR_ID_SEMICO, USB_DEVICE_ID_SEMICO_USB_KEYKOARD2), HID_QUIRK_NO_INIT_REPORTS },
162	164	{ HID_USB_DEVICE(USB_VENDOR_ID_SEMICO, USB_DEVICE_ID_SEMICO_USB_KEYKOARD), HID_QUIRK_NO_INIT_REPORTS },
163	165	{ HID_USB_DEVICE(USB_VENDOR_ID_SENNHEISER, USB_DEVICE_ID_SENNHEISER_BTD500USB), HID_QUIRK_NOGET },
@@ -176,6 +178,7 @@ static const struct hid_device_id hid_quirks[] = { · 12 unmodified lines
176	178	{ HID_USB_DEVICE(USB_VENDOR_ID_SYNAPTICS, USB_DEVICE_ID_SYNAPTICS_QUAD_HD), HID_QUIRK_NO_INIT_REPORTS },
177	179	{ HID_USB_DEVICE(USB_VENDOR_ID_SYNAPTICS, USB_DEVICE_ID_SYNAPTICS_TP_V103), HID_QUIRK_NO_INIT_REPORTS },
178	180	{ HID_USB_DEVICE(USB_VENDOR_ID_SYNAPTICS, USB_DEVICE_ID_SYNAPTICS_DELL_K12A), HID_QUIRK_NO_INIT_REPORTS },
	181	+ { HID_USB_DEVICE(USB_VENDOR_ID_SYNAPTICS, USB_DEVICE_ID_SYNAPTICS_DELL_K15A), HID_QUIRK_NO_INIT_REPORTS },
179	182	{ HID_USB_DEVICE(USB_VENDOR_ID_TOPMAX, USB_DEVICE_ID_TOPMAX_COBRAPAD), HID_QUIRK_BADPAD },
180	183	{ HID_USB_DEVICE(USB_VENDOR_ID_TOUCHPACK, USB_DEVICE_ID_TOUCHPACK_RTS), HID_QUIRK_MULTI_INPUT },
181	184	{ HID_USB_DEVICE(USB_VENDOR_ID_TPV, USB_DEVICE_ID_TPV_OPTICAL_TOUCHSCREEN_8882), HID_QUIRK_NOGET },
@@ -211,6 +214,7 @@ static const struct hid_device_id hid_have_special_driver[] = { · 29 unmodified lines
211	214	{ HID_USB_DEVICE(USB_VENDOR_ID_A4TECH, USB_DEVICE_ID_A4TECH_WCP32PU) },
212	215	{ HID_USB_DEVICE(USB_VENDOR_ID_A4TECH, USB_DEVICE_ID_A4TECH_X5_005D) },
213	216	{ HID_USB_DEVICE(USB_VENDOR_ID_A4TECH, USB_DEVICE_ID_A4TECH_RP_649) },
	217	+ { HID_USB_DEVICE(USB_VENDOR_ID_A4TECH, USB_DEVICE_ID_A4TECH_NB_95) },
214	218	#endif
215	219	#if IS_ENABLED(CONFIG_HID_ACCUTOUCH)
216	220	{ HID_USB_DEVICE(USB_VENDOR_ID_ELO, USB_DEVICE_ID_ELO_ACCUTOUCH_2216) },

drivers/hid/hid-semitek.c+40−0

@@ -0,0 +1,40 @@
	1	+// SPDX-License-Identifier: GPL-2.0-or-later
	2	+/*
	3	+ * HID driver for Semitek keyboards
	4	+ *
	5	+ * Copyright (c) 2021 Benjamin Moody
	6	+ */
	7	+
	8	+#include <linux/device.h>
	9	+#include <linux/hid.h>
	10	+#include <linux/module.h>
	11	+
	12	+#include "hid-ids.h"
	13	+
	14	+static __u8 semitek_report_fixup(struct hid_device hdev, __u8 *rdesc,
	15	+ unsigned int *rsize)
	16	+{
	17	+ /* In the report descriptor for interface 2, fix the incorrect
	18	+ description of report ID 0x04 (the report contains a
	19	+ bitmask, not an array of keycodes.) */
	20	+ if (*rsize == 0xcb && rdesc[0x83] == 0x81 && rdesc[0x84] == 0x00) {
	21	+ hid_info(hdev, "fixing up Semitek report descriptor\n");
	22	+ rdesc[0x84] = 0x02;
	23	+ }
	24	+ return rdesc;
	25	+}
	26	+
	27	+static const struct hid_device_id semitek_devices[] = {
	28	+ { HID_USB_DEVICE(USB_VENDOR_ID_SEMITEK, USB_DEVICE_ID_SEMITEK_KEYBOARD) },
	29	+ { }
	30	+};
	31	+MODULE_DEVICE_TABLE(hid, semitek_devices);
	32	+
	33	+static struct hid_driver semitek_driver = {
	34	+ .name = "semitek",
	35	+ .id_table = semitek_devices,
	36	+ .report_fixup = semitek_report_fixup,
	37	+};
	38	+module_hid_driver(semitek_driver);
	39	+
	40	+MODULE_LICENSE("GPL");

drivers/hid/hid-sensor-custom.c+5−3

@@ -387,7 +387,7 @@ static ssize_t store_value(struct device dev, struct device_attribute attr, · 386 unmodified lines
387	387	struct hid_sensor_custom *sensor_inst = dev_get_drvdata(dev);
388	388	int index, field_index, usage;
389	389	char name[HID_CUSTOM_NAME_LENGTH];
390		− int value;
	390	+ int value, ret;
391	391
392	392	if (sscanf(attr->attr.name, "feature-%x-%x-%s", &index, &usage,
393	393	name) == 3) {
@@ -403,8 +403,10 @@ static ssize_t store_value(struct device dev, struct device_attribute attr, · 9 unmodified lines
403	403
404	404	report_id = sensor_inst->fields[field_index].attribute.
405	405	report_id;
406		− sensor_hub_set_feature(sensor_inst->hsdev, report_id,
407		− index, sizeof(value), &value);
	406	+ ret = sensor_hub_set_feature(sensor_inst->hsdev, report_id,
	407	+ index, sizeof(value), &value);
	408	+ if (ret)
	409	+ return ret;
408	410	} else
409	411	return -EINVAL;
410	412

drivers/hid/hid-sensor-hub.c+9−4

@@ -209,16 +209,21 @@ int sensor_hub_set_feature(struct hid_sensor_hub_device *hsdev, u32 report_id, · 208 unmodified lines
209	209	buffer_size = buffer_size / sizeof(__s32);
210	210	if (buffer_size) {
211	211	for (i = 0; i < buffer_size; ++i) {
212		− hid_set_field(report->field[field_index], i,
213		− (__force __s32)cpu_to_le32(*buf32));
	212	+ ret = hid_set_field(report->field[field_index], i,
	213	+ (__force __s32)cpu_to_le32(*buf32));
	214	+ if (ret)
	215	+ goto done_proc;
	216	+
214	217	++buf32;
215	218	}
216	219	}
217	220	if (remaining_bytes) {
218	221	value = 0;
219	222	memcpy(&value, (u8 *)buf32, remaining_bytes);
220		− hid_set_field(report->field[field_index], i,
221		− (__force __s32)cpu_to_le32(value));
	223	+ ret = hid_set_field(report->field[field_index], i,
	224	+ (__force __s32)cpu_to_le32(value));
	225	+ if (ret)
	226	+ goto done_proc;
222	227	}
223	228	hid_hw_request(hsdev->hdev, report, HID_REQ_SET_REPORT);
224	229	hid_hw_wait(hsdev->hdev);

drivers/hid/hid-thrustmaster.c+1−1

@@ -312,7 +312,7 @@ static int thrustmaster_probe(struct hid_device *hdev, const struct hid_device_i · 311 unmodified lines
312	312	}
313	313
314	314	tm_wheel->change_request = kzalloc(sizeof(struct usb_ctrlrequest), GFP_KERNEL);
315		− if (!tm_wheel->model_request) {
	315	+ if (!tm_wheel->change_request) {
316	316	ret = -ENOMEM;
317	317	goto error5;
318	318	}

drivers/hid/i2c-hid/i2c-hid-core.c+10−3

@@ -45,6 +45,7 @@ · 44 unmodified lines
45	45	#define I2C_HID_QUIRK_BOGUS_IRQ BIT(4)
46	46	#define I2C_HID_QUIRK_RESET_ON_RESUME BIT(5)
47	47	#define I2C_HID_QUIRK_BAD_INPUT_SIZE BIT(6)
	48	+#define I2C_HID_QUIRK_NO_WAKEUP_AFTER_RESET BIT(7)
48	49
49	50
50	51	/* flags */
@@ -178,6 +179,11 @@ static const struct i2c_hid_quirks { · 127 unmodified lines
178	179	I2C_HID_QUIRK_RESET_ON_RESUME },
179	180	{ USB_VENDOR_ID_ITE, I2C_DEVICE_ID_ITE_LENOVO_LEGION_Y720,
180	181	I2C_HID_QUIRK_BAD_INPUT_SIZE },
	182	+ /*
	183	+ * Sending the wakeup after reset actually break ELAN touchscreen controller
	184	+ */
	185	+ { USB_VENDOR_ID_ELAN, HID_ANY_ID,
	186	+ I2C_HID_QUIRK_NO_WAKEUP_AFTER_RESET },
181	187	{ 0, 0 }
182	188	};
183	189
@@ -461,7 +467,8 @@ static int i2c_hid_hwreset(struct i2c_client *client) · 277 unmodified lines
461	467	}
462	468
463	469	/* At least some SIS devices need this after reset */
464		− ret = i2c_hid_set_power(client, I2C_HID_PWR_ON);
	470	+ if (!(ihid->quirks & I2C_HID_QUIRK_NO_WAKEUP_AFTER_RESET))
	471	+ ret = i2c_hid_set_power(client, I2C_HID_PWR_ON);
465	472
466	473	out_unlock:
467	474	mutex_unlock(&ihid->reset_lock);
@@ -990,8 +997,8 @@ int i2c_hid_core_probe(struct i2c_client client, struct i2chid_ops ops, · 522 unmodified lines
990	997	hid->vendor = le16_to_cpu(ihid->hdesc.wVendorID);
991	998	hid->product = le16_to_cpu(ihid->hdesc.wProductID);
992	999
993		− snprintf(hid->name, sizeof(hid->name), "%s %04hX:%04hX",
994		− client->name, hid->vendor, hid->product);
	1000	+ snprintf(hid->name, sizeof(hid->name), "%s %04X:%04X",
	1001	+ client->name, (u16)hid->vendor, (u16)hid->product);
995	1002	strlcpy(hid->phys, dev_name(&client->dev), sizeof(hid->phys));
996	1003
997	1004	ihid->quirks = i2c_hid_lookup_quirk(hid->vendor, hid->product);

drivers/hid/intel-ish-hid/ipc/hw-ish.h+2−0

@@ -28,6 +28,8 @@ · 27 unmodified lines
28	28	#define EHL_Ax_DEVICE_ID 0x4BB3
29	29	#define TGL_LP_DEVICE_ID 0xA0FC
30	30	#define TGL_H_DEVICE_ID 0x43FC
	31	+#define ADL_S_DEVICE_ID 0x7AF8
	32	+#define ADL_P_DEVICE_ID 0x51FC
31	33
32	34	#define REVISION_ID_CHT_A0 0x6
33	35	#define REVISION_ID_CHT_Ax_SI 0x0

drivers/hid/intel-ish-hid/ipc/pci-ish.c+2−0

@@ -39,6 +39,8 @@ static const struct pci_device_id ish_pci_tbl[] = { · 38 unmodified lines
39	39	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, EHL_Ax_DEVICE_ID)},
40	40	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, TGL_LP_DEVICE_ID)},
41	41	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, TGL_H_DEVICE_ID)},
	42	+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ADL_S_DEVICE_ID)},
	43	+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ADL_P_DEVICE_ID)},
42	44	{0, }
43	45	};
44	46	MODULE_DEVICE_TABLE(pci, ish_pci_tbl);

drivers/hid/surface-hid/surface_hid_core.c+3−3

@@ -168,9 +168,9 @@ int surface_hid_device_add(struct surface_hid_device *shid) · 167 unmodified lines
168	168
169	169	shid->hid->dev.parent = shid->dev;
170	170	shid->hid->bus = BUS_HOST;
171		− shid->hid->vendor = cpu_to_le16(shid->attrs.vendor);
172		− shid->hid->product = cpu_to_le16(shid->attrs.product);
173		− shid->hid->version = cpu_to_le16(shid->hid_desc.hid_version);
	171	+ shid->hid->vendor = get_unaligned_le16(&shid->attrs.vendor);
	172	+ shid->hid->product = get_unaligned_le16(&shid->attrs.product);
	173	+ shid->hid->version = get_unaligned_le16(&shid->hid_desc.hid_version);
174	174	shid->hid->country = shid->hid_desc.country_code;
175	175
176	176	snprintf(shid->hid->name, sizeof(shid->hid->name), "Microsoft Surface %04X:%04X",

drivers/hid/usbhid/hid-core.c+1−1

@@ -374,7 +374,7 @@ static int hid_submit_ctrl(struct hid_device *hid) · 373 unmodified lines
374	374	raw_report = usbhid->ctrl[usbhid->ctrltail].raw_report;
375	375	dir = usbhid->ctrl[usbhid->ctrltail].dir;
376	376
377		− len = ((report->size - 1) >> 3) + 1 + (report->id > 0);
	377	+ len = hid_report_len(report);
378	378	if (dir == USB_DIR_OUT) {
379	379	usbhid->urbctrl->pipe = usb_sndctrlpipe(hid_to_usb_dev(hid), 0);
380	380	usbhid->urbctrl->transfer_buffer_length = len;

drivers/hid/usbhid/hid-pidff.c+1−0

@@ -1292,6 +1292,7 @@ int hid_pidff_init(struct hid_device *hid) · 1291 unmodified lines
1292	1292
1293	1293	if (pidff->pool[PID_DEVICE_MANAGED_POOL].value &&
1294	1294	pidff->pool[PID_DEVICE_MANAGED_POOL].value[0] == 0) {
	1295	+ error = -EPERM;
1295	1296	hid_notice(hid,
1296	1297	"device does not support device managed pool\n");
1297	1298	goto fail;

drivers/hwmon/adm9240.c+1−1

@@ -485,7 +485,7 @@ static int adm9240_in_write(struct device *dev, u32 attr, int channel, long val) · 484 unmodified lines
485	485	reg = ADM9240_REG_IN_MIN(channel);
486	486	break;
487	487	case hwmon_in_max:
488		− reg = ADM9240_REG_IN(channel);
	488	+ reg = ADM9240_REG_IN_MAX(channel);
489	489	break;
490	490	default:
491	491	return -EOPNOTSUPP;

drivers/hwmon/corsair-psu.c+16−2

@@ -355,7 +355,7 @@ static umode_t corsairpsu_hwmon_power_is_visible(const struct corsairpsu_data *p · 354 unmodified lines
355	355	return 0444;
356	356	default:
357	357	return 0;
358		− };
	358	+ }
359	359	}
360	360
361	361	static umode_t corsairpsu_hwmon_in_is_visible(const struct corsairpsu_data *priv, u32 attr,
@@ -376,7 +376,7 @@ static umode_t corsairpsu_hwmon_in_is_visible(const struct corsairpsu_data *priv · 14 unmodified lines
376	376	break;
377	377	default:
378	378	break;
379		− };
	379	+ }
380	380
381	381	return res;
382	382	}
@@ -771,6 +771,16 @@ static int corsairpsu_raw_event(struct hid_device hdev, struct hid_report repo · 388 unmodified lines
771	771	return 0;
772	772	}
773	773
	774	+#ifdef CONFIG_PM
	775	+static int corsairpsu_resume(struct hid_device *hdev)
	776	+{
	777	+ struct corsairpsu_data *priv = hid_get_drvdata(hdev);
	778	+
	779	+ /* some PSUs turn off the microcontroller during standby, so a reinit is required */
	780	+ return corsairpsu_init(priv);
	781	+}
	782	+#endif
	783	+
774	784	static const struct hid_device_id corsairpsu_idtable[] = {
775	785	{ HID_USB_DEVICE(0x1b1c, 0x1c03) }, /* Corsair HX550i */
776	786	{ HID_USB_DEVICE(0x1b1c, 0x1c04) }, /* Corsair HX650i */
@@ -793,6 +803,10 @@ static struct hid_driver corsairpsu_driver = { · 16 unmodified lines
793	803	.probe = corsairpsu_probe,
794	804	.remove = corsairpsu_remove,
795	805	.raw_event = corsairpsu_raw_event,
	806	+#ifdef CONFIG_PM
	807	+ .resume = corsairpsu_resume,
	808	+ .reset_resume = corsairpsu_resume,
	809	+#endif
796	810	};
797	811	module_hid_driver(corsairpsu_driver);
798	812

drivers/hwmon/dell-smm-hwmon.c+2−2

@@ -838,10 +838,10 @@ static struct attribute *i8k_attrs[] = { · 837 unmodified lines
838	838	static umode_t i8k_is_visible(struct kobject kobj, struct attribute attr,
839	839	int index)
840	840	{
841		− if (disallow_fan_support && index >= 8)
	841	+ if (disallow_fan_support && index >= 20)
842	842	return 0;
843	843	if (disallow_fan_type_call &&
844		− (index == 9 \|\| index == 12 \|\| index == 15))
	844	+ (index == 21 \|\| index == 25 \|\| index == 28))
845	845	return 0;
846	846	if (index >= 0 && index <= 1 &&
847	847	!(i8k_hwmon_flags & I8K_HWMON_HAVE_TEMP1))

drivers/hwmon/lm80.c+2−9

@@ -596,7 +596,6 @@ static int lm80_probe(struct i2c_client *client) · 595 unmodified lines
596	596	struct device *dev = &client->dev;
597	597	struct device *hwmon_dev;
598	598	struct lm80_data *data;
599		− int rv;
600	599
601	600	data = devm_kzalloc(dev, sizeof(struct lm80_data), GFP_KERNEL);
602	601	if (!data)
@@ -609,14 +608,8 @@ static int lm80_probe(struct i2c_client *client) · 6 unmodified lines
609	608	lm80_init_client(client);
610	609
611	610	/* A few vars need to be filled upon startup */
612		− rv = lm80_read_value(client, LM80_REG_FAN_MIN(1));
613		− if (rv < 0)
614		− return rv;
615		− data->fan[f_min][0] = rv;
616		− rv = lm80_read_value(client, LM80_REG_FAN_MIN(2));
617		− if (rv < 0)
618		− return rv;
619		− data->fan[f_min][1] = rv;
	611	+ data->fan[f_min][0] = lm80_read_value(client, LM80_REG_FAN_MIN(1));
	612	+ data->fan[f_min][1] = lm80_read_value(client, LM80_REG_FAN_MIN(2));
620	613
621	614	hwmon_dev = devm_hwmon_device_register_with_groups(dev, client->name,
622	615	data, lm80_groups);

drivers/hwmon/ltc2992.c+6−2

@@ -900,11 +900,15 @@ static int ltc2992_parse_dt(struct ltc2992_state *st) · 899 unmodified lines
900	900
901	901	fwnode_for_each_available_child_node(fwnode, child) {
902	902	ret = fwnode_property_read_u32(child, "reg", &addr);
903		− if (ret < 0)
	903	+ if (ret < 0) {
	904	+ fwnode_handle_put(child);
904	905	return ret;
	906	+ }
905	907
906		− if (addr > 1)
	908	+ if (addr > 1) {
	909	+ fwnode_handle_put(child);
907	910	return -EINVAL;
	911	+ }
908	912
909	913	ret = fwnode_property_read_u32(child, "shunt-resistor-micro-ohms", &val);
910	914	if (!ret)

drivers/hwmon/occ/common.c+3−2

@@ -217,9 +217,9 @@ int occ_update_response(struct occ *occ) · 216 unmodified lines
217	217	return rc;
218	218
219	219	/* limit the maximum rate of polling the OCC */
220		− if (time_after(jiffies, occ->last_update + OCC_UPDATE_FREQUENCY)) {
	220	+ if (time_after(jiffies, occ->next_update)) {
221	221	rc = occ_poll(occ);
222		− occ->last_update = jiffies;
	222	+ occ->next_update = jiffies + OCC_UPDATE_FREQUENCY;
223	223	} else {
224	224	rc = occ->last_error;
225	225	}
@@ -1165,6 +1165,7 @@ int occ_setup(struct occ occ, const char name) · 939 unmodified lines
1165	1165	return rc;
1166	1166	}
1167	1167
	1168	+ occ->next_update = jiffies + OCC_UPDATE_FREQUENCY;
1168	1169	occ_parse_poll_response(occ);
1169	1170
1170	1171	rc = occ_setup_sensor_attrs(occ);

drivers/hwmon/occ/common.h+1−1

@@ -99,7 +99,7 @@ struct occ { · 98 unmodified lines
99	99	u8 poll_cmd_data; /* to perform OCC poll command */
100	100	int (send_cmd)(struct occ occ, u8 *cmd);
101	101
102		− unsigned long last_update;
	102	+ unsigned long next_update;
103	103	struct mutex lock; /* lock OCC access */
104	104
105	105	struct device *hwmon;

drivers/hwmon/pmbus/fsp-3y.c+43−2

@@ -37,6 +37,8 @@ struct fsp3y_data { · 36 unmodified lines
37	37	struct pmbus_driver_info info;
38	38	int chip;
39	39	int page;
	40	+
	41	+ bool vout_linear_11;
40	42	};
41	43
42	44	#define to_fsp3y_data(x) container_of(x, struct fsp3y_data, info)
@@ -57,7 +59,7 @@ static int page_log_to_page_real(int page_log, enum chips chip) · 14 unmodified lines
57	59	case YH5151E_PAGE_12V_LOG:
58	60	return YH5151E_PAGE_12V_REAL;
59	61	case YH5151E_PAGE_5V_LOG:
60		− return YH5151E_PAGE_5V_LOG;
	62	+ return YH5151E_PAGE_5V_REAL;
61	63	case YH5151E_PAGE_3V3_LOG:
62	64	return YH5151E_PAGE_3V3_REAL;
63	65	}
@@ -103,8 +105,16 @@ static int set_page(struct i2c_client *client, int page_log) · 39 unmodified lines
103	105
104	106	static int fsp3y_read_byte_data(struct i2c_client *client, int page, int reg)
105	107	{
	108	+ const struct pmbus_driver_info *info = pmbus_get_driver_info(client);
	109	+ struct fsp3y_data *data = to_fsp3y_data(info);
106	110	int rv;
107	111
	112	+ /*
	113	+ * Inject an exponent for non-compliant YH5151-E.
	114	+ */
	115	+ if (data->vout_linear_11 && reg == PMBUS_VOUT_MODE)
	116	+ return 0x1A;
	117	+
108	118	rv = set_page(client, page);
109	119	if (rv < 0)
110	120	return rv;
@@ -114,6 +124,8 @@ static int fsp3y_read_byte_data(struct i2c_client *client, int page, int reg) · 3 unmodified lines
114	124
115	125	static int fsp3y_read_word_data(struct i2c_client *client, int page, int phase, int reg)
116	126	{
	127	+ const struct pmbus_driver_info *info = pmbus_get_driver_info(client);
	128	+ struct fsp3y_data *data = to_fsp3y_data(info);
117	129	int rv;
118	130
119	131	/*
@@ -144,7 +156,17 @@ static int fsp3y_read_word_data(struct i2c_client *client, int page, int phase, · 24 unmodified lines
144	156	if (rv < 0)
145	157	return rv;
146	158
147		− return i2c_smbus_read_word_data(client, reg);
	159	+ rv = i2c_smbus_read_word_data(client, reg);
	160	+ if (rv < 0)
	161	+ return rv;
	162	+
	163	+ /*
	164	+ * Handle YH-5151E non-compliant linear11 vout voltage.
	165	+ */
	166	+ if (data->vout_linear_11 && reg == PMBUS_READ_VOUT)
	167	+ rv = sign_extend32(rv, 10) & 0xffff;
	168	+
	169	+ return rv;
148	170	}
149	171
150	172	static struct pmbus_driver_info fsp3y_info[] = {
@@ -233,6 +255,25 @@ static int fsp3y_probe(struct i2c_client *client) · 82 unmodified lines
233	255
234	256	data->info = fsp3y_info[data->chip];
235	257
	258	+ /*
	259	+ * YH-5151E sometimes reports vout in linear11 and sometimes in
	260	+ * linear16. This depends on the exact individual piece of hardware. One
	261	+ * YH-5151E can use linear16 and another might use linear11 instead.
	262	+ *
	263	+ * The format can be recognized by reading VOUT_MODE - if it doesn't
	264	+ * report a valid exponent, then vout uses linear11. Otherwise, the
	265	+ * device is compliant and uses linear16.
	266	+ */
	267	+ data->vout_linear_11 = false;
	268	+ if (data->chip == yh5151e) {
	269	+ rv = i2c_smbus_read_byte_data(client, PMBUS_VOUT_MODE);
	270	+ if (rv < 0)
	271	+ return rv;
	272	+
	273	+ if (rv == 0xFF)
	274	+ data->vout_linear_11 = true;
	275	+ }
	276	+
236	277	return pmbus_do_probe(client, &data->info);
237	278	}
238	279

drivers/hwmon/pmbus/isl68137.c+2−2

@@ -244,8 +244,8 @@ static int isl68137_probe(struct i2c_client *client) · 243 unmodified lines
244	244	info->read_word_data = raa_dmpvr2_read_word_data;
245	245	break;
246	246	case raa_dmpvr2_2rail_nontc:
247		− info->func[0] &= ~PMBUS_HAVE_TEMP;
248		− info->func[1] &= ~PMBUS_HAVE_TEMP;
	247	+ info->func[0] &= ~PMBUS_HAVE_TEMP3;
	248	+ info->func[1] &= ~PMBUS_HAVE_TEMP3;
249	249	fallthrough;
250	250	case raa_dmpvr2_2rail:
251	251	info->pages = 2;

drivers/hwmon/pmbus/q54sj108a2.c+1−1

@@ -299,7 +299,7 @@ static int q54sj108a2_probe(struct i2c_client *client) · 298 unmodified lines
299	299	dev_err(&client->dev, "Failed to read Manufacturer ID\n");
300	300	return ret;
301	301	}
302		− if (ret != 5 \|\| strncmp(buf, "DELTA", 5)) {
	302	+ if (ret != 6 \|\| strncmp(buf, "DELTA", 5)) {
303	303	buf[ret] = '\0';
304	304	dev_err(dev, "Unsupported Manufacturer ID '%s'\n", buf);
305	305	return -ENODEV;

drivers/hwmon/scpi-hwmon.c+9−0

@@ -99,6 +99,15 @@ scpi_show_sensor(struct device dev, struct device_attribute attr, char *buf) · 98 unmodified lines
99	99
100	100	scpi_scale_reading(&value, sensor);
101	101
	102	+ /*
	103	+ * Temperature sensor values are treated as signed values based on
	104	+ * observation even though that is not explicitly specified, and
	105	+ * because an unsigned u64 temperature does not really make practical
	106	+ * sense especially when the temperature is below zero degrees Celsius.
	107	+ */
	108	+ if (sensor->info.class == TEMPERATURE)
	109	+ return sprintf(buf, "%lld\n", (s64)value);
	110	+
102	111	return sprintf(buf, "%llu\n", value);
103	112	}
104	113

drivers/hwmon/tps23861.c+15−2

@@ -99,11 +99,14 @@ · 98 unmodified lines
99	99	#define POWER_ENABLE 0x19
100	100	#define TPS23861_NUM_PORTS 4
101	101
	102	+#define TPS23861_GENERAL_MASK_1 0x17
	103	+#define TPS23861_CURRENT_SHUNT_MASK BIT(0)
	104	+
102	105	#define TEMPERATURE_LSB 652 /* 0.652 degrees Celsius */
103	106	#define VOLTAGE_LSB 3662 /* 3.662 mV */
104	107	#define SHUNT_RESISTOR_DEFAULT 255000 /* 255 mOhm */
105		−#define CURRENT_LSB_255 62260 /* 62.260 uA */
106		−#define CURRENT_LSB_250 61039 /* 61.039 uA */
	108	+#define CURRENT_LSB_250 62260 /* 62.260 uA */
	109	+#define CURRENT_LSB_255 61039 /* 61.039 uA */
107	110	#define RESISTANCE_LSB 110966 /* 11.0966 Ohm*/
108	111	#define RESISTANCE_LSB_LOW 157216 /* 15.7216 Ohm*/
109	112
@@ -117,6 +120,7 @@ struct tps23861_data { · 7 unmodified lines
117	120	static struct regmap_config tps23861_regmap_config = {
118	121	.reg_bits = 8,
119	122	.val_bits = 8,
	123	+ .max_register = 0x6f,
120	124	};
121	125
122	126	static int tps23861_read_temp(struct tps23861_data data, long val)
@@ -560,6 +564,15 @@ static int tps23861_probe(struct i2c_client *client) · 437 unmodified lines
560	564	else
561	565	data->shunt_resistor = SHUNT_RESISTOR_DEFAULT;
562	566
	567	+ if (data->shunt_resistor == SHUNT_RESISTOR_DEFAULT)
	568	+ regmap_clear_bits(data->regmap,
	569	+ TPS23861_GENERAL_MASK_1,
	570	+ TPS23861_CURRENT_SHUNT_MASK);
	571	+ else
	572	+ regmap_set_bits(data->regmap,
	573	+ TPS23861_GENERAL_MASK_1,
	574	+ TPS23861_CURRENT_SHUNT_MASK);
	575	+
563	576	hwmon_dev = devm_hwmon_device_register_with_info(dev, client->name,
564	577	data, &tps23861_chip_info,
565	578	NULL);

drivers/i2c/busses/Kconfig+1−1

@@ -647,7 +647,7 @@ config I2C_HIGHLANDER · 646 unmodified lines
647	647
648	648	config I2C_HISI
649	649	tristate "HiSilicon I2C controller"
650		− depends on ARM64 \|\| COMPILE_TEST
	650	+ depends on (ARM64 && ACPI) \|\| COMPILE_TEST
651	651	help
652	652	Say Y here if you want to have Hisilicon I2C controller support
653	653	available on the Kunpeng Server.

drivers/i2c/busses/i2c-ali1563.c+1−1

@@ -1,5 +1,5 @@
1	1	// SPDX-License-Identifier: GPL-2.0-only
2		−/**
	2	+/*
3	3	* i2c-ali1563.c - i2c driver for the ALi 1563 Southbridge
4	4	*
5	5	* Copyright (C) 2004 Patrick Mochel

drivers/i2c/busses/i2c-altera.c+4−5

@@ -55,7 +55,7 @@ · 54 unmodified lines
55	55	#define ALTR_I2C_XFER_TIMEOUT (msecs_to_jiffies(250))
56	56
57	57	/**
58		− * altr_i2c_dev - I2C device context
	58	+ * struct altr_i2c_dev - I2C device context
59	59	* @base: pointer to register struct
60	60	* @msg: pointer to current message
61	61	* @msg_len: number of bytes transferred in msg
@@ -172,7 +172,7 @@ static void altr_i2c_init(struct altr_i2c_dev *idev) · 110 unmodified lines
172	172	altr_i2c_int_enable(idev, ALTR_I2C_ALL_IRQ, false);
173	173	}
174	174
175		−/**
	175	+/*
176	176	* altr_i2c_transfer - On the last byte to be transmitted, send
177	177	* a Stop bit on the last byte.
178	178	*/
@@ -185,7 +185,7 @@ static void altr_i2c_transfer(struct altr_i2c_dev *idev, u32 data) · 6 unmodified lines
185	185	writel(data, idev->base + ALTR_I2C_TFR_CMD);
186	186	}
187	187
188		−/**
	188	+/*
189	189	* altr_i2c_empty_rx_fifo - Fetch data from RX FIFO until end of
190	190	* transfer. Send a Stop bit on the last byte.
191	191	*/
@@ -201,9 +201,8 @@ static void altr_i2c_empty_rx_fifo(struct altr_i2c_dev *idev) · 9 unmodified lines
201	201	}
202	202	}
203	203
204		−/**
	204	+/*
205	205	* altr_i2c_fill_tx_fifo - Fill TX FIFO from current message buffer.
206		− * @return: Number of bytes left to transfer.
207	206	*/
208	207	static int altr_i2c_fill_tx_fifo(struct altr_i2c_dev *idev)
209	208	{

drivers/i2c/busses/i2c-cadence.c+1−1

@@ -144,7 +144,7 @@ enum cdns_i2c_mode { · 143 unmodified lines
144	144	};
145	145
146	146	/**
147		− * enum cdns_i2c_slave_mode - Slave state when I2C is operating in slave mode
	147	+ * enum cdns_i2c_slave_state - Slave state when I2C is operating in slave mode
148	148	*
149	149	* @CDNS_I2C_SLAVE_STATE_IDLE: I2C slave idle
150	150	* @CDNS_I2C_SLAVE_STATE_SEND: I2C slave sending data to master

drivers/i2c/busses/i2c-designware-master.c+1−1

@@ -165,7 +165,7 @@ static int i2c_dw_set_timings_master(struct dw_i2c_dev *dev) · 164 unmodified lines
165	165	}
166	166
167	167	/**
168		− * i2c_dw_init() - Initialize the designware I2C master hardware
	168	+ * i2c_dw_init_master() - Initialize the designware I2C master hardware
169	169	* @dev: device private data
170	170	*
171	171	* This functions configures and enables the I2C master.

drivers/i2c/busses/i2c-eg20t.c+2−1

@@ -148,7 +148,7 @@ struct i2c_algo_pch_data { · 147 unmodified lines
148	148
149	149	/**
150	150	* struct adapter_info - This structure holds the adapter information for the
151		− PCH i2c controller
	151	+ * PCH i2c controller
152	152	* @pch_data: stores a list of i2c_algo_pch_data
153	153	* @pch_i2c_suspended: specifies whether the system is suspended or not
154	154	* perhaps with more lines and words.
@@ -358,6 +358,7 @@ static void pch_i2c_repstart(struct i2c_algo_pch_data *adap) · 203 unmodified lines
358	358	/**
359	359	* pch_i2c_writebytes() - write data to I2C bus in normal mode
360	360	* @i2c_adap: Pointer to the struct i2c_adapter.
	361	+ * @msgs: Pointer to the i2c message structure.
361	362	* @last: specifies whether last message or not.
362	363	* In the case of compound mode it will be 1 for last message,
363	364	* otherwise 0.

drivers/i2c/busses/i2c-i801.c+2−4

@@ -395,11 +395,9 @@ static int i801_check_post(struct i801_priv *priv, int status) · 394 unmodified lines
395	395	dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
396	396	/* try to stop the current command */
397	397	dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
398		− outb_p(inb_p(SMBHSTCNT(priv)) \| SMBHSTCNT_KILL,
399		− SMBHSTCNT(priv));
	398	+ outb_p(SMBHSTCNT_KILL, SMBHSTCNT(priv));
400	399	usleep_range(1000, 2000);
401		− outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
402		− SMBHSTCNT(priv));
	400	+ outb_p(0, SMBHSTCNT(priv));
403	401
404	402	/* Check if it worked */
405	403	status = inb_p(SMBHSTSTS(priv));

drivers/i2c/busses/i2c-icy.c+0−1

@@ -123,7 +123,6 @@ static int icy_probe(struct zorro_dev *z, · 122 unmodified lines
123	123	{
124	124	struct icy_i2c *i2c;
125	125	struct i2c_algo_pcf_data *algo_data;
126		− struct fwnode_handle *new_fwnode;
127	126	struct i2c_board_info ltc2990_info = {
128	127	.type = "ltc2990",
129	128	.swnode = &icy_ltc2990_node,

drivers/i2c/busses/i2c-mpc.c+79−2

@@ -19,6 +19,7 @@ · 18 unmodified lines
19	19
20	20	#include <linux/clk.h>
21	21	#include <linux/io.h>
	22	+#include <linux/iopoll.h>
22	23	#include <linux/fsl_devices.h>
23	24	#include <linux/i2c.h>
24	25	#include <linux/interrupt.h>
@@ -45,6 +46,7 @@ · 20 unmodified lines
45	46	#define CCR_MTX 0x10
46	47	#define CCR_TXAK 0x08
47	48	#define CCR_RSTA 0x04
	49	+#define CCR_RSVD 0x02
48	50
49	51	#define CSR_MCF 0x80
50	52	#define CSR_MAAS 0x40
@@ -97,7 +99,7 @@ struct mpc_i2c { · 46 unmodified lines
97	99	u32 block;
98	100	int rc;
99	101	int expect_rxack;
100		−
	102	+ bool has_errata_A004447;
101	103	};
102	104
103	105	struct mpc_i2c_divider {
@@ -136,6 +138,75 @@ static void mpc_i2c_fixup(struct mpc_i2c *i2c) · 32 unmodified lines
136	138	}
137	139	}
138	140
	141	+static int i2c_mpc_wait_sr(struct mpc_i2c *i2c, int mask)
	142	+{
	143	+ void __iomem *addr = i2c->base + MPC_I2C_SR;
	144	+ u8 val;
	145	+
	146	+ return readb_poll_timeout(addr, val, val & mask, 0, 100);
	147	+}
	148	+
	149	+/*
	150	+ * Workaround for Erratum A004447. From the P2040CE Rev Q
	151	+ *
	152	+ * 1. Set up the frequency divider and sampling rate.
	153	+ * 2. I2CCR - a0h
	154	+ * 3. Poll for I2CSR[MBB] to get set.
	155	+ * 4. If I2CSR[MAL] is set (an indication that SDA is stuck low), then go to
	156	+ * step 5. If MAL is not set, then go to step 13.
	157	+ * 5. I2CCR - 00h
	158	+ * 6. I2CCR - 22h
	159	+ * 7. I2CCR - a2h
	160	+ * 8. Poll for I2CSR[MBB] to get set.
	161	+ * 9. Issue read to I2CDR.
	162	+ * 10. Poll for I2CSR[MIF] to be set.
	163	+ * 11. I2CCR - 82h
	164	+ * 12. Workaround complete. Skip the next steps.
	165	+ * 13. Issue read to I2CDR.
	166	+ * 14. Poll for I2CSR[MIF] to be set.
	167	+ * 15. I2CCR - 80h
	168	+ */
	169	+static void mpc_i2c_fixup_A004447(struct mpc_i2c *i2c)
	170	+{
	171	+ int ret;
	172	+ u32 val;
	173	+
	174	+ writeccr(i2c, CCR_MEN \| CCR_MSTA);
	175	+ ret = i2c_mpc_wait_sr(i2c, CSR_MBB);
	176	+ if (ret) {
	177	+ dev_err(i2c->dev, "timeout waiting for CSR_MBB\n");
	178	+ return;
	179	+ }
	180	+
	181	+ val = readb(i2c->base + MPC_I2C_SR);
	182	+
	183	+ if (val & CSR_MAL) {
	184	+ writeccr(i2c, 0x00);
	185	+ writeccr(i2c, CCR_MSTA \| CCR_RSVD);
	186	+ writeccr(i2c, CCR_MEN \| CCR_MSTA \| CCR_RSVD);
	187	+ ret = i2c_mpc_wait_sr(i2c, CSR_MBB);
	188	+ if (ret) {
	189	+ dev_err(i2c->dev, "timeout waiting for CSR_MBB\n");
	190	+ return;
	191	+ }
	192	+ val = readb(i2c->base + MPC_I2C_DR);
	193	+ ret = i2c_mpc_wait_sr(i2c, CSR_MIF);
	194	+ if (ret) {
	195	+ dev_err(i2c->dev, "timeout waiting for CSR_MIF\n");
	196	+ return;
	197	+ }
	198	+ writeccr(i2c, CCR_MEN \| CCR_RSVD);
	199	+ } else {
	200	+ val = readb(i2c->base + MPC_I2C_DR);
	201	+ ret = i2c_mpc_wait_sr(i2c, CSR_MIF);
	202	+ if (ret) {
	203	+ dev_err(i2c->dev, "timeout waiting for CSR_MIF\n");
	204	+ return;
	205	+ }
	206	+ writeccr(i2c, CCR_MEN);
	207	+ }
	208	+}
	209	+
139	210	#if defined(CONFIG_PPC_MPC52xx) \|\| defined(CONFIG_PPC_MPC512x)
140	211	static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = {
141	212	{20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23},
@@ -670,7 +741,10 @@ static int fsl_i2c_bus_recovery(struct i2c_adapter *adap) · 528 unmodified lines
670	741	{
671	742	struct mpc_i2c *i2c = i2c_get_adapdata(adap);
672	743
673		− mpc_i2c_fixup(i2c);
	744	+ if (i2c->has_errata_A004447)
	745	+ mpc_i2c_fixup_A004447(i2c);
	746	+ else
	747	+ mpc_i2c_fixup(i2c);
674	748
675	749	return 0;
676	750	}
@@ -767,6 +841,9 @@ static int fsl_i2c_probe(struct platform_device *op) · 90 unmodified lines
767	841	}
768	842	dev_info(i2c->dev, "timeout %u us\n", mpc_ops.timeout * 1000000 / HZ);
769	843
	844	+ if (of_property_read_bool(op->dev.of_node, "fsl,i2c-erratum-a004447"))
	845	+ i2c->has_errata_A004447 = true;
	846	+
770	847	i2c->adap = mpc_ops;
771	848	scnprintf(i2c->adap.name, sizeof(i2c->adap.name),
772	849	"MPC adapter (%s)", of_node_full_name(op->dev.of_node));

drivers/i2c/busses/i2c-mt65xx.c+5−0

@@ -479,6 +479,11 @@ static void mtk_i2c_clock_disable(struct mtk_i2c *i2c) · 478 unmodified lines
479	479	static void mtk_i2c_init_hw(struct mtk_i2c *i2c)
480	480	{
481	481	u16 control_reg;
	482	+ u16 intr_stat_reg;
	483	+
	484	+ mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_START);
	485	+ intr_stat_reg = mtk_i2c_readw(i2c, OFFSET_INTR_STAT);
	486	+ mtk_i2c_writew(i2c, intr_stat_reg, OFFSET_INTR_STAT);
482	487
483	488	if (i2c->dev_comp->apdma_sync) {
484	489	writel(I2C_DMA_WARM_RST, i2c->pdmabase + OFFSET_RST);

drivers/i2c/busses/i2c-nomadik.c+1−1

@@ -159,7 +159,7 @@ struct i2c_nmk_client { · 158 unmodified lines
159	159	* @clk_freq: clock frequency for the operation mode
160	160	* @tft: Tx FIFO Threshold in bytes
161	161	* @rft: Rx FIFO Threshold in bytes
162		− * @timeout Slave response timeout (ms)
	162	+ * @timeout: Slave response timeout (ms)
163	163	* @sm: speed mode
164	164	* @stop: stop condition.
165	165	* @xfer_complete: acknowledge completion for a I2C message.

drivers/i2c/busses/i2c-ocores.c+4−4

@@ -250,7 +250,7 @@ static irqreturn_t ocores_isr(int irq, void *dev_id) · 249 unmodified lines
250	250	}
251	251
252	252	/**
253		− * Process timeout event
	253	+ * ocores_process_timeout() - Process timeout event
254	254	* @i2c: ocores I2C device instance
255	255	*/
256	256	static void ocores_process_timeout(struct ocores_i2c *i2c)
@@ -264,7 +264,7 @@ static void ocores_process_timeout(struct ocores_i2c *i2c) · 7 unmodified lines
264	264	}
265	265
266	266	/**
267		− * Wait until something change in a given register
	267	+ * ocores_wait() - Wait until something change in a given register
268	268	* @i2c: ocores I2C device instance
269	269	* @reg: register to query
270	270	* @mask: bitmask to apply on register value
@@ -296,7 +296,7 @@ static int ocores_wait(struct ocores_i2c *i2c, · 25 unmodified lines
296	296	}
297	297
298	298	/**
299		− * Wait until is possible to process some data
	299	+ * ocores_poll_wait() - Wait until is possible to process some data
300	300	* @i2c: ocores I2C device instance
301	301	*
302	302	* Used when the device is in polling mode (interrupts disabled).
@@ -334,7 +334,7 @@ static int ocores_poll_wait(struct ocores_i2c *i2c) · 31 unmodified lines
334	334	}
335	335
336	336	/**
337		− * It handles an IRQ-less transfer
	337	+ * ocores_process_polling() - It handles an IRQ-less transfer
338	338	* @i2c: ocores I2C device instance
339	339	*
340	340	* Even if IRQ are disabled, the I2C OpenCore IP behavior is exactly the same

drivers/i2c/busses/i2c-pnx.c+4−4

@@ -138,7 +138,7 @@ static inline void i2c_pnx_arm_timer(struct i2c_pnx_algo_data *alg_data) · 137 unmodified lines
138	138	/**
139	139	* i2c_pnx_start - start a device
140	140	* @slave_addr: slave address
141		− * @adap: pointer to adapter structure
	141	+ * @alg_data: pointer to local driver data structure
142	142	*
143	143	* Generate a START signal in the desired mode.
144	144	*/
@@ -194,7 +194,7 @@ static int i2c_pnx_start(unsigned char slave_addr, · 49 unmodified lines
194	194
195	195	/**
196	196	* i2c_pnx_stop - stop a device
197		− * @adap: pointer to I2C adapter structure
	197	+ * @alg_data: pointer to local driver data structure
198	198	*
199	199	* Generate a STOP signal to terminate the master transaction.
200	200	*/
@@ -223,7 +223,7 @@ static void i2c_pnx_stop(struct i2c_pnx_algo_data *alg_data) · 22 unmodified lines
223	223
224	224	/**
225	225	* i2c_pnx_master_xmit - transmit data to slave
226		− * @adap: pointer to I2C adapter structure
	226	+ * @alg_data: pointer to local driver data structure
227	227	*
228	228	* Sends one byte of data to the slave
229	229	*/
@@ -293,7 +293,7 @@ static int i2c_pnx_master_xmit(struct i2c_pnx_algo_data *alg_data) · 63 unmodified lines
293	293
294	294	/**
295	295	* i2c_pnx_master_rcv - receive data from slave
296		− * @adap: pointer to I2C adapter structure
	296	+ * @alg_data: pointer to local driver data structure
297	297	*
298	298	* Reads one byte data from the slave
299	299	*/

drivers/i2c/busses/i2c-qcom-geni.c+21−2

@@ -100,7 +100,7 @@ static const struct geni_i2c_err_log gi2c_log[] = { · 99 unmodified lines
100	100	[GP_IRQ0] = {-EIO, "Unknown I2C err GP_IRQ0"},
101	101	[NACK] = {-ENXIO, "NACK: slv unresponsive, check its power/reset-ln"},
102	102	[GP_IRQ2] = {-EIO, "Unknown I2C err GP IRQ2"},
103		− [BUS_PROTO] = {-EPROTO, "Bus proto err, noisy/unepxected start/stop"},
	103	+ [BUS_PROTO] = {-EPROTO, "Bus proto err, noisy/unexpected start/stop"},
104	104	[ARB_LOST] = {-EAGAIN, "Bus arbitration lost, clock line undriveable"},
105	105	[GP_IRQ5] = {-EIO, "Unknown I2C err GP IRQ5"},
106	106	[GENI_OVERRUN] = {-EIO, "Cmd overrun, check GENI cmd-state machine"},
@@ -650,6 +650,14 @@ static int geni_i2c_remove(struct platform_device *pdev) · 543 unmodified lines
650	650	return 0;
651	651	}
652	652
	653	+static void geni_i2c_shutdown(struct platform_device *pdev)
	654	+{
	655	+ struct geni_i2c_dev *gi2c = platform_get_drvdata(pdev);
	656	+
	657	+ /* Make client i2c transfers start failing */
	658	+ i2c_mark_adapter_suspended(&gi2c->adap);
	659	+}
	660	+
653	661	static int __maybe_unused geni_i2c_runtime_suspend(struct device *dev)
654	662	{
655	663	int ret;
@@ -690,6 +698,8 @@ static int __maybe_unused geni_i2c_suspend_noirq(struct device *dev) · 34 unmodified lines
690	698	{
691	699	struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
692	700
	701	+ i2c_mark_adapter_suspended(&gi2c->adap);
	702	+
693	703	if (!gi2c->suspended) {
694	704	geni_i2c_runtime_suspend(dev);
695	705	pm_runtime_disable(dev);
@@ -699,8 +709,16 @@ static int __maybe_unused geni_i2c_suspend_noirq(struct device *dev) · 3 unmodified lines
699	709	return 0;
700	710	}
701	711
	712	+static int __maybe_unused geni_i2c_resume_noirq(struct device *dev)
	713	+{
	714	+ struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
	715	+
	716	+ i2c_mark_adapter_resumed(&gi2c->adap);
	717	+ return 0;
	718	+}
	719	+
702	720	static const struct dev_pm_ops geni_i2c_pm_ops = {
703		− SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(geni_i2c_suspend_noirq, NULL)
	721	+ SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(geni_i2c_suspend_noirq, geni_i2c_resume_noirq)
704	722	SET_RUNTIME_PM_OPS(geni_i2c_runtime_suspend, geni_i2c_runtime_resume,
705	723	NULL)
706	724	};
@@ -714,6 +732,7 @@ MODULE_DEVICE_TABLE(of, geni_i2c_dt_match); · 7 unmodified lines
714	732	static struct platform_driver geni_i2c_driver = {
715	733	.probe = geni_i2c_probe,
716	734	.remove = geni_i2c_remove,
	735	+ .shutdown = geni_i2c_shutdown,
717	736	.driver = {
718	737	.name = "geni_i2c",
719	738	.pm = &geni_i2c_pm_ops,

drivers/i2c/busses/i2c-s3c2410.c+3−0

@@ -480,7 +480,10 @@ static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat) · 479 unmodified lines
480	480	* forces us to send a new START
481	481	* when we change direction
482	482	*/
	483	+ dev_dbg(i2c->dev,
	484	+ "missing START before write->read\n");
483	485	s3c24xx_i2c_stop(i2c, -EINVAL);
	486	+ break;
484	487	}
485	488
486	489	goto retry_write;

drivers/i2c/busses/i2c-sh_mobile.c+1−1

@@ -807,7 +807,7 @@ static const struct sh_mobile_dt_config r8a7740_dt_config = { · 806 unmodified lines
807	807	static const struct of_device_id sh_mobile_i2c_dt_ids[] = {
808	808	{ .compatible = "renesas,iic-r8a73a4", .data = &fast_clock_dt_config },
809	809	{ .compatible = "renesas,iic-r8a7740", .data = &r8a7740_dt_config },
810		− { .compatible = "renesas,iic-r8a774c0", .data = &fast_clock_dt_config },
	810	+ { .compatible = "renesas,iic-r8a774c0", .data = &v2_freq_calc_dt_config },
811	811	{ .compatible = "renesas,iic-r8a7790", .data = &v2_freq_calc_dt_config },
812	812	{ .compatible = "renesas,iic-r8a7791", .data = &v2_freq_calc_dt_config },
813	813	{ .compatible = "renesas,iic-r8a7792", .data = &v2_freq_calc_dt_config },

drivers/i2c/busses/i2c-st.c+2−2

@@ -524,7 +524,7 @@ static void st_i2c_handle_write(struct st_i2c_dev *i2c_dev) · 523 unmodified lines
524	524	}
525	525
526	526	/**
527		− * st_i2c_handle_write() - Handle FIFO enmpty interrupt in case of read
	527	+ * st_i2c_handle_read() - Handle FIFO empty interrupt in case of read
528	528	* @i2c_dev: Controller's private data
529	529	*/
530	530	static void st_i2c_handle_read(struct st_i2c_dev *i2c_dev)
@@ -558,7 +558,7 @@ static void st_i2c_handle_read(struct st_i2c_dev *i2c_dev) · 27 unmodified lines
558	558	}
559	559
560	560	/**
561		− * st_i2c_isr() - Interrupt routine
	561	+ * st_i2c_isr_thread() - Interrupt routine
562	562	* @irq: interrupt number
563	563	* @data: Controller's private data
564	564	*/

drivers/i2c/busses/i2c-stm32f4.c+1−1

@@ -313,7 +313,7 @@ static int stm32f4_i2c_wait_free_bus(struct stm32f4_i2c_dev *i2c_dev) · 312 unmodified lines
313	313	}
314	314
315	315	/**
316		− * stm32f4_i2c_write_ byte() - Write a byte in the data register
	316	+ * stm32f4_i2c_write_byte() - Write a byte in the data register
317	317	* @i2c_dev: Controller's private data
318	318	* @byte: Data to write in the register
319	319	*/

drivers/i2c/busses/i2c-tegra-bpmp.c+2−2

@@ -65,7 +65,7 @@ static void tegra_bpmp_xlate_flags(u16 flags, u16 *out) · 64 unmodified lines
65	65	*out \|= SERIALI2C_RECV_LEN;
66	66	}
67	67
68		−/**
	68	+/*
69	69	* The serialized I2C format is simply the following:
70	70	* [addr little-endian][flags little-endian][len little-endian][data if write]
71	71	* [addr little-endian][flags little-endian][len little-endian][data if write]
@@ -109,7 +109,7 @@ static void tegra_bpmp_serialize_i2c_msg(struct tegra_bpmp_i2c *i2c, · 37 unmodified lines
109	109	request->xfer.data_size = pos;
110	110	}
111	111
112		−/**
	112	+/*
113	113	* The data in the BPMP -> CPU direction is composed of sequential blocks for
114	114	* those messages that have I2C_M_RD. So, for example, if you have:
115	115	*

drivers/i2c/muxes/i2c-arb-gpio-challenge.c+2−2

@@ -34,7 +34,7 @@ struct i2c_arbitrator_data { · 33 unmodified lines
34	34	};
35	35
36	36
37		−/**
	37	+/*
38	38	* i2c_arbitrator_select - claim the I2C bus
39	39	*
40	40	* Use the GPIO-based signalling protocol; return -EBUSY if we fail.
@@ -77,7 +77,7 @@ static int i2c_arbitrator_select(struct i2c_mux_core *muxc, u32 chan) · 36 unmodified lines
77	77	return -EBUSY;
78	78	}
79	79
80		−/**
	80	+/*
81	81	* i2c_arbitrator_deselect - release the I2C bus
82	82	*
83	83	* Release the I2C bus using the GPIO-based signalling protocol.

drivers/iio/accel/Kconfig+0−1

@@ -229,7 +229,6 @@ config DMARD10 · 228 unmodified lines
229	229	config HID_SENSOR_ACCEL_3D
230	230	depends on HID_SENSOR_HUB
231	231	select IIO_BUFFER
232		− select IIO_TRIGGERED_BUFFER
233	232	select HID_SENSOR_IIO_COMMON
234	233	select HID_SENSOR_IIO_TRIGGER
235	234	tristate "HID Accelerometers 3D"

drivers/iio/adc/ad7124.c+20−16

@@ -771,6 +771,13 @@ static int ad7124_of_parse_channel_config(struct iio_dev *indio_dev, · 770 unmodified lines
771	771	if (ret)
772	772	goto err;
773	773
	774	+ if (channel >= indio_dev->num_channels) {
	775	+ dev_err(indio_dev->dev.parent,
	776	+ "Channel index >= number of channels\n");
	777	+ ret = -EINVAL;
	778	+ goto err;
	779	+ }
	780	+
774	781	ret = of_property_read_u32_array(child, "diff-channels",
775	782	ain, 2);
776	783	if (ret)
@@ -850,6 +857,11 @@ static int ad7124_setup(struct ad7124_state *st) · 73 unmodified lines
850	857	return ret;
851	858	}
852	859
	860	+static void ad7124_reg_disable(void *r)
	861	+{
	862	+ regulator_disable(r);
	863	+}
	864	+
853	865	static int ad7124_probe(struct spi_device *spi)
854	866	{
855	867	const struct ad7124_chip_info *info;
@@ -895,17 +907,20 @@ static int ad7124_probe(struct spi_device *spi) · 39 unmodified lines
895	907	ret = regulator_enable(st->vref[i]);
896	908	if (ret)
897	909	return ret;
	910	+
	911	+ ret = devm_add_action_or_reset(&spi->dev, ad7124_reg_disable,
	912	+ st->vref[i]);
	913	+ if (ret)
	914	+ return ret;
898	915	}
899	916
900	917	st->mclk = devm_clk_get(&spi->dev, "mclk");
901		− if (IS_ERR(st->mclk)) {
902		− ret = PTR_ERR(st->mclk);
903		− goto error_regulator_disable;
904		− }
	918	+ if (IS_ERR(st->mclk))
	919	+ return PTR_ERR(st->mclk);
905	920
906	921	ret = clk_prepare_enable(st->mclk);
907	922	if (ret < 0)
908		− goto error_regulator_disable;
	923	+ return ret;
909	924
910	925	ret = ad7124_soft_reset(st);
911	926	if (ret < 0)
@@ -935,11 +950,6 @@ error_remove_trigger: · 23 unmodified lines
935	950	ad_sd_cleanup_buffer_and_trigger(indio_dev);
936	951	error_clk_disable_unprepare:
937	952	clk_disable_unprepare(st->mclk);
938		−error_regulator_disable:
939		− for (i = ARRAY_SIZE(st->vref) - 1; i >= 0; i--) {
940		− if (!IS_ERR_OR_NULL(st->vref[i]))
941		− regulator_disable(st->vref[i]);
942		− }
943	953
944	954	return ret;
945	955	}
@@ -948,17 +958,11 @@ static int ad7124_remove(struct spi_device *spi) · 2 unmodified lines
948	958	{
949	959	struct iio_dev *indio_dev = spi_get_drvdata(spi);
950	960	struct ad7124_state *st = iio_priv(indio_dev);
951		− int i;
952	961
953	962	iio_device_unregister(indio_dev);
954	963	ad_sd_cleanup_buffer_and_trigger(indio_dev);
955	964	clk_disable_unprepare(st->mclk);
956	965
957		− for (i = ARRAY_SIZE(st->vref) - 1; i >= 0; i--) {
958		− if (!IS_ERR_OR_NULL(st->vref[i]))
959		− regulator_disable(st->vref[i]);
960		− }
961		−
962	966	return 0;
963	967	}
964	968

drivers/iio/adc/ad7192.c+10−9

@@ -912,7 +912,7 @@ static int ad7192_probe(struct spi_device *spi) · 911 unmodified lines
912	912	{
913	913	struct ad7192_state *st;
914	914	struct iio_dev *indio_dev;
915		− int ret, voltage_uv = 0;
	915	+ int ret;
916	916
917	917	if (!spi->irq) {
918	918	dev_err(&spi->dev, "no IRQ?\n");
@@ -949,15 +949,12 @@ static int ad7192_probe(struct spi_device *spi) · 30 unmodified lines
949	949	goto error_disable_avdd;
950	950	}
951	951
952		− voltage_uv = regulator_get_voltage(st->avdd);
953		−
954		− if (voltage_uv > 0) {
955		− st->int_vref_mv = voltage_uv / 1000;
956		− } else {
957		− ret = voltage_uv;
	952	+ ret = regulator_get_voltage(st->avdd);
	953	+ if (ret < 0) {
958	954	dev_err(&spi->dev, "Device tree error, reference voltage undefined\n");
959	955	goto error_disable_avdd;
960	956	}
	957	+ st->int_vref_mv = ret / 1000;
961	958
962	959	spi_set_drvdata(spi, indio_dev);
963	960	st->chip_info = of_device_get_match_data(&spi->dev);
@@ -1014,7 +1011,9 @@ static int ad7192_probe(struct spi_device *spi) · 50 unmodified lines
1014	1011	return 0;
1015	1012
1016	1013	error_disable_clk:
1017		− clk_disable_unprepare(st->mclk);
	1014	+ if (st->clock_sel == AD7192_CLK_EXT_MCLK1_2 \|\|
	1015	+ st->clock_sel == AD7192_CLK_EXT_MCLK2)
	1016	+ clk_disable_unprepare(st->mclk);
1018	1017	error_remove_trigger:
1019	1018	ad_sd_cleanup_buffer_and_trigger(indio_dev);
1020	1019	error_disable_dvdd:
@@ -1031,7 +1030,9 @@ static int ad7192_remove(struct spi_device *spi) · 10 unmodified lines
1031	1030	struct ad7192_state *st = iio_priv(indio_dev);
1032	1031
1033	1032	iio_device_unregister(indio_dev);
1034		− clk_disable_unprepare(st->mclk);
	1033	+ if (st->clock_sel == AD7192_CLK_EXT_MCLK1_2 \|\|
	1034	+ st->clock_sel == AD7192_CLK_EXT_MCLK2)
	1035	+ clk_disable_unprepare(st->mclk);
1035	1036	ad_sd_cleanup_buffer_and_trigger(indio_dev);
1036	1037
1037	1038	regulator_disable(st->dvdd);

drivers/iio/adc/ad7768-1.c+6−2

@@ -167,6 +167,10 @@ struct ad7768_state { · 166 unmodified lines
167	167	* transfer buffers to live in their own cache lines.
168	168	*/
169	169	union {
	170	+ struct {
	171	+ __be32 chan;
	172	+ s64 timestamp;
	173	+ } scan;
170	174	__be32 d32;
171	175	u8 d8[2];
172	176	} data ____cacheline_aligned;
@@ -469,11 +473,11 @@ static irqreturn_t ad7768_trigger_handler(int irq, void *p) · 296 unmodified lines
469	473
470	474	mutex_lock(&st->lock);
471	475
472		− ret = spi_read(st->spi, &st->data.d32, 3);
	476	+ ret = spi_read(st->spi, &st->data.scan.chan, 3);
473	477	if (ret < 0)
474	478	goto err_unlock;
475	479
476		− iio_push_to_buffers_with_timestamp(indio_dev, &st->data.d32,
	480	+ iio_push_to_buffers_with_timestamp(indio_dev, &st->data.scan,
477	481	iio_get_time_ns(indio_dev));
478	482
479	483	iio_trigger_notify_done(indio_dev->trig);

drivers/iio/adc/ad7793.c+1−0

@@ -279,6 +279,7 @@ static int ad7793_setup(struct iio_dev *indio_dev, · 278 unmodified lines
279	279	id &= AD7793_ID_MASK;
280	280
281	281	if (id != st->chip_info->id) {
	282	+ ret = -ENODEV;
282	283	dev_err(&st->sd.spi->dev, "device ID query failed\n");
283	284	goto out;
284	285	}

drivers/iio/adc/ad7923.c+3−1

@@ -59,8 +59,10 @@ struct ad7923_state { · 58 unmodified lines
59	59	/*
60	60	* DMA (thus cache coherency maintenance) requires the
61	61	* transfer buffers to live in their own cache lines.
	62	+ * Ensure rx_buf can be directly used in iio_push_to_buffers_with_timetamp
	63	+ * Length = 8 channels + 4 extra for 8 byte timestamp
62	64	*/
63		− __be16 rx_buf[4] ____cacheline_aligned;
	65	+ __be16 rx_buf[12] ____cacheline_aligned;
64	66	__be16 tx_buf[4];
65	67	};
66	68

drivers/iio/common/hid-sensors/Kconfig+1−0

@@ -19,6 +19,7 @@ config HID_SENSOR_IIO_TRIGGER · 18 unmodified lines
19	19	tristate "Common module (trigger) for all HID Sensor IIO drivers"
20	20	depends on HID_SENSOR_HUB && HID_SENSOR_IIO_COMMON && IIO_BUFFER
21	21	select IIO_TRIGGER
	22	+ select IIO_TRIGGERED_BUFFER
22	23	help
23	24	Say yes here to build trigger support for HID sensors.
24	25	Triggers will be send if all requested attributes were read.

drivers/iio/dac/ad5770r.c+11−5

@@ -524,23 +524,29 @@ static int ad5770r_channel_config(struct ad5770r_state *st) · 523 unmodified lines
524	524	device_for_each_child_node(&st->spi->dev, child) {
525	525	ret = fwnode_property_read_u32(child, "num", &num);
526	526	if (ret)
527		− return ret;
528		− if (num >= AD5770R_MAX_CHANNELS)
529		− return -EINVAL;
	527	+ goto err_child_out;
	528	+ if (num >= AD5770R_MAX_CHANNELS) {
	529	+ ret = -EINVAL;
	530	+ goto err_child_out;
	531	+ }
530	532
531	533	ret = fwnode_property_read_u32_array(child,
532	534	"adi,range-microamp",
533	535	tmp, 2);
534	536	if (ret)
535		− return ret;
	537	+ goto err_child_out;
536	538
537	539	min = tmp[0] / 1000;
538	540	max = tmp[1] / 1000;
539	541	ret = ad5770r_store_output_range(st, min, max, num);
540	542	if (ret)
541		− return ret;
	543	+ goto err_child_out;
542	544	}
543	545
	546	+ return 0;
	547	+
	548	+err_child_out:
	549	+ fwnode_handle_put(child);
544	550	return ret;
545	551	}
546	552

drivers/iio/gyro/Kconfig+0−1

@@ -111,7 +111,6 @@ config FXAS21002C_SPI · 110 unmodified lines
111	111	config HID_SENSOR_GYRO_3D
112	112	depends on HID_SENSOR_HUB
113	113	select IIO_BUFFER
114		− select IIO_TRIGGERED_BUFFER
115	114	select HID_SENSOR_IIO_COMMON
116	115	select HID_SENSOR_IIO_TRIGGER
117	116	tristate "HID Gyroscope 3D"

drivers/iio/gyro/fxas21002c_core.c+2−0

@@ -399,6 +399,7 @@ static int fxas21002c_temp_get(struct fxas21002c_data data, int val) · 398 unmodified lines
399	399	ret = regmap_field_read(data->regmap_fields[F_TEMP], &temp);
400	400	if (ret < 0) {
401	401	dev_err(dev, "failed to read temp: %d\n", ret);
	402	+ fxas21002c_pm_put(data);
402	403	goto data_unlock;
403	404	}
404	405
@@ -432,6 +433,7 @@ static int fxas21002c_axis_get(struct fxas21002c_data *data, · 27 unmodified lines
432	433	&axis_be, sizeof(axis_be));
433	434	if (ret < 0) {
434	435	dev_err(dev, "failed to read axis: %d: %d\n", index, ret);
	436	+ fxas21002c_pm_put(data);
435	437	goto data_unlock;
436	438	}
437	439

drivers/iio/gyro/mpu3050-core.c+11−2

@@ -272,7 +272,16 @@ static int mpu3050_read_raw(struct iio_dev *indio_dev, · 271 unmodified lines
272	272	case IIO_CHAN_INFO_OFFSET:
273	273	switch (chan->type) {
274	274	case IIO_TEMP:
275		− /* The temperature scaling is (x+23000)/280 Celsius */
	275	+ /*
	276	+ * The temperature scaling is (x+23000)/280 Celsius
	277	+ * for the "best fit straight line" temperature range
	278	+ * of -30C..85C. The 23000 includes room temperature
	279	+ * offset of +35C, 280 is the precision scale and x is
	280	+ * the 16-bit signed integer reported by hardware.
	281	+ *
	282	+ * Temperature value itself represents temperature of
	283	+ * the sensor die.
	284	+ */
276	285	*val = 23000;
277	286	return IIO_VAL_INT;
278	287	default:
@@ -329,7 +338,7 @@ static int mpu3050_read_raw(struct iio_dev *indio_dev, · 50 unmodified lines
329	338	goto out_read_raw_unlock;
330	339	}
331	340
332		− *val = be16_to_cpu(raw_val);
	341	+ *val = (s16)be16_to_cpu(raw_val);
333	342	ret = IIO_VAL_INT;
334	343
335	344	goto out_read_raw_unlock;

drivers/iio/humidity/Kconfig+0−1

@@ -52,7 +52,6 @@ config HID_SENSOR_HUMIDITY · 51 unmodified lines
52	52	tristate "HID Environmental humidity sensor"
53	53	depends on HID_SENSOR_HUB
54	54	select IIO_BUFFER
55		− select IIO_TRIGGERED_BUFFER
56	55	select HID_SENSOR_IIO_COMMON
57	56	select HID_SENSOR_IIO_TRIGGER
58	57	help

drivers/iio/industrialio-core.c+1−8

@@ -1778,7 +1778,6 @@ static long iio_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) · 1777 unmodified lines
1778	1778	if (!indio_dev->info)
1779	1779	goto out_unlock;
1780	1780
1781		− ret = -EINVAL;
1782	1781	list_for_each_entry(h, &iio_dev_opaque->ioctl_handlers, entry) {
1783	1782	ret = h->ioctl(indio_dev, filp, cmd, arg);
1784	1783	if (ret != IIO_IOCTL_UNHANDLED)
@@ -1786,7 +1785,7 @@ static long iio_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) · 1 unmodified line
1786	1785	}
1787	1786
1788	1787	if (ret == IIO_IOCTL_UNHANDLED)
1789		− ret = -EINVAL;
	1788	+ ret = -ENODEV;
1790	1789
1791	1790	out_unlock:
1792	1791	mutex_unlock(&indio_dev->info_exist_lock);
@@ -1926,9 +1925,6 @@ EXPORT_SYMBOL(__iio_device_register); · 133 unmodified lines
1926	1925	**/
1927	1926	void iio_device_unregister(struct iio_dev *indio_dev)
1928	1927	{
1929		− struct iio_dev_opaque *iio_dev_opaque = to_iio_dev_opaque(indio_dev);
1930		− struct iio_ioctl_handler h, t;
1931		−
1932	1928	cdev_device_del(&indio_dev->chrdev, &indio_dev->dev);
1933	1929
1934	1930	mutex_lock(&indio_dev->info_exist_lock);
@@ -1939,9 +1935,6 @@ void iio_device_unregister(struct iio_dev *indio_dev) · 4 unmodified lines
1939	1935
1940	1936	indio_dev->info = NULL;
1941	1937
1942		− list_for_each_entry_safe(h, t, &iio_dev_opaque->ioctl_handlers, entry)
1943		− list_del(&h->entry);
1944		−
1945	1938	iio_device_wakeup_eventset(indio_dev);
1946	1939	iio_buffer_wakeup_poll(indio_dev);
1947	1940

drivers/iio/light/Kconfig+0−2

@@ -256,7 +256,6 @@ config ISL29125 · 255 unmodified lines
256	256	config HID_SENSOR_ALS
257	257	depends on HID_SENSOR_HUB
258	258	select IIO_BUFFER
259		− select IIO_TRIGGERED_BUFFER
260	259	select HID_SENSOR_IIO_COMMON
261	260	select HID_SENSOR_IIO_TRIGGER
262	261	tristate "HID ALS"
@@ -270,7 +269,6 @@ config HID_SENSOR_ALS · 7 unmodified lines
270	269	config HID_SENSOR_PROX
271	270	depends on HID_SENSOR_HUB
272	271	select IIO_BUFFER
273		− select IIO_TRIGGERED_BUFFER
274	272	select HID_SENSOR_IIO_COMMON
275	273	select HID_SENSOR_IIO_TRIGGER
276	274	tristate "HID PROX"

drivers/iio/light/gp2ap002.c+3−2

@@ -582,7 +582,7 @@ static int gp2ap002_probe(struct i2c_client *client, · 581 unmodified lines
582	582	"gp2ap002", indio_dev);
583	583	if (ret) {
584	584	dev_err(dev, "unable to request IRQ\n");
585		− goto out_disable_vio;
	585	+ goto out_put_pm;
586	586	}
587	587	gp2ap002->irq = client->irq;
588	588
@@ -612,8 +612,9 @@ static int gp2ap002_probe(struct i2c_client *client, · 23 unmodified lines
612	612
613	613	return 0;
614	614
615		−out_disable_pm:
	615	+out_put_pm:
616	616	pm_runtime_put_noidle(dev);
	617	+out_disable_pm:
617	618	pm_runtime_disable(dev);
618	619	out_disable_vio:
619	620	regulator_disable(gp2ap002->vio);

drivers/iio/light/tsl2583.c+8−0

@@ -341,6 +341,14 @@ static int tsl2583_als_calibrate(struct iio_dev *indio_dev) · 340 unmodified lines
341	341	return lux_val;
342	342	}
343	343
	344	+ /* Avoid division by zero of lux_value later on */
	345	+ if (lux_val == 0) {
	346	+ dev_err(&chip->client->dev,
	347	+ "%s: lux_val of 0 will produce out of range trim_value\n",
	348	+ __func__);
	349	+ return -ENODATA;
	350	+ }
	351	+
344	352	gain_trim_val = (unsigned int)(((chip->als_settings.als_cal_target)
345	353	* chip->als_settings.als_gain_trim) / lux_val);
346	354	if ((gain_trim_val < 250) \|\| (gain_trim_val > 4000)) {

drivers/iio/magnetometer/Kconfig+0−1

@@ -95,7 +95,6 @@ config MAG3110 · 94 unmodified lines
95	95	config HID_SENSOR_MAGNETOMETER_3D
96	96	depends on HID_SENSOR_HUB
97	97	select IIO_BUFFER
98		− select IIO_TRIGGERED_BUFFER
99	98	select HID_SENSOR_IIO_COMMON
100	99	select HID_SENSOR_IIO_TRIGGER
101	100	tristate "HID Magenetometer 3D"

drivers/iio/orientation/Kconfig+0−2

@@ -9,7 +9,6 @@ menu "Inclinometer sensors" · 8 unmodified lines
9	9	config HID_SENSOR_INCLINOMETER_3D
10	10	depends on HID_SENSOR_HUB
11	11	select IIO_BUFFER
12		− select IIO_TRIGGERED_BUFFER
13	12	select HID_SENSOR_IIO_COMMON
14	13	select HID_SENSOR_IIO_TRIGGER
15	14	tristate "HID Inclinometer 3D"
@@ -20,7 +19,6 @@ config HID_SENSOR_INCLINOMETER_3D · 4 unmodified lines
20	19	config HID_SENSOR_DEVICE_ROTATION
21	20	depends on HID_SENSOR_HUB
22	21	select IIO_BUFFER
23		− select IIO_TRIGGERED_BUFFER
24	22	select HID_SENSOR_IIO_COMMON
25	23	select HID_SENSOR_IIO_TRIGGER
26	24	tristate "HID Device Rotation"

drivers/iio/pressure/Kconfig+0−1

@@ -79,7 +79,6 @@ config DPS310 · 78 unmodified lines
79	79	config HID_SENSOR_PRESS
80	80	depends on HID_SENSOR_HUB
81	81	select IIO_BUFFER
82		− select IIO_TRIGGERED_BUFFER
83	82	select HID_SENSOR_IIO_COMMON
84	83	select HID_SENSOR_IIO_TRIGGER
85	84	tristate "HID PRESS"

drivers/iio/proximity/pulsedlight-lidar-lite-v2.c+1−0

@@ -160,6 +160,7 @@ static int lidar_get_measurement(struct lidar_data data, u16 reg) · 159 unmodified lines
160	160	ret = lidar_write_control(data, LIDAR_REG_CONTROL_ACQUIRE);
161	161	if (ret < 0) {
162	162	dev_err(&client->dev, "cannot send start measurement command");
	163	+ pm_runtime_put_noidle(&client->dev);
163	164	return ret;
164	165	}
165	166

drivers/iio/temperature/Kconfig+0−1

@@ -45,7 +45,6 @@ config HID_SENSOR_TEMP · 44 unmodified lines
45	45	tristate "HID Environmental temperature sensor"
46	46	depends on HID_SENSOR_HUB
47	47	select IIO_BUFFER
48		− select IIO_TRIGGERED_BUFFER
49	48	select HID_SENSOR_IIO_COMMON
50	49	select HID_SENSOR_IIO_TRIGGER
51	50	help

drivers/infiniband/core/cma.c+3−2

@@ -473,6 +473,7 @@ static void cma_release_dev(struct rdma_id_private *id_priv) · 472 unmodified lines
473	473	list_del(&id_priv->list);
474	474	cma_dev_put(id_priv->cma_dev);
475	475	id_priv->cma_dev = NULL;
	476	+ id_priv->id.device = NULL;
476	477	if (id_priv->id.route.addr.dev_addr.sgid_attr) {
477	478	rdma_put_gid_attr(id_priv->id.route.addr.dev_addr.sgid_attr);
478	479	id_priv->id.route.addr.dev_addr.sgid_attr = NULL;
@@ -1860,6 +1861,7 @@ static void _destroy_id(struct rdma_id_private *id_priv, · 1381 unmodified lines
1860	1861	iw_destroy_cm_id(id_priv->cm_id.iw);
1861	1862	}
1862	1863	cma_leave_mc_groups(id_priv);
	1864	+ rdma_restrack_del(&id_priv->res);
1863	1865	cma_release_dev(id_priv);
1864	1866	}
1865	1867
@@ -1873,7 +1875,6 @@ static void _destroy_id(struct rdma_id_private *id_priv, · 7 unmodified lines
1873	1875	kfree(id_priv->id.route.path_rec);
1874	1876
1875	1877	put_net(id_priv->id.route.addr.dev_addr.net);
1876		− rdma_restrack_del(&id_priv->res);
1877	1878	kfree(id_priv);
1878	1879	}
1879	1880
@@ -3774,7 +3775,7 @@ int rdma_listen(struct rdma_cm_id *id, int backlog) · 1894 unmodified lines
3774	3775	}
3775	3776
3776	3777	id_priv->backlog = backlog;
3777		− if (id->device) {
	3778	+ if (id_priv->cma_dev) {
3778	3779	if (rdma_cap_ib_cm(id->device, 1)) {
3779	3780	ret = cma_ib_listen(id_priv);
3780	3781	if (ret)

drivers/infiniband/core/uverbs_cmd.c+5−0

@@ -3265,6 +3265,11 @@ static int ib_uverbs_ex_create_flow(struct uverbs_attr_bundle *attrs) · 3264 unmodified lines
3265	3265	goto err_free_attr;
3266	3266	}
3267	3267
	3268	+ if (!rdma_is_port_valid(uobj->context->device, cmd.flow_attr.port)) {
	3269	+ err = -EINVAL;
	3270	+ goto err_uobj;
	3271	+ }
	3272	+
3268	3273	qp = uobj_get_obj_read(qp, UVERBS_OBJECT_QP, cmd.qp_handle, attrs);
3269	3274	if (!qp) {
3270	3275	err = -EINVAL;

drivers/infiniband/core/uverbs_std_types_device.c+5−2

@@ -117,8 +117,8 @@ static int UVERBS_HANDLER(UVERBS_METHOD_INFO_HANDLES)( · 116 unmodified lines
117	117	return ret;
118	118
119	119	uapi_object = uapi_get_object(attrs->ufile->device->uapi, object_id);
120		− if (!uapi_object)
121		− return -EINVAL;
	120	+ if (IS_ERR(uapi_object))
	121	+ return PTR_ERR(uapi_object);
122	122
123	123	handles = gather_objects_handle(attrs->ufile, uapi_object, attrs,
124	124	out_len, &total);
@@ -331,6 +331,9 @@ static int UVERBS_HANDLER(UVERBS_METHOD_QUERY_GID_TABLE)( · 206 unmodified lines
331	331	if (ret)
332	332	return ret;
333	333
	334	+ if (!user_entry_size)
	335	+ return -EINVAL;
	336	+
334	337	max_entries = uverbs_attr_ptr_get_array_size(
335	338	attrs, UVERBS_ATTR_QUERY_GID_TABLE_RESP_ENTRIES,
336	339	user_entry_size);

drivers/infiniband/hw/mlx4/main.c+1−7

@@ -581,12 +581,9 @@ static int mlx4_ib_query_device(struct ib_device *ibdev, · 580 unmodified lines
581	581	props->cq_caps.max_cq_moderation_count = MLX4_MAX_CQ_COUNT;
582	582	props->cq_caps.max_cq_moderation_period = MLX4_MAX_CQ_PERIOD;
583	583
584		− if (!mlx4_is_slave(dev->dev))
585		− err = mlx4_get_internal_clock_params(dev->dev, &clock_params);
586		−
587	584	if (uhw->outlen >= resp.response_length + sizeof(resp.hca_core_clock_offset)) {
588	585	resp.response_length += sizeof(resp.hca_core_clock_offset);
589		− if (!err && !mlx4_is_slave(dev->dev)) {
	586	+ if (!mlx4_get_internal_clock_params(dev->dev, &clock_params)) {
590	587	resp.comp_mask \|= MLX4_IB_QUERY_DEV_RESP_MASK_CORE_CLOCK_OFFSET;
591	588	resp.hca_core_clock_offset = clock_params.offset % PAGE_SIZE;
592	589	}
@@ -1702,9 +1699,6 @@ static struct ib_flow mlx4_ib_create_flow(struct ib_qp qp, · 1109 unmodified lines
1702	1699	struct mlx4_dev *dev = (to_mdev(qp->device))->dev;
1703	1700	int is_bonded = mlx4_is_bonded(dev);
1704	1701
1705		− if (!rdma_is_port_valid(qp->device, flow_attr->port))
1706		− return ERR_PTR(-EINVAL);
1707		−
1708	1702	if (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP)
1709	1703	return ERR_PTR(-EOPNOTSUPP);
1710	1704

drivers/infiniband/hw/mlx5/cq.c+4−5

@@ -849,15 +849,14 @@ static void destroy_cq_user(struct mlx5_ib_cq cq, struct ib_udata udata) · 848 unmodified lines
849	849	ib_umem_release(cq->buf.umem);
850	850	}
851	851
852		−static void init_cq_frag_buf(struct mlx5_ib_cq *cq,
853		− struct mlx5_ib_cq_buf *buf)
	852	+static void init_cq_frag_buf(struct mlx5_ib_cq_buf *buf)
854	853	{
855	854	int i;
856	855	void *cqe;
857	856	struct mlx5_cqe64 *cqe64;
858	857
859	858	for (i = 0; i < buf->nent; i++) {
860		− cqe = get_cqe(cq, i);
	859	+ cqe = mlx5_frag_buf_get_wqe(&buf->fbc, i);
861	860	cqe64 = buf->cqe_size == 64 ? cqe : cqe + 64;
862	861	cqe64->op_own = MLX5_CQE_INVALID << 4;
863	862	}
@@ -883,7 +882,7 @@ static int create_cq_kernel(struct mlx5_ib_dev dev, struct mlx5_ib_cq cq, · 19 unmodified lines
883	882	if (err)
884	883	goto err_db;
885	884
886		− init_cq_frag_buf(cq, &cq->buf);
	885	+ init_cq_frag_buf(&cq->buf);
887	886
888	887	*inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
889	888	MLX5_FLD_SZ_BYTES(create_cq_in, pas[0]) *
@@ -1184,7 +1183,7 @@ static int resize_kernel(struct mlx5_ib_dev dev, struct mlx5_ib_cq cq, · 294 unmodified lines
1184	1183	if (err)
1185	1184	goto ex;
1186	1185
1187		− init_cq_frag_buf(cq, cq->resize_buf);
	1186	+ init_cq_frag_buf(cq->resize_buf);
1188	1187
1189	1188	return 0;
1190	1189

drivers/infiniband/hw/mlx5/devx.c+2−4

@@ -630,9 +630,8 @@ static bool devx_is_valid_obj_id(struct uverbs_attr_bundle *attrs, · 629 unmodified lines
630	630	case UVERBS_OBJECT_QP:
631	631	{
632	632	struct mlx5_ib_qp *qp = to_mqp(uobj->object);
633		− enum ib_qp_type qp_type = qp->ibqp.qp_type;
634	633
635		− if (qp_type == IB_QPT_RAW_PACKET \|\|
	634	+ if (qp->type == IB_QPT_RAW_PACKET \|\|
636	635	(qp->flags & IB_QP_CREATE_SOURCE_QPN)) {
637	636	struct mlx5_ib_raw_packet_qp *raw_packet_qp =
638	637	&qp->raw_packet_qp;
@@ -649,10 +648,9 @@ static bool devx_is_valid_obj_id(struct uverbs_attr_bundle *attrs, · 10 unmodified lines
649	648	sq->tisn) == obj_id);
650	649	}
651	650
652		− if (qp_type == MLX5_IB_QPT_DCT)
	651	+ if (qp->type == MLX5_IB_QPT_DCT)
653	652	return get_enc_obj_id(MLX5_CMD_OP_CREATE_DCT,
654	653	qp->dct.mdct.mqp.qpn) == obj_id;
655		−
656	654	return get_enc_obj_id(MLX5_CMD_OP_CREATE_QP,
657	655	qp->ibqp.qp_num) == obj_id;
658	656	}

drivers/infiniband/hw/mlx5/dm.c+3−0

@@ -217,6 +217,9 @@ static int UVERBS_HANDLER(MLX5_IB_METHOD_DM_MAP_OP_ADDR)( · 216 unmodified lines
217	217	if (err)
218	218	return err;
219	219
	220	+ if (op >= BITS_PER_TYPE(u32))
	221	+ return -EOPNOTSUPP;
	222	+
220	223	if (!(MLX5_CAP_DEV_MEM(dev->mdev, memic_operations) & BIT(op)))
221	224	return -EOPNOTSUPP;
222	225

drivers/infiniband/hw/mlx5/doorbell.c+6−1

@@ -41,6 +41,7 @@ struct mlx5_ib_user_db_page { · 40 unmodified lines
41	41	struct ib_umem *umem;
42	42	unsigned long user_virt;
43	43	int refcnt;
	44	+ struct mm_struct *mm;
44	45	};
45	46
46	47	int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, unsigned long virt,
@@ -52,7 +53,8 @@ int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, unsigned long virt, · 5 unmodified lines
52	53	mutex_lock(&context->db_page_mutex);
53	54
54	55	list_for_each_entry(page, &context->db_page_list, list)
55		− if (page->user_virt == (virt & PAGE_MASK))
	56	+ if ((current->mm == page->mm) &&
	57	+ (page->user_virt == (virt & PAGE_MASK)))
56	58	goto found;
57	59
58	60	page = kmalloc(sizeof(*page), GFP_KERNEL);
@@ -70,6 +72,8 @@ int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, unsigned long virt, · 11 unmodified lines
70	72	kfree(page);
71	73	goto out;
72	74	}
	75	+ mmgrab(current->mm);
	76	+ page->mm = current->mm;
73	77
74	78	list_add(&page->list, &context->db_page_list);
75	79
@@ -90,6 +94,7 @@ void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext context, struct mlx5_db db) · 14 unmodified lines
90	94
91	95	if (!--db->u.user_page->refcnt) {
92	96	list_del(&db->u.user_page->list);
	97	+ mmdrop(db->u.user_page->mm);
93	98	ib_umem_release(db->u.user_page->umem);
94	99	kfree(db->u.user_page);
95	100	}

drivers/infiniband/hw/mlx5/fs.c+8−3

@@ -1194,9 +1194,8 @@ static struct ib_flow mlx5_ib_create_flow(struct ib_qp qp, · 1193 unmodified lines
1194	1194	goto free_ucmd;
1195	1195	}
1196	1196
1197		− if (flow_attr->port > dev->num_ports \|\|
1198		− (flow_attr->flags &
1199		− ~(IB_FLOW_ATTR_FLAGS_DONT_TRAP \| IB_FLOW_ATTR_FLAGS_EGRESS))) {
	1197	+ if (flow_attr->flags &
	1198	+ ~(IB_FLOW_ATTR_FLAGS_DONT_TRAP \| IB_FLOW_ATTR_FLAGS_EGRESS)) {
1200	1199	err = -EINVAL;
1201	1200	goto free_ucmd;
1202	1201	}
@@ -2134,6 +2133,12 @@ static int UVERBS_HANDLER(MLX5_IB_METHOD_FLOW_MATCHER_CREATE)( · 931 unmodified lines
2134	2133	if (err)
2135	2134	goto end;
2136	2135
	2136	+ if (obj->ns_type == MLX5_FLOW_NAMESPACE_FDB &&
	2137	+ mlx5_eswitch_mode(dev->mdev) != MLX5_ESWITCH_OFFLOADS) {
	2138	+ err = -EINVAL;
	2139	+ goto end;
	2140	+ }
	2141	+
2137	2142	uobj->object = obj;
2138	2143	obj->mdev = dev->mdev;
2139	2144	atomic_set(&obj->usecnt, 0);

drivers/infiniband/hw/mlx5/main.c+1−0

@@ -4423,6 +4423,7 @@ static int mlx5r_mp_probe(struct auxiliary_device *adev, · 4422 unmodified lines
4423	4423
4424	4424	if (bound) {
4425	4425	rdma_roce_rescan_device(&dev->ib_dev);
	4426	+ mpi->ibdev->ib_active = true;
4426	4427	break;
4427	4428	}
4428	4429	}

drivers/infiniband/hw/mlx5/mr.c+4−4

@@ -744,10 +744,10 @@ int mlx5_mr_cache_init(struct mlx5_ib_dev *dev) · 743 unmodified lines
744	744	ent->xlt = (1 << ent->order) * sizeof(struct mlx5_mtt) /
745	745	MLX5_IB_UMR_OCTOWORD;
746	746	ent->access_mode = MLX5_MKC_ACCESS_MODE_MTT;
747		− if ((dev->mdev->profile->mask & MLX5_PROF_MASK_MR_CACHE) &&
	747	+ if ((dev->mdev->profile.mask & MLX5_PROF_MASK_MR_CACHE) &&
748	748	!dev->is_rep && mlx5_core_is_pf(dev->mdev) &&
749	749	mlx5_ib_can_load_pas_with_umr(dev, 0))
750		− ent->limit = dev->mdev->profile->mr_cache[i].limit;
	750	+ ent->limit = dev->mdev->profile.mr_cache[i].limit;
751	751	else
752	752	ent->limit = 0;
753	753	spin_lock_irq(&ent->lock);
@@ -1942,8 +1942,8 @@ int mlx5_ib_dereg_mr(struct ib_mr ibmr, struct ib_udata udata) · 1188 unmodified lines
1942	1942	mlx5r_deref_wait_odp_mkey(&mr->mmkey);
1943	1943
1944	1944	if (ibmr->type == IB_MR_TYPE_INTEGRITY) {
1945		− xa_cmpxchg(&dev->sig_mrs, mlx5_base_mkey(mr->mmkey.key), ibmr,
1946		− NULL, GFP_KERNEL);
	1945	+ xa_cmpxchg(&dev->sig_mrs, mlx5_base_mkey(mr->mmkey.key),
	1946	+ mr->sig, NULL, GFP_KERNEL);
1947	1947
1948	1948	if (mr->mtt_mr) {
1949	1949	rc = mlx5_ib_dereg_mr(&mr->mtt_mr->ibmr, NULL);

drivers/infiniband/sw/rxe/rxe_comp.c+10−6

@@ -350,13 +350,15 @@ static inline enum comp_state do_read(struct rxe_qp *qp, · 349 unmodified lines
350	350	ret = copy_data(qp->pd, IB_ACCESS_LOCAL_WRITE,
351	351	&wqe->dma, payload_addr(pkt),
352	352	payload_size(pkt), RXE_TO_MR_OBJ, NULL);
353		− if (ret)
	353	+ if (ret) {
	354	+ wqe->status = IB_WC_LOC_PROT_ERR;
354	355	return COMPST_ERROR;
	356	+ }
355	357
356	358	if (wqe->dma.resid == 0 && (pkt->mask & RXE_END_MASK))
357	359	return COMPST_COMP_ACK;
358		− else
359		− return COMPST_UPDATE_COMP;
	360	+
	361	+ return COMPST_UPDATE_COMP;
360	362	}
361	363
362	364	static inline enum comp_state do_atomic(struct rxe_qp *qp,
@@ -370,10 +372,12 @@ static inline enum comp_state do_atomic(struct rxe_qp *qp, · 7 unmodified lines
370	372	ret = copy_data(qp->pd, IB_ACCESS_LOCAL_WRITE,
371	373	&wqe->dma, &atomic_orig,
372	374	sizeof(u64), RXE_TO_MR_OBJ, NULL);
373		− if (ret)
	375	+ if (ret) {
	376	+ wqe->status = IB_WC_LOC_PROT_ERR;
374	377	return COMPST_ERROR;
375		− else
376		− return COMPST_COMP_ACK;
	378	+ }
	379	+
	380	+ return COMPST_COMP_ACK;
377	381	}
378	382
379	383	static void make_send_cqe(struct rxe_qp qp, struct rxe_send_wqe wqe,

drivers/infiniband/sw/rxe/rxe_qp.c+7−0

@@ -244,6 +244,7 @@ static int rxe_qp_init_req(struct rxe_dev rxe, struct rxe_qp qp, · 243 unmodified lines
244	244	if (err) {
245	245	vfree(qp->sq.queue->buf);
246	246	kfree(qp->sq.queue);
	247	+ qp->sq.queue = NULL;
247	248	return err;
248	249	}
249	250
@@ -304,6 +305,7 @@ static int rxe_qp_init_resp(struct rxe_dev rxe, struct rxe_qp qp, · 54 unmodified lines
304	305	if (err) {
305	306	vfree(qp->rq.queue->buf);
306	307	kfree(qp->rq.queue);
	308	+ qp->rq.queue = NULL;
307	309	return err;
308	310	}
309	311	}
@@ -366,6 +368,11 @@ int rxe_qp_from_init(struct rxe_dev rxe, struct rxe_qp qp, struct rxe_pd *pd, · 56 unmodified lines
366	368	err2:
367	369	rxe_queue_cleanup(qp->sq.queue);
368	370	err1:
	371	+ qp->pd = NULL;
	372	+ qp->rcq = NULL;
	373	+ qp->scq = NULL;
	374	+ qp->srq = NULL;
	375	+
369	376	if (srq)
370	377	rxe_drop_ref(srq);
371	378	rxe_drop_ref(scq);

drivers/infiniband/sw/siw/siw_verbs.c+4−7

@@ -300,7 +300,6 @@ struct ib_qp siw_create_qp(struct ib_pd pd, · 299 unmodified lines
300	300	struct siw_ucontext *uctx =
301	301	rdma_udata_to_drv_context(udata, struct siw_ucontext,
302	302	base_ucontext);
303		− struct siw_cq scq = NULL, rcq = NULL;
304	303	unsigned long flags;
305	304	int num_sqe, num_rqe, rv = 0;
306	305	size_t length;
@@ -343,10 +342,8 @@ struct ib_qp siw_create_qp(struct ib_pd pd, · 36 unmodified lines
343	342	rv = -EINVAL;
344	343	goto err_out;
345	344	}
346		− scq = to_siw_cq(attrs->send_cq);
347		− rcq = to_siw_cq(attrs->recv_cq);
348	345
349		− if (!scq \|\| (!rcq && !attrs->srq)) {
	346	+ if (!attrs->send_cq \|\| (!attrs->recv_cq && !attrs->srq)) {
350	347	siw_dbg(base_dev, "send CQ or receive CQ invalid\n");
351	348	rv = -EINVAL;
352	349	goto err_out;
@@ -378,7 +375,7 @@ struct ib_qp siw_create_qp(struct ib_pd pd, · 25 unmodified lines
378	375	else {
379	376	/* Zero sized SQ is not supported */
380	377	rv = -EINVAL;
381		− goto err_out;
	378	+ goto err_out_xa;
382	379	}
383	380	if (num_rqe)
384	381	num_rqe = roundup_pow_of_two(num_rqe);
@@ -401,8 +398,8 @@ struct ib_qp siw_create_qp(struct ib_pd pd, · 16 unmodified lines
401	398	}
402	399	}
403	400	qp->pd = pd;
404		− qp->scq = scq;
405		− qp->rcq = rcq;
	401	+ qp->scq = to_siw_cq(attrs->send_cq);
	402	+ qp->rcq = to_siw_cq(attrs->recv_cq);
406	403
407	404	if (attrs->srq) {
408	405	/*

drivers/infiniband/ulp/ipoib/ipoib_netlink.c+1−0

@@ -163,6 +163,7 @@ static size_t ipoib_get_size(const struct net_device *dev) · 162 unmodified lines
163	163
164	164	static struct rtnl_link_ops ipoib_link_ops __read_mostly = {
165	165	.kind = "ipoib",
	166	+ .netns_refund = true,
166	167	.maxtype = IFLA_IPOIB_MAX,
167	168	.policy = ipoib_policy,
168	169	.priv_size = sizeof(struct ipoib_dev_priv),

drivers/interconnect/qcom/bcm-voter.c+3−1

@@ -1,6 +1,6 @@
1	1	// SPDX-License-Identifier: GPL-2.0
2	2	/*
3		− * Copyright (c) 2020, The Linux Foundation. All rights reserved.
	3	+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
4	4	*/
5	5
6	6	#include <asm/div64.h>
@@ -205,6 +205,7 @@ struct bcm_voter of_bcm_voter_get(struct device dev, const char *name) · 198 unmodified lines
205	205	}
206	206	mutex_unlock(&bcm_voter_lock);
207	207
	208	+ of_node_put(node);
208	209	return voter;
209	210	}
210	211	EXPORT_SYMBOL_GPL(of_bcm_voter_get);
@@ -362,6 +363,7 @@ static const struct of_device_id bcm_voter_of_match[] = { · 151 unmodified lines
362	363	{ .compatible = "qcom,bcm-voter" },
363	364	{ }
364	365	};
	366	+MODULE_DEVICE_TABLE(of, bcm_voter_of_match);
365	367
366	368	static struct platform_driver qcom_icc_bcm_voter_driver = {
367	369	.probe = qcom_icc_bcm_voter_probe,

drivers/iommu/amd/iommu.c+3−1

@@ -884,7 +884,7 @@ static inline u64 build_inv_address(u64 address, size_t size) · 883 unmodified lines
884	884	* The msb-bit must be clear on the address. Just set all the
885	885	* lower bits.
886	886	*/
887		− address \|= 1ull << (msb_diff - 1);
	887	+ address \|= (1ull << msb_diff) - 1;
888	888	}
889	889
890	890	/* Clear bits 11:0 */
@@ -1714,6 +1714,8 @@ static void amd_iommu_probe_finalize(struct device *dev) · 823 unmodified lines
1714	1714	domain = iommu_get_domain_for_dev(dev);
1715	1715	if (domain->type == IOMMU_DOMAIN_DMA)
1716	1716	iommu_setup_dma_ops(dev, IOVA_START_PFN << PAGE_SHIFT, 0);
	1717	+ else
	1718	+ set_dma_ops(dev, NULL);
1717	1719	}
1718	1720
1719	1721	static void amd_iommu_release_device(struct device *dev)

drivers/iommu/intel/dmar.c+3−1

@@ -1142,7 +1142,7 @@ static int alloc_iommu(struct dmar_drhd_unit *drhd) · 1141 unmodified lines
1142	1142
1143	1143	err = iommu_device_register(&iommu->iommu, &intel_iommu_ops, NULL);
1144	1144	if (err)
1145		− goto err_unmap;
	1145	+ goto err_sysfs;
1146	1146	}
1147	1147
1148	1148	drhd->iommu = iommu;
@@ -1150,6 +1150,8 @@ static int alloc_iommu(struct dmar_drhd_unit *drhd) · 1 unmodified line
1150	1150
1151	1151	return 0;
1152	1152
	1153	+err_sysfs:
	1154	+ iommu_device_sysfs_remove(&iommu->iommu);
1153	1155	err_unmap:
1154	1156	unmap_iommu(iommu);
1155	1157	error_free_seq_id:

drivers/iommu/intel/iommu.c+7−2

@@ -2525,9 +2525,9 @@ static int domain_setup_first_level(struct intel_iommu *iommu, · 2524 unmodified lines
2525	2525	struct device *dev,
2526	2526	u32 pasid)
2527	2527	{
2528		− int flags = PASID_FLAG_SUPERVISOR_MODE;
2529	2528	struct dma_pte *pgd = domain->pgd;
2530	2529	int agaw, level;
	2530	+ int flags = 0;
2531	2531
2532	2532	/*
2533	2533	* Skip top levels of page tables for iommu which has
@@ -2543,7 +2543,10 @@ static int domain_setup_first_level(struct intel_iommu *iommu, · 9 unmodified lines
2543	2543	if (level != 4 && level != 5)
2544	2544	return -EINVAL;
2545	2545
2546		− flags \|= (level == 5) ? PASID_FLAG_FL5LP : 0;
	2546	+ if (pasid != PASID_RID2PASID)
	2547	+ flags \|= PASID_FLAG_SUPERVISOR_MODE;
	2548	+ if (level == 5)
	2549	+ flags \|= PASID_FLAG_FL5LP;
2547	2550
2548	2551	if (domain->domain.type == IOMMU_DOMAIN_UNMANAGED)
2549	2552	flags \|= PASID_FLAG_PAGE_SNOOP;
@@ -4606,6 +4609,8 @@ static int auxiliary_link_device(struct dmar_domain *domain, · 2056 unmodified lines
4606	4609
4607	4610	if (!sinfo) {
4608	4611	sinfo = kzalloc(sizeof(*sinfo), GFP_ATOMIC);
	4612	+ if (!sinfo)
	4613	+ return -ENOMEM;
4609	4614	sinfo->domain = domain;
4610	4615	sinfo->pdev = dev;
4611	4616	list_add(&sinfo->link_phys, &info->subdevices);

drivers/iommu/intel/pasid.c+2−1

@@ -699,7 +699,8 @@ int intel_pasid_setup_second_level(struct intel_iommu *iommu, · 698 unmodified lines
699	699	* Since it is a second level only translation setup, we should
700	700	* set SRE bit as well (addresses are expected to be GPAs).
701	701	*/
702		− pasid_set_sre(pte);
	702	+ if (pasid != PASID_RID2PASID)
	703	+ pasid_set_sre(pte);
703	704	pasid_set_present(pte);
704	705	pasid_flush_caches(iommu, pte, pasid, did);
705	706

drivers/iommu/virtio-iommu.c+1−0

@@ -1136,6 +1136,7 @@ static struct virtio_device_id id_table[] = { · 1135 unmodified lines
1136	1136	{ VIRTIO_ID_IOMMU, VIRTIO_DEV_ANY_ID },
1137	1137	{ 0 },
1138	1138	};
	1139	+MODULE_DEVICE_TABLE(virtio, id_table);
1139	1140
1140	1141	static struct virtio_driver virtio_iommu_drv = {
1141	1142	.driver.name = KBUILD_MODNAME,

drivers/irqchip/Kconfig+1−1

@@ -596,7 +596,7 @@ config IRQ_IDT3243X · 595 unmodified lines
596	596	config APPLE_AIC
597	597	bool "Apple Interrupt Controller (AIC)"
598	598	depends on ARM64
599		− default ARCH_APPLE
	599	+ depends on ARCH_APPLE \|\| COMPILE_TEST
600	600	help
601	601	Support for the Apple Interrupt Controller found on Apple Silicon SoCs,
602	602	such as the M1.

drivers/irqchip/irq-gic-v3.c+35−1

@@ -642,11 +642,45 @@ static inline void gic_handle_nmi(u32 irqnr, struct pt_regs *regs) · 641 unmodified lines
642	642	nmi_exit();
643	643	}
644	644
	645	+static u32 do_read_iar(struct pt_regs *regs)
	646	+{
	647	+ u32 iar;
	648	+
	649	+ if (gic_supports_nmi() && unlikely(!interrupts_enabled(regs))) {
	650	+ u64 pmr;
	651	+
	652	+ /*
	653	+ * We were in a context with IRQs disabled. However, the
	654	+ * entry code has set PMR to a value that allows any
	655	+ * interrupt to be acknowledged, and not just NMIs. This can
	656	+ * lead to surprising effects if the NMI has been retired in
	657	+ * the meantime, and that there is an IRQ pending. The IRQ
	658	+ * would then be taken in NMI context, something that nobody
	659	+ * wants to debug twice.
	660	+ *
	661	+ * Until we sort this, drop PMR again to a level that will
	662	+ * actually only allow NMIs before reading IAR, and then
	663	+ * restore it to what it was.
	664	+ */
	665	+ pmr = gic_read_pmr();
	666	+ gic_pmr_mask_irqs();
	667	+ isb();
	668	+
	669	+ iar = gic_read_iar();
	670	+
	671	+ gic_write_pmr(pmr);
	672	+ } else {
	673	+ iar = gic_read_iar();
	674	+ }
	675	+
	676	+ return iar;
	677	+}
	678	+
645	679	static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
646	680	{
647	681	u32 irqnr;
648	682
649		− irqnr = gic_read_iar();
	683	+ irqnr = do_read_iar(regs);
650	684
651	685	/* Check for special IDs first */
652	686	if ((irqnr >= 1020 && irqnr <= 1023))

drivers/irqchip/irq-mvebu-icu.c+1−3

@@ -359,10 +359,8 @@ static int mvebu_icu_probe(struct platform_device *pdev) · 358 unmodified lines
359	359
360	360	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
361	361	icu->base = devm_ioremap_resource(&pdev->dev, res);
362		− if (IS_ERR(icu->base)) {
363		− dev_err(&pdev->dev, "Failed to map icu base address.\n");
	362	+ if (IS_ERR(icu->base))
364	363	return PTR_ERR(icu->base);
365		− }
366	364
367	365	/*
368	366	* Legacy bindings: ICU is one node with one MSI parent: force manually

drivers/irqchip/irq-mvebu-sei.c+1−3

@@ -384,10 +384,8 @@ static int mvebu_sei_probe(struct platform_device *pdev) · 383 unmodified lines
384	384
385	385	sei->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
386	386	sei->base = devm_ioremap_resource(sei->dev, sei->res);
387		− if (IS_ERR(sei->base)) {
388		− dev_err(sei->dev, "Failed to remap SEI resource\n");
	387	+ if (IS_ERR(sei->base))
389	388	return PTR_ERR(sei->base);
390		− }
391	389
392	390	/* Retrieve the SEI capabilities with the interrupt ranges */
393	391	sei->caps = of_device_get_match_data(&pdev->dev);

drivers/irqchip/irq-stm32-exti.c+1−3

@@ -892,10 +892,8 @@ static int stm32_exti_probe(struct platform_device *pdev) · 891 unmodified lines
892	892
893	893	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
894	894	host_data->base = devm_ioremap_resource(dev, res);
895		− if (IS_ERR(host_data->base)) {
896		− dev_err(dev, "Unable to map registers\n");
	895	+ if (IS_ERR(host_data->base))
897	896	return PTR_ERR(host_data->base);
898		− }
899	897
900	898	for (i = 0; i < drv_data->bank_nr; i++)
901	899	stm32_exti_chip_init(host_data, i, np);

drivers/isdn/hardware/mISDN/hfcsusb.c+8−9

@@ -46,7 +46,7 @@ static void hfcsusb_start_endpoint(struct hfcsusb *hw, int channel); · 45 unmodified lines
46	46	static void hfcsusb_stop_endpoint(struct hfcsusb *hw, int channel);
47	47	static int hfcsusb_setup_bch(struct bchannel *bch, int protocol);
48	48	static void deactivate_bchannel(struct bchannel *bch);
49		−static void hfcsusb_ph_info(struct hfcsusb *hw);
	49	+static int hfcsusb_ph_info(struct hfcsusb *hw);
50	50
51	51	/* start next background transfer for control channel */
52	52	static void
@@ -241,7 +241,7 @@ hfcusb_l2l1B(struct mISDNchannel ch, struct sk_buff skb) · 188 unmodified lines
241	241	* send full D/B channel status information
242	242	* as MPH_INFORMATION_IND
243	243	*/
244		−static void
	244	+static int
245	245	hfcsusb_ph_info(struct hfcsusb *hw)
246	246	{
247	247	struct ph_info *phi;
@@ -250,7 +250,7 @@ hfcsusb_ph_info(struct hfcsusb *hw) · 2 unmodified lines
250	250
251	251	phi = kzalloc(struct_size(phi, bch, dch->dev.nrbchan), GFP_ATOMIC);
252	252	if (!phi)
253		− return;
	253	+ return -ENOMEM;
254	254
255	255	phi->dch.ch.protocol = hw->protocol;
256	256	phi->dch.ch.Flags = dch->Flags;
@@ -263,6 +263,8 @@ hfcsusb_ph_info(struct hfcsusb *hw) · 6 unmodified lines
263	263	_queue_data(&dch->dev.D, MPH_INFORMATION_IND, MISDN_ID_ANY,
264	264	struct_size(phi, bch, dch->dev.nrbchan), phi, GFP_ATOMIC);
265	265	kfree(phi);
	266	+
	267	+ return 0;
266	268	}
267	269
268	270	/*
@@ -347,8 +349,7 @@ hfcusb_l2l1D(struct mISDNchannel ch, struct sk_buff skb) · 78 unmodified lines
347	349	ret = l1_event(dch->l1, hh->prim);
348	350	break;
349	351	case MPH_INFORMATION_REQ:
350		− hfcsusb_ph_info(hw);
351		− ret = 0;
	352	+ ret = hfcsusb_ph_info(hw);
352	353	break;
353	354	}
354	355
@@ -403,8 +404,7 @@ hfc_l1callback(struct dchannel *dch, u_int cmd) · 48 unmodified lines
403	404	hw->name, __func__, cmd);
404	405	return -1;
405	406	}
406		− hfcsusb_ph_info(hw);
407		− return 0;
	407	+ return hfcsusb_ph_info(hw);
408	408	}
409	409
410	410	static int
@@ -746,8 +746,7 @@ hfcsusb_setup_bch(struct bchannel *bch, int protocol) · 335 unmodified lines
746	746	handle_led(hw, (bch->nr == 1) ? LED_B1_OFF :
747	747	LED_B2_OFF);
748	748	}
749		− hfcsusb_ph_info(hw);
750		− return 0;
	749	+ return hfcsusb_ph_info(hw);
751	750	}
752	751
753	752	static void

drivers/isdn/hardware/mISDN/mISDNinfineon.c+13−8

@@ -630,17 +630,19 @@ static void · 629 unmodified lines
630	630	release_io(struct inf_hw *hw)
631	631	{
632	632	if (hw->cfg.mode) {
633		− if (hw->cfg.p) {
	633	+ if (hw->cfg.mode == AM_MEMIO) {
634	634	release_mem_region(hw->cfg.start, hw->cfg.size);
635		− iounmap(hw->cfg.p);
	635	+ if (hw->cfg.p)
	636	+ iounmap(hw->cfg.p);
636	637	} else
637	638	release_region(hw->cfg.start, hw->cfg.size);
638	639	hw->cfg.mode = AM_NONE;
639	640	}
640	641	if (hw->addr.mode) {
641		− if (hw->addr.p) {
	642	+ if (hw->addr.mode == AM_MEMIO) {
642	643	release_mem_region(hw->addr.start, hw->addr.size);
643		− iounmap(hw->addr.p);
	644	+ if (hw->addr.p)
	645	+ iounmap(hw->addr.p);
644	646	} else
645	647	release_region(hw->addr.start, hw->addr.size);
646	648	hw->addr.mode = AM_NONE;
@@ -670,9 +672,12 @@ setup_io(struct inf_hw *hw) · 23 unmodified lines
670	672	(ulong)hw->cfg.start, (ulong)hw->cfg.size);
671	673	return err;
672	674	}
673		− if (hw->ci->cfg_mode == AM_MEMIO)
674		− hw->cfg.p = ioremap(hw->cfg.start, hw->cfg.size);
675	675	hw->cfg.mode = hw->ci->cfg_mode;
	676	+ if (hw->ci->cfg_mode == AM_MEMIO) {
	677	+ hw->cfg.p = ioremap(hw->cfg.start, hw->cfg.size);
	678	+ if (!hw->cfg.p)
	679	+ return -ENOMEM;
	680	+ }
676	681	if (debug & DEBUG_HW)
677	682	pr_notice("%s: IO cfg %lx (%lu bytes) mode%d\n",
678	683	hw->name, (ulong)hw->cfg.start,
@@ -697,12 +702,12 @@ setup_io(struct inf_hw *hw) · 18 unmodified lines
697	702	(ulong)hw->addr.start, (ulong)hw->addr.size);
698	703	return err;
699	704	}
	705	+ hw->addr.mode = hw->ci->addr_mode;
700	706	if (hw->ci->addr_mode == AM_MEMIO) {
701	707	hw->addr.p = ioremap(hw->addr.start, hw->addr.size);
702		− if (unlikely(!hw->addr.p))
	708	+ if (!hw->addr.p)
703	709	return -ENOMEM;
704	710	}
705		− hw->addr.mode = hw->ci->addr_mode;
706	711	if (debug & DEBUG_HW)
707	712	pr_notice("%s: IO addr %lx (%lu bytes) mode%d\n",
708	713	hw->name, (ulong)hw->addr.start,

drivers/isdn/hardware/mISDN/netjet.c+0−1

@@ -1100,7 +1100,6 @@ nj_probe(struct pci_dev pdev, const struct pci_device_id ent) · 1099 unmodified lines
1100	1100	card->typ = NETJET_S_TJ300;
1101	1101
1102	1102	card->base = pci_resource_start(pdev, 0);
1103		− card->irq = pdev->irq;
1104	1103	pci_set_drvdata(pdev, card);
1105	1104	err = setup_instance(card);
1106	1105	if (err)

drivers/leds/leds-lp5523.c+1−1

@@ -307,7 +307,7 @@ static int lp5523_init_program_engine(struct lp55xx_chip *chip) · 306 unmodified lines
307	307	usleep_range(3000, 6000);
308	308	ret = lp55xx_read(chip, LP5523_REG_STATUS, &status);
309	309	if (ret)
310		− return ret;
	310	+ goto out;
311	311	status &= LP5523_ENG_STATUS_MASK;
312	312
313	313	if (status != LP5523_ENG_STATUS_MASK) {

drivers/md/bcache/bcache.h+0−1

@@ -364,7 +364,6 @@ struct cached_dev { · 363 unmodified lines
364	364
365	365	/* The rest of this all shows up in sysfs */
366	366	unsigned int sequential_cutoff;
367		− unsigned int readahead;
368	367
369	368	unsigned int io_disable:1;
370	369	unsigned int verify:1;

drivers/md/bcache/request.c+7−13

@@ -880,9 +880,9 @@ static int cached_dev_cache_miss(struct btree b, struct search s, · 879 unmodified lines
880	880	struct bio *bio, unsigned int sectors)
881	881	{
882	882	int ret = MAP_CONTINUE;
883		− unsigned int reada = 0;
884	883	struct cached_dev *dc = container_of(s->d, struct cached_dev, disk);
885	884	struct bio miss, cache_bio;
	885	+ unsigned int size_limit;
886	886
887	887	s->cache_missed = 1;
888	888
@@ -892,14 +892,10 @@ static int cached_dev_cache_miss(struct btree b, struct search s, · 3 unmodified lines
892	892	goto out_submit;
893	893	}
894	894
895		− if (!(bio->bi_opf & REQ_RAHEAD) &&
896		− !(bio->bi_opf & (REQ_META\|REQ_PRIO)) &&
897		− s->iop.c->gc_stats.in_use < CUTOFF_CACHE_READA)
898		− reada = min_t(sector_t, dc->readahead >> 9,
899		− get_capacity(bio->bi_bdev->bd_disk) -
900		− bio_end_sector(bio));
901		−
902		− s->insert_bio_sectors = min(sectors, bio_sectors(bio) + reada);
	895	+ /* Limitation for valid replace key size and cache_bio bvecs number */
	896	+ size_limit = min_t(unsigned int, BIO_MAX_VECS * PAGE_SECTORS,
	897	+ (1 << KEY_SIZE_BITS) - 1);
	898	+ s->insert_bio_sectors = min3(size_limit, sectors, bio_sectors(bio));
903	899
904	900	s->iop.replace_key = KEY(s->iop.inode,
905	901	bio->bi_iter.bi_sector + s->insert_bio_sectors,
@@ -911,7 +907,8 @@ static int cached_dev_cache_miss(struct btree b, struct search s, · 5 unmodified lines
911	907
912	908	s->iop.replace = true;
913	909
914		− miss = bio_next_split(bio, sectors, GFP_NOIO, &s->d->bio_split);
	910	+ miss = bio_next_split(bio, s->insert_bio_sectors, GFP_NOIO,
	911	+ &s->d->bio_split);
915	912
916	913	/* btree_search_recurse()'s btree iterator is no good anymore */
917	914	ret = miss == bio ? MAP_DONE : -EINTR;
@@ -933,9 +930,6 @@ static int cached_dev_cache_miss(struct btree b, struct search s, · 15 unmodified lines
933	930	if (bch_bio_alloc_pages(cache_bio, __GFP_NOWARN\|GFP_NOIO))
934	931	goto out_put;
935	932
936		− if (reada)
937		− bch_mark_cache_readahead(s->iop.c, s->d);
938		−
939	933	s->cache_miss = miss;
940	934	s->iop.bio = cache_bio;
941	935	bio_get(cache_bio);

drivers/md/bcache/stats.c+0−14

@@ -46,7 +46,6 @@ read_attribute(cache_misses); · 45 unmodified lines
46	46	read_attribute(cache_bypass_hits);
47	47	read_attribute(cache_bypass_misses);
48	48	read_attribute(cache_hit_ratio);
49		−read_attribute(cache_readaheads);
50	49	read_attribute(cache_miss_collisions);
51	50	read_attribute(bypassed);
52	51
@@ -64,7 +63,6 @@ SHOW(bch_stats) · 11 unmodified lines
64	63	DIV_SAFE(var(cache_hits) * 100,
65	64	var(cache_hits) + var(cache_misses)));
66	65
67		− var_print(cache_readaheads);
68	66	var_print(cache_miss_collisions);
69	67	sysfs_hprint(bypassed, var(sectors_bypassed) << 9);
70	68	#undef var
@@ -86,7 +84,6 @@ static struct attribute *bch_stats_files[] = { · 15 unmodified lines
86	84	&sysfs_cache_bypass_hits,
87	85	&sysfs_cache_bypass_misses,
88	86	&sysfs_cache_hit_ratio,
89		− &sysfs_cache_readaheads,
90	87	&sysfs_cache_miss_collisions,
91	88	&sysfs_bypassed,
92	89	NULL
@@ -113,7 +110,6 @@ void bch_cache_accounting_clear(struct cache_accounting *acc) · 20 unmodified lines
113	110	acc->total.cache_misses = 0;
114	111	acc->total.cache_bypass_hits = 0;
115	112	acc->total.cache_bypass_misses = 0;
116		− acc->total.cache_readaheads = 0;
117	113	acc->total.cache_miss_collisions = 0;
118	114	acc->total.sectors_bypassed = 0;
119	115	}
@@ -145,7 +141,6 @@ static void scale_stats(struct cache_stats *stats, unsigned long rescale_at) · 25 unmodified lines
145	141	scale_stat(&stats->cache_misses);
146	142	scale_stat(&stats->cache_bypass_hits);
147	143	scale_stat(&stats->cache_bypass_misses);
148		− scale_stat(&stats->cache_readaheads);
149	144	scale_stat(&stats->cache_miss_collisions);
150	145	scale_stat(&stats->sectors_bypassed);
151	146	}
@@ -168,7 +163,6 @@ static void scale_accounting(struct timer_list *t) · 16 unmodified lines
168	163	move_stat(cache_misses);
169	164	move_stat(cache_bypass_hits);
170	165	move_stat(cache_bypass_misses);
171		− move_stat(cache_readaheads);
172	166	move_stat(cache_miss_collisions);
173	167	move_stat(sectors_bypassed);
174	168
@@ -209,14 +203,6 @@ void bch_mark_cache_accounting(struct cache_set c, struct bcache_device d, · 34 unmodified lines
209	203	mark_cache_stats(&c->accounting.collector, hit, bypass);
210	204	}
211	205
212		−void bch_mark_cache_readahead(struct cache_set c, struct bcache_device d)
213		−{
214		− struct cached_dev *dc = container_of(d, struct cached_dev, disk);
215		−
216		− atomic_inc(&dc->accounting.collector.cache_readaheads);
217		− atomic_inc(&c->accounting.collector.cache_readaheads);
218		−}
219		−
220	206	void bch_mark_cache_miss_collision(struct cache_set c, struct bcache_device d)
221	207	{
222	208	struct cached_dev *dc = container_of(d, struct cached_dev, disk);

drivers/md/bcache/stats.h+0−1

@@ -7,7 +7,6 @@ struct cache_stat_collector { · 6 unmodified lines
7	7	atomic_t cache_misses;
8	8	atomic_t cache_bypass_hits;
9	9	atomic_t cache_bypass_misses;
10		− atomic_t cache_readaheads;
11	10	atomic_t cache_miss_collisions;
12	11	atomic_t sectors_bypassed;
13	12	};

drivers/md/bcache/sysfs.c+0−4

@@ -137,7 +137,6 @@ rw_attribute(io_disable); · 136 unmodified lines
137	137	rw_attribute(discard);
138	138	rw_attribute(running);
139	139	rw_attribute(label);
140		−rw_attribute(readahead);
141	140	rw_attribute(errors);
142	141	rw_attribute(io_error_limit);
143	142	rw_attribute(io_error_halflife);
@@ -260,7 +259,6 @@ SHOW(__bch_cached_dev) · 116 unmodified lines
260	259	var_printf(partial_stripes_expensive, "%u");
261	260
262	261	var_hprint(sequential_cutoff);
263		− var_hprint(readahead);
264	262
265	263	sysfs_print(running, atomic_read(&dc->running));
266	264	sysfs_print(state, states[BDEV_STATE(&dc->sb)]);
@@ -365,7 +363,6 @@ STORE(__cached_dev) · 98 unmodified lines
365	363	sysfs_strtoul_clamp(sequential_cutoff,
366	364	dc->sequential_cutoff,
367	365	0, UINT_MAX);
368		− d_strtoi_h(readahead);
369	366
370	367	if (attr == &sysfs_clear_stats)
371	368	bch_cache_accounting_clear(&dc->accounting);
@@ -538,7 +535,6 @@ static struct attribute *bch_cached_dev_files[] = { · 166 unmodified lines
538	535	&sysfs_running,
539	536	&sysfs_state,
540	537	&sysfs_label,
541		− &sysfs_readahead,
542	538	#ifdef CONFIG_BCACHE_DEBUG
543	539	&sysfs_verify,
544	540	&sysfs_bypass_torture_test,

drivers/md/dm-integrity.c+36−45

@@ -66,14 +66,14 @@ struct superblock { · 65 unmodified lines
66	66	__u8 magic[8];
67	67	__u8 version;
68	68	__u8 log2_interleave_sectors;
69		− __u16 integrity_tag_size;
70		− __u32 journal_sections;
71		− __u64 provided_data_sectors; /* userspace uses this value */
72		− __u32 flags;
	69	+ __le16 integrity_tag_size;
	70	+ __le32 journal_sections;
	71	+ __le64 provided_data_sectors; /* userspace uses this value */
	72	+ __le32 flags;
73	73	__u8 log2_sectors_per_block;
74	74	__u8 log2_blocks_per_bitmap_bit;
75	75	__u8 pad[2];
76		− __u64 recalc_sector;
	76	+ __le64 recalc_sector;
77	77	__u8 pad2[8];
78	78	__u8 salt[SALT_SIZE];
79	79	};
@@ -86,16 +86,16 @@ struct superblock { · 6 unmodified lines
86	86
87	87	#define JOURNAL_ENTRY_ROUNDUP 8
88	88
89		−typedef __u64 commit_id_t;
	89	+typedef __le64 commit_id_t;
90	90	#define JOURNAL_MAC_PER_SECTOR 8
91	91
92	92	struct journal_entry {
93	93	union {
94	94	struct {
95		− __u32 sector_lo;
96		− __u32 sector_hi;
	95	+ __le32 sector_lo;
	96	+ __le32 sector_hi;
97	97	} s;
98		− __u64 sector;
	98	+ __le64 sector;
99	99	} u;
100	100	commit_id_t last_bytes[];
101	101	/* __u8 tag[0]; */
@@ -806,7 +806,7 @@ static void section_mac(struct dm_integrity_c *ic, unsigned section, __u8 result · 704 unmodified lines
806	806	}
807	807
808	808	if (ic->sb->flags & cpu_to_le32(SB_FLAG_FIXED_HMAC)) {
809		− uint64_t section_le;
	809	+ __le64 section_le;
810	810
811	811	r = crypto_shash_update(desc, (__u8 *)&ic->sb->salt, SALT_SIZE);
812	812	if (unlikely(r < 0)) {
@@ -1640,7 +1640,7 @@ static void integrity_end_io(struct bio *bio) · 827 unmodified lines
1640	1640	static void integrity_sector_checksum(struct dm_integrity_c *ic, sector_t sector,
1641	1641	const char data, char result)
1642	1642	{
1643		− __u64 sector_le = cpu_to_le64(sector);
	1643	+ __le64 sector_le = cpu_to_le64(sector);
1644	1644	SHASH_DESC_ON_STACK(req, ic->internal_hash);
1645	1645	int r;
1646	1646	unsigned digest_size;
@@ -2689,30 +2689,26 @@ next_chunk: · 1042 unmodified lines
2689	2689	if (unlikely(dm_integrity_failed(ic)))
2690	2690	goto err;
2691	2691
2692		− if (!ic->discard) {
2693		− io_req.bi_op = REQ_OP_READ;
2694		− io_req.bi_op_flags = 0;
2695		− io_req.mem.type = DM_IO_VMA;
2696		− io_req.mem.ptr.addr = ic->recalc_buffer;
2697		− io_req.notify.fn = NULL;
2698		− io_req.client = ic->io;
2699		− io_loc.bdev = ic->dev->bdev;
2700		− io_loc.sector = get_data_sector(ic, area, offset);
2701		− io_loc.count = n_sectors;
	2692	+ io_req.bi_op = REQ_OP_READ;
	2693	+ io_req.bi_op_flags = 0;
	2694	+ io_req.mem.type = DM_IO_VMA;
	2695	+ io_req.mem.ptr.addr = ic->recalc_buffer;
	2696	+ io_req.notify.fn = NULL;
	2697	+ io_req.client = ic->io;
	2698	+ io_loc.bdev = ic->dev->bdev;
	2699	+ io_loc.sector = get_data_sector(ic, area, offset);
	2700	+ io_loc.count = n_sectors;
2702	2701
2703		− r = dm_io(&io_req, 1, &io_loc, NULL);
2704		− if (unlikely(r)) {
2705		− dm_integrity_io_error(ic, "reading data", r);
2706		− goto err;
2707		− }
	2702	+ r = dm_io(&io_req, 1, &io_loc, NULL);
	2703	+ if (unlikely(r)) {
	2704	+ dm_integrity_io_error(ic, "reading data", r);
	2705	+ goto err;
	2706	+ }
2708	2707
2709		− t = ic->recalc_tags;
2710		− for (i = 0; i < n_sectors; i += ic->sectors_per_block) {
2711		− integrity_sector_checksum(ic, logical_sector + i, ic->recalc_buffer + (i << SECTOR_SHIFT), t);
2712		− t += ic->tag_size;
2713		− }
2714		− } else {
2715		− t = ic->recalc_tags + (n_sectors >> ic->sb->log2_sectors_per_block) * ic->tag_size;
	2708	+ t = ic->recalc_tags;
	2709	+ for (i = 0; i < n_sectors; i += ic->sectors_per_block) {
	2710	+ integrity_sector_checksum(ic, logical_sector + i, ic->recalc_buffer + (i << SECTOR_SHIFT), t);
	2711	+ t += ic->tag_size;
2716	2712	}
2717	2713
2718	2714	metadata_block = get_metadata_sector_and_offset(ic, area, offset, &metadata_offset);
@@ -3826,7 +3822,7 @@ static int create_journal(struct dm_integrity_c ic, char *error) · 1107 unmodified lines
3826	3822	for (i = 0; i < ic->journal_sections; i++) {
3827	3823	struct scatterlist sg;
3828	3824	struct skcipher_request *section_req;
3829		− __u32 section_le = cpu_to_le32(i);
	3825	+ __le32 section_le = cpu_to_le32(i);
3830	3826
3831	3827	memset(crypt_iv, 0x00, ivsize);
3832	3828	memset(crypt_data, 0x00, crypt_len);
@@ -4368,13 +4364,11 @@ try_smaller_buffer: · 535 unmodified lines
4368	4364	goto bad;
4369	4365	}
4370	4366	INIT_WORK(&ic->recalc_work, integrity_recalc);
4371		− if (!ic->discard) {
4372		− ic->recalc_buffer = vmalloc(RECALC_SECTORS << SECTOR_SHIFT);
4373		− if (!ic->recalc_buffer) {
4374		− ti->error = "Cannot allocate buffer for recalculating";
4375		− r = -ENOMEM;
4376		− goto bad;
4377		− }
	4367	+ ic->recalc_buffer = vmalloc(RECALC_SECTORS << SECTOR_SHIFT);
	4368	+ if (!ic->recalc_buffer) {
	4369	+ ti->error = "Cannot allocate buffer for recalculating";
	4370	+ r = -ENOMEM;
	4371	+ goto bad;
4378	4372	}
4379	4373	ic->recalc_tags = kvmalloc_array(RECALC_SECTORS >> ic->sb->log2_sectors_per_block,
4380	4374	ic->tag_size, GFP_KERNEL);
@@ -4383,9 +4377,6 @@ try_smaller_buffer: · 2 unmodified lines
4383	4377	r = -ENOMEM;
4384	4378	goto bad;
4385	4379	}
4386		− if (ic->discard)
4387		− memset(ic->recalc_tags, DISCARD_FILLER,
4388		− (RECALC_SECTORS >> ic->sb->log2_sectors_per_block) * ic->tag_size);
4389	4380	} else {
4390	4381	if (ic->sb->flags & cpu_to_le32(SB_FLAG_RECALCULATING)) {
4391	4382	ti->error = "Recalculate can only be specified with internal_hash";
@@ -4579,7 +4570,7 @@ static void dm_integrity_dtr(struct dm_target *ti) · 187 unmodified lines
4579	4570
4580	4571	static struct target_type integrity_target = {
4581	4572	.name = "integrity",
4582		− .version = {1, 9, 0},
	4573	+ .version = {1, 10, 0},
4583	4574	.module = THIS_MODULE,
4584	4575	.features = DM_TARGET_SINGLETON \| DM_TARGET_INTEGRITY,
4585	4576	.ctr = dm_integrity_ctr,

drivers/md/dm-snap.c+2−1

@@ -855,7 +855,7 @@ static int dm_add_exception(void *context, chunk_t old, chunk_t new) · 854 unmodified lines
855	855	static uint32_t __minimum_chunk_size(struct origin *o)
856	856	{
857	857	struct dm_snapshot *snap;
858		− unsigned chunk_size = 0;
	858	+ unsigned chunk_size = rounddown_pow_of_two(UINT_MAX);
859	859
860	860	if (o)
861	861	list_for_each_entry(snap, &o->snapshots, list)
@@ -1409,6 +1409,7 @@ static int snapshot_ctr(struct dm_target ti, unsigned int argc, char *argv) · 547 unmodified lines
1409	1409
1410	1410	if (!s->store->chunk_size) {
1411	1411	ti->error = "Chunk size not set";
	1412	+ r = -EINVAL;
1412	1413	goto bad_read_metadata;
1413	1414	}
1414	1415

drivers/md/dm-verity-verify-sig.c+1−1

@@ -15,7 +15,7 @@ · 14 unmodified lines
15	15	#define DM_VERITY_VERIFY_ERR(s) DM_VERITY_ROOT_HASH_VERIFICATION " " s
16	16
17	17	static bool require_signatures;
18		−module_param(require_signatures, bool, false);
	18	+module_param(require_signatures, bool, 0444);
19	19	MODULE_PARM_DESC(require_signatures,
20	20	"Verify the roothash of dm-verity hash tree");
21	21

drivers/md/raid5.c+0−2

@@ -5311,8 +5311,6 @@ static int in_chunk_boundary(struct mddev mddev, struct bio bio) · 5310 unmodified lines
5311	5311	unsigned int chunk_sectors;
5312	5312	unsigned int bio_sectors = bio_sectors(bio);
5313	5313
5314		− WARN_ON_ONCE(bio->bi_bdev->bd_partno);
5315		−
5316	5314	chunk_sectors = min(conf->chunk_sectors, conf->prev_chunk_sectors);
5317	5315	return chunk_sectors >=
5318	5316	((sector & (chunk_sectors - 1)) + bio_sectors);

drivers/media/dvb-frontends/sp8870.c+1−1

@@ -281,7 +281,7 @@ static int sp8870_set_frontend_parameters(struct dvb_frontend *fe) · 280 unmodified lines
281	281
282	282	// read status reg in order to clear pending irqs
283	283	err = sp8870_readreg(state, 0x200);
284		− if (err)
	284	+ if (err < 0)
285	285	return err;
286	286
287	287	// system controller start

drivers/media/platform/rcar_drif.c+0−1

@@ -915,7 +915,6 @@ static int rcar_drif_g_fmt_sdr_cap(struct file file, void priv, · 914 unmodified lines
915	915	{
916	916	struct rcar_drif_sdr *sdr = video_drvdata(file);
917	917
918		− memset(f->fmt.sdr.reserved, 0, sizeof(f->fmt.sdr.reserved));
919	918	f->fmt.sdr.pixelformat = sdr->fmt->pixelformat;
920	919	f->fmt.sdr.buffersize = sdr->fmt->buffersize;
921	920

drivers/media/usb/gspca/cpia1.c+1−5

@@ -1424,7 +1424,6 @@ static int sd_config(struct gspca_dev *gspca_dev, · 1423 unmodified lines
1424	1424	{
1425	1425	struct sd sd = (struct sd ) gspca_dev;
1426	1426	struct cam *cam;
1427		− int ret;
1428	1427
1429	1428	sd->mainsFreq = FREQ_DEF == V4L2_CID_POWER_LINE_FREQUENCY_60HZ;
1430	1429	reset_camera_params(gspca_dev);
@@ -1436,10 +1435,7 @@ static int sd_config(struct gspca_dev *gspca_dev, · 5 unmodified lines
1436	1435	cam->cam_mode = mode;
1437	1436	cam->nmodes = ARRAY_SIZE(mode);
1438	1437
1439		− ret = goto_low_power(gspca_dev);
1440		− if (ret)
1441		− gspca_err(gspca_dev, "Cannot go to low power mode: %d\n",
1442		− ret);
	1438	+ goto_low_power(gspca_dev);
1443	1439	/* Check the firmware version. */
1444	1440	sd->params.version.firmwareVersion = 0;
1445	1441	get_version_information(gspca_dev);

drivers/media/usb/gspca/m5602/m5602_mt9m111.c+8−8

@@ -195,7 +195,7 @@ static const struct v4l2_ctrl_config mt9m111_greenbal_cfg = { · 194 unmodified lines
195	195	int mt9m111_probe(struct sd *sd)
196	196	{
197	197	u8 data[2] = {0x00, 0x00};
198		− int i, rc = 0;
	198	+ int i, err;
199	199	struct gspca_dev gspca_dev = (struct gspca_dev )sd;
200	200
201	201	if (force_sensor) {
@@ -213,18 +213,18 @@ int mt9m111_probe(struct sd *sd) · 11 unmodified lines
213	213	/* Do the preinit */
214	214	for (i = 0; i < ARRAY_SIZE(preinit_mt9m111); i++) {
215	215	if (preinit_mt9m111[i][0] == BRIDGE) {
216		− rc \|= m5602_write_bridge(sd,
217		− preinit_mt9m111[i][1],
218		− preinit_mt9m111[i][2]);
	216	+ err = m5602_write_bridge(sd,
	217	+ preinit_mt9m111[i][1],
	218	+ preinit_mt9m111[i][2]);
219	219	} else {
220	220	data[0] = preinit_mt9m111[i][2];
221	221	data[1] = preinit_mt9m111[i][3];
222		− rc \|= m5602_write_sensor(sd,
223		− preinit_mt9m111[i][1], data, 2);
	222	+ err = m5602_write_sensor(sd,
	223	+ preinit_mt9m111[i][1], data, 2);
224	224	}
	225	+ if (err < 0)
	226	+ return err;
225	227	}
226		− if (rc < 0)
227		− return rc;
228	228
229	229	if (m5602_read_sensor(sd, MT9M111_SC_CHIPVER, data, 2))
230	230	return -ENODEV;

drivers/media/usb/gspca/m5602/m5602_po1030.c+7−7

@@ -154,8 +154,8 @@ static const struct v4l2_ctrl_config po1030_greenbal_cfg = { · 153 unmodified lines
154	154
155	155	int po1030_probe(struct sd *sd)
156	156	{
157		− int rc = 0;
158	157	u8 dev_id_h = 0, i;
	158	+ int err;
159	159	struct gspca_dev gspca_dev = (struct gspca_dev )sd;
160	160
161	161	if (force_sensor) {
@@ -174,14 +174,14 @@ int po1030_probe(struct sd *sd) · 12 unmodified lines
174	174	for (i = 0; i < ARRAY_SIZE(preinit_po1030); i++) {
175	175	u8 data = preinit_po1030[i][2];
176	176	if (preinit_po1030[i][0] == SENSOR)
177		− rc \|= m5602_write_sensor(sd,
178		− preinit_po1030[i][1], &data, 1);
	177	+ err = m5602_write_sensor(sd, preinit_po1030[i][1],
	178	+ &data, 1);
179	179	else
180		− rc \|= m5602_write_bridge(sd, preinit_po1030[i][1],
181		− data);
	180	+ err = m5602_write_bridge(sd, preinit_po1030[i][1],
	181	+ data);
	182	+ if (err < 0)
	183	+ return err;
182	184	}
183		− if (rc < 0)
184		− return rc;
185	185
186	186	if (m5602_read_sensor(sd, PO1030_DEVID_H, &dev_id_h, 1))
187	187	return -ENODEV;

drivers/misc/cardreader/rtl8411.c+1−0

@@ -468,6 +468,7 @@ static void rtl8411_init_common_params(struct rtsx_pcr *pcr) · 467 unmodified lines
468	468	pcr->sd30_drive_sel_1v8 = DRIVER_TYPE_B;
469	469	pcr->sd30_drive_sel_3v3 = DRIVER_TYPE_D;
470	470	pcr->aspm_en = ASPM_L1_EN;
	471	+ pcr->aspm_mode = ASPM_MODE_CFG;
471	472	pcr->tx_initial_phase = SET_CLOCK_PHASE(23, 7, 14);
472	473	pcr->rx_initial_phase = SET_CLOCK_PHASE(4, 3, 10);
473	474	pcr->ic_version = rtl8411_get_ic_version(pcr);

drivers/misc/cardreader/rts5209.c+1−0

@@ -255,6 +255,7 @@ void rts5209_init_params(struct rtsx_pcr *pcr) · 254 unmodified lines
255	255	pcr->sd30_drive_sel_1v8 = DRIVER_TYPE_B;
256	256	pcr->sd30_drive_sel_3v3 = DRIVER_TYPE_D;
257	257	pcr->aspm_en = ASPM_L1_EN;
	258	+ pcr->aspm_mode = ASPM_MODE_CFG;
258	259	pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 16);
259	260	pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
260	261

drivers/misc/cardreader/rts5227.c+2−0

@@ -358,6 +358,7 @@ void rts5227_init_params(struct rtsx_pcr *pcr) · 357 unmodified lines
358	358	pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
359	359	pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
360	360	pcr->aspm_en = ASPM_L1_EN;
	361	+ pcr->aspm_mode = ASPM_MODE_CFG;
361	362	pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 15);
362	363	pcr->rx_initial_phase = SET_CLOCK_PHASE(30, 7, 7);
363	364
@@ -483,6 +484,7 @@ void rts522a_init_params(struct rtsx_pcr *pcr) · 119 unmodified lines
483	484
484	485	rts5227_init_params(pcr);
485	486	pcr->ops = &rts522a_pcr_ops;
	487	+ pcr->aspm_mode = ASPM_MODE_REG;
486	488	pcr->tx_initial_phase = SET_CLOCK_PHASE(20, 20, 11);
487	489	pcr->reg_pm_ctrl3 = RTS522A_PM_CTRL3;
488	490

drivers/misc/cardreader/rts5228.c+1−0

@@ -718,6 +718,7 @@ void rts5228_init_params(struct rtsx_pcr *pcr) · 717 unmodified lines
718	718	pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
719	719	pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
720	720	pcr->aspm_en = ASPM_L1_EN;
	721	+ pcr->aspm_mode = ASPM_MODE_REG;
721	722	pcr->tx_initial_phase = SET_CLOCK_PHASE(28, 27, 11);
722	723	pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
723	724

drivers/misc/cardreader/rts5229.c+1−0

@@ -246,6 +246,7 @@ void rts5229_init_params(struct rtsx_pcr *pcr) · 245 unmodified lines
246	246	pcr->sd30_drive_sel_1v8 = DRIVER_TYPE_B;
247	247	pcr->sd30_drive_sel_3v3 = DRIVER_TYPE_D;
248	248	pcr->aspm_en = ASPM_L1_EN;
	249	+ pcr->aspm_mode = ASPM_MODE_CFG;
249	250	pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 15);
250	251	pcr->rx_initial_phase = SET_CLOCK_PHASE(30, 6, 6);
251	252

drivers/misc/cardreader/rts5249.c+3−0

@@ -566,6 +566,7 @@ void rts5249_init_params(struct rtsx_pcr *pcr) · 565 unmodified lines
566	566	pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
567	567	pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
568	568	pcr->aspm_en = ASPM_L1_EN;
	569	+ pcr->aspm_mode = ASPM_MODE_CFG;
569	570	pcr->tx_initial_phase = SET_CLOCK_PHASE(1, 29, 16);
570	571	pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
571	572
@@ -729,6 +730,7 @@ static const struct pcr_ops rts524a_pcr_ops = { · 157 unmodified lines
729	730	void rts524a_init_params(struct rtsx_pcr *pcr)
730	731	{
731	732	rts5249_init_params(pcr);
	733	+ pcr->aspm_mode = ASPM_MODE_REG;
732	734	pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 29, 11);
733	735	pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF;
734	736	pcr->option.ltr_l1off_snooze_sspwrgate =
@@ -845,6 +847,7 @@ static const struct pcr_ops rts525a_pcr_ops = { · 110 unmodified lines
845	847	void rts525a_init_params(struct rtsx_pcr *pcr)
846	848	{
847	849	rts5249_init_params(pcr);
	850	+ pcr->aspm_mode = ASPM_MODE_REG;
848	851	pcr->tx_initial_phase = SET_CLOCK_PHASE(25, 29, 11);
849	852	pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF;
850	853	pcr->option.ltr_l1off_snooze_sspwrgate =

drivers/misc/cardreader/rts5260.c+1−0

@@ -628,6 +628,7 @@ void rts5260_init_params(struct rtsx_pcr *pcr) · 627 unmodified lines
628	628	pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
629	629	pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
630	630	pcr->aspm_en = ASPM_L1_EN;
	631	+ pcr->aspm_mode = ASPM_MODE_REG;
631	632	pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 29, 11);
632	633	pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
633	634

drivers/misc/cardreader/rts5261.c+1−0

@@ -783,6 +783,7 @@ void rts5261_init_params(struct rtsx_pcr *pcr) · 782 unmodified lines
783	783	pcr->sd30_drive_sel_1v8 = 0x00;
784	784	pcr->sd30_drive_sel_3v3 = 0x00;
785	785	pcr->aspm_en = ASPM_L1_EN;
	786	+ pcr->aspm_mode = ASPM_MODE_REG;
786	787	pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 11);
787	788	pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
788	789

drivers/misc/cardreader/rtsx_pcr.c+31−13

@@ -85,12 +85,18 @@ static void rtsx_comm_set_aspm(struct rtsx_pcr *pcr, bool enable) · 84 unmodified lines
85	85	if (pcr->aspm_enabled == enable)
86	86	return;
87	87
88		− if (pcr->aspm_en & 0x02)
89		− rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, FORCE_ASPM_CTL0 \|
90		− FORCE_ASPM_CTL1, enable ? 0 : FORCE_ASPM_CTL0 \| FORCE_ASPM_CTL1);
91		− else
92		− rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, FORCE_ASPM_CTL0 \|
93		− FORCE_ASPM_CTL1, FORCE_ASPM_CTL0 \| FORCE_ASPM_CTL1);
	88	+ if (pcr->aspm_mode == ASPM_MODE_CFG) {
	89	+ pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
	90	+ PCI_EXP_LNKCTL_ASPMC,
	91	+ enable ? pcr->aspm_en : 0);
	92	+ } else if (pcr->aspm_mode == ASPM_MODE_REG) {
	93	+ if (pcr->aspm_en & 0x02)
	94	+ rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, FORCE_ASPM_CTL0 \|
	95	+ FORCE_ASPM_CTL1, enable ? 0 : FORCE_ASPM_CTL0 \| FORCE_ASPM_CTL1);
	96	+ else
	97	+ rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, FORCE_ASPM_CTL0 \|
	98	+ FORCE_ASPM_CTL1, FORCE_ASPM_CTL0 \| FORCE_ASPM_CTL1);
	99	+ }
94	100
95	101	if (!enable && (pcr->aspm_en & 0x02))
96	102	mdelay(10);
@@ -1394,7 +1400,8 @@ static int rtsx_pci_init_hw(struct rtsx_pcr *pcr) · 1297 unmodified lines
1394	1400	return err;
1395	1401	}
1396	1402
1397		− rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0x30, 0x30);
	1403	+ if (pcr->aspm_mode == ASPM_MODE_REG)
	1404	+ rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0x30, 0x30);
1398	1405
1399	1406	/* No CD interrupt if probing driver with card inserted.
1400	1407	* So we need to initialize pcr->card_exist here.
@@ -1410,6 +1417,8 @@ static int rtsx_pci_init_hw(struct rtsx_pcr *pcr) · 9 unmodified lines
1410	1417	static int rtsx_pci_init_chip(struct rtsx_pcr *pcr)
1411	1418	{
1412	1419	int err;
	1420	+ u16 cfg_val;
	1421	+ u8 val;
1413	1422
1414	1423	spin_lock_init(&pcr->lock);
1415	1424	mutex_init(&pcr->pcr_mutex);
@@ -1477,6 +1486,21 @@ static int rtsx_pci_init_chip(struct rtsx_pcr *pcr) · 61 unmodified lines
1477	1486	if (!pcr->slots)
1478	1487	return -ENOMEM;
1479	1488
	1489	+ if (pcr->aspm_mode == ASPM_MODE_CFG) {
	1490	+ pcie_capability_read_word(pcr->pci, PCI_EXP_LNKCTL, &cfg_val);
	1491	+ if (cfg_val & PCI_EXP_LNKCTL_ASPM_L1)
	1492	+ pcr->aspm_enabled = true;
	1493	+ else
	1494	+ pcr->aspm_enabled = false;
	1495	+
	1496	+ } else if (pcr->aspm_mode == ASPM_MODE_REG) {
	1497	+ rtsx_pci_read_register(pcr, ASPM_FORCE_CTL, &val);
	1498	+ if (val & FORCE_ASPM_CTL0 && val & FORCE_ASPM_CTL1)
	1499	+ pcr->aspm_enabled = false;
	1500	+ else
	1501	+ pcr->aspm_enabled = true;
	1502	+ }
	1503	+
1480	1504	if (pcr->ops->fetch_vendor_settings)
1481	1505	pcr->ops->fetch_vendor_settings(pcr);
1482	1506
@@ -1506,7 +1530,6 @@ static int rtsx_pci_probe(struct pci_dev *pcidev, · 23 unmodified lines
1506	1530	struct pcr_handle *handle;
1507	1531	u32 base, len;
1508	1532	int ret, i, bar = 0;
1509		− u8 val;
1510	1533
1511	1534	dev_dbg(&(pcidev->dev),
1512	1535	": Realtek PCI-E Card Reader found at %s [%04x:%04x] (rev %x)\n",
@@ -1572,11 +1595,6 @@ static int rtsx_pci_probe(struct pci_dev *pcidev, · 59 unmodified lines
1572	1595	pcr->host_cmds_addr = pcr->rtsx_resv_buf_addr;
1573	1596	pcr->host_sg_tbl_ptr = pcr->rtsx_resv_buf + HOST_CMDS_BUF_LEN;
1574	1597	pcr->host_sg_tbl_addr = pcr->rtsx_resv_buf_addr + HOST_CMDS_BUF_LEN;
1575		− rtsx_pci_read_register(pcr, ASPM_FORCE_CTL, &val);
1576		− if (val & FORCE_ASPM_CTL0 && val & FORCE_ASPM_CTL1)
1577		− pcr->aspm_enabled = false;
1578		− else
1579		− pcr->aspm_enabled = true;
1580	1598	pcr->card_inserted = 0;
1581	1599	pcr->card_removed = 0;
1582	1600	INIT_DELAYED_WORK(&pcr->carddet_work, rtsx_pci_card_detect);

drivers/misc/eeprom/at24.c+4−2

@@ -763,7 +763,8 @@ static int at24_probe(struct i2c_client *client) · 762 unmodified lines
763	763	at24->nvmem = devm_nvmem_register(dev, &nvmem_config);
764	764	if (IS_ERR(at24->nvmem)) {
765	765	pm_runtime_disable(dev);
766		− regulator_disable(at24->vcc_reg);
	766	+ if (!pm_runtime_status_suspended(dev))
	767	+ regulator_disable(at24->vcc_reg);
767	768	return PTR_ERR(at24->nvmem);
768	769	}
769	770
@@ -774,7 +775,8 @@ static int at24_probe(struct i2c_client *client) · 4 unmodified lines
774	775	err = at24_read(at24, 0, &test_byte, 1);
775	776	if (err) {
776	777	pm_runtime_disable(dev);
777		− regulator_disable(at24->vcc_reg);
	778	+ if (!pm_runtime_status_suspended(dev))
	779	+ regulator_disable(at24->vcc_reg);
778	780	return -ENODEV;
779	781	}
780	782

drivers/misc/habanalabs/common/command_submission.c+1−1

@@ -2017,7 +2017,7 @@ wait_again: · 2016 unmodified lines
2017	2017	if (completion_value >= target_value) {
2018	2018	*status = CS_WAIT_STATUS_COMPLETED;
2019	2019	} else {
2020		− timeout -= jiffies_to_usecs(completion_rc);
	2020	+ timeout = completion_rc;
2021	2021	goto wait_again;
2022	2022	}
2023	2023	} else {

drivers/misc/habanalabs/common/firmware_if.c+31−22

@@ -362,12 +362,9 @@ static int fw_read_errors(struct hl_device *hdev, u32 boot_err0_reg, · 361 unmodified lines
362	362	}
363	363
364	364	if (err_val & CPU_BOOT_ERR0_SECURITY_NOT_RDY) {
365		− dev_warn(hdev->dev,
	365	+ dev_err(hdev->dev,
366	366	"Device boot warning - security not ready\n");
367		− /* This is a warning so we don't want it to disable the
368		− * device
369		− */
370		− err_val &= ~CPU_BOOT_ERR0_SECURITY_NOT_RDY;
	367	+ err_exists = true;
371	368	}
372	369
373	370	if (err_val & CPU_BOOT_ERR0_SECURITY_FAIL) {
@@ -403,7 +400,8 @@ static int fw_read_errors(struct hl_device *hdev, u32 boot_err0_reg, · 29 unmodified lines
403	400	err_exists = true;
404	401	}
405	402
406		− if (err_exists)
	403	+ if (err_exists && ((err_val & ~CPU_BOOT_ERR0_ENABLED) &
	404	+ lower_32_bits(hdev->boot_error_status_mask)))
407	405	return -EIO;
408	406
409	407	return 0;
@@ -661,18 +659,13 @@ int hl_fw_cpucp_total_energy_get(struct hl_device hdev, u64 total_energy) · 251 unmodified lines
661	659	return rc;
662	660	}
663	661
664		−int get_used_pll_index(struct hl_device *hdev, enum pll_index input_pll_index,
	662	+int get_used_pll_index(struct hl_device *hdev, u32 input_pll_index,
665	663	enum pll_index *pll_index)
666	664	{
667	665	struct asic_fixed_properties *prop = &hdev->asic_prop;
668	666	u8 pll_byte, pll_bit_off;
669	667	bool dynamic_pll;
670		−
671		− if (input_pll_index >= PLL_MAX) {
672		− dev_err(hdev->dev, "PLL index %d is out of range\n",
673		− input_pll_index);
674		− return -EINVAL;
675		− }
	668	+ int fw_pll_idx;
676	669
677	670	dynamic_pll = prop->fw_security_status_valid &&
678	671	(prop->fw_app_security_map & CPU_BOOT_DEV_STS0_DYN_PLL_EN);
@@ -680,28 +673,39 @@ int get_used_pll_index(struct hl_device *hdev, enum pll_index input_pll_index, · 1 unmodified line
680	673	if (!dynamic_pll) {
681	674	/*
682	675	* in case we are working with legacy FW (each asic has unique
683		− * PLL numbering) extract the legacy numbering
	676	+ * PLL numbering) use the driver based index as they are
	677	+ * aligned with fw legacy numbering
684	678	*/
685		− *pll_index = hdev->legacy_pll_map[input_pll_index];
	679	+ *pll_index = input_pll_index;
686	680	return 0;
687	681	}
688	682
	683	+ /* retrieve a FW compatible PLL index based on
	684	+ * ASIC specific user request
	685	+ */
	686	+ fw_pll_idx = hdev->asic_funcs->map_pll_idx_to_fw_idx(input_pll_index);
	687	+ if (fw_pll_idx < 0) {
	688	+ dev_err(hdev->dev, "Invalid PLL index (%u) error %d\n",
	689	+ input_pll_index, fw_pll_idx);
	690	+ return -EINVAL;
	691	+ }
	692	+
689	693	/* PLL map is a u8 array */
690		− pll_byte = prop->cpucp_info.pll_map[input_pll_index >> 3];
691		− pll_bit_off = input_pll_index & 0x7;
	694	+ pll_byte = prop->cpucp_info.pll_map[fw_pll_idx >> 3];
	695	+ pll_bit_off = fw_pll_idx & 0x7;
692	696
693	697	if (!(pll_byte & BIT(pll_bit_off))) {
694	698	dev_err(hdev->dev, "PLL index %d is not supported\n",
695		− input_pll_index);
	699	+ fw_pll_idx);
696	700	return -EINVAL;
697	701	}
698	702
699		− *pll_index = input_pll_index;
	703	+ *pll_index = fw_pll_idx;
700	704
701	705	return 0;
702	706	}
703	707
704		−int hl_fw_cpucp_pll_info_get(struct hl_device *hdev, enum pll_index pll_index,
	708	+int hl_fw_cpucp_pll_info_get(struct hl_device *hdev, u32 pll_index,
705	709	u16 *pll_freq_arr)
706	710	{
707	711	struct cpucp_packet pkt;
@@ -844,8 +848,13 @@ int hl_fw_read_preboot_status(struct hl_device *hdev, u32 cpu_boot_status_reg, · 136 unmodified lines
844	848	if (rc) {
845	849	dev_err(hdev->dev, "Failed to read preboot version\n");
846	850	detect_cpu_boot_status(hdev, status);
847		− fw_read_errors(hdev, boot_err0_reg,
848		− cpu_security_boot_status_reg);
	851	+
	852	+ /* If we read all FF, then something is totally wrong, no point
	853	+ * of reading specific errors
	854	+ */
	855	+ if (status != -1)
	856	+ fw_read_errors(hdev, boot_err0_reg,
	857	+ cpu_security_boot_status_reg);
849	858	return -EIO;
850	859	}
851	860

drivers/misc/habanalabs/common/habanalabs.h+15−8

@@ -930,6 +930,9 @@ enum div_select_defs { · 929 unmodified lines
930	930	* driver is ready to receive asynchronous events. This
931	931	* function should be called during the first init and
932	932	* after every hard-reset of the device
	933	+ * @get_msi_info: Retrieve asic-specific MSI ID of the f/w async event
	934	+ * @map_pll_idx_to_fw_idx: convert driver specific per asic PLL index to
	935	+ * generic f/w compatible PLL Indexes
933	936	*/
934	937	struct hl_asic_funcs {
935	938	int (early_init)(struct hl_device hdev);
@@ -1054,6 +1057,7 @@ struct hl_asic_funcs { · 118 unmodified lines
1054	1057	u32 block_id, u32 block_size);
1055	1058	void (enable_events_from_fw)(struct hl_device hdev);
1056	1059	void (get_msi_info)(u32 table);
	1060	+ int (*map_pll_idx_to_fw_idx)(u32 pll_idx);
1057	1061	};
1058	1062
1059	1063
@@ -1950,8 +1954,6 @@ struct hl_mmu_funcs { · 890 unmodified lines
1950	1954	* @aggregated_cs_counters: aggregated cs counters among all contexts
1951	1955	* @mmu_priv: device-specific MMU data.
1952	1956	* @mmu_func: device-related MMU functions.
1953		− * @legacy_pll_map: map holding map between dynamic (common) PLL indexes and
1954		− * static (asic specific) PLL indexes.
1955	1957	* @dram_used_mem: current DRAM memory consumption.
1956	1958	* @timeout_jiffies: device CS timeout value.
1957	1959	* @max_power: the max power of the device, as configured by the sysadmin. This
@@ -1960,6 +1962,12 @@ struct hl_mmu_funcs { · 2 unmodified lines
1960	1962	* @clock_gating_mask: is clock gating enabled. bitmask that represents the
1961	1963	* different engines. See debugfs-driver-habanalabs for
1962	1964	* details.
	1965	+ * @boot_error_status_mask: contains a mask of the device boot error status.
	1966	+ * Each bit represents a different error, according to
	1967	+ * the defines in hl_boot_if.h. If the bit is cleared,
	1968	+ * the error will be ignored by the driver during
	1969	+ * device initialization. Mainly used to debug and
	1970	+ * workaround firmware bugs
1963	1971	* @in_reset: is device in reset flow.
1964	1972	* @curr_pll_profile: current PLL profile.
1965	1973	* @card_type: Various ASICs have several card types. This indicates the card
@@ -2071,12 +2079,11 @@ struct hl_device { · 105 unmodified lines
2071	2079	struct hl_mmu_priv mmu_priv;
2072	2080	struct hl_mmu_funcs mmu_func[MMU_NUM_PGT_LOCATIONS];
2073	2081
2074		− enum pll_index *legacy_pll_map;
2075		−
2076	2082	atomic64_t dram_used_mem;
2077	2083	u64 timeout_jiffies;
2078	2084	u64 max_power;
2079	2085	u64 clock_gating_mask;
	2086	+ u64 boot_error_status_mask;
2080	2087	atomic_t in_reset;
2081	2088	enum hl_pll_frequency curr_pll_profile;
2082	2089	enum cpucp_card_types card_type;
@@ -2387,9 +2394,9 @@ int hl_fw_cpucp_pci_counters_get(struct hl_device *hdev, · 304 unmodified lines
2387	2394	struct hl_info_pci_counters *counters);
2388	2395	int hl_fw_cpucp_total_energy_get(struct hl_device *hdev,
2389	2396	u64 *total_energy);
2390		−int get_used_pll_index(struct hl_device *hdev, enum pll_index input_pll_index,
	2397	+int get_used_pll_index(struct hl_device *hdev, u32 input_pll_index,
2391	2398	enum pll_index *pll_index);
2392		−int hl_fw_cpucp_pll_info_get(struct hl_device *hdev, enum pll_index pll_index,
	2399	+int hl_fw_cpucp_pll_info_get(struct hl_device *hdev, u32 pll_index,
2393	2400	u16 *pll_freq_arr);
2394	2401	int hl_fw_cpucp_power_get(struct hl_device hdev, u64 power);
2395	2402	int hl_fw_init_cpu(struct hl_device *hdev, u32 cpu_boot_status_reg,
@@ -2411,9 +2418,9 @@ int hl_pci_set_outbound_region(struct hl_device *hdev, · 15 unmodified lines
2411	2418	int hl_pci_init(struct hl_device *hdev);
2412	2419	void hl_pci_fini(struct hl_device *hdev);
2413	2420
2414		−long hl_get_frequency(struct hl_device *hdev, enum pll_index pll_index,
	2421	+long hl_get_frequency(struct hl_device *hdev, u32 pll_index,
2415	2422	bool curr);
2416		−void hl_set_frequency(struct hl_device *hdev, enum pll_index pll_index,
	2423	+void hl_set_frequency(struct hl_device *hdev, u32 pll_index,
2417	2424	u64 freq);
2418	2425	int hl_get_temperature(struct hl_device *hdev,
2419	2426	int sensor_index, u32 attr, long *value);

drivers/misc/habanalabs/common/habanalabs_drv.c+7−0

@@ -30,6 +30,7 @@ static DEFINE_MUTEX(hl_devs_idr_lock); · 29 unmodified lines
30	30	static int timeout_locked = 30;
31	31	static int reset_on_lockup = 1;
32	32	static int memory_scrub = 1;
	33	+static ulong boot_error_status_mask = ULONG_MAX;
33	34
34	35	module_param(timeout_locked, int, 0444);
35	36	MODULE_PARM_DESC(timeout_locked,
@@ -43,6 +44,10 @@ module_param(memory_scrub, int, 0444); · 7 unmodified lines
43	44	MODULE_PARM_DESC(memory_scrub,
44	45	"Scrub device memory in various states (0 = no, 1 = yes, default yes)");
45	46
	47	+module_param(boot_error_status_mask, ulong, 0444);
	48	+MODULE_PARM_DESC(boot_error_status_mask,
	49	+ "Mask of the error status during device CPU boot (If bitX is cleared then error X is masked. Default all 1's)");
	50	+
46	51	#define PCI_VENDOR_ID_HABANALABS 0x1da3
47	52
48	53	#define PCI_IDS_GOYA 0x0001
@@ -319,6 +324,8 @@ int create_hdev(struct hl_device *dev, struct pci_dev pdev, · 270 unmodified lines
319	324	hdev->major = hl_major;
320	325	hdev->reset_on_lockup = reset_on_lockup;
321	326	hdev->memory_scrub = memory_scrub;
	327	+ hdev->boot_error_status_mask = boot_error_status_mask;
	328	+
322	329	hdev->pldm = 0;
323	330
324	331	set_driver_behavior_per_device(hdev);

drivers/misc/habanalabs/common/sysfs.c+2−2

@@ -9,7 +9,7 @@ · 8 unmodified lines
9	9
10	10	#include <linux/pci.h>
11	11
12		−long hl_get_frequency(struct hl_device *hdev, enum pll_index pll_index,
	12	+long hl_get_frequency(struct hl_device *hdev, u32 pll_index,
13	13	bool curr)
14	14	{
15	15	struct cpucp_packet pkt;
@@ -44,7 +44,7 @@ long hl_get_frequency(struct hl_device *hdev, enum pll_index pll_index, · 28 unmodified lines
44	44	return (long) result;
45	45	}
46	46
47		−void hl_set_frequency(struct hl_device *hdev, enum pll_index pll_index,
	47	+void hl_set_frequency(struct hl_device *hdev, u32 pll_index,
48	48	u64 freq)
49	49	{
50	50	struct cpucp_packet pkt;

drivers/misc/habanalabs/gaudi/gaudi.c+23−36

@@ -105,36 +105,6 @@ · 104 unmodified lines
105	105
106	106	#define GAUDI_PLL_MAX 10
107	107
108		−/*
109		− * this enum kept here for compatibility with old FW (in which each asic has
110		− * unique PLL numbering
111		− */
112		−enum gaudi_pll_index {
113		− GAUDI_CPU_PLL = 0,
114		− GAUDI_PCI_PLL,
115		− GAUDI_SRAM_PLL,
116		− GAUDI_HBM_PLL,
117		− GAUDI_NIC_PLL,
118		− GAUDI_DMA_PLL,
119		− GAUDI_MESH_PLL,
120		− GAUDI_MME_PLL,
121		− GAUDI_TPC_PLL,
122		− GAUDI_IF_PLL,
123		−};
124		−
125		−static enum pll_index gaudi_pll_map[PLL_MAX] = {
126		− [CPU_PLL] = GAUDI_CPU_PLL,
127		− [PCI_PLL] = GAUDI_PCI_PLL,
128		− [SRAM_PLL] = GAUDI_SRAM_PLL,
129		− [HBM_PLL] = GAUDI_HBM_PLL,
130		− [NIC_PLL] = GAUDI_NIC_PLL,
131		− [DMA_PLL] = GAUDI_DMA_PLL,
132		− [MESH_PLL] = GAUDI_MESH_PLL,
133		− [MME_PLL] = GAUDI_MME_PLL,
134		− [TPC_PLL] = GAUDI_TPC_PLL,
135		− [IF_PLL] = GAUDI_IF_PLL,
136		−};
137		−
138	108	static const char gaudi_irq_name[GAUDI_MSI_ENTRIES][GAUDI_MAX_STRING_LEN] = {
139	109	"gaudi cq 0_0", "gaudi cq 0_1", "gaudi cq 0_2", "gaudi cq 0_3",
140	110	"gaudi cq 1_0", "gaudi cq 1_1", "gaudi cq 1_2", "gaudi cq 1_3",
@@ -810,7 +780,7 @@ static int gaudi_fetch_psoc_frequency(struct hl_device *hdev) · 669 unmodified lines
810	780	freq = 0;
811	781	}
812	782	} else {
813		− rc = hl_fw_cpucp_pll_info_get(hdev, CPU_PLL, pll_freq_arr);
	783	+ rc = hl_fw_cpucp_pll_info_get(hdev, HL_GAUDI_CPU_PLL, pll_freq_arr);
814	784
815	785	if (rc)
816	786	return rc;
@@ -1652,9 +1622,6 @@ static int gaudi_sw_init(struct hl_device *hdev) · 835 unmodified lines
1652	1622
1653	1623	hdev->asic_specific = gaudi;
1654	1624
1655		− /* store legacy PLL map */
1656		− hdev->legacy_pll_map = gaudi_pll_map;
1657		−
1658	1625	/* Create DMA pool for small allocations */
1659	1626	hdev->dma_pool = dma_pool_create(dev_name(hdev->dev),
1660	1627	&hdev->pdev->dev, GAUDI_DMA_POOL_BLK_SIZE, 8, 0);
@@ -5612,6 +5579,7 @@ static int gaudi_memset_device_memory(struct hl_device *hdev, u64 addr, · 3951 unmodified lines
5612	5579	struct hl_cs_job *job;
5613	5580	u32 cb_size, ctl, err_cause;
5614	5581	struct hl_cb *cb;
	5582	+ u64 id;
5615	5583	int rc;
5616	5584
5617	5585	cb = hl_cb_kernel_create(hdev, PAGE_SIZE, false);
@@ -5678,8 +5646,9 @@ static int gaudi_memset_device_memory(struct hl_device *hdev, u64 addr, · 60 unmodified lines
5678	5646	}
5679	5647
5680	5648	release_cb:
	5649	+ id = cb->id;
5681	5650	hl_cb_put(cb);
5682		− hl_cb_destroy(hdev, &hdev->kernel_cb_mgr, cb->id << PAGE_SHIFT);
	5651	+ hl_cb_destroy(hdev, &hdev->kernel_cb_mgr, id << PAGE_SHIFT);
5683	5652
5684	5653	return rc;
5685	5654	}
@@ -8783,6 +8752,23 @@ static void gaudi_enable_events_from_fw(struct hl_device *hdev) · 3097 unmodified lines
8783	8752	WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR, GAUDI_EVENT_INTS_REGISTER);
8784	8753	}
8785	8754
	8755	+static int gaudi_map_pll_idx_to_fw_idx(u32 pll_idx)
	8756	+{
	8757	+ switch (pll_idx) {
	8758	+ case HL_GAUDI_CPU_PLL: return CPU_PLL;
	8759	+ case HL_GAUDI_PCI_PLL: return PCI_PLL;
	8760	+ case HL_GAUDI_NIC_PLL: return NIC_PLL;
	8761	+ case HL_GAUDI_DMA_PLL: return DMA_PLL;
	8762	+ case HL_GAUDI_MESH_PLL: return MESH_PLL;
	8763	+ case HL_GAUDI_MME_PLL: return MME_PLL;
	8764	+ case HL_GAUDI_TPC_PLL: return TPC_PLL;
	8765	+ case HL_GAUDI_IF_PLL: return IF_PLL;
	8766	+ case HL_GAUDI_SRAM_PLL: return SRAM_PLL;
	8767	+ case HL_GAUDI_HBM_PLL: return HBM_PLL;
	8768	+ default: return -EINVAL;
	8769	+ }
	8770	+}
	8771	+
8786	8772	static const struct hl_asic_funcs gaudi_funcs = {
8787	8773	.early_init = gaudi_early_init,
8788	8774	.early_fini = gaudi_early_fini,
@@ -8866,7 +8852,8 @@ static const struct hl_asic_funcs gaudi_funcs = { · 77 unmodified lines
8866	8852	.ack_protection_bits_errors = gaudi_ack_protection_bits_errors,
8867	8853	.get_hw_block_id = gaudi_get_hw_block_id,
8868	8854	.hw_block_mmap = gaudi_block_mmap,
8869		− .enable_events_from_fw = gaudi_enable_events_from_fw
	8855	+ .enable_events_from_fw = gaudi_enable_events_from_fw,
	8856	+ .map_pll_idx_to_fw_idx = gaudi_map_pll_idx_to_fw_idx
8870	8857	};
8871	8858
8872	8859	/**

drivers/misc/habanalabs/gaudi/gaudi_hwmgr.c+6−6

@@ -13,7 +13,7 @@ void gaudi_set_pll_profile(struct hl_device *hdev, enum hl_pll_frequency freq) · 12 unmodified lines
13	13	struct gaudi_device *gaudi = hdev->asic_specific;
14	14
15	15	if (freq == PLL_LAST)
16		− hl_set_frequency(hdev, MME_PLL, gaudi->max_freq_value);
	16	+ hl_set_frequency(hdev, HL_GAUDI_MME_PLL, gaudi->max_freq_value);
17	17	}
18	18
19	19	int gaudi_get_clk_rate(struct hl_device hdev, u32 cur_clk, u32 *max_clk)
@@ -23,7 +23,7 @@ int gaudi_get_clk_rate(struct hl_device hdev, u32 cur_clk, u32 *max_clk) · 3 unmodified lines
23	23	if (!hl_device_operational(hdev, NULL))
24	24	return -ENODEV;
25	25
26		− value = hl_get_frequency(hdev, MME_PLL, false);
	26	+ value = hl_get_frequency(hdev, HL_GAUDI_MME_PLL, false);
27	27
28	28	if (value < 0) {
29	29	dev_err(hdev->dev, "Failed to retrieve device max clock %ld\n",
@@ -33,7 +33,7 @@ int gaudi_get_clk_rate(struct hl_device hdev, u32 cur_clk, u32 *max_clk) · 3 unmodified lines
33	33
34	34	*max_clk = (value / 1000 / 1000);
35	35
36		− value = hl_get_frequency(hdev, MME_PLL, true);
	36	+ value = hl_get_frequency(hdev, HL_GAUDI_MME_PLL, true);
37	37
38	38	if (value < 0) {
39	39	dev_err(hdev->dev,
@@ -57,7 +57,7 @@ static ssize_t clk_max_freq_mhz_show(struct device *dev, · 17 unmodified lines
57	57	if (!hl_device_operational(hdev, NULL))
58	58	return -ENODEV;
59	59
60		− value = hl_get_frequency(hdev, MME_PLL, false);
	60	+ value = hl_get_frequency(hdev, HL_GAUDI_MME_PLL, false);
61	61
62	62	gaudi->max_freq_value = value;
63	63
@@ -85,7 +85,7 @@ static ssize_t clk_max_freq_mhz_store(struct device *dev, · 21 unmodified lines
85	85
86	86	gaudi->max_freq_value = value * 1000 * 1000;
87	87
88		− hl_set_frequency(hdev, MME_PLL, gaudi->max_freq_value);
	88	+ hl_set_frequency(hdev, HL_GAUDI_MME_PLL, gaudi->max_freq_value);
89	89
90	90	fail:
91	91	return count;
@@ -100,7 +100,7 @@ static ssize_t clk_cur_freq_mhz_show(struct device *dev, · 8 unmodified lines
100	100	if (!hl_device_operational(hdev, NULL))
101	101	return -ENODEV;
102	102
103		− value = hl_get_frequency(hdev, MME_PLL, true);
	103	+ value = hl_get_frequency(hdev, HL_GAUDI_MME_PLL, true);
104	104
105	105	return sprintf(buf, "%lu\n", (value / 1000 / 1000));
106	106	}

drivers/misc/habanalabs/goya/goya.c+18−29

@@ -118,30 +118,6 @@ · 117 unmodified lines
118	118	#define IS_MME_IDLE(mme_arch_sts) \
119	119	(((mme_arch_sts) & MME_ARCH_IDLE_MASK) == MME_ARCH_IDLE_MASK)
120	120
121		−/*
122		− * this enum kept here for compatibility with old FW (in which each asic has
123		− * unique PLL numbering
124		− */
125		−enum goya_pll_index {
126		− GOYA_CPU_PLL = 0,
127		− GOYA_IC_PLL,
128		− GOYA_MC_PLL,
129		− GOYA_MME_PLL,
130		− GOYA_PCI_PLL,
131		− GOYA_EMMC_PLL,
132		− GOYA_TPC_PLL,
133		−};
134		−
135		−static enum pll_index goya_pll_map[PLL_MAX] = {
136		− [CPU_PLL] = GOYA_CPU_PLL,
137		− [IC_PLL] = GOYA_IC_PLL,
138		− [MC_PLL] = GOYA_MC_PLL,
139		− [MME_PLL] = GOYA_MME_PLL,
140		− [PCI_PLL] = GOYA_PCI_PLL,
141		− [EMMC_PLL] = GOYA_EMMC_PLL,
142		− [TPC_PLL] = GOYA_TPC_PLL,
143		−};
144		−
145	121	static const char goya_irq_name[GOYA_MSIX_ENTRIES][GOYA_MAX_STRING_LEN] = {
146	122	"goya cq 0", "goya cq 1", "goya cq 2", "goya cq 3",
147	123	"goya cq 4", "goya cpu eq"
@@ -775,7 +751,8 @@ static void goya_fetch_psoc_frequency(struct hl_device *hdev) · 627 unmodified lines
775	751	freq = 0;
776	752	}
777	753	} else {
778		− rc = hl_fw_cpucp_pll_info_get(hdev, PCI_PLL, pll_freq_arr);
	754	+ rc = hl_fw_cpucp_pll_info_get(hdev, HL_GOYA_PCI_PLL,
	755	+ pll_freq_arr);
779	756
780	757	if (rc)
781	758	return;
@@ -897,9 +874,6 @@ static int goya_sw_init(struct hl_device *hdev) · 115 unmodified lines
897	874
898	875	hdev->asic_specific = goya;
899	876
900		− /* store legacy PLL map */
901		− hdev->legacy_pll_map = goya_pll_map;
902		−
903	877	/* Create DMA pool for small allocations */
904	878	hdev->dma_pool = dma_pool_create(dev_name(hdev->dev),
905	879	&hdev->pdev->dev, GOYA_DMA_POOL_BLK_SIZE, 8, 0);
@@ -5512,6 +5486,20 @@ static void goya_enable_events_from_fw(struct hl_device *hdev) · 4606 unmodified lines
5512	5486	GOYA_ASYNC_EVENT_ID_INTS_REGISTER);
5513	5487	}
5514	5488
	5489	+static int goya_map_pll_idx_to_fw_idx(u32 pll_idx)
	5490	+{
	5491	+ switch (pll_idx) {
	5492	+ case HL_GOYA_CPU_PLL: return CPU_PLL;
	5493	+ case HL_GOYA_PCI_PLL: return PCI_PLL;
	5494	+ case HL_GOYA_MME_PLL: return MME_PLL;
	5495	+ case HL_GOYA_TPC_PLL: return TPC_PLL;
	5496	+ case HL_GOYA_IC_PLL: return IC_PLL;
	5497	+ case HL_GOYA_MC_PLL: return MC_PLL;
	5498	+ case HL_GOYA_EMMC_PLL: return EMMC_PLL;
	5499	+ default: return -EINVAL;
	5500	+ }
	5501	+}
	5502	+
5515	5503	static const struct hl_asic_funcs goya_funcs = {
5516	5504	.early_init = goya_early_init,
5517	5505	.early_fini = goya_early_fini,
@@ -5595,7 +5583,8 @@ static const struct hl_asic_funcs goya_funcs = { · 77 unmodified lines
5595	5583	.ack_protection_bits_errors = goya_ack_protection_bits_errors,
5596	5584	.get_hw_block_id = goya_get_hw_block_id,
5597	5585	.hw_block_mmap = goya_block_mmap,
5598		− .enable_events_from_fw = goya_enable_events_from_fw
	5586	+ .enable_events_from_fw = goya_enable_events_from_fw,
	5587	+ .map_pll_idx_to_fw_idx = goya_map_pll_idx_to_fw_idx
5599	5588	};
5600	5589
5601	5590	/*

drivers/misc/habanalabs/goya/goya_hwmgr.c+20−20

@@ -13,19 +13,19 @@ void goya_set_pll_profile(struct hl_device *hdev, enum hl_pll_frequency freq) · 12 unmodified lines
13	13
14	14	switch (freq) {
15	15	case PLL_HIGH:
16		− hl_set_frequency(hdev, MME_PLL, hdev->high_pll);
17		− hl_set_frequency(hdev, TPC_PLL, hdev->high_pll);
18		− hl_set_frequency(hdev, IC_PLL, hdev->high_pll);
	16	+ hl_set_frequency(hdev, HL_GOYA_MME_PLL, hdev->high_pll);
	17	+ hl_set_frequency(hdev, HL_GOYA_TPC_PLL, hdev->high_pll);
	18	+ hl_set_frequency(hdev, HL_GOYA_IC_PLL, hdev->high_pll);
19	19	break;
20	20	case PLL_LOW:
21		− hl_set_frequency(hdev, MME_PLL, GOYA_PLL_FREQ_LOW);
22		− hl_set_frequency(hdev, TPC_PLL, GOYA_PLL_FREQ_LOW);
23		− hl_set_frequency(hdev, IC_PLL, GOYA_PLL_FREQ_LOW);
	21	+ hl_set_frequency(hdev, HL_GOYA_MME_PLL, GOYA_PLL_FREQ_LOW);
	22	+ hl_set_frequency(hdev, HL_GOYA_TPC_PLL, GOYA_PLL_FREQ_LOW);
	23	+ hl_set_frequency(hdev, HL_GOYA_IC_PLL, GOYA_PLL_FREQ_LOW);
24	24	break;
25	25	case PLL_LAST:
26		− hl_set_frequency(hdev, MME_PLL, goya->mme_clk);
27		− hl_set_frequency(hdev, TPC_PLL, goya->tpc_clk);
28		− hl_set_frequency(hdev, IC_PLL, goya->ic_clk);
	26	+ hl_set_frequency(hdev, HL_GOYA_MME_PLL, goya->mme_clk);
	27	+ hl_set_frequency(hdev, HL_GOYA_TPC_PLL, goya->tpc_clk);
	28	+ hl_set_frequency(hdev, HL_GOYA_IC_PLL, goya->ic_clk);
29	29	break;
30	30	default:
31	31	dev_err(hdev->dev, "unknown frequency setting\n");
@@ -39,7 +39,7 @@ int goya_get_clk_rate(struct hl_device hdev, u32 cur_clk, u32 *max_clk) · 7 unmodified lines
39	39	if (!hl_device_operational(hdev, NULL))
40	40	return -ENODEV;
41	41
42		− value = hl_get_frequency(hdev, MME_PLL, false);
	42	+ value = hl_get_frequency(hdev, HL_GOYA_MME_PLL, false);
43	43
44	44	if (value < 0) {
45	45	dev_err(hdev->dev, "Failed to retrieve device max clock %ld\n",
@@ -49,7 +49,7 @@ int goya_get_clk_rate(struct hl_device hdev, u32 cur_clk, u32 *max_clk) · 3 unmodified lines
49	49
50	50	*max_clk = (value / 1000 / 1000);
51	51
52		− value = hl_get_frequency(hdev, MME_PLL, true);
	52	+ value = hl_get_frequency(hdev, HL_GOYA_MME_PLL, true);
53	53
54	54	if (value < 0) {
55	55	dev_err(hdev->dev,
@@ -72,7 +72,7 @@ static ssize_t mme_clk_show(struct device dev, struct device_attribute attr, · 16 unmodified lines
72	72	if (!hl_device_operational(hdev, NULL))
73	73	return -ENODEV;
74	74
75		− value = hl_get_frequency(hdev, MME_PLL, false);
	75	+ value = hl_get_frequency(hdev, HL_GOYA_MME_PLL, false);
76	76
77	77	if (value < 0)
78	78	return value;
@@ -105,7 +105,7 @@ static ssize_t mme_clk_store(struct device dev, struct device_attribute attr, · 26 unmodified lines
105	105	goto fail;
106	106	}
107	107
108		− hl_set_frequency(hdev, MME_PLL, value);
	108	+ hl_set_frequency(hdev, HL_GOYA_MME_PLL, value);
109	109	goya->mme_clk = value;
110	110
111	111	fail:
@@ -121,7 +121,7 @@ static ssize_t tpc_clk_show(struct device dev, struct device_attribute attr, · 9 unmodified lines
121	121	if (!hl_device_operational(hdev, NULL))
122	122	return -ENODEV;
123	123
124		− value = hl_get_frequency(hdev, TPC_PLL, false);
	124	+ value = hl_get_frequency(hdev, HL_GOYA_TPC_PLL, false);
125	125
126	126	if (value < 0)
127	127	return value;
@@ -154,7 +154,7 @@ static ssize_t tpc_clk_store(struct device dev, struct device_attribute attr, · 26 unmodified lines
154	154	goto fail;
155	155	}
156	156
157		− hl_set_frequency(hdev, TPC_PLL, value);
	157	+ hl_set_frequency(hdev, HL_GOYA_TPC_PLL, value);
158	158	goya->tpc_clk = value;
159	159
160	160	fail:
@@ -170,7 +170,7 @@ static ssize_t ic_clk_show(struct device dev, struct device_attribute attr, · 9 unmodified lines
170	170	if (!hl_device_operational(hdev, NULL))
171	171	return -ENODEV;
172	172
173		− value = hl_get_frequency(hdev, IC_PLL, false);
	173	+ value = hl_get_frequency(hdev, HL_GOYA_IC_PLL, false);
174	174
175	175	if (value < 0)
176	176	return value;
@@ -203,7 +203,7 @@ static ssize_t ic_clk_store(struct device dev, struct device_attribute attr, · 26 unmodified lines
203	203	goto fail;
204	204	}
205	205
206		− hl_set_frequency(hdev, IC_PLL, value);
	206	+ hl_set_frequency(hdev, HL_GOYA_IC_PLL, value);
207	207	goya->ic_clk = value;
208	208
209	209	fail:
@@ -219,7 +219,7 @@ static ssize_t mme_clk_curr_show(struct device *dev, · 9 unmodified lines
219	219	if (!hl_device_operational(hdev, NULL))
220	220	return -ENODEV;
221	221
222		− value = hl_get_frequency(hdev, MME_PLL, true);
	222	+ value = hl_get_frequency(hdev, HL_GOYA_MME_PLL, true);
223	223
224	224	if (value < 0)
225	225	return value;
@@ -236,7 +236,7 @@ static ssize_t tpc_clk_curr_show(struct device *dev, · 10 unmodified lines
236	236	if (!hl_device_operational(hdev, NULL))
237	237	return -ENODEV;
238	238
239		− value = hl_get_frequency(hdev, TPC_PLL, true);
	239	+ value = hl_get_frequency(hdev, HL_GOYA_TPC_PLL, true);
240	240
241	241	if (value < 0)
242	242	return value;
@@ -253,7 +253,7 @@ static ssize_t ic_clk_curr_show(struct device *dev, · 10 unmodified lines
253	253	if (!hl_device_operational(hdev, NULL))
254	254	return -ENODEV;
255	255
256		− value = hl_get_frequency(hdev, IC_PLL, true);
	256	+ value = hl_get_frequency(hdev, HL_GOYA_IC_PLL, true);
257	257
258	258	if (value < 0)
259	259	return value;

drivers/misc/ics932s401.c+1−1

@@ -134,7 +134,7 @@ static struct ics932s401_data ics932s401_update_device(struct device dev) · 133 unmodified lines
134	134	for (i = 0; i < NUM_MIRRORED_REGS; i++) {
135	135	temp = i2c_smbus_read_word_data(client, regs_to_copy[i]);
136	136	if (temp < 0)
137		− data->regs[regs_to_copy[i]] = 0;
	137	+ temp = 0;
138	138	data->regs[regs_to_copy[i]] = temp >> 8;
139	139	}
140	140

drivers/misc/kgdbts.c+2−1

@@ -101,8 +101,9 @@ · 100 unmodified lines
101	101	printk(KERN_INFO a); \
102	102	} while (0)
103	103	#define v2printk(a...) do { \
104		− if (verbose > 1) \
	104	+ if (verbose > 1) { \
105	105	printk(KERN_INFO a); \
	106	+ } \
106	107	touch_nmi_watchdog(); \
107	108	} while (0)
108	109	#define eprintk(a...) do { \

drivers/misc/lis3lv02d/lis3lv02d.h+1−0

@@ -271,6 +271,7 @@ struct lis3lv02d { · 270 unmodified lines
271	271	int regs_size;
272	272	u8 *reg_cache;
273	273	bool regs_stored;
	274	+ bool init_required;
274	275	u8 odr_mask; /* ODR bit mask */
275	276	u8 whoami; /* indicates measurement precision */
276	277	s16 (read_data) (struct lis3lv02d lis3, int reg);

drivers/misc/mei/interrupt.c+3−0

@@ -277,6 +277,9 @@ static int mei_cl_irq_read(struct mei_cl cl, struct mei_cl_cb cb, · 276 unmodified lines
277	277	return ret;
278	278	}
279	279
	280	+ pm_runtime_mark_last_busy(dev->dev);
	281	+ pm_request_autosuspend(dev->dev);
	282	+
280	283	list_move_tail(&cb->list, &cl->rd_pending);
281	284
282	285	return 0;

drivers/mmc/host/meson-gx-mmc.c+5−2

@@ -236,7 +236,8 @@ static void meson_mmc_get_transfer_mode(struct mmc_host *mmc, · 235 unmodified lines
236	236	if (host->dram_access_quirk)
237	237	return;
238	238
239		− if (data->blocks > 1) {
	239	+ /* SD_IO_RW_EXTENDED (CMD53) can also use block mode under the hood */
	240	+ if (data->blocks > 1 \|\| mrq->cmd->opcode == SD_IO_RW_EXTENDED) {
240	241	/*
241	242	* In block mode DMA descriptor format, "length" field indicates
242	243	* number of blocks and there is no way to pass DMA size that
@@ -258,7 +259,9 @@ static void meson_mmc_get_transfer_mode(struct mmc_host *mmc, · 15 unmodified lines
258	259	for_each_sg(data->sg, sg, data->sg_len, i) {
259	260	/* check for 8 byte alignment */
260	261	if (sg->offset % 8) {
261		− WARN_ONCE(1, "unaligned scatterlist buffer\n");
	262	+ dev_warn_once(mmc_dev(mmc),
	263	+ "unaligned sg offset %u, disabling descriptor DMA for transfer\n",
	264	+ sg->offset);
262	265	return;
263	266	}
264	267	}

drivers/mmc/host/renesas_sdhi_core.c+7−2

@@ -692,14 +692,19 @@ static int renesas_sdhi_execute_tuning(struct mmc_host *mmc, u32 opcode) · 691 unmodified lines
692	692
693	693	/* Issue CMD19 twice for each tap */
694	694	for (i = 0; i < 2 * priv->tap_num; i++) {
	695	+ int cmd_error;
	696	+
695	697	/* Set sampling clock position */
696	698	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, i % priv->tap_num);
697	699
698		− if (mmc_send_tuning(mmc, opcode, NULL) == 0)
	700	+ if (mmc_send_tuning(mmc, opcode, &cmd_error) == 0)
699	701	set_bit(i, priv->taps);
700	702
701	703	if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) == 0)
702	704	set_bit(i, priv->smpcmp);
	705	+
	706	+ if (cmd_error)
	707	+ mmc_abort_tuning(mmc, opcode);
703	708	}
704	709
705	710	ret = renesas_sdhi_select_tuning(host);
@@ -939,7 +944,7 @@ static const struct soc_device_attribute sdhi_quirks_match[] = { · 233 unmodified lines
939	944	{ .soc_id = "r8a7795", .revision = "ES3.*", .data = &sdhi_quirks_bad_taps2367 },
940	945	{ .soc_id = "r8a7796", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 },
941	946	{ .soc_id = "r8a7796", .revision = "ES1.*", .data = &sdhi_quirks_r8a7796_es13 },
942		− { .soc_id = "r8a7796", .revision = "ES3.*", .data = &sdhi_quirks_bad_taps1357 },
	947	+ { .soc_id = "r8a77961", .data = &sdhi_quirks_bad_taps1357 },
943	948	{ .soc_id = "r8a77965", .data = &sdhi_quirks_r8a77965 },
944	949	{ .soc_id = "r8a77980", .data = &sdhi_quirks_nohs400 },
945	950	{ .soc_id = "r8a77990", .data = &sdhi_quirks_r8a77990 },

drivers/mmc/host/sdhci-pci-gli.c+6−1

@@ -627,8 +627,13 @@ static void sdhci_gli_voltage_switch(struct sdhci_host *host) · 626 unmodified lines
627	627	*
628	628	* Wait 5ms after set 1.8V signal enable in Host Control 2 register
629	629	* to ensure 1.8V signal enable bit is set by GL9750/GL9755.
	630	+ *
	631	+ * ...however, the controller in the NUC10i3FNK4 (a 9755) requires
	632	+ * slightly longer than 5ms before the control register reports that
	633	+ * 1.8V is ready, and far longer still before the card will actually
	634	+ * work reliably.
630	635	*/
631		− usleep_range(5000, 5500);
	636	+ usleep_range(100000, 110000);
632	637	}
633	638
634	639	static void sdhci_gl9750_reset(struct sdhci_host *host, u8 mask)

drivers/mtd/nand/raw/cs553x_nand.c+11−1

@@ -18,6 +18,7 @@ · 17 unmodified lines
18	18	#include <linux/module.h>
19	19	#include <linux/delay.h>
20	20	#include <linux/mtd/mtd.h>
	21	+#include <linux/mtd/nand-ecc-sw-hamming.h>
21	22	#include <linux/mtd/rawnand.h>
22	23	#include <linux/mtd/partitions.h>
23	24	#include <linux/iopoll.h>
@@ -240,6 +241,15 @@ static int cs_calculate_ecc(struct nand_chip this, const u_char dat, · 216 unmodified lines
240	241	return 0;
241	242	}
242	243
	244	+static int cs553x_ecc_correct(struct nand_chip *chip,
	245	+ unsigned char *buf,
	246	+ unsigned char *read_ecc,
	247	+ unsigned char *calc_ecc)
	248	+{
	249	+ return ecc_sw_hamming_correct(buf, read_ecc, calc_ecc,
	250	+ chip->ecc.size, false);
	251	+}
	252	+
243	253	static struct cs553x_nand_controller *controllers[4];
244	254
245	255	static int cs553x_attach_chip(struct nand_chip *chip)
@@ -251,7 +261,7 @@ static int cs553x_attach_chip(struct nand_chip *chip) · 5 unmodified lines
251	261	chip->ecc.bytes = 3;
252	262	chip->ecc.hwctl = cs_enable_hwecc;
253	263	chip->ecc.calculate = cs_calculate_ecc;
254		− chip->ecc.correct = rawnand_sw_hamming_correct;
	264	+ chip->ecc.correct = cs553x_ecc_correct;
255	265	chip->ecc.strength = 1;
256	266
257	267	return 0;

drivers/mtd/nand/raw/fsmc_nand.c+11−1

@@ -25,6 +25,7 @@ · 24 unmodified lines
25	25	#include <linux/sched.h>
26	26	#include <linux/types.h>
27	27	#include <linux/mtd/mtd.h>
	28	+#include <linux/mtd/nand-ecc-sw-hamming.h>
28	29	#include <linux/mtd/rawnand.h>
29	30	#include <linux/platform_device.h>
30	31	#include <linux/of.h>
@@ -432,6 +433,15 @@ static int fsmc_read_hwecc_ecc1(struct nand_chip chip, const u8 data, · 401 unmodified lines
432	433	return 0;
433	434	}
434	435
	436	+static int fsmc_correct_ecc1(struct nand_chip *chip,
	437	+ unsigned char *buf,
	438	+ unsigned char *read_ecc,
	439	+ unsigned char *calc_ecc)
	440	+{
	441	+ return ecc_sw_hamming_correct(buf, read_ecc, calc_ecc,
	442	+ chip->ecc.size, false);
	443	+}
	444	+
435	445	/* Count the number of 0's in buff upto a max of max_bits */
436	446	static int count_written_bits(u8 *buff, int size, int max_bits)
437	447	{
@@ -917,7 +927,7 @@ static int fsmc_nand_attach_chip(struct nand_chip *nand) · 479 unmodified lines
917	927	case NAND_ECC_ENGINE_TYPE_ON_HOST:
918	928	dev_info(host->dev, "Using 1-bit HW ECC scheme\n");
919	929	nand->ecc.calculate = fsmc_read_hwecc_ecc1;
920		− nand->ecc.correct = rawnand_sw_hamming_correct;
	930	+ nand->ecc.correct = fsmc_correct_ecc1;
921	931	nand->ecc.hwctl = fsmc_enable_hwecc;
922	932	nand->ecc.bytes = 3;
923	933	nand->ecc.strength = 1;

drivers/mtd/nand/raw/lpc32xx_slc.c+14−1

@@ -27,6 +27,7 @@ · 26 unmodified lines
27	27	#include <linux/of.h>
28	28	#include <linux/of_gpio.h>
29	29	#include <linux/mtd/lpc32xx_slc.h>
	30	+#include <linux/mtd/nand-ecc-sw-hamming.h>
30	31
31	32	#define LPC32XX_MODNAME "lpc32xx-nand"
32	33
@@ -344,6 +345,18 @@ static int lpc32xx_nand_ecc_calculate(struct nand_chip *chip, · 311 unmodified lines
344	345	return 0;
345	346	}
346	347
	348	+/*
	349	+ * Corrects the data
	350	+ */
	351	+static int lpc32xx_nand_ecc_correct(struct nand_chip *chip,
	352	+ unsigned char *buf,
	353	+ unsigned char *read_ecc,
	354	+ unsigned char *calc_ecc)
	355	+{
	356	+ return ecc_sw_hamming_correct(buf, read_ecc, calc_ecc,
	357	+ chip->ecc.size, false);
	358	+}
	359	+
347	360	/*
348	361	* Read a single byte from NAND device
349	362	*/
@@ -802,7 +815,7 @@ static int lpc32xx_nand_attach_chip(struct nand_chip *chip) · 452 unmodified lines
802	815	chip->ecc.write_oob = lpc32xx_nand_write_oob_syndrome;
803	816	chip->ecc.read_oob = lpc32xx_nand_read_oob_syndrome;
804	817	chip->ecc.calculate = lpc32xx_nand_ecc_calculate;
805		− chip->ecc.correct = rawnand_sw_hamming_correct;
	818	+ chip->ecc.correct = lpc32xx_nand_ecc_correct;
806	819	chip->ecc.hwctl = lpc32xx_nand_ecc_enable;
807	820
808	821	/*

drivers/mtd/nand/raw/ndfc.c+11−1

@@ -22,6 +22,7 @@ · 21 unmodified lines
22	22	#include <linux/mtd/ndfc.h>
23	23	#include <linux/slab.h>
24	24	#include <linux/mtd/mtd.h>
	25	+#include <linux/mtd/nand-ecc-sw-hamming.h>
25	26	#include <linux/of_address.h>
26	27	#include <linux/of_platform.h>
27	28	#include <asm/io.h>
@@ -100,6 +101,15 @@ static int ndfc_calculate_ecc(struct nand_chip *chip, · 72 unmodified lines
100	101	return 0;
101	102	}
102	103
	104	+static int ndfc_correct_ecc(struct nand_chip *chip,
	105	+ unsigned char *buf,
	106	+ unsigned char *read_ecc,
	107	+ unsigned char *calc_ecc)
	108	+{
	109	+ return ecc_sw_hamming_correct(buf, read_ecc, calc_ecc,
	110	+ chip->ecc.size, false);
	111	+}
	112	+
103	113	/*
104	114	* Speedups for buffer read/write/verify
105	115	*
@@ -145,7 +155,7 @@ static int ndfc_chip_init(struct ndfc_controller *ndfc, · 39 unmodified lines
145	155	chip->controller = &ndfc->ndfc_control;
146	156	chip->legacy.read_buf = ndfc_read_buf;
147	157	chip->legacy.write_buf = ndfc_write_buf;
148		− chip->ecc.correct = rawnand_sw_hamming_correct;
	158	+ chip->ecc.correct = ndfc_correct_ecc;
149	159	chip->ecc.hwctl = ndfc_enable_hwecc;
150	160	chip->ecc.calculate = ndfc_calculate_ecc;
151	161	chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;

drivers/mtd/nand/raw/sharpsl.c+11−1

@@ -11,6 +11,7 @@ · 10 unmodified lines
11	11	#include <linux/module.h>
12	12	#include <linux/delay.h>
13	13	#include <linux/mtd/mtd.h>
	14	+#include <linux/mtd/nand-ecc-sw-hamming.h>
14	15	#include <linux/mtd/rawnand.h>
15	16	#include <linux/mtd/partitions.h>
16	17	#include <linux/mtd/sharpsl.h>
@@ -96,6 +97,15 @@ static int sharpsl_nand_calculate_ecc(struct nand_chip *chip, · 79 unmodified lines
96	97	return readb(sharpsl->io + ECCCNTR) != 0;
97	98	}
98	99
	100	+static int sharpsl_nand_correct_ecc(struct nand_chip *chip,
	101	+ unsigned char *buf,
	102	+ unsigned char *read_ecc,
	103	+ unsigned char *calc_ecc)
	104	+{
	105	+ return ecc_sw_hamming_correct(buf, read_ecc, calc_ecc,
	106	+ chip->ecc.size, false);
	107	+}
	108	+
99	109	static int sharpsl_attach_chip(struct nand_chip *chip)
100	110	{
101	111	if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST)
@@ -106,7 +116,7 @@ static int sharpsl_attach_chip(struct nand_chip *chip) · 4 unmodified lines
106	116	chip->ecc.strength = 1;
107	117	chip->ecc.hwctl = sharpsl_nand_enable_hwecc;
108	118	chip->ecc.calculate = sharpsl_nand_calculate_ecc;
109		− chip->ecc.correct = rawnand_sw_hamming_correct;
	119	+ chip->ecc.correct = sharpsl_nand_correct_ecc;
110	120
111	121	return 0;
112	122	}

drivers/mtd/nand/raw/tmio_nand.c+5−3

@@ -34,6 +34,7 @@ · 33 unmodified lines
34	34	#include <linux/interrupt.h>
35	35	#include <linux/ioport.h>
36	36	#include <linux/mtd/mtd.h>
	37	+#include <linux/mtd/nand-ecc-sw-hamming.h>
37	38	#include <linux/mtd/rawnand.h>
38	39	#include <linux/mtd/partitions.h>
39	40	#include <linux/slab.h>
@@ -292,11 +293,12 @@ static int tmio_nand_correct_data(struct nand_chip chip, unsigned char buf, · 252 unmodified lines
292	293	int r0, r1;
293	294
294	295	/* assume ecc.size = 512 and ecc.bytes = 6 */
295		− r0 = rawnand_sw_hamming_correct(chip, buf, read_ecc, calc_ecc);
	296	+ r0 = ecc_sw_hamming_correct(buf, read_ecc, calc_ecc,
	297	+ chip->ecc.size, false);
296	298	if (r0 < 0)
297	299	return r0;
298		− r1 = rawnand_sw_hamming_correct(chip, buf + 256, read_ecc + 3,
299		− calc_ecc + 3);
	300	+ r1 = ecc_sw_hamming_correct(buf + 256, read_ecc + 3, calc_ecc + 3,
	301	+ chip->ecc.size, false);
300	302	if (r1 < 0)
301	303	return r1;
302	304	return r0 + r1;

drivers/mtd/nand/raw/txx9ndfmc.c+3−2

@@ -13,6 +13,7 @@ · 12 unmodified lines
13	13	#include <linux/platform_device.h>
14	14	#include <linux/delay.h>
15	15	#include <linux/mtd/mtd.h>
	16	+#include <linux/mtd/nand-ecc-sw-hamming.h>
16	17	#include <linux/mtd/rawnand.h>
17	18	#include <linux/mtd/partitions.h>
18	19	#include <linux/io.h>
@@ -193,8 +194,8 @@ static int txx9ndfmc_correct_data(struct nand_chip chip, unsigned char buf, · 174 unmodified lines
193	194	int stat;
194	195
195	196	for (eccsize = chip->ecc.size; eccsize > 0; eccsize -= 256) {
196		− stat = rawnand_sw_hamming_correct(chip, buf, read_ecc,
197		− calc_ecc);
	197	+ stat = ecc_sw_hamming_correct(buf, read_ecc, calc_ecc,
	198	+ chip->ecc.size, false);
198	199	if (stat < 0)
199	200	return stat;
200	201	corrected += stat;

drivers/mtd/parsers/ofpart_core.c+14−12

@@ -57,20 +57,22 @@ static int parse_fixed_partitions(struct mtd_info *master, · 56 unmodified lines
57	57	if (!mtd_node)
58	58	return 0;
59	59
60		− ofpart_node = of_get_child_by_name(mtd_node, "partitions");
61		− if (!ofpart_node && !master->parent) {
62		− /*
63		− * We might get here even when ofpart isn't used at all (e.g.,
64		− * when using another parser), so don't be louder than
65		− * KERN_DEBUG
66		− */
67		− pr_debug("%s: 'partitions' subnode not found on %pOF. Trying to parse direct subnodes as partitions.\n",
68		− master->name, mtd_node);
	60	+ if (!master->parent) { /* Master */
	61	+ ofpart_node = of_get_child_by_name(mtd_node, "partitions");
	62	+ if (!ofpart_node) {
	63	+ /*
	64	+ * We might get here even when ofpart isn't used at all (e.g.,
	65	+ * when using another parser), so don't be louder than
	66	+ * KERN_DEBUG
	67	+ */
	68	+ pr_debug("%s: 'partitions' subnode not found on %pOF. Trying to parse direct subnodes as partitions.\n",
	69	+ master->name, mtd_node);
	70	+ ofpart_node = mtd_node;
	71	+ dedicated = false;
	72	+ }
	73	+ } else { /* Partition */
69	74	ofpart_node = mtd_node;
70		− dedicated = false;
71	75	}
72		− if (!ofpart_node)
73		− return 0;
74	76
75	77	of_id = of_match_node(parse_ofpart_match_table, ofpart_node);
76	78	if (dedicated && !of_id) {

drivers/net/appletalk/cops.c+2−2

@@ -327,6 +327,8 @@ static int __init cops_probe1(struct net_device *dev, int ioaddr) · 326 unmodified lines
327	327	break;
328	328	}
329	329
	330	+ dev->base_addr = ioaddr;
	331	+
330	332	/* Reserve any actual interrupt. */
331	333	if (dev->irq) {
332	334	retval = request_irq(dev->irq, cops_interrupt, 0, dev->name, dev);
@@ -334,8 +336,6 @@ static int __init cops_probe1(struct net_device *dev, int ioaddr) · 1 unmodified line
334	336	goto err_out;
335	337	}
336	338
337		− dev->base_addr = ioaddr;
338		−
339	339	lp = netdev_priv(dev);
340	340	spin_lock_init(&lp->lock);
341	341

drivers/net/bonding/bond_main.c+1−1

@@ -1526,6 +1526,7 @@ static struct slave bond_alloc_slave(struct bonding bond, · 1525 unmodified lines
1526	1526
1527	1527	slave->bond = bond;
1528	1528	slave->dev = slave_dev;
	1529	+ INIT_DELAYED_WORK(&slave->notify_work, bond_netdev_notify_work);
1529	1530
1530	1531	if (bond_kobj_init(slave))
1531	1532	return NULL;
@@ -1538,7 +1539,6 @@ static struct slave bond_alloc_slave(struct bonding bond, · 6 unmodified lines
1538	1539	return NULL;
1539	1540	}
1540	1541	}
1541		− INIT_DELAYED_WORK(&slave->notify_work, bond_netdev_notify_work);
1542	1542
1543	1543	return slave;
1544	1544	}

drivers/net/caif/caif_serial.c+1−3

@@ -269,9 +269,6 @@ static netdev_tx_t caif_xmit(struct sk_buff skb, struct net_device dev) · 268 unmodified lines
269	269	{
270	270	struct ser_device *ser;
271	271
272		− if (WARN_ON(!dev))
273		− return -EINVAL;
274		−
275	272	ser = netdev_priv(dev);
276	273
277	274	/* Send flow off once, on high water mark */
@@ -353,6 +350,7 @@ static int ldisc_open(struct tty_struct *tty) · 75 unmodified lines
353	350	rtnl_lock();
354	351	result = register_netdevice(dev);
355	352	if (result) {
	353	+ tty_kref_put(tty);
356	354	rtnl_unlock();
357	355	free_netdev(dev);
358	356	return -ENODEV;

drivers/net/can/usb/mcba_usb.c+15−2

@@ -82,6 +82,8 @@ struct mcba_priv { · 81 unmodified lines
82	82	bool can_ka_first_pass;
83	83	bool can_speed_check;
84	84	atomic_t free_ctx_cnt;
	85	+ void *rxbuf[MCBA_MAX_RX_URBS];
	86	+ dma_addr_t rxbuf_dma[MCBA_MAX_RX_URBS];
85	87	};
86	88
87	89	/* CAN frame */
@@ -633,6 +635,7 @@ static int mcba_usb_start(struct mcba_priv *priv) · 545 unmodified lines
633	635	for (i = 0; i < MCBA_MAX_RX_URBS; i++) {
634	636	struct urb *urb = NULL;
635	637	u8 *buf;
	638	+ dma_addr_t buf_dma;
636	639
637	640	/* create a URB, and a buffer for it */
638	641	urb = usb_alloc_urb(0, GFP_KERNEL);
@@ -642,7 +645,7 @@ static int mcba_usb_start(struct mcba_priv *priv) · 3 unmodified lines
642	645	}
643	646
644	647	buf = usb_alloc_coherent(priv->udev, MCBA_USB_RX_BUFF_SIZE,
645		− GFP_KERNEL, &urb->transfer_dma);
	648	+ GFP_KERNEL, &buf_dma);
646	649	if (!buf) {
647	650	netdev_err(netdev, "No memory left for USB buffer\n");
648	651	usb_free_urb(urb);
@@ -661,11 +664,14 @@ static int mcba_usb_start(struct mcba_priv *priv) · 12 unmodified lines
661	664	if (err) {
662	665	usb_unanchor_urb(urb);
663	666	usb_free_coherent(priv->udev, MCBA_USB_RX_BUFF_SIZE,
664		− buf, urb->transfer_dma);
	667	+ buf, buf_dma);
665	668	usb_free_urb(urb);
666	669	break;
667	670	}
668	671
	672	+ priv->rxbuf[i] = buf;
	673	+ priv->rxbuf_dma[i] = buf_dma;
	674	+
669	675	/* Drop reference, USB core will take care of freeing it */
670	676	usb_free_urb(urb);
671	677	}
@@ -708,7 +714,14 @@ static int mcba_usb_open(struct net_device *netdev) · 36 unmodified lines
708	714
709	715	static void mcba_urb_unlink(struct mcba_priv *priv)
710	716	{
	717	+ int i;
	718	+
711	719	usb_kill_anchored_urbs(&priv->rx_submitted);
	720	+
	721	+ for (i = 0; i < MCBA_MAX_RX_URBS; ++i)
	722	+ usb_free_coherent(priv->udev, MCBA_USB_RX_BUFF_SIZE,
	723	+ priv->rxbuf[i], priv->rxbuf_dma[i]);
	724	+
712	725	usb_kill_anchored_urbs(&priv->tx_submitted);
713	726	}
714	727

drivers/net/dsa/bcm_sf2.c+2−3

@@ -821,11 +821,9 @@ static void bcm_sf2_sw_mac_link_up(struct dsa_switch *ds, int port, · 820 unmodified lines
821	821	bcm_sf2_sw_mac_link_set(ds, port, interface, true);
822	822
823	823	if (port != core_readl(priv, CORE_IMP0_PRT_ID)) {
824		− u32 reg_rgmii_ctrl;
	824	+ u32 reg_rgmii_ctrl = 0;
825	825	u32 reg, offset;
826	826
827		− reg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, port);
828		−
829	827	if (priv->type == BCM4908_DEVICE_ID \|\|
830	828	priv->type == BCM7445_DEVICE_ID)
831	829	offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);
@@ -836,6 +834,7 @@ static void bcm_sf2_sw_mac_link_up(struct dsa_switch *ds, int port, · 4 unmodified lines
836	834	interface == PHY_INTERFACE_MODE_RGMII_TXID \|\|
837	835	interface == PHY_INTERFACE_MODE_MII \|\|
838	836	interface == PHY_INTERFACE_MODE_REVMII) {
	837	+ reg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, port);
839	838	reg = reg_readl(priv, reg_rgmii_ctrl);
840	839	reg &= ~(RX_PAUSE_EN \| TX_PAUSE_EN);
841	840

drivers/net/dsa/microchip/ksz9477.c+1−0

@@ -1530,6 +1530,7 @@ static const struct ksz_chip_data ksz9477_switch_chips[] = { · 1529 unmodified lines
1530	1530	.num_statics = 16,
1531	1531	.cpu_ports = 0x7F, /* can be configured as cpu port */
1532	1532	.port_cnt = 7, /* total physical port count */
	1533	+ .phy_errata_9477 = true,
1533	1534	},
1534	1535	};
1535	1536

drivers/net/dsa/mt7530.c+0−8

@@ -1262,14 +1262,6 @@ mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port) · 1261 unmodified lines
1262	1262	{
1263	1263	struct mt7530_priv *priv = ds->priv;
1264	1264
1265		− /* The real fabric path would be decided on the membership in the
1266		− * entry of VLAN table. PCR_MATRIX set up here with ALL_MEMBERS
1267		− * means potential VLAN can be consisting of certain subset of all
1268		− * ports.
1269		− */
1270		− mt7530_rmw(priv, MT7530_PCR_P(port),
1271		− PCR_MATRIX_MASK, PCR_MATRIX(MT7530_ALL_MEMBERS));
1272		−
1273	1265	/* Trapped into security mode allows packet forwarding through VLAN
1274	1266	* table lookup. CPU port is set to fallback mode to let untagged
1275	1267	* frames pass through.

drivers/net/dsa/ocelot/felix_vsc9959.c+10−5

@@ -1227,12 +1227,17 @@ static int vsc9959_qos_port_tas_set(struct ocelot *ocelot, int port, · 1226 unmodified lines
1227	1227	if (taprio->num_entries > VSC9959_TAS_GCL_ENTRY_MAX)
1228	1228	return -ERANGE;
1229	1229
1230		− /* Set port num and disable ALWAYS_GUARD_BAND_SCH_Q, which means set
1231		− * guard band to be implemented for nonschedule queues to schedule
1232		− * queues transition.
	1230	+ /* Enable guard band. The switch will schedule frames without taking
	1231	+ * their length into account. Thus we'll always need to enable the
	1232	+ * guard band which reserves the time of a maximum sized frame at the
	1233	+ * end of the time window.
	1234	+ *
	1235	+ * Although the ALWAYS_GUARD_BAND_SCH_Q bit is global for all ports, we
	1236	+ * need to set PORT_NUM, because subsequent writes to PARAM_CFG_REG_n
	1237	+ * operate on the port number.
1233	1238	*/
1234		− ocelot_rmw(ocelot,
1235		− QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(port),
	1239	+ ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(port) \|
	1240	+ QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q,
1236	1241	QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M \|
1237	1242	QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q,
1238	1243	QSYS_TAS_PARAM_CFG_CTRL);

drivers/net/dsa/sja1105/sja1105_dynamic_config.c+19−4

@@ -167,9 +167,10 @@ enum sja1105_hostcmd { · 166 unmodified lines
167	167	SJA1105_HOSTCMD_INVALIDATE = 4,
168	168	};
169	169
	170	+/* Command and entry overlap */
170	171	static void
171		−sja1105_vl_lookup_cmd_packing(void buf, struct sja1105_dyn_cmd cmd,
172		− enum packing_op op)
	172	+sja1105et_vl_lookup_cmd_packing(void buf, struct sja1105_dyn_cmd cmd,
	173	+ enum packing_op op)
173	174	{
174	175	const int size = SJA1105_SIZE_DYN_CMD;
175	176
@@ -179,6 +180,20 @@ sja1105_vl_lookup_cmd_packing(void buf, struct sja1105_dyn_cmd cmd, · 3 unmodified lines
179	180	sja1105_packing(buf, &cmd->index, 9, 0, size, op);
180	181	}
181	182
	183	+/* Command and entry are separate */
	184	+static void
	185	+sja1105pqrs_vl_lookup_cmd_packing(void buf, struct sja1105_dyn_cmd cmd,
	186	+ enum packing_op op)
	187	+{
	188	+ u8 *p = buf + SJA1105_SIZE_VL_LOOKUP_ENTRY;
	189	+ const int size = SJA1105_SIZE_DYN_CMD;
	190	+
	191	+ sja1105_packing(p, &cmd->valid, 31, 31, size, op);
	192	+ sja1105_packing(p, &cmd->errors, 30, 30, size, op);
	193	+ sja1105_packing(p, &cmd->rdwrset, 29, 29, size, op);
	194	+ sja1105_packing(p, &cmd->index, 9, 0, size, op);
	195	+}
	196	+
182	197	static size_t sja1105et_vl_lookup_entry_packing(void buf, void entry_ptr,
183	198	enum packing_op op)
184	199	{
@@ -641,7 +656,7 @@ static size_t sja1105pqrs_cbs_entry_packing(void buf, void entry_ptr, · 456 unmodified lines
641	656	const struct sja1105_dynamic_table_ops sja1105et_dyn_ops[BLK_IDX_MAX_DYN] = {
642	657	[BLK_IDX_VL_LOOKUP] = {
643	658	.entry_packing = sja1105et_vl_lookup_entry_packing,
644		− .cmd_packing = sja1105_vl_lookup_cmd_packing,
	659	+ .cmd_packing = sja1105et_vl_lookup_cmd_packing,
645	660	.access = OP_WRITE,
646	661	.max_entry_count = SJA1105_MAX_VL_LOOKUP_COUNT,
647	662	.packed_size = SJA1105ET_SIZE_VL_LOOKUP_DYN_CMD,
@@ -725,7 +740,7 @@ const struct sja1105_dynamic_table_ops sja1105et_dyn_ops[BLK_IDX_MAX_DYN] = { · 77 unmodified lines
725	740	const struct sja1105_dynamic_table_ops sja1105pqrs_dyn_ops[BLK_IDX_MAX_DYN] = {
726	741	[BLK_IDX_VL_LOOKUP] = {
727	742	.entry_packing = sja1105_vl_lookup_entry_packing,
728		− .cmd_packing = sja1105_vl_lookup_cmd_packing,
	743	+ .cmd_packing = sja1105pqrs_vl_lookup_cmd_packing,
729	744	.access = (OP_READ \| OP_WRITE),
730	745	.max_entry_count = SJA1105_MAX_VL_LOOKUP_COUNT,
731	746	.packed_size = SJA1105PQRS_SIZE_VL_LOOKUP_DYN_CMD,

drivers/net/dsa/sja1105/sja1105_main.c+51−23

@@ -26,6 +26,7 @@ · 25 unmodified lines
26	26	#include "sja1105_tas.h"
27	27
28	28	#define SJA1105_UNKNOWN_MULTICAST 0x010000000000ull
	29	+#define SJA1105_DEFAULT_VLAN (VLAN_N_VID - 1)
29	30
30	31	static const struct dsa_switch_ops sja1105_switch_ops;
31	32
@@ -207,6 +208,7 @@ static int sja1105_init_mii_settings(struct sja1105_private *priv, · 175 unmodified lines
207	208	default:
208	209	dev_err(dev, "Unsupported PHY mode %s!\n",
209	210	phy_modes(ports[i].phy_mode));
	211	+ return -EINVAL;
210	212	}
211	213
212	214	/* Even though the SerDes port is able to drive SGMII autoneg
@@ -321,6 +323,13 @@ static int sja1105_init_l2_lookup_params(struct sja1105_private *priv) · 108 unmodified lines
321	323	return 0;
322	324	}
323	325
	326	+/* Set up a default VLAN for untagged traffic injected from the CPU
	327	+ * using management routes (e.g. STP, PTP) as opposed to tag_8021q.
	328	+ * All DT-defined ports are members of this VLAN, and there are no
	329	+ * restrictions on forwarding (since the CPU selects the destination).
	330	+ * Frames from this VLAN will always be transmitted as untagged, and
	331	+ * neither the bridge nor the 8021q module cannot create this VLAN ID.
	332	+ */
324	333	static int sja1105_init_static_vlan(struct sja1105_private *priv)
325	334	{
326	335	struct sja1105_table *table;
@@ -330,17 +339,13 @@ static int sja1105_init_static_vlan(struct sja1105_private *priv) · 3 unmodified lines
330	339	.vmemb_port = 0,
331	340	.vlan_bc = 0,
332	341	.tag_port = 0,
333		− .vlanid = 1,
	342	+ .vlanid = SJA1105_DEFAULT_VLAN,
334	343	};
335	344	struct dsa_switch *ds = priv->ds;
336	345	int port;
337	346
338	347	table = &priv->static_config.tables[BLK_IDX_VLAN_LOOKUP];
339	348
340		− /* The static VLAN table will only contain the initial pvid of 1.
341		− * All other VLANs are to be configured through dynamic entries,
342		− * and kept in the static configuration table as backing memory.
343		− */
344	349	if (table->entry_count) {
345	350	kfree(table->entries);
346	351	table->entry_count = 0;
@@ -353,9 +358,6 @@ static int sja1105_init_static_vlan(struct sja1105_private *priv) · 6 unmodified lines
353	358
354	359	table->entry_count = 1;
355	360
356		− /* VLAN 1: all DT-defined ports are members; no restrictions on
357		− * forwarding; always transmit as untagged.
358		− */
359	361	for (port = 0; port < ds->num_ports; port++) {
360	362	struct sja1105_bridge_vlan *v;
361	363
@@ -366,15 +368,12 @@ static int sja1105_init_static_vlan(struct sja1105_private *priv) · 4 unmodified lines
366	368	pvid.vlan_bc \|= BIT(port);
367	369	pvid.tag_port &= ~BIT(port);
368	370
369		− /* Let traffic that don't need dsa_8021q (e.g. STP, PTP) be
370		− * transmitted as untagged.
371		− */
372	371	v = kzalloc(sizeof(*v), GFP_KERNEL);
373	372	if (!v)
374	373	return -ENOMEM;
375	374
376	375	v->port = port;
377		− v->vid = 1;
	376	+ v->vid = SJA1105_DEFAULT_VLAN;
378	377	v->untagged = true;
379	378	if (dsa_is_cpu_port(ds, port))
380	379	v->pvid = true;
@@ -2817,11 +2816,22 @@ static int sja1105_vlan_add_one(struct dsa_switch *ds, int port, u16 vid, · 2436 unmodified lines
2817	2816	bool pvid = flags & BRIDGE_VLAN_INFO_PVID;
2818	2817	struct sja1105_bridge_vlan *v;
2819	2818
2820		− list_for_each_entry(v, vlan_list, list)
2821		− if (v->port == port && v->vid == vid &&
2822		− v->untagged == untagged && v->pvid == pvid)
	2819	+ list_for_each_entry(v, vlan_list, list) {
	2820	+ if (v->port == port && v->vid == vid) {
2823	2821	/* Already added */
2824		− return 0;
	2822	+ if (v->untagged == untagged && v->pvid == pvid)
	2823	+ /* Nothing changed */
	2824	+ return 0;
	2825	+
	2826	+ /* It's the same VLAN, but some of the flags changed
	2827	+ * and the user did not bother to delete it first.
	2828	+ * Update it and trigger sja1105_build_vlan_table.
	2829	+ */
	2830	+ v->untagged = untagged;
	2831	+ v->pvid = pvid;
	2832	+ return 1;
	2833	+ }
	2834	+ }
2825	2835
2826	2836	v = kzalloc(sizeof(*v), GFP_KERNEL);
2827	2837	if (!v) {
@@ -2976,13 +2986,13 @@ static int sja1105_setup(struct dsa_switch *ds) · 148 unmodified lines
2976	2986	rc = sja1105_static_config_load(priv, ports);
2977	2987	if (rc < 0) {
2978	2988	dev_err(ds->dev, "Failed to load static config: %d\n", rc);
2979		− return rc;
	2989	+ goto out_ptp_clock_unregister;
2980	2990	}
2981	2991	/* Configure the CGU (PHY link modes and speeds) */
2982	2992	rc = sja1105_clocking_setup(priv);
2983	2993	if (rc < 0) {
2984	2994	dev_err(ds->dev, "Failed to configure MII clocking: %d\n", rc);
2985		− return rc;
	2995	+ goto out_static_config_free;
2986	2996	}
2987	2997	/* On SJA1105, VLAN filtering per se is always enabled in hardware.
2988	2998	* The only thing we can do to disable it is lie about what the 802.1Q
@@ -3003,7 +3013,7 @@ static int sja1105_setup(struct dsa_switch *ds) · 14 unmodified lines
3003	3013

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drivers/net/ethernet/amazon/ena/ena_netdev.c+28−26

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drivers/net/ethernet/atheros/alx/main.c+1−0

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drivers/net/ethernet/broadcom/bnx2.c+1−1

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drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c+3−1

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drivers/net/ethernet/broadcom/bnxt/bnxt.c+117−29

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drivers/net/ethernet/broadcom/bnxt/bnxt.h+10−0

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drivers/net/ethernet/cadence/macb_main.c+3−0

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drivers/net/ethernet/cavium/liquidio/lio_main.c+17−10

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drivers/net/ethernet/cavium/liquidio/lio_vf_main.c+20−7

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drivers/net/ethernet/chelsio/cxgb4/cxgb4.h+0−2

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drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c+35−13

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drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c+2−2

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drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c+3−5

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drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c+5−9

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drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_mqprio.c+6−3

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drivers/net/ethernet/chelsio/cxgb4/sge.c+6−0

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drivers/net/ethernet/chelsio/cxgb4/t4_hw.c+29−17

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drivers/net/ethernet/chelsio/inline_crypto/ch_ktls/chcr_ktls.c+79−1

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drivers/net/ethernet/chelsio/inline_crypto/ch_ktls/chcr_ktls.h+2−0

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drivers/net/ethernet/chelsio/inline_crypto/chtls/chtls_io.c+4−2

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drivers/net/ethernet/ec_bhf.c+3−1

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drivers/net/ethernet/emulex/benet/be_main.c+1−0

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drivers/net/ethernet/freescale/fec_main.c+19−5

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drivers/net/ethernet/freescale/fec_ptp.c+5−3

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drivers/net/ethernet/fujitsu/fmvj18x_cs.c+2−2

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drivers/net/ethernet/google/gve/gve_main.c+12−9

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drivers/net/ethernet/google/gve/gve_tx.c+7−3

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drivers/net/ethernet/hisilicon/hns/hns_ethtool.c+3−3

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drivers/net/ethernet/hisilicon/hns3/hns3_enet.c+51−59

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drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c+23−41

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drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c+3−1

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drivers/net/ethernet/intel/i40e/i40e_txrx.c+6−1

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drivers/net/ethernet/intel/i40e/i40e_xsk.c+6−2

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drivers/net/ethernet/intel/ice/ice.h+5−3

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drivers/net/ethernet/intel/ice/ice_ethtool.c+6−45

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drivers/net/ethernet/intel/ice/ice_hw_autogen.h+1−0

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drivers/net/ethernet/intel/ice/ice_lib.c+22−8

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drivers/net/ethernet/intel/ice/ice_main.c+15−0

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drivers/net/ethernet/intel/ice/ice_txrx.c+13−4

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drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c+13−6

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drivers/net/ethernet/intel/ice/ice_xsk.c+9−2

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drivers/net/ethernet/intel/igb/igb.h+1−1

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drivers/net/ethernet/intel/igb/igb_main.c+32−23

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drivers/net/ethernet/intel/igb/igb_ptp.c+10−13

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drivers/net/ethernet/intel/igc/igc_main.c+5−6

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drivers/net/ethernet/intel/ixgbe/ixgbe_main.c+8−8

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drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c+7−9

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drivers/net/ethernet/intel/ixgbe/ixgbe_xsk.c+8−6

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drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.c+3−0

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drivers/net/ethernet/korina.c+6−6

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drivers/net/ethernet/lantiq_xrx200.c+11−6

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drivers/net/ethernet/marvell/mvpp2/mvpp2.h+22−0

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drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c+45−9

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drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c+4−0

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drivers/net/ethernet/mediatek/mtk_eth_soc.c+52−25

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drivers/net/ethernet/mediatek/mtk_eth_soc.h+22−2

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drivers/net/ethernet/mellanox/mlx4/en_ethtool.c+1−3

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drivers/net/ethernet/mellanox/mlx4/fw.c+3−0

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drivers/net/ethernet/mellanox/mlx4/fw.h+1−0

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drivers/net/ethernet/mellanox/mlx4/main.c+6−0

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drivers/net/ethernet/mellanox/mlx4/port.c+103−4

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drivers/net/ethernet/mellanox/mlx5/core/dev.c+19−0

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drivers/net/ethernet/mellanox/mlx5/core/en/devlink.c+2−0

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drivers/net/ethernet/mellanox/mlx5/core/en/ptp.c+0−1

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drivers/net/ethernet/mellanox/mlx5/core/en/ptp.h+22−0

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drivers/net/ethernet/mellanox/mlx5/core/en/rep/bond.c+2−0

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drivers/net/ethernet/mellanox/mlx5/core/en/rep/neigh.c+6−9

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drivers/net/ethernet/mellanox/mlx5/core/en/rep/tc.c+2−6

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drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_encap.c+31−4

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drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c+0−3

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drivers/net/ethernet/mellanox/mlx5/core/en_arfs.c+1−1

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drivers/net/ethernet/mellanox/mlx5/core/en_fs.c+1−0

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drivers/net/ethernet/mellanox/mlx5/core/en_main.c+81−33

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drivers/net/ethernet/mellanox/mlx5/core/en_tc.c+32−7

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drivers/net/ethernet/mellanox/mlx5/core/en_tc.h+3−0

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drivers/net/ethernet/mellanox/mlx5/core/en_tx.c+3−22

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drivers/net/ethernet/mellanox/mlx5/core/eq.c+4−2

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drivers/net/ethernet/mellanox/mlx5/core/eswitch.c+7−0

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drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c+2−1

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drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads_termtbl.c+26−35

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drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c+3−0

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drivers/net/ethernet/mellanox/mlx5/core/lag_mp.c+6−0

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drivers/net/ethernet/mellanox/mlx5/core/lib/fs_chains.c+1−1

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drivers/net/ethernet/mellanox/mlx5/core/lib/fs_chains.h+5−0

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drivers/net/ethernet/mellanox/mlx5/core/lib/mpfs.c+3−0

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drivers/net/ethernet/mellanox/mlx5/core/lib/mpfs.h+1−4

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drivers/net/ethernet/mellanox/mlx5/core/main.c+7−7

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drivers/net/ethernet/mellanox/mlx5/core/mr.c+1−1

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drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c+17−5

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drivers/net/ethernet/mellanox/mlx5/core/rdma.c+3−0

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drivers/net/ethernet/mellanox/mlx5/core/sf/dev/dev.c+1−0

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drivers/net/ethernet/mellanox/mlx5/core/sf/devlink.c+11−7

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drivers/net/ethernet/mellanox/mlx5/core/steering/dr_fw.c+2−1

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drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v1.c+16−10

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drivers/net/ethernet/mellanox/mlx5/core/steering/mlx5dr.h+5−4

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drivers/net/ethernet/mellanox/mlx5/core/transobj.c+24−6

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drivers/net/ethernet/mellanox/mlx5/core/vport.c+0−2

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drivers/net/ethernet/mellanox/mlxsw/core_thermal.c+4−2

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drivers/net/ethernet/mellanox/mlxsw/reg.h+1−1

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drivers/net/ethernet/mellanox/mlxsw/spectrum_qdisc.c+4−1

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drivers/net/ethernet/microchip/encx24j600.c+1−1

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drivers/net/ethernet/microchip/encx24j600_hw.h+1−1

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drivers/net/ethernet/mscc/ocelot.c+5−0

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drivers/net/ethernet/myricom/myri10ge/myri10ge.c+1−0

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drivers/net/ethernet/pensando/Kconfig+1−0

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drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c+2−0

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drivers/net/ethernet/qlogic/qed/qed_dcbx.c+3−1

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drivers/net/ethernet/qlogic/qla3xxx.c+1−1

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drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c+2−1

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drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c+1−0

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drivers/net/ethernet/qualcomm/rmnet/rmnet_vnd.c+9−9

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drivers/net/ethernet/realtek/r8169_main.c+1−1

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drivers/net/ethernet/renesas/sh_eth.c+1−1

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drivers/net/ethernet/sfc/nic.c+1−0

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drivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c+4−4

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drivers/net/ethernet/stmicro/stmmac/dwmac1000.h+4−4

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drivers/net/ethernet/stmicro/stmmac/stmmac_main.c+25−13

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drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c+2−0

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drivers/net/ethernet/sun/niu.c+20−12

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drivers/net/ethernet/ti/netcp_core.c+2−2

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drivers/net/ethernet/xilinx/ll_temac_main.c+24−3

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drivers/net/hamradio/mkiss.c+1−0

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drivers/net/ieee802154/mrf24j40.c+2−2

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drivers/net/ipa/ipa.h+2−0

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drivers/net/ipa/ipa_mem.c+2−1

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drivers/net/mdio/mdio-octeon.c+0−2

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drivers/net/mdio/mdio-thunder.c+0−1

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drivers/net/mhi/net.c+1−1

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drivers/net/phy/dp83867.c+1−5

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drivers/net/phy/mdio_bus.c+2−1

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drivers/net/usb/cdc_eem.c+2−2

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drivers/net/usb/cdc_ncm.c+1−1

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drivers/net/usb/hso.c+22−23

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drivers/net/usb/lan78xx.c+1−0

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drivers/net/usb/qmi_wwan.c+1−1

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drivers/net/usb/r8152.c+38−6

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drivers/net/usb/smsc75xx.c+9−3

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drivers/net/virtio_net.c+8−12

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drivers/net/vrf.c+2−4

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drivers/net/wireguard/Makefile+1−2

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drivers/net/wireguard/allowedips.c+99−90

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drivers/net/wireguard/allowedips.h+7−7

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drivers/net/wireguard/main.c+16−1

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drivers/net/wireguard/peer.c+20−7

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drivers/net/wireguard/peer.h+3−0

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drivers/net/wireguard/selftest/allowedips.c+79−86

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drivers/net/wireguard/socket.c+1−1

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drivers/net/wireless/ath/ath10k/htt.h+1−0

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drivers/net/wireless/ath/ath10k/htt_rx.c+191−10

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drivers/net/wireless/ath/ath10k/rx_desc.h+13−1

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drivers/net/wireless/ath/ath11k/dp_rx.c+34−0

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drivers/net/wireless/ath/ath11k/dp_rx.h+1−0

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drivers/net/wireless/ath/ath11k/mac.c+6−0

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drivers/net/wireless/ath/ath6kl/debug.c+4−1

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drivers/net/wireless/broadcom/brcm80211/brcmfmac/bcmsdh.c+2−6

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drivers/net/wireless/broadcom/brcm80211/brcmfmac/bus.h+17−2

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drivers/net/wireless/broadcom/brcm80211/brcmfmac/core.c+18−24

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drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c+2−7

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drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.h+0−5

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drivers/net/wireless/broadcom/brcm80211/brcmfmac/usb.c+2−6

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drivers/net/wireless/mac80211_hwsim.c+5−0

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drivers/net/wireless/marvell/libertas/mesh.c+4−29

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drivers/net/wireless/mediatek/mt76/mac80211.c+26−0

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drivers/net/wireless/mediatek/mt76/mt7615/init.c+0−1

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drivers/net/wireless/mediatek/mt76/mt7615/mac.c+3−2

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drivers/net/wireless/mediatek/mt76/mt7615/sdio_mcu.c+12−7

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drivers/net/wireless/mediatek/mt76/mt7615/usb_mcu.c+0−3

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drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.c+4−0

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drivers/net/wireless/mediatek/mt76/mt76x0/pci.c+77−4

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drivers/net/wireless/mediatek/mt76/mt7921/init.c+2−2

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drivers/net/wireless/mediatek/mt76/mt7921/mac.c+3−2

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drivers/net/wireless/mediatek/mt76/mt7921/main.c+1−2

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drivers/net/wireless/mediatek/mt76/mt7921/mcu.c+10−7

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drivers/net/wireless/realtek/rtlwifi/base.c+9−9

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drivers/net/xen-netback/interface.c+6−0

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drivers/nfc/nfcmrvl/fw_dnld.h+1−1

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drivers/nfc/nfcmrvl/i2c.c+1−1

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drivers/nfc/nfcmrvl/nfcmrvl.h+1−1

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drivers/nfc/nfcmrvl/spi.c+1−1

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drivers/nfc/nfcmrvl/uart.c+1−1

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drivers/nfc/nfcmrvl/usb.c+1−1

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drivers/nvme/host/Kconfig+2−1

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drivers/nvme/host/core.c+5−2

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drivers/nvme/host/fabrics.c+5−0

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drivers/nvme/host/fc.c+29−8

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drivers/nvme/host/multipath.c+29−26

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drivers/nvme/host/nvme.h+6−2

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drivers/nvme/host/rdma.c+3−2

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drivers/nvme/host/tcp.c+3−2

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drivers/nvme/target/admin-cmd.c+2−5

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drivers/nvme/target/core.c+28−22

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drivers/nvme/target/discovery.c+1−1

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drivers/nvme/target/fabrics-cmd.c+3−3

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drivers/nvme/target/io-cmd-bdev.c+1−1

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drivers/nvme/target/io-cmd-file.c+5−3

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drivers/nvme/target/loop.c+11−4

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drivers/nvme/target/nvmet.h+7−1

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drivers/nvme/target/passthru.c+1−1

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drivers/nvme/target/rdma.c+2−2

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drivers/nvme/target/tcp.c+1−1

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drivers/pci/controller/dwc/Makefile+2−1

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drivers/pci/controller/dwc/pcie-tegra194-acpi.c+108−0

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drivers/pci/controller/dwc/pcie-tegra194.c+18−120

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drivers/pci/controller/pci-aardvark.c+40−9

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drivers/pci/of.c+9−0

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drivers/pci/probe.c+2−1

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drivers/pci/quirks.c+92−1

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drivers/phy/broadcom/phy-brcm-usb-init.h+2−2

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drivers/phy/cadence/phy-cadence-sierra.c+1−0

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drivers/phy/mediatek/phy-mtk-tphy.c+2−0

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drivers/phy/microchip/sparx5_serdes.c+4−0

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drivers/phy/ralink/phy-mt7621-pci.c+1−1

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drivers/phy/ti/phy-j721e-wiz.c+1−0

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drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c+2−2

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drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c+2−2

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drivers/pinctrl/aspeed/pinctrl-aspeed.c+2−1

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drivers/pinctrl/aspeed/pinmux-aspeed.c+2−1

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drivers/pinctrl/qcom/Kconfig+1−1

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drivers/pinctrl/qcom/pinctrl-sdx55.c+9−9

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drivers/pinctrl/ralink/pinctrl-rt2880.c+1−1

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drivers/platform/mellanox/mlxbf-tmfifo.c+10−1

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drivers/platform/mellanox/mlxreg-hotplug.c+2−2

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drivers/platform/surface/aggregator/controller.c+2−3

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drivers/platform/surface/surface_aggregator_registry.c+5−2

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drivers/platform/surface/surface_dtx.c+2−7

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drivers/platform/x86/Kconfig+1−1

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drivers/platform/x86/dell/dell-smbios-wmi.c+2−1

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drivers/platform/x86/gigabyte-wmi.c+14−24

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drivers/platform/x86/hp-wireless.c+2−0

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drivers/platform/x86/hp_accel.c+21−1

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drivers/platform/x86/ideapad-laptop.c+7−6

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drivers/platform/x86/intel_int0002_vgpio.c+56−24

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drivers/platform/x86/intel_punit_ipc.c+1−0

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drivers/platform/x86/thinkpad_acpi.c+1−0

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drivers/platform/x86/touchscreen_dmi.c+43−0

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drivers/ptp/ptp_clock.c+3−3

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drivers/ptp/ptp_ocp.c+3−1

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drivers/rapidio/rio_cm.c+8−9

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drivers/regulator/Kconfig+1−1

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drivers/regulator/atc260x-regulator.c+10−9

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drivers/regulator/bd718x7-regulator.c+1−1

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drivers/regulator/core.c+6−0

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drivers/regulator/cros-ec-regulator.c+2−1

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drivers/regulator/da9121-regulator.c+7−3

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drivers/regulator/fan53555.c+1−2

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drivers/regulator/fan53880.c+3−0

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drivers/regulator/fixed.c+6−1

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drivers/regulator/helpers.c+1−1

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drivers/regulator/hi6421v600-regulator.c+2−2

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drivers/regulator/hi655x-regulator.c+1−1

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drivers/regulator/max77620-regulator.c+11−6

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drivers/regulator/mt6315-regulator.c+1−1

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drivers/regulator/rt4801-regulator.c+2−2

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drivers/regulator/rtmv20-regulator.c+42−2

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drivers/regulator/scmi-regulator.c+1−1

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drivers/s390/block/dasd_diag.c+7−1

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drivers/s390/block/dasd_fba.c+7−1

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drivers/s390/block/dasd_int.h+0−1

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drivers/s390/cio/vfio_ccw_cp.c+4−0

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drivers/s390/cio/vfio_ccw_drv.c+10−2

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drivers/s390/cio/vfio_ccw_fsm.c+1−0

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drivers/s390/cio/vfio_ccw_ops.c+0−2

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drivers/s390/crypto/ap_queue.c+9−2

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drivers/scsi/BusLogic.c+3−3

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drivers/scsi/BusLogic.h+1−1

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drivers/scsi/aic7xxx/aicasm/aicasm_gram.y+0−1

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drivers/scsi/aic7xxx/aicasm/aicasm_symbol.h+1−1

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drivers/scsi/aic7xxx/scsi_message.h+11−0

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drivers/scsi/bnx2fc/bnx2fc_io.c+1−0

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drivers/scsi/hisi_sas/hisi_sas_v3_hw.c+4−4

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drivers/scsi/hosts.c+26−21

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drivers/scsi/libsas/sas_port.c+2−2

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drivers/scsi/lpfc/lpfc_sli.c+1−3

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drivers/scsi/pm8001/pm8001_hwi.c+6−4

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drivers/scsi/pm8001/pm8001_init.c+1−1

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drivers/scsi/pm8001/pm8001_sas.c+6−1

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drivers/scsi/pm8001/pm80xx_hwi.c+6−6

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drivers/scsi/qedf/qedf_main.c+12−12

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drivers/scsi/qla2xxx/qla_nx.c+2−1

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drivers/scsi/qla2xxx/qla_target.c+2−0

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drivers/scsi/scsi_devinfo.c+1−0

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drivers/scsi/ufs/ufs-hisi.c+9−6

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drivers/scsi/ufs/ufs-mediatek.c+18−1

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drivers/scsi/ufs/ufshcd.c+4−1

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drivers/scsi/vmw_pvscsi.c+7−1

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drivers/soc/amlogic/meson-clk-measure.c+1−3

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drivers/soundwire/qcom.c+10−2

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drivers/spi/Kconfig+1−1

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drivers/spi/spi-bcm2835.c+8−2

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drivers/spi/spi-bitbang.c+14−4

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drivers/spi/spi-fsl-dspi.c+3−1

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drivers/spi/spi-fsl-spi.c+4−0

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drivers/spi/spi-omap-uwire.c+8−1

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drivers/spi/spi-omap2-mcspi.c+20−13

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drivers/spi/spi-pxa2xx.c+8−1

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drivers/spi/spi-sc18is602.c+8−1

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drivers/spi/spi-sprd.c+1−0

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drivers/spi/spi-stm32-qspi.c+4−1

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drivers/spi/spi-zynq-qspi.c+8−8

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drivers/spi/spi.c+38−13

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drivers/staging/emxx_udc/emxx_udc.c+2−2

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drivers/staging/iio/cdc/ad7746.c+0−1

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drivers/staging/ralink-gdma/ralink-gdma.c+0−2

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drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c+16−13

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drivers/staging/rtl8723bs/os_dep/ioctl_linux.c+12−9

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drivers/target/target_core_iblock.c+2−2

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drivers/target/target_core_transport.c+2−4

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drivers/target/target_core_user.c+7−5

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drivers/tee/amdtee/amdtee_private.h+13−0

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drivers/tee/amdtee/call.c+84−10

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drivers/tee/amdtee/core.c+9−6

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drivers/tee/optee/call.c+4−2

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drivers/tee/optee/optee_msg.h+4−2

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drivers/thermal/intel/int340x_thermal/int340x_thermal_zone.c+4−0

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drivers/thermal/intel/therm_throt.c+11−4

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drivers/thermal/intel/x86_pkg_temp_thermal.c+1−1

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drivers/thermal/qcom/qcom-spmi-adc-tm5.c+1−1

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drivers/thermal/ti-soc-thermal/ti-bandgap.c+1−1

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drivers/thunderbolt/dma_port.c+6−5

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drivers/thunderbolt/usb4.c+5−4

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drivers/tty/serial/8250/8250.h+17−15

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drivers/tty/serial/8250/8250_aspeed_vuart.c+1−0

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drivers/tty/serial/8250/8250_dw.c+1−0

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drivers/tty/serial/8250/8250_exar.c+5−1

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drivers/tty/serial/8250/8250_pci.c+35−12

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drivers/tty/serial/8250/8250_port.c+12−0

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drivers/tty/serial/max310x.c+2−0

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drivers/tty/serial/mvebu-uart.c+0−3

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drivers/tty/serial/rp2.c+17−35

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drivers/tty/serial/serial-tegra.c+1−1

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drivers/tty/serial/serial_core.c+5−3

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drivers/tty/serial/sh-sci.c+2−2

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drivers/tty/vt/vt.c+1−1

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drivers/tty/vt/vt_ioctl.c+47−10

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drivers/uio/uio_hv_generic.c+9−3

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drivers/uio/uio_pci_generic.c+1−1

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drivers/usb/cdns3/cdns3-gadget.c+6−6

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drivers/usb/cdns3/cdnsp-gadget.c+7−7

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drivers/usb/cdns3/cdnsp-ring.c+4−3

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drivers/usb/chipidea/udc.c+1−0

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drivers/usb/chipidea/usbmisc_imx.c+14−2

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drivers/usb/class/cdc-wdm.c+22−8

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drivers/usb/core/devio.c+8−3

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drivers/usb/core/hub.c+10−3

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drivers/usb/dwc2/core.h+2−0

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drivers/usb/dwc2/gadget.c+2−1

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drivers/usb/dwc2/platform.c+0−4

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drivers/usb/dwc3/core.c+1−7

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drivers/usb/dwc3/core.h+4−3

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drivers/usb/dwc3/debug.h+7−4

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drivers/usb/dwc3/debugfs.c+2−19

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drivers/usb/dwc3/dwc3-imx8mp.c+2−1

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drivers/usb/dwc3/dwc3-meson-g12a.c+10−3

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drivers/usb/dwc3/dwc3-omap.c+5−0

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drivers/usb/dwc3/dwc3-pci.c+1−0

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drivers/usb/dwc3/ep0.c+3−0

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drivers/usb/dwc3/gadget.c+29−15

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drivers/usb/gadget/config.c+8−0

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drivers/usb/gadget/function/f_ecm.c+1−1

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drivers/usb/gadget/function/f_eem.c+3−3

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drivers/usb/gadget/function/f_fs.c+3−0

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drivers/usb/gadget/function/f_hid.c+2−1

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drivers/usb/gadget/function/f_loopback.c+1−1

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drivers/usb/gadget/function/f_ncm.c+5−5

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drivers/usb/gadget/function/f_printer.c+2−1

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drivers/usb/gadget/function/f_rndis.c+1−1

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drivers/usb/gadget/function/f_serial.c+1−1

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drivers/usb/gadget/function/f_sourcesink.c+2−1

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drivers/usb/gadget/function/f_subset.c+1−1

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drivers/usb/gadget/function/f_tcm.c+2−1

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drivers/usb/gadget/udc/renesas_usb3.c+3−2

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drivers/usb/host/fotg210-hcd.c+2−2

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drivers/usb/host/xhci-ext-caps.h+3−2

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drivers/usb/host/xhci-pci.c+12−3

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drivers/usb/host/xhci-ring.c+18−12

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drivers/usb/host/xhci.c+3−3

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drivers/usb/host/xhci.h+1−0

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drivers/usb/misc/brcmstb-usb-pinmap.c+2−0

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drivers/usb/misc/trancevibrator.c+2−2

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drivers/usb/misc/uss720.c+1−0

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drivers/usb/musb/mediatek.c+1−1

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drivers/usb/musb/musb_core.c+1−2

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