tty: 8250: Add 64byte UART support for FSL platforms

Some of FSL SoCs like T1040 has new version of UART controller which can support 64byte FiFo. To enable 64 byte support, following needs to be done: -FCR[EN64] needs to be programmed to 1 to enable it. -Also, when FCR[EN64]==1, RTL bits to be used as below to define various Receive Trigger Levels: -FCR[RTL] = 00 1 byte -FCR[RTL] = 01 16 bytes -FCR[RTL] = 10 32 bytes -FCR[RTL] = 11 56 bytes -tx_loadsz is set to 63-bytes instead of 64-bytes to implement workaround of errata A-008006 which states that tx_loadsz should be configured less than Maximum supported fifo bytes

Vijay Rai committed 11 years ago

Commit fddceb81 parent 5fafc893 files · +26 −3Browse files

Showing the changes to include/uapi/linux (2 of 3 files). Show all

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include/uapi/linux/serial_core.h +2 −1
include/uapi/linux/serial_reg.h +2 −1

include/uapi/linux/serial_core.h+2−1

@@ -55,7 +55,8 @@ · 54 unmodified lines
55	55	#define PORT_ALTR_16550_F64 27 /* Altera 16550 UART with 64 FIFOs */
56	56	#define PORT_ALTR_16550_F128 28 /* Altera 16550 UART with 128 FIFOs */
57	57	#define PORT_RT2880 29 /* Ralink RT2880 internal UART */
58		−#define PORT_MAX_8250 29 /* max port ID */
	58	+#define PORT_16550A_FSL64 30 /* Freescale 16550 UART with 64 FIFOs */
	59	+#define PORT_MAX_8250 30 /* max port ID */
59	60
60	61	/*
61	62	* ARM specific type numbers. These are not currently guaranteed

include/uapi/linux/serial_reg.h+2−1

@@ -86,7 +86,8 @@ · 85 unmodified lines
86	86	#define UART_FCR6_T_TRIGGER_8 0x10 /* Mask for transmit trigger set at 8 */
87	87	#define UART_FCR6_T_TRIGGER_24 0x20 /* Mask for transmit trigger set at 24 */
88	88	#define UART_FCR6_T_TRIGGER_30 0x30 /* Mask for transmit trigger set at 30 */
89		−#define UART_FCR7_64BYTE 0x20 /* Go into 64 byte mode (TI16C750) */
	89	+#define UART_FCR7_64BYTE 0x20 /* Go into 64 byte mode (TI16C750 and
	90	+ some Freescale UARTs) */
90	91
91	92	#define UART_FCR_R_TRIG_SHIFT 6
92	93	#define UART_FCR_R_TRIG_BITS(x) \