History

Merge tag 'mailbox-v5.3' of git://git.linaro.org/landing-teams/working/fujitsu/integration

Pull mailbox updates from Jassi Brar: - stm32: race fix by adding a spinlock - mhu: trim included headers - omap: add support for K3 SoCs - imx: Irq disable fix - bcm: tidy up extracting driver data - tegra: make resume 'noirq' - api: fix error handling * tag 'mailbox-v5.3' of git://git.linaro.org/landing-teams/working/fujitsu/integration: mailbox: handle failed named mailbox channel request mailbox: tegra: avoid resume NULL mailboxes mailbox: tegra: hsp: add noirq resume mailbox: bcm-flexrm-mailbox: using dev_get_drvdata directly mailbox: imx: Clear GIEn bit at shutdown mailbox: omap: Add support for TI K3 SoCs dt-bindings: mailbox: omap: Update bindings for TI K3 SoCs mailbox: arm_mhu: reorder header inclusion and drop unneeded ones mailbox: stm32_ipcc: add spinlock to fix channels concurrent access

Linus Torvalds committed 7 years ago

Commit fde7dc62 parents a1240cf 25777e510 files · +134 −58Browse files

Unified · Split

10 files
  1. Documentation/devicetree/bindings/mailbox/omap-mailbox.txt +50 −9
  2. drivers/mailbox/Kconfig +1 −1
  3. drivers/mailbox/arm_mhu.c +4 −7
  4. drivers/mailbox/bcm-flexrm-mailbox.c +2 −4
  5. drivers/mailbox/imx-mailbox.c +2 −2
  6. drivers/mailbox/mailbox.c +4 −2
  7. drivers/mailbox/omap-mailbox.c +26 −17
  8. drivers/mailbox/stm32-ipcc.c +27 −10
  9. drivers/mailbox/tegra-hsp.c +15 −5
  10. include/linux/omap-mailbox.h +3 −1
Documentation/devicetree/bindings/mailbox/omap-mailbox.txt+50−9
@@ -1,4 +1,4 @@
1OMAP2+ Mailbox Driver1OMAP2+ and K3 Mailbox
2=====================2=====================
3 3
4The OMAP mailbox hardware facilitates communication between different processors4The OMAP mailbox hardware facilitates communication between different processors
@@ -7,7 +7,7 @@ various processor subsystems and is connected on an interconnect bus. The · 2 unmodified lines
7communication is achieved through a set of registers for message storage and7communication is achieved through a set of registers for message storage and
8interrupt configuration registers.8interrupt configuration registers.
9 9
10Each mailbox IP block has a certain number of h/w fifo queues and output10Each mailbox IP block/cluster has a certain number of h/w fifo queues and output
11interrupt lines. An output interrupt line is routed to an interrupt controller11interrupt lines. An output interrupt line is routed to an interrupt controller
12within a processor subsystem, and there can be more than one line going to a12within a processor subsystem, and there can be more than one line going to a
13specific processor's interrupt controller. The interrupt line connections are13specific processor's interrupt controller. The interrupt line connections are
@@ -23,12 +23,16 @@ All the current OMAP SoCs except for the newest DRA7xx SoC has a single IP · 9 unmodified lines
23instance. DRA7xx has multiple instances with different number of h/w fifo queues23instance. DRA7xx has multiple instances with different number of h/w fifo queues
24and interrupt lines between different instances. The interrupt lines can also be24and interrupt lines between different instances. The interrupt lines can also be
25routed to different processor sub-systems on DRA7xx as they are routed through25routed to different processor sub-systems on DRA7xx as they are routed through
26the Crossbar, a kind of interrupt router/multiplexer.26the Crossbar, a kind of interrupt router/multiplexer. The K3 AM65x and J721E
27SoCs has each of these instances form a cluster and combine multiple clusters
28into a single IP block present within the Main NavSS. The interrupt lines from
29all these clusters are multiplexed and routed to different processor subsystems
30over a limited number of common interrupt output lines of an Interrupt Router.
27 31
28Mailbox Device Node:32Mailbox Device Node:
29====================33====================
30A Mailbox device node is used to represent a Mailbox IP instance within a SoC.34A Mailbox device node is used to represent a Mailbox IP instance/cluster within
31The sub-mailboxes are represented as child nodes of this parent node.35a SoC. The sub-mailboxes are represented as child nodes of this parent node.
32 36
33Required properties:37Required properties:
34--------------------38--------------------
@@ -37,12 +41,12 @@ Required properties: · 2 unmodified lines
37 "ti,omap3-mailbox" for OMAP3430, OMAP3630 SoCs41 "ti,omap3-mailbox" for OMAP3430, OMAP3630 SoCs
38 "ti,omap4-mailbox" for OMAP44xx, OMAP54xx, AM33xx,42 "ti,omap4-mailbox" for OMAP44xx, OMAP54xx, AM33xx,
39 AM43xx and DRA7xx SoCs43 AM43xx and DRA7xx SoCs
44 "ti,am654-mailbox" for K3 AM65x and J721E SoCs
40- reg: Contains the mailbox register address range (base45- reg: Contains the mailbox register address range (base
41 address and length)46 address and length)
42- interrupts: Contains the interrupt information for the mailbox47- interrupts: Contains the interrupt information for the mailbox
43 device. The format is dependent on which interrupt48 device. The format is dependent on which interrupt
44 controller the OMAP device uses49 controller the Mailbox device uses
45- ti,hwmods: Name of the hwmod associated with the mailbox
46- #mbox-cells: Common mailbox binding property to identify the number50- #mbox-cells: Common mailbox binding property to identify the number
47 of cells required for the mailbox specifier. Should be51 of cells required for the mailbox specifier. Should be
48 152 1
@@ -50,6 +54,23 @@ Required properties: · 1 unmodified line
50 device can interrupt54 device can interrupt
51- ti,mbox-num-fifos: Number of h/w fifo queues within the mailbox IP block55- ti,mbox-num-fifos: Number of h/w fifo queues within the mailbox IP block
52 56
57SoC-specific Required properties:
58---------------------------------
59The following are mandatory properties for the OMAP architecture based SoCs
60only:
61- ti,hwmods: Name of the hwmod associated with the mailbox. This
62 should be defined in the mailbox node only if the node
63 is not defined as a child node of a corresponding sysc
64 interconnect node.
65
66The following are mandatory properties for the K3 AM65x and J721E SoCs only:
67- interrupt-parent: Should contain a phandle to the TI-SCI interrupt
68 controller node that is used to dynamically program
69 the interrupt routes between the IP and the main GIC
70 controllers. See the following binding for additional
71 details,
72 Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.txt
73
53Child Nodes:74Child Nodes:
54============75============
55A child node is used for representing the actual sub-mailbox device that is76A child node is used for representing the actual sub-mailbox device that is
@@ -98,7 +119,7 @@ to be used by the client user. · 42 unmodified lines
98Example:119Example:
99--------120--------
100 121
101/* OMAP4 */1221. /* OMAP4 */
102mailbox: mailbox@4a0f4000 {123mailbox: mailbox@4a0f4000 {
103 compatible = "ti,omap4-mailbox";124 compatible = "ti,omap4-mailbox";
104 reg = <0x4a0f4000 0x200>;125 reg = <0x4a0f4000 0x200>;
@@ -123,7 +144,7 @@ dsp { · 18 unmodified lines
123 ...144 ...
124};145};
125 146
126/* AM33xx */1472. /* AM33xx */
127mailbox: mailbox@480c8000 {148mailbox: mailbox@480c8000 {
128 compatible = "ti,omap4-mailbox";149 compatible = "ti,omap4-mailbox";
129 reg = <0x480C8000 0x200>;150 reg = <0x480C8000 0x200>;
@@ -137,3 +158,23 @@ mailbox: mailbox@480c8000 { · 7 unmodified lines
137 ti,mbox-rx = <0 0 3>;158 ti,mbox-rx = <0 0 3>;
138 };159 };
139};160};
161
1623. /* AM65x */
163&cbass_main {
164 cbass_main_navss: interconnect0 {
165 mailbox0_cluster0: mailbox@31f80000 {
166 compatible = "ti,am654-mailbox";
167 reg = <0x00 0x31f80000 0x00 0x200>;
168 #mbox-cells = <1>;
169 ti,mbox-num-users = <4>;
170 ti,mbox-num-fifos = <16>;
171 interrupt-parent = <&intr_main_navss>;
172 interrupts = <164 0>;
173
174 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
175 ti,mbox-tx = <1 0 0>;
176 ti,mbox-rx = <0 0 0>;
177 };
178 };
179 };
180};
drivers/mailbox/Kconfig+1−1
@@ -54,7 +54,7 @@ config ARMADA_37XX_RWTM_MBOX · 53 unmodified lines
54 54
55config OMAP2PLUS_MBOX55config OMAP2PLUS_MBOX
56 tristate "OMAP2+ Mailbox framework support"56 tristate "OMAP2+ Mailbox framework support"
57 depends on ARCH_OMAP2PLUS57 depends on ARCH_OMAP2PLUS || ARCH_K3
58 help58 help
59 Mailbox implementation for OMAP family chips with hardware for59 Mailbox implementation for OMAP family chips with hardware for
60 interprocessor communication involving DSP, IVA1.0 and IVA2 in60 interprocessor communication involving DSP, IVA1.0 and IVA2 in
drivers/mailbox/arm_mhu.c+4−7
@@ -5,16 +5,13 @@ · 4 unmodified lines
5 * Author: Jassi Brar <jaswinder.singh@linaro.org>5 * Author: Jassi Brar <jaswinder.singh@linaro.org>
6 */6 */
7 7
8#include <linux/interrupt.h>8#include <linux/amba/bus.h>
9#include <linux/spinlock.h>9#include <linux/device.h>
10#include <linux/mutex.h>
11#include <linux/delay.h>
12#include <linux/slab.h>
13#include <linux/err.h>10#include <linux/err.h>
11#include <linux/interrupt.h>
14#include <linux/io.h>12#include <linux/io.h>
15#include <linux/module.h>
16#include <linux/amba/bus.h>
17#include <linux/mailbox_controller.h>13#include <linux/mailbox_controller.h>
14#include <linux/module.h>
18 15
19#define INTR_STAT_OFS 0x016#define INTR_STAT_OFS 0x0
20#define INTR_SET_OFS 0x817#define INTR_SET_OFS 0x8
drivers/mailbox/bcm-flexrm-mailbox.c+2−4
@@ -1163,8 +1163,7 @@ static int flexrm_process_completions(struct flexrm_ring *ring) · 1162 unmodified lines
1163 1163
1164static int flexrm_debugfs_conf_show(struct seq_file *file, void *offset)1164static int flexrm_debugfs_conf_show(struct seq_file *file, void *offset)
1165{1165{
1166 struct platform_device *pdev = to_platform_device(file->private);1166 struct flexrm_mbox *mbox = dev_get_drvdata(file->private);
1167 struct flexrm_mbox *mbox = platform_get_drvdata(pdev);
1168 1167
1169 /* Write config in file */1168 /* Write config in file */
1170 flexrm_write_config_in_seqfile(mbox, file);1169 flexrm_write_config_in_seqfile(mbox, file);
@@ -1174,8 +1173,7 @@ static int flexrm_debugfs_conf_show(struct seq_file *file, void *offset) · 3 unmodified lines
1174 1173
1175static int flexrm_debugfs_stats_show(struct seq_file *file, void *offset)1174static int flexrm_debugfs_stats_show(struct seq_file *file, void *offset)
1176{1175{
1177 struct platform_device *pdev = to_platform_device(file->private);1176 struct flexrm_mbox *mbox = dev_get_drvdata(file->private);
1178 struct flexrm_mbox *mbox = platform_get_drvdata(pdev);
1179 1177
1180 /* Write stats in file */1178 /* Write stats in file */
1181 flexrm_write_stats_in_seqfile(mbox, file);1179 flexrm_write_stats_in_seqfile(mbox, file);
drivers/mailbox/imx-mailbox.c+2−2
@@ -217,8 +217,8 @@ static void imx_mu_shutdown(struct mbox_chan *chan) · 216 unmodified lines
217 if (cp->type == IMX_MU_TYPE_TXDB)217 if (cp->type == IMX_MU_TYPE_TXDB)
218 tasklet_kill(&cp->txdb_tasklet);218 tasklet_kill(&cp->txdb_tasklet);
219 219
220 imx_mu_xcr_rmw(priv, 0,220 imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx) |
221 IMX_MU_xCR_TIEn(cp->idx) | IMX_MU_xCR_RIEn(cp->idx));221 IMX_MU_xCR_RIEn(cp->idx) | IMX_MU_xCR_GIEn(cp->idx));
222 222
223 free_irq(priv->irq, chan);223 free_irq(priv->irq, chan);
224}224}
drivers/mailbox/mailbox.c+4−2
@@ -418,11 +418,13 @@ struct mbox_chan *mbox_request_channel_byname(struct mbox_client *cl, · 417 unmodified lines
418 418
419 of_property_for_each_string(np, "mbox-names", prop, mbox_name) {419 of_property_for_each_string(np, "mbox-names", prop, mbox_name) {
420 if (!strncmp(name, mbox_name, strlen(name)))420 if (!strncmp(name, mbox_name, strlen(name)))
421 break;421 return mbox_request_channel(cl, index);
422 index++;422 index++;
423 }423 }
424 424
425 return mbox_request_channel(cl, index);425 dev_err(cl->dev, "%s() could not locate channel named \"%s\"\n",
426 __func__, name);
427 return ERR_PTR(-EINVAL);
426}428}
427EXPORT_SYMBOL_GPL(mbox_request_channel_byname);429EXPORT_SYMBOL_GPL(mbox_request_channel_byname);
428 430
drivers/mailbox/omap-mailbox.c+26−17
@@ -3,7 +3,7 @@ · 2 unmodified lines
3 * OMAP mailbox driver3 * OMAP mailbox driver
4 *4 *
5 * Copyright (C) 2006-2009 Nokia Corporation. All rights reserved.5 * Copyright (C) 2006-2009 Nokia Corporation. All rights reserved.
6 * Copyright (C) 2013-2016 Texas Instruments Incorporated - http://www.ti.com6 * Copyright (C) 2013-2019 Texas Instruments Incorporated - http://www.ti.com
7 *7 *
8 * Contact: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>8 * Contact: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
9 * Suman Anna <s-anna@ti.com>9 * Suman Anna <s-anna@ti.com>
@@ -141,14 +141,14 @@ void mbox_write_reg(struct omap_mbox_device *mdev, u32 val, size_t ofs) · 131 unmodified lines
141}141}
142 142
143/* Mailbox FIFO handle functions */143/* Mailbox FIFO handle functions */
144static mbox_msg_t mbox_fifo_read(struct omap_mbox *mbox)144static u32 mbox_fifo_read(struct omap_mbox *mbox)
145{145{
146 struct omap_mbox_fifo *fifo = &mbox->rx_fifo;146 struct omap_mbox_fifo *fifo = &mbox->rx_fifo;
147 147
148 return (mbox_msg_t)mbox_read_reg(mbox->parent, fifo->msg);148 return mbox_read_reg(mbox->parent, fifo->msg);
149}149}
150 150
151static void mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)151static void mbox_fifo_write(struct omap_mbox *mbox, u32 msg)
152{152{
153 struct omap_mbox_fifo *fifo = &mbox->tx_fifo;153 struct omap_mbox_fifo *fifo = &mbox->tx_fifo;
154 154
@@ -256,14 +256,16 @@ static void mbox_rx_work(struct work_struct *work) · 101 unmodified lines
256{256{
257 struct omap_mbox_queue *mq =257 struct omap_mbox_queue *mq =
258 container_of(work, struct omap_mbox_queue, work);258 container_of(work, struct omap_mbox_queue, work);
259 mbox_msg_t msg;259 mbox_msg_t data;
260 u32 msg;
260 int len;261 int len;
261 262
262 while (kfifo_len(&mq->fifo) >= sizeof(msg)) {263 while (kfifo_len(&mq->fifo) >= sizeof(msg)) {
263 len = kfifo_out(&mq->fifo, (unsigned char *)&msg, sizeof(msg));264 len = kfifo_out(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
264 WARN_ON(len != sizeof(msg));265 WARN_ON(len != sizeof(msg));
266 data = msg;
265 267
266 mbox_chan_received_data(mq->mbox->chan, (void *)msg);268 mbox_chan_received_data(mq->mbox->chan, (void *)data);
267 spin_lock_irq(&mq->lock);269 spin_lock_irq(&mq->lock);
268 if (mq->full) {270 if (mq->full) {
269 mq->full = false;271 mq->full = false;
@@ -286,7 +288,7 @@ static void __mbox_tx_interrupt(struct omap_mbox *mbox) · 16 unmodified lines
286static void __mbox_rx_interrupt(struct omap_mbox *mbox)288static void __mbox_rx_interrupt(struct omap_mbox *mbox)
287{289{
288 struct omap_mbox_queue *mq = mbox->rxq;290 struct omap_mbox_queue *mq = mbox->rxq;
289 mbox_msg_t msg;291 u32 msg;
290 int len;292 int len;
291 293
292 while (!mbox_fifo_empty(mbox)) {294 while (!mbox_fifo_empty(mbox)) {
@@ -540,13 +542,13 @@ static void omap_mbox_chan_shutdown(struct mbox_chan *chan) · 247 unmodified lines
540 mutex_unlock(&mdev->cfg_lock);542 mutex_unlock(&mdev->cfg_lock);
541}543}
542 544
543static int omap_mbox_chan_send_noirq(struct omap_mbox *mbox, void *data)545static int omap_mbox_chan_send_noirq(struct omap_mbox *mbox, u32 msg)
544{546{
545 int ret = -EBUSY;547 int ret = -EBUSY;
546 548
547 if (!mbox_fifo_full(mbox)) {549 if (!mbox_fifo_full(mbox)) {
548 _omap_mbox_enable_irq(mbox, IRQ_RX);550 _omap_mbox_enable_irq(mbox, IRQ_RX);
549 mbox_fifo_write(mbox, (mbox_msg_t)data);551 mbox_fifo_write(mbox, msg);
550 ret = 0;552 ret = 0;
551 _omap_mbox_disable_irq(mbox, IRQ_RX);553 _omap_mbox_disable_irq(mbox, IRQ_RX);
552 554
@@ -558,12 +560,12 @@ static int omap_mbox_chan_send_noirq(struct omap_mbox *mbox, void *data) · 5 unmodified lines
558 return ret;560 return ret;
559}561}
560 562
561static int omap_mbox_chan_send(struct omap_mbox *mbox, void *data)563static int omap_mbox_chan_send(struct omap_mbox *mbox, u32 msg)
562{564{
563 int ret = -EBUSY;565 int ret = -EBUSY;
564 566
565 if (!mbox_fifo_full(mbox)) {567 if (!mbox_fifo_full(mbox)) {
566 mbox_fifo_write(mbox, (mbox_msg_t)data);568 mbox_fifo_write(mbox, msg);
567 ret = 0;569 ret = 0;
568 }570 }
569 571
@@ -576,14 +578,15 @@ static int omap_mbox_chan_send_data(struct mbox_chan *chan, void *data) · 6 unmodified lines
576{578{
577 struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan);579 struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan);
578 int ret;580 int ret;
581 u32 msg = omap_mbox_message(data);
579 582
580 if (!mbox)583 if (!mbox)
581 return -EINVAL;584 return -EINVAL;
582 585
583 if (mbox->send_no_irq)586 if (mbox->send_no_irq)
584 ret = omap_mbox_chan_send_noirq(mbox, data);587 ret = omap_mbox_chan_send_noirq(mbox, msg);
585 else588 else
586 ret = omap_mbox_chan_send(mbox, data);589 ret = omap_mbox_chan_send(mbox, msg);
587 590
588 return ret;591 return ret;
589}592}
@@ -656,6 +659,10 @@ static const struct of_device_id omap_mailbox_of_match[] = { · 66 unmodified lines
656 .compatible = "ti,omap4-mailbox",659 .compatible = "ti,omap4-mailbox",
657 .data = &omap4_data,660 .data = &omap4_data,
658 },661 },
662 {
663 .compatible = "ti,am654-mailbox",
664 .data = &omap4_data,
665 },
659 {666 {
660 /* end */667 /* end */
661 },668 },
@@ -830,7 +837,10 @@ static int omap_mbox_probe(struct platform_device *pdev) · 168 unmodified lines
830 mdev->intr_type = intr_type;837 mdev->intr_type = intr_type;
831 mdev->mboxes = list;838 mdev->mboxes = list;
832 839
833 /* OMAP does not have a Tx-Done IRQ, but rather a Tx-Ready IRQ */840 /*
841 * OMAP/K3 Mailbox IP does not have a Tx-Done IRQ, but rather a Tx-Ready
842 * IRQ and is needed to run the Tx state machine
843 */
834 mdev->controller.txdone_irq = true;844 mdev->controller.txdone_irq = true;
835 mdev->controller.dev = mdev->dev;845 mdev->controller.dev = mdev->dev;
836 mdev->controller.ops = &omap_mbox_chan_ops;846 mdev->controller.ops = &omap_mbox_chan_ops;
@@ -899,9 +909,8 @@ static int __init omap_mbox_init(void) · 62 unmodified lines
899 return err;909 return err;
900 910
901 /* kfifo size sanity check: alignment and minimal size */911 /* kfifo size sanity check: alignment and minimal size */
902 mbox_kfifo_size = ALIGN(mbox_kfifo_size, sizeof(mbox_msg_t));912 mbox_kfifo_size = ALIGN(mbox_kfifo_size, sizeof(u32));
903 mbox_kfifo_size = max_t(unsigned int, mbox_kfifo_size,913 mbox_kfifo_size = max_t(unsigned int, mbox_kfifo_size, sizeof(u32));
904 sizeof(mbox_msg_t));
905 914
906 err = platform_driver_register(&omap_mbox_driver);915 err = platform_driver_register(&omap_mbox_driver);
907 if (err)916 if (err)
drivers/mailbox/stm32-ipcc.c+27−10
@@ -50,6 +50,7 @@ struct stm32_ipcc { · 49 unmodified lines
50 void __iomem *reg_base;50 void __iomem *reg_base;
51 void __iomem *reg_proc;51 void __iomem *reg_proc;
52 struct clk *clk;52 struct clk *clk;
53 spinlock_t lock; /* protect access to IPCC registers */
53 int irqs[IPCC_IRQ_NUM];54 int irqs[IPCC_IRQ_NUM];
54 int wkp;55 int wkp;
55 u32 proc_id;56 u32 proc_id;
@@ -58,14 +59,24 @@ struct stm32_ipcc { · 2 unmodified lines
58 u32 xmr;59 u32 xmr;
59};60};
60 61
61static inline void stm32_ipcc_set_bits(void __iomem *reg, u32 mask)62static inline void stm32_ipcc_set_bits(spinlock_t *lock, void __iomem *reg,
63 u32 mask)
62{64{
65 unsigned long flags;
66
67 spin_lock_irqsave(lock, flags);
63 writel_relaxed(readl_relaxed(reg) | mask, reg);68 writel_relaxed(readl_relaxed(reg) | mask, reg);
69 spin_unlock_irqrestore(lock, flags);
64}70}
65 71
66static inline void stm32_ipcc_clr_bits(void __iomem *reg, u32 mask)72static inline void stm32_ipcc_clr_bits(spinlock_t *lock, void __iomem *reg,
73 u32 mask)
67{74{
75 unsigned long flags;
76
77 spin_lock_irqsave(lock, flags);
68 writel_relaxed(readl_relaxed(reg) & ~mask, reg);78 writel_relaxed(readl_relaxed(reg) & ~mask, reg);
79 spin_unlock_irqrestore(lock, flags);
69}80}
70 81
71static irqreturn_t stm32_ipcc_rx_irq(int irq, void *data)82static irqreturn_t stm32_ipcc_rx_irq(int irq, void *data)
@@ -92,7 +103,7 @@ static irqreturn_t stm32_ipcc_rx_irq(int irq, void *data) · 20 unmodified lines
92 103
93 mbox_chan_received_data(&ipcc->controller.chans[chan], NULL);104 mbox_chan_received_data(&ipcc->controller.chans[chan], NULL);
94 105
95 stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XSCR,106 stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XSCR,
96 RX_BIT_CHAN(chan));107 RX_BIT_CHAN(chan));
97 108
98 ret = IRQ_HANDLED;109 ret = IRQ_HANDLED;
@@ -121,7 +132,7 @@ static irqreturn_t stm32_ipcc_tx_irq(int irq, void *data) · 22 unmodified lines
121 dev_dbg(dev, "%s: chan:%d tx\n", __func__, chan);132 dev_dbg(dev, "%s: chan:%d tx\n", __func__, chan);
122 133
123 /* mask 'tx channel free' interrupt */134 /* mask 'tx channel free' interrupt */
124 stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XMR,135 stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR,
125 TX_BIT_CHAN(chan));136 TX_BIT_CHAN(chan));
126 137
127 mbox_chan_txdone(&ipcc->controller.chans[chan], 0);138 mbox_chan_txdone(&ipcc->controller.chans[chan], 0);
@@ -141,10 +152,12 @@ static int stm32_ipcc_send_data(struct mbox_chan *link, void *data) · 13 unmodified lines
141 dev_dbg(ipcc->controller.dev, "%s: chan:%d\n", __func__, chan);152 dev_dbg(ipcc->controller.dev, "%s: chan:%d\n", __func__, chan);
142 153
143 /* set channel n occupied */154 /* set channel n occupied */
144 stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XSCR, TX_BIT_CHAN(chan));155 stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XSCR,
156 TX_BIT_CHAN(chan));
145 157
146 /* unmask 'tx channel free' interrupt */158 /* unmask 'tx channel free' interrupt */
147 stm32_ipcc_clr_bits(ipcc->reg_proc + IPCC_XMR, TX_BIT_CHAN(chan));159 stm32_ipcc_clr_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR,
160 TX_BIT_CHAN(chan));
148 161
149 return 0;162 return 0;
150}163}
@@ -163,7 +176,8 @@ static int stm32_ipcc_startup(struct mbox_chan *link) · 12 unmodified lines
163 }176 }
164 177
165 /* unmask 'rx channel occupied' interrupt */178 /* unmask 'rx channel occupied' interrupt */
166 stm32_ipcc_clr_bits(ipcc->reg_proc + IPCC_XMR, RX_BIT_CHAN(chan));179 stm32_ipcc_clr_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR,
180 RX_BIT_CHAN(chan));
167 181
168 return 0;182 return 0;
169}183}
@@ -175,7 +189,7 @@ static void stm32_ipcc_shutdown(struct mbox_chan *link) · 5 unmodified lines
175 controller);189 controller);
176 190
177 /* mask rx/tx interrupt */191 /* mask rx/tx interrupt */
178 stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XMR,192 stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR,
179 RX_BIT_CHAN(chan) | TX_BIT_CHAN(chan));193 RX_BIT_CHAN(chan) | TX_BIT_CHAN(chan));
180 194
181 clk_disable_unprepare(ipcc->clk);195 clk_disable_unprepare(ipcc->clk);
@@ -208,6 +222,8 @@ static int stm32_ipcc_probe(struct platform_device *pdev) · 26 unmodified lines
208 if (!ipcc)222 if (!ipcc)
209 return -ENOMEM;223 return -ENOMEM;
210 224
225 spin_lock_init(&ipcc->lock);
226
211 /* proc_id */227 /* proc_id */
212 if (of_property_read_u32(np, "st,proc-id", &ipcc->proc_id)) {228 if (of_property_read_u32(np, "st,proc-id", &ipcc->proc_id)) {
213 dev_err(dev, "Missing st,proc-id\n");229 dev_err(dev, "Missing st,proc-id\n");
@@ -259,9 +275,10 @@ static int stm32_ipcc_probe(struct platform_device *pdev) · 45 unmodified lines
259 }275 }
260 276
261 /* mask and enable rx/tx irq */277 /* mask and enable rx/tx irq */
262 stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XMR,278 stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR,
263 RX_BIT_MASK | TX_BIT_MASK);279 RX_BIT_MASK | TX_BIT_MASK);
264 stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XCR, XCR_RXOIE | XCR_TXOIE);280 stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XCR,
281 XCR_RXOIE | XCR_TXOIE);
265 282
266 /* wakeup */283 /* wakeup */
267 if (of_property_read_bool(np, "wakeup-source")) {284 if (of_property_read_bool(np, "wakeup-source")) {
drivers/mailbox/tegra-hsp.c+15−5
@@ -775,18 +775,28 @@ static int __maybe_unused tegra_hsp_resume(struct device *dev) · 774 unmodified lines
775{775{
776 struct tegra_hsp *hsp = dev_get_drvdata(dev);776 struct tegra_hsp *hsp = dev_get_drvdata(dev);
777 unsigned int i;777 unsigned int i;
778 struct tegra_hsp_doorbell *db;
778 779
779 for (i = 0; i < hsp->num_sm; i++) {780 list_for_each_entry(db, &hsp->doorbells, list) {
780 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[i];781 if (db && db->channel.chan)
782 tegra_hsp_doorbell_startup(db->channel.chan);
783 }
784
785 if (hsp->mailboxes) {
786 for (i = 0; i < hsp->num_sm; i++) {
787 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[i];
781 788
782 if (mb->channel.chan->cl)789 if (mb->channel.chan->cl)
783 tegra_hsp_mailbox_startup(mb->channel.chan);790 tegra_hsp_mailbox_startup(mb->channel.chan);
791 }
784 }792 }
785 793
786 return 0;794 return 0;
787}795}
788 796
789static SIMPLE_DEV_PM_OPS(tegra_hsp_pm_ops, NULL, tegra_hsp_resume);797static const struct dev_pm_ops tegra_hsp_pm_ops = {
798 .resume_noirq = tegra_hsp_resume,
799};
790 800
791static const struct tegra_hsp_db_map tegra186_hsp_db_map[] = {801static const struct tegra_hsp_db_map tegra186_hsp_db_map[] = {
792 { "ccplex", TEGRA_HSP_DB_MASTER_CCPLEX, HSP_DB_CCPLEX, },802 { "ccplex", TEGRA_HSP_DB_MASTER_CCPLEX, HSP_DB_CCPLEX, },
include/linux/omap-mailbox.h+3−1
@@ -6,7 +6,9 @@ · 5 unmodified lines
6#ifndef OMAP_MAILBOX_H6#ifndef OMAP_MAILBOX_H
7#define OMAP_MAILBOX_H7#define OMAP_MAILBOX_H
8 8
9typedef u32 mbox_msg_t;9typedef uintptr_t mbox_msg_t;
10
11#define omap_mbox_message(data) (u32)(mbox_msg_t)(data)
10 12
11typedef int __bitwise omap_mbox_irq_t;13typedef int __bitwise omap_mbox_irq_t;
12#define IRQ_TX ((__force omap_mbox_irq_t) 1)14#define IRQ_TX ((__force omap_mbox_irq_t) 1)

Keyboard shortcuts

General

Show keyboard shortcuts
?
Focus the current search
/

Issues and pull requests

Open filters
f

Issues, pull requests and Inbox

Select next item
j↓
Select previous item
k↑
Open selected item
Enter
Dismiss filters or clear selection
Esc

Repository code

Go to file
t