Older processors used to encode processor version and revision in two 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores have switched to use the 8-bits as 3:3:2 bitfield with the last field as the patch number.
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| @@ -124,6 +124,17 @@ · 123 unmodified lines | ||
| 124 | 124 | #define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */ |
| 125 | 125 | #define PRID_REV_VR4130 0x0080 |
| 126 | 126 | |
| 127 | +/* | |
| 128 | + * Older processors used to encode processor version and revision in two | |
| 129 | + * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores | |
| 130 | + * have switched to use the 8-bits as 3:3:2 bitfield with the last field as | |
| 131 | + * the patch number. *ARGH* | |
| 132 | + */ | |
| 133 | +#define PRID_REV_ENCODE_44(ver, rev) \ | |
| 134 | + ((ver) << 4 | (rev)) | |
| 135 | +#define PRID_REV_ENCODE_332(ver, rev, patch) \ | |
| 136 | + ((ver) << 5 | (rev) << 2 | (patch)) | |
| 137 | + | |
| 127 | 138 | /* |
| 128 | 139 | * FPU implementation/revision register (CP1 control register 0). |
| 129 | 140 | * |