Saeed Mahameed says: ==================== mlx5 fixes 2022-07-06 This series provides bug fixes to mlx5 driver. * tag 'mlx5-fixes-2022-07-06' of git://git.kernel.org/pub/scm/linux/kernel/git/saeed/linux: net/mlx5e: Ring the TX doorbell on DMA errors net/mlx5e: Fix capability check for updating vnic env counters net/mlx5e: CT: Use own workqueue instead of mlx5e priv net/mlx5: Lag, correct get the port select mode str net/mlx5e: Fix enabling sriov while tc nic rules are offloaded net/mlx5e: kTLS, Fix build time constant test in RX net/mlx5e: kTLS, Fix build time constant test in TX net/mlx5: Lag, decouple FDB selection and shared FDB net/mlx5: TC, allow offload from uplink to other PF's VF ====================
Unified · Split
| @@ -76,6 +76,7 @@ struct mlx5_tc_ct_priv { · 75 unmodified lines | ||
| 76 | 76 | struct mlx5_ct_fs *fs; |
| 77 | 77 | struct mlx5_ct_fs_ops *fs_ops; |
| 78 | 78 | spinlock_t ht_lock; /* protects ft entries */ |
| 79 | + struct workqueue_struct *wq; | |
| 79 | 80 | |
| 80 | 81 | struct mlx5_tc_ct_debugfs debugfs; |
| 81 | 82 | }; |
| @@ -941,14 +942,11 @@ static void mlx5_tc_ct_entry_del_work(struct work_struct *work) · 859 unmodified lines | ||
| 941 | 942 | static void |
| 942 | 943 | __mlx5_tc_ct_entry_put(struct mlx5_ct_entry *entry) |
| 943 | 944 | { |
| 944 | − struct mlx5e_priv *priv; | |
| 945 | − | |
| 946 | 945 | if (!refcount_dec_and_test(&entry->refcnt)) |
| 947 | 946 | return; |
| 948 | 947 | |
| 949 | − priv = netdev_priv(entry->ct_priv->netdev); | |
| 950 | 948 | INIT_WORK(&entry->work, mlx5_tc_ct_entry_del_work); |
| 951 | − queue_work(priv->wq, &entry->work); | |
| 949 | + queue_work(entry->ct_priv->wq, &entry->work); | |
| 952 | 950 | } |
| 953 | 951 | |
| 954 | 952 | static struct mlx5_ct_counter * |
| @@ -1759,19 +1757,16 @@ mlx5_tc_ct_flush_ft_entry(void *ptr, void *arg) · 804 unmodified lines | ||
| 1759 | 1757 | static void |
| 1760 | 1758 | mlx5_tc_ct_del_ft_cb(struct mlx5_tc_ct_priv *ct_priv, struct mlx5_ct_ft *ft) |
| 1761 | 1759 | { |
| 1762 | − struct mlx5e_priv *priv; | |
| 1763 | − | |
| 1764 | 1760 | if (!refcount_dec_and_test(&ft->refcount)) |
| 1765 | 1761 | return; |
| 1766 | 1762 | |
| 1763 | + flush_workqueue(ct_priv->wq); | |
| 1767 | 1764 | nf_flow_table_offload_del_cb(ft->nf_ft, |
| 1768 | 1765 | mlx5_tc_ct_block_flow_offload, ft); |
| 1769 | 1766 | rhashtable_remove_fast(&ct_priv->zone_ht, &ft->node, zone_params); |
| 1770 | 1767 | rhashtable_free_and_destroy(&ft->ct_entries_ht, |
| 1771 | 1768 | mlx5_tc_ct_flush_ft_entry, |
| 1772 | 1769 | ct_priv); |
| 1773 | − priv = netdev_priv(ct_priv->netdev); | |
| 1774 | − flush_workqueue(priv->wq); | |
| 1775 | 1770 | mlx5_tc_ct_free_pre_ct_tables(ft); |
| 1776 | 1771 | mapping_remove(ct_priv->zone_mapping, ft->zone_restore_id); |
| 1777 | 1772 | kfree(ft); |
| @@ -2176,6 +2171,12 @@ mlx5_tc_ct_init(struct mlx5e_priv *priv, struct mlx5_fs_chains *chains, · 398 unmodified lines | ||
| 2176 | 2171 | if (rhashtable_init(&ct_priv->ct_tuples_nat_ht, &tuples_nat_ht_params)) |
| 2177 | 2172 | goto err_ct_tuples_nat_ht; |
| 2178 | 2173 | |
| 2174 | + ct_priv->wq = alloc_ordered_workqueue("mlx5e_ct_priv_wq", 0); | |
| 2175 | + if (!ct_priv->wq) { | |
| 2176 | + err = -ENOMEM; | |
| 2177 | + goto err_wq; | |
| 2178 | + } | |
| 2179 | + | |
| 2179 | 2180 | err = mlx5_tc_ct_fs_init(ct_priv); |
| 2180 | 2181 | if (err) |
| 2181 | 2182 | goto err_init_fs; |
| @@ -2184,6 +2185,8 @@ mlx5_tc_ct_init(struct mlx5e_priv *priv, struct mlx5_fs_chains *chains, · 2 unmodified lines | ||
| 2184 | 2185 | return ct_priv; |
| 2185 | 2186 | |
| 2186 | 2187 | err_init_fs: |
| 2188 | + destroy_workqueue(ct_priv->wq); | |
| 2189 | +err_wq: | |
| 2187 | 2190 | rhashtable_destroy(&ct_priv->ct_tuples_nat_ht); |
| 2188 | 2191 | err_ct_tuples_nat_ht: |
| 2189 | 2192 | rhashtable_destroy(&ct_priv->ct_tuples_ht); |
| @@ -2213,6 +2216,7 @@ mlx5_tc_ct_clean(struct mlx5_tc_ct_priv *ct_priv) · 23 unmodified lines | ||
| 2213 | 2216 | if (!ct_priv) |
| 2214 | 2217 | return; |
| 2215 | 2218 | |
| 2219 | + destroy_workqueue(ct_priv->wq); | |
| 2216 | 2220 | mlx5_ct_tc_remove_dbgfs(ct_priv); |
| 2217 | 2221 | chains = ct_priv->chains; |
| 2218 | 2222 | |
| @@ -231,8 +231,7 @@ mlx5e_set_ktls_rx_priv_ctx(struct tls_context *tls_ctx, · 230 unmodified lines | ||
| 231 | 231 | struct mlx5e_ktls_offload_context_rx **ctx = |
| 232 | 232 | __tls_driver_ctx(tls_ctx, TLS_OFFLOAD_CTX_DIR_RX); |
| 233 | 233 | |
| 234 | − BUILD_BUG_ON(sizeof(struct mlx5e_ktls_offload_context_rx *) > | |
| 235 | − TLS_OFFLOAD_CONTEXT_SIZE_RX); | |
| 234 | + BUILD_BUG_ON(sizeof(priv_rx) > TLS_DRIVER_STATE_SIZE_RX); | |
| 236 | 235 | |
| 237 | 236 | *ctx = priv_rx; |
| 238 | 237 | } |
| @@ -68,8 +68,7 @@ mlx5e_set_ktls_tx_priv_ctx(struct tls_context *tls_ctx, · 67 unmodified lines | ||
| 68 | 68 | struct mlx5e_ktls_offload_context_tx **ctx = |
| 69 | 69 | __tls_driver_ctx(tls_ctx, TLS_OFFLOAD_CTX_DIR_TX); |
| 70 | 70 | |
| 71 | − BUILD_BUG_ON(sizeof(struct mlx5e_ktls_offload_context_tx *) > | |
| 72 | − TLS_OFFLOAD_CONTEXT_SIZE_TX); | |
| 71 | + BUILD_BUG_ON(sizeof(priv_tx) > TLS_DRIVER_STATE_SIZE_TX); | |
| 73 | 72 | |
| 74 | 73 | *ctx = priv_tx; |
| 75 | 74 | } |
| @@ -688,7 +688,7 @@ static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(vnic_env) · 687 unmodified lines | ||
| 688 | 688 | u32 in[MLX5_ST_SZ_DW(query_vnic_env_in)] = {}; |
| 689 | 689 | struct mlx5_core_dev *mdev = priv->mdev; |
| 690 | 690 | |
| 691 | − if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard)) | |
| 691 | + if (!mlx5e_stats_grp_vnic_env_num_stats(priv)) | |
| 692 | 692 | return; |
| 693 | 693 | |
| 694 | 694 | MLX5_SET(query_vnic_env_in, in, opcode, MLX5_CMD_OP_QUERY_VNIC_ENV); |
| @@ -3793,7 +3793,7 @@ static bool is_lag_dev(struct mlx5e_priv *priv, · 3792 unmodified lines | ||
| 3793 | 3793 | |
| 3794 | 3794 | static bool is_multiport_eligible(struct mlx5e_priv *priv, struct net_device *out_dev) |
| 3795 | 3795 | { |
| 3796 | − if (mlx5e_eswitch_uplink_rep(out_dev) && | |
| 3796 | + if (same_hw_reps(priv, out_dev) && | |
| 3797 | 3797 | MLX5_CAP_PORT_SELECTION(priv->mdev, port_select_flow_table) && |
| 3798 | 3798 | MLX5_CAP_GEN(priv->mdev, create_lag_when_not_master_up)) |
| 3799 | 3799 | return true; |
| @@ -341,6 +341,26 @@ static void mlx5e_tx_check_stop(struct mlx5e_txqsq *sq) · 340 unmodified lines | ||
| 341 | 341 | } |
| 342 | 342 | } |
| 343 | 343 | |
| 344 | +static void mlx5e_tx_flush(struct mlx5e_txqsq *sq) | |
| 345 | +{ | |
| 346 | + struct mlx5e_tx_wqe_info *wi; | |
| 347 | + struct mlx5e_tx_wqe *wqe; | |
| 348 | + u16 pi; | |
| 349 | + | |
| 350 | + /* Must not be called when a MPWQE session is active but empty. */ | |
| 351 | + mlx5e_tx_mpwqe_ensure_complete(sq); | |
| 352 | + | |
| 353 | + pi = mlx5_wq_cyc_ctr2ix(&sq->wq, sq->pc); | |
| 354 | + wi = &sq->db.wqe_info[pi]; | |
| 355 | + | |
| 356 | + *wi = (struct mlx5e_tx_wqe_info) { | |
| 357 | + .num_wqebbs = 1, | |
| 358 | + }; | |
| 359 | + | |
| 360 | + wqe = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc); | |
| 361 | + mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &wqe->ctrl); | |
| 362 | +} | |
| 363 | + | |
| 344 | 364 | static inline void |
| 345 | 365 | mlx5e_txwqe_complete(struct mlx5e_txqsq *sq, struct sk_buff *skb, |
| 346 | 366 | const struct mlx5e_tx_attr *attr, |
| @@ -459,6 +479,7 @@ mlx5e_sq_xmit_wqe(struct mlx5e_txqsq *sq, struct sk_buff *skb, · 112 unmodified lines | ||
| 459 | 479 | err_drop: |
| 460 | 480 | stats->dropped++; |
| 461 | 481 | dev_kfree_skb_any(skb); |
| 482 | + mlx5e_tx_flush(sq); | |
| 462 | 483 | } |
| 463 | 484 | |
| 464 | 485 | static bool mlx5e_tx_skb_supports_mpwqe(struct sk_buff *skb, struct mlx5e_tx_attr *attr) |
| @@ -560,6 +581,13 @@ mlx5e_sq_xmit_mpwqe(struct mlx5e_txqsq *sq, struct sk_buff *skb, · 95 unmodified lines | ||
| 560 | 581 | struct mlx5_wqe_ctrl_seg *cseg; |
| 561 | 582 | struct mlx5e_xmit_data txd; |
| 562 | 583 | |
| 584 | + txd.data = skb->data; | |
| 585 | + txd.len = skb->len; | |
| 586 | + | |
| 587 | + txd.dma_addr = dma_map_single(sq->pdev, txd.data, txd.len, DMA_TO_DEVICE); | |
| 588 | + if (unlikely(dma_mapping_error(sq->pdev, txd.dma_addr))) | |
| 589 | + goto err_unmap; | |
| 590 | + | |
| 563 | 591 | if (!mlx5e_tx_mpwqe_session_is_active(sq)) { |
| 564 | 592 | mlx5e_tx_mpwqe_session_start(sq, eseg); |
| 565 | 593 | } else if (!mlx5e_tx_mpwqe_same_eseg(sq, eseg)) { |
| @@ -569,18 +597,9 @@ mlx5e_sq_xmit_mpwqe(struct mlx5e_txqsq *sq, struct sk_buff *skb, · 3 unmodified lines | ||
| 569 | 597 | |
| 570 | 598 | sq->stats->xmit_more += xmit_more; |
| 571 | 599 | |
| 572 | − txd.data = skb->data; | |
| 573 | − txd.len = skb->len; | |
| 574 | − | |
| 575 | − txd.dma_addr = dma_map_single(sq->pdev, txd.data, txd.len, DMA_TO_DEVICE); | |
| 576 | − if (unlikely(dma_mapping_error(sq->pdev, txd.dma_addr))) | |
| 577 | − goto err_unmap; | |
| 578 | 600 | mlx5e_dma_push(sq, txd.dma_addr, txd.len, MLX5E_DMA_MAP_SINGLE); |
| 579 | − | |
| 580 | 601 | mlx5e_skb_fifo_push(&sq->db.skb_fifo, skb); |
| 581 | − | |
| 582 | 602 | mlx5e_tx_mpwqe_add_dseg(sq, &txd); |
| 583 | − | |
| 584 | 603 | mlx5e_tx_skb_update_hwts_flags(skb); |
| 585 | 604 | |
| 586 | 605 | if (unlikely(mlx5e_tx_mpwqe_is_full(&sq->mpwqe, sq->max_sq_mpw_wqebbs))) { |
| @@ -602,6 +621,7 @@ err_unmap: · 15 unmodified lines | ||
| 602 | 621 | mlx5e_dma_unmap_wqe_err(sq, 1); |
| 603 | 622 | sq->stats->dropped++; |
| 604 | 623 | dev_kfree_skb_any(skb); |
| 624 | + mlx5e_tx_flush(sq); | |
| 605 | 625 | } |
| 606 | 626 | |
| 607 | 627 | void mlx5e_tx_mpwqe_ensure_complete(struct mlx5e_txqsq *sq) |
| @@ -1006,5 +1026,6 @@ void mlx5i_sq_xmit(struct mlx5e_txqsq *sq, struct sk_buff *skb, · 398 unmodified lines | ||
| 1006 | 1026 | err_drop: |
| 1007 | 1027 | stats->dropped++; |
| 1008 | 1028 | dev_kfree_skb_any(skb); |
| 1029 | + mlx5e_tx_flush(sq); | |
| 1009 | 1030 | } |
| 1010 | 1031 | #endif |
| @@ -11,6 +11,7 @@ · 10 unmodified lines | ||
| 11 | 11 | #include "mlx5_core.h" |
| 12 | 12 | #include "eswitch.h" |
| 13 | 13 | #include "fs_core.h" |
| 14 | +#include "fs_ft_pool.h" | |
| 14 | 15 | #include "esw/qos.h" |
| 15 | 16 | |
| 16 | 17 | enum { |
| @@ -95,8 +96,7 @@ static int esw_create_legacy_fdb_table(struct mlx5_eswitch *esw) · 78 unmodified lines | ||
| 95 | 96 | if (!flow_group_in) |
| 96 | 97 | return -ENOMEM; |
| 97 | 98 | |
| 98 | − table_size = BIT(MLX5_CAP_ESW_FLOWTABLE_FDB(dev, log_max_ft_size)); | |
| 99 | − ft_attr.max_fte = table_size; | |
| 99 | + ft_attr.max_fte = POOL_NEXT_SIZE; | |
| 100 | 100 | ft_attr.prio = LEGACY_FDB_PRIO; |
| 101 | 101 | fdb = mlx5_create_flow_table(root_ns, &ft_attr); |
| 102 | 102 | if (IS_ERR(fdb)) { |
| @@ -105,6 +105,7 @@ static int esw_create_legacy_fdb_table(struct mlx5_eswitch *esw) · 2 unmodified lines | ||
| 105 | 105 | goto out; |
| 106 | 106 | } |
| 107 | 107 | esw->fdb_table.legacy.fdb = fdb; |
| 108 | + table_size = fdb->max_fte; | |
| 108 | 109 | |
| 109 | 110 | /* Addresses group : Full match unicast/multicast addresses */ |
| 110 | 111 | MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable, |
| @@ -44,7 +44,7 @@ static int port_sel_mode_show(struct seq_file *file, void *priv) · 43 unmodified lines | ||
| 44 | 44 | ldev = dev->priv.lag; |
| 45 | 45 | mutex_lock(&ldev->lock); |
| 46 | 46 | if (__mlx5_lag_is_active(ldev)) |
| 47 | − mode = mlx5_get_str_port_sel_mode(ldev); | |
| 47 | + mode = mlx5_get_str_port_sel_mode(ldev->mode, ldev->mode_flags); | |
| 48 | 48 | else |
| 49 | 49 | ret = -EINVAL; |
| 50 | 50 | mutex_unlock(&ldev->lock); |
| @@ -72,6 +72,7 @@ static int state_show(struct seq_file *file, void *priv) · 21 unmodified lines | ||
| 72 | 72 | static int flags_show(struct seq_file *file, void *priv) |
| 73 | 73 | { |
| 74 | 74 | struct mlx5_core_dev *dev = file->private; |
| 75 | + bool fdb_sel_mode_native; | |
| 75 | 76 | struct mlx5_lag *ldev; |
| 76 | 77 | bool shared_fdb; |
| 77 | 78 | bool lag_active; |
| @@ -79,14 +80,21 @@ static int flags_show(struct seq_file *file, void *priv) · 1 unmodified line | ||
| 79 | 80 | ldev = dev->priv.lag; |
| 80 | 81 | mutex_lock(&ldev->lock); |
| 81 | 82 | lag_active = __mlx5_lag_is_active(ldev); |
| 82 | − if (lag_active) | |
| 83 | − shared_fdb = test_bit(MLX5_LAG_MODE_FLAG_SHARED_FDB, &ldev->mode_flags); | |
| 83 | + if (!lag_active) | |
| 84 | + goto unlock; | |
| 85 | + | |
| 86 | + shared_fdb = test_bit(MLX5_LAG_MODE_FLAG_SHARED_FDB, &ldev->mode_flags); | |
| 87 | + fdb_sel_mode_native = test_bit(MLX5_LAG_MODE_FLAG_FDB_SEL_MODE_NATIVE, | |
| 88 | + &ldev->mode_flags); | |
| 84 | 89 | |
| 90 | +unlock: | |
| 85 | 91 | mutex_unlock(&ldev->lock); |
| 86 | 92 | if (!lag_active) |
| 87 | 93 | return -EINVAL; |
| 88 | 94 | |
| 89 | 95 | seq_printf(file, "%s:%s\n", "shared_fdb", shared_fdb ? "on" : "off"); |
| 96 | + seq_printf(file, "%s:%s\n", "fdb_selection_mode", | |
| 97 | + fdb_sel_mode_native ? "native" : "affinity"); | |
| 90 | 98 | return 0; |
| 91 | 99 | } |
| 92 | 100 | |
| @@ -68,14 +68,15 @@ static int get_port_sel_mode(enum mlx5_lag_mode mode, unsigned long flags) · 67 unmodified lines | ||
| 68 | 68 | static int mlx5_cmd_create_lag(struct mlx5_core_dev *dev, u8 *ports, int mode, |
| 69 | 69 | unsigned long flags) |
| 70 | 70 | { |
| 71 | − bool shared_fdb = test_bit(MLX5_LAG_MODE_FLAG_SHARED_FDB, &flags); | |
| 71 | + bool fdb_sel_mode = test_bit(MLX5_LAG_MODE_FLAG_FDB_SEL_MODE_NATIVE, | |
| 72 | + &flags); | |
| 72 | 73 | int port_sel_mode = get_port_sel_mode(mode, flags); |
| 73 | 74 | u32 in[MLX5_ST_SZ_DW(create_lag_in)] = {}; |
| 74 | 75 | void *lag_ctx; |
| 75 | 76 | |
| 76 | 77 | lag_ctx = MLX5_ADDR_OF(create_lag_in, in, ctx); |
| 77 | 78 | MLX5_SET(create_lag_in, in, opcode, MLX5_CMD_OP_CREATE_LAG); |
| 78 | − MLX5_SET(lagc, lag_ctx, fdb_selection_mode, shared_fdb); | |
| 79 | + MLX5_SET(lagc, lag_ctx, fdb_selection_mode, fdb_sel_mode); | |
| 79 | 80 | if (port_sel_mode == MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY) { |
| 80 | 81 | MLX5_SET(lagc, lag_ctx, tx_remap_affinity_1, ports[0]); |
| 81 | 82 | MLX5_SET(lagc, lag_ctx, tx_remap_affinity_2, ports[1]); |
| @@ -471,8 +472,13 @@ static int mlx5_lag_set_flags(struct mlx5_lag *ldev, enum mlx5_lag_mode mode, · 389 unmodified lines | ||
| 471 | 472 | bool roce_lag = mode == MLX5_LAG_MODE_ROCE; |
| 472 | 473 | |
| 473 | 474 | *flags = 0; |
| 474 | − if (shared_fdb) | |
| 475 | + if (shared_fdb) { | |
| 475 | 476 | set_bit(MLX5_LAG_MODE_FLAG_SHARED_FDB, flags); |
| 477 | + set_bit(MLX5_LAG_MODE_FLAG_FDB_SEL_MODE_NATIVE, flags); | |
| 478 | + } | |
| 479 | + | |
| 480 | + if (mode == MLX5_LAG_MODE_MPESW) | |
| 481 | + set_bit(MLX5_LAG_MODE_FLAG_FDB_SEL_MODE_NATIVE, flags); | |
| 476 | 482 | |
| 477 | 483 | if (roce_lag) |
| 478 | 484 | return mlx5_lag_set_port_sel_mode_roce(ldev, flags); |
| @@ -481,9 +487,9 @@ static int mlx5_lag_set_flags(struct mlx5_lag *ldev, enum mlx5_lag_mode mode, · 2 unmodified lines | ||
| 481 | 487 | return 0; |
| 482 | 488 | } |
| 483 | 489 | |
| 484 | −char *mlx5_get_str_port_sel_mode(struct mlx5_lag *ldev) | |
| 490 | +char *mlx5_get_str_port_sel_mode(enum mlx5_lag_mode mode, unsigned long flags) | |
| 485 | 491 | { |
| 486 | − int port_sel_mode = get_port_sel_mode(ldev->mode, ldev->mode_flags); | |
| 492 | + int port_sel_mode = get_port_sel_mode(mode, flags); | |
| 487 | 493 | |
| 488 | 494 | switch (port_sel_mode) { |
| 489 | 495 | case MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY: return "queue_affinity"; |
| @@ -507,7 +513,7 @@ static int mlx5_create_lag(struct mlx5_lag *ldev, · 17 unmodified lines | ||
| 507 | 513 | if (tracker) |
| 508 | 514 | mlx5_lag_print_mapping(dev0, ldev, tracker, flags); |
| 509 | 515 | mlx5_core_info(dev0, "shared_fdb:%d mode:%s\n", |
| 510 | − shared_fdb, mlx5_get_str_port_sel_mode(ldev)); | |
| 516 | + shared_fdb, mlx5_get_str_port_sel_mode(mode, flags)); | |
| 511 | 517 | |
| 512 | 518 | err = mlx5_cmd_create_lag(dev0, ldev->v2p_map, mode, flags); |
| 513 | 519 | if (err) { |
| @@ -24,6 +24,7 @@ enum { · 23 unmodified lines | ||
| 24 | 24 | enum { |
| 25 | 25 | MLX5_LAG_MODE_FLAG_HASH_BASED, |
| 26 | 26 | MLX5_LAG_MODE_FLAG_SHARED_FDB, |
| 27 | + MLX5_LAG_MODE_FLAG_FDB_SEL_MODE_NATIVE, | |
| 27 | 28 | }; |
| 28 | 29 | |
| 29 | 30 | enum mlx5_lag_mode { |
| @@ -114,7 +115,7 @@ bool mlx5_shared_fdb_supported(struct mlx5_lag *ldev); · 84 unmodified lines | ||
| 114 | 115 | void mlx5_lag_del_mpesw_rule(struct mlx5_core_dev *dev); |
| 115 | 116 | int mlx5_lag_add_mpesw_rule(struct mlx5_core_dev *dev); |
| 116 | 117 | |
| 117 | −char *mlx5_get_str_port_sel_mode(struct mlx5_lag *ldev); | |
| 118 | +char *mlx5_get_str_port_sel_mode(enum mlx5_lag_mode mode, unsigned long flags); | |
| 118 | 119 | void mlx5_infer_tx_enabled(struct lag_tracker *tracker, u8 num_ports, |
| 119 | 120 | u8 *ports, int *num_enabled); |
| 120 | 121 | |
| @@ -41,7 +41,6 @@ void mlx5_lag_del_mpesw_rule(struct mlx5_core_dev *dev) · 40 unmodified lines | ||
| 41 | 41 | int mlx5_lag_add_mpesw_rule(struct mlx5_core_dev *dev) |
| 42 | 42 | { |
| 43 | 43 | struct mlx5_lag *ldev = dev->priv.lag; |
| 44 | − bool shared_fdb; | |
| 45 | 44 | int err = 0; |
| 46 | 45 | |
| 47 | 46 | if (!ldev) |
| @@ -55,8 +54,8 @@ int mlx5_lag_add_mpesw_rule(struct mlx5_core_dev *dev) · 7 unmodified lines | ||
| 55 | 54 | err = -EINVAL; |
| 56 | 55 | goto out; |
| 57 | 56 | } |
| 58 | − shared_fdb = mlx5_shared_fdb_supported(ldev); | |
| 59 | − err = mlx5_activate_lag(ldev, NULL, MLX5_LAG_MODE_MPESW, shared_fdb); | |
| 57 | + | |
| 58 | + err = mlx5_activate_lag(ldev, NULL, MLX5_LAG_MODE_MPESW, false); | |
| 60 | 59 | if (err) |
| 61 | 60 | mlx5_core_warn(dev, "Failed to create LAG in MPESW mode (%d)\n", err); |
| 62 | 61 | |