- Support for STM32F769 - Rework AT91 sckc DT bindings - Fix slow RC oscillator issue on sama5d3 - AT91 sam9x60 PMC support - SiFive FU540 PRCI and PLL support * clk-stm32f4: clk: stm32mp1: Add ddrperfm clock clk: stm32: Introduce clocks of STM32F769 board * clk-tegra: clk: tegra: divider: Mark Memory Controller clock as read-only clk: tegra: emc: Replace BUG() with WARN_ONCE() clk: tegra: emc: Fix EMC max-rate clamping clk: tegra: emc: Support multiple RAM codes clk: tegra: emc: Don't enable EMC clock manually clk: tegra124: Remove lock-enable bit from PLLM clk: tegra: Fix PLLM programming on Tegra124+ when PMC overrides divider clk: tegra: Don't enable already enabled PLLs * clk-at91: clk: at91: Mark struct clk_range as const clk: at91: add sam9x60 pmc driver dt-bindings: clk: at91: add bindings for SAM9X60 pmc clk: at91: add sam9x60 PLL driver clk: at91: master: Add sam9x60 support clk: at91: usb: Add sam9x60 support clk: at91: allow configuring generated PCR layout clk: at91: allow configuring peripheral PCR layout clk: at91: sckc: handle different RC startup time clk: at91: modernize sckc binding dt-bindings: clock: at91: new sckc bindings * clk-sifive-fu540: clk: sifive: add a driver for the SiFive FU540 PRCI IP block clk: analogbits: add Wide-Range PLL library dt-bindings: clk: add documentation for the SiFive PRCI driver * clk-spdx: clk: sunxi-ng: Use the correct style for SPDX License Identifier clk: sprd: Use the correct style for SPDX License Identifier clk: renesas: Use the correct style for SPDX License Identifier clk: qcom: Use the correct style for SPDX License Identifier clk: davinci: Use the correct style for SPDX License Identifier clk: actions: Use the correct style for SPDX License Identifier
ff060016 parents 5816b74 b06df56 e71f4d3 7b4c162 30b8e27 d65530c59 files · +2424 −259Browse filesShowing the changes to include/linux (2 of 59 files). Show all
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| @@ -0,0 +1,79 @@ | ||
| 1 | +/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | +/* | |
| 3 | + * Copyright (C) 2018-2019 SiFive, Inc. | |
| 4 | + * Wesley Terpstra | |
| 5 | + * Paul Walmsley | |
| 6 | + */ | |
| 7 | + | |
| 8 | +#ifndef __LINUX_CLK_ANALOGBITS_WRPLL_CLN28HPC_H | |
| 9 | +#define __LINUX_CLK_ANALOGBITS_WRPLL_CLN28HPC_H | |
| 10 | + | |
| 11 | +#include <linux/types.h> | |
| 12 | + | |
| 13 | +/* DIVQ_VALUES: number of valid DIVQ values */ | |
| 14 | +#define DIVQ_VALUES 6 | |
| 15 | + | |
| 16 | +/* | |
| 17 | + * Bit definitions for struct wrpll_cfg.flags | |
| 18 | + * | |
| 19 | + * WRPLL_FLAGS_BYPASS_FLAG: if set, the PLL is either in bypass, or should be | |
| 20 | + * programmed to enter bypass | |
| 21 | + * WRPLL_FLAGS_RESET_FLAG: if set, the PLL is in reset | |
| 22 | + * WRPLL_FLAGS_INT_FEEDBACK_FLAG: if set, the PLL is configured for internal | |
| 23 | + * feedback mode | |
| 24 | + * WRPLL_FLAGS_EXT_FEEDBACK_FLAG: if set, the PLL is configured for external | |
| 25 | + * feedback mode (not yet supported by this driver) | |
| 26 | + */ | |
| 27 | +#define WRPLL_FLAGS_BYPASS_SHIFT 0 | |
| 28 | +#define WRPLL_FLAGS_BYPASS_MASK BIT(WRPLL_FLAGS_BYPASS_SHIFT) | |
| 29 | +#define WRPLL_FLAGS_RESET_SHIFT 1 | |
| 30 | +#define WRPLL_FLAGS_RESET_MASK BIT(WRPLL_FLAGS_RESET_SHIFT) | |
| 31 | +#define WRPLL_FLAGS_INT_FEEDBACK_SHIFT 2 | |
| 32 | +#define WRPLL_FLAGS_INT_FEEDBACK_MASK BIT(WRPLL_FLAGS_INT_FEEDBACK_SHIFT) | |
| 33 | +#define WRPLL_FLAGS_EXT_FEEDBACK_SHIFT 3 | |
| 34 | +#define WRPLL_FLAGS_EXT_FEEDBACK_MASK BIT(WRPLL_FLAGS_EXT_FEEDBACK_SHIFT) | |
| 35 | + | |
| 36 | +/** | |
| 37 | + * struct wrpll_cfg - WRPLL configuration values | |
| 38 | + * @divr: reference divider value (6 bits), as presented to the PLL signals | |
| 39 | + * @divf: feedback divider value (9 bits), as presented to the PLL signals | |
| 40 | + * @divq: output divider value (3 bits), as presented to the PLL signals | |
| 41 | + * @flags: PLL configuration flags. See above for more information | |
| 42 | + * @range: PLL loop filter range. See below for more information | |
| 43 | + * @output_rate_cache: cached output rates, swept across DIVQ | |
| 44 | + * @parent_rate: PLL refclk rate for which values are valid | |
| 45 | + * @max_r: maximum possible R divider value, given @parent_rate | |
| 46 | + * @init_r: initial R divider value to start the search from | |
| 47 | + * | |
| 48 | + * @divr, @divq, @divq, @range represent what the PLL expects to see | |
| 49 | + * on its input signals. Thus @divr and @divf are the actual divisors | |
| 50 | + * minus one. @divq is a power-of-two divider; for example, 1 = | |
| 51 | + * divide-by-2 and 6 = divide-by-64. 0 is an invalid @divq value. | |
| 52 | + * | |
| 53 | + * When initially passing a struct wrpll_cfg record, the | |
| 54 | + * record should be zero-initialized with the exception of the @flags | |
| 55 | + * field. The only flag bits that need to be set are either | |
| 56 | + * WRPLL_FLAGS_INT_FEEDBACK or WRPLL_FLAGS_EXT_FEEDBACK. | |
| 57 | + */ | |
| 58 | +struct wrpll_cfg { | |
| 59 | + u8 divr; | |
| 60 | + u8 divq; | |
| 61 | + u8 range; | |
| 62 | + u8 flags; | |
| 63 | + u16 divf; | |
| 64 | +/* private: */ | |
| 65 | + u32 output_rate_cache[DIVQ_VALUES]; | |
| 66 | + unsigned long parent_rate; | |
| 67 | + u8 max_r; | |
| 68 | + u8 init_r; | |
| 69 | +}; | |
| 70 | + | |
| 71 | +int wrpll_configure_for_rate(struct wrpll_cfg *c, u32 target_rate, | |
| 72 | + unsigned long parent_rate); | |
| 73 | + | |
| 74 | +unsigned int wrpll_calc_max_lock_us(const struct wrpll_cfg *c); | |
| 75 | + | |
| 76 | +unsigned long wrpll_calc_output_rate(const struct wrpll_cfg *c, | |
| 77 | + unsigned long parent_rate); | |
| 78 | + | |
| 79 | +#endif /* __LINUX_CLK_ANALOGBITS_WRPLL_CLN28HPC_H */ | |
| @@ -74,6 +74,8 @@ · 73 unmodified lines | ||
| 74 | 74 | #define AT91_PMC_USBDIV_4 (2 << 28) |
| 75 | 75 | #define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */ |
| 76 | 76 | |
| 77 | +#define AT91_PMC_CPU_CKR 0x28 /* CPU Clock Register */ | |
| 78 | + | |
| 77 | 79 | #define AT91_PMC_MCKR 0x30 /* Master Clock Register */ |
| 78 | 80 | #define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */ |
| 79 | 81 | #define AT91_PMC_CSS_SLOW (0 << 0) |
| @@ -187,16 +189,8 @@ · 107 unmodified lines | ||
| 187 | 189 | |
| 188 | 190 | #define AT91_PMC_PCR 0x10c /* Peripheral Control Register [some SAM9 and SAMA5] */ |
| 189 | 191 | #define AT91_PMC_PCR_PID_MASK 0x3f |
| 190 | −#define AT91_PMC_PCR_GCKCSS_OFFSET 8 | |
| 191 | −#define AT91_PMC_PCR_GCKCSS_MASK (0x7 << AT91_PMC_PCR_GCKCSS_OFFSET) | |
| 192 | −#define AT91_PMC_PCR_GCKCSS(n) ((n) << AT91_PMC_PCR_GCKCSS_OFFSET) /* GCK Clock Source Selection */ | |
| 193 | 192 | #define AT91_PMC_PCR_CMD (0x1 << 12) /* Command (read=0, write=1) */ |
| 194 | −#define AT91_PMC_PCR_DIV_OFFSET 16 | |
| 195 | −#define AT91_PMC_PCR_DIV_MASK (0x3 << AT91_PMC_PCR_DIV_OFFSET) | |
| 196 | −#define AT91_PMC_PCR_DIV(n) ((n) << AT91_PMC_PCR_DIV_OFFSET) /* Divisor Value */ | |
| 197 | −#define AT91_PMC_PCR_GCKDIV_OFFSET 20 | |
| 198 | −#define AT91_PMC_PCR_GCKDIV_MASK (0xff << AT91_PMC_PCR_GCKDIV_OFFSET) | |
| 199 | −#define AT91_PMC_PCR_GCKDIV(n) ((n) << AT91_PMC_PCR_GCKDIV_OFFSET) /* Generated Clock Divisor Value */ | |
| 193 | +#define AT91_PMC_PCR_GCKDIV_MASK GENMASK(27, 20) | |
| 200 | 194 | #define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */ |
| 201 | 195 | #define AT91_PMC_PCR_GCKEN (0x1 << 29) /* GCK Enable */ |
| 202 | 196 | |