History

Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

Pull MIPS fixes from Ralf Baechle: "Another round of MIPS fixes for 4.9: - Fix unreadable output in __do_page_fault due to the KERN_CONT patchset - Correctly handle MIPS R6 fixes to the c0_wired register" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: MIPS: mm: Fix output of __do_page_fault MIPS: Mask out limit field when calculating wired entry count

Linus Torvalds committed 9 years ago

Commit ff17bf82 parents d8e435f 2a872a55 files · +29 −9Browse files

Unified · Split

5 files
  1. arch/mips/include/asm/mipsregs.h +6 −0
  2. arch/mips/include/asm/tlb.h +13 −0
  3. arch/mips/mm/fault.c +5 −4
  4. arch/mips/mm/init.c +2 −2
  5. arch/mips/mm/tlb-r4k.c +3 −3
arch/mips/include/asm/mipsregs.h+6−0
@@ -214,6 +214,12 @@ · 213 unmodified lines
214#error Bad page size configuration for hugetlbfs!214#error Bad page size configuration for hugetlbfs!
215#endif215#endif
216 216
217/*
218 * Wired register bits
219 */
220#define MIPSR6_WIRED_LIMIT (_ULCAST_(0xffff) << 16)
221#define MIPSR6_WIRED_WIRED (_ULCAST_(0xffff) << 0)
222
217/*223/*
218 * Values used for computation of new tlb entries224 * Values used for computation of new tlb entries
219 */225 */
arch/mips/include/asm/tlb.h+13−0
@@ -1,6 +1,9 @@
1#ifndef __ASM_TLB_H1#ifndef __ASM_TLB_H
2#define __ASM_TLB_H2#define __ASM_TLB_H
3 3
4#include <asm/cpu-features.h>
5#include <asm/mipsregs.h>
6
4/*7/*
5 * MIPS doesn't need any special per-pte or per-vma handling, except8 * MIPS doesn't need any special per-pte or per-vma handling, except
6 * we need to flush cache for area to be unmapped.9 * we need to flush cache for area to be unmapped.
@@ -22,6 +25,16 @@ · 15 unmodified lines
22 ((CKSEG0 + ((idx) << (PAGE_SHIFT + 1))) | \25 ((CKSEG0 + ((idx) << (PAGE_SHIFT + 1))) | \
23 (cpu_has_tlbinv ? MIPS_ENTRYHI_EHINV : 0))26 (cpu_has_tlbinv ? MIPS_ENTRYHI_EHINV : 0))
24 27
28static inline unsigned int num_wired_entries(void)
29{
30 unsigned int wired = read_c0_wired();
31
32 if (cpu_has_mips_r6)
33 wired &= MIPSR6_WIRED_WIRED;
34
35 return wired;
36}
37
25#include <asm-generic/tlb.h>38#include <asm-generic/tlb.h>
26 39
27#endif /* __ASM_TLB_H */40#endif /* __ASM_TLB_H */
arch/mips/mm/fault.c+5−4
@@ -209,17 +209,18 @@ bad_area_nosemaphore: · 208 unmodified lines
209 if (show_unhandled_signals &&209 if (show_unhandled_signals &&
210 unhandled_signal(tsk, SIGSEGV) &&210 unhandled_signal(tsk, SIGSEGV) &&
211 __ratelimit(&ratelimit_state)) {211 __ratelimit(&ratelimit_state)) {
212 pr_info("\ndo_page_fault(): sending SIGSEGV to %s for invalid %s %0*lx",212 pr_info("do_page_fault(): sending SIGSEGV to %s for invalid %s %0*lx\n",
213 tsk->comm,213 tsk->comm,
214 write ? "write access to" : "read access from",214 write ? "write access to" : "read access from",
215 field, address);215 field, address);
216 pr_info("epc = %0*lx in", field,216 pr_info("epc = %0*lx in", field,
217 (unsigned long) regs->cp0_epc);217 (unsigned long) regs->cp0_epc);
218 print_vma_addr(" ", regs->cp0_epc);218 print_vma_addr(KERN_CONT " ", regs->cp0_epc);
219 pr_cont("\n");
219 pr_info("ra = %0*lx in", field,220 pr_info("ra = %0*lx in", field,
220 (unsigned long) regs->regs[31]);221 (unsigned long) regs->regs[31]);
221 print_vma_addr(" ", regs->regs[31]);222 print_vma_addr(KERN_CONT " ", regs->regs[31]);
222 pr_info("\n");223 pr_cont("\n");
223 }224 }
224 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;225 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
225 info.si_signo = SIGSEGV;226 info.si_signo = SIGSEGV;
arch/mips/mm/init.c+2−2
@@ -118,7 +118,7 @@ static void *__kmap_pgprot(struct page *page, unsigned long addr, pgprot_t prot) · 117 unmodified lines
118 writex_c0_entrylo1(entrylo);118 writex_c0_entrylo1(entrylo);
119 }119 }
120#endif120#endif
121 tlbidx = read_c0_wired();121 tlbidx = num_wired_entries();
122 write_c0_wired(tlbidx + 1);122 write_c0_wired(tlbidx + 1);
123 write_c0_index(tlbidx);123 write_c0_index(tlbidx);
124 mtc0_tlbw_hazard();124 mtc0_tlbw_hazard();
@@ -147,7 +147,7 @@ void kunmap_coherent(void) · 22 unmodified lines
147 147
148 local_irq_save(flags);148 local_irq_save(flags);
149 old_ctx = read_c0_entryhi();149 old_ctx = read_c0_entryhi();
150 wired = read_c0_wired() - 1;150 wired = num_wired_entries() - 1;
151 write_c0_wired(wired);151 write_c0_wired(wired);
152 write_c0_index(wired);152 write_c0_index(wired);
153 write_c0_entryhi(UNIQUE_ENTRYHI(wired));153 write_c0_entryhi(UNIQUE_ENTRYHI(wired));
arch/mips/mm/tlb-r4k.c+3−3
@@ -65,7 +65,7 @@ void local_flush_tlb_all(void) · 64 unmodified lines
65 write_c0_entrylo0(0);65 write_c0_entrylo0(0);
66 write_c0_entrylo1(0);66 write_c0_entrylo1(0);
67 67
68 entry = read_c0_wired();68 entry = num_wired_entries();
69 69
70 /*70 /*
71 * Blast 'em all away.71 * Blast 'em all away.
@@ -385,7 +385,7 @@ void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, · 313 unmodified lines
385 old_ctx = read_c0_entryhi();385 old_ctx = read_c0_entryhi();
386 htw_stop();386 htw_stop();
387 old_pagemask = read_c0_pagemask();387 old_pagemask = read_c0_pagemask();
388 wired = read_c0_wired();388 wired = num_wired_entries();
389 write_c0_wired(wired + 1);389 write_c0_wired(wired + 1);
390 write_c0_index(wired);390 write_c0_index(wired);
391 tlbw_use_hazard(); /* What is the hazard here? */391 tlbw_use_hazard(); /* What is the hazard here? */
@@ -449,7 +449,7 @@ __init int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1, · 57 unmodified lines
449 htw_stop();449 htw_stop();
450 old_ctx = read_c0_entryhi();450 old_ctx = read_c0_entryhi();
451 old_pagemask = read_c0_pagemask();451 old_pagemask = read_c0_pagemask();
452 wired = read_c0_wired();452 wired = num_wired_entries();
453 if (--temp_tlb_entry < wired) {453 if (--temp_tlb_entry < wired) {
454 printk(KERN_WARNING454 printk(KERN_WARNING
455 "No TLB space left for add_temporary_entry\n");455 "No TLB space left for add_temporary_entry\n");