After commit fc0c209c147f ("clk: Allow parents to be specified without string names") we can use DT or direct clk_hw pointers to specify parents. Create a generic function that shouldn't be used very often to encode the multitude of ways of registering a divider clk with different parent information. Then add a bunch of wrapper macros that only pass down what needs to be passed down to the generic function to support this with less arguments.
Unified · Split
| @@ -463,11 +463,12 @@ const struct clk_ops clk_divider_ro_ops = { · 462 unmodified lines | |||
| 463 | }; | 463 | }; |
| 464 | EXPORT_SYMBOL_GPL(clk_divider_ro_ops); | 464 | EXPORT_SYMBOL_GPL(clk_divider_ro_ops); |
| 465 | 465 | ||
| 466 | static struct clk_hw *_register_divider(struct device *dev, const char *name, | 466 | struct clk_hw *__clk_hw_register_divider(struct device *dev, |
| 467 | const char *parent_name, unsigned long flags, | 467 | struct device_node *np, const char *name, |
| 468 | void __iomem *reg, u8 shift, u8 width, | 468 | const char *parent_name, const struct clk_hw *parent_hw, |
| 469 | u8 clk_divider_flags, const struct clk_div_table *table, | 469 | const struct clk_parent_data *parent_data, unsigned long flags, |
| 470 | spinlock_t *lock) | 470 | void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, |
| 471 | const struct clk_div_table *table, spinlock_t *lock) | ||
| 471 | { | 472 | { |
| 472 | struct clk_divider *div; | 473 | struct clk_divider *div; |
| 473 | struct clk_hw *hw; | 474 | struct clk_hw *hw; |
| @@ -514,55 +515,7 @@ static struct clk_hw *_register_divider(struct device *dev, const char *name, · 40 unmodified lines | |||
| 514 | 515 | ||
| 515 | return hw; | 516 | return hw; |
| 516 | } | 517 | } |
| 517 | 518 | EXPORT_SYMBOL_GPL(__clk_hw_register_divider); | |
| 518 | /** | ||
| 519 | * clk_register_divider - register a divider clock with the clock framework | ||
| 520 | * @dev: device registering this clock | ||
| 521 | * @name: name of this clock | ||
| 522 | * @parent_name: name of clock's parent | ||
| 523 | * @flags: framework-specific flags | ||
| 524 | * @reg: register address to adjust divider | ||
| 525 | * @shift: number of bits to shift the bitfield | ||
| 526 | * @width: width of the bitfield | ||
| 527 | * @clk_divider_flags: divider-specific flags for this clock | ||
| 528 | * @lock: shared register lock for this clock | ||
| 529 | */ | ||
| 530 | struct clk *clk_register_divider(struct device *dev, const char *name, | ||
| 531 | const char *parent_name, unsigned long flags, | ||
| 532 | void __iomem *reg, u8 shift, u8 width, | ||
| 533 | u8 clk_divider_flags, spinlock_t *lock) | ||
| 534 | { | ||
| 535 | struct clk_hw *hw; | ||
| 536 | |||
| 537 | hw = _register_divider(dev, name, parent_name, flags, reg, shift, | ||
| 538 | width, clk_divider_flags, NULL, lock); | ||
| 539 | if (IS_ERR(hw)) | ||
| 540 | return ERR_CAST(hw); | ||
| 541 | return hw->clk; | ||
| 542 | } | ||
| 543 | EXPORT_SYMBOL_GPL(clk_register_divider); | ||
| 544 | |||
| 545 | /** | ||
| 546 | * clk_hw_register_divider - register a divider clock with the clock framework | ||
| 547 | * @dev: device registering this clock | ||
| 548 | * @name: name of this clock | ||
| 549 | * @parent_name: name of clock's parent | ||
| 550 | * @flags: framework-specific flags | ||
| 551 | * @reg: register address to adjust divider | ||
| 552 | * @shift: number of bits to shift the bitfield | ||
| 553 | * @width: width of the bitfield | ||
| 554 | * @clk_divider_flags: divider-specific flags for this clock | ||
| 555 | * @lock: shared register lock for this clock | ||
| 556 | */ | ||
| 557 | struct clk_hw *clk_hw_register_divider(struct device *dev, const char *name, | ||
| 558 | const char *parent_name, unsigned long flags, | ||
| 559 | void __iomem *reg, u8 shift, u8 width, | ||
| 560 | u8 clk_divider_flags, spinlock_t *lock) | ||
| 561 | { | ||
| 562 | return _register_divider(dev, name, parent_name, flags, reg, shift, | ||
| 563 | width, clk_divider_flags, NULL, lock); | ||
| 564 | } | ||
| 565 | EXPORT_SYMBOL_GPL(clk_hw_register_divider); | ||
| 566 | 519 | ||
| 567 | /** | 520 | /** |
| 568 | * clk_register_divider_table - register a table based divider clock with | 521 | * clk_register_divider_table - register a table based divider clock with |
| @@ -586,39 +539,15 @@ struct clk *clk_register_divider_table(struct device *dev, const char *name, · 17 unmodified lines | |||
| 586 | { | 539 | { |
| 587 | struct clk_hw *hw; | 540 | struct clk_hw *hw; |
| 588 | 541 | ||
| 589 | hw = _register_divider(dev, name, parent_name, flags, reg, shift, | 542 | hw = __clk_hw_register_divider(dev, NULL, name, parent_name, NULL, |
| 590 | width, clk_divider_flags, table, lock); | 543 | NULL, flags, reg, shift, width, clk_divider_flags, |
| 544 | table, lock); | ||
| 591 | if (IS_ERR(hw)) | 545 | if (IS_ERR(hw)) |
| 592 | return ERR_CAST(hw); | 546 | return ERR_CAST(hw); |
| 593 | return hw->clk; | 547 | return hw->clk; |
| 594 | } | 548 | } |
| 595 | EXPORT_SYMBOL_GPL(clk_register_divider_table); | 549 | EXPORT_SYMBOL_GPL(clk_register_divider_table); |
| 596 | 550 | ||
| 597 | /** | ||
| 598 | * clk_hw_register_divider_table - register a table based divider clock with | ||
| 599 | * the clock framework | ||
| 600 | * @dev: device registering this clock | ||
| 601 | * @name: name of this clock | ||
| 602 | * @parent_name: name of clock's parent | ||
| 603 | * @flags: framework-specific flags | ||
| 604 | * @reg: register address to adjust divider | ||
| 605 | * @shift: number of bits to shift the bitfield | ||
| 606 | * @width: width of the bitfield | ||
| 607 | * @clk_divider_flags: divider-specific flags for this clock | ||
| 608 | * @table: array of divider/value pairs ending with a div set to 0 | ||
| 609 | * @lock: shared register lock for this clock | ||
| 610 | */ | ||
| 611 | struct clk_hw *clk_hw_register_divider_table(struct device *dev, | ||
| 612 | const char *name, const char *parent_name, unsigned long flags, | ||
| 613 | void __iomem *reg, u8 shift, u8 width, | ||
| 614 | u8 clk_divider_flags, const struct clk_div_table *table, | ||
| 615 | spinlock_t *lock) | ||
| 616 | { | ||
| 617 | return _register_divider(dev, name, parent_name, flags, reg, shift, | ||
| 618 | width, clk_divider_flags, table, lock); | ||
| 619 | } | ||
| 620 | EXPORT_SYMBOL_GPL(clk_hw_register_divider_table); | ||
| 621 | |||
| 622 | void clk_unregister_divider(struct clk *clk) | 551 | void clk_unregister_divider(struct clk *clk) |
| 623 | { | 552 | { |
| 624 | struct clk_divider *div; | 553 | struct clk_divider *div; |
| @@ -626,24 +626,153 @@ int divider_get_val(unsigned long rate, unsigned long parent_rate, · 625 unmodified lines | |||
| 626 | const struct clk_div_table *table, u8 width, | 626 | const struct clk_div_table *table, u8 width, |
| 627 | unsigned long flags); | 627 | unsigned long flags); |
| 628 | 628 | ||
| 629 | struct clk *clk_register_divider(struct device *dev, const char *name, | 629 | struct clk_hw *__clk_hw_register_divider(struct device *dev, |
| 630 | const char *parent_name, unsigned long flags, | 630 | struct device_node *np, const char *name, |
| 631 | void __iomem *reg, u8 shift, u8 width, | 631 | const char *parent_name, const struct clk_hw *parent_hw, |
| 632 | u8 clk_divider_flags, spinlock_t *lock); | 632 | const struct clk_parent_data *parent_data, unsigned long flags, |
| 633 | struct clk_hw *clk_hw_register_divider(struct device *dev, const char *name, | 633 | void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, |
| 634 | const char *parent_name, unsigned long flags, | 634 | const struct clk_div_table *table, spinlock_t *lock); |
| 635 | void __iomem *reg, u8 shift, u8 width, | ||
| 636 | u8 clk_divider_flags, spinlock_t *lock); | ||
| 637 | struct clk *clk_register_divider_table(struct device *dev, const char *name, | 635 | struct clk *clk_register_divider_table(struct device *dev, const char *name, |
| 638 | const char *parent_name, unsigned long flags, | 636 | const char *parent_name, unsigned long flags, |
| 639 | void __iomem *reg, u8 shift, u8 width, | 637 | void __iomem *reg, u8 shift, u8 width, |
| 640 | u8 clk_divider_flags, const struct clk_div_table *table, | 638 | u8 clk_divider_flags, const struct clk_div_table *table, |
| 641 | spinlock_t *lock); | 639 | spinlock_t *lock); |
| 642 | struct clk_hw *clk_hw_register_divider_table(struct device *dev, | 640 | /** |
| 643 | const char *name, const char *parent_name, unsigned long flags, | 641 | * clk_register_divider - register a divider clock with the clock framework |
| 644 | void __iomem *reg, u8 shift, u8 width, | 642 | * @dev: device registering this clock |
| 645 | u8 clk_divider_flags, const struct clk_div_table *table, | 643 | * @name: name of this clock |
| 646 | spinlock_t *lock); | 644 | * @parent_name: name of clock's parent |
| 645 | * @flags: framework-specific flags | ||
| 646 | * @reg: register address to adjust divider | ||
| 647 | * @shift: number of bits to shift the bitfield | ||
| 648 | * @width: width of the bitfield | ||
| 649 | * @clk_divider_flags: divider-specific flags for this clock | ||
| 650 | * @lock: shared register lock for this clock | ||
| 651 | */ | ||
| 652 | #define clk_register_divider(dev, name, parent_name, flags, reg, shift, width, \ | ||
| 653 | clk_divider_flags, lock) \ | ||
| 654 | clk_register_divider_table((dev), (name), (parent_name), (flags), \ | ||
| 655 | (reg), (shift), (width), \ | ||
| 656 | (clk_divider_flags), NULL, (lock)) | ||
| 657 | /** | ||
| 658 | * clk_hw_register_divider - register a divider clock with the clock framework | ||
| 659 | * @dev: device registering this clock | ||
| 660 | * @name: name of this clock | ||
| 661 | * @parent_name: name of clock's parent | ||
| 662 | * @flags: framework-specific flags | ||
| 663 | * @reg: register address to adjust divider | ||
| 664 | * @shift: number of bits to shift the bitfield | ||
| 665 | * @width: width of the bitfield | ||
| 666 | * @clk_divider_flags: divider-specific flags for this clock | ||
| 667 | * @lock: shared register lock for this clock | ||
| 668 | */ | ||
| 669 | #define clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, \ | ||
| 670 | width, clk_divider_flags, lock) \ | ||
| 671 | __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \ | ||
| 672 | NULL, (flags), (reg), (shift), (width), \ | ||
| 673 | (clk_divider_flags), NULL, (lock)) | ||
| 674 | /** | ||
| 675 | * clk_hw_register_divider_parent_hw - register a divider clock with the clock | ||
| 676 | * framework | ||
| 677 | * @dev: device registering this clock | ||
| 678 | * @name: name of this clock | ||
| 679 | * @parent_hw: pointer to parent clk | ||
| 680 | * @flags: framework-specific flags | ||
| 681 | * @reg: register address to adjust divider | ||
| 682 | * @shift: number of bits to shift the bitfield | ||
| 683 | * @width: width of the bitfield | ||
| 684 | * @clk_divider_flags: divider-specific flags for this clock | ||
| 685 | * @lock: shared register lock for this clock | ||
| 686 | */ | ||
| 687 | #define clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags, reg, \ | ||
| 688 | shift, width, clk_divider_flags, \ | ||
| 689 | lock) \ | ||
| 690 | __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \ | ||
| 691 | NULL, (flags), (reg), (shift), (width), \ | ||
| 692 | (clk_divider_flags), NULL, (lock)) | ||
| 693 | /** | ||
| 694 | * clk_hw_register_divider_parent_data - register a divider clock with the clock | ||
| 695 | * framework | ||
| 696 | * @dev: device registering this clock | ||
| 697 | * @name: name of this clock | ||
| 698 | * @parent_data: parent clk data | ||
| 699 | * @flags: framework-specific flags | ||
| 700 | * @reg: register address to adjust divider | ||
| 701 | * @shift: number of bits to shift the bitfield | ||
| 702 | * @width: width of the bitfield | ||
| 703 | * @clk_divider_flags: divider-specific flags for this clock | ||
| 704 | * @lock: shared register lock for this clock | ||
| 705 | */ | ||
| 706 | #define clk_hw_register_divider_parent_data(dev, name, parent_data, flags, \ | ||
| 707 | reg, shift, width, \ | ||
| 708 | clk_divider_flags, lock) \ | ||
| 709 | __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \ | ||
| 710 | (parent_data), (flags), (reg), (shift), \ | ||
| 711 | (width), (clk_divider_flags), NULL, (lock)) | ||
| 712 | /** | ||
| 713 | * clk_hw_register_divider_table - register a table based divider clock with | ||
| 714 | * the clock framework | ||
| 715 | * @dev: device registering this clock | ||
| 716 | * @name: name of this clock | ||
| 717 | * @parent_name: name of clock's parent | ||
| 718 | * @flags: framework-specific flags | ||
| 719 | * @reg: register address to adjust divider | ||
| 720 | * @shift: number of bits to shift the bitfield | ||
| 721 | * @width: width of the bitfield | ||
| 722 | * @clk_divider_flags: divider-specific flags for this clock | ||
| 723 | * @table: array of divider/value pairs ending with a div set to 0 | ||
| 724 | * @lock: shared register lock for this clock | ||
| 725 | */ | ||
| 726 | #define clk_hw_register_divider_table(dev, name, parent_name, flags, reg, \ | ||
| 727 | shift, width, clk_divider_flags, table, \ | ||
| 728 | lock) \ | ||
| 729 | __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \ | ||
| 730 | NULL, (flags), (reg), (shift), (width), \ | ||
| 731 | (clk_divider_flags), (table), (lock)) | ||
| 732 | /** | ||
| 733 | * clk_hw_register_divider_table_parent_hw - register a table based divider | ||
| 734 | * clock with the clock framework | ||
| 735 | * @dev: device registering this clock | ||
| 736 | * @name: name of this clock | ||
| 737 | * @parent_hw: pointer to parent clk | ||
| 738 | * @flags: framework-specific flags | ||
| 739 | * @reg: register address to adjust divider | ||
| 740 | * @shift: number of bits to shift the bitfield | ||
| 741 | * @width: width of the bitfield | ||
| 742 | * @clk_divider_flags: divider-specific flags for this clock | ||
| 743 | * @table: array of divider/value pairs ending with a div set to 0 | ||
| 744 | * @lock: shared register lock for this clock | ||
| 745 | */ | ||
| 746 | #define clk_hw_register_divider_table_parent_hw(dev, name, parent_hw, flags, \ | ||
| 747 | reg, shift, width, \ | ||
| 748 | clk_divider_flags, table, \ | ||
| 749 | lock) \ | ||
| 750 | __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \ | ||
| 751 | NULL, (flags), (reg), (shift), (width), \ | ||
| 752 | (clk_divider_flags), (table), (lock)) | ||
| 753 | /** | ||
| 754 | * clk_hw_register_divider_table_parent_data - register a table based divider | ||
| 755 | * clock with the clock framework | ||
| 756 | * @dev: device registering this clock | ||
| 757 | * @name: name of this clock | ||
| 758 | * @parent_data: parent clk data | ||
| 759 | * @flags: framework-specific flags | ||
| 760 | * @reg: register address to adjust divider | ||
| 761 | * @shift: number of bits to shift the bitfield | ||
| 762 | * @width: width of the bitfield | ||
| 763 | * @clk_divider_flags: divider-specific flags for this clock | ||
| 764 | * @table: array of divider/value pairs ending with a div set to 0 | ||
| 765 | * @lock: shared register lock for this clock | ||
| 766 | */ | ||
| 767 | #define clk_hw_register_divider_table_parent_data(dev, name, parent_data, \ | ||
| 768 | flags, reg, shift, width, \ | ||
| 769 | clk_divider_flags, table, \ | ||
| 770 | lock) \ | ||
| 771 | __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \ | ||
| 772 | (parent_data), (flags), (reg), (shift), \ | ||
| 773 | (width), (clk_divider_flags), (table), \ | ||
| 774 | (lock)) | ||
| 775 | |||
| 647 | void clk_unregister_divider(struct clk *clk); | 776 | void clk_unregister_divider(struct clk *clk); |
| 648 | void clk_hw_unregister_divider(struct clk_hw *hw); | 777 | void clk_hw_unregister_divider(struct clk_hw *hw); |
| 649 | 778 | ||