lael-labs/linux

Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml+16−0

 examples:
   - |
+    #include <dt-bindings/clock/aspeed-clock.h>
     apb {
         compatible = "simple-bus";
         #address-cells = <1>;
         syscon: scu@1e6e2000 {
             compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd";
             reg = <0x1e6e2000 0x1a8>;
+            #clock-cells = <1>;
+            #reset-cells = <1>;
             pinctrl: pinctrl {
                 compatible = "aspeed,ast2500-pinctrl";
         gfx: display@1e6e6000 {
             compatible = "aspeed,ast2500-gfx", "syscon";
             reg = <0x1e6e6000 0x1000>;
+            reg-io-width = <4>;
+            clocks = <&syscon ASPEED_CLK_GATE_D1CLK>;
+            resets = <&syscon ASPEED_RESET_CRT1>;
+            interrupts = <0x19>;
+            syscon = <&syscon>;
+            memory-region = <&gfx_memory>;
         };
     };
             };
         };
     };
+    gfx_memory: framebuffer {
+        size = <0x01000000>;
+        alignment = <0x01000000>;
+        compatible = "shared-dma-pool";
+        reusable;
+    };

Documentation/devicetree/bindings/pinctrl/brcm,bcm11351-pinctrl.txt+1−1

@@ -85,7 +85,7 @@ Optional Properties (for I2C pins): · 84 unmodified lines
85	- function: String. Specifies the pin mux selection. Values	85	- function: String. Specifies the pin mux selection. Values
86	must be one of: "alt1", "alt2", "alt3", "alt4"	86	must be one of: "alt1", "alt2", "alt3", "alt4"
87	- bias-pull-up: Integer. Pull up strength in Ohm. There are 3	87	- bias-pull-up: Integer. Pull up strength in Ohm. There are 3
88	pull-up resisitors (1.2k, 1.8k, 2.7k) available	88	pull-up resistors (1.2k, 1.8k, 2.7k) available
89	in parallel for I2C pins, so the valid values	89	in parallel for I2C pins, so the valid values
90	are: 568, 720, 831, 1080, 1200, 1800, 2700 Ohm.	90	are: 568, 720, 831, 1080, 1200, 1800, 2700 Ohm.
91	- bias-disable: No arguments. Disable pin bias.	91	- bias-disable: No arguments. Disable pin bias.

Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml+72−0

@@ -0,0 +1,72 @@
	1	# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/pinctrl/brcm,bcm4908-pinctrl.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: Broadcom BCM4908 pin controller
	8
	9	maintainers:
	10	- Rafał Miłecki <rafal@milecki.pl>
	11
	12	description:
	13	Binding for pin controller present on BCM4908 family SoCs.
	14
	15	properties:
	16	compatible:
	17	const: brcm,bcm4908-pinctrl
	18
	19	reg:
	20	maxItems: 1
	21
	22	patternProperties:
	23	'-pins$':
	24	type: object
	25	$ref: pinmux-node.yaml#
	26
	27	properties:
	28	function:
	29	enum: [ led_0, led_1, led_2, led_3, led_4, led_5, led_6, led_7, led_8,
	30	led_9, led_10, led_11, led_12, led_13, led_14, led_15, led_16,
	31	led_17, led_18, led_19, led_20, led_21, led_22, led_23, led_24,
	32	led_25, led_26, led_27, led_28, led_29, led_30, led_31,
	33	hs_uart, i2c, i2s, nand_ctrl, nand_data, emmc_ctrl, usb0_pwr,
	34	usb1_pwr ]
	35
	36	groups:
	37	minItems: 1
	38	maxItems: 2
	39	items:
	40	enum: [ led_0_grp_a, led_1_grp_a, led_2_grp_a, led_3_grp_a,
	41	led_4_grp_a, led_5_grp_a, led_6_grp_a, led_7_grp_a,
	42	led_8_grp_a, led_9_grp_a, led_10_grp_a, led_10_grp_b,
	43	led_11_grp_a, led_11_grp_b, led_12_grp_a, led_12_grp_b,
	44	led_13_grp_a, led_13_grp_b, led_14_grp_a, led_15_grp_a,
	45	led_16_grp_a, led_17_grp_a, led_18_grp_a, led_19_grp_a,
	46	led_20_grp_a, led_21_grp_a, led_22_grp_a, led_23_grp_a,
	47	led_24_grp_a, led_25_grp_a, led_26_grp_a, led_27_grp_a,
	48	led_28_grp_a, led_29_grp_a, led_30_grp_a, led_31_grp_a,
	49	led_31_grp_b, hs_uart_grp, i2c_grp_a, i2c_grp_b, i2s_grp,
	50	nand_ctrl_grp, nand_data_grp, emmc_ctrl_grp, usb0_pwr_grp,
	51	usb1_pwr_grp ]
	52
	53	allOf:
	54	- $ref: pinctrl.yaml#
	55
	56	required:
	57	- compatible
	58	- reg
	59
	60	unevaluatedProperties: false
	61
	62	examples:
	63	- \|
	64	pinctrl@ff800560 {
	65	compatible = "brcm,bcm4908-pinctrl";
	66	reg = <0xff800560 0x10>;
	67
	68	led_0-a-pins {
	69	function = "led_0";
	70	groups = "led_0_grp_a";
	71	};
	72	};

Documentation/devicetree/bindings/pinctrl/fsl,imx93-pinctrl.yaml+85−0

@@ -0,0 +1,85 @@
	1	# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/pinctrl/fsl,imx93-pinctrl.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: Freescale IMX93 IOMUX Controller
	8
	9	maintainers:
	10	- Peng Fan <peng.fan@nxp.com>
	11
	12	description:
	13	Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
	14	for common binding part and usage.
	15
	16	allOf:
	17	- $ref: "pinctrl.yaml#"
	18
	19	properties:
	20	compatible:
	21	const: fsl,imx93-iomuxc
	22
	23	reg:
	24	maxItems: 1
	25
	26	# Client device subnode's properties
	27	patternProperties:
	28	'grp$':
	29	type: object
	30	description:
	31	Pinctrl node's client devices use subnodes for desired pin configuration.
	32	Client device subnodes use below standard properties.
	33
	34	properties:
	35	fsl,pins:
	36	description:
	37	each entry consists of 6 integers and represents the mux and config
	38	setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
	39	mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
	40	be found in <arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h>. The last
	41	integer CONFIG is the pad setting value like pull-up on this pin. Please
	42	refer to i.MX8M Plus Reference Manual for detailed CONFIG settings.
	43	$ref: /schemas/types.yaml#/definitions/uint32-matrix
	44	items:
	45	items:
	46	- description: \|
	47	"mux_reg" indicates the offset of mux register.
	48	- description: \|
	49	"conf_reg" indicates the offset of pad configuration register.
	50	- description: \|
	51	"input_reg" indicates the offset of select input register.
	52	- description: \|
	53	"mux_val" indicates the mux value to be applied.
	54	- description: \|
	55	"input_val" indicates the select input value to be applied.
	56	- description: \|
	57	"pad_setting" indicates the pad configuration value to be applied.
	58
	59
	60	required:
	61	- fsl,pins
	62
	63	additionalProperties: false
	64
	65	required:
	66	- compatible
	67	- reg
	68
	69	additionalProperties: false
	70
	71	examples:
	72	# Pinmux controller node
	73	- \|
	74	iomuxc: pinctrl@443c0000 {
	75	compatible = "fsl,imx93-iomuxc";
	76	reg = <0x30330000 0x10000>;
	77
	78	pinctrl_uart3: uart3grp {
	79	fsl,pins =
	80	<0x48 0x1f8 0x41c 0x1 0x0 0x49>,
	81	<0x4c 0x1fc 0x418 0x1 0x0 0x49>;
	82	};
	83	};
	84
	85	...

Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt+1−0

@@ -16,6 +16,7 @@ Required properties for the root node: · 15 unmodified lines
16	"amlogic,meson-g12a-periphs-pinctrl"	16	"amlogic,meson-g12a-periphs-pinctrl"
17	"amlogic,meson-g12a-aobus-pinctrl"	17	"amlogic,meson-g12a-aobus-pinctrl"
18	"amlogic,meson-a1-periphs-pinctrl"	18	"amlogic,meson-a1-periphs-pinctrl"
		19	"amlogic,meson-s4-periphs-pinctrl"
19	- reg: address and size of registers controlling irq functionality	20	- reg: address and size of registers controlling irq functionality
20		21
21	=== GPIO sub-nodes ===	22	=== GPIO sub-nodes ===

Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml+1−1

@@ -145,7 +145,7 @@ examples: · 144 unmodified lines
145	clocks = <&sys_clk>;	145	clocks = <&sys_clk>;
146	pinctrl-0 = <&sgpio2_pins>;	146	pinctrl-0 = <&sgpio2_pins>;
147	pinctrl-names = "default";	147	pinctrl-names = "default";
148	reg = <0x1101059c 0x100>;	148	reg = <0x1101059c 0x118>;
149	microchip,sgpio-port-ranges = <0 0>, <16 18>, <28 31>;	149	microchip,sgpio-port-ranges = <0 0>, <16 18>, <28 31>;
150	bus-frequency = <25000000>;	150	bus-frequency = <25000000>;
151	sgpio_in2: gpio@0 {	151	sgpio_in2: gpio@0 {

Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt+2−2

@@ -4,8 +4,8 @@ Microsemi Ocelot pin controller Device Tree Bindings · 3 unmodified lines
4	Required properties:	4	Required properties:
5	- compatible : Should be "mscc,ocelot-pinctrl",	5	- compatible : Should be "mscc,ocelot-pinctrl",
6	"mscc,jaguar2-pinctrl", "microchip,sparx5-pinctrl",	6	"mscc,jaguar2-pinctrl", "microchip,sparx5-pinctrl",
7	"mscc,luton-pinctrl", "mscc,serval-pinctrl" or	7	"mscc,luton-pinctrl", "mscc,serval-pinctrl",
8	"microchip,lan966x-pinctrl"	8	"microchip,lan966x-pinctrl" or "mscc,servalt-pinctrl"
9	- reg : Address and length of the register set for the device	9	- reg : Address and length of the register set for the device
10	- gpio-controller : Indicates this device is a GPIO controller	10	- gpio-controller : Indicates this device is a GPIO controller
11	- #gpio-cells : Must be 2.	11	- #gpio-cells : Must be 2.

Documentation/devicetree/bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml+160−0

@@ -0,0 +1,160 @@
	1	# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/pinctrl/nuvoton,wpcm450-pinctrl.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: Nuvoton WPCM450 pin control and GPIO
	8
	9	maintainers:
	10	- Jonathan Neuschäfer <j.neuschaefer@gmx.net>
	11
	12	properties:
	13	compatible:
	14	const: nuvoton,wpcm450-pinctrl
	15
	16	reg:
	17	maxItems: 1
	18
	19	'#address-cells':
	20	const: 1
	21
	22	'#size-cells':
	23	const: 0
	24
	25	patternProperties:
	26	# There are three kinds of subnodes:
	27	# 1. a GPIO controller node for each GPIO bank
	28	# 2. a pinmux node configures pin muxing for a group of pins (e.g. rmii2)
	29	# 3. a pinconf node configures properties of a single pin
	30
	31	"^gpio@[0-7]$":
	32	type: object
	33
	34	description:
	35	Eight GPIO banks (gpio@0 to gpio@7), that each contain between 14 and 18
	36	GPIOs. Some GPIOs support interrupts.
	37
	38	properties:
	39	reg:
	40	minimum: 0
	41	maximum: 7
	42
	43	gpio-controller: true
	44
	45	"#gpio-cells":
	46	const: 2
	47
	48	interrupt-controller: true
	49
	50	"#interrupt-cells":
	51	const: 2
	52
	53	interrupts:
	54	maxItems: 3
	55	description:
	56	The interrupts associated with this GPIO bank
	57
	58	required:
	59	- reg
	60	- gpio-controller
	61	- '#gpio-cells'
	62
	63	"^mux-":
	64	$ref: pinmux-node.yaml#
	65
	66	properties:
	67	groups:
	68	description:
	69	One or more groups of pins to mux to a certain function
	70	items:
	71	enum: [ smb3, smb4, smb5, scs1, scs2, scs3, smb0, smb1, smb2, bsp,
	72	hsp1, hsp2, r1err, r1md, rmii2, r2err, r2md, kbcc, dvo,
	73	clko, smi, uinc, gspi, mben, xcs2, xcs1, sdio, sspi, fi0,
	74	fi1, fi2, fi3, fi4, fi5, fi6, fi7, fi8, fi9, fi10, fi11,
	75	fi12, fi13, fi14, fi15, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5,
	76	pwm6, pwm7, hg0, hg1, hg2, hg3, hg4, hg5, hg6, hg7 ]
	77	function:
	78	description:
	79	The function that a group of pins is muxed to
	80	enum: [ smb3, smb4, smb5, scs1, scs2, scs3, smb0, smb1, smb2, bsp,
	81	hsp1, hsp2, r1err, r1md, rmii2, r2err, r2md, kbcc, dvo0,
	82	dvo1, dvo2, dvo3, dvo4, dvo5, dvo6, dvo7, clko, smi, uinc,
	83	gspi, mben, xcs2, xcs1, sdio, sspi, fi0, fi1, fi2, fi3, fi4,
	84	fi5, fi6, fi7, fi8, fi9, fi10, fi11, fi12, fi13, fi14, fi15,
	85	pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, pwm6, pwm7, hg0, hg1,
	86	hg2, hg3, hg4, hg5, hg6, hg7, gpio ]
	87
	88	dependencies:
	89	groups: [ function ]
	90	function: [ groups ]
	91
	92	additionalProperties: false
	93
	94	"^cfg-":
	95	$ref: pincfg-node.yaml#
	96
	97	properties:
	98	pins:
	99	description:
	100	A list of pins to configure in certain ways, such as enabling
	101	debouncing
	102	items:
	103	pattern: "^gpio1?[0-9]{1,2}$"
	104
	105	input-debounce: true
	106
	107	additionalProperties: false
	108
	109	required:
	110	- compatible
	111	- reg
	112
	113	additionalProperties: false
	114
	115	examples:
	116	- \|
	117	#include <dt-bindings/interrupt-controller/irq.h>
	118	#include <dt-bindings/gpio/gpio.h>
	119	pinctrl: pinctrl@b8003000 {
	120	compatible = "nuvoton,wpcm450-pinctrl";
	121	reg = <0xb8003000 0x1000>;
	122	#address-cells = <1>;
	123	#size-cells = <0>;
	124
	125	gpio0: gpio@0 {
	126	reg = <0>;
	127	gpio-controller;
	128	#gpio-cells = <2>;
	129	interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
	130	<3 IRQ_TYPE_LEVEL_HIGH>,
	131	<4 IRQ_TYPE_LEVEL_HIGH>;
	132	};
	133
	134	mux-rmii2 {
	135	groups = "rmii2";
	136	function = "rmii2";
	137	};
	138
	139	pinmux_uid: mux-uid {
	140	groups = "gspi", "sspi";
	141	function = "gpio";
	142	};
	143
	144	pinctrl_uid: cfg-uid {
	145	pins = "gpio14";
	146	input-debounce = <1>;
	147	};
	148	};
	149
	150	gpio-keys {
	151	compatible = "gpio-keys";
	152	pinctrl-names = "default";
	153	pinctrl-0 = <&pinctrl_uid>, <&pinmux_uid>;
	154
	155	uid {
	156	label = "UID";
	157	linux,code = <102>;
	158	gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
	159	};
	160	};

Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.yaml+297−0

@@ -0,0 +1,297 @@
	1	# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8186.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: Mediatek MT8186 Pin Controller
	8
	9	maintainers:
	10	- Sean Wang <sean.wang@mediatek.com>
	11
	12	description: \|
	13	The Mediatek's Pin controller is used to control SoC pins.
	14
	15	properties:
	16	compatible:
	17	const: mediatek,mt8186-pinctrl
	18
	19	gpio-controller: true
	20
	21	'#gpio-cells':
	22	description: \|
	23	Number of cells in GPIO specifier. Since the generic GPIO binding is used,
	24	the amount of cells must be specified as 2. See the below
	25	mentioned gpio binding representation for description of particular cells.
	26	const: 2
	27
	28	gpio-ranges:
	29	maxItems: 1
	30
	31	reg:
	32	description: \|
	33	Physical address base for gpio base registers. There are 8 different GPIO
	34	physical address base in mt8186.
	35	maxItems: 8
	36
	37	reg-names:
	38	description: \|
	39	Gpio base register names.
	40	items:
	41	- const: iocfg0
	42	- const: iocfg_bm
	43	- const: iocfg_bl
	44	- const: iocfg_br
	45	- const: iocfg_lm
	46	- const: iocfg_rb
	47	- const: iocfg_tl
	48	- const: eint
	49
	50	interrupt-controller: true
	51
	52	'#interrupt-cells':
	53	const: 2
	54
	55	interrupts:
	56	description: The interrupt outputs to sysirq
	57	maxItems: 1
	58
	59	mediatek,rsel-resistance-in-si-unit:
	60	type: boolean
	61	description: \|
	62	Identifying i2c pins pull up/down type which is RSEL. It can support
	63	RSEL define or si unit value(ohm) to set different resistance.
	64
	65	# PIN CONFIGURATION NODES
	66	patternProperties:
	67	'-pins$':
	68	type: object
	69	additionalProperties: false
	70	patternProperties:
	71	'^pins':
	72	type: object
	73	additionalProperties: false
	74	description: \|
	75	A pinctrl node should contain at least one subnodes representing the
	76	pinctrl groups available on the machine. Each subnode will list the
	77	pins it needs, and how they should be configured, with regard to muxer
	78	configuration, pullups, drive strength, input enable/disable and
	79	input schmitt.
	80	An example of using macro:
	81	pincontroller {
	82	/* GPIO0 set as multifunction GPIO0 */
	83	gpio-pins {
	84	pins {
	85	pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
	86	}
	87	};
	88	/* GPIO128 set as multifunction SDA0 */
	89	i2c0-pins {
	90	pins {
	91	pinmux = <PINMUX_GPIO128__FUNC_SDA0>;
	92	}
	93	};
	94	};
	95	$ref: "pinmux-node.yaml"
	96
	97	properties:
	98	pinmux:
	99	description: \|
	100	Integer array, represents gpio pin number and mux setting.
	101	Supported pin number and mux varies for different SoCs, and are
	102	defined as macros in dt-bindings/pinctrl/<soc>-pinfunc.h
	103	directly.
	104
	105	drive-strength:
	106	enum: [2, 4, 6, 8, 10, 12, 14, 16]
	107
	108	mediatek,drive-strength-adv:
	109	description: \|
	110	Describe the specific driving setup property.
	111	For I2C pins, the existing generic driving setup can only support
	112	2/4/6/8/10/12/14/16mA driving. But in specific driving setup, they
	113	can support 0.125/0.25/0.5/1mA adjustment. If we enable specific
	114	driving setup, the existing generic setup will be disabled.
	115	The specific driving setup is controlled by E1E0EN.
	116	When E1=0/E0=0, the strength is 0.125mA.
	117	When E1=0/E0=1, the strength is 0.25mA.
	118	When E1=1/E0=0, the strength is 0.5mA.
	119	When E1=1/E0=1, the strength is 1mA.
	120	EN is used to enable or disable the specific driving setup.
	121	Valid arguments are described as below:
	122	0: (E1, E0, EN) = (0, 0, 0)
	123	1: (E1, E0, EN) = (0, 0, 1)
	124	2: (E1, E0, EN) = (0, 1, 0)
	125	3: (E1, E0, EN) = (0, 1, 1)
	126	4: (E1, E0, EN) = (1, 0, 0)
	127	5: (E1, E0, EN) = (1, 0, 1)
	128	6: (E1, E0, EN) = (1, 1, 0)
	129	7: (E1, E0, EN) = (1, 1, 1)
	130	So the valid arguments are from 0 to 7.
	131	$ref: /schemas/types.yaml#/definitions/uint32
	132	enum: [0, 1, 2, 3, 4, 5, 6, 7]
	133
	134	bias-pull-down:
	135	oneOf:
	136	- type: boolean
	137	- enum: [100, 101, 102, 103]
	138	description: mt8186 pull down PUPD/R0/R1 type define value.
	139	- enum: [200, 201, 202, 203]
	140	description: mt8186 pull down RSEL type define value.
	141	- enum: [75000, 5000]
	142	description: mt8186 pull down RSEL type si unit value(ohm).
	143	description: \|
	144	For pull down type is normal, it don't need add RSEL & R1R0 define
	145	and resistance value.
	146	For pull down type is PUPD/R0/R1 type, it can add R1R0 define to
	147	set different resistance. It can support "MTK_PUPD_SET_R1R0_00" &
	148	"MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" &
	149	"MTK_PUPD_SET_R1R0_11" define in mt8186.
	150	For pull down type is RSEL, it can add RSEL define & resistance
	151	value(ohm) to set different resistance by identifying property
	152	"mediatek,rsel-resistance-in-si-unit".
	153	It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001"
	154	& "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011"
	155	define in mt8186. It can also support resistance value(ohm)
	156	"75000" & "5000" in mt8186.
	157	An example of using RSEL define:
	158	pincontroller {
	159	i2c0_pin {
	160	pins {
	161	pinmux = <PINMUX_GPIO128__FUNC_SDA0>;
	162	bias-pull-down = <MTK_PULL_SET_RSEL_001>;
	163	}
	164	};
	165	};
	166	An example of using si unit resistance value(ohm):
	167	&pio {
	168	mediatek,rsel-resistance-in-si-unit;
	169	}
	170	pincontroller {
	171	i2c0_pin {
	172	pins {
	173	pinmux = <PINMUX_GPIO128__FUNC_SDA0>;
	174	bias-pull-down = <75000>;
	175	}
	176	};
	177	};
	178
	179	bias-pull-up:
	180	oneOf:
	181	- type: boolean
	182	- enum: [100, 101, 102, 103]
	183	description: mt8186 pull up PUPD/R0/R1 type define value.
	184	- enum: [200, 201, 202, 203]
	185	description: mt8186 pull up RSEL type define value.
	186	- enum: [1000, 5000, 10000, 75000]
	187	description: mt8186 pull up RSEL type si unit value(ohm).
	188	description: \|
	189	For pull up type is normal, it don't need add RSEL & R1R0 define
	190	and resistance value.
	191	For pull up type is PUPD/R0/R1 type, it can add R1R0 define to
	192	set different resistance. It can support "MTK_PUPD_SET_R1R0_00" &
	193	"MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" &
	194	"MTK_PUPD_SET_R1R0_11" define in mt8186.
	195	For pull up type is RSEL, it can add RSEL define & resistance
	196	value(ohm) to set different resistance by identifying property
	197	"mediatek,rsel-resistance-in-si-unit".
	198	It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001"
	199	& "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011"
	200	define in mt8186. It can also support resistance value(ohm)
	201	"1000" & "5000" & "10000" & "75000" in mt8186.
	202	An example of using si unit resistance value(ohm):
	203	&pio {
	204	mediatek,rsel-resistance-in-si-unit;
	205	}
	206	pincontroller {
	207	i2c0-pins {
	208	pins {
	209	pinmux = <PINMUX_GPIO128__FUNC_SDA0>;
	210	bias-pull-up = <1000>;
	211	}
	212	};
	213	};
	214
	215	bias-disable: true
	216
	217	output-high: true
	218
	219	output-low: true
	220
	221	input-enable: true
	222
	223	input-disable: true
	224
	225	input-schmitt-enable: true
	226
	227	input-schmitt-disable: true
	228
	229	required:
	230	- pinmux
	231
	232	required:
	233	- compatible
	234	- reg
	235	- interrupts
	236	- interrupt-controller
	237	- '#interrupt-cells'
	238	- gpio-controller
	239	- '#gpio-cells'
	240	- gpio-ranges
	241
	242	additionalProperties: false
	243
	244	examples:
	245	- \|
	246	#include <dt-bindings/pinctrl/mt8186-pinfunc.h>
	247	#include <dt-bindings/interrupt-controller/arm-gic.h>
	248
	249	pio: pinctrl@10005000 {
	250	compatible = "mediatek,mt8186-pinctrl";
	251	reg = <0x10005000 0x1000>,
	252	<0x10002000 0x0200>,
	253	<0x10002200 0x0200>,
	254	<0x10002400 0x0200>,
	255	<0x10002600 0x0200>,
	256	<0x10002A00 0x0200>,
	257	<0x10002c00 0x0200>,
	258	<0x1000b000 0x1000>;
	259	reg-names = "iocfg0", "iocfg_bm", "iocfg_bl",
	260	"iocfg_br", "iocfg_lm", "iocfg_rb",
	261	"iocfg_tl", "eint";
	262	gpio-controller;
	263	#gpio-cells = <2>;
	264	gpio-ranges = <&pio 0 0 185>;
	265	interrupt-controller;
	266	interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>;
	267	#interrupt-cells = <2>;
	268
	269	pio-pins {
	270	pins {
	271	pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
	272	output-low;
	273	};
	274	};
	275
	276	spi0-pins {
	277	pins-spi {
	278	pinmux = <PINMUX_GPIO0__FUNC_SPI0_CLK_B>,
	279	<PINMUX_GPIO1__FUNC_SPI0_CSB_B>,
	280	<PINMUX_GPIO2__FUNC_SPI0_MO_B>;
	281	bias-disable;
	282	};
	283	pins-spi-mi {
	284	pinmux = <PINMUX_GPIO3__FUNC_SPI0_MI_B>;
	285	bias-pull-down;
	286	};
	287	};
	288
	289	i2c0-pins {
	290	pins {
	291	pinmux = <PINMUX_GPIO127__FUNC_SCL0>,
	292	<PINMUX_GPIO128__FUNC_SDA0>;
	293	bias-pull-up = <MTK_PULL_SET_RSEL_001>;
	294	mediatek,drive-strength-adv = <7>;
	295	};
	296	};
	297	};

Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml+51−14

@@ -98,7 +98,41 @@ patternProperties: · 97 unmodified lines
98	drive-strength:	98	drive-strength:
99	enum: [2, 4, 6, 8, 10, 12, 14, 16]	99	enum: [2, 4, 6, 8, 10, 12, 14, 16]
100		100
		101	mediatek,drive-strength-adv:
		102	description: \|
		103	Describe the specific driving setup property.
		104	For I2C pins, the existing generic driving setup can only support
		105	2/4/6/8/10/12/14/16mA driving. But in specific driving setup, they
		106	can support 0.125/0.25/0.5/1mA adjustment. If we enable specific
		107	driving setup, the existing generic setup will be disabled.
		108	The specific driving setup is controlled by E1E0EN.
		109	When E1=0/E0=0, the strength is 0.125mA.
		110	When E1=0/E0=1, the strength is 0.25mA.
		111	When E1=1/E0=0, the strength is 0.5mA.
		112	When E1=1/E0=1, the strength is 1mA.
		113	EN is used to enable or disable the specific driving setup.
		114	Valid arguments are described as below:
		115	0: (E1, E0, EN) = (0, 0, 0)
		116	1: (E1, E0, EN) = (0, 0, 1)
		117	2: (E1, E0, EN) = (0, 1, 0)
		118	3: (E1, E0, EN) = (0, 1, 1)
		119	4: (E1, E0, EN) = (1, 0, 0)
		120	5: (E1, E0, EN) = (1, 0, 1)
		121	6: (E1, E0, EN) = (1, 1, 0)
		122	7: (E1, E0, EN) = (1, 1, 1)
		123	So the valid arguments are from 0 to 7.
		124	$ref: /schemas/types.yaml#/definitions/uint32
		125	enum: [0, 1, 2, 3, 4, 5, 6, 7]
		126
101	bias-pull-down:	127	bias-pull-down:
		128	oneOf:
		129	- type: boolean
		130	- enum: [100, 101, 102, 103]
		131	description: mt8195 pull down PUPD/R0/R1 type define value.
		132	- enum: [200, 201, 202, 203, 204, 205, 206, 207]
		133	description: mt8195 pull down RSEL type define value.
		134	- enum: [75000, 5000]
		135	description: mt8195 pull down RSEL type si unit value(ohm).
102	description: \|	136	description: \|
103	For pull down type is normal, it don't need add RSEL & R1R0 define	137	For pull down type is normal, it don't need add RSEL & R1R0 define
104	and resistance value.	138	and resistance value.
@@ -115,13 +149,6 @@ patternProperties: · 10 unmodified lines
115	& "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111"	149	& "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111"
116	define in mt8195. It can also support resistance value(ohm)	150	define in mt8195. It can also support resistance value(ohm)
117	"75000" & "5000" in mt8195.	151	"75000" & "5000" in mt8195.
118	oneOf:
119	- enum: [100, 101, 102, 103]
120	- description: mt8195 pull down PUPD/R0/R1 type define value.
121	- enum: [200, 201, 202, 203, 204, 205, 206, 207]
122	- description: mt8195 pull down RSEL type define value.
123	- enum: [75000, 5000]
124	- description: mt8195 pull down RSEL type si unit value(ohm).
125		152
126	An example of using RSEL define:	153	An example of using RSEL define:
127	pincontroller {	154	pincontroller {
@@ -146,6 +173,14 @@ patternProperties: · 18 unmodified lines
146	};	173	};
147		174
148	bias-pull-up:	175	bias-pull-up:
		176	oneOf:
		177	- type: boolean
		178	- enum: [100, 101, 102, 103]
		179	description: mt8195 pull up PUPD/R0/R1 type define value.
		180	- enum: [200, 201, 202, 203, 204, 205, 206, 207]
		181	description: mt8195 pull up RSEL type define value.
		182	- enum: [1000, 1500, 2000, 3000, 4000, 5000, 10000, 75000]
		183	description: mt8195 pull up RSEL type si unit value(ohm).
149	description: \|	184	description: \|
150	For pull up type is normal, it don't need add RSEL & R1R0 define	185	For pull up type is normal, it don't need add RSEL & R1R0 define
151	and resistance value.	186	and resistance value.
@@ -163,13 +198,6 @@ patternProperties: · 11 unmodified lines
163	define in mt8195. It can also support resistance value(ohm)	198	define in mt8195. It can also support resistance value(ohm)
164	"1000" & "1500" & "2000" & "3000" & "4000" & "5000" & "10000" &	199	"1000" & "1500" & "2000" & "3000" & "4000" & "5000" & "10000" &
165	"75000" in mt8195.	200	"75000" in mt8195.
166	oneOf:
167	- enum: [100, 101, 102, 103]
168	- description: mt8195 pull up PUPD/R0/R1 type define value.
169	- enum: [200, 201, 202, 203, 204, 205, 206, 207]
170	- description: mt8195 pull up RSEL type define value.
171	- enum: [1000, 1500, 2000, 3000, 4000, 5000, 10000, 75000]
172	- description: mt8195 pull up RSEL type si unit value(ohm).
173	An example of using RSEL define:	201	An example of using RSEL define:
174	pincontroller {	202	pincontroller {
175	i2c0-pins {	203	i2c0-pins {
@@ -268,4 +296,13 @@ examples: · 92 unmodified lines
268	bias-pull-down;	296	bias-pull-down;
269	};	297	};
270	};	298	};
		299
		300	i2c0-pins {
		301	pins {
		302	pinmux = <PINMUX_GPIO8__FUNC_SDA0>,
		303	<PINMUX_GPIO9__FUNC_SCL0>;
		304	bias-disable;
		305	mediatek,drive-strength-adv = <7>;
		306	};
		307	};
271	};	308	};

Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml+2−0

@@ -34,6 +34,8 @@ properties: · 33 unmodified lines
34		34
35	gpio-controller: true	35	gpio-controller: true
36		36
		37	gpio-reserved-ranges: true
		38
37	'#gpio-cells':	39	'#gpio-cells':
38	description: Specifying the pin number and flags, as defined in	40	description: Specifying the pin number and flags, as defined in
39	include/dt-bindings/gpio/gpio.h	41	include/dt-bindings/gpio/gpio.h

Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml+1−0

@@ -36,6 +36,7 @@ properties: · 35 unmodified lines
36	- qcom,pm8350-gpio	36	- qcom,pm8350-gpio
37	- qcom,pm8350b-gpio	37	- qcom,pm8350b-gpio
38	- qcom,pm8350c-gpio	38	- qcom,pm8350c-gpio
		39	- qcom,pm8450-gpio
39	- qcom,pm8916-gpio	40	- qcom,pm8916-gpio
40	- qcom,pm8917-gpio	41	- qcom,pm8917-gpio
41	- qcom,pm8921-gpio	42	- qcom,pm8921-gpio

Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml+1−0

@@ -21,6 +21,7 @@ properties: · 20 unmodified lines
21	- qcom,pm8019-mpp	21	- qcom,pm8019-mpp
22	- qcom,pm8038-mpp	22	- qcom,pm8038-mpp
23	- qcom,pm8058-mpp	23	- qcom,pm8058-mpp
		24	- qcom,pm8226-mpp
24	- qcom,pm8821-mpp	25	- qcom,pm8821-mpp
25	- qcom,pm8841-mpp	26	- qcom,pm8841-mpp
26	- qcom,pm8916-mpp	27	- qcom,pm8916-mpp

Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-pinctrl.yaml+151−0

@@ -0,0 +1,151 @@
	1	# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/pinctrl/qcom,sc8280xp-pinctrl.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: Qualcomm Technologies, Inc. SC8280XP TLMM block
	8
	9	maintainers:
	10	- Bjorn Andersson <bjorn.andersson@linaro.org>
	11
	12	description: \|
	13	This binding describes the Top Level Mode Multiplexer block found in the
	14	SC8280XP platform.
	15
	16	allOf:
	17	- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
	18
	19	properties:
	20	compatible:
	21	const: qcom,sc8280xp-tlmm
	22
	23	reg:
	24	maxItems: 1
	25
	26	interrupts: true
	27	interrupt-controller: true
	28	'#interrupt-cells': true
	29	gpio-controller: true
	30	gpio-reserved-ranges: true
	31	'#gpio-cells': true
	32	gpio-ranges: true
	33	wakeup-parent: true
	34
	35	required:
	36	- compatible
	37	- reg
	38
	39	additionalProperties: false
	40
	41	patternProperties:
	42	'-state$':
	43	oneOf:
	44	- $ref: "#/$defs/qcom-sc8280xp-tlmm-state"
	45	- patternProperties:
	46	".*":
	47	$ref: "#/$defs/qcom-sc8280xp-tlmm-state"
	48
	49	'$defs':
	50	qcom-sc8280xp-tlmm-state:
	51	type: object
	52	description:
	53	Pinctrl node's client devices use subnodes for desired pin configuration.
	54	Client device subnodes use below standard properties.
	55	$ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
	56
	57	properties:
	58	pins:
	59	description:
	60	List of gpio pins affected by the properties specified in this
	61	subnode.
	62	items:
	63	oneOf:
	64	- pattern: "^gpio([0-9]\|[1-9][0-9]\|1[0-9][0-9]\|2[0-1][0-9]\|22[0-7])$"
	65	- enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset, ufs1_reset ]
	66	minItems: 1
	67	maxItems: 16
	68
	69	function:
	70	description:
	71	Specify the alternative function to be configured for the specified
	72	pins.
	73
	74	enum: [ atest_char, atest_usb, audio_ref, cam_mclk, cci_async, cci_i2c,
	75	cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
	76	cci_timer5, cci_timer6, cci_timer7, cci_timer8, cci_timer9,
	77	cmu_rng, cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist,
	78	ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, ddr_pxi4, ddr_pxi5,
	79	ddr_pxi6, ddr_pxi7, dp2_hot, dp3_hot, edp0_lcd, edp1_lcd,
	80	edp2_lcd, edp3_lcd, edp_hot, emac0_dll, emac0_mcg0, emac0_mcg1,
	81	emac0_mcg2, emac0_mcg3, emac0_phy, emac0_ptp, emac1_dll0,
	82	emac1_dll1, emac1_mcg0, emac1_mcg1, emac1_mcg2, emac1_mcg3,
	83	emac1_phy, emac1_ptp, gcc_gp1, gcc_gp2, gcc_gp3, gcc_gp4,
	84	gcc_gp5, gpio, hs1_mi2s, hs2_mi2s, hs3_mi2s, ibi_i3c,
	85	jitter_bist, lpass_slimbus, mdp0_vsync0, mdp0_vsync1,
	86	mdp0_vsync2, mdp0_vsync3, mdp0_vsync4, mdp0_vsync5,
	87	mdp0_vsync6, mdp0_vsync7, mdp0_vsync8, mdp1_vsync0,
	88	mdp1_vsync1, mdp1_vsync2, mdp1_vsync3, mdp1_vsync4,
	89	mdp1_vsync5, mdp1_vsync6, mdp1_vsync7, mdp1_vsync8, mdp_vsync,
	90	mi2s0_data0, mi2s0_data1, mi2s0_sck, mi2s0_ws, mi2s1_data0,
	91	mi2s1_data1, mi2s1_sck, mi2s1_ws, mi2s2_data0, mi2s2_data1,
	92	mi2s2_sck, mi2s2_ws, mi2s_mclk1, mi2s_mclk2, pcie2a_clkreq,
	93	pcie2b_clkreq, pcie3a_clkreq, pcie3b_clkreq, pcie4_clkreq,
	94	phase_flag, pll_bist, pll_clk, prng_rosc0, prng_rosc1,
	95	prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio, qspi, qspi_clk,
	96	qspi_cs, qup0, qup1, qup2, qup3, qup4, qup5, qup6, qup7, qup8,
	97	qup9, qup10, qup11, qup12, qup13, qup14, qup15, qup16, qup17,
	98	qup18, qup19, qup20, qup21, qup22, qup23, rgmii_0, rgmii_1,
	99	sd_write, sdc40, sdc42, sdc43, sdc4_clk, sdc4_cmd, tb_trig,
	100	tgu, tsense_pwm1, tsense_pwm2, tsense_pwm3, tsense_pwm4,
	101	usb0_dp, usb0_phy, usb0_sbrx, usb0_sbtx, usb0_usb4, usb1_dp,
	102	usb1_phy, usb1_sbrx, usb1_sbtx, usb1_usb4, usb2phy_ac,
	103	vsense_trigger ]
	104
	105	bias-disable: true
	106	bias-pull-down: true
	107	bias-pull-up: true
	108	drive-strength: true
	109	input-enable: true
	110	output-high: true
	111	output-low: true
	112
	113	required:
	114	- pins
	115	- function
	116
	117	additionalProperties: false
	118
	119	examples:
	120	- \|
	121	#include <dt-bindings/interrupt-controller/arm-gic.h>
	122	pinctrl@f100000 {
	123	compatible = "qcom,sc8280xp-tlmm";
	124	reg = <0x0f100000 0x300000>;
	125	interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
	126	gpio-controller;
	127	#gpio-cells = <2>;
	128	interrupt-controller;
	129	#interrupt-cells = <2>;
	130	gpio-ranges = <&tlmm 0 0 230>;
	131
	132	gpio-wo-subnode-state {
	133	pins = "gpio1";
	134	function = "gpio";
	135	};
	136
	137	uart-w-subnodes-state {
	138	rx {
	139	pins = "gpio4";
	140	function = "qup14";
	141	bias-pull-up;
	142	};
	143
	144	tx {
	145	pins = "gpio5";
	146	function = "qup14";
	147	bias-disable;
	148	};
	149	};
	150	};
	151	...

Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml+0−1

@@ -73,7 +73,6 @@ $defs: · 72 unmodified lines
73	properties:	73	properties:
74	drive-strength:	74	drive-strength:
75	enum: [2, 4, 6, 8, 10, 12, 14, 16]	75	enum: [2, 4, 6, 8, 10, 12, 14, 16]
76	default: 2
77	description:	76	description:
78	Selects the drive strength for the specified pins, in mA.	77	Selects the drive strength for the specified pins, in mA.
79		78

Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinmux.yaml+6−5

   - Sergio Paracuellos <sergio.paracuellos@gmail.com>
 description:
-  The rt2880 pinmux can only set the muxing of pin groups. muxing indiviual pins
+  The rt2880 pinmux can only set the muxing of pin groups. Muxing indiviual pins
   is not supported. There is no pinconf support.
 properties:
         properties:
           groups:
             description: Name of the pin group to use for the functions.
-            enum: [i2c, spi, uart1, uart2, uart3, rgmii1, rgmii2, mdio,
+            enum: [i2c, jtag, mdio, pcie, rgmii1, rgmii2, sdhci, spi,
-                   pcie, sdhci]
+                   uart1, uart2, uart3, wdt]
           function:
             description: The mux function to select
-            enum: [gpio, i2c, spi, uart1, uart2, uart3, rgmii1, rgmii2,
+            enum: [gpio, i2c, i2s, jtag, mdio, nand1, nand2, pcie refclk,
-                   mdio, nand1, nand2, sdhci]
+                   pcie rst, pcm, rgmii1, rgmii2, sdhci, spdif2, spdif3,
+                   spi, uart1, uart2, uart3, wdt refclk, wdt rst]
         required:
           - groups

Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml+1−0

@@ -44,6 +44,7 @@ properties: · 43 unmodified lines
44	- renesas,pfc-r8a77990 # R-Car E3	44	- renesas,pfc-r8a77990 # R-Car E3
45	- renesas,pfc-r8a77995 # R-Car D3	45	- renesas,pfc-r8a77995 # R-Car D3
46	- renesas,pfc-r8a779a0 # R-Car V3U	46	- renesas,pfc-r8a779a0 # R-Car V3U
		47	- renesas,pfc-r8a779f0 # R-Car S4-8
47	- renesas,pfc-sh73a0 # SH-Mobile AG5	48	- renesas,pfc-sh73a0 # SH-Mobile AG5
48		49
49	reg:	50	reg:

Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml+12−4

 $id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Renesas RZ/G2L combined Pin and GPIO controller
+title: Renesas RZ/{G2L,V2L} combined Pin and GPIO controller
 maintainers:
   - Geert Uytterhoeven <geert+renesas@glider.be>
   - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
 description:
-  The Renesas SoCs of the RZ/G2L series feature a combined Pin and GPIO
+  The Renesas SoCs of the RZ/{G2L,V2L} series feature a combined Pin and GPIO
   controller.
   Pin multiplexing and GPIO configuration is performed on a per-pin basis.
   Each port features up to 8 pins, each of them configurable for GPIO function
 properties:
   compatible:
-    enum:
+    oneOf:
-      - renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
+      - items:
+          - enum:
+              - renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
+      - items:
+          - enum:
+              - renesas,r9a07g054-pinctrl     # RZ/V2L
+          - const: renesas,r9a07g044-pinctrl  # RZ/G2{L,LC} fallback for RZ/V2L
   reg:
     maxItems: 1
         output-impedance-ohms:
           enum: [ 33, 50, 66, 100 ]
         power-source:
+          description: I/O voltage in millivolt.
           enum: [ 1800, 2500, 3300 ]
         slew-rate: true
         gpio-hog: true

Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml+1−0

@@ -56,6 +56,7 @@ properties: · 55 unmodified lines
56	- samsung,exynos7885-pinctrl	56	- samsung,exynos7885-pinctrl
57	- samsung,exynos850-pinctrl	57	- samsung,exynos850-pinctrl
58	- samsung,exynosautov9-pinctrl	58	- samsung,exynosautov9-pinctrl
		59	- tesla,fsd-pinctrl
59		60
60	interrupts:	61	interrupts:
61	description:	62	description:

Documentation/devicetree/bindings/pinctrl/sunplus,sp7021-pinctrl.yaml+374−0

@@ -0,0 +1,374 @@
	1	# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	2	# Copyright (C) Sunplus Co., Ltd.
	3	%YAML 1.2
	4	---
	5	$id: http://devicetree.org/schemas/pinctrl/sunplus,sp7021-pinctrl.yaml#
	6	$schema: http://devicetree.org/meta-schemas/core.yaml#
	7
	8	title: Sunplus SP7021 Pin Controller Device Tree Bindings
	9
	10	maintainers:
	11	- Dvorkin Dmitry <dvorkin@tibbo.com>
	12	- Wells Lu <wellslutw@gmail.com>
	13
	14	description: \|
	15	The Sunplus SP7021 pin controller is used to control SoC pins. Please
	16	refer to pinctrl-bindings.txt in this directory for details of the common
	17	pinctrl bindings used by client devices.
	18
	19	SP7021 has 99 digital GPIO pins which are numbered from GPIO 0 to 98. All
	20	are multiplexed with some special function pins. SP7021 has 3 types of
	21	special function pins:
	22
	23	(1) function-group pins:
	24	Ex 1 (SPI-NOR flash):
	25	If control-field SPI_FLASH_SEL is set to 1, GPIO 83, 84, 86 and 87
	26	will be pins of SPI-NOR flash. If it is set to 2, GPIO 76, 78, 79
	27	and 81 will be pins of SPI-NOR flash.
	28
	29	Ex 2 (UART_0):
	30	If control-bit UA0_SEL is set to 1, GPIO 88 and 89 will be TX and
	31	RX pins of UART_0 (UART channel 0).
	32
	33	Ex 3 (eMMC):
	34	If control-bit EMMC_SEL is set to 1, GPIO 72, 73, 74, 75, 76, 77,
	35	78, 79, 80, 81 will be pins of an eMMC device.
	36
	37	Properties "function" and "groups" are used to select function-group
	38	pins.
	39
	40	(2) fully pin-mux (like phone exchange mux) pins:
	41	GPIO 8 to 71 are 'fully pin-mux' pins. Any pins of peripherals of
	42	SP7021 (ex: UART_1, UART_2, UART_3, UART_4, I2C_0, I2C_1, and etc.)
	43	can be routed to any pins of fully pin-mux pins.
	44
	45	Ex 1 (UART channel 1):
	46	If control-field UA1_TX_SEL is set to 3, TX pin of UART_1 will be
	47	routed to GPIO 10 (3 - 1 + 8 = 10).
	48	If control-field UA1_RX_SEL is set to 4, RX pin of UART_1 will be
	49	routed to GPIO 11 (4 - 1 + 8 = 11).
	50	If control-field UA1_RTS_SEL is set to 5, RTS pin of UART_1 will
	51	be routed to GPIO 12 (5 - 1 + 8 = 12).
	52	If control-field UA1_CTS_SEL is set to 6, CTS pin of UART_1 will
	53	be routed to GPIO 13 (6 - 1 + 8 = 13).
	54
	55	Ex 2 (I2C channel 0):
	56	If control-field I2C0_CLK_SEL is set to 20, CLK pin of I2C_0 will
	57	be routed to GPIO 27 (20 - 1 + 8 = 27).
	58	If control-field I2C0_DATA_SEL is set to 21, DATA pin of I2C_0
	59	will be routed to GPIO 28 (21 - 1 + 9 = 28).
	60
	61	Totally, SP7021 has 120 peripheral pins. The peripheral pins can be
	62	routed to any of 64 'fully pin-mux' pins.
	63
	64	(3) I/O processor pins
	65	SP7021 has a built-in I/O processor.
	66	Any GPIO pins (GPIO 0 to 98) can be set to pins of I/O processor.
	67
	68	Vendor property "sunplus,pins" is used to select "fully pin-mux" pins,
	69	"I/O processor pins" and "digital GPIO" pins.
	70
	71	The device node of pin controller of Sunplus SP7021 has following
	72	properties.
	73
	74	properties:
	75	compatible:
	76	const: sunplus,sp7021-pctl
	77
	78	gpio-controller: true
	79
	80	'#gpio-cells':
	81	const: 2
	82
	83	reg:
	84	items:
	85	- description: the MOON2 registers
	86	- description: the GPIOXT registers
	87	- description: the FIRST registers
	88	- description: the MOON1 registers
	89
	90	reg-names:
	91	items:
	92	- const: moon2
	93	- const: gpioxt
	94	- const: first
	95	- const: moon1
	96
	97	clocks:
	98	maxItems: 1
	99
	100	resets:
	101	maxItems: 1
	102
	103	patternProperties:
	104	'-pins$':
	105	type: object
	106	description: \|
	107	A pinctrl node should contain at least one subnodes representing the
	108	pins or function-pins group available on the machine. Each subnode
	109	will list the pins it needs, and how they should be configured.
	110
	111	Pinctrl node's client devices use subnodes for desired pin
	112	configuration. Client device subnodes use below standard properties.
	113	$ref: pinmux-node.yaml#
	114
	115	properties:
	116	sunplus,pins:
	117	description: \|
	118	Define 'sunplus,pins' which are used by pinctrl node's client
	119	device.
	120
	121	It consists of one or more integers which represents the config
	122	setting for corresponding pin. Each integer defines a individual
	123	pin in which:
	124
	125	Bit 32~24: defines GPIO number. Its range is 0 ~ 98.
	126	Bit 23~16: defines types: (1) fully pin-mux pins
	127	(2) IO processor pins
	128	(3) digital GPIO pins
	129	Bit 15~8: defines pins of peripherals (which are defined in
	130	'include/dt-binging/pinctrl/sppctl.h').
	131	Bit 7~0: defines types or initial-state of digital GPIO pins.
	132
	133	Please use macro SPPCTL_IOPAD to define the integers for pins.
	134
	135	$ref: /schemas/types.yaml#/definitions/uint32-array
	136
	137	function:
	138	description: \|
	139	Define pin-function which is used by pinctrl node's client device.
	140	The name should be one of string in the following enumeration.
	141	$ref: "/schemas/types.yaml#/definitions/string"
	142	enum: [ SPI_FLASH, SPI_FLASH_4BIT, SPI_NAND, CARD0_EMMC, SD_CARD,
	143	UA0, FPGA_IFX, HDMI_TX, LCDIF, USB0_OTG, USB1_OTG ]
	144
	145	groups:
	146	description: \|
	147	Define pin-group in a specified pin-function.
	148	The name should be one of string in the following enumeration.
	149	$ref: "/schemas/types.yaml#/definitions/string"
	150	enum: [ SPI_FLASH1, SPI_FLASH2, SPI_FLASH_4BIT1, SPI_FLASH_4BIT2,
	151	SPI_NAND, CARD0_EMMC, SD_CARD, UA0, FPGA_IFX, HDMI_TX1,
	152	HDMI_TX2, HDMI_TX3, LCDIF, USB0_OTG, USB1_OTG ]
	153
	154	sunplus,zerofunc:
	155	description: \|
	156	This is a vendor specific property. It is used to disable pins
	157	which are not used by pinctrl node's client device.
	158	Some pins may be enabled by boot-loader. We can use this
	159	property to disable them.
	160	$ref: /schemas/types.yaml#/definitions/uint32-array
	161
	162	additionalProperties: false
	163
	164	allOf:
	165	- if:
	166	properties:
	167	function:
	168	enum:
	169	- SPI_FLASH
	170	then:
	171	properties:
	172	groups:
	173	enum:
	174	- SPI_FLASH1
	175	- SPI_FLASH2
	176	- if:
	177	properties:
	178	function:
	179	enum:
	180	- SPI_FLASH_4BIT
	181	then:
	182	properties:
	183	groups:
	184	enum:
	185	- SPI_FLASH_4BIT1
	186	- SPI_FLASH_4BIT2
	187	- if:
	188	properties:
	189	function:
	190	enum:
	191	- SPI_NAND
	192	then:
	193	properties:
	194	groups:
	195	enum:
	196	- SPI_NAND
	197	- if:
	198	properties:
	199	function:
	200	enum:
	201	- CARD0_EMMC
	202	then:
	203	properties:
	204	groups:
	205	enum:
	206	- CARD0_EMMC
	207	- if:
	208	properties:
	209	function:
	210	enum:
	211	- SD_CARD
	212	then:
	213	properties:
	214	groups:
	215	enum:
	216	- SD_CARD
	217	- if:
	218	properties:
	219	function:
	220	enum:
	221	- UA0
	222	then:
	223	properties:
	224	groups:
	225	enum:
	226	- UA0
	227	- if:
	228	properties:
	229	function:
	230	enum:
	231	- FPGA_IFX
	232	then:
	233	properties:
	234	groups:
	235	enum:
	236	- FPGA_IFX
	237	- if:
	238	properties:
	239	function:
	240	enum:
	241	- HDMI_TX
	242	then:
	243	properties:
	244	groups:
	245	enum:
	246	- HDMI_TX1
	247	- HDMI_TX2
	248	- HDMI_TX3
	249	- if:
	250	properties:
	251	function:
	252	enum:
	253	- LCDIF
	254	then:
	255	properties:
	256	groups:
	257	enum:
	258	- LCDIF
	259	- if:
	260	properties:
	261	function:
	262	enum:
	263	- USB0_OTG
	264	then:
	265	properties:
	266	groups:
	267	enum:
	268	- USB0_OTG
	269	- if:
	270	properties:
	271	function:
	272	enum:
	273	- USB1_OTG
	274	then:
	275	properties:
	276	groups:
	277	enum:
	278	- USB1_OTG
	279
	280	required:
	281	- compatible
	282	- reg
	283	- reg-names
	284	- "#gpio-cells"
	285	- gpio-controller
	286	- clocks
	287	- resets
	288
	289	additionalProperties: false
	290
	291	examples:
	292	- \|
	293	#include <dt-bindings/pinctrl/sppctl-sp7021.h>
	294
	295	pinctl@9c000100 {
	296	compatible = "sunplus,sp7021-pctl";
	297	reg = <0x9c000100 0x100>, <0x9c000300 0x100>,
	298	<0x9c0032e4 0x1c>, <0x9c000080 0x20>;
	299	reg-names = "moon2", "gpioxt", "first", "moon1";
	300	gpio-controller;
	301	#gpio-cells = <2>;
	302	clocks = <&clkc 0x83>;
	303	resets = <&rstc 0x73>;
	304
	305	uart0-pins {
	306	function = "UA0";
	307	groups = "UA0";
	308	};
	309
	310	spinand0-pins {
	311	function = "SPI_NAND";
	312	groups = "SPI_NAND";
	313	};
	314
	315	uart1-pins {
	316	sunplus,pins = <
	317	SPPCTL_IOPAD(11, SPPCTL_PCTL_G_PMUX, MUXF_UA1_TX, 0)
	318	SPPCTL_IOPAD(10, SPPCTL_PCTL_G_PMUX, MUXF_UA1_RX, 0)
	319	>;
	320	};
	321
	322	uart2-pins {
	323	sunplus,pins = <
	324	SPPCTL_IOPAD(20, SPPCTL_PCTL_G_PMUX, MUXF_UA1_TX, 0)
	325	SPPCTL_IOPAD(21, SPPCTL_PCTL_G_PMUX, MUXF_UA1_RX, 0)
	326	SPPCTL_IOPAD(22, SPPCTL_PCTL_G_PMUX, MUXF_UA1_RTS, 0)
	327	SPPCTL_IOPAD(23, SPPCTL_PCTL_G_PMUX, MUXF_UA1_CTS, 0)
	328	>;
	329	};
	330
	331	emmc-pins {
	332	function = "CARD0_EMMC";
	333	groups = "CARD0_EMMC";
	334	};
	335
	336	sdcard-pins {
	337	function = "SD_CARD";
	338	groups = "SD_CARD";
	339	sunplus,pins = < SPPCTL_IOPAD(91, SPPCTL_PCTL_G_GPIO, 0, 0) >;
	340	};
	341
	342	hdmi_A_tx1-pins {
	343	function = "HDMI_TX";
	344	groups = "HDMI_TX1";
	345	};
	346	hdmi_A_tx2-pins {
	347	function = "HDMI_TX";
	348	groups = "HDMI_TX2";
	349	};
	350	hdmi_A_tx3-pins {
	351	function = "HDMI_TX";
	352	groups = "HDMI_TX3";
	353	};
	354
	355	ethernet-pins {
	356	sunplus,pins = <
	357	SPPCTL_IOPAD(49,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_CLK_OUT,0)
	358	SPPCTL_IOPAD(44,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_MAC_SMI_MDC,0)
	359	SPPCTL_IOPAD(43,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_MAC_SMI_MDIO,0)
	360	SPPCTL_IOPAD(52,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXEN,0)
	361	SPPCTL_IOPAD(50,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXD0,0)
	362	SPPCTL_IOPAD(51,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXD1,0)
	363	SPPCTL_IOPAD(46,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_CRSDV,0)
	364	SPPCTL_IOPAD(47,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXD0,0)
	365	SPPCTL_IOPAD(48,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXD1,0)
	366	>;
	367	sunplus,zerofunc = <
	368	MUXF_L2SW_LED_FLASH0
	369	MUXF_L2SW_LED_ON0
	370	MUXF_L2SW_P0_MAC_RMII_RXER
	371	>;
	372	};
	373	};
	374	...

MAINTAINERS+19−0

@@ -2383,6 +2383,7 @@ W: https://github.com/neuschaefer/wpcm450/wiki · 2382 unmodified lines
2383	F: Documentation/devicetree/bindings//wpcm*	2383	F: Documentation/devicetree/bindings//wpcm*
2384	F: arch/arm/boot/dts/nuvoton-wpcm450*	2384	F: arch/arm/boot/dts/nuvoton-wpcm450*
2385	F: arch/arm/mach-npcm/wpcm450.c	2385	F: arch/arm/mach-npcm/wpcm450.c
		2386	F: drivers///wpcm
2386	F: drivers//wpcm*	2387	F: drivers//wpcm*
2387		2388
2388	ARM/NXP S32G ARCHITECTURE	2389	ARM/NXP S32G ARCHITECTURE
@@ -3716,6 +3717,14 @@ F: Documentation/devicetree/bindings/net/brcm,bcm4908-enet.yaml · 1327 unmodified lines
3716	F: drivers/net/ethernet/broadcom/bcm4908_enet.*	3717	F: drivers/net/ethernet/broadcom/bcm4908_enet.*
3717	F: drivers/net/ethernet/broadcom/unimac.h	3718	F: drivers/net/ethernet/broadcom/unimac.h
3718		3719
		3720	BROADCOM BCM4908 PINMUX DRIVER
		3721	M: Rafał Miłecki <rafal@milecki.pl>
		3722	M: bcm-kernel-feedback-list@broadcom.com
		3723	L: linux-gpio@vger.kernel.org
		3724	S: Maintained
		3725	F: Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml
		3726	F: drivers/pinctrl/bcm/pinctrl-bcm4908.c
		3727
3719	BROADCOM BCM5301X ARM ARCHITECTURE	3728	BROADCOM BCM5301X ARM ARCHITECTURE
3720	M: Florian Fainelli <f.fainelli@gmail.com>	3729	M: Florian Fainelli <f.fainelli@gmail.com>
3721	M: Hauke Mehrtens <hauke@hauke-m.de>	3730	M: Hauke Mehrtens <hauke@hauke-m.de>
@@ -15478,6 +15487,16 @@ M: Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com> · 11756 unmodified lines
15478	S: Supported	15487	S: Supported
15479	F: drivers/pinctrl/pinctrl-thunderbay.c	15488	F: drivers/pinctrl/pinctrl-thunderbay.c
15480		15489
		15490	PIN CONTROLLER - SUNPLUS / TIBBO
		15491	M: Dvorkin Dmitry <dvorkin@tibbo.com>
		15492	M: Wells Lu <wellslutw@gmail.com>
		15493	L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
		15494	S: Maintained
		15495	W: https://sunplus.atlassian.net/wiki/spaces/doc/overview
		15496	F: Documentation/devicetree/bindings/pinctrl/sunplus,*
		15497	F: drivers/pinctrl/sunplus/
		15498	F: include/dt-bindings/pinctrl/sppctl*.h
		15499
15481	PKTCDVD DRIVER	15500	PKTCDVD DRIVER
15482	M: linux-block@vger.kernel.org	15501	M: linux-block@vger.kernel.org
15483	S: Orphan	15502	S: Orphan

drivers/pinctrl/Kconfig+1−0

@@ -527,6 +527,7 @@ source "drivers/pinctrl/samsung/Kconfig" · 526 unmodified lines
527	source "drivers/pinctrl/spear/Kconfig"	527	source "drivers/pinctrl/spear/Kconfig"
528	source "drivers/pinctrl/sprd/Kconfig"	528	source "drivers/pinctrl/sprd/Kconfig"
529	source "drivers/pinctrl/stm32/Kconfig"	529	source "drivers/pinctrl/stm32/Kconfig"
		530	source "drivers/pinctrl/sunplus/Kconfig"
530	source "drivers/pinctrl/sunxi/Kconfig"	531	source "drivers/pinctrl/sunxi/Kconfig"
531	source "drivers/pinctrl/tegra/Kconfig"	532	source "drivers/pinctrl/tegra/Kconfig"
532	source "drivers/pinctrl/ti/Kconfig"	533	source "drivers/pinctrl/ti/Kconfig"

drivers/pinctrl/Makefile+2−1

 obj-$(CONFIG_PINCTRL_MESON)	+= meson/
 obj-y				+= mvebu/
 obj-y				+= nomadik/
-obj-$(CONFIG_ARCH_NPCM7XX)	+= nuvoton/
+obj-y				+= nuvoton/
 obj-$(CONFIG_PINCTRL_PXA)	+= pxa/
 obj-$(CONFIG_ARCH_QCOM)		+= qcom/
 obj-$(CONFIG_PINCTRL_RALINK)	+= ralink/
 obj-$(CONFIG_PINCTRL_SPEAR)	+= spear/
 obj-y				+= sprd/
 obj-$(CONFIG_PINCTRL_STM32)	+= stm32/
+obj-y				+= sunplus/
 obj-$(CONFIG_PINCTRL_SUNXI)	+= sunxi/
 obj-$(CONFIG_ARCH_TEGRA)	+= tegra/
 obj-y				+= ti/

drivers/pinctrl/bcm/Kconfig+14−0

@@ -29,6 +29,20 @@ config PINCTRL_BCM2835 · 28 unmodified lines
29	help	29	help
30	Say Y here to enable the Broadcom BCM2835 GPIO driver.	30	Say Y here to enable the Broadcom BCM2835 GPIO driver.
31		31
		32	config PINCTRL_BCM4908
		33	tristate "Broadcom BCM4908 pinmux driver"
		34	depends on OF && (ARCH_BCM4908 \|\| COMPILE_TEST)
		35	select PINMUX
		36	select PINCONF
		37	select GENERIC_PINCONF
		38	select GENERIC_PINCTRL_GROUPS
		39	select GENERIC_PINMUX_FUNCTIONS
		40	default ARCH_BCM4908
		41	help
		42	Driver for BCM4908 family SoCs with integrated pin controller.
		43
		44	If compiled as module it will be called pinctrl-bcm4908.
		45
32	config PINCTRL_BCM63XX	46	config PINCTRL_BCM63XX
33	bool	47	bool
34	select PINMUX	48	select PINMUX

drivers/pinctrl/bcm/Makefile+1−0

@@ -3,6 +3,7 @@ · 2 unmodified lines
3		3
4	obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o	4	obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o
5	obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o	5	obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o
		6	obj-$(CONFIG_PINCTRL_BCM4908) += pinctrl-bcm4908.o
6	obj-$(CONFIG_PINCTRL_BCM63XX) += pinctrl-bcm63xx.o	7	obj-$(CONFIG_PINCTRL_BCM63XX) += pinctrl-bcm63xx.o
7	obj-$(CONFIG_PINCTRL_BCM6318) += pinctrl-bcm6318.o	8	obj-$(CONFIG_PINCTRL_BCM6318) += pinctrl-bcm6318.o
8	obj-$(CONFIG_PINCTRL_BCM6328) += pinctrl-bcm6328.o	9	obj-$(CONFIG_PINCTRL_BCM6328) += pinctrl-bcm6328.o

drivers/pinctrl/bcm/pinctrl-bcm4908.c+563−0

@@ -0,0 +1,563 @@
	1	// SPDX-License-Identifier: GPL-2.0
	2	/* Copyright (C) 2021 Rafał Miłecki <rafal@milecki.pl> */
	3
	4	#include <linux/err.h>
	5	#include <linux/io.h>
	6	#include <linux/mod_devicetable.h>
	7	#include <linux/module.h>
	8	#include <linux/pinctrl/pinconf-generic.h>
	9	#include <linux/pinctrl/pinctrl.h>
	10	#include <linux/pinctrl/pinmux.h>
	11	#include <linux/platform_device.h>
	12	#include <linux/slab.h>
	13	#include <linux/string_helpers.h>
	14
	15	#include "../core.h"
	16	#include "../pinmux.h"
	17
	18	#define BCM4908_NUM_PINS 86
	19
	20	#define BCM4908_TEST_PORT_BLOCK_EN_LSB 0x00
	21	#define BCM4908_TEST_PORT_BLOCK_DATA_MSB 0x04
	22	#define BCM4908_TEST_PORT_BLOCK_DATA_LSB 0x08
	23	#define BCM4908_TEST_PORT_LSB_PINMUX_DATA_SHIFT 12
	24	#define BCM4908_TEST_PORT_COMMAND 0x0c
	25	#define BCM4908_TEST_PORT_CMD_LOAD_MUX_REG 0x00000021
	26
	27	struct bcm4908_pinctrl {
	28	struct device *dev;
	29	void __iomem *base;
	30	struct mutex mutex;
	31	struct pinctrl_dev *pctldev;
	32	struct pinctrl_desc pctldesc;
	33	};
	34
	35	/*
	36	* Groups
	37	*/
	38
	39	struct bcm4908_pinctrl_pin_setup {
	40	unsigned int number;
	41	unsigned int function;
	42	};
	43
	44	static const struct bcm4908_pinctrl_pin_setup led_0_pins_a[] = {
	45	{ 0, 3 },
	46	};
	47
	48	static const struct bcm4908_pinctrl_pin_setup led_1_pins_a[] = {
	49	{ 1, 3 },
	50	};
	51
	52	static const struct bcm4908_pinctrl_pin_setup led_2_pins_a[] = {
	53	{ 2, 3 },
	54	};
	55
	56	static const struct bcm4908_pinctrl_pin_setup led_3_pins_a[] = {
	57	{ 3, 3 },
	58	};
	59
	60	static const struct bcm4908_pinctrl_pin_setup led_4_pins_a[] = {
	61	{ 4, 3 },
	62	};
	63
	64	static const struct bcm4908_pinctrl_pin_setup led_5_pins_a[] = {
	65	{ 5, 3 },
	66	};
	67
	68	static const struct bcm4908_pinctrl_pin_setup led_6_pins_a[] = {
	69	{ 6, 3 },
	70	};
	71
	72	static const struct bcm4908_pinctrl_pin_setup led_7_pins_a[] = {
	73	{ 7, 3 },
	74	};
	75
	76	static const struct bcm4908_pinctrl_pin_setup led_8_pins_a[] = {
	77	{ 8, 3 },
	78	};
	79
	80	static const struct bcm4908_pinctrl_pin_setup led_9_pins_a[] = {
	81	{ 9, 3 },
	82	};
	83
	84	static const struct bcm4908_pinctrl_pin_setup led_10_pins_a[] = {
	85	{ 10, 3 },
	86	};
	87
	88	static const struct bcm4908_pinctrl_pin_setup led_11_pins_a[] = {
	89	{ 11, 3 },
	90	};
	91
	92	static const struct bcm4908_pinctrl_pin_setup led_12_pins_a[] = {
	93	{ 12, 3 },
	94	};
	95
	96	static const struct bcm4908_pinctrl_pin_setup led_13_pins_a[] = {
	97	{ 13, 3 },
	98	};
	99
	100	static const struct bcm4908_pinctrl_pin_setup led_14_pins_a[] = {
	101	{ 14, 3 },
	102	};
	103
	104	static const struct bcm4908_pinctrl_pin_setup led_15_pins_a[] = {
	105	{ 15, 3 },
	106	};
	107
	108	static const struct bcm4908_pinctrl_pin_setup led_16_pins_a[] = {
	109	{ 16, 3 },
	110	};
	111
	112	static const struct bcm4908_pinctrl_pin_setup led_17_pins_a[] = {
	113	{ 17, 3 },
	114	};
	115
	116	static const struct bcm4908_pinctrl_pin_setup led_18_pins_a[] = {
	117	{ 18, 3 },
	118	};
	119
	120	static const struct bcm4908_pinctrl_pin_setup led_19_pins_a[] = {
	121	{ 19, 3 },
	122	};
	123
	124	static const struct bcm4908_pinctrl_pin_setup led_20_pins_a[] = {
	125	{ 20, 3 },
	126	};
	127
	128	static const struct bcm4908_pinctrl_pin_setup led_21_pins_a[] = {
	129	{ 21, 3 },
	130	};
	131
	132	static const struct bcm4908_pinctrl_pin_setup led_22_pins_a[] = {
	133	{ 22, 3 },
	134	};
	135
	136	static const struct bcm4908_pinctrl_pin_setup led_23_pins_a[] = {
	137	{ 23, 3 },
	138	};
	139
	140	static const struct bcm4908_pinctrl_pin_setup led_24_pins_a[] = {
	141	{ 24, 3 },
	142	};
	143
	144	static const struct bcm4908_pinctrl_pin_setup led_25_pins_a[] = {
	145	{ 25, 3 },
	146	};
	147
	148	static const struct bcm4908_pinctrl_pin_setup led_26_pins_a[] = {
	149	{ 26, 3 },
	150	};
	151
	152	static const struct bcm4908_pinctrl_pin_setup led_27_pins_a[] = {
	153	{ 27, 3 },
	154	};
	155
	156	static const struct bcm4908_pinctrl_pin_setup led_28_pins_a[] = {
	157	{ 28, 3 },
	158	};
	159
	160	static const struct bcm4908_pinctrl_pin_setup led_29_pins_a[] = {
	161	{ 29, 3 },
	162	};
	163
	164	static const struct bcm4908_pinctrl_pin_setup led_30_pins_a[] = {
	165	{ 30, 3 },
	166	};
	167
	168	static const struct bcm4908_pinctrl_pin_setup led_31_pins_a[] = {
	169	{ 31, 3 },
	170	};
	171
	172	static const struct bcm4908_pinctrl_pin_setup led_10_pins_b[] = {
	173	{ 8, 2 },
	174	};
	175
	176	static const struct bcm4908_pinctrl_pin_setup led_11_pins_b[] = {
	177	{ 9, 2 },
	178	};
	179
	180	static const struct bcm4908_pinctrl_pin_setup led_12_pins_b[] = {
	181	{ 0, 2 },
	182	};
	183
	184	static const struct bcm4908_pinctrl_pin_setup led_13_pins_b[] = {
	185	{ 1, 2 },
	186	};
	187
	188	static const struct bcm4908_pinctrl_pin_setup led_31_pins_b[] = {
	189	{ 30, 2 },
	190	};
	191
	192	static const struct bcm4908_pinctrl_pin_setup hs_uart_pins[] = {
	193	{ 10, 0 }, /* CTS */
	194	{ 11, 0 }, /* RTS */
	195	{ 12, 0 }, /* RXD */
	196	{ 13, 0 }, /* TXD */
	197	};
	198
	199	static const struct bcm4908_pinctrl_pin_setup i2c_pins_a[] = {
	200	{ 18, 0 }, /* SDA */
	201	{ 19, 0 }, /* SCL */
	202	};
	203
	204	static const struct bcm4908_pinctrl_pin_setup i2c_pins_b[] = {
	205	{ 22, 0 }, /* SDA */
	206	{ 23, 0 }, /* SCL */
	207	};
	208
	209	static const struct bcm4908_pinctrl_pin_setup i2s_pins[] = {
	210	{ 27, 0 }, /* MCLK */
	211	{ 28, 0 }, /* LRCK */
	212	{ 29, 0 }, /* SDATA */
	213	{ 30, 0 }, /* SCLK */
	214	};
	215
	216	static const struct bcm4908_pinctrl_pin_setup nand_ctrl_pins[] = {
	217	{ 32, 0 },
	218	{ 33, 0 },
	219	{ 34, 0 },
	220	{ 43, 0 },
	221	{ 44, 0 },
	222	{ 45, 0 },
	223	{ 56, 1 },
	224	};
	225
	226	static const struct bcm4908_pinctrl_pin_setup nand_data_pins[] = {
	227	{ 35, 0 },
	228	{ 36, 0 },
	229	{ 37, 0 },
	230	{ 38, 0 },
	231	{ 39, 0 },
	232	{ 40, 0 },
	233	{ 41, 0 },
	234	{ 42, 0 },
	235	};
	236
	237	static const struct bcm4908_pinctrl_pin_setup emmc_ctrl_pins[] = {
	238	{ 46, 0 },
	239	{ 47, 0 },
	240	};
	241
	242	static const struct bcm4908_pinctrl_pin_setup usb0_pwr_pins[] = {
	243	{ 63, 0 },
	244	{ 64, 0 },
	245	};
	246
	247	static const struct bcm4908_pinctrl_pin_setup usb1_pwr_pins[] = {
	248	{ 66, 0 },
	249	{ 67, 0 },
	250	};
	251
	252	struct bcm4908_pinctrl_grp {
	253	const char *name;
	254	const struct bcm4908_pinctrl_pin_setup *pins;
	255	const unsigned int num_pins;
	256	};
	257
	258	static const struct bcm4908_pinctrl_grp bcm4908_pinctrl_grps[] = {
	259	{ "led_0_grp_a", led_0_pins_a, ARRAY_SIZE(led_0_pins_a) },
	260	{ "led_1_grp_a", led_1_pins_a, ARRAY_SIZE(led_1_pins_a) },
	261	{ "led_2_grp_a", led_2_pins_a, ARRAY_SIZE(led_2_pins_a) },
	262	{ "led_3_grp_a", led_3_pins_a, ARRAY_SIZE(led_3_pins_a) },
	263	{ "led_4_grp_a", led_4_pins_a, ARRAY_SIZE(led_4_pins_a) },
	264	{ "led_5_grp_a", led_5_pins_a, ARRAY_SIZE(led_5_pins_a) },
	265	{ "led_6_grp_a", led_6_pins_a, ARRAY_SIZE(led_6_pins_a) },
	266	{ "led_7_grp_a", led_7_pins_a, ARRAY_SIZE(led_7_pins_a) },
	267	{ "led_8_grp_a", led_8_pins_a, ARRAY_SIZE(led_8_pins_a) },
	268	{ "led_9_grp_a", led_9_pins_a, ARRAY_SIZE(led_9_pins_a) },
	269	{ "led_10_grp_a", led_10_pins_a, ARRAY_SIZE(led_10_pins_a) },
	270	{ "led_11_grp_a", led_11_pins_a, ARRAY_SIZE(led_11_pins_a) },
	271	{ "led_12_grp_a", led_12_pins_a, ARRAY_SIZE(led_12_pins_a) },
	272	{ "led_13_grp_a", led_13_pins_a, ARRAY_SIZE(led_13_pins_a) },
	273	{ "led_14_grp_a", led_14_pins_a, ARRAY_SIZE(led_14_pins_a) },
	274	{ "led_15_grp_a", led_15_pins_a, ARRAY_SIZE(led_15_pins_a) },
	275	{ "led_16_grp_a", led_16_pins_a, ARRAY_SIZE(led_16_pins_a) },
	276	{ "led_17_grp_a", led_17_pins_a, ARRAY_SIZE(led_17_pins_a) },
	277	{ "led_18_grp_a", led_18_pins_a, ARRAY_SIZE(led_18_pins_a) },
	278	{ "led_19_grp_a", led_19_pins_a, ARRAY_SIZE(led_19_pins_a) },
	279	{ "led_20_grp_a", led_20_pins_a, ARRAY_SIZE(led_20_pins_a) },
	280	{ "led_21_grp_a", led_21_pins_a, ARRAY_SIZE(led_21_pins_a) },
	281	{ "led_22_grp_a", led_22_pins_a, ARRAY_SIZE(led_22_pins_a) },
	282	{ "led_23_grp_a", led_23_pins_a, ARRAY_SIZE(led_23_pins_a) },
	283	{ "led_24_grp_a", led_24_pins_a, ARRAY_SIZE(led_24_pins_a) },
	284	{ "led_25_grp_a", led_25_pins_a, ARRAY_SIZE(led_25_pins_a) },
	285	{ "led_26_grp_a", led_26_pins_a, ARRAY_SIZE(led_26_pins_a) },
	286	{ "led_27_grp_a", led_27_pins_a, ARRAY_SIZE(led_27_pins_a) },
	287	{ "led_28_grp_a", led_28_pins_a, ARRAY_SIZE(led_28_pins_a) },
	288	{ "led_29_grp_a", led_29_pins_a, ARRAY_SIZE(led_29_pins_a) },
	289	{ "led_30_grp_a", led_30_pins_a, ARRAY_SIZE(led_30_pins_a) },
	290	{ "led_31_grp_a", led_31_pins_a, ARRAY_SIZE(led_31_pins_a) },
	291	{ "led_10_grp_b", led_10_pins_b, ARRAY_SIZE(led_10_pins_b) },
	292	{ "led_11_grp_b", led_11_pins_b, ARRAY_SIZE(led_11_pins_b) },
	293	{ "led_12_grp_b", led_12_pins_b, ARRAY_SIZE(led_12_pins_b) },
	294	{ "led_13_grp_b", led_13_pins_b, ARRAY_SIZE(led_13_pins_b) },
	295	{ "led_31_grp_b", led_31_pins_b, ARRAY_SIZE(led_31_pins_b) },
	296	{ "hs_uart_grp", hs_uart_pins, ARRAY_SIZE(hs_uart_pins) },
	297	{ "i2c_grp_a", i2c_pins_a, ARRAY_SIZE(i2c_pins_a) },
	298	{ "i2c_grp_b", i2c_pins_b, ARRAY_SIZE(i2c_pins_b) },
	299	{ "i2s_grp", i2s_pins, ARRAY_SIZE(i2s_pins) },
	300	{ "nand_ctrl_grp", nand_ctrl_pins, ARRAY_SIZE(nand_ctrl_pins) },
	301	{ "nand_data_grp", nand_data_pins, ARRAY_SIZE(nand_data_pins) },
	302	{ "emmc_ctrl_grp", emmc_ctrl_pins, ARRAY_SIZE(emmc_ctrl_pins) },
	303	{ "usb0_pwr_grp", usb0_pwr_pins, ARRAY_SIZE(usb0_pwr_pins) },
	304	{ "usb1_pwr_grp", usb1_pwr_pins, ARRAY_SIZE(usb1_pwr_pins) },
	305	};
	306
	307	/*
	308	* Functions
	309	*/
	310
	311	struct bcm4908_pinctrl_function {
	312	const char *name;
	313	const char * const *groups;
	314	const unsigned int num_groups;
	315	};
	316
	317	static const char * const led_0_groups[] = { "led_0_grp_a" };
	318	static const char * const led_1_groups[] = { "led_1_grp_a" };
	319	static const char * const led_2_groups[] = { "led_2_grp_a" };
	320	static const char * const led_3_groups[] = { "led_3_grp_a" };
	321	static const char * const led_4_groups[] = { "led_4_grp_a" };
	322	static const char * const led_5_groups[] = { "led_5_grp_a" };
	323	static const char * const led_6_groups[] = { "led_6_grp_a" };
	324	static const char * const led_7_groups[] = { "led_7_grp_a" };
	325	static const char * const led_8_groups[] = { "led_8_grp_a" };
	326	static const char * const led_9_groups[] = { "led_9_grp_a" };
	327	static const char * const led_10_groups[] = { "led_10_grp_a", "led_10_grp_b" };
	328	static const char * const led_11_groups[] = { "led_11_grp_a", "led_11_grp_b" };
	329	static const char * const led_12_groups[] = { "led_12_grp_a", "led_12_grp_b" };
	330	static const char * const led_13_groups[] = { "led_13_grp_a", "led_13_grp_b" };
	331	static const char * const led_14_groups[] = { "led_14_grp_a" };
	332	static const char * const led_15_groups[] = { "led_15_grp_a" };
	333	static const char * const led_16_groups[] = { "led_16_grp_a" };
	334	static const char * const led_17_groups[] = { "led_17_grp_a" };
	335	static const char * const led_18_groups[] = { "led_18_grp_a" };
	336	static const char * const led_19_groups[] = { "led_19_grp_a" };
	337	static const char * const led_20_groups[] = { "led_20_grp_a" };
	338	static const char * const led_21_groups[] = { "led_21_grp_a" };
	339	static const char * const led_22_groups[] = { "led_22_grp_a" };
	340	static const char * const led_23_groups[] = { "led_23_grp_a" };
	341	static const char * const led_24_groups[] = { "led_24_grp_a" };
	342	static const char * const led_25_groups[] = { "led_25_grp_a" };
	343	static const char * const led_26_groups[] = { "led_26_grp_a" };
	344	static const char * const led_27_groups[] = { "led_27_grp_a" };
	345	static const char * const led_28_groups[] = { "led_28_grp_a" };
	346	static const char * const led_29_groups[] = { "led_29_grp_a" };
	347	static const char * const led_30_groups[] = { "led_30_grp_a" };
	348	static const char * const led_31_groups[] = { "led_31_grp_a", "led_31_grp_b" };
	349	static const char * const hs_uart_groups[] = { "hs_uart_grp" };
	350	static const char * const i2c_groups[] = { "i2c_grp_a", "i2c_grp_b" };
	351	static const char * const i2s_groups[] = { "i2s_grp" };
	352	static const char * const nand_ctrl_groups[] = { "nand_ctrl_grp" };
	353	static const char * const nand_data_groups[] = { "nand_data_grp" };
	354	static const char * const emmc_ctrl_groups[] = { "emmc_ctrl_grp" };
	355	static const char * const usb0_pwr_groups[] = { "usb0_pwr_grp" };
	356	static const char * const usb1_pwr_groups[] = { "usb1_pwr_grp" };
	357
	358	static const struct bcm4908_pinctrl_function bcm4908_pinctrl_functions[] = {
	359	{ "led_0", led_0_groups, ARRAY_SIZE(led_0_groups) },
	360	{ "led_1", led_1_groups, ARRAY_SIZE(led_1_groups) },
	361	{ "led_2", led_2_groups, ARRAY_SIZE(led_2_groups) },
	362	{ "led_3", led_3_groups, ARRAY_SIZE(led_3_groups) },
	363	{ "led_4", led_4_groups, ARRAY_SIZE(led_4_groups) },
	364	{ "led_5", led_5_groups, ARRAY_SIZE(led_5_groups) },
	365	{ "led_6", led_6_groups, ARRAY_SIZE(led_6_groups) },
	366	{ "led_7", led_7_groups, ARRAY_SIZE(led_7_groups) },
	367	{ "led_8", led_8_groups, ARRAY_SIZE(led_8_groups) },
	368	{ "led_9", led_9_groups, ARRAY_SIZE(led_9_groups) },
	369	{ "led_10", led_10_groups, ARRAY_SIZE(led_10_groups) },
	370	{ "led_11", led_11_groups, ARRAY_SIZE(led_11_groups) },
	371	{ "led_12", led_12_groups, ARRAY_SIZE(led_12_groups) },
	372	{ "led_13", led_13_groups, ARRAY_SIZE(led_13_groups) },
	373	{ "led_14", led_14_groups, ARRAY_SIZE(led_14_groups) },
	374	{ "led_15", led_15_groups, ARRAY_SIZE(led_15_groups) },
	375	{ "led_16", led_16_groups, ARRAY_SIZE(led_16_groups) },
	376	{ "led_17", led_17_groups, ARRAY_SIZE(led_17_groups) },
	377	{ "led_18", led_18_groups, ARRAY_SIZE(led_18_groups) },
	378	{ "led_19", led_19_groups, ARRAY_SIZE(led_19_groups) },
	379	{ "led_20", led_20_groups, ARRAY_SIZE(led_20_groups) },
	380	{ "led_21", led_21_groups, ARRAY_SIZE(led_21_groups) },
	381	{ "led_22", led_22_groups, ARRAY_SIZE(led_22_groups) },
	382	{ "led_23", led_23_groups, ARRAY_SIZE(led_23_groups) },
	383	{ "led_24", led_24_groups, ARRAY_SIZE(led_24_groups) },
	384	{ "led_25", led_25_groups, ARRAY_SIZE(led_25_groups) },
	385	{ "led_26", led_26_groups, ARRAY_SIZE(led_26_groups) },
	386	{ "led_27", led_27_groups, ARRAY_SIZE(led_27_groups) },
	387	{ "led_28", led_28_groups, ARRAY_SIZE(led_28_groups) },
	388	{ "led_29", led_29_groups, ARRAY_SIZE(led_29_groups) },
	389	{ "led_30", led_30_groups, ARRAY_SIZE(led_30_groups) },
	390	{ "led_31", led_31_groups, ARRAY_SIZE(led_31_groups) },
	391	{ "hs_uart", hs_uart_groups, ARRAY_SIZE(hs_uart_groups) },
	392	{ "i2c", i2c_groups, ARRAY_SIZE(i2c_groups) },
	393	{ "i2s", i2s_groups, ARRAY_SIZE(i2s_groups) },
	394	{ "nand_ctrl", nand_ctrl_groups, ARRAY_SIZE(nand_ctrl_groups) },
	395	{ "nand_data", nand_data_groups, ARRAY_SIZE(nand_data_groups) },
	396	{ "emmc_ctrl", emmc_ctrl_groups, ARRAY_SIZE(emmc_ctrl_groups) },
	397	{ "usb0_pwr", usb0_pwr_groups, ARRAY_SIZE(usb0_pwr_groups) },
	398	{ "usb1_pwr", usb1_pwr_groups, ARRAY_SIZE(usb1_pwr_groups) },
	399	};
	400
	401	/*
	402	* Groups code
	403	*/
	404
	405	static const struct pinctrl_ops bcm4908_pinctrl_ops = {
	406	.get_groups_count = pinctrl_generic_get_group_count,
	407	.get_group_name = pinctrl_generic_get_group_name,
	408	.get_group_pins = pinctrl_generic_get_group_pins,
	409	.dt_node_to_map = pinconf_generic_dt_node_to_map_group,
	410	.dt_free_map = pinconf_generic_dt_free_map,
	411	};
	412
	413	/*
	414	* Functions code
	415	*/
	416
	417	static int bcm4908_pinctrl_set_mux(struct pinctrl_dev *pctrl_dev,
	418	unsigned int func_selector,
	419	unsigned int group_selector)
	420	{
	421	struct bcm4908_pinctrl *bcm4908_pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
	422	const struct bcm4908_pinctrl_grp *group;
	423	struct group_desc *group_desc;
	424	int i;
	425
	426	group_desc = pinctrl_generic_get_group(pctrl_dev, group_selector);
	427	if (!group_desc)
	428	return -EINVAL;
	429	group = group_desc->data;
	430
	431	mutex_lock(&bcm4908_pinctrl->mutex);
	432	for (i = 0; i < group->num_pins; i++) {
	433	u32 lsb = 0;
	434
	435	lsb \|= group->pins[i].number;
	436	lsb \|= group->pins[i].function << BCM4908_TEST_PORT_LSB_PINMUX_DATA_SHIFT;
	437
	438	writel(0x0, bcm4908_pinctrl->base + BCM4908_TEST_PORT_BLOCK_DATA_MSB);
	439	writel(lsb, bcm4908_pinctrl->base + BCM4908_TEST_PORT_BLOCK_DATA_LSB);
	440	writel(BCM4908_TEST_PORT_CMD_LOAD_MUX_REG,
	441	bcm4908_pinctrl->base + BCM4908_TEST_PORT_COMMAND);
	442	}
	443	mutex_unlock(&bcm4908_pinctrl->mutex);
	444
	445	return 0;
	446	}
	447
	448	static const struct pinmux_ops bcm4908_pinctrl_pmxops = {
	449	.get_functions_count = pinmux_generic_get_function_count,
	450	.get_function_name = pinmux_generic_get_function_name,
	451	.get_function_groups = pinmux_generic_get_function_groups,
	452	.set_mux = bcm4908_pinctrl_set_mux,
	453	};
	454
	455	/*
	456	* Controller code
	457	*/
	458
	459	static struct pinctrl_desc bcm4908_pinctrl_desc = {
	460	.name = "bcm4908-pinctrl",
	461	.pctlops = &bcm4908_pinctrl_ops,
	462	.pmxops = &bcm4908_pinctrl_pmxops,
	463	};
	464
	465	static const struct of_device_id bcm4908_pinctrl_of_match_table[] = {
	466	{ .compatible = "brcm,bcm4908-pinctrl", },
	467	{ }
	468	};
	469
	470	static int bcm4908_pinctrl_probe(struct platform_device *pdev)
	471	{
	472	struct device *dev = &pdev->dev;
	473	struct bcm4908_pinctrl *bcm4908_pinctrl;
	474	struct pinctrl_desc *pctldesc;
	475	struct pinctrl_pin_desc *pins;
	476	char **pin_names;
	477	int i;
	478
	479	bcm4908_pinctrl = devm_kzalloc(dev, sizeof(*bcm4908_pinctrl), GFP_KERNEL);
	480	if (!bcm4908_pinctrl)
	481	return -ENOMEM;
	482	pctldesc = &bcm4908_pinctrl->pctldesc;
	483	platform_set_drvdata(pdev, bcm4908_pinctrl);
	484
	485	/* Set basic properties */
	486
	487	bcm4908_pinctrl->dev = dev;
	488
	489	bcm4908_pinctrl->base = devm_platform_ioremap_resource(pdev, 0);
	490	if (IS_ERR(bcm4908_pinctrl->base))
	491	return PTR_ERR(bcm4908_pinctrl->base);
	492
	493	mutex_init(&bcm4908_pinctrl->mutex);
	494
	495	memcpy(pctldesc, &bcm4908_pinctrl_desc, sizeof(*pctldesc));
	496
	497	/* Set pinctrl properties */
	498
	499	pin_names = devm_kasprintf_strarray(dev, "pin", BCM4908_NUM_PINS);
	500	if (IS_ERR(pin_names))
	501	return PTR_ERR(pin_names);
	502
	503	pins = devm_kcalloc(dev, BCM4908_NUM_PINS, sizeof(*pins), GFP_KERNEL);
	504	if (!pins)
	505	return -ENOMEM;
	506	for (i = 0; i < BCM4908_NUM_PINS; i++) {
	507	pins[i].number = i;
	508	pins[i].name = pin_names[i];
	509	}
	510	pctldesc->pins = pins;
	511	pctldesc->npins = BCM4908_NUM_PINS;
	512
	513	/* Register */
	514
	515	bcm4908_pinctrl->pctldev = devm_pinctrl_register(dev, pctldesc, bcm4908_pinctrl);
	516	if (IS_ERR(bcm4908_pinctrl->pctldev))
	517	return dev_err_probe(dev, PTR_ERR(bcm4908_pinctrl->pctldev),
	518	"Failed to register pinctrl\n");
	519
	520	/* Groups */
	521
	522	for (i = 0; i < ARRAY_SIZE(bcm4908_pinctrl_grps); i++) {
	523	const struct bcm4908_pinctrl_grp *group = &bcm4908_pinctrl_grps[i];
	524	int *pins;
	525	int j;
	526
	527	pins = devm_kcalloc(dev, group->num_pins, sizeof(*pins), GFP_KERNEL);
	528	if (!pins)
	529	return -ENOMEM;
	530	for (j = 0; j < group->num_pins; j++)
	531	pins[j] = group->pins[j].number;
	532
	533	pinctrl_generic_add_group(bcm4908_pinctrl->pctldev, group->name,
	534	pins, group->num_pins, (void *)group);
	535	}
	536
	537	/* Functions */
	538
	539	for (i = 0; i < ARRAY_SIZE(bcm4908_pinctrl_functions); i++) {
	540	const struct bcm4908_pinctrl_function *function = &bcm4908_pinctrl_functions[i];
	541
	542	pinmux_generic_add_function(bcm4908_pinctrl->pctldev,
	543	function->name,
	544	function->groups,
	545	function->num_groups, NULL);
	546	}
	547
	548	return 0;
	549	}
	550
	551	static struct platform_driver bcm4908_pinctrl_driver = {
	552	.probe = bcm4908_pinctrl_probe,
	553	.driver = {
	554	.name = "bcm4908-pinctrl",
	555	.of_match_table = bcm4908_pinctrl_of_match_table,
	556	},
	557	};
	558
	559	module_platform_driver(bcm4908_pinctrl_driver);
	560
	561	MODULE_AUTHOR("Rafał Miłecki");
	562	MODULE_LICENSE("GPL v2");
	563	MODULE_DEVICE_TABLE(of, bcm4908_pinctrl_of_match_table);

drivers/pinctrl/berlin/berlin.c+2−0

@@ -233,6 +233,8 @@ static int berlin_pinctrl_build_state(struct platform_device *pdev) · 232 unmodified lines
233	pctrl->functions = krealloc(pctrl->functions,	233	pctrl->functions = krealloc(pctrl->functions,
234	pctrl->nfunctions * sizeof(*pctrl->functions),	234	pctrl->nfunctions * sizeof(*pctrl->functions),
235	GFP_KERNEL);	235	GFP_KERNEL);
		236	if (!pctrl->functions)
		237	return -ENOMEM;
236		238
237	/* map functions to theirs groups */	239	/* map functions to theirs groups */
238	for (i = 0; i < pctrl->desc->ngroups; i++) {	240	for (i = 0; i < pctrl->desc->ngroups; i++) {

drivers/pinctrl/freescale/Kconfig+7−0

@@ -180,6 +180,13 @@ config PINCTRL_IMXRT1050 · 179 unmodified lines
180	help	180	help
181	Say Y here to enable the imxrt1050 pinctrl driver	181	Say Y here to enable the imxrt1050 pinctrl driver
182		182
		183	config PINCTRL_IMX93
		184	tristate "IMX93 pinctrl driver"
		185	depends on ARCH_MXC
		186	select PINCTRL_IMX
		187	help
		188	Say Y here to enable the imx93 pinctrl driver
		189
183	config PINCTRL_VF610	190	config PINCTRL_VF610
184	bool "Freescale Vybrid VF610 pinctrl driver"	191	bool "Freescale Vybrid VF610 pinctrl driver"
185	depends on SOC_VF610	192	depends on SOC_VF610

drivers/pinctrl/freescale/Makefile+1−0

@@ -25,6 +25,7 @@ obj-$(CONFIG_PINCTRL_IMX8QM) += pinctrl-imx8qm.o · 24 unmodified lines
25	obj-$(CONFIG_PINCTRL_IMX8QXP) += pinctrl-imx8qxp.o	25	obj-$(CONFIG_PINCTRL_IMX8QXP) += pinctrl-imx8qxp.o
26	obj-$(CONFIG_PINCTRL_IMX8DXL) += pinctrl-imx8dxl.o	26	obj-$(CONFIG_PINCTRL_IMX8DXL) += pinctrl-imx8dxl.o
27	obj-$(CONFIG_PINCTRL_IMX8ULP) += pinctrl-imx8ulp.o	27	obj-$(CONFIG_PINCTRL_IMX8ULP) += pinctrl-imx8ulp.o
		28	obj-$(CONFIG_PINCTRL_IMX93) += pinctrl-imx93.o
28	obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o	29	obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o
29	obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o	30	obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
30	obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o	31	obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o

drivers/pinctrl/freescale/pinctrl-imx.c+1−1

@@ -661,7 +661,7 @@ static int imx_pinctrl_parse_functions(struct device_node *np, · 660 unmodified lines
661	func->name = np->name;	661	func->name = np->name;
662	func->num_group_names = of_get_child_count(np);	662	func->num_group_names = of_get_child_count(np);
663	if (func->num_group_names == 0) {	663	if (func->num_group_names == 0) {
664	dev_err(ipctl->dev, "no groups defined in %pOF\n", np);	664	dev_info(ipctl->dev, "no groups defined in %pOF\n", np);
665	return -EINVAL;	665	return -EINVAL;
666	}	666	}
667		667

drivers/pinctrl/freescale/pinctrl-imx93.c+272−0

@@ -0,0 +1,272 @@
	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright 2021 NXP
	4	*/
	5
	6	#include <linux/err.h>
	7	#include <linux/init.h>
	8	#include <linux/io.h>
	9	#include <linux/module.h>
	10	#include <linux/of.h>
	11	#include <linux/of_device.h>
	12	#include <linux/pinctrl/pinctrl.h>
	13
	14	#include "pinctrl-imx.h"
	15
	16	enum imx93_pads {
	17	IMX93_IOMUXC_DAP_TDI = 0,
	18	IMX93_IOMUXC_DAP_TMS_SWDIO = 1,
	19	IMX93_IOMUXC_DAP_TCLK_SWCLK = 2,
	20	IMX93_IOMUXC_DAP_TDO_TRACESWO = 3,
	21	IMX93_IOMUXC_GPIO_IO00 = 4,
	22	IMX93_IOMUXC_GPIO_IO01 = 5,
	23	IMX93_IOMUXC_GPIO_IO02 = 6,
	24	IMX93_IOMUXC_GPIO_IO03 = 7,
	25	IMX93_IOMUXC_GPIO_IO04 = 8,
	26	IMX93_IOMUXC_GPIO_IO05 = 9,
	27	IMX93_IOMUXC_GPIO_IO06 = 10,
	28	IMX93_IOMUXC_GPIO_IO07 = 11,
	29	IMX93_IOMUXC_GPIO_IO08 = 12,
	30	IMX93_IOMUXC_GPIO_IO09 = 13,
	31	IMX93_IOMUXC_GPIO_IO10 = 14,
	32	IMX93_IOMUXC_GPIO_IO11 = 15,
	33	IMX93_IOMUXC_GPIO_IO12 = 16,
	34	IMX93_IOMUXC_GPIO_IO13 = 17,
	35	IMX93_IOMUXC_GPIO_IO14 = 18,
	36	IMX93_IOMUXC_GPIO_IO15 = 19,
	37	IMX93_IOMUXC_GPIO_IO16 = 20,
	38	IMX93_IOMUXC_GPIO_IO17 = 21,
	39	IMX93_IOMUXC_GPIO_IO18 = 22,
	40	IMX93_IOMUXC_GPIO_IO19 = 23,
	41	IMX93_IOMUXC_GPIO_IO20 = 24,
	42	IMX93_IOMUXC_GPIO_IO21 = 25,
	43	IMX93_IOMUXC_GPIO_IO22 = 26,
	44	IMX93_IOMUXC_GPIO_IO23 = 27,
	45	IMX93_IOMUXC_GPIO_IO24 = 28,
	46	IMX93_IOMUXC_GPIO_IO25 = 29,
	47	IMX93_IOMUXC_GPIO_IO26 = 30,
	48	IMX93_IOMUXC_GPIO_IO27 = 31,
	49	IMX93_IOMUXC_GPIO_IO28 = 32,
	50	IMX93_IOMUXC_GPIO_IO29 = 33,
	51	IMX93_IOMUXC_CCM_CLKO1 = 34,
	52	IMX93_IOMUXC_CCM_CLKO2 = 35,
	53	IMX93_IOMUXC_CCM_CLKO3 = 36,
	54	IMX93_IOMUXC_CCM_CLKO4 = 37,
	55	IMX93_IOMUXC_ENET1_MDC = 38,
	56	IMX93_IOMUXC_ENET1_MDIO = 39,
	57	IMX93_IOMUXC_ENET1_TD3 = 40,
	58	IMX93_IOMUXC_ENET1_TD2 = 41,
	59	IMX93_IOMUXC_ENET1_TD1 = 42,
	60	IMX93_IOMUXC_ENET1_TD0 = 43,
	61	IMX93_IOMUXC_ENET1_TX_CTL = 44,
	62	IMX93_IOMUXC_ENET1_TXC = 45,
	63	IMX93_IOMUXC_ENET1_RX_CTL = 46,
	64	IMX93_IOMUXC_ENET1_RXC = 47,
	65	IMX93_IOMUXC_ENET1_RD0 = 48,
	66	IMX93_IOMUXC_ENET1_RD1 = 49,
	67	IMX93_IOMUXC_ENET1_RD2 = 50,
	68	IMX93_IOMUXC_ENET1_RD3 = 51,
	69	IMX93_IOMUXC_ENET2_MDC = 52,
	70	IMX93_IOMUXC_ENET2_MDIO = 53,
	71	IMX93_IOMUXC_ENET2_TD3 = 54,
	72	IMX93_IOMUXC_ENET2_TD2 = 55,
	73	IMX93_IOMUXC_ENET2_TD1 = 56,
	74	IMX93_IOMUXC_ENET2_TD0 = 57,
	75	IMX93_IOMUXC_ENET2_TX_CTL = 58,
	76	IMX93_IOMUXC_ENET2_TXC = 59,
	77	IMX93_IOMUXC_ENET2_RX_CTL = 60,
	78	IMX93_IOMUXC_ENET2_RXC = 61,
	79	IMX93_IOMUXC_ENET2_RD0 = 62,
	80	IMX93_IOMUXC_ENET2_RD1 = 63,
	81	IMX93_IOMUXC_ENET2_RD2 = 64,
	82	IMX93_IOMUXC_ENET2_RD3 = 65,
	83	IMX93_IOMUXC_SD1_CLK = 66,
	84	IMX93_IOMUXC_SD1_CMD = 67,
	85	IMX93_IOMUXC_SD1_DATA0 = 68,
	86	IMX93_IOMUXC_SD1_DATA1 = 69,
	87	IMX93_IOMUXC_SD1_DATA2 = 70,
	88	IMX93_IOMUXC_SD1_DATA3 = 71,
	89	IMX93_IOMUXC_SD1_DATA4 = 72,
	90	IMX93_IOMUXC_SD1_DATA5 = 73,
	91	IMX93_IOMUXC_SD1_DATA6 = 74,
	92	IMX93_IOMUXC_SD1_DATA7 = 75,
	93	IMX93_IOMUXC_SD1_STROBE = 76,
	94	IMX93_IOMUXC_SD2_VSELECT = 77,
	95	IMX93_IOMUXC_SD3_CLK = 78,
	96	IMX93_IOMUXC_SD3_CMD = 79,
	97	IMX93_IOMUXC_SD3_DATA0 = 80,
	98	IMX93_IOMUXC_SD3_DATA1 = 81,
	99	IMX93_IOMUXC_SD3_DATA2 = 82,
	100	IMX93_IOMUXC_SD3_DATA3 = 83,
	101	IMX93_IOMUXC_SD2_CD_B = 84,
	102	IMX93_IOMUXC_SD2_CLK = 85,
	103	IMX93_IOMUXC_SD2_CMD = 86,
	104	IMX93_IOMUXC_SD2_DATA0 = 87,
	105	IMX93_IOMUXC_SD2_DATA1 = 88,
	106	IMX93_IOMUXC_SD2_DATA2 = 89,
	107	IMX93_IOMUXC_SD2_DATA3 = 90,
	108	IMX93_IOMUXC_SD2_RESET_B = 91,
	109	IMX93_IOMUXC_I2C1_SCL = 92,
	110	IMX93_IOMUXC_I2C1_SDA = 93,
	111	IMX93_IOMUXC_I2C2_SCL = 94,
	112	IMX93_IOMUXC_I2C2_SDA = 95,
	113	IMX93_IOMUXC_UART1_RXD = 96,
	114	IMX93_IOMUXC_UART1_TXD = 97,
	115	IMX93_IOMUXC_UART2_RXD = 98,
	116	IMX93_IOMUXC_UART2_TXD = 99,
	117	IMX93_IOMUXC_PDM_CLK = 100,
	118	IMX93_IOMUXC_PDM_BIT_STREAM0 = 101,
	119	IMX93_IOMUXC_PDM_BIT_STREAM1 = 102,
	120	IMX93_IOMUXC_SAI1_TXFS = 103,
	121	IMX93_IOMUXC_SAI1_TXC = 104,
	122	IMX93_IOMUXC_SAI1_TXD0 = 105,
	123	IMX93_IOMUXC_SAI1_RXD0 = 106,
	124	IMX93_IOMUXC_WDOG_ANY = 107,
	125	};
	126
	127	/* Pad names for the pinmux subsystem */
	128	static const struct pinctrl_pin_desc imx93_pinctrl_pads[] = {
	129	IMX_PINCTRL_PIN(IMX93_IOMUXC_DAP_TDI),
	130	IMX_PINCTRL_PIN(IMX93_IOMUXC_DAP_TMS_SWDIO),
	131	IMX_PINCTRL_PIN(IMX93_IOMUXC_DAP_TCLK_SWCLK),
	132	IMX_PINCTRL_PIN(IMX93_IOMUXC_DAP_TDO_TRACESWO),
	133	IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO00),
	134	IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO01),
	135	IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO02),
	136	IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO03),
	137	IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO04),
	138	IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO05),
	139	IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO06),
	140	IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO07),
	141	IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO08),
	142	IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO09),
	143	IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO10),
	144	IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO11),
	145	IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO12),
	146	IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO13),
	147	IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO14),
	148	IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO15),
	149	IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO16),
	150	IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO17),
	151	IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO18),
	152	IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO19),
	153	IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO20),
	154	IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO21),
	155	IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO22),
	156	IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO23),
	157	IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO24),
	158	IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO25),
	159	IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO26),
	160	IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO27),
	161	IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO28),
	162	IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO29),
	163	IMX_PINCTRL_PIN(IMX93_IOMUXC_CCM_CLKO1),
	164	IMX_PINCTRL_PIN(IMX93_IOMUXC_CCM_CLKO2),
	165	IMX_PINCTRL_PIN(IMX93_IOMUXC_CCM_CLKO3),
	166	IMX_PINCTRL_PIN(IMX93_IOMUXC_CCM_CLKO4),
	167	IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_MDC),
	168	IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_MDIO),
	169	IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_TD3),
	170	IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_TD2),
	171	IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_TD1),
	172	IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_TD0),
	173	IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_TX_CTL),
	174	IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_TXC),
	175	IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_RX_CTL),
	176	IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_RXC),
	177	IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_RD0),
	178	IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_RD1),
	179	IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_RD2),
	180	IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_RD3),
	181	IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_MDC),
	182	IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_MDIO),
	183	IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_TD3),
	184	IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_TD2),
	185	IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_TD1),
	186	IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_TD0),
	187	IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_TX_CTL),
	188	IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_TXC),
	189	IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_RX_CTL),
	190	IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_RXC),
	191	IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_RD0),
	192	IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_RD1),
	193	IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_RD2),
	194	IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_RD3),
	195	IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_CLK),
	196	IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_CMD),
	197	IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA0),
	198	IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA1),
	199	IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA2),
	200	IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA3),
	201	IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA4),
	202	IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA5),
	203	IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA6),
	204	IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA7),
	205	IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_STROBE),
	206	IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_VSELECT),
	207	IMX_PINCTRL_PIN(IMX93_IOMUXC_SD3_CLK),
	208	IMX_PINCTRL_PIN(IMX93_IOMUXC_SD3_CMD),
	209	IMX_PINCTRL_PIN(IMX93_IOMUXC_SD3_DATA0),
	210	IMX_PINCTRL_PIN(IMX93_IOMUXC_SD3_DATA1),
	211	IMX_PINCTRL_PIN(IMX93_IOMUXC_SD3_DATA2),
	212	IMX_PINCTRL_PIN(IMX93_IOMUXC_SD3_DATA3),
	213	IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_CD_B),
	214	IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_CLK),
	215	IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_CMD),
	216	IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_DATA0),
	217	IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_DATA1),
	218	IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_DATA2),
	219	IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_DATA3),
	220	IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_RESET_B),
	221	IMX_PINCTRL_PIN(IMX93_IOMUXC_I2C1_SCL),
	222	IMX_PINCTRL_PIN(IMX93_IOMUXC_I2C1_SDA),
	223	IMX_PINCTRL_PIN(IMX93_IOMUXC_I2C2_SCL),
	224	IMX_PINCTRL_PIN(IMX93_IOMUXC_I2C2_SDA),
	225	IMX_PINCTRL_PIN(IMX93_IOMUXC_UART1_RXD),
	226	IMX_PINCTRL_PIN(IMX93_IOMUXC_UART1_TXD),
	227	IMX_PINCTRL_PIN(IMX93_IOMUXC_UART2_RXD),
	228	IMX_PINCTRL_PIN(IMX93_IOMUXC_UART2_TXD),
	229	IMX_PINCTRL_PIN(IMX93_IOMUXC_PDM_CLK),
	230	IMX_PINCTRL_PIN(IMX93_IOMUXC_PDM_BIT_STREAM0),
	231	IMX_PINCTRL_PIN(IMX93_IOMUXC_PDM_BIT_STREAM1),
	232	IMX_PINCTRL_PIN(IMX93_IOMUXC_SAI1_TXFS),
	233	IMX_PINCTRL_PIN(IMX93_IOMUXC_SAI1_TXC),
	234	IMX_PINCTRL_PIN(IMX93_IOMUXC_SAI1_TXD0),
	235	IMX_PINCTRL_PIN(IMX93_IOMUXC_SAI1_RXD0),
	236	IMX_PINCTRL_PIN(IMX93_IOMUXC_WDOG_ANY),
	237	};
	238
	239	static const struct imx_pinctrl_soc_info imx93_pinctrl_info = {
	240	.pins = imx93_pinctrl_pads,
	241	.npins = ARRAY_SIZE(imx93_pinctrl_pads),
	242	.gpr_compatible = "fsl,imx93-iomuxc-gpr",
	243	};
	244
	245	static const struct of_device_id imx93_pinctrl_of_match[] = {
	246	{ .compatible = "fsl,imx93-iomuxc", },
	247	{ /* sentinel */ }
	248	};
	249
	250	static int imx93_pinctrl_probe(struct platform_device *pdev)
	251	{
	252	return imx_pinctrl_probe(pdev, &imx93_pinctrl_info);
	253	}
	254
	255	static struct platform_driver imx93_pinctrl_driver = {
	256	.driver = {
	257	.name = "imx93-pinctrl",
	258	.of_match_table = imx93_pinctrl_of_match,
	259	.suppress_bind_attrs = true,
	260	},
	261	.probe = imx93_pinctrl_probe,
	262	};
	263
	264	static int __init imx93_pinctrl_init(void)
	265	{
	266	return platform_driver_register(&imx93_pinctrl_driver);
	267	}
	268	arch_initcall(imx93_pinctrl_init);
	269
	270	MODULE_AUTHOR("Bai Ping <ping.bai@nxp.com>");
	271	MODULE_DESCRIPTION("NXP i.MX93 pinctrl driver");
	272	MODULE_LICENSE("GPL v2");

drivers/pinctrl/intel/pinctrl-alderlake.c+316−1

@@ -2,7 +2,7 @@ · 1 unmodified line
2	/*	2	/*
3	* Intel Alder Lake PCH pinctrl/GPIO driver	3	* Intel Alder Lake PCH pinctrl/GPIO driver
4	*	4	*
5	* Copyright (C) 2020, Intel Corporation	5	* Copyright (C) 2020, 2022 Intel Corporation
6	* Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>	6	* Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
7	*/	7	*/
8		8
@@ -42,6 +42,319 @@ · 33 unmodified lines
42	.ngpps = ARRAY_SIZE(g), \	42	.ngpps = ARRAY_SIZE(g), \
43	}	43	}
44		44
		45	/* Alder Lake-N */
		46	static const struct pinctrl_pin_desc adln_pins[] = {
		47	/* GPP_B */
		48	PINCTRL_PIN(0, "CORE_VID_0"),
		49	PINCTRL_PIN(1, "CORE_VID_1"),
		50	PINCTRL_PIN(2, "GPPC_B_2"),
		51	PINCTRL_PIN(3, "GPPC_B_3"),
		52	PINCTRL_PIN(4, "GPPC_B_4"),
		53	PINCTRL_PIN(5, "GPPC_B_5"),
		54	PINCTRL_PIN(6, "GPPC_B_6"),
		55	PINCTRL_PIN(7, "GPPC_B_7"),
		56	PINCTRL_PIN(8, "GPPC_B_8"),
		57	PINCTRL_PIN(9, "GPPC_B_9"),
		58	PINCTRL_PIN(10, "GPPC_B_10"),
		59	PINCTRL_PIN(11, "GPPC_B_11"),
		60	PINCTRL_PIN(12, "SLP_S0B"),
		61	PINCTRL_PIN(13, "PLTRSTB"),
		62	PINCTRL_PIN(14, "GPPC_B_14"),
		63	PINCTRL_PIN(15, "GPPC_B_15"),
		64	PINCTRL_PIN(16, "GPPC_B_16"),
		65	PINCTRL_PIN(17, "GPPC_B_17"),
		66	PINCTRL_PIN(18, "GPPC_B_18"),
		67	PINCTRL_PIN(19, "GPPC_B_19"),
		68	PINCTRL_PIN(20, "GPPC_B_20"),
		69	PINCTRL_PIN(21, "GPPC_B_21"),
		70	PINCTRL_PIN(22, "GPPC_B_22"),
		71	PINCTRL_PIN(23, "GPPC_B_23"),
		72	PINCTRL_PIN(24, "GSPI0_CLK_LOOPBK"),
		73	PINCTRL_PIN(25, "GSPI1_CLK_LOOPBK"),
		74	/* GPP_T */
		75	PINCTRL_PIN(26, "GPPC_T_0"),
		76	PINCTRL_PIN(27, "GPPC_T_1"),
		77	PINCTRL_PIN(28, "FUSA_DIAGTEST_EN"),
		78	PINCTRL_PIN(29, "FUSA_DIAGTEST_MODE"),
		79	PINCTRL_PIN(30, "GPPC_T_4"),
		80	PINCTRL_PIN(31, "GPPC_T_5"),
		81	PINCTRL_PIN(32, "GPPC_T_6"),
		82	PINCTRL_PIN(33, "GPPC_T_7"),
		83	PINCTRL_PIN(34, "GPPC_T_8"),
		84	PINCTRL_PIN(35, "GPPC_T_9"),
		85	PINCTRL_PIN(36, "GPPC_T_10"),
		86	PINCTRL_PIN(37, "GPPC_T_11"),
		87	PINCTRL_PIN(38, "GPPC_T_12"),
		88	PINCTRL_PIN(39, "GPPC_T_13"),
		89	PINCTRL_PIN(40, "GPPC_T_14"),
		90	PINCTRL_PIN(41, "GPPC_T_15"),
		91	/* GPP_A */
		92	PINCTRL_PIN(42, "ESPI_IO_0"),
		93	PINCTRL_PIN(43, "ESPI_IO_1"),
		94	PINCTRL_PIN(44, "ESPI_IO_2"),
		95	PINCTRL_PIN(45, "ESPI_IO_3"),
		96	PINCTRL_PIN(46, "ESPI_CS0B"),
		97	PINCTRL_PIN(47, "ESPI_ALERT0B"),
		98	PINCTRL_PIN(48, "ESPI_ALERT1B"),
		99	PINCTRL_PIN(49, "GPPC_A_7"),
		100	PINCTRL_PIN(50, "GPPC_A_8"),
		101	PINCTRL_PIN(51, "ESPI_CLK"),
		102	PINCTRL_PIN(52, "ESPI_RESETB"),
		103	PINCTRL_PIN(53, "GPPC_A_11"),
		104	PINCTRL_PIN(54, "GPPC_A_12"),
		105	PINCTRL_PIN(55, "GPPC_A_13"),
		106	PINCTRL_PIN(56, "GPPC_A_14"),
		107	PINCTRL_PIN(57, "GPPC_A_15"),
		108	PINCTRL_PIN(58, "GPPC_A_16"),
		109	PINCTRL_PIN(59, "GPPC_A_17"),
		110	PINCTRL_PIN(60, "GPPC_A_18"),
		111	PINCTRL_PIN(61, "GPPC_A_19"),
		112	PINCTRL_PIN(62, "GPPC_A_20"),
		113	PINCTRL_PIN(63, "GPPC_A_21"),
		114	PINCTRL_PIN(64, "GPPC_A_22"),
		115	PINCTRL_PIN(65, "ESPI_CS1B"),
		116	PINCTRL_PIN(66, "ESPI_CLK_LOOPBK"),
		117	/* GPP_S */
		118	PINCTRL_PIN(67, "GPP_S_0"),
		119	PINCTRL_PIN(68, "GPP_S_1"),
		120	PINCTRL_PIN(69, "GPP_S_2"),
		121	PINCTRL_PIN(70, "GPP_S_3"),
		122	PINCTRL_PIN(71, "GPP_S_4"),
		123	PINCTRL_PIN(72, "GPP_S_5"),
		124	PINCTRL_PIN(73, "GPP_S_6"),
		125	PINCTRL_PIN(74, "GPP_S_7"),
		126	/* GPP_I */
		127	PINCTRL_PIN(75, "GPP_F_0_CNV_BRI_DT_UART0_RTSB"),
		128	PINCTRL_PIN(76, "GPP_F_1_CNV_BRI_RSP_UART0_RXD"),
		129	PINCTRL_PIN(77, "GPP_F_2_CNV_RGI_DT_UART0_TXD"),
		130	PINCTRL_PIN(78, "GPP_F_3_CNV_RGI_RSP_UART0_CTSB"),
		131	PINCTRL_PIN(79, "GPP_F_4_CNV_RF_RESET_B"),
		132	PINCTRL_PIN(80, "GPP_F_5_MODEM_CLKREQ"),
		133	PINCTRL_PIN(81, "GPP_F_6_CNV_PA_BLANKING"),
		134	PINCTRL_PIN(82, "GPP_F_7_EMMC_CMD"),
		135	PINCTRL_PIN(83, "GPP_F_8_EMMC_DATA0"),
		136	PINCTRL_PIN(84, "GPP_F_9_EMMC_DATA1"),
		137	PINCTRL_PIN(85, "GPP_F_10_EMMC_DATA2"),
		138	PINCTRL_PIN(86, "GPP_F_11_EMMC_DATA3"),
		139	PINCTRL_PIN(87, "GPP_F_12_EMMC_DATA4"),
		140	PINCTRL_PIN(88, "GPP_F_13_EMMC_DATA5"),
		141	PINCTRL_PIN(89, "GPP_F_14_EMMC_DATA6"),
		142	PINCTRL_PIN(90, "GPP_F_15_EMMC_DATA7"),
		143	PINCTRL_PIN(91, "GPP_F_16_EMMC_RCLK"),
		144	PINCTRL_PIN(92, "GPP_F_17_EMMC_CLK"),
		145	PINCTRL_PIN(93, "GPP_F_18_EMMC_RESETB"),
		146	PINCTRL_PIN(94, "GPP_F_19_A4WP_PRESENT"),
		147	/* GPP_H */
		148	PINCTRL_PIN(95, "GPPC_H_0"),
		149	PINCTRL_PIN(96, "GPPC_H_1"),
		150	PINCTRL_PIN(97, "GPPC_H_2"),
		151	PINCTRL_PIN(98, "GPPC_H_3"),
		152	PINCTRL_PIN(99, "GPPC_H_4"),
		153	PINCTRL_PIN(100, "GPPC_H_5"),
		154	PINCTRL_PIN(101, "GPPC_H_6"),
		155	PINCTRL_PIN(102, "GPPC_H_7"),
		156	PINCTRL_PIN(103, "GPPC_H_8"),
		157	PINCTRL_PIN(104, "GPPC_H_9"),
		158	PINCTRL_PIN(105, "GPPC_H_10"),
		159	PINCTRL_PIN(106, "GPPC_H_11"),
		160	PINCTRL_PIN(107, "I2C7_SDA"),
		161	PINCTRL_PIN(108, "I2C7_SCL"),
		162	PINCTRL_PIN(109, "GPPC_H_14"),
		163	PINCTRL_PIN(110, "GPPC_H_15"),
		164	PINCTRL_PIN(111, "GPPC_H_16"),
		165	PINCTRL_PIN(112, "GPPC_H_17"),
		166	PINCTRL_PIN(113, "CPU_C10_GATEB"),
		167	PINCTRL_PIN(114, "GPPC_H_19"),
		168	PINCTRL_PIN(115, "GPPC_H_20"),
		169	PINCTRL_PIN(116, "GPPC_H_21"),
		170	PINCTRL_PIN(117, "GPPC_H_22"),
		171	PINCTRL_PIN(118, "GPPC_H_23"),
		172	/* GPP_D */
		173	PINCTRL_PIN(119, "GPPC_D_0"),
		174	PINCTRL_PIN(120, "GPPC_D_1"),
		175	PINCTRL_PIN(121, "GPPC_D_2"),
		176	PINCTRL_PIN(122, "GPPC_D_3"),
		177	PINCTRL_PIN(123, "GPPC_D_4"),
		178	PINCTRL_PIN(124, "GPPC_D_5"),
		179	PINCTRL_PIN(125, "GPPC_D_6"),
		180	PINCTRL_PIN(126, "GPPC_D_7"),
		181	PINCTRL_PIN(127, "GPPC_D_8"),
		182	PINCTRL_PIN(128, "BSSB_LS2_RX"),
		183	PINCTRL_PIN(129, "BSSB_LS2_TX"),
		184	PINCTRL_PIN(130, "BSSB_LS3_RX"),
		185	PINCTRL_PIN(131, "BSSB_LS3_TX"),
		186	PINCTRL_PIN(132, "GPPC_D_13"),
		187	PINCTRL_PIN(133, "GPPC_D_14"),
		188	PINCTRL_PIN(134, "GPPC_D_15"),
		189	PINCTRL_PIN(135, "GPPC_D_16"),
		190	PINCTRL_PIN(136, "GPPC_D_17"),
		191	PINCTRL_PIN(137, "GPPC_D_18"),
		192	PINCTRL_PIN(138, "GPPC_D_19"),
		193	PINCTRL_PIN(139, "GSPI2_CLK_LOOPBK"),
		194	/* vGPIO */
		195	PINCTRL_PIN(140, "CNV_BTEN"),
		196	PINCTRL_PIN(141, "CNV_BT_HOST_WAKEB"),
		197	PINCTRL_PIN(142, "CNV_BT_IF_SELECT"),
		198	PINCTRL_PIN(143, "vCNV_BT_UART_TXD"),
		199	PINCTRL_PIN(144, "vCNV_BT_UART_RXD"),
		200	PINCTRL_PIN(145, "vCNV_BT_UART_CTS_B"),
		201	PINCTRL_PIN(146, "vCNV_BT_UART_RTS_B"),
		202	PINCTRL_PIN(147, "vCNV_MFUART1_TXD"),
		203	PINCTRL_PIN(148, "vCNV_MFUART1_RXD"),
		204	PINCTRL_PIN(149, "vCNV_MFUART1_CTS_B"),
		205	PINCTRL_PIN(150, "vCNV_MFUART1_RTS_B"),
		206	PINCTRL_PIN(151, "vUART0_TXD"),
		207	PINCTRL_PIN(152, "vUART0_RXD"),
		208	PINCTRL_PIN(153, "vUART0_CTS_B"),
		209	PINCTRL_PIN(154, "vUART0_RTS_B"),
		210	PINCTRL_PIN(155, "vISH_UART0_TXD"),
		211	PINCTRL_PIN(156, "vISH_UART0_RXD"),
		212	PINCTRL_PIN(157, "vISH_UART0_CTS_B"),
		213	PINCTRL_PIN(158, "vISH_UART0_RTS_B"),
		214	PINCTRL_PIN(159, "vCNV_BT_I2S_BCLK"),
		215	PINCTRL_PIN(160, "vCNV_BT_I2S_WS_SYNC"),
		216	PINCTRL_PIN(161, "vCNV_BT_I2S_SDO"),
		217	PINCTRL_PIN(162, "vCNV_BT_I2S_SDI"),
		218	PINCTRL_PIN(163, "vI2S2_SCLK"),
		219	PINCTRL_PIN(164, "vI2S2_SFRM"),
		220	PINCTRL_PIN(165, "vI2S2_TXD"),
		221	PINCTRL_PIN(166, "vI2S2_RXD"),
		222	PINCTRL_PIN(167, "THC0_WOT_INT"),
		223	PINCTRL_PIN(168, "THC1_WOT_INT"),
		224	/* GPP_C */
		225	PINCTRL_PIN(169, "SMBCLK"),
		226	PINCTRL_PIN(170, "SMBDATA"),
		227	PINCTRL_PIN(171, "SMBALERTB"),
		228	PINCTRL_PIN(172, "SML0CLK"),
		229	PINCTRL_PIN(173, "SML0DATA"),
		230	PINCTRL_PIN(174, "GPPC_C_5"),
		231	PINCTRL_PIN(175, "GPPC_C_6"),
		232	PINCTRL_PIN(176, "GPPC_C_7"),
		233	PINCTRL_PIN(177, "GPPC_C_8"),
		234	PINCTRL_PIN(178, "GPPC_C_9"),
		235	PINCTRL_PIN(179, "GPPC_C_10"),
		236	PINCTRL_PIN(180, "GPPC_C_11"),
		237	PINCTRL_PIN(181, "GPPC_C_12"),
		238	PINCTRL_PIN(182, "GPPC_C_13"),
		239	PINCTRL_PIN(183, "GPPC_C_14"),
		240	PINCTRL_PIN(184, "GPPC_C_15"),
		241	PINCTRL_PIN(185, "GPPC_C_16"),
		242	PINCTRL_PIN(186, "GPPC_C_17"),
		243	PINCTRL_PIN(187, "GPPC_C_18"),
		244	PINCTRL_PIN(188, "GPPC_C_19"),
		245	PINCTRL_PIN(189, "GPPC_C_20"),
		246	PINCTRL_PIN(190, "GPPC_C_21"),
		247	PINCTRL_PIN(191, "GPPC_C_22"),
		248	PINCTRL_PIN(192, "GPPC_C_23"),
		249	/* GPP_F */
		250	PINCTRL_PIN(193, "CNV_BRI_DT"),
		251	PINCTRL_PIN(194, "CNV_BRI_RSP"),
		252	PINCTRL_PIN(195, "CNV_RGI_DT"),
		253	PINCTRL_PIN(196, "CNV_RGI_RSP"),
		254	PINCTRL_PIN(197, "CNV_RF_RESET_B"),
		255	PINCTRL_PIN(198, "MODEM_CLKREQ"),
		256	PINCTRL_PIN(199, "GPPC_F_6"),
		257	PINCTRL_PIN(200, "GPPC_F_7"),
		258	PINCTRL_PIN(201, "GPPC_F_8"),
		259	PINCTRL_PIN(202, "BOOTMPC"),
		260	PINCTRL_PIN(203, "GPPC_F_10"),
		261	PINCTRL_PIN(204, "GPPC_F_11"),
		262	PINCTRL_PIN(205, "GPPC_F_12"),
		263	PINCTRL_PIN(206, "GPPC_F_13"),
		264	PINCTRL_PIN(207, "GPPC_F_14"),
		265	PINCTRL_PIN(208, "GPPC_F_15"),
		266	PINCTRL_PIN(209, "GPPC_F_16"),
		267	PINCTRL_PIN(210, "GPPC_F_17"),
		268	PINCTRL_PIN(211, "GPPC_F_18"),
		269	PINCTRL_PIN(212, "GPPC_F_19"),
		270	PINCTRL_PIN(213, "EXT_PWR_GATEB"),
		271	PINCTRL_PIN(214, "EXT_PWR_GATE2B"),
		272	PINCTRL_PIN(215, "GPPC_F_22"),
		273	PINCTRL_PIN(216, "GPPC_F_23"),
		274	PINCTRL_PIN(217, "GPPF_CLK_LOOPBACK"),
		275	/* HVCMOS */
		276	PINCTRL_PIN(218, "L_BKLTEN"),
		277	PINCTRL_PIN(219, "L_BKLTCTL"),
		278	PINCTRL_PIN(220, "L_VDDEN"),
		279	PINCTRL_PIN(221, "SYS_PWROK"),
		280	PINCTRL_PIN(222, "SYS_RESETB"),
		281	PINCTRL_PIN(223, "MLK_RSTB"),
		282	/* GPP_E */
		283	PINCTRL_PIN(224, "GPPC_E_0"),
		284	PINCTRL_PIN(225, "GPPC_E_1"),
		285	PINCTRL_PIN(226, "GPPC_E_2"),
		286	PINCTRL_PIN(227, "GPPC_E_3"),
		287	PINCTRL_PIN(228, "GPPC_E_4"),
		288	PINCTRL_PIN(229, "GPPC_E_5"),
		289	PINCTRL_PIN(230, "GPPC_E_6"),
		290	PINCTRL_PIN(231, "GPPC_E_7"),
		291	PINCTRL_PIN(232, "GPPC_E_8"),
		292	PINCTRL_PIN(233, "GPPC_E_9"),
		293	PINCTRL_PIN(234, "GPPC_E_10"),
		294	PINCTRL_PIN(235, "GPPC_E_11"),
		295	PINCTRL_PIN(236, "GPPC_E_12"),
		296	PINCTRL_PIN(237, "GPPC_E_13"),
		297	PINCTRL_PIN(238, "GPPC_E_14"),
		298	PINCTRL_PIN(239, "FIVR_DIGPB_0"),
		299	PINCTRL_PIN(240, "FIVR_DIGPB_1"),
		300	PINCTRL_PIN(241, "GPPC_E_17"),
		301	PINCTRL_PIN(242, "BSSB_LS0_RX"),
		302	PINCTRL_PIN(243, "BSSB_LS0_TX"),
		303	PINCTRL_PIN(244, "BSSB_LS1_RX"),
		304	PINCTRL_PIN(245, "BSSB_LS1_TX"),
		305	PINCTRL_PIN(246, "DNX_FORCE_RELOAD"),
		306	PINCTRL_PIN(247, "GPPC_E_23"),
		307	PINCTRL_PIN(248, "GPPE_CLK_LOOPBACK"),
		308	/* GPP_R */
		309	PINCTRL_PIN(249, "HDA_BCLK"),
		310	PINCTRL_PIN(250, "HDA_SYNC"),
		311	PINCTRL_PIN(251, "HDA_SDO"),
		312	PINCTRL_PIN(252, "HDA_SDI_0"),
		313	PINCTRL_PIN(253, "HDA_RSTB"),
		314	PINCTRL_PIN(254, "GPP_R_5"),
		315	PINCTRL_PIN(255, "GPP_R_6"),
		316	PINCTRL_PIN(256, "GPP_R_7"),
		317	};
		318
		319	static const struct intel_padgroup adln_community0_gpps[] = {
		320	ADL_GPP(0, 0, 25, 0), /* GPP_B */
		321	ADL_GPP(1, 26, 41, 32), /* GPP_T */
		322	ADL_GPP(2, 42, 66, 64), /* GPP_A */
		323	};
		324
		325	static const struct intel_padgroup adln_community1_gpps[] = {
		326	ADL_GPP(0, 67, 74, 96), /* GPP_S */
		327	ADL_GPP(1, 75, 94, 128), /* GPP_I */
		328	ADL_GPP(2, 95, 118, 160), /* GPP_H */
		329	ADL_GPP(3, 119, 139, 192), /* GPP_D */
		330	ADL_GPP(4, 140, 168, 224), /* vGPIO */
		331	};
		332
		333	static const struct intel_padgroup adln_community4_gpps[] = {
		334	ADL_GPP(0, 169, 192, 256), /* GPP_C */
		335	ADL_GPP(1, 193, 217, 288), /* GPP_F */
		336	ADL_GPP(2, 218, 223, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
		337	ADL_GPP(3, 224, 248, 320), /* GPP_E */
		338	};
		339
		340	static const struct intel_padgroup adln_community5_gpps[] = {
		341	ADL_GPP(0, 249, 256, 352), /* GPP_R */
		342	};
		343
		344	static const struct intel_community adln_communities[] = {
		345	ADL_COMMUNITY(0, 0, 66, adln_community0_gpps),
		346	ADL_COMMUNITY(1, 67, 168, adln_community1_gpps),
		347	ADL_COMMUNITY(2, 169, 248, adln_community4_gpps),
		348	ADL_COMMUNITY(3, 249, 256, adln_community5_gpps),
		349	};
		350
		351	static const struct intel_pinctrl_soc_data adln_soc_data = {
		352	.pins = adln_pins,
		353	.npins = ARRAY_SIZE(adln_pins),
		354	.communities = adln_communities,
		355	.ncommunities = ARRAY_SIZE(adln_communities),
		356	};
		357
45	/* Alder Lake-S */	358	/* Alder Lake-S */
46	static const struct pinctrl_pin_desc adls_pins[] = {	359	static const struct pinctrl_pin_desc adls_pins[] = {
47	/* GPP_I */	360	/* GPP_I */
@@ -416,6 +729,8 @@ static const struct intel_pinctrl_soc_data adls_soc_data = { · 368 unmodified lines
416		729
417	static const struct acpi_device_id adl_pinctrl_acpi_match[] = {	730	static const struct acpi_device_id adl_pinctrl_acpi_match[] = {
418	{ "INTC1056", (kernel_ulong_t)&adls_soc_data },	731	{ "INTC1056", (kernel_ulong_t)&adls_soc_data },
		732	{ "INTC1057", (kernel_ulong_t)&adln_soc_data },
		733	{ "INTC1085", (kernel_ulong_t)&adls_soc_data },
419	{ }	734	{ }
420	};	735	};
421	MODULE_DEVICE_TABLE(acpi, adl_pinctrl_acpi_match);	736	MODULE_DEVICE_TABLE(acpi, adl_pinctrl_acpi_match);

drivers/pinctrl/intel/pinctrl-baytrail.c+53−2

@@ -32,6 +32,7 @@ · 31 unmodified lines
32	#define BYT_VAL_REG 0x008	32	#define BYT_VAL_REG 0x008
33	#define BYT_DFT_REG 0x00c	33	#define BYT_DFT_REG 0x00c
34	#define BYT_INT_STAT_REG 0x800	34	#define BYT_INT_STAT_REG 0x800
		35	#define BYT_DIRECT_IRQ_REG 0x980
35	#define BYT_DEBOUNCE_REG 0x9d0	36	#define BYT_DEBOUNCE_REG 0x9d0
36		37
37	/* BYT_CONF0_REG register bits */	38	/* BYT_CONF0_REG register bits */
@@ -1475,6 +1476,51 @@ static void byt_gpio_irq_handler(struct irq_desc *desc) · 1437 unmodified lines
1475	chip->irq_eoi(data);	1476	chip->irq_eoi(data);
1476	}	1477	}
1477		1478
		1479	static bool byt_direct_irq_sanity_check(struct intel_pinctrl *vg, int pin, u32 conf0)
		1480	{
		1481	int direct_irq, ioapic_direct_irq_base;
		1482	u8 *match, direct_irq_mux[16];
		1483	u32 trig;
		1484
		1485	memcpy_fromio(direct_irq_mux, vg->communities->pad_regs + BYT_DIRECT_IRQ_REG,
		1486	sizeof(direct_irq_mux));
		1487	match = memchr(direct_irq_mux, pin, sizeof(direct_irq_mux));
		1488	if (!match) {
		1489	dev_warn(vg->dev, FW_BUG "pin %i: direct_irq_en set but no IRQ assigned, clearing\n", pin);
		1490	return false;
		1491	}
		1492
		1493	direct_irq = match - direct_irq_mux;
		1494	/* Base IO-APIC pin numbers come from atom-e3800-family-datasheet.pdf */
		1495	ioapic_direct_irq_base = (vg->communities->npins == BYT_NGPIO_SCORE) ? 51 : 67;
		1496	dev_dbg(vg->dev, "Pin %i: uses direct IRQ %d (IO-APIC %d)\n", pin,
		1497	direct_irq, direct_irq + ioapic_direct_irq_base);
		1498
		1499	/*
		1500	* Testing has shown that the way direct IRQs work is that the combination of the
		1501	* direct-irq-en flag and the direct IRQ mux connect the output of the GPIO's IRQ
		1502	* trigger block, which normally sets the status flag in the IRQ status reg at
		1503	* 0x800, to one of the IO-APIC pins according to the mux registers.
		1504	*
		1505	* This means that:
		1506	* 1. The TRIG_MASK bits must be set to configure the GPIO's IRQ trigger block
		1507	* 2. The TRIG_LVL bit must be set, so that the GPIO's input value is directly
		1508	* passed (1:1 or inverted) to the IO-APIC pin, if TRIG_LVL is not set,
		1509	* selecting edge mode operation then on the first edge the IO-APIC pin goes
		1510	* high, but since no write-to-clear write will be done to the IRQ status reg
		1511	* at 0x800, the detected edge condition will never get cleared.
		1512	*/
		1513	trig = conf0 & BYT_TRIG_MASK;
		1514	if (trig != (BYT_TRIG_POS \| BYT_TRIG_LVL) &&
		1515	trig != (BYT_TRIG_NEG \| BYT_TRIG_LVL)) {
		1516	dev_warn(vg->dev, FW_BUG "pin %i: direct_irq_en set without trigger (conf0: %xh), clearing\n",
		1517	pin, conf0);
		1518	return false;
		1519	}
		1520
		1521	return true;
		1522	}
		1523
1478	static void byt_init_irq_valid_mask(struct gpio_chip *chip,	1524	static void byt_init_irq_valid_mask(struct gpio_chip *chip,
1479	unsigned long *valid_mask,	1525	unsigned long *valid_mask,
1480	unsigned int ngpios)	1526	unsigned int ngpios)
@@ -1502,8 +1548,13 @@ static void byt_init_irq_valid_mask(struct gpio_chip *chip, · 21 unmodified lines
1502		1548
1503	value = readl(reg);	1549	value = readl(reg);
1504	if (value & BYT_DIRECT_IRQ_EN) {	1550	if (value & BYT_DIRECT_IRQ_EN) {
1505	clear_bit(i, valid_mask);	1551	if (byt_direct_irq_sanity_check(vg, i, value)) {
1506	dev_dbg(vg->dev, "excluding GPIO %d from IRQ domain\n", i);	1552	clear_bit(i, valid_mask);
		1553	} else {
		1554	value &= ~(BYT_DIRECT_IRQ_EN \| BYT_TRIG_POS \|
		1555	BYT_TRIG_NEG \| BYT_TRIG_LVL);
		1556	writel(value, reg);
		1557	}
1507	} else if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i)) {	1558	} else if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i)) {
1508	byt_gpio_clear_triggering(vg, i);	1559	byt_gpio_clear_triggering(vg, i);
1509	dev_dbg(vg->dev, "disabling GPIO %d\n", i);	1560	dev_dbg(vg->dev, "disabling GPIO %d\n", i);

drivers/pinctrl/intel/pinctrl-icelake.c+283−8

@@ -2,7 +2,7 @@ · 1 unmodified line
2	/*	2	/*
3	* Intel Ice Lake PCH pinctrl/GPIO driver	3	* Intel Ice Lake PCH pinctrl/GPIO driver
4	*	4	*
5	* Copyright (C) 2018, Intel Corporation	5	* Copyright (C) 2018, 2022 Intel Corporation
6	* Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>	6	* Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
7	* Mika Westerberg <mika.westerberg@linux.intel.com>	7	* Mika Westerberg <mika.westerberg@linux.intel.com>
8	*/	8	*/
@@ -19,7 +19,8 @@ · 10 unmodified lines
19	#define ICL_PADCFGLOCK 0x080	19	#define ICL_PADCFGLOCK 0x080
20	#define ICL_HOSTSW_OWN 0x0b0	20	#define ICL_HOSTSW_OWN 0x0b0
21	#define ICL_GPI_IS 0x100	21	#define ICL_GPI_IS 0x100
22	#define ICL_GPI_IE 0x110	22	#define ICL_LP_GPI_IE 0x110
		23	#define ICL_N_GPI_IE 0x120
23		24
24	#define ICL_GPP(r, s, e, g) \	25	#define ICL_GPP(r, s, e, g) \
25	{ \	26	{ \
@@ -29,20 +30,26 @@ · 3 unmodified lines
29	.gpio_base = (g), \	30	.gpio_base = (g), \
30	}	31	}
31		32
32	#define ICL_COMMUNITY(b, s, e, g) \	33	#define ICL_COMMUNITY(b, s, e, ie, g) \
33	{ \	34	{ \
34	.barno = (b), \	35	.barno = (b), \
35	.padown_offset = ICL_PAD_OWN, \	36	.padown_offset = ICL_PAD_OWN, \
36	.padcfglock_offset = ICL_PADCFGLOCK, \	37	.padcfglock_offset = ICL_PADCFGLOCK, \
37	.hostown_offset = ICL_HOSTSW_OWN, \	38	.hostown_offset = ICL_HOSTSW_OWN, \
38	.is_offset = ICL_GPI_IS, \	39	.is_offset = ICL_GPI_IS, \
39	.ie_offset = ICL_GPI_IE, \	40	.ie_offset = (ie), \
40	.pin_base = (s), \	41	.pin_base = (s), \
41	.npins = ((e) - (s) + 1), \	42	.npins = ((e) - (s) + 1), \
42	.gpps = (g), \	43	.gpps = (g), \
43	.ngpps = ARRAY_SIZE(g), \	44	.ngpps = ARRAY_SIZE(g), \
44	}	45	}
45		46
		47	#define ICL_LP_COMMUNITY(b, s, e, g) \
		48	ICL_COMMUNITY(b, s, e, ICL_LP_GPI_IE, g)
		49
		50	#define ICL_N_COMMUNITY(b, s, e, g) \
		51	ICL_COMMUNITY(b, s, e, ICL_N_GPI_IE, g)
		52
46	/* Ice Lake-LP */	53	/* Ice Lake-LP */
47	static const struct pinctrl_pin_desc icllp_pins[] = {	54	static const struct pinctrl_pin_desc icllp_pins[] = {
48	/* GPP_G */	55	/* GPP_G */
@@ -329,10 +336,10 @@ static const struct intel_padgroup icllp_community5_gpps[] = { · 280 unmodified lines
329	};	336	};
330		337
331	static const struct intel_community icllp_communities[] = {	338	static const struct intel_community icllp_communities[] = {
332	ICL_COMMUNITY(0, 0, 58, icllp_community0_gpps),	339	ICL_LP_COMMUNITY(0, 0, 58, icllp_community0_gpps),
333	ICL_COMMUNITY(1, 59, 152, icllp_community1_gpps),	340	ICL_LP_COMMUNITY(1, 59, 152, icllp_community1_gpps),
334	ICL_COMMUNITY(2, 153, 215, icllp_community4_gpps),	341	ICL_LP_COMMUNITY(2, 153, 215, icllp_community4_gpps),
335	ICL_COMMUNITY(3, 216, 240, icllp_community5_gpps),	342	ICL_LP_COMMUNITY(3, 216, 240, icllp_community5_gpps),
336	};	343	};
337		344
338	static const unsigned int icllp_spi0_pins[] = { 22, 23, 24, 25, 26 };	345	static const unsigned int icllp_spi0_pins[] = { 22, 23, 24, 25, 26 };
@@ -403,10 +410,278 @@ static const struct intel_pinctrl_soc_data icllp_soc_data = { · 64 unmodified lines
403	.ncommunities = ARRAY_SIZE(icllp_communities),	410	.ncommunities = ARRAY_SIZE(icllp_communities),
404	};	411	};
405		412
		413	/* Ice Lake-N */
		414	static const struct pinctrl_pin_desc icln_pins[] = {
		415	/* SPI */
		416	PINCTRL_PIN(0, "SPI0_IO_2"),
		417	PINCTRL_PIN(1, "SPI0_IO_3"),
		418	PINCTRL_PIN(2, "SPI0_MOSI_IO_0"),
		419	PINCTRL_PIN(3, "SPI0_MISO_IO_1"),
		420	PINCTRL_PIN(4, "SPI0_TPM_CSB"),
		421	PINCTRL_PIN(5, "SPI0_FLASH_0_CSB"),
		422	PINCTRL_PIN(6, "SPI0_FLASH_1_CSB"),
		423	PINCTRL_PIN(7, "SPI0_CLK"),
		424	PINCTRL_PIN(8, "SPI0_CLK_LOOPBK"),
		425	/* GPP_B */
		426	PINCTRL_PIN(9, "CORE_VID_0"),
		427	PINCTRL_PIN(10, "CORE_VID_1"),
		428	PINCTRL_PIN(11, "VRALERTB"),
		429	PINCTRL_PIN(12, "CPU_GP_2"),
		430	PINCTRL_PIN(13, "CPU_GP_3"),
		431	PINCTRL_PIN(14, "SRCCLKREQB_0"),
		432	PINCTRL_PIN(15, "SRCCLKREQB_1"),
		433	PINCTRL_PIN(16, "SRCCLKREQB_2"),
		434	PINCTRL_PIN(17, "SRCCLKREQB_3"),
		435	PINCTRL_PIN(18, "SRCCLKREQB_4"),
		436	PINCTRL_PIN(19, "SRCCLKREQB_5"),
		437	PINCTRL_PIN(20, "EXT_PWR_GATEB"),
		438	PINCTRL_PIN(21, "SLP_S0B"),
		439	PINCTRL_PIN(22, "PLTRSTB"),
		440	PINCTRL_PIN(23, "SPKR_GSPI0_CS1B"),
		441	PINCTRL_PIN(24, "GSPI0_CS0B"),
		442	PINCTRL_PIN(25, "GSPI0_CLK"),
		443	PINCTRL_PIN(26, "GSPI0_MISO_TBT_LSX3_A"),
		444	PINCTRL_PIN(27, "GSPI0_MOSI_TBT_LSX3_B"),
		445	PINCTRL_PIN(28, "GSPI1_CS0B"),
		446	PINCTRL_PIN(29, "GSPI1_CLK_NFC_CLK"),
		447	PINCTRL_PIN(30, "GSPI1_MISO_NFC_CLKREQ"),
		448	PINCTRL_PIN(31, "GSPI1_MOSI"),
		449	PINCTRL_PIN(32, "GSPI1_CS1B"),
		450	PINCTRL_PIN(33, "GSPI0_CLK_LOOPBK"),
		451	PINCTRL_PIN(34, "GSPI1_CLK_LOOPBK"),
		452	/* GPP_A */
		453	PINCTRL_PIN(35, "ESPI_IO_0"),
		454	PINCTRL_PIN(36, "ESPI_IO_1"),
		455	PINCTRL_PIN(37, "ESPI_IO_2"),
		456	PINCTRL_PIN(38, "ESPI_IO_3"),
		457	PINCTRL_PIN(39, "ESPI_CSB"),
		458	PINCTRL_PIN(40, "ESPI_CLK"),
		459	PINCTRL_PIN(41, "ESPI_RESETB"),
		460	PINCTRL_PIN(42, "SMBCLK"),
		461	PINCTRL_PIN(43, "SMBDATA"),
		462	PINCTRL_PIN(44, "SMBALERTB"),
		463	PINCTRL_PIN(45, "CPU_GP_0"),
		464	PINCTRL_PIN(46, "CPU_GP_1"),
		465	PINCTRL_PIN(47, "USB2_OCB_1"),
		466	PINCTRL_PIN(48, "USB2_OCB_2"),
		467	PINCTRL_PIN(49, "USB2_OCB_3"),
		468	PINCTRL_PIN(50, "DDSP_HPD_A_TIME_SYNC_0"),
		469	PINCTRL_PIN(51, "DDSP_HPD_B_TIME_SYNC_1"),
		470	PINCTRL_PIN(52, "DDSP_HPD_C"),
		471	PINCTRL_PIN(53, "USB2_OCB_0"),
		472	PINCTRL_PIN(54, "PCHHOTB"),
		473	PINCTRL_PIN(55, "ESPI_CLK_LOOPBK"),
		474	/* GPP_S */
		475	PINCTRL_PIN(56, "SNDW1_CLK"),
		476	PINCTRL_PIN(57, "SNDW1_DATA"),
		477	PINCTRL_PIN(58, "SNDW2_CLK"),
		478	PINCTRL_PIN(59, "SNDW2_DATA"),
		479	PINCTRL_PIN(60, "SNDW3_CLK_DMIC_CLK_1"),
		480	PINCTRL_PIN(61, "SNDW3_DATA_DMIC_DATA_1"),
		481	PINCTRL_PIN(62, "SNDW4_CLK_DMIC_CLK_0"),
		482	PINCTRL_PIN(63, "SNDW4_DATA_DMIC_DATA_0"),
		483	/* GPP_R */
		484	PINCTRL_PIN(64, "HDA_BCLK"),
		485	PINCTRL_PIN(65, "HDA_SYNC"),
		486	PINCTRL_PIN(66, "HDA_SDO"),
		487	PINCTRL_PIN(67, "HDA_SDI_0"),
		488	PINCTRL_PIN(68, "HDA_RSTB"),
		489	PINCTRL_PIN(69, "HDA_SDI_1_I2S1_RXD"),
		490	PINCTRL_PIN(70, "I2S1_SFRM"),
		491	PINCTRL_PIN(71, "I2S1_TXD"),
		492	/* GPP_H */
		493	PINCTRL_PIN(72, "GPPC_H_0"),
		494	PINCTRL_PIN(73, "CNV_RF_RESET_B"),
		495	PINCTRL_PIN(74, "MODEM_CLKREQ"),
		496	PINCTRL_PIN(75, "SX_EXIT_HOLDOFFB"),
		497	PINCTRL_PIN(76, "I2C2_SDA"),
		498	PINCTRL_PIN(77, "I2C2_SCL"),
		499	PINCTRL_PIN(78, "I2C3_SDA"),
		500	PINCTRL_PIN(79, "I2C3_SCL"),
		501	PINCTRL_PIN(80, "I2C4_SDA"),
		502	PINCTRL_PIN(81, "I2C4_SCL"),
		503	PINCTRL_PIN(82, "CPU_VCCIO_PWR_GATEB"),
		504	PINCTRL_PIN(83, "I2S2_SCLK"),
		505	PINCTRL_PIN(84, "CNV_RF_RESET_B"),
		506	PINCTRL_PIN(85, "MODEM_CLKREQ"),
		507	PINCTRL_PIN(86, "I2S2_RXD"),
		508	PINCTRL_PIN(87, "I2S1_SCLK"),
		509	PINCTRL_PIN(88, "GPPC_H_16"),
		510	PINCTRL_PIN(89, "GPPC_H_17"),
		511	PINCTRL_PIN(90, "GPPC_H_18"),
		512	PINCTRL_PIN(91, "GPPC_H_19"),
		513	PINCTRL_PIN(92, "GPPC_H_20"),
		514	PINCTRL_PIN(93, "GPPC_H_21"),
		515	PINCTRL_PIN(94, "GPPC_H_22"),
		516	PINCTRL_PIN(95, "GPPC_H_23"),
		517	/* GPP_D */
		518	PINCTRL_PIN(96, "SPI1_CSB_BK_0_SBK_0"),
		519	PINCTRL_PIN(97, "SPI1_CLK_BK_1_SBK_1"),
		520	PINCTRL_PIN(98, "SPI1_MISO_IO_1_BK_2_SBK_2"),
		521	PINCTRL_PIN(99, "SPI1_MOSI_IO_0_BK_3_SBK_3"),
		522	PINCTRL_PIN(100, "ISH_I2C0_SDA"),
		523	PINCTRL_PIN(101, "ISH_I2C0_SCL"),
		524	PINCTRL_PIN(102, "ISH_I2C1_SDA"),
		525	PINCTRL_PIN(103, "ISH_I2C1_SCL"),
		526	PINCTRL_PIN(104, "ISH_SPI_CSB_GSPI2_CS0B_TBT_LSX4_A"),
		527	PINCTRL_PIN(105, "ISH_SPI_CLK_GSPI2_CLK_TBT_LSX4_B"),
		528	PINCTRL_PIN(106, "ISH_SPI_MISO_GSPI2_MISO_TBT_LSX5_A"),
		529	PINCTRL_PIN(107, "ISH_SPI_MOSI_GSPI2_MOSI_TBT_LSX5_B"),
		530	PINCTRL_PIN(108, "ISH_UART0_RXD_I2C4B_SDA"),
		531	PINCTRL_PIN(109, "ISH_UART0_TXD_I2C4B_SCL"),
		532	PINCTRL_PIN(110, "ISH_UART0_RTSB_GSPI2_CS1B"),
		533	PINCTRL_PIN(111, "ISH_UART0_CTSB_CNV_WCEN"),
		534	PINCTRL_PIN(112, "SPI1_IO_2"),
		535	PINCTRL_PIN(113, "SPI1_IO_3"),
		536	PINCTRL_PIN(114, "I2S_MCLK"),
		537	PINCTRL_PIN(115, "CNV_MFUART2_RXD"),
		538	PINCTRL_PIN(116, "CNV_MFUART2_TXD"),
		539	PINCTRL_PIN(117, "CNV_PA_BLANKING"),
		540	PINCTRL_PIN(118, "I2C5_SDA_ISH_I2C2_SDA"),
		541	PINCTRL_PIN(119, "I2C5_SCL_ISH_I2C2_SCL"),
		542	PINCTRL_PIN(120, "GSPI2_CLK_LOOPBK"),
		543	PINCTRL_PIN(121, "SPI1_CLK_LOOPBK"),
		544	/* vGPIO */
		545	PINCTRL_PIN(122, "CNV_BTEN"),
		546	PINCTRL_PIN(123, "CNV_WCEN"),
		547	PINCTRL_PIN(124, "CNV_BT_HOST_WAKEB"),
		548	PINCTRL_PIN(125, "CNV_BT_IF_SELECT"),
		549	PINCTRL_PIN(126, "vCNV_BT_UART_TXD"),
		550	PINCTRL_PIN(127, "vCNV_BT_UART_RXD"),
		551	PINCTRL_PIN(128, "vCNV_BT_UART_CTS_B"),
		552	PINCTRL_PIN(129, "vCNV_BT_UART_RTS_B"),
		553	PINCTRL_PIN(130, "vCNV_MFUART1_TXD"),
		554	PINCTRL_PIN(131, "vCNV_MFUART1_RXD"),
		555	PINCTRL_PIN(132, "vCNV_MFUART1_CTS_B"),
		556	PINCTRL_PIN(133, "vCNV_MFUART1_RTS_B"),
		557	PINCTRL_PIN(134, "vUART0_TXD"),
		558	PINCTRL_PIN(135, "vUART0_RXD"),
		559	PINCTRL_PIN(136, "vUART0_CTS_B"),
		560	PINCTRL_PIN(137, "vUART0_RTS_B"),
		561	PINCTRL_PIN(138, "vISH_UART0_TXD"),
		562	PINCTRL_PIN(139, "vISH_UART0_RXD"),
		563	PINCTRL_PIN(140, "vISH_UART0_CTS_B"),
		564	PINCTRL_PIN(141, "vISH_UART0_RTS_B"),
		565	PINCTRL_PIN(142, "vCNV_BT_I2S_BCLK"),
		566	PINCTRL_PIN(143, "vCNV_BT_I2S_WS_SYNC"),
		567	PINCTRL_PIN(144, "vCNV_BT_I2S_SDO"),
		568	PINCTRL_PIN(145, "vCNV_BT_I2S_SDI"),
		569	PINCTRL_PIN(146, "vI2S2_SCLK"),
		570	PINCTRL_PIN(147, "vI2S2_SFRM"),
		571	PINCTRL_PIN(148, "vI2S2_TXD"),
		572	PINCTRL_PIN(149, "vI2S2_RXD"),
		573	PINCTRL_PIN(150, "vSD3_CD_B"),
		574	/* GPP_C */
		575	PINCTRL_PIN(151, "GPPC_C_0"),
		576	PINCTRL_PIN(152, "GPPC_C_1"),
		577	PINCTRL_PIN(153, "GPPC_C_2"),
		578	PINCTRL_PIN(154, "GPPC_C_3"),
		579	PINCTRL_PIN(155, "GPPC_C_4"),
		580	PINCTRL_PIN(156, "GPPC_C_5"),
		581	PINCTRL_PIN(157, "SUSWARNB_SUSPWRDNACK"),
		582	PINCTRL_PIN(158, "SUSACKB"),
		583	PINCTRL_PIN(159, "UART0_RXD"),
		584	PINCTRL_PIN(160, "UART0_TXD"),
		585	PINCTRL_PIN(161, "UART0_RTSB"),
		586	PINCTRL_PIN(162, "UART0_CTSB"),
		587	PINCTRL_PIN(163, "UART1_RXD_ISH_UART1_RXD"),
		588	PINCTRL_PIN(164, "UART1_TXD_ISH_UART1_TXD"),
		589	PINCTRL_PIN(165, "UART1_RTSB_ISH_UART1_RTSB"),
		590	PINCTRL_PIN(166, "UART1_CTSB_ISH_UART1_CTSB"),
		591	PINCTRL_PIN(167, "I2C0_SDA"),
		592	PINCTRL_PIN(168, "I2C0_SCL"),
		593	PINCTRL_PIN(169, "I2C1_SDA"),
		594	PINCTRL_PIN(170, "I2C1_SCL"),
		595	PINCTRL_PIN(171, "UART2_RXD_CNV_MFUART0_RXD"),
		596	PINCTRL_PIN(172, "UART2_TXD_CNV_MFUART0_TXD"),
		597	PINCTRL_PIN(173, "UART2_RTSB_CNV_MFUART0_RTS_B"),
		598	PINCTRL_PIN(174, "UART2_CTSB_CNV_MFUART0_CTS_B"),
		599	/* HVCMOS */
		600	PINCTRL_PIN(175, "L_BKLTEN"),
		601	PINCTRL_PIN(176, "L_BKLTCTL"),
		602	PINCTRL_PIN(177, "L_VDDEN"),
		603	PINCTRL_PIN(178, "SYS_PWROK"),
		604	PINCTRL_PIN(179, "SYS_RESETB"),
		605	PINCTRL_PIN(180, "MLK_RSTB"),
		606	/* GPP_E */
		607	PINCTRL_PIN(181, "ISH_GP_0_IMGCLKOUT_0"),
		608	PINCTRL_PIN(182, "ISH_GP_1"),
		609	PINCTRL_PIN(183, "IMGCLKOUT_1"),
		610	PINCTRL_PIN(184, "ISH_GP_2_SATA_DEVSLP_0"),
		611	PINCTRL_PIN(185, "IMGCLKOUT_2"),
		612	PINCTRL_PIN(186, "SATA_LEDB_SPI1_CS1B"),
		613	PINCTRL_PIN(187, "IMGCLKOUT_3"),
		614	PINCTRL_PIN(188, "ISH_GP_3_SATA_DEVSLP_1"),
		615	PINCTRL_PIN(189, "FIVR_DIGPB_0"),
		616	PINCTRL_PIN(190, "SML0CLK"),
		617	PINCTRL_PIN(191, "SML0DATA"),
		618	PINCTRL_PIN(192, "BSSB_LS3_RX"),
		619	PINCTRL_PIN(193, "BSSB_LS3_TX"),
		620	PINCTRL_PIN(194, "BSSB_LS0_RX"),
		621	PINCTRL_PIN(195, "BSSB_LS0_TX"),
		622	PINCTRL_PIN(196, "BSSB_LS1_RX"),
		623	PINCTRL_PIN(197, "BSSB_LS1_TX"),
		624	PINCTRL_PIN(198, "BSSB_LS2_RX"),
		625	PINCTRL_PIN(199, "BSSB_LS2_TX"),
		626	PINCTRL_PIN(200, "FIVR_DIGPB_1"),
		627	PINCTRL_PIN(201, "CNV_BRI_DT"),
		628	PINCTRL_PIN(202, "CNV_BRI_RSP"),
		629	PINCTRL_PIN(203, "CNV_RGI_DT"),
		630	PINCTRL_PIN(204, "CNV_RGI_RSP"),
		631	/* GPP_G */
		632	PINCTRL_PIN(205, "SD3_CMD"),
		633	PINCTRL_PIN(206, "SD3_D0"),
		634	PINCTRL_PIN(207, "SD3_D1"),
		635	PINCTRL_PIN(208, "SD3_D2"),
		636	PINCTRL_PIN(209, "SD3_D3"),
		637	PINCTRL_PIN(210, "SD3_CDB"),
		638	PINCTRL_PIN(211, "SD3_CLK"),
		639	PINCTRL_PIN(212, "SD3_WP"),
		640	};
		641
		642	static const struct intel_padgroup icln_community0_gpps[] = {
		643	ICL_GPP(0, 0, 8, INTEL_GPIO_BASE_NOMAP), /* SPI */
		644	ICL_GPP(1, 9, 34, 32), /* GPP_B */
		645	ICL_GPP(2, 35, 55, 64), /* GPP_A */
		646	ICL_GPP(3, 56, 63, 96), /* GPP_S */
		647	ICL_GPP(4, 64, 71, 128), /* GPP_R */
		648	};
		649
		650	static const struct intel_padgroup icln_community1_gpps[] = {
		651	ICL_GPP(0, 72, 95, 160), /* GPP_H */
		652	ICL_GPP(1, 96, 121, 192), /* GPP_D */
		653	ICL_GPP(2, 122, 150, 224), /* vGPIO */
		654	ICL_GPP(3, 151, 174, 256), /* GPP_C */
		655	};
		656
		657	static const struct intel_padgroup icln_community4_gpps[] = {
		658	ICL_GPP(0, 175, 180, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
		659	ICL_GPP(1, 181, 204, 288), /* GPP_E */
		660	};
		661
		662	static const struct intel_padgroup icln_community5_gpps[] = {
		663	ICL_GPP(0, 205, 212, INTEL_GPIO_BASE_ZERO), /* GPP_G */
		664	};
		665
		666	static const struct intel_community icln_communities[] = {
		667	ICL_N_COMMUNITY(0, 0, 71, icln_community0_gpps),
		668	ICL_N_COMMUNITY(1, 72, 174, icln_community1_gpps),
		669	ICL_N_COMMUNITY(2, 175, 204, icln_community4_gpps),
		670	ICL_N_COMMUNITY(3, 205, 212, icln_community5_gpps),
		671	};
		672
		673	static const struct intel_pinctrl_soc_data icln_soc_data = {
		674	.pins = icln_pins,
		675	.npins = ARRAY_SIZE(icln_pins),
		676	.communities = icln_communities,
		677	.ncommunities = ARRAY_SIZE(icln_communities),
		678	};
		679
406	static INTEL_PINCTRL_PM_OPS(icl_pinctrl_pm_ops);	680	static INTEL_PINCTRL_PM_OPS(icl_pinctrl_pm_ops);
407		681
408	static const struct acpi_device_id icl_pinctrl_acpi_match[] = {	682	static const struct acpi_device_id icl_pinctrl_acpi_match[] = {
409	{ "INT3455", (kernel_ulong_t)&icllp_soc_data },	683	{ "INT3455", (kernel_ulong_t)&icllp_soc_data },
		684	{ "INT34C3", (kernel_ulong_t)&icln_soc_data },
410	{ }	685	{ }
411	};	686	};
412	MODULE_DEVICE_TABLE(acpi, icl_pinctrl_acpi_match);	687	MODULE_DEVICE_TABLE(acpi, icl_pinctrl_acpi_match);

drivers/pinctrl/mediatek/Kconfig+7−0

@@ -147,6 +147,13 @@ config PINCTRL_MT8183 · 146 unmodified lines
147	default ARM64 && ARCH_MEDIATEK	147	default ARM64 && ARCH_MEDIATEK
148	select PINCTRL_MTK_PARIS	148	select PINCTRL_MTK_PARIS
149		149
		150	config PINCTRL_MT8186
		151	bool "Mediatek MT8186 pin control"
		152	depends on OF
		153	depends on ARM64 \|\| COMPILE_TEST
		154	default ARM64 && ARCH_MEDIATEK
		155	select PINCTRL_MTK_PARIS
		156
150	config PINCTRL_MT8192	157	config PINCTRL_MT8192
151	bool "Mediatek MT8192 pin control"	158	bool "Mediatek MT8192 pin control"
152	depends on OF	159	depends on OF

drivers/pinctrl/mediatek/Makefile+1−0

@@ -21,6 +21,7 @@ obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o · 20 unmodified lines
21	obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o	21	obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o
22	obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o	22	obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
23	obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o	23	obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o
		24	obj-$(CONFIG_PINCTRL_MT8186) += pinctrl-mt8186.o
24	obj-$(CONFIG_PINCTRL_MT8192) += pinctrl-mt8192.o	25	obj-$(CONFIG_PINCTRL_MT8192) += pinctrl-mt8192.o
25	obj-$(CONFIG_PINCTRL_MT8195) += pinctrl-mt8195.o	26	obj-$(CONFIG_PINCTRL_MT8195) += pinctrl-mt8195.o
26	obj-$(CONFIG_PINCTRL_MT8365) += pinctrl-mt8365.o	27	obj-$(CONFIG_PINCTRL_MT8365) += pinctrl-mt8365.o

drivers/pinctrl/mediatek/pinctrl-moore.c+9−16

 int mtk_moore_pinctrl_probe(struct platform_device *pdev,
 			    const struct mtk_pin_soc *soc)
 {
+	struct device *dev = &pdev->dev;
 	struct pinctrl_pin_desc *pins;
 	struct mtk_pinctrl *hw;
 	int err, i;
 	hw->soc = soc;
 	hw->dev = &pdev->dev;
-	if (!hw->soc->nbase_names) {
+	if (!hw->soc->nbase_names)
-		dev_err(&pdev->dev,
+		return dev_err_probe(dev, -EINVAL,
 			"SoC should be assigned at least one register base\n");
-		return -EINVAL;
-	}
 	hw->base = devm_kmalloc_array(&pdev->dev, hw->soc->nbase_names,
 				      sizeof(*hw->base), GFP_KERNEL);
 	/* Setup groups descriptions per SoC types */
 	err = mtk_build_groups(hw);
-	if (err) {
+	if (err)
-		dev_err(&pdev->dev, "Failed to build groups\n");
+		return dev_err_probe(dev, err, "Failed to build groups\n");
-		return err;
-	}
 	/* Setup functions descriptions per SoC types */
 	err = mtk_build_functions(hw);
-	if (err) {
+	if (err)
-		dev_err(&pdev->dev, "Failed to build functions\n");
+		return dev_err_probe(dev, err, "Failed to build functions\n");
-		return err;
-	}
 	/* For able to make pinctrl_claim_hogs, we must not enable pinctrl
 	 * until all groups and functions are being added one.
 	/* Build gpiochip should be after pinctrl_enable is done */
 	err = mtk_build_gpiochip(hw);
-	if (err) {
+	if (err)
-		dev_err(&pdev->dev, "Failed to add gpio_chip\n");
+		return dev_err_probe(dev, err, "Failed to add gpio_chip\n");
-		return err;
-	}
 	platform_set_drvdata(pdev, hw);

drivers/pinctrl/mediatek/pinctrl-mt2701.c+11−29

 	MTK_PIN_PUPD_SPEC_SR(261, 0x140, 8, 9, 10),	/* ms1 ins */
 };
-static int mt2701_spec_pull_set(struct regmap *regmap, unsigned int pin,
-		unsigned char align, bool isup, unsigned int r1r0)
-{
-	return mtk_pctrl_spec_pull_set_samereg(regmap, mt2701_spec_pupd,
-		ARRAY_SIZE(mt2701_spec_pupd), pin, align, isup, r1r0);
-}
 static const struct mtk_pin_ies_smt_set mt2701_ies_set[] = {
 	MTK_PIN_IES_SMT_SPEC(0, 6, 0xb20, 0),
 	MTK_PIN_IES_SMT_SPEC(7, 9, 0xb20, 1),
 	MTK_PIN_IES_SMT_SPEC(278, 278, 0xb70, 13),
 };
-static int mt2701_ies_smt_set(struct regmap *regmap, unsigned int pin,
-		unsigned char align, int value, enum pin_config_param arg)
-{
-	if (arg == PIN_CONFIG_INPUT_ENABLE)
-		return mtk_pconf_spec_set_ies_smt_range(regmap, mt2701_ies_set,
-			ARRAY_SIZE(mt2701_ies_set), pin, align, value);
-	else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
-		return mtk_pconf_spec_set_ies_smt_range(regmap, mt2701_smt_set,
-			ARRAY_SIZE(mt2701_smt_set), pin, align, value);
-	return -EINVAL;
-}
 static const struct mtk_spec_pinmux_set mt2701_spec_pinmux[] = {
 	MTK_PINMUX_SPEC(22, 0xb10, 3),
 	MTK_PINMUX_SPEC(23, 0xb10, 4),
 	.n_grp_cls = ARRAY_SIZE(mt2701_drv_grp),
 	.pin_drv_grp = mt2701_pin_drv,
 	.n_pin_drv_grps = ARRAY_SIZE(mt2701_pin_drv),
-	.spec_pull_set = mt2701_spec_pull_set,
+	.spec_ies = mt2701_ies_set,
-	.spec_ies_smt_set = mt2701_ies_smt_set,
+	.n_spec_ies = ARRAY_SIZE(mt2701_ies_set),
+	.spec_pupd = mt2701_spec_pupd,
+	.n_spec_pupd = ARRAY_SIZE(mt2701_spec_pupd),
+	.spec_smt = mt2701_smt_set,
+	.n_spec_smt = ARRAY_SIZE(mt2701_smt_set),
+	.spec_pull_set = mtk_pctrl_spec_pull_set_samereg,
+	.spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range,
 	.spec_pinmux_set = mt2701_spec_pinmux_set,
 	.spec_dir_set = mt2701_spec_dir_set,
 	.dir_offset = 0x0000,
 	},
 };
-static int mt2701_pinctrl_probe(struct platform_device *pdev)
-{
-	return mtk_pctrl_init(pdev, &mt2701_pinctrl_data, NULL);
-}
 static const struct of_device_id mt2701_pctrl_match[] = {
-	{ .compatible = "mediatek,mt2701-pinctrl", },
+	{ .compatible = "mediatek,mt2701-pinctrl", .data = &mt2701_pinctrl_data },
-	{ .compatible = "mediatek,mt7623-pinctrl", },
+	{ .compatible = "mediatek,mt7623-pinctrl", .data = &mt2701_pinctrl_data },
 	{}
 };
 MODULE_DEVICE_TABLE(of, mt2701_pctrl_match);
 static struct platform_driver mtk_pinctrl_driver = {
-	.probe = mt2701_pinctrl_probe,
+	.probe = mtk_pctrl_common_probe,
 	.driver = {
 		.name = "mediatek-mt2701-pinctrl",
 		.of_match_table = mt2701_pctrl_match,

drivers/pinctrl/mediatek/pinctrl-mt2712.c+10−34

 	MTK_PIN_PUPD_SPEC_SR(142, 0xe60, 5, 4, 3)
 };
-static int mt2712_spec_pull_set(struct regmap *regmap,
-				unsigned int pin,
-				unsigned char align,
-				bool isup,
-				unsigned int r1r0)
-{
-	return mtk_pctrl_spec_pull_set_samereg(regmap, mt2712_spec_pupd,
-		ARRAY_SIZE(mt2712_spec_pupd), pin, align, isup, r1r0);
-}
 static const struct mtk_pin_ies_smt_set mt2712_smt_set[] = {
 	MTK_PIN_IES_SMT_SPEC(0, 3, 0x900, 2),
 	MTK_PIN_IES_SMT_SPEC(4, 7, 0x900, 0),
 	MTK_PIN_IES_SMT_SPEC(207, 209, 0x8b0, 15)
 };
-static int mt2712_ies_smt_set(struct regmap *regmap, unsigned int pin,
-			      unsigned char align,
-			      int value, enum pin_config_param arg)
-{
-	if (arg == PIN_CONFIG_INPUT_ENABLE)
-		return mtk_pconf_spec_set_ies_smt_range(regmap, mt2712_ies_set,
-			ARRAY_SIZE(mt2712_ies_set), pin, align, value);
-	if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
-		return mtk_pconf_spec_set_ies_smt_range(regmap, mt2712_smt_set,
-			ARRAY_SIZE(mt2712_smt_set), pin, align, value);
-	return -EINVAL;
-}
 static const struct mtk_drv_group_desc mt2712_drv_grp[] =  {
 	/* 0E4E8SR 4/8/12/16 */
 	MTK_DRV_GRP(4, 16, 1, 2, 4),
 	.n_grp_cls = ARRAY_SIZE(mt2712_drv_grp),
 	.pin_drv_grp = mt2712_pin_drv,
 	.n_pin_drv_grps = ARRAY_SIZE(mt2712_pin_drv),
-	.spec_pull_set = mt2712_spec_pull_set,
+	.spec_ies = mt2712_ies_set,
-	.spec_ies_smt_set = mt2712_ies_smt_set,
+	.n_spec_ies = ARRAY_SIZE(mt2712_ies_set),
+	.spec_pupd = mt2712_spec_pupd,
+	.n_spec_pupd = ARRAY_SIZE(mt2712_spec_pupd),
+	.spec_smt = mt2712_smt_set,
+	.n_spec_smt = ARRAY_SIZE(mt2712_smt_set),
+	.spec_pull_set = mtk_pctrl_spec_pull_set_samereg,
+	.spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range,
 	.dir_offset = 0x0000,
 	.pullen_offset = 0x0100,
 	.pullsel_offset = 0x0200,
 	},
 };
-static int mt2712_pinctrl_probe(struct platform_device *pdev)
-{
-	return mtk_pctrl_init(pdev, &mt2712_pinctrl_data, NULL);
-}
 static const struct of_device_id mt2712_pctrl_match[] = {
-	{
+	{ .compatible = "mediatek,mt2712-pinctrl", .data = &mt2712_pinctrl_data },
-		.compatible = "mediatek,mt2712-pinctrl",
-	},
 	{ }
 };
 MODULE_DEVICE_TABLE(of, mt2712_pctrl_match);
 static struct platform_driver mtk_pinctrl_driver = {
-	.probe = mt2712_pinctrl_probe,
+	.probe = mtk_pctrl_common_probe,
 	.driver = {
 		.name = "mediatek-mt2712-pinctrl",
 		.of_match_table = mt2712_pctrl_match,

drivers/pinctrl/mediatek/pinctrl-mt6765.c+2−7

 };
 static const struct of_device_id mt6765_pinctrl_of_match[] = {
-	{ .compatible = "mediatek,mt6765-pinctrl", },
+	{ .compatible = "mediatek,mt6765-pinctrl", .data = &mt6765_data },
 	{ }
 };
-static int mt6765_pinctrl_probe(struct platform_device *pdev)
-{
-	return mtk_paris_pinctrl_probe(pdev, &mt6765_data);
-}
 static struct platform_driver mt6765_pinctrl_driver = {
 	.driver = {
 		.name = "mt6765-pinctrl",
 		.of_match_table = mt6765_pinctrl_of_match,
 	},
-	.probe = mt6765_pinctrl_probe,
+	.probe = mtk_paris_pinctrl_probe,
 };
 static int __init mt6765_pinctrl_init(void)

drivers/pinctrl/mediatek/pinctrl-mt6779.c+2−7

 };
 static const struct of_device_id mt6779_pinctrl_of_match[] = {
-	{ .compatible = "mediatek,mt6779-pinctrl", },
+	{ .compatible = "mediatek,mt6779-pinctrl", .data = &mt6779_data },
 	{ }
 };
-static int mt6779_pinctrl_probe(struct platform_device *pdev)
-{
-	return mtk_paris_pinctrl_probe(pdev, &mt6779_data);
-}
 static struct platform_driver mt6779_pinctrl_driver = {
 	.driver = {
 		.name = "mt6779-pinctrl",
 		.of_match_table = mt6779_pinctrl_of_match,
 	},
-	.probe = mt6779_pinctrl_probe,
+	.probe = mtk_paris_pinctrl_probe,
 };
 static int __init mt6779_pinctrl_init(void)

drivers/pinctrl/mediatek/pinctrl-mt6797.c+2−7

 };
 static const struct of_device_id mt6797_pinctrl_of_match[] = {
-	{ .compatible = "mediatek,mt6797-pinctrl", },
+	{ .compatible = "mediatek,mt6797-pinctrl", .data = &mt6797_data },
 	{ }
 };
-static int mt6797_pinctrl_probe(struct platform_device *pdev)
-{
-	return mtk_paris_pinctrl_probe(pdev, &mt6797_data);
-}
 static struct platform_driver mt6797_pinctrl_driver = {
 	.driver = {
 		.name = "mt6797-pinctrl",
 		.of_match_table = mt6797_pinctrl_of_match,
 	},
-	.probe = mt6797_pinctrl_probe,
+	.probe = mtk_paris_pinctrl_probe,
 };
 static int __init mt6797_pinctrl_init(void)

drivers/pinctrl/mediatek/pinctrl-mt8127.c+10−29

 	MTK_PIN_PUPD_SPEC_SR(142, 0xdc0, 2, 0, 1),	/* EINT21 */
 };
-static int mt8127_spec_pull_set(struct regmap *regmap, unsigned int pin,
-		unsigned char align, bool isup, unsigned int r1r0)
-{
-	return mtk_pctrl_spec_pull_set_samereg(regmap, mt8127_spec_pupd,
-		ARRAY_SIZE(mt8127_spec_pupd), pin, align, isup, r1r0);
-}
 static const struct mtk_pin_ies_smt_set mt8127_ies_set[] = {
 	MTK_PIN_IES_SMT_SPEC(0, 9, 0x900, 0),
 	MTK_PIN_IES_SMT_SPEC(10, 13, 0x900, 1),
 	MTK_PIN_IES_SMT_SPEC(142, 142, 0x920, 13),
 };
-static int mt8127_ies_smt_set(struct regmap *regmap, unsigned int pin,
-		unsigned char align, int value, enum pin_config_param arg)
-{
-	if (arg == PIN_CONFIG_INPUT_ENABLE)
-		return mtk_pconf_spec_set_ies_smt_range(regmap, mt8127_ies_set,
-			ARRAY_SIZE(mt8127_ies_set), pin, align, value);
-	else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
-		return mtk_pconf_spec_set_ies_smt_range(regmap, mt8127_smt_set,
-			ARRAY_SIZE(mt8127_smt_set), pin, align, value);
-	return -EINVAL;
-}
 static const struct mtk_pinctrl_devdata mt8127_pinctrl_data = {
 	.pins = mtk_pins_mt8127,
 	.npins = ARRAY_SIZE(mtk_pins_mt8127),
 	.n_grp_cls = ARRAY_SIZE(mt8127_drv_grp),
 	.pin_drv_grp = mt8127_pin_drv,
 	.n_pin_drv_grps = ARRAY_SIZE(mt8127_pin_drv),
-	.spec_pull_set = mt8127_spec_pull_set,
+	.spec_ies = mt8127_ies_set,
-	.spec_ies_smt_set = mt8127_ies_smt_set,
+	.n_spec_ies = ARRAY_SIZE(mt8127_ies_set),
+	.spec_pupd = mt8127_spec_pupd,
+	.n_spec_pupd = ARRAY_SIZE(mt8127_spec_pupd),
+	.spec_smt = mt8127_smt_set,
+	.n_spec_smt = ARRAY_SIZE(mt8127_smt_set),
+	.spec_pull_set = mtk_pctrl_spec_pull_set_samereg,
+	.spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range,
 	.dir_offset = 0x0000,
 	.pullen_offset = 0x0100,
 	.pullsel_offset = 0x0200,
 	},
 };
-static int mt8127_pinctrl_probe(struct platform_device *pdev)
-{
-	return mtk_pctrl_init(pdev, &mt8127_pinctrl_data, NULL);
-}
 static const struct of_device_id mt8127_pctrl_match[] = {
-	{ .compatible = "mediatek,mt8127-pinctrl", },
+	{ .compatible = "mediatek,mt8127-pinctrl", .data = &mt8127_pinctrl_data },
 	{ }
 };
 static struct platform_driver mtk_pinctrl_driver = {
-	.probe = mt8127_pinctrl_probe,
+	.probe = mtk_pctrl_common_probe,
 	.driver = {
 		.name = "mediatek-mt8127-pinctrl",
 		.of_match_table = mt8127_pctrl_match,

drivers/pinctrl/mediatek/pinctrl-mt8135.c+6−11

 	SPEC_PULL(202, PUPD_BASE2+0xc0, 10, R0_BASE1, 12, R1_BASE2+0xc0, 10)
 };
-static int spec_pull_set(struct regmap *regmap, unsigned int pin,
+static int spec_pull_set(struct regmap *regmap,
-		unsigned char align, bool isup, unsigned int r1r0)
+		const struct mtk_pinctrl_devdata *devdata,
+		unsigned int pin, bool isup, unsigned int r1r0)
 {
 	unsigned int i;
 	unsigned int reg_pupd, reg_set_r0, reg_set_r1;
 	unsigned int reg_rst_r0, reg_rst_r1;
+	unsigned char align = devdata->port_align;
 	bool find = false;
 	for (i = 0; i < ARRAY_SIZE(spec_pupd); i++) {
 	},
 };
-static int mt8135_pinctrl_probe(struct platform_device *pdev)
-{
-	return mtk_pctrl_init(pdev, &mt8135_pinctrl_data, NULL);
-}
 static const struct of_device_id mt8135_pctrl_match[] = {
-	{
+	{ .compatible = "mediatek,mt8135-pinctrl", .data = &mt8135_pinctrl_data },
-		.compatible = "mediatek,mt8135-pinctrl",
-	},
 	{ }
 };
 static struct platform_driver mtk_pinctrl_driver = {
-	.probe = mt8135_pinctrl_probe,
+	.probe = mtk_pctrl_common_probe,
 	.driver = {
 		.name = "mediatek-mt8135-pinctrl",
 		.of_match_table = mt8135_pctrl_match,

drivers/pinctrl/mediatek/pinctrl-mt8167.c+10−30

 	MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 2, 1, 0),
 };
-static int mt8167_spec_pull_set(struct regmap *regmap, unsigned int pin,
-			unsigned char align, bool isup, unsigned int r1r0)
-{
-	return mtk_pctrl_spec_pull_set_samereg(regmap, mt8167_spec_pupd,
-		ARRAY_SIZE(mt8167_spec_pupd), pin, align, isup, r1r0);
-}
 static const struct mtk_pin_ies_smt_set mt8167_ies_set[] = {
 	MTK_PIN_IES_SMT_SPEC(0, 6, 0x900, 2),
 	MTK_PIN_IES_SMT_SPEC(7, 10, 0x900, 3),
 	MTK_PIN_IES_SMT_SPEC(121, 124, 0xA10, 9),
 };
-static int mt8167_ies_smt_set(struct regmap *regmap, unsigned int pin,
-		unsigned char align, int value, enum pin_config_param arg)
-{
-	if (arg == PIN_CONFIG_INPUT_ENABLE)
-		return mtk_pconf_spec_set_ies_smt_range(regmap, mt8167_ies_set,
-			ARRAY_SIZE(mt8167_ies_set), pin, align, value);
-	else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
-		return mtk_pconf_spec_set_ies_smt_range(regmap, mt8167_smt_set,
-			ARRAY_SIZE(mt8167_smt_set), pin, align, value);
-	return -EINVAL;
-}
 static const struct mtk_pinctrl_devdata mt8167_pinctrl_data = {
 	.pins = mtk_pins_mt8167,
 	.npins = ARRAY_SIZE(mtk_pins_mt8167),
 	.n_grp_cls = ARRAY_SIZE(mt8167_drv_grp),
 	.pin_drv_grp = mt8167_pin_drv,
 	.n_pin_drv_grps = ARRAY_SIZE(mt8167_pin_drv),
-	.spec_pull_set = mt8167_spec_pull_set,
+	.spec_ies = mt8167_ies_set,
-	.spec_ies_smt_set = mt8167_ies_smt_set,
+	.n_spec_ies = ARRAY_SIZE(mt8167_ies_set),
+	.spec_pupd = mt8167_spec_pupd,
+	.n_spec_pupd = ARRAY_SIZE(mt8167_spec_pupd),
+	.spec_smt = mt8167_smt_set,
+	.n_spec_smt = ARRAY_SIZE(mt8167_smt_set),
+	.spec_pull_set = mtk_pctrl_spec_pull_set_samereg,
+	.spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range,
 	.dir_offset = 0x0000,
 	.pullen_offset = 0x0500,
 	.pullsel_offset = 0x0600,
 	},
 };
-static int mt8167_pinctrl_probe(struct platform_device *pdev)
-{
-	return mtk_pctrl_init(pdev, &mt8167_pinctrl_data, NULL);
-}
 static const struct of_device_id mt8167_pctrl_match[] = {
-	{
+	{ .compatible = "mediatek,mt8167-pinctrl", .data = &mt8167_pinctrl_data },
-		.compatible = "mediatek,mt8167-pinctrl",
-	},
 	{}
 };
 MODULE_DEVICE_TABLE(of, mt8167_pctrl_match);
 static struct platform_driver mtk_pinctrl_driver = {
-	.probe = mt8167_pinctrl_probe,
+	.probe = mtk_pctrl_common_probe,
 	.driver = {
 		.name = "mediatek-mt8167-pinctrl",
 		.of_match_table = mt8167_pctrl_match,

drivers/pinctrl/mediatek/pinctrl-mt8173.c+8−21

 	MTK_PIN_PUPD_SPEC_SR(27, 0xcd0, 2, 1, 0)     /* ms3 cmd */
 };
-static int mt8173_spec_pull_set(struct regmap *regmap, unsigned int pin,
-		unsigned char align, bool isup, unsigned int r1r0)
-{
-	return mtk_pctrl_spec_pull_set_samereg(regmap, mt8173_spec_pupd,
-		ARRAY_SIZE(mt8173_spec_pupd), pin, align, isup, r1r0);
-}
 static const struct mtk_pin_ies_smt_set mt8173_smt_set[] = {
 	MTK_PIN_IES_SMT_SPEC(0, 4, 0x930, 1),
 	MTK_PIN_IES_SMT_SPEC(5, 9, 0x930, 2),
 	MTK_PIN_IES_SMT_SPEC(133, 134, 0x910, 8)
 };
-static int mt8173_ies_smt_set(struct regmap *regmap, unsigned int pin,
-		unsigned char align, int value, enum pin_config_param arg)
-{
-	if (arg == PIN_CONFIG_INPUT_ENABLE)
-		return mtk_pconf_spec_set_ies_smt_range(regmap, mt8173_ies_set,
-			ARRAY_SIZE(mt8173_ies_set), pin, align, value);
-	else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
-		return mtk_pconf_spec_set_ies_smt_range(regmap, mt8173_smt_set,
-			ARRAY_SIZE(mt8173_smt_set), pin, align, value);
-	return -EINVAL;
-}
 static const struct mtk_drv_group_desc mt8173_drv_grp[] =  {
 	/* 0E4E8SR 4/8/12/16 */
 	MTK_DRV_GRP(4, 16, 1, 2, 4),
 	.n_grp_cls = ARRAY_SIZE(mt8173_drv_grp),
 	.pin_drv_grp = mt8173_pin_drv,
 	.n_pin_drv_grps = ARRAY_SIZE(mt8173_pin_drv),
-	.spec_pull_set = mt8173_spec_pull_set,
+	.spec_ies = mt8173_ies_set,
-	.spec_ies_smt_set = mt8173_ies_smt_set,
+	.n_spec_ies = ARRAY_SIZE(mt8173_ies_set),
+	.spec_pupd = mt8173_spec_pupd,
+	.n_spec_pupd = ARRAY_SIZE(mt8173_spec_pupd),
+	.spec_smt = mt8173_smt_set,
+	.n_spec_smt = ARRAY_SIZE(mt8173_smt_set),
+	.spec_pull_set = mtk_pctrl_spec_pull_set_samereg,
+	.spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range,
 	.dir_offset = 0x0000,
 	.pullen_offset = 0x0100,
 	.pullsel_offset = 0x0200,

drivers/pinctrl/mediatek/pinctrl-mt8183.c+2−7

 };
 static const struct of_device_id mt8183_pinctrl_of_match[] = {
-	{ .compatible = "mediatek,mt8183-pinctrl", },
+	{ .compatible = "mediatek,mt8183-pinctrl", .data = &mt8183_data },
 	{ }
 };
-static int mt8183_pinctrl_probe(struct platform_device *pdev)
-{
-	return mtk_paris_pinctrl_probe(pdev, &mt8183_data);
-}
 static struct platform_driver mt8183_pinctrl_driver = {
 	.driver = {
 		.name = "mt8183-pinctrl",
 		.of_match_table = mt8183_pinctrl_of_match,
 		.pm = &mtk_paris_pinctrl_pm_ops,
 	},
-	.probe = mt8183_pinctrl_probe,
+	.probe = mtk_paris_pinctrl_probe,
 };
 static int __init mt8183_pinctrl_init(void)

drivers/pinctrl/mediatek/pinctrl-mt8186.c+1267−0

@@ -0,0 +1,1267 @@
	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright (C) 2021 MediaTek Inc.
	4	*
	5	* Author: Guodong Liu <guodong.liu@mediatek.com>
	6	*
	7	*/
	8
	9	#include "pinctrl-mtk-mt8186.h"
	10	#include "pinctrl-paris.h"
	11
	12	/* MT8186 have multiple bases to program pin configuration listed as the below:
	13	* iocfg[0]:0x10005000, iocfg[1]:0x10002000, iocfg[2]:0x10002200,
	14	* iocfg[3]:0x10002400, iocfg[4]:0x10002600, iocfg[5]:0x10002800,
	15	* iocfg[6]:0x10002C00.
	16	* _i_based could be used to indicate what base the pin should be mapped into.
	17	*/
	18
	19	#define PIN_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \
	20	PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, 32, 0)
	21
	22	#define PINS_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \
	23	PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, 32, 1)
	24
	25	static const struct mtk_pin_field_calc mt8186_pin_mode_range[] = {
	26	PIN_FIELD(0, 184, 0x300, 0x10, 0, 4),
	27	};
	28
	29	static const struct mtk_pin_field_calc mt8186_pin_dir_range[] = {
	30	PIN_FIELD(0, 184, 0x0, 0x10, 0, 1),
	31	};
	32
	33	static const struct mtk_pin_field_calc mt8186_pin_di_range[] = {
	34	PIN_FIELD(0, 184, 0x200, 0x10, 0, 1),
	35	};
	36
	37	static const struct mtk_pin_field_calc mt8186_pin_do_range[] = {
	38	PIN_FIELD(0, 184, 0x100, 0x10, 0, 1),
	39	};
	40
	41	static const struct mtk_pin_field_calc mt8186_pin_ies_range[] = {
	42	PIN_FIELD_BASE(0, 0, 6, 0x0030, 0x10, 13, 1),
	43	PIN_FIELD_BASE(1, 1, 6, 0x0030, 0x10, 14, 1),
	44	PIN_FIELD_BASE(2, 2, 6, 0x0030, 0x10, 17, 1),
	45	PIN_FIELD_BASE(3, 3, 6, 0x0030, 0x10, 18, 1),
	46	PIN_FIELD_BASE(4, 4, 6, 0x0030, 0x10, 19, 1),
	47	PIN_FIELD_BASE(5, 5, 6, 0x0030, 0x10, 20, 1),
	48	PIN_FIELD_BASE(6, 6, 4, 0x0020, 0x10, 19, 1),
	49	PIN_FIELD_BASE(7, 7, 4, 0x0020, 0x10, 20, 1),
	50	PIN_FIELD_BASE(8, 8, 4, 0x0020, 0x10, 21, 1),
	51	PIN_FIELD_BASE(9, 9, 4, 0x0020, 0x10, 22, 1),
	52	PIN_FIELD_BASE(10, 10, 4, 0x0020, 0x10, 16, 1),
	53	PIN_FIELD_BASE(11, 11, 4, 0x0020, 0x10, 17, 1),
	54	PIN_FIELD_BASE(12, 12, 4, 0x0020, 0x10, 18, 1),
	55	PIN_FIELD_BASE(13, 13, 3, 0x0040, 0x10, 0, 1),
	56	PIN_FIELD_BASE(14, 14, 3, 0x0040, 0x10, 1, 1),
	57	PIN_FIELD_BASE(15, 15, 6, 0x0030, 0x10, 15, 1),
	58	PIN_FIELD_BASE(16, 16, 6, 0x0030, 0x10, 16, 1),
	59	PIN_FIELD_BASE(17, 17, 5, 0x0050, 0x10, 9, 1),
	60	PIN_FIELD_BASE(18, 18, 5, 0x0050, 0x10, 10, 1),
	61	PIN_FIELD_BASE(19, 19, 5, 0x0050, 0x10, 3, 1),
	62	PIN_FIELD_BASE(20, 20, 5, 0x0050, 0x10, 6, 1),
	63	PIN_FIELD_BASE(21, 21, 5, 0x0050, 0x10, 4, 1),
	64	PIN_FIELD_BASE(22, 22, 5, 0x0050, 0x10, 7, 1),
	65	PIN_FIELD_BASE(23, 23, 5, 0x0050, 0x10, 5, 1),
	66	PIN_FIELD_BASE(24, 24, 5, 0x0050, 0x10, 8, 1),
	67	PIN_FIELD_BASE(25, 25, 5, 0x0050, 0x10, 18, 1),
	68	PIN_FIELD_BASE(26, 26, 5, 0x0050, 0x10, 15, 1),
	69	PIN_FIELD_BASE(27, 27, 5, 0x0050, 0x10, 17, 1),
	70	PIN_FIELD_BASE(28, 28, 5, 0x0050, 0x10, 16, 1),
	71	PIN_FIELD_BASE(29, 29, 6, 0x0030, 0x10, 0, 1),
	72	PIN_FIELD_BASE(30, 30, 6, 0x0030, 0x10, 1, 1),
	73	PIN_FIELD_BASE(31, 31, 6, 0x0030, 0x10, 2, 1),
	74	PIN_FIELD_BASE(32, 32, 2, 0x0040, 0x10, 25, 1),
	75	PIN_FIELD_BASE(33, 33, 2, 0x0040, 0x10, 27, 1),
	76	PIN_FIELD_BASE(34, 34, 2, 0x0040, 0x10, 26, 1),
	77	PIN_FIELD_BASE(35, 35, 2, 0x0040, 0x10, 28, 1),
	78	PIN_FIELD_BASE(36, 36, 2, 0x0040, 0x10, 9, 1),
	79	PIN_FIELD_BASE(37, 37, 2, 0x0040, 0x10, 10, 1),
	80	PIN_FIELD_BASE(38, 38, 2, 0x0040, 0x10, 12, 1),
	81	PIN_FIELD_BASE(39, 39, 2, 0x0040, 0x10, 11, 1),
	82	PIN_FIELD_BASE(40, 40, 2, 0x0040, 0x10, 13, 1),
	83	PIN_FIELD_BASE(41, 41, 2, 0x0040, 0x10, 14, 1),
	84	PIN_FIELD_BASE(42, 42, 2, 0x0040, 0x10, 16, 1),
	85	PIN_FIELD_BASE(43, 43, 2, 0x0040, 0x10, 15, 1),
	86	PIN_FIELD_BASE(44, 44, 5, 0x0060, 0x10, 0, 1),
	87	PIN_FIELD_BASE(45, 45, 5, 0x0060, 0x10, 1, 1),
	88	PIN_FIELD_BASE(46, 46, 5, 0x0060, 0x10, 3, 1),
	89	PIN_FIELD_BASE(47, 47, 5, 0x0060, 0x10, 2, 1),
	90	PIN_FIELD_BASE(48, 48, 2, 0x0040, 0x10, 17, 1),
	91	PIN_FIELD_BASE(49, 49, 2, 0x0040, 0x10, 18, 1),
	92	PIN_FIELD_BASE(50, 50, 2, 0x0040, 0x10, 20, 1),
	93	PIN_FIELD_BASE(51, 51, 2, 0x0040, 0x10, 19, 1),
	94	PIN_FIELD_BASE(52, 52, 3, 0x0040, 0x10, 18, 1),
	95	PIN_FIELD_BASE(53, 53, 3, 0x0040, 0x10, 19, 1),
	96	PIN_FIELD_BASE(54, 54, 3, 0x0040, 0x10, 21, 1),
	97	PIN_FIELD_BASE(55, 55, 3, 0x0040, 0x10, 20, 1),
	98	PIN_FIELD_BASE(56, 56, 5, 0x0050, 0x10, 12, 1),
	99	PIN_FIELD_BASE(57, 57, 5, 0x0050, 0x10, 11, 1),
	100	PIN_FIELD_BASE(58, 58, 5, 0x0050, 0x10, 13, 1),
	101	PIN_FIELD_BASE(59, 59, 5, 0x0050, 0x10, 14, 1),
	102	PIN_FIELD_BASE(60, 60, 3, 0x0040, 0x10, 27, 1),
	103	PIN_FIELD_BASE(61, 61, 3, 0x0040, 0x10, 22, 1),
	104	PIN_FIELD_BASE(62, 62, 3, 0x0040, 0x10, 28, 1),
	105	PIN_FIELD_BASE(63, 63, 3, 0x0040, 0x10, 23, 1),
	106	PIN_FIELD_BASE(64, 64, 3, 0x0040, 0x10, 24, 1),
	107	PIN_FIELD_BASE(65, 65, 3, 0x0040, 0x10, 25, 1),
	108	PIN_FIELD_BASE(66, 66, 3, 0x0040, 0x10, 26, 1),
	109	PIN_FIELD_BASE(67, 67, 1, 0x0050, 0x10, 18, 1),
	110	PIN_FIELD_BASE(68, 68, 1, 0x0050, 0x10, 8, 1),
	111	PIN_FIELD_BASE(69, 69, 1, 0x0050, 0x10, 9, 1),
	112	PIN_FIELD_BASE(70, 70, 1, 0x0050, 0x10, 19, 1),
	113	PIN_FIELD_BASE(71, 71, 1, 0x0050, 0x10, 10, 1),
	114	PIN_FIELD_BASE(72, 72, 1, 0x0050, 0x10, 11, 1),
	115	PIN_FIELD_BASE(73, 73, 1, 0x0050, 0x10, 12, 1),
	116	PIN_FIELD_BASE(74, 74, 1, 0x0050, 0x10, 13, 1),
	117	PIN_FIELD_BASE(75, 75, 1, 0x0050, 0x10, 14, 1),
	118	PIN_FIELD_BASE(76, 76, 1, 0x0050, 0x10, 15, 1),
	119	PIN_FIELD_BASE(77, 77, 1, 0x0050, 0x10, 16, 1),
	120	PIN_FIELD_BASE(78, 78, 1, 0x0050, 0x10, 17, 1),
	121	PIN_FIELD_BASE(79, 79, 5, 0x0050, 0x10, 24, 1),
	122	PIN_FIELD_BASE(80, 80, 5, 0x0050, 0x10, 25, 1),
	123	PIN_FIELD_BASE(81, 81, 5, 0x0050, 0x10, 26, 1),
	124	PIN_FIELD_BASE(82, 82, 5, 0x0050, 0x10, 27, 1),
	125	PIN_FIELD_BASE(83, 83, 6, 0x0030, 0x10, 3, 1),
	126	PIN_FIELD_BASE(84, 84, 3, 0x0040, 0x10, 4, 1),
	127	PIN_FIELD_BASE(85, 85, 3, 0x0040, 0x10, 5, 1),
	128	PIN_FIELD_BASE(86, 86, 3, 0x0040, 0x10, 6, 1),
	129	PIN_FIELD_BASE(87, 87, 3, 0x0040, 0x10, 7, 1),
	130	PIN_FIELD_BASE(88, 88, 3, 0x0040, 0x10, 8, 1),
	131	PIN_FIELD_BASE(89, 89, 3, 0x0040, 0x10, 9, 1),
	132	PIN_FIELD_BASE(90, 90, 3, 0x0040, 0x10, 2, 1),
	133	PIN_FIELD_BASE(91, 91, 3, 0x0040, 0x10, 29, 1),
	134	PIN_FIELD_BASE(92, 92, 3, 0x0040, 0x10, 31, 1),
	135	PIN_FIELD_BASE(93, 93, 3, 0x0040, 0x10, 3, 1),
	136	PIN_FIELD_BASE(94, 94, 3, 0x0040, 0x10, 30, 1),
	137	PIN_FIELD_BASE(95, 95, 3, 0x0050, 0x10, 0, 1),
	138	PIN_FIELD_BASE(96, 96, 2, 0x0040, 0x10, 1, 1),
	139	PIN_FIELD_BASE(97, 97, 2, 0x0040, 0x10, 0, 1),
	140	PIN_FIELD_BASE(98, 98, 2, 0x0040, 0x10, 2, 1),
	141	PIN_FIELD_BASE(99, 99, 4, 0x0020, 0x10, 14, 1),
	142	PIN_FIELD_BASE(100, 100, 4, 0x0020, 0x10, 15, 1),
	143	PIN_FIELD_BASE(101, 101, 4, 0x0020, 0x10, 13, 1),
	144	PIN_FIELD_BASE(102, 102, 4, 0x0020, 0x10, 12, 1),
	145	PIN_FIELD_BASE(103, 103, 4, 0x0020, 0x10, 0, 1),
	146	PIN_FIELD_BASE(104, 104, 4, 0x0020, 0x10, 1, 1),
	147	PIN_FIELD_BASE(105, 105, 4, 0x0020, 0x10, 4, 1),
	148	PIN_FIELD_BASE(106, 106, 4, 0x0020, 0x10, 5, 1),
	149	PIN_FIELD_BASE(107, 107, 4, 0x0020, 0x10, 6, 1),
	150	PIN_FIELD_BASE(108, 108, 4, 0x0020, 0x10, 7, 1),
	151	PIN_FIELD_BASE(109, 109, 4, 0x0020, 0x10, 8, 1),
	152	PIN_FIELD_BASE(110, 110, 4, 0x0020, 0x10, 9, 1),
	153	PIN_FIELD_BASE(111, 111, 4, 0x0020, 0x10, 10, 1),
	154	PIN_FIELD_BASE(112, 112, 4, 0x0020, 0x10, 11, 1),
	155	PIN_FIELD_BASE(113, 113, 4, 0x0020, 0x10, 2, 1),
	156	PIN_FIELD_BASE(114, 114, 4, 0x0020, 0x10, 3, 1),
	157	PIN_FIELD_BASE(115, 115, 3, 0x0040, 0x10, 10, 1),
	158	PIN_FIELD_BASE(116, 116, 3, 0x0040, 0x10, 13, 1),
	159	PIN_FIELD_BASE(117, 117, 3, 0x0040, 0x10, 11, 1),
	160	PIN_FIELD_BASE(118, 118, 3, 0x0040, 0x10, 12, 1),
	161	PIN_FIELD_BASE(119, 119, 5, 0x0050, 0x10, 22, 1),
	162	PIN_FIELD_BASE(120, 120, 5, 0x0050, 0x10, 19, 1),
	163	PIN_FIELD_BASE(121, 121, 5, 0x0050, 0x10, 20, 1),
	164	PIN_FIELD_BASE(122, 122, 5, 0x0050, 0x10, 21, 1),
	165	PIN_FIELD_BASE(123, 123, 5, 0x0050, 0x10, 23, 1),
	166	PIN_FIELD_BASE(124, 124, 5, 0x0050, 0x10, 0, 1),
	167	PIN_FIELD_BASE(125, 125, 5, 0x0050, 0x10, 1, 1),
	168	PIN_FIELD_BASE(126, 126, 5, 0x0050, 0x10, 2, 1),
	169	PIN_FIELD_BASE(127, 127, 3, 0x0040, 0x10, 14, 1),
	170	PIN_FIELD_BASE(128, 128, 3, 0x0040, 0x10, 16, 1),
	171	PIN_FIELD_BASE(129, 129, 5, 0x0050, 0x10, 28, 1),
	172	PIN_FIELD_BASE(130, 130, 5, 0x0050, 0x10, 30, 1),
	173	PIN_FIELD_BASE(131, 131, 5, 0x0050, 0x10, 29, 1),
	174	PIN_FIELD_BASE(132, 132, 5, 0x0050, 0x10, 31, 1),
	175	PIN_FIELD_BASE(133, 133, 1, 0x0050, 0x10, 21, 1),
	176	PIN_FIELD_BASE(134, 134, 1, 0x0050, 0x10, 24, 1),
	177	PIN_FIELD_BASE(135, 135, 6, 0x0030, 0x10, 21, 1),
	178	PIN_FIELD_BASE(136, 136, 6, 0x0030, 0x10, 24, 1),
	179	PIN_FIELD_BASE(137, 137, 1, 0x0050, 0x10, 22, 1),
	180	PIN_FIELD_BASE(138, 138, 1, 0x0050, 0x10, 25, 1),
	181	PIN_FIELD_BASE(139, 139, 2, 0x0040, 0x10, 7, 1),
	182	PIN_FIELD_BASE(140, 140, 2, 0x0040, 0x10, 8, 1),
	183	PIN_FIELD_BASE(141, 141, 3, 0x0040, 0x10, 15, 1),
	184	PIN_FIELD_BASE(142, 142, 3, 0x0040, 0x10, 17, 1),
	185	PIN_FIELD_BASE(143, 143, 6, 0x0030, 0x10, 22, 1),
	186	PIN_FIELD_BASE(144, 144, 6, 0x0030, 0x10, 25, 1),
	187	PIN_FIELD_BASE(145, 145, 6, 0x0030, 0x10, 23, 1),
	188	PIN_FIELD_BASE(146, 146, 6, 0x0030, 0x10, 26, 1),
	189	PIN_FIELD_BASE(147, 147, 4, 0x0020, 0x10, 23, 1),
	190	PIN_FIELD_BASE(148, 148, 4, 0x0020, 0x10, 24, 1),
	191	PIN_FIELD_BASE(149, 149, 4, 0x0020, 0x10, 25, 1),
	192	PIN_FIELD_BASE(150, 150, 4, 0x0020, 0x10, 26, 1),
	193	PIN_FIELD_BASE(151, 151, 4, 0x0020, 0x10, 27, 1),
	194	PIN_FIELD_BASE(152, 152, 4, 0x0020, 0x10, 28, 1),
	195	PIN_FIELD_BASE(153, 153, 4, 0x0020, 0x10, 29, 1),
	196	PIN_FIELD_BASE(154, 154, 4, 0x0020, 0x10, 30, 1),
	197	PIN_FIELD_BASE(155, 155, 4, 0x0020, 0x10, 31, 1),
	198	PIN_FIELD_BASE(156, 156, 4, 0x0030, 0x10, 0, 1),
	199	PIN_FIELD_BASE(157, 157, 2, 0x0040, 0x10, 4, 1),
	200	PIN_FIELD_BASE(158, 158, 2, 0x0040, 0x10, 3, 1),
	201	PIN_FIELD_BASE(159, 159, 2, 0x0040, 0x10, 6, 1),
	202	PIN_FIELD_BASE(160, 160, 2, 0x0040, 0x10, 5, 1),
	203	PIN_FIELD_BASE(161, 161, 2, 0x0040, 0x10, 23, 1),
	204	PIN_FIELD_BASE(162, 162, 2, 0x0040, 0x10, 24, 1),
	205	PIN_FIELD_BASE(163, 163, 1, 0x0050, 0x10, 23, 1),
	206	PIN_FIELD_BASE(164, 164, 1, 0x0050, 0x10, 20, 1),
	207	PIN_FIELD_BASE(165, 165, 1, 0x0050, 0x10, 26, 1),
	208	PIN_FIELD_BASE(166, 166, 1, 0x0050, 0x10, 1, 1),
	209	PIN_FIELD_BASE(167, 167, 1, 0x0050, 0x10, 7, 1),
	210	PIN_FIELD_BASE(168, 168, 1, 0x0050, 0x10, 4, 1),
	211	PIN_FIELD_BASE(169, 169, 1, 0x0050, 0x10, 5, 1),
	212	PIN_FIELD_BASE(170, 170, 1, 0x0050, 0x10, 0, 1),
	213	PIN_FIELD_BASE(171, 171, 1, 0x0050, 0x10, 6, 1),
	214	PIN_FIELD_BASE(172, 172, 1, 0x0050, 0x10, 2, 1),
	215	PIN_FIELD_BASE(173, 173, 1, 0x0050, 0x10, 3, 1),
	216	PIN_FIELD_BASE(174, 174, 6, 0x0030, 0x10, 7, 1),
	217	PIN_FIELD_BASE(175, 175, 6, 0x0030, 0x10, 8, 1),
	218	PIN_FIELD_BASE(176, 176, 6, 0x0030, 0x10, 4, 1),
	219	PIN_FIELD_BASE(177, 177, 6, 0x0030, 0x10, 5, 1),
	220	PIN_FIELD_BASE(178, 178, 6, 0x0030, 0x10, 6, 1),
	221	PIN_FIELD_BASE(179, 179, 6, 0x0030, 0x10, 9, 1),
	222	PIN_FIELD_BASE(180, 180, 6, 0x0030, 0x10, 10, 1),
	223	PIN_FIELD_BASE(181, 181, 6, 0x0030, 0x10, 11, 1),
	224	PIN_FIELD_BASE(182, 182, 6, 0x0030, 0x10, 12, 1),
	225	PIN_FIELD_BASE(183, 183, 2, 0x0040, 0x10, 21, 1),
	226	PIN_FIELD_BASE(184, 184, 2, 0x0040, 0x10, 22, 1),
	227	};
	228
	229	static const struct mtk_pin_field_calc mt8186_pin_smt_range[] = {
	230	PIN_FIELD_BASE(0, 0, 6, 0x0080, 0x10, 0, 1),
	231	PIN_FIELD_BASE(1, 1, 6, 0x0080, 0x10, 0, 1),
	232	PIN_FIELD_BASE(2, 2, 6, 0x0080, 0x10, 0, 1),
	233	PIN_FIELD_BASE(3, 3, 6, 0x0080, 0x10, 0, 1),
	234	PIN_FIELD_BASE(4, 4, 6, 0x0080, 0x10, 1, 1),
	235	PIN_FIELD_BASE(5, 5, 6, 0x0080, 0x10, 1, 1),
	236	PIN_FIELD_BASE(6, 6, 4, 0x0090, 0x10, 0, 1),
	237	PIN_FIELD_BASE(7, 7, 4, 0x0090, 0x10, 1, 1),
	238	PIN_FIELD_BASE(8, 8, 4, 0x0090, 0x10, 1, 1),
	239	PIN_FIELD_BASE(9, 9, 4, 0x0090, 0x10, 1, 1),
	240	PIN_FIELD_BASE(10, 10, 4, 0x0090, 0x10, 0, 1),
	241	PIN_FIELD_BASE(11, 11, 4, 0x0090, 0x10, 0, 1),
	242	PIN_FIELD_BASE(12, 12, 4, 0x0090, 0x10, 0, 1),
	243	PIN_FIELD_BASE(13, 13, 3, 0x00e0, 0x10, 11, 1),
	244	PIN_FIELD_BASE(14, 14, 3, 0x00e0, 0x10, 11, 1),
	245	PIN_FIELD_BASE(15, 15, 6, 0x0080, 0x10, 2, 1),
	246	PIN_FIELD_BASE(16, 16, 6, 0x0080, 0x10, 2, 1),
	247	PIN_FIELD_BASE(17, 17, 5, 0x00e0, 0x10, 3, 1),
	248	PIN_FIELD_BASE(18, 18, 5, 0x00e0, 0x10, 7, 1),
	249	PIN_FIELD_BASE(19, 19, 5, 0x00e0, 0x10, 6, 1),
	250	PIN_FIELD_BASE(20, 20, 5, 0x00e0, 0x10, 5, 1),
	251	PIN_FIELD_BASE(21, 21, 5, 0x00e0, 0x10, 6, 1),
	252	PIN_FIELD_BASE(22, 22, 5, 0x00e0, 0x10, 5, 1),
	253	PIN_FIELD_BASE(23, 23, 5, 0x00e0, 0x10, 7, 1),
	254	PIN_FIELD_BASE(24, 24, 5, 0x00e0, 0x10, 10, 1),
	255	PIN_FIELD_BASE(25, 25, 5, 0x00e0, 0x10, 7, 1),
	256	PIN_FIELD_BASE(26, 26, 5, 0x00e0, 0x10, 6, 1),
	257	PIN_FIELD_BASE(27, 27, 5, 0x00e0, 0x10, 6, 1),
	258	PIN_FIELD_BASE(28, 28, 5, 0x00e0, 0x10, 7, 1),
	259	PIN_FIELD_BASE(29, 29, 6, 0x0080, 0x10, 1, 1),
	260	PIN_FIELD_BASE(30, 30, 6, 0x0080, 0x10, 1, 1),
	261	PIN_FIELD_BASE(31, 31, 6, 0x0080, 0x10, 2, 1),
	262	PIN_FIELD_BASE(32, 32, 2, 0x0090, 0x10, 2, 1),
	263	PIN_FIELD_BASE(33, 33, 2, 0x0090, 0x10, 2, 1),
	264	PIN_FIELD_BASE(34, 34, 2, 0x0090, 0x10, 1, 1),
	265	PIN_FIELD_BASE(35, 35, 2, 0x0090, 0x10, 1, 1),
	266	PIN_FIELD_BASE(36, 36, 2, 0x0090, 0x10, 3, 1),
	267	PIN_FIELD_BASE(37, 37, 2, 0x0090, 0x10, 3, 1),
	268	PIN_FIELD_BASE(38, 38, 2, 0x0090, 0x10, 4, 1),
	269	PIN_FIELD_BASE(39, 39, 2, 0x0090, 0x10, 3, 1),
	270	PIN_FIELD_BASE(40, 40, 2, 0x0090, 0x10, 5, 1),
	271	PIN_FIELD_BASE(41, 41, 2, 0x0090, 0x10, 4, 1),
	272	PIN_FIELD_BASE(42, 42, 2, 0x0090, 0x10, 4, 1),
	273	PIN_FIELD_BASE(43, 43, 2, 0x0090, 0x10, 4, 1),
	274	PIN_FIELD_BASE(44, 44, 5, 0x00e0, 0x10, 9, 1),
	275	PIN_FIELD_BASE(45, 45, 5, 0x00e0, 0x10, 8, 1),
	276	PIN_FIELD_BASE(46, 46, 5, 0x00e0, 0x10, 8, 1),
	277	PIN_FIELD_BASE(47, 47, 5, 0x00e0, 0x10, 9, 1),
	278	PIN_FIELD_BASE(48, 48, 2, 0x0090, 0x10, 5, 1),
	279	PIN_FIELD_BASE(49, 49, 2, 0x0090, 0x10, 5, 1),
	280	PIN_FIELD_BASE(50, 50, 2, 0x0090, 0x10, 5, 1),
	281	PIN_FIELD_BASE(51, 51, 2, 0x0090, 0x10, 6, 1),
	282	PIN_FIELD_BASE(52, 52, 3, 0x00e0, 0x10, 9, 1),
	283	PIN_FIELD_BASE(53, 53, 3, 0x00e0, 0x10, 10, 1),
	284	PIN_FIELD_BASE(54, 54, 3, 0x00e0, 0x10, 9, 1),
	285	PIN_FIELD_BASE(55, 55, 3, 0x00e0, 0x10, 9, 1),
	286	PIN_FIELD_BASE(56, 56, 5, 0x00e0, 0x10, 8, 1),
	287	PIN_FIELD_BASE(57, 57, 5, 0x00e0, 0x10, 9, 1),
	288	PIN_FIELD_BASE(58, 58, 5, 0x00e0, 0x10, 9, 1),
	289	PIN_FIELD_BASE(59, 59, 5, 0x00e0, 0x10, 8, 1),
	290	PIN_FIELD_BASE(60, 60, 3, 0x00e0, 0x10, 6, 1),
	291	PIN_FIELD_BASE(61, 61, 3, 0x00e0, 0x10, 6, 1),
	292	PIN_FIELD_BASE(62, 62, 3, 0x00e0, 0x10, 6, 1),
	293	PIN_FIELD_BASE(63, 63, 3, 0x00e0, 0x10, 6, 1),
	294	PIN_FIELD_BASE(64, 64, 3, 0x00e0, 0x10, 7, 1),
	295	PIN_FIELD_BASE(65, 65, 3, 0x00e0, 0x10, 7, 1),
	296	PIN_FIELD_BASE(66, 66, 3, 0x00e0, 0x10, 7, 1),
	297	PIN_FIELD_BASE(67, 67, 1, 0x00f0, 0x10, 10, 1),
	298	PIN_FIELD_BASE(68, 68, 1, 0x00f0, 0x10, 0, 1),
	299	PIN_FIELD_BASE(69, 69, 1, 0x00f0, 0x10, 1, 1),
	300	PIN_FIELD_BASE(70, 70, 1, 0x00f0, 0x10, 11, 1),
	301	PIN_FIELD_BASE(71, 71, 1, 0x00f0, 0x10, 2, 1),
	302	PIN_FIELD_BASE(72, 72, 1, 0x00f0, 0x10, 3, 1),
	303	PIN_FIELD_BASE(73, 73, 1, 0x00f0, 0x10, 4, 1),
	304	PIN_FIELD_BASE(74, 74, 1, 0x00f0, 0x10, 5, 1),
	305	PIN_FIELD_BASE(75, 75, 1, 0x00f0, 0x10, 6, 1),
	306	PIN_FIELD_BASE(76, 76, 1, 0x00f0, 0x10, 7, 1),
	307	PIN_FIELD_BASE(77, 77, 1, 0x00f0, 0x10, 8, 1),
	308	PIN_FIELD_BASE(78, 78, 1, 0x00f0, 0x10, 9, 1),
	309	PIN_FIELD_BASE(79, 79, 5, 0x00e0, 0x10, 5, 1),
	310	PIN_FIELD_BASE(80, 80, 5, 0x00e0, 0x10, 5, 1),
	311	PIN_FIELD_BASE(81, 81, 5, 0x00e0, 0x10, 4, 1),
	312	PIN_FIELD_BASE(82, 82, 5, 0x00e0, 0x10, 4, 1),
	313	PIN_FIELD_BASE(83, 83, 6, 0x0080, 0x10, 2, 1),
	314	PIN_FIELD_BASE(84, 84, 3, 0x00e0, 0x10, 0, 1),
	315	PIN_FIELD_BASE(85, 85, 3, 0x00e0, 0x10, 1, 1),
	316	PIN_FIELD_BASE(86, 86, 3, 0x00e0, 0x10, 2, 1),
	317	PIN_FIELD_BASE(87, 87, 3, 0x00e0, 0x10, 3, 1),
	318	PIN_FIELD_BASE(88, 88, 3, 0x00e0, 0x10, 4, 1),
	319	PIN_FIELD_BASE(89, 89, 3, 0x00e0, 0x10, 5, 1),
	320	PIN_FIELD_BASE(90, 90, 3, 0x00e0, 0x10, 7, 1),
	321	PIN_FIELD_BASE(91, 91, 3, 0x00e0, 0x10, 8, 1),
	322	PIN_FIELD_BASE(92, 92, 3, 0x00e0, 0x10, 8, 1),
	323	PIN_FIELD_BASE(93, 93, 3, 0x00e0, 0x10, 8, 1),
	324	PIN_FIELD_BASE(94, 94, 3, 0x00e0, 0x10, 8, 1),
	325	PIN_FIELD_BASE(95, 95, 3, 0x00e0, 0x10, 9, 1),
	326	PIN_FIELD_BASE(96, 96, 2, 0x0090, 0x10, 3, 1),
	327	PIN_FIELD_BASE(97, 97, 2, 0x0090, 0x10, 2, 1),
	328	PIN_FIELD_BASE(98, 98, 2, 0x0090, 0x10, 1, 1),
	329	PIN_FIELD_BASE(99, 99, 4, 0x0090, 0x10, 4, 1),
	330	PIN_FIELD_BASE(100, 100, 4, 0x0090, 0x10, 4, 1),
	331	PIN_FIELD_BASE(101, 101, 4, 0x0090, 0x10, 4, 1),
	332	PIN_FIELD_BASE(102, 102, 4, 0x0090, 0x10, 5, 1),
	333	PIN_FIELD_BASE(103, 103, 4, 0x0090, 0x10, 5, 1),
	334	PIN_FIELD_BASE(104, 104, 4, 0x0090, 0x10, 5, 1),
	335	PIN_FIELD_BASE(105, 105, 4, 0x0090, 0x10, 5, 1),
	336	PIN_FIELD_BASE(106, 106, 4, 0x0090, 0x10, 6, 1),
	337	PIN_FIELD_BASE(107, 107, 4, 0x0090, 0x10, 6, 1),
	338	PIN_FIELD_BASE(108, 108, 4, 0x0090, 0x10, 6, 1),
	339	PIN_FIELD_BASE(109, 109, 4, 0x0090, 0x10, 6, 1),
	340	PIN_FIELD_BASE(110, 110, 4, 0x0090, 0x10, 7, 1),
	341	PIN_FIELD_BASE(111, 111, 4, 0x0090, 0x10, 7, 1),
	342	PIN_FIELD_BASE(112, 112, 4, 0x0090, 0x10, 7, 1),
	343	PIN_FIELD_BASE(113, 113, 4, 0x0090, 0x10, 7, 1),
	344	PIN_FIELD_BASE(114, 114, 4, 0x0090, 0x10, 8, 1),
	345	PIN_FIELD_BASE(115, 115, 3, 0x00e0, 0x10, 10, 1),
	346	PIN_FIELD_BASE(116, 116, 3, 0x00e0, 0x10, 11, 1),
	347	PIN_FIELD_BASE(117, 117, 3, 0x00e0, 0x10, 10, 1),
	348	PIN_FIELD_BASE(118, 118, 3, 0x00e0, 0x10, 10, 1),
	349	PIN_FIELD_BASE(119, 119, 5, 0x00e0, 0x10, 4, 1),
	350	PIN_FIELD_BASE(120, 120, 5, 0x00e0, 0x10, 4, 1),
	351	PIN_FIELD_BASE(121, 121, 5, 0x00e0, 0x10, 3, 1),
	352	PIN_FIELD_BASE(122, 122, 5, 0x00e0, 0x10, 3, 1),
	353	PIN_FIELD_BASE(123, 123, 5, 0x00e0, 0x10, 3, 1),
	354	PIN_FIELD_BASE(124, 124, 5, 0x00e0, 0x10, 0, 1),
	355	PIN_FIELD_BASE(125, 125, 5, 0x00e0, 0x10, 1, 1),
	356	PIN_FIELD_BASE(126, 126, 5, 0x00e0, 0x10, 2, 1),
	357	PIN_FIELD_BASE(127, 127, 3, 0x00e0, 0x10, 12, 1),
	358	PIN_FIELD_BASE(128, 128, 3, 0x00e0, 0x10, 14, 1),
	359	PIN_FIELD_BASE(129, 129, 5, 0x00e0, 0x10, 11, 1),
	360	PIN_FIELD_BASE(130, 130, 5, 0x00e0, 0x10, 13, 1),
	361	PIN_FIELD_BASE(131, 131, 5, 0x00e0, 0x10, 12, 1),
	362	PIN_FIELD_BASE(132, 132, 5, 0x00e0, 0x10, 14, 1),
	363	PIN_FIELD_BASE(133, 133, 1, 0x00f0, 0x10, 15, 1),
	364	PIN_FIELD_BASE(134, 134, 1, 0x00f0, 0x10, 17, 1),
	365	PIN_FIELD_BASE(135, 135, 6, 0x0080, 0x10, 6, 1),
	366	PIN_FIELD_BASE(136, 136, 6, 0x0080, 0x10, 9, 1),
	367	PIN_FIELD_BASE(137, 137, 1, 0x00f0, 0x10, 16, 1),
	368	PIN_FIELD_BASE(138, 138, 1, 0x00f0, 0x10, 18, 1),
	369	PIN_FIELD_BASE(139, 139, 2, 0x0090, 0x10, 7, 1),
	370	PIN_FIELD_BASE(140, 140, 2, 0x0090, 0x10, 8, 1),
	371	PIN_FIELD_BASE(141, 141, 3, 0x00e0, 0x10, 13, 1),
	372	PIN_FIELD_BASE(142, 142, 3, 0x00e0, 0x10, 15, 1),
	373	PIN_FIELD_BASE(143, 143, 6, 0x0080, 0x10, 7, 1),
	374	PIN_FIELD_BASE(144, 144, 6, 0x0080, 0x10, 10, 1),
	375	PIN_FIELD_BASE(145, 145, 6, 0x0080, 0x10, 8, 1),
	376	PIN_FIELD_BASE(146, 146, 6, 0x0080, 0x10, 11, 1),
	377	PIN_FIELD_BASE(147, 147, 4, 0x0090, 0x10, 2, 1),
	378	PIN_FIELD_BASE(148, 148, 4, 0x0090, 0x10, 2, 1),
	379	PIN_FIELD_BASE(149, 149, 4, 0x0090, 0x10, 2, 1),
	380	PIN_FIELD_BASE(150, 150, 4, 0x0090, 0x10, 2, 1),
	381	PIN_FIELD_BASE(151, 151, 4, 0x0090, 0x10, 3, 1),
	382	PIN_FIELD_BASE(152, 152, 4, 0x0090, 0x10, 1, 1),
	383	PIN_FIELD_BASE(153, 153, 4, 0x0090, 0x10, 3, 1),
	384	PIN_FIELD_BASE(154, 154, 4, 0x0090, 0x10, 3, 1),
	385	PIN_FIELD_BASE(155, 155, 4, 0x0090, 0x10, 3, 1),
	386	PIN_FIELD_BASE(156, 156, 4, 0x0090, 0x10, 4, 1),
	387	PIN_FIELD_BASE(157, 157, 2, 0x0090, 0x10, 0, 1),
	388	PIN_FIELD_BASE(158, 158, 2, 0x0090, 0x10, 0, 1),
	389	PIN_FIELD_BASE(159, 159, 2, 0x0090, 0x10, 0, 1),
	390	PIN_FIELD_BASE(160, 160, 2, 0x0090, 0x10, 0, 1),
	391	PIN_FIELD_BASE(161, 161, 2, 0x0090, 0x10, 2, 1),
	392	PIN_FIELD_BASE(162, 162, 2, 0x0090, 0x10, 1, 1),
	393	PIN_FIELD_BASE(163, 163, 1, 0x00f0, 0x10, 14, 1),
	394	PIN_FIELD_BASE(164, 164, 1, 0x00f0, 0x10, 12, 1),
	395	PIN_FIELD_BASE(165, 165, 1, 0x00f0, 0x10, 12, 1),
	396	PIN_FIELD_BASE(166, 166, 1, 0x00f0, 0x10, 13, 1),
	397	PIN_FIELD_BASE(167, 167, 1, 0x00f0, 0x10, 13, 1),
	398	PIN_FIELD_BASE(168, 168, 1, 0x00f0, 0x10, 12, 1),
	399	PIN_FIELD_BASE(169, 169, 1, 0x00f0, 0x10, 14, 1),
	400	PIN_FIELD_BASE(170, 170, 1, 0x00f0, 0x10, 13, 1),
	401	PIN_FIELD_BASE(171, 171, 1, 0x00f0, 0x10, 13, 1),
	402	PIN_FIELD_BASE(172, 172, 1, 0x00f0, 0x10, 14, 1),
	403	PIN_FIELD_BASE(173, 173, 1, 0x00f0, 0x10, 12, 1),
	404	PIN_FIELD_BASE(174, 174, 6, 0x0080, 0x10, 3, 1),
	405	PIN_FIELD_BASE(175, 175, 6, 0x0080, 0x10, 3, 1),
	406	PIN_FIELD_BASE(176, 176, 6, 0x0080, 0x10, 4, 1),
	407	PIN_FIELD_BASE(177, 177, 6, 0x0080, 0x10, 4, 1),
	408	PIN_FIELD_BASE(178, 178, 6, 0x0080, 0x10, 3, 1),
	409	PIN_FIELD_BASE(179, 179, 6, 0x0080, 0x10, 3, 1),
	410	PIN_FIELD_BASE(180, 180, 6, 0x0080, 0x10, 4, 1),
	411	PIN_FIELD_BASE(181, 181, 6, 0x0080, 0x10, 4, 1),
	412	PIN_FIELD_BASE(182, 182, 6, 0x0080, 0x10, 5, 1),
	413	PIN_FIELD_BASE(183, 183, 2, 0x0090, 0x10, 9, 1),
	414	PIN_FIELD_BASE(184, 184, 2, 0x0090, 0x10, 10, 1),
	415	};
	416
	417	static const struct mtk_pin_field_calc mt8186_pin_pu_range[] = {
	418	PIN_FIELD_BASE(0, 0, 6, 0x0050, 0x10, 13, 1),
	419	PIN_FIELD_BASE(1, 1, 6, 0x0050, 0x10, 14, 1),
	420	PIN_FIELD_BASE(2, 2, 6, 0x0050, 0x10, 17, 1),
	421	PIN_FIELD_BASE(3, 3, 6, 0x0050, 0x10, 18, 1),
	422	PIN_FIELD_BASE(4, 4, 6, 0x0050, 0x10, 19, 1),
	423	PIN_FIELD_BASE(5, 5, 6, 0x0050, 0x10, 20, 1),
	424	PIN_FIELD_BASE(6, 6, 4, 0x0060, 0x10, 19, 1),
	425	PIN_FIELD_BASE(7, 7, 4, 0x0060, 0x10, 20, 1),
	426	PIN_FIELD_BASE(8, 8, 4, 0x0060, 0x10, 21, 1),
	427	PIN_FIELD_BASE(9, 9, 4, 0x0060, 0x10, 22, 1),
	428	PIN_FIELD_BASE(10, 10, 4, 0x0060, 0x10, 16, 1),
	429	PIN_FIELD_BASE(11, 11, 4, 0x0060, 0x10, 17, 1),
	430	PIN_FIELD_BASE(12, 12, 4, 0x0060, 0x10, 18, 1),
	431	PIN_FIELD_BASE(13, 13, 3, 0x0080, 0x10, 0, 1),
	432	PIN_FIELD_BASE(14, 14, 3, 0x0080, 0x10, 1, 1),
	433	PIN_FIELD_BASE(15, 15, 6, 0x0050, 0x10, 15, 1),
	434	PIN_FIELD_BASE(16, 16, 6, 0x0050, 0x10, 16, 1),
	435	PIN_FIELD_BASE(17, 17, 5, 0x0090, 0x10, 9, 1),
	436	PIN_FIELD_BASE(18, 18, 5, 0x0090, 0x10, 10, 1),
	437	PIN_FIELD_BASE(19, 19, 5, 0x0090, 0x10, 3, 1),
	438	PIN_FIELD_BASE(20, 20, 5, 0x0090, 0x10, 6, 1),
	439	PIN_FIELD_BASE(21, 21, 5, 0x0090, 0x10, 4, 1),
	440	PIN_FIELD_BASE(22, 22, 5, 0x0090, 0x10, 7, 1),
	441	PIN_FIELD_BASE(23, 23, 5, 0x0090, 0x10, 5, 1),
	442	PIN_FIELD_BASE(24, 24, 5, 0x0090, 0x10, 8, 1),
	443	PIN_FIELD_BASE(25, 25, 5, 0x0090, 0x10, 18, 1),
	444	PIN_FIELD_BASE(26, 26, 5, 0x0090, 0x10, 15, 1),
	445	PIN_FIELD_BASE(27, 27, 5, 0x0090, 0x10, 17, 1),
	446	PIN_FIELD_BASE(28, 28, 5, 0x0090, 0x10, 16, 1),
	447	PIN_FIELD_BASE(29, 29, 6, 0x0050, 0x10, 0, 1),
	448	PIN_FIELD_BASE(30, 30, 6, 0x0050, 0x10, 1, 1),
	449	PIN_FIELD_BASE(31, 31, 6, 0x0050, 0x10, 2, 1),
	450	PIN_FIELD_BASE(32, 32, 2, 0x0060, 0x10, 25, 1),
	451	PIN_FIELD_BASE(33, 33, 2, 0x0060, 0x10, 27, 1),
	452	PIN_FIELD_BASE(34, 34, 2, 0x0060, 0x10, 26, 1),
	453	PIN_FIELD_BASE(35, 35, 2, 0x0060, 0x10, 28, 1),
	454	PIN_FIELD_BASE(36, 36, 2, 0x0060, 0x10, 9, 1),
	455	PIN_FIELD_BASE(37, 37, 2, 0x0060, 0x10, 10, 1),
	456	PIN_FIELD_BASE(38, 38, 2, 0x0060, 0x10, 12, 1),
	457	PIN_FIELD_BASE(39, 39, 2, 0x0060, 0x10, 11, 1),
	458	PIN_FIELD_BASE(40, 40, 2, 0x0060, 0x10, 13, 1),
	459	PIN_FIELD_BASE(41, 41, 2, 0x0060, 0x10, 14, 1),
	460	PIN_FIELD_BASE(42, 42, 2, 0x0060, 0x10, 16, 1),
	461	PIN_FIELD_BASE(43, 43, 2, 0x0060, 0x10, 15, 1),
	462	PIN_FIELD_BASE(44, 44, 5, 0x0090, 0x10, 28, 1),
	463	PIN_FIELD_BASE(45, 45, 5, 0x0090, 0x10, 29, 1),
	464	PIN_FIELD_BASE(46, 46, 5, 0x0090, 0x10, 31, 1),
	465	PIN_FIELD_BASE(47, 47, 5, 0x0090, 0x10, 30, 1),
	466	PIN_FIELD_BASE(48, 48, 2, 0x0060, 0x10, 17, 1),
	467	PIN_FIELD_BASE(49, 49, 2, 0x0060, 0x10, 18, 1),
	468	PIN_FIELD_BASE(50, 50, 2, 0x0060, 0x10, 20, 1),
	469	PIN_FIELD_BASE(51, 51, 2, 0x0060, 0x10, 19, 1),
	470	PIN_FIELD_BASE(52, 52, 3, 0x0080, 0x10, 12, 1),
	471	PIN_FIELD_BASE(53, 53, 3, 0x0080, 0x10, 13, 1),
	472	PIN_FIELD_BASE(54, 54, 3, 0x0080, 0x10, 15, 1),
	473	PIN_FIELD_BASE(55, 55, 3, 0x0080, 0x10, 14, 1),
	474	PIN_FIELD_BASE(56, 56, 5, 0x0090, 0x10, 12, 1),
	475	PIN_FIELD_BASE(57, 57, 5, 0x0090, 0x10, 11, 1),
	476	PIN_FIELD_BASE(58, 58, 5, 0x0090, 0x10, 13, 1),
	477	PIN_FIELD_BASE(59, 59, 5, 0x0090, 0x10, 14, 1),
	478	PIN_FIELD_BASE(60, 60, 3, 0x0080, 0x10, 21, 1),
	479	PIN_FIELD_BASE(61, 61, 3, 0x0080, 0x10, 16, 1),
	480	PIN_FIELD_BASE(62, 62, 3, 0x0080, 0x10, 22, 1),
	481	PIN_FIELD_BASE(63, 63, 3, 0x0080, 0x10, 17, 1),
	482	PIN_FIELD_BASE(64, 64, 3, 0x0080, 0x10, 18, 1),
	483	PIN_FIELD_BASE(65, 65, 3, 0x0080, 0x10, 19, 1),
	484	PIN_FIELD_BASE(66, 66, 3, 0x0080, 0x10, 20, 1),
	485	PIN_FIELD_BASE(83, 83, 6, 0x0050, 0x10, 3, 1),
	486	PIN_FIELD_BASE(90, 90, 3, 0x0080, 0x10, 2, 1),
	487	PIN_FIELD_BASE(91, 91, 3, 0x0080, 0x10, 23, 1),
	488	PIN_FIELD_BASE(92, 92, 3, 0x0080, 0x10, 25, 1),
	489	PIN_FIELD_BASE(93, 93, 3, 0x0080, 0x10, 3, 1),
	490	PIN_FIELD_BASE(94, 94, 3, 0x0080, 0x10, 24, 1),
	491	PIN_FIELD_BASE(95, 95, 3, 0x0080, 0x10, 26, 1),
	492	PIN_FIELD_BASE(96, 96, 2, 0x0060, 0x10, 1, 1),
	493	PIN_FIELD_BASE(97, 97, 2, 0x0060, 0x10, 0, 1),
	494	PIN_FIELD_BASE(98, 98, 2, 0x0060, 0x10, 2, 1),
	495	PIN_FIELD_BASE(99, 99, 4, 0x0060, 0x10, 14, 1),
	496	PIN_FIELD_BASE(100, 100, 4, 0x0060, 0x10, 15, 1),
	497	PIN_FIELD_BASE(101, 101, 4, 0x0060, 0x10, 13, 1),
	498	PIN_FIELD_BASE(102, 102, 4, 0x0060, 0x10, 12, 1),
	499	PIN_FIELD_BASE(103, 103, 4, 0x0060, 0x10, 0, 1),
	500	PIN_FIELD_BASE(104, 104, 4, 0x0060, 0x10, 1, 1),
	501	PIN_FIELD_BASE(105, 105, 4, 0x0060, 0x10, 4, 1),
	502	PIN_FIELD_BASE(106, 106, 4, 0x0060, 0x10, 5, 1),
	503	PIN_FIELD_BASE(107, 107, 4, 0x0060, 0x10, 6, 1),
	504	PIN_FIELD_BASE(108, 108, 4, 0x0060, 0x10, 7, 1),
	505	PIN_FIELD_BASE(109, 109, 4, 0x0060, 0x10, 8, 1),
	506	PIN_FIELD_BASE(110, 110, 4, 0x0060, 0x10, 9, 1),
	507	PIN_FIELD_BASE(111, 111, 4, 0x0060, 0x10, 10, 1),
	508	PIN_FIELD_BASE(112, 112, 4, 0x0060, 0x10, 11, 1),
	509	PIN_FIELD_BASE(113, 113, 4, 0x0060, 0x10, 2, 1),
	510	PIN_FIELD_BASE(114, 114, 4, 0x0060, 0x10, 3, 1),
	511	PIN_FIELD_BASE(115, 115, 3, 0x0080, 0x10, 4, 1),
	512	PIN_FIELD_BASE(116, 116, 3, 0x0080, 0x10, 7, 1),
	513	PIN_FIELD_BASE(117, 117, 3, 0x0080, 0x10, 5, 1),
	514	PIN_FIELD_BASE(118, 118, 3, 0x0080, 0x10, 6, 1),
	515	PIN_FIELD_BASE(119, 119, 5, 0x0090, 0x10, 22, 1),
	516	PIN_FIELD_BASE(120, 120, 5, 0x0090, 0x10, 19, 1),
	517	PIN_FIELD_BASE(121, 121, 5, 0x0090, 0x10, 20, 1),
	518	PIN_FIELD_BASE(122, 122, 5, 0x0090, 0x10, 21, 1),
	519	PIN_FIELD_BASE(123, 123, 5, 0x0090, 0x10, 23, 1),
	520	PIN_FIELD_BASE(124, 124, 5, 0x0090, 0x10, 0, 1),
	521	PIN_FIELD_BASE(125, 125, 5, 0x0090, 0x10, 1, 1),
	522	PIN_FIELD_BASE(126, 126, 5, 0x0090, 0x10, 2, 1),
	523	PIN_FIELD_BASE(127, 127, 3, 0x0080, 0x10, 8, 1),
	524	PIN_FIELD_BASE(128, 128, 3, 0x0080, 0x10, 10, 1),
	525	PIN_FIELD_BASE(129, 129, 5, 0x0090, 0x10, 24, 1),
	526	PIN_FIELD_BASE(130, 130, 5, 0x0090, 0x10, 26, 1),
	527	PIN_FIELD_BASE(131, 131, 5, 0x0090, 0x10, 25, 1),
	528	PIN_FIELD_BASE(132, 132, 5, 0x0090, 0x10, 27, 1),
	529	PIN_FIELD_BASE(133, 133, 1, 0x0080, 0x10, 9, 1),
	530	PIN_FIELD_BASE(134, 134, 1, 0x0080, 0x10, 12, 1),
	531	PIN_FIELD_BASE(135, 135, 6, 0x0050, 0x10, 21, 1),
	532	PIN_FIELD_BASE(136, 136, 6, 0x0050, 0x10, 24, 1),
	533	PIN_FIELD_BASE(137, 137, 1, 0x0080, 0x10, 10, 1),
	534	PIN_FIELD_BASE(138, 138, 1, 0x0080, 0x10, 13, 1),
	535	PIN_FIELD_BASE(139, 139, 2, 0x0060, 0x10, 7, 1),
	536	PIN_FIELD_BASE(140, 140, 2, 0x0060, 0x10, 8, 1),
	537	PIN_FIELD_BASE(141, 141, 3, 0x0080, 0x10, 9, 1),
	538	PIN_FIELD_BASE(142, 142, 3, 0x0080, 0x10, 11, 1),
	539	PIN_FIELD_BASE(143, 143, 6, 0x0050, 0x10, 22, 1),
	540	PIN_FIELD_BASE(144, 144, 6, 0x0050, 0x10, 25, 1),
	541	PIN_FIELD_BASE(145, 145, 6, 0x0050, 0x10, 23, 1),
	542	PIN_FIELD_BASE(146, 146, 6, 0x0050, 0x10, 26, 1),
	543	PIN_FIELD_BASE(147, 147, 4, 0x0060, 0x10, 23, 1),
	544	PIN_FIELD_BASE(148, 148, 4, 0x0060, 0x10, 24, 1),
	545	PIN_FIELD_BASE(149, 149, 4, 0x0060, 0x10, 25, 1),
	546	PIN_FIELD_BASE(150, 150, 4, 0x0060, 0x10, 26, 1),
	547	PIN_FIELD_BASE(151, 151, 4, 0x0060, 0x10, 27, 1),
	548	PIN_FIELD_BASE(152, 152, 4, 0x0060, 0x10, 28, 1),
	549	PIN_FIELD_BASE(153, 153, 4, 0x0060, 0x10, 29, 1),
	550	PIN_FIELD_BASE(154, 154, 4, 0x0060, 0x10, 30, 1),
	551	PIN_FIELD_BASE(155, 155, 4, 0x0060, 0x10, 31, 1),
	552	PIN_FIELD_BASE(156, 156, 4, 0x0070, 0x10, 0, 1),
	553	PIN_FIELD_BASE(157, 157, 2, 0x0060, 0x10, 4, 1),
	554	PIN_FIELD_BASE(158, 158, 2, 0x0060, 0x10, 3, 1),
	555	PIN_FIELD_BASE(159, 159, 2, 0x0060, 0x10, 6, 1),
	556	PIN_FIELD_BASE(160, 160, 2, 0x0060, 0x10, 5, 1),
	557	PIN_FIELD_BASE(161, 161, 2, 0x0060, 0x10, 23, 1),
	558	PIN_FIELD_BASE(162, 162, 2, 0x0060, 0x10, 24, 1),
	559	PIN_FIELD_BASE(163, 163, 1, 0x0080, 0x10, 11, 1),
	560	PIN_FIELD_BASE(164, 164, 1, 0x0080, 0x10, 8, 1),
	561	PIN_FIELD_BASE(165, 165, 1, 0x0080, 0x10, 16, 1),
	562	PIN_FIELD_BASE(166, 166, 1, 0x0080, 0x10, 1, 1),
	563	PIN_FIELD_BASE(167, 167, 1, 0x0080, 0x10, 7, 1),
	564	PIN_FIELD_BASE(168, 168, 1, 0x0080, 0x10, 4, 1),
	565	PIN_FIELD_BASE(169, 169, 1, 0x0080, 0x10, 5, 1),
	566	PIN_FIELD_BASE(170, 170, 1, 0x0080, 0x10, 0, 1),
	567	PIN_FIELD_BASE(171, 171, 1, 0x0080, 0x10, 6, 1),
	568	PIN_FIELD_BASE(172, 172, 1, 0x0080, 0x10, 2, 1),
	569	PIN_FIELD_BASE(173, 173, 1, 0x0080, 0x10, 3, 1),
	570	PIN_FIELD_BASE(174, 174, 6, 0x0050, 0x10, 7, 1),
	571	PIN_FIELD_BASE(175, 175, 6, 0x0050, 0x10, 8, 1),
	572	PIN_FIELD_BASE(176, 176, 6, 0x0050, 0x10, 4, 1),
	573	PIN_FIELD_BASE(177, 177, 6, 0x0050, 0x10, 5, 1),
	574	PIN_FIELD_BASE(178, 178, 6, 0x0050, 0x10, 6, 1),
	575	PIN_FIELD_BASE(179, 179, 6, 0x0050, 0x10, 9, 1),
	576	PIN_FIELD_BASE(180, 180, 6, 0x0050, 0x10, 10, 1),
	577	PIN_FIELD_BASE(181, 181, 6, 0x0050, 0x10, 11, 1),
	578	PIN_FIELD_BASE(182, 182, 6, 0x0050, 0x10, 12, 1),
	579	PIN_FIELD_BASE(183, 183, 2, 0x0060, 0x10, 21, 1),
	580	PIN_FIELD_BASE(184, 184, 2, 0x0060, 0x10, 22, 1),
	581	};
	582
	583	static const struct mtk_pin_field_calc mt8186_pin_pd_range[] = {
	584	PIN_FIELD_BASE(0, 0, 6, 0x0040, 0x10, 13, 1),
	585	PIN_FIELD_BASE(1, 1, 6, 0x0040, 0x10, 14, 1),
	586	PIN_FIELD_BASE(2, 2, 6, 0x0040, 0x10, 17, 1),
	587	PIN_FIELD_BASE(3, 3, 6, 0x0040, 0x10, 18, 1),
	588	PIN_FIELD_BASE(4, 4, 6, 0x0040, 0x10, 19, 1),
	589	PIN_FIELD_BASE(5, 5, 6, 0x0040, 0x10, 20, 1),
	590	PIN_FIELD_BASE(6, 6, 4, 0x0040, 0x10, 19, 1),
	591	PIN_FIELD_BASE(7, 7, 4, 0x0040, 0x10, 20, 1),
	592	PIN_FIELD_BASE(8, 8, 4, 0x0040, 0x10, 21, 1),
	593	PIN_FIELD_BASE(9, 9, 4, 0x0040, 0x10, 22, 1),
	594	PIN_FIELD_BASE(10, 10, 4, 0x0040, 0x10, 16, 1),
	595	PIN_FIELD_BASE(11, 11, 4, 0x0040, 0x10, 17, 1),
	596	PIN_FIELD_BASE(12, 12, 4, 0x0040, 0x10, 18, 1),
	597	PIN_FIELD_BASE(13, 13, 3, 0x0060, 0x10, 0, 1),
	598	PIN_FIELD_BASE(14, 14, 3, 0x0060, 0x10, 1, 1),
	599	PIN_FIELD_BASE(15, 15, 6, 0x0040, 0x10, 15, 1),
	600	PIN_FIELD_BASE(16, 16, 6, 0x0040, 0x10, 16, 1),
	601	PIN_FIELD_BASE(17, 17, 5, 0x0070, 0x10, 9, 1),
	602	PIN_FIELD_BASE(18, 18, 5, 0x0070, 0x10, 10, 1),
	603	PIN_FIELD_BASE(19, 19, 5, 0x0070, 0x10, 3, 1),
	604	PIN_FIELD_BASE(20, 20, 5, 0x0070, 0x10, 6, 1),
	605	PIN_FIELD_BASE(21, 21, 5, 0x0070, 0x10, 4, 1),
	606	PIN_FIELD_BASE(22, 22, 5, 0x0070, 0x10, 7, 1),
	607	PIN_FIELD_BASE(23, 23, 5, 0x0070, 0x10, 5, 1),
	608	PIN_FIELD_BASE(24, 24, 5, 0x0070, 0x10, 8, 1),
	609	PIN_FIELD_BASE(25, 25, 5, 0x0070, 0x10, 18, 1),
	610	PIN_FIELD_BASE(26, 26, 5, 0x0070, 0x10, 15, 1),
	611	PIN_FIELD_BASE(27, 27, 5, 0x0070, 0x10, 17, 1),
	612	PIN_FIELD_BASE(28, 28, 5, 0x0070, 0x10, 16, 1),
	613	PIN_FIELD_BASE(29, 29, 6, 0x0040, 0x10, 0, 1),
	614	PIN_FIELD_BASE(30, 30, 6, 0x0040, 0x10, 1, 1),
	615	PIN_FIELD_BASE(31, 31, 6, 0x0040, 0x10, 2, 1),
	616	PIN_FIELD_BASE(32, 32, 2, 0x0050, 0x10, 25, 1),
	617	PIN_FIELD_BASE(33, 33, 2, 0x0050, 0x10, 27, 1),
	618	PIN_FIELD_BASE(34, 34, 2, 0x0050, 0x10, 26, 1),
	619	PIN_FIELD_BASE(35, 35, 2, 0x0050, 0x10, 28, 1),
	620	PIN_FIELD_BASE(36, 36, 2, 0x0050, 0x10, 9, 1),
	621	PIN_FIELD_BASE(37, 37, 2, 0x0050, 0x10, 10, 1),
	622	PIN_FIELD_BASE(38, 38, 2, 0x0050, 0x10, 12, 1),
	623	PIN_FIELD_BASE(39, 39, 2, 0x0050, 0x10, 11, 1),
	624	PIN_FIELD_BASE(40, 40, 2, 0x0050, 0x10, 13, 1),
	625	PIN_FIELD_BASE(41, 41, 2, 0x0050, 0x10, 14, 1),
	626	PIN_FIELD_BASE(42, 42, 2, 0x0050, 0x10, 16, 1),
	627	PIN_FIELD_BASE(43, 43, 2, 0x0050, 0x10, 15, 1),
	628	PIN_FIELD_BASE(44, 44, 5, 0x0070, 0x10, 28, 1),
	629	PIN_FIELD_BASE(45, 45, 5, 0x0070, 0x10, 29, 1),
	630	PIN_FIELD_BASE(46, 46, 5, 0x0070, 0x10, 31, 1),
	631	PIN_FIELD_BASE(47, 47, 5, 0x0070, 0x10, 30, 1),
	632	PIN_FIELD_BASE(48, 48, 2, 0x0050, 0x10, 17, 1),
	633	PIN_FIELD_BASE(49, 49, 2, 0x0050, 0x10, 18, 1),
	634	PIN_FIELD_BASE(50, 50, 2, 0x0050, 0x10, 20, 1),
	635	PIN_FIELD_BASE(51, 51, 2, 0x0050, 0x10, 19, 1),
	636	PIN_FIELD_BASE(52, 52, 3, 0x0060, 0x10, 12, 1),
	637	PIN_FIELD_BASE(53, 53, 3, 0x0060, 0x10, 13, 1),
	638	PIN_FIELD_BASE(54, 54, 3, 0x0060, 0x10, 15, 1),
	639	PIN_FIELD_BASE(55, 55, 3, 0x0060, 0x10, 14, 1),
	640	PIN_FIELD_BASE(56, 56, 5, 0x0070, 0x10, 12, 1),
	641	PIN_FIELD_BASE(57, 57, 5, 0x0070, 0x10, 11, 1),
	642	PIN_FIELD_BASE(58, 58, 5, 0x0070, 0x10, 13, 1),
	643	PIN_FIELD_BASE(59, 59, 5, 0x0070, 0x10, 14, 1),
	644	PIN_FIELD_BASE(60, 60, 3, 0x0060, 0x10, 21, 1),
	645	PIN_FIELD_BASE(61, 61, 3, 0x0060, 0x10, 16, 1),
	646	PIN_FIELD_BASE(62, 62, 3, 0x0060, 0x10, 22, 1),
	647	PIN_FIELD_BASE(63, 63, 3, 0x0060, 0x10, 17, 1),
	648	PIN_FIELD_BASE(64, 64, 3, 0x0060, 0x10, 18, 1),
	649	PIN_FIELD_BASE(65, 65, 3, 0x0060, 0x10, 19, 1),
	650	PIN_FIELD_BASE(66, 66, 3, 0x0060, 0x10, 20, 1),
	651	PIN_FIELD_BASE(83, 83, 6, 0x0040, 0x10, 3, 1),
	652	PIN_FIELD_BASE(90, 90, 3, 0x0060, 0x10, 2, 1),
	653	PIN_FIELD_BASE(91, 91, 3, 0x0060, 0x10, 23, 1),
	654	PIN_FIELD_BASE(92, 92, 3, 0x0060, 0x10, 25, 1),
	655	PIN_FIELD_BASE(93, 93, 3, 0x0060, 0x10, 3, 1),
	656	PIN_FIELD_BASE(94, 94, 3, 0x0060, 0x10, 24, 1),
	657	PIN_FIELD_BASE(95, 95, 3, 0x0060, 0x10, 26, 1),
	658	PIN_FIELD_BASE(96, 96, 2, 0x0050, 0x10, 1, 1),
	659	PIN_FIELD_BASE(97, 97, 2, 0x0050, 0x10, 0, 1),
	660	PIN_FIELD_BASE(98, 98, 2, 0x0050, 0x10, 2, 1),
	661	PIN_FIELD_BASE(99, 99, 4, 0x0040, 0x10, 14, 1),
	662	PIN_FIELD_BASE(100, 100, 4, 0x0040, 0x10, 15, 1),
	663	PIN_FIELD_BASE(101, 101, 4, 0x0040, 0x10, 13, 1),
	664	PIN_FIELD_BASE(102, 102, 4, 0x0040, 0x10, 12, 1),
	665	PIN_FIELD_BASE(103, 103, 4, 0x0040, 0x10, 0, 1),
	666	PIN_FIELD_BASE(104, 104, 4, 0x0040, 0x10, 1, 1),
	667	PIN_FIELD_BASE(105, 105, 4, 0x0040, 0x10, 4, 1),
	668	PIN_FIELD_BASE(106, 106, 4, 0x0040, 0x10, 5, 1),
	669	PIN_FIELD_BASE(107, 107, 4, 0x0040, 0x10, 6, 1),
	670	PIN_FIELD_BASE(108, 108, 4, 0x0040, 0x10, 7, 1),
	671	PIN_FIELD_BASE(109, 109, 4, 0x0040, 0x10, 8, 1),
	672	PIN_FIELD_BASE(110, 110, 4, 0x0040, 0x10, 9, 1),
	673	PIN_FIELD_BASE(111, 111, 4, 0x0040, 0x10, 10, 1),
	674	PIN_FIELD_BASE(112, 112, 4, 0x0040, 0x10, 11, 1),
	675	PIN_FIELD_BASE(113, 113, 4, 0x0040, 0x10, 2, 1),
	676	PIN_FIELD_BASE(114, 114, 4, 0x0040, 0x10, 3, 1),
	677	PIN_FIELD_BASE(115, 115, 3, 0x0060, 0x10, 4, 1),
	678	PIN_FIELD_BASE(116, 116, 3, 0x0060, 0x10, 7, 1),
	679	PIN_FIELD_BASE(117, 117, 3, 0x0060, 0x10, 5, 1),
	680	PIN_FIELD_BASE(118, 118, 3, 0x0060, 0x10, 6, 1),
	681	PIN_FIELD_BASE(119, 119, 5, 0x0070, 0x10, 22, 1),
	682	PIN_FIELD_BASE(120, 120, 5, 0x0070, 0x10, 19, 1),
	683	PIN_FIELD_BASE(121, 121, 5, 0x0070, 0x10, 20, 1),
	684	PIN_FIELD_BASE(122, 122, 5, 0x0070, 0x10, 21, 1),
	685	PIN_FIELD_BASE(123, 123, 5, 0x0070, 0x10, 23, 1),
	686	PIN_FIELD_BASE(124, 124, 5, 0x0070, 0x10, 0, 1),
	687	PIN_FIELD_BASE(125, 125, 5, 0x0070, 0x10, 1, 1),
	688	PIN_FIELD_BASE(126, 126, 5, 0x0070, 0x10, 2, 1),
	689	PIN_FIELD_BASE(127, 127, 3, 0x0060, 0x10, 8, 1),
	690	PIN_FIELD_BASE(128, 128, 3, 0x0060, 0x10, 10, 1),
	691	PIN_FIELD_BASE(129, 129, 5, 0x0070, 0x10, 24, 1),
	692	PIN_FIELD_BASE(130, 130, 5, 0x0070, 0x10, 26, 1),
	693	PIN_FIELD_BASE(131, 131, 5, 0x0070, 0x10, 25, 1),
	694	PIN_FIELD_BASE(132, 132, 5, 0x0070, 0x10, 27, 1),
	695	PIN_FIELD_BASE(133, 133, 1, 0x0060, 0x10, 9, 1),
	696	PIN_FIELD_BASE(134, 134, 1, 0x0060, 0x10, 12, 1),
	697	PIN_FIELD_BASE(135, 135, 6, 0x0040, 0x10, 21, 1),
	698	PIN_FIELD_BASE(136, 136, 6, 0x0040, 0x10, 24, 1),
	699	PIN_FIELD_BASE(137, 137, 1, 0x0060, 0x10, 10, 1),
	700	PIN_FIELD_BASE(138, 138, 1, 0x0060, 0x10, 13, 1),
	701	PIN_FIELD_BASE(139, 139, 2, 0x0050, 0x10, 7, 1),
	702	PIN_FIELD_BASE(140, 140, 2, 0x0050, 0x10, 8, 1),
	703	PIN_FIELD_BASE(141, 141, 3, 0x0060, 0x10, 9, 1),
	704	PIN_FIELD_BASE(142, 142, 3, 0x0060, 0x10, 11, 1),
	705	PIN_FIELD_BASE(143, 143, 6, 0x0040, 0x10, 22, 1),
	706	PIN_FIELD_BASE(144, 144, 6, 0x0040, 0x10, 25, 1),
	707	PIN_FIELD_BASE(145, 145, 6, 0x0040, 0x10, 23, 1),
	708	PIN_FIELD_BASE(146, 146, 6, 0x0040, 0x10, 26, 1),
	709	PIN_FIELD_BASE(147, 147, 4, 0x0040, 0x10, 23, 1),
	710	PIN_FIELD_BASE(148, 148, 4, 0x0040, 0x10, 24, 1),
	711	PIN_FIELD_BASE(149, 149, 4, 0x0040, 0x10, 25, 1),
	712	PIN_FIELD_BASE(150, 150, 4, 0x0040, 0x10, 26, 1),
	713	PIN_FIELD_BASE(151, 151, 4, 0x0040, 0x10, 27, 1),
	714	PIN_FIELD_BASE(152, 152, 4, 0x0040, 0x10, 28, 1),
	715	PIN_FIELD_BASE(153, 153, 4, 0x0040, 0x10, 29, 1),
	716	PIN_FIELD_BASE(154, 154, 4, 0x0040, 0x10, 30, 1),
	717	PIN_FIELD_BASE(155, 155, 4, 0x0040, 0x10, 31, 1),
	718	PIN_FIELD_BASE(156, 156, 4, 0x0050, 0x10, 0, 1),
	719	PIN_FIELD_BASE(157, 157, 2, 0x0050, 0x10, 4, 1),
	720	PIN_FIELD_BASE(158, 158, 2, 0x0050, 0x10, 3, 1),
	721	PIN_FIELD_BASE(159, 159, 2, 0x0050, 0x10, 6, 1),
	722	PIN_FIELD_BASE(160, 160, 2, 0x0050, 0x10, 5, 1),
	723	PIN_FIELD_BASE(161, 161, 2, 0x0050, 0x10, 23, 1),
	724	PIN_FIELD_BASE(162, 162, 2, 0x0050, 0x10, 24, 1),
	725	PIN_FIELD_BASE(163, 163, 1, 0x0060, 0x10, 11, 1),
	726	PIN_FIELD_BASE(164, 164, 1, 0x0060, 0x10, 8, 1),
	727	PIN_FIELD_BASE(165, 165, 1, 0x0060, 0x10, 16, 1),
	728	PIN_FIELD_BASE(166, 166, 1, 0x0060, 0x10, 1, 1),
	729	PIN_FIELD_BASE(167, 167, 1, 0x0060, 0x10, 7, 1),
	730	PIN_FIELD_BASE(168, 168, 1, 0x0060, 0x10, 4, 1),
	731	PIN_FIELD_BASE(169, 169, 1, 0x0060, 0x10, 5, 1),
	732	PIN_FIELD_BASE(170, 170, 1, 0x0060, 0x10, 0, 1),
	733	PIN_FIELD_BASE(171, 171, 1, 0x0060, 0x10, 6, 1),
	734	PIN_FIELD_BASE(172, 172, 1, 0x0060, 0x10, 2, 1),
	735	PIN_FIELD_BASE(173, 173, 1, 0x0060, 0x10, 3, 1),
	736	PIN_FIELD_BASE(174, 174, 6, 0x0040, 0x10, 7, 1),
	737	PIN_FIELD_BASE(175, 175, 6, 0x0040, 0x10, 8, 1),
	738	PIN_FIELD_BASE(176, 176, 6, 0x0040, 0x10, 4, 1),
	739	PIN_FIELD_BASE(177, 177, 6, 0x0040, 0x10, 5, 1),
	740	PIN_FIELD_BASE(178, 178, 6, 0x0040, 0x10, 6, 1),
	741	PIN_FIELD_BASE(179, 179, 6, 0x0040, 0x10, 9, 1),
	742	PIN_FIELD_BASE(180, 180, 6, 0x0040, 0x10, 10, 1),
	743	PIN_FIELD_BASE(181, 181, 6, 0x0040, 0x10, 11, 1),
	744	PIN_FIELD_BASE(182, 182, 6, 0x0040, 0x10, 12, 1),
	745	PIN_FIELD_BASE(183, 183, 2, 0x0050, 0x10, 21, 1),
	746	PIN_FIELD_BASE(184, 184, 2, 0x0050, 0x10, 22, 1),
	747	};
	748
	749	static const struct mtk_pin_field_calc mt8186_pin_pupd_range[] = {
	750	PIN_FIELD_BASE(67, 67, 1, 0x0070, 0x10, 10, 1),
	751	PIN_FIELD_BASE(68, 68, 1, 0x0070, 0x10, 0, 1),
	752	PIN_FIELD_BASE(69, 69, 1, 0x0070, 0x10, 1, 1),
	753	PIN_FIELD_BASE(70, 70, 1, 0x0070, 0x10, 11, 1),
	754	PIN_FIELD_BASE(71, 71, 1, 0x0070, 0x10, 2, 1),
	755	PIN_FIELD_BASE(72, 72, 1, 0x0070, 0x10, 3, 1),
	756	PIN_FIELD_BASE(73, 73, 1, 0x0070, 0x10, 4, 1),
	757	PIN_FIELD_BASE(74, 74, 1, 0x0070, 0x10, 5, 1),
	758	PIN_FIELD_BASE(75, 75, 1, 0x0070, 0x10, 6, 1),
	759	PIN_FIELD_BASE(76, 76, 1, 0x0070, 0x10, 7, 1),
	760	PIN_FIELD_BASE(77, 77, 1, 0x0070, 0x10, 8, 1),
	761	PIN_FIELD_BASE(78, 78, 1, 0x0070, 0x10, 9, 1),
	762	PIN_FIELD_BASE(79, 79, 5, 0x0080, 0x10, 0, 1),
	763	PIN_FIELD_BASE(80, 80, 5, 0x0080, 0x10, 1, 1),
	764	PIN_FIELD_BASE(81, 81, 5, 0x0080, 0x10, 2, 1),
	765	PIN_FIELD_BASE(82, 82, 5, 0x0080, 0x10, 3, 1),
	766	PIN_FIELD_BASE(84, 84, 3, 0x0070, 0x10, 0, 1),
	767	PIN_FIELD_BASE(85, 85, 3, 0x0070, 0x10, 1, 1),
	768	PIN_FIELD_BASE(86, 86, 3, 0x0070, 0x10, 2, 1),
	769	PIN_FIELD_BASE(87, 87, 3, 0x0070, 0x10, 3, 1),
	770	PIN_FIELD_BASE(88, 88, 3, 0x0070, 0x10, 4, 1),
	771	PIN_FIELD_BASE(89, 89, 3, 0x0070, 0x10, 5, 1),
	772	};
	773
	774	static const struct mtk_pin_field_calc mt8186_pin_r0_range[] = {
	775	PIN_FIELD_BASE(67, 67, 1, 0x0090, 0x10, 10, 1),
	776	PIN_FIELD_BASE(68, 68, 1, 0x0090, 0x10, 0, 1),
	777	PIN_FIELD_BASE(69, 69, 1, 0x0090, 0x10, 1, 1),
	778	PIN_FIELD_BASE(70, 70, 1, 0x0090, 0x10, 11, 1),
	779	PIN_FIELD_BASE(71, 71, 1, 0x0090, 0x10, 2, 1),
	780	PIN_FIELD_BASE(72, 72, 1, 0x0090, 0x10, 3, 1),
	781	PIN_FIELD_BASE(73, 73, 1, 0x0090, 0x10, 4, 1),
	782	PIN_FIELD_BASE(74, 74, 1, 0x0090, 0x10, 5, 1),
	783	PIN_FIELD_BASE(75, 75, 1, 0x0090, 0x10, 6, 1),
	784	PIN_FIELD_BASE(76, 76, 1, 0x0090, 0x10, 7, 1),
	785	PIN_FIELD_BASE(77, 77, 1, 0x0090, 0x10, 8, 1),
	786	PIN_FIELD_BASE(78, 78, 1, 0x0090, 0x10, 9, 1),
	787	PIN_FIELD_BASE(79, 79, 5, 0x00a0, 0x10, 0, 1),
	788	PIN_FIELD_BASE(80, 80, 5, 0x00a0, 0x10, 1, 1),
	789	PIN_FIELD_BASE(81, 81, 5, 0x00a0, 0x10, 2, 1),
	790	PIN_FIELD_BASE(82, 82, 5, 0x00a0, 0x10, 3, 1),
	791	PIN_FIELD_BASE(84, 84, 3, 0x0090, 0x10, 0, 1),
	792	PIN_FIELD_BASE(85, 85, 3, 0x0090, 0x10, 1, 1),
	793	PIN_FIELD_BASE(86, 86, 3, 0x0090, 0x10, 2, 1),
	794	PIN_FIELD_BASE(87, 87, 3, 0x0090, 0x10, 3, 1),
	795	PIN_FIELD_BASE(88, 88, 3, 0x0090, 0x10, 4, 1),
	796	PIN_FIELD_BASE(89, 89, 3, 0x0090, 0x10, 5, 1),
	797	};
	798
	799	static const struct mtk_pin_field_calc mt8186_pin_r1_range[] = {
	800	PIN_FIELD_BASE(67, 67, 1, 0x00a0, 0x10, 10, 1),
	801	PIN_FIELD_BASE(68, 68, 1, 0x00a0, 0x10, 0, 1),
	802	PIN_FIELD_BASE(69, 69, 1, 0x00a0, 0x10, 1, 1),
	803	PIN_FIELD_BASE(70, 70, 1, 0x00a0, 0x10, 11, 1),
	804	PIN_FIELD_BASE(71, 71, 1, 0x00a0, 0x10, 2, 1),
	805	PIN_FIELD_BASE(72, 72, 1, 0x00a0, 0x10, 3, 1),
	806	PIN_FIELD_BASE(73, 73, 1, 0x00a0, 0x10, 4, 1),
	807	PIN_FIELD_BASE(74, 74, 1, 0x00a0, 0x10, 5, 1),
	808	PIN_FIELD_BASE(75, 75, 1, 0x00a0, 0x10, 6, 1),
	809	PIN_FIELD_BASE(76, 76, 1, 0x00a0, 0x10, 7, 1),
	810	PIN_FIELD_BASE(77, 77, 1, 0x00a0, 0x10, 8, 1),
	811	PIN_FIELD_BASE(78, 78, 1, 0x00a0, 0x10, 9, 1),
	812	PIN_FIELD_BASE(79, 79, 5, 0x00b0, 0x10, 0, 1),
	813	PIN_FIELD_BASE(80, 80, 5, 0x00b0, 0x10, 1, 1),
	814	PIN_FIELD_BASE(81, 81, 5, 0x00b0, 0x10, 2, 1),
	815	PIN_FIELD_BASE(82, 82, 5, 0x00b0, 0x10, 3, 1),
	816	PIN_FIELD_BASE(84, 84, 3, 0x00a0, 0x10, 0, 1),
	817	PIN_FIELD_BASE(85, 85, 3, 0x00a0, 0x10, 1, 1),
	818	PIN_FIELD_BASE(86, 86, 3, 0x00a0, 0x10, 2, 1),
	819	PIN_FIELD_BASE(87, 87, 3, 0x00a0, 0x10, 3, 1),
	820	PIN_FIELD_BASE(88, 88, 3, 0x00a0, 0x10, 4, 1),
	821	PIN_FIELD_BASE(89, 89, 3, 0x00a0, 0x10, 5, 1),
	822	};
	823
	824	static const struct mtk_pin_field_calc mt8186_pin_drv_range[] = {
	825	PIN_FIELD_BASE(0, 0, 6, 0x0000, 0x10, 27, 3),
	826	PIN_FIELD_BASE(1, 1, 6, 0x0000, 0x10, 27, 3),
	827	PIN_FIELD_BASE(2, 2, 6, 0x0000, 0x10, 27, 3),
	828	PIN_FIELD_BASE(3, 3, 6, 0x0000, 0x10, 27, 3),
	829	PIN_FIELD_BASE(4, 4, 6, 0x0010, 0x10, 0, 3),
	830	PIN_FIELD_BASE(5, 5, 6, 0x0010, 0x10, 0, 3),
	831	PIN_FIELD_BASE(6, 6, 4, 0x0000, 0x10, 9, 3),
	832	PIN_FIELD_BASE(7, 7, 4, 0x0000, 0x10, 9, 3),
	833	PIN_FIELD_BASE(8, 8, 4, 0x0000, 0x10, 9, 3),
	834	PIN_FIELD_BASE(9, 9, 4, 0x0000, 0x10, 12, 3),
	835	PIN_FIELD_BASE(10, 10, 4, 0x0000, 0x10, 0, 3),
	836	PIN_FIELD_BASE(11, 11, 4, 0x0000, 0x10, 3, 3),
	837	PIN_FIELD_BASE(12, 12, 4, 0x0000, 0x10, 6, 3),
	838	PIN_FIELD_BASE(13, 13, 3, 0x0000, 0x10, 0, 3),
	839	PIN_FIELD_BASE(14, 14, 3, 0x0000, 0x10, 3, 3),
	840	PIN_FIELD_BASE(15, 15, 6, 0x0010, 0x10, 3, 3),
	841	PIN_FIELD_BASE(16, 16, 6, 0x0010, 0x10, 3, 3),
	842	PIN_FIELD_BASE(17, 17, 5, 0x0000, 0x10, 21, 3),
	843	PIN_FIELD_BASE(18, 18, 5, 0x0010, 0x10, 0, 3),
	844	PIN_FIELD_BASE(19, 19, 5, 0x0000, 0x10, 27, 3),
	845	PIN_FIELD_BASE(20, 20, 5, 0x0000, 0x10, 24, 3),
	846	PIN_FIELD_BASE(21, 21, 5, 0x0000, 0x10, 27, 3),
	847	PIN_FIELD_BASE(22, 22, 5, 0x0000, 0x10, 24, 3),
	848	PIN_FIELD_BASE(23, 23, 5, 0x0010, 0x10, 0, 3),
	849	PIN_FIELD_BASE(24, 24, 5, 0x0010, 0x10, 9, 3),
	850	PIN_FIELD_BASE(25, 25, 5, 0x0010, 0x10, 0, 3),
	851	PIN_FIELD_BASE(26, 26, 5, 0x0000, 0x10, 27, 3),
	852	PIN_FIELD_BASE(27, 27, 5, 0x0000, 0x10, 27, 3),
	853	PIN_FIELD_BASE(28, 28, 5, 0x0010, 0x10, 0, 3),
	854	PIN_FIELD_BASE(29, 29, 6, 0x0010, 0x10, 0, 3),
	855	PIN_FIELD_BASE(30, 30, 6, 0x0010, 0x10, 0, 3),
	856	PIN_FIELD_BASE(31, 31, 6, 0x0010, 0x10, 3, 3),
	857	PIN_FIELD_BASE(32, 32, 2, 0x0000, 0x10, 6, 3),
	858	PIN_FIELD_BASE(33, 33, 2, 0x0000, 0x10, 6, 3),
	859	PIN_FIELD_BASE(34, 34, 2, 0x0000, 0x10, 3, 3),
	860	PIN_FIELD_BASE(35, 35, 2, 0x0000, 0x10, 3, 3),
	861	PIN_FIELD_BASE(36, 36, 2, 0x0000, 0x10, 9, 3),
	862	PIN_FIELD_BASE(37, 37, 2, 0x0000, 0x10, 9, 3),
	863	PIN_FIELD_BASE(38, 38, 2, 0x0000, 0x10, 12, 3),
	864	PIN_FIELD_BASE(39, 39, 2, 0x0000, 0x10, 9, 3),
	865	PIN_FIELD_BASE(40, 40, 2, 0x0000, 0x10, 15, 3),
	866	PIN_FIELD_BASE(41, 41, 2, 0x0000, 0x10, 12, 3),
	867	PIN_FIELD_BASE(42, 42, 2, 0x0000, 0x10, 12, 3),
	868	PIN_FIELD_BASE(43, 43, 2, 0x0000, 0x10, 12, 3),
	869	PIN_FIELD_BASE(44, 44, 5, 0x0010, 0x10, 6, 3),
	870	PIN_FIELD_BASE(45, 45, 5, 0x0010, 0x10, 3, 3),
	871	PIN_FIELD_BASE(46, 46, 5, 0x0010, 0x10, 3, 3),
	872	PIN_FIELD_BASE(47, 47, 5, 0x0010, 0x10, 6, 3),
	873	PIN_FIELD_BASE(48, 48, 2, 0x0000, 0x10, 15, 3),
	874	PIN_FIELD_BASE(49, 49, 2, 0x0000, 0x10, 15, 3),
	875	PIN_FIELD_BASE(50, 50, 2, 0x0000, 0x10, 15, 3),
	876	PIN_FIELD_BASE(51, 51, 2, 0x0000, 0x10, 18, 3),
	877	PIN_FIELD_BASE(52, 52, 3, 0x0010, 0x10, 3, 3),
	878	PIN_FIELD_BASE(53, 53, 3, 0x0010, 0x10, 6, 3),
	879	PIN_FIELD_BASE(54, 54, 3, 0x0010, 0x10, 3, 3),
	880	PIN_FIELD_BASE(55, 55, 3, 0x0010, 0x10, 3, 3),
	881	PIN_FIELD_BASE(56, 56, 5, 0x0010, 0x10, 3, 3),
	882	PIN_FIELD_BASE(57, 57, 5, 0x0010, 0x10, 6, 3),
	883	PIN_FIELD_BASE(58, 58, 5, 0x0010, 0x10, 6, 3),
	884	PIN_FIELD_BASE(59, 59, 5, 0x0010, 0x10, 3, 3),
	885	PIN_FIELD_BASE(60, 60, 3, 0x0000, 0x10, 24, 3),
	886	PIN_FIELD_BASE(61, 61, 3, 0x0000, 0x10, 24, 3),
	887	PIN_FIELD_BASE(62, 62, 3, 0x0000, 0x10, 24, 3),
	888	PIN_FIELD_BASE(63, 63, 3, 0x0000, 0x10, 24, 3),
	889	PIN_FIELD_BASE(64, 64, 3, 0x0000, 0x10, 27, 3),
	890	PIN_FIELD_BASE(65, 65, 3, 0x0000, 0x10, 27, 3),
	891	PIN_FIELD_BASE(66, 66, 3, 0x0000, 0x10, 27, 3),
	892	PIN_FIELD_BASE(67, 67, 1, 0x0010, 0x10, 0, 3),
	893	PIN_FIELD_BASE(68, 68, 1, 0x0000, 0x10, 0, 3),
	894	PIN_FIELD_BASE(69, 69, 1, 0x0000, 0x10, 3, 3),
	895	PIN_FIELD_BASE(70, 70, 1, 0x0010, 0x10, 3, 3),
	896	PIN_FIELD_BASE(71, 71, 1, 0x0000, 0x10, 6, 3),
	897	PIN_FIELD_BASE(72, 72, 1, 0x0000, 0x10, 9, 3),
	898	PIN_FIELD_BASE(73, 73, 1, 0x0000, 0x10, 12, 3),
	899	PIN_FIELD_BASE(74, 74, 1, 0x0000, 0x10, 15, 3),
	900	PIN_FIELD_BASE(75, 75, 1, 0x0000, 0x10, 18, 3),
	901	PIN_FIELD_BASE(76, 76, 1, 0x0000, 0x10, 21, 3),
	902	PIN_FIELD_BASE(77, 77, 1, 0x0000, 0x10, 24, 3),
	903	PIN_FIELD_BASE(78, 78, 1, 0x0000, 0x10, 27, 3),
	904	PIN_FIELD_BASE(79, 79, 5, 0x0000, 0x10, 24, 3),
	905	PIN_FIELD_BASE(80, 80, 5, 0x0000, 0x10, 24, 3),
	906	PIN_FIELD_BASE(81, 81, 5, 0x0000, 0x10, 21, 3),
	907	PIN_FIELD_BASE(82, 82, 5, 0x0000, 0x10, 21, 3),
	908	PIN_FIELD_BASE(83, 83, 6, 0x0010, 0x10, 3, 3),
	909	PIN_FIELD_BASE(84, 84, 3, 0x0000, 0x10, 6, 3),
	910	PIN_FIELD_BASE(85, 85, 3, 0x0000, 0x10, 9, 3),
	911	PIN_FIELD_BASE(86, 86, 3, 0x0000, 0x10, 12, 3),
	912	PIN_FIELD_BASE(87, 87, 3, 0x0000, 0x10, 15, 3),
	913	PIN_FIELD_BASE(88, 88, 3, 0x0000, 0x10, 18, 3),
	914	PIN_FIELD_BASE(89, 89, 3, 0x0000, 0x10, 21, 3),
	915	PIN_FIELD_BASE(90, 90, 3, 0x0000, 0x10, 27, 3),
	916	PIN_FIELD_BASE(91, 91, 3, 0x0010, 0x10, 0, 3),
	917	PIN_FIELD_BASE(92, 92, 3, 0x0010, 0x10, 0, 3),
	918	PIN_FIELD_BASE(93, 93, 3, 0x0010, 0x10, 0, 3),
	919	PIN_FIELD_BASE(94, 94, 3, 0x0010, 0x10, 0, 3),
	920	PIN_FIELD_BASE(95, 95, 3, 0x0010, 0x10, 3, 3),
	921	PIN_FIELD_BASE(96, 96, 2, 0x0000, 0x10, 9, 3),
	922	PIN_FIELD_BASE(97, 97, 2, 0x0000, 0x10, 6, 3),
	923	PIN_FIELD_BASE(98, 98, 2, 0x0000, 0x10, 3, 3),
	924	PIN_FIELD_BASE(99, 99, 4, 0x0000, 0x10, 18, 3),
	925	PIN_FIELD_BASE(100, 100, 4, 0x0000, 0x10, 18, 3),
	926	PIN_FIELD_BASE(101, 101, 4, 0x0000, 0x10, 21, 3),
	927	PIN_FIELD_BASE(102, 102, 4, 0x0000, 0x10, 21, 3),
	928	PIN_FIELD_BASE(103, 103, 4, 0x0000, 0x10, 21, 3),
	929	PIN_FIELD_BASE(104, 104, 4, 0x0000, 0x10, 21, 3),
	930	PIN_FIELD_BASE(105, 105, 4, 0x0000, 0x10, 24, 3),
	931	PIN_FIELD_BASE(106, 106, 4, 0x0000, 0x10, 24, 3),
	932	PIN_FIELD_BASE(107, 107, 4, 0x0000, 0x10, 24, 3),
	933	PIN_FIELD_BASE(108, 108, 4, 0x0000, 0x10, 24, 3),
	934	PIN_FIELD_BASE(109, 109, 4, 0x0000, 0x10, 27, 3),
	935	PIN_FIELD_BASE(110, 110, 4, 0x0000, 0x10, 27, 3),
	936	PIN_FIELD_BASE(111, 111, 4, 0x0000, 0x10, 27, 3),
	937	PIN_FIELD_BASE(112, 112, 4, 0x0000, 0x10, 27, 3),
	938	PIN_FIELD_BASE(113, 113, 4, 0x0010, 0x10, 0, 3),
	939	PIN_FIELD_BASE(114, 114, 4, 0x0010, 0x10, 0, 3),
	940	PIN_FIELD_BASE(115, 115, 3, 0x0010, 0x10, 6, 3),
	941	PIN_FIELD_BASE(116, 116, 3, 0x0010, 0x10, 9, 3),
	942	PIN_FIELD_BASE(117, 117, 3, 0x0010, 0x10, 6, 3),
	943	PIN_FIELD_BASE(118, 118, 3, 0x0010, 0x10, 6, 3),
	944	PIN_FIELD_BASE(119, 119, 5, 0x0000, 0x10, 18, 3),
	945	PIN_FIELD_BASE(120, 120, 5, 0x0000, 0x10, 9, 3),
	946	PIN_FIELD_BASE(121, 121, 5, 0x0000, 0x10, 12, 3),
	947	PIN_FIELD_BASE(122, 122, 5, 0x0000, 0x10, 15, 3),
	948	PIN_FIELD_BASE(123, 123, 5, 0x0000, 0x10, 21, 3),
	949	PIN_FIELD_BASE(124, 124, 5, 0x0000, 0x10, 0, 3),
	950	PIN_FIELD_BASE(125, 125, 5, 0x0000, 0x10, 3, 3),
	951	PIN_FIELD_BASE(126, 126, 5, 0x0000, 0x10, 6, 3),
	952	PIN_FIELD_BASE(127, 127, 3, 0x0010, 0x10, 12, 3),
	953	PIN_FIELD_BASE(128, 128, 3, 0x0010, 0x10, 18, 3),
	954	PIN_FIELD_BASE(129, 129, 5, 0x0010, 0x10, 12, 3),
	955	PIN_FIELD_BASE(130, 130, 5, 0x0010, 0x10, 18, 3),
	956	PIN_FIELD_BASE(131, 131, 5, 0x0010, 0x10, 15, 3),
	957	PIN_FIELD_BASE(132, 132, 5, 0x0010, 0x10, 21, 3),
	958	PIN_FIELD_BASE(133, 133, 1, 0x0010, 0x10, 15, 3),
	959	PIN_FIELD_BASE(134, 134, 1, 0x0010, 0x10, 21, 3),
	960	PIN_FIELD_BASE(135, 135, 6, 0x0010, 0x10, 6, 3),
	961	PIN_FIELD_BASE(136, 136, 6, 0x0010, 0x10, 15, 3),
	962	PIN_FIELD_BASE(137, 137, 1, 0x0010, 0x10, 18, 3),
	963	PIN_FIELD_BASE(138, 138, 1, 0x0010, 0x10, 24, 3),
	964	PIN_FIELD_BASE(139, 139, 2, 0x0000, 0x10, 21, 3),
	965	PIN_FIELD_BASE(140, 140, 2, 0x0000, 0x10, 24, 3),
	966	PIN_FIELD_BASE(141, 141, 3, 0x0010, 0x10, 15, 3),
	967	PIN_FIELD_BASE(142, 142, 3, 0x0010, 0x10, 21, 3),
	968	PIN_FIELD_BASE(143, 143, 6, 0x0010, 0x10, 9, 3),
	969	PIN_FIELD_BASE(144, 144, 6, 0x0010, 0x10, 18, 3),
	970	PIN_FIELD_BASE(145, 145, 6, 0x0010, 0x10, 12, 3),
	971	PIN_FIELD_BASE(146, 146, 6, 0x0010, 0x10, 21, 3),
	972	PIN_FIELD_BASE(147, 147, 4, 0x0000, 0x10, 12, 3),
	973	PIN_FIELD_BASE(148, 148, 4, 0x0000, 0x10, 12, 3),
	974	PIN_FIELD_BASE(149, 149, 4, 0x0000, 0x10, 12, 3),
	975	PIN_FIELD_BASE(150, 150, 4, 0x0000, 0x10, 15, 3),
	976	PIN_FIELD_BASE(151, 151, 4, 0x0000, 0x10, 15, 3),
	977	PIN_FIELD_BASE(152, 152, 4, 0x0000, 0x10, 9, 3),
	978	PIN_FIELD_BASE(153, 153, 4, 0x0000, 0x10, 15, 3),
	979	PIN_FIELD_BASE(154, 154, 4, 0x0000, 0x10, 15, 3),
	980	PIN_FIELD_BASE(155, 155, 4, 0x0000, 0x10, 18, 3),
	981	PIN_FIELD_BASE(156, 156, 4, 0x0000, 0x10, 18, 3),
	982	PIN_FIELD_BASE(157, 157, 2, 0x0000, 0x10, 0, 3),
	983	PIN_FIELD_BASE(158, 158, 2, 0x0000, 0x10, 0, 3),
	984	PIN_FIELD_BASE(159, 159, 2, 0x0000, 0x10, 0, 3),
	985	PIN_FIELD_BASE(160, 160, 2, 0x0000, 0x10, 0, 3),
	986	PIN_FIELD_BASE(161, 161, 2, 0x0000, 0x10, 6, 3),
	987	PIN_FIELD_BASE(162, 162, 2, 0x0000, 0x10, 3, 3),
	988	PIN_FIELD_BASE(163, 163, 1, 0x0010, 0x10, 12, 3),
	989	PIN_FIELD_BASE(165, 165, 1, 0x0010, 0x10, 6, 3),
	990	PIN_FIELD_BASE(166, 166, 1, 0x0010, 0x10, 6, 3),
	991	PIN_FIELD_BASE(167, 167, 1, 0x0010, 0x10, 9, 3),
	992	PIN_FIELD_BASE(168, 168, 1, 0x0010, 0x10, 6, 3),
	993	PIN_FIELD_BASE(169, 169, 1, 0x0010, 0x10, 12, 3),
	994	PIN_FIELD_BASE(170, 170, 1, 0x0010, 0x10, 9, 3),
	995	PIN_FIELD_BASE(171, 171, 1, 0x0010, 0x10, 9, 3),
	996	PIN_FIELD_BASE(172, 172, 1, 0x0010, 0x10, 9, 3),
	997	PIN_FIELD_BASE(173, 173, 1, 0x0010, 0x10, 6, 3),
	998	PIN_FIELD_BASE(174, 174, 6, 0x0000, 0x10, 9, 3),
	999	PIN_FIELD_BASE(175, 175, 6, 0x0000, 0x10, 12, 3),
	1000	PIN_FIELD_BASE(176, 176, 6, 0x0000, 0x10, 0, 3),
	1001	PIN_FIELD_BASE(177, 177, 6, 0x0000, 0x10, 3, 3),
	1002	PIN_FIELD_BASE(178, 178, 6, 0x0000, 0x10, 6, 3),
	1003	PIN_FIELD_BASE(179, 179, 6, 0x0000, 0x10, 15, 3),
	1004	PIN_FIELD_BASE(180, 180, 6, 0x0000, 0x10, 18, 3),
	1005	PIN_FIELD_BASE(181, 181, 6, 0x0000, 0x10, 21, 3),
	1006	PIN_FIELD_BASE(182, 182, 6, 0x0000, 0x10, 24, 3),
	1007	PIN_FIELD_BASE(183, 183, 2, 0x0000, 0x10, 27, 3),
	1008	PIN_FIELD_BASE(184, 184, 2, 0x0010, 0x10, 0, 3),
	1009	};
	1010
	1011	static const struct mtk_pin_field_calc mt8186_pin_drv_adv_range[] = {
	1012	PIN_FIELD_BASE(127, 127, 3, 0x0030, 0x10, 0, 3),
	1013	PIN_FIELD_BASE(128, 128, 3, 0x0030, 0x10, 6, 3),
	1014	PIN_FIELD_BASE(129, 129, 5, 0x0030, 0x10, 0, 3),
	1015	PIN_FIELD_BASE(130, 130, 5, 0x0030, 0x10, 6, 3),
	1016	PIN_FIELD_BASE(131, 131, 5, 0x0030, 0x10, 3, 3),
	1017	PIN_FIELD_BASE(132, 132, 5, 0x0030, 0x10, 9, 3),
	1018	PIN_FIELD_BASE(133, 133, 1, 0x0030, 0x10, 0, 3),
	1019	PIN_FIELD_BASE(134, 134, 1, 0x0030, 0x10, 6, 3),
	1020	PIN_FIELD_BASE(135, 135, 6, 0x0020, 0x10, 0, 3),
	1021	PIN_FIELD_BASE(136, 136, 6, 0x0020, 0x10, 9, 3),
	1022	PIN_FIELD_BASE(137, 137, 1, 0x0030, 0x10, 3, 3),
	1023	PIN_FIELD_BASE(138, 138, 1, 0x0030, 0x10, 9, 3),
	1024	PIN_FIELD_BASE(139, 139, 2, 0x0020, 0x10, 0, 3),
	1025	PIN_FIELD_BASE(140, 140, 2, 0x0020, 0x10, 3, 3),
	1026	PIN_FIELD_BASE(141, 141, 3, 0x0030, 0x10, 3, 3),
	1027	PIN_FIELD_BASE(142, 142, 3, 0x0030, 0x10, 9, 3),
	1028	PIN_FIELD_BASE(143, 143, 6, 0x0020, 0x10, 3, 3),
	1029	PIN_FIELD_BASE(144, 144, 6, 0x0020, 0x10, 12, 3),
	1030	PIN_FIELD_BASE(145, 145, 6, 0x0020, 0x10, 6, 3),
	1031	PIN_FIELD_BASE(146, 146, 6, 0x0020, 0x10, 15, 3),
	1032	};
	1033
	1034	static const struct mtk_pin_field_calc mt8186_pin_rsel_range[] = {
	1035	PIN_FIELD_BASE(127, 127, 3, 0x00d0, 0x10, 0, 2),
	1036	PIN_FIELD_BASE(128, 128, 3, 0x00d0, 0x10, 4, 2),
	1037	PIN_FIELD_BASE(129, 129, 5, 0x00d0, 0x10, 0, 2),
	1038	PIN_FIELD_BASE(130, 130, 5, 0x00d0, 0x10, 4, 2),
	1039	PIN_FIELD_BASE(131, 131, 5, 0x00d0, 0x10, 2, 2),
	1040	PIN_FIELD_BASE(132, 132, 5, 0x00d0, 0x10, 6, 2),
	1041	PIN_FIELD_BASE(133, 133, 1, 0x00e0, 0x10, 0, 2),
	1042	PIN_FIELD_BASE(134, 134, 1, 0x00e0, 0x10, 4, 2),
	1043	PIN_FIELD_BASE(135, 135, 6, 0x0070, 0x10, 0, 2),
	1044	PIN_FIELD_BASE(136, 136, 6, 0x0070, 0x10, 6, 2),
	1045	PIN_FIELD_BASE(137, 137, 1, 0x00e0, 0x10, 2, 2),
	1046	PIN_FIELD_BASE(138, 138, 1, 0x00e0, 0x10, 6, 2),
	1047	PIN_FIELD_BASE(139, 139, 2, 0x0080, 0x10, 0, 2),
	1048	PIN_FIELD_BASE(140, 140, 2, 0x0080, 0x10, 2, 2),
	1049	PIN_FIELD_BASE(141, 141, 3, 0x00d0, 0x10, 2, 2),
	1050	PIN_FIELD_BASE(142, 142, 3, 0x00d0, 0x10, 6, 2),
	1051	PIN_FIELD_BASE(143, 143, 6, 0x0070, 0x10, 2, 2),
	1052	PIN_FIELD_BASE(144, 144, 6, 0x0070, 0x10, 8, 2),
	1053	PIN_FIELD_BASE(145, 145, 6, 0x0070, 0x10, 4, 2),
	1054	PIN_FIELD_BASE(146, 146, 6, 0x0070, 0x10, 10, 2),
	1055	};
	1056
	1057	static const struct mtk_pin_rsel mt8186_pin_rsel_val_range[] = {
	1058	PIN_RSEL(127, 128, 0x0, 75000, 75000),
	1059	PIN_RSEL(127, 128, 0x1, 10000, 75000),
	1060	PIN_RSEL(127, 128, 0x2, 5000, 5000),
	1061	PIN_RSEL(127, 128, 0x3, 1000, 5000),
	1062	PIN_RSEL(129, 130, 0x0, 75000, 75000),
	1063	PIN_RSEL(129, 130, 0x1, 10000, 75000),
	1064	PIN_RSEL(129, 130, 0x2, 5000, 5000),
	1065	PIN_RSEL(129, 130, 0x3, 1000, 5000),
	1066	PIN_RSEL(131, 132, 0x0, 75000, 75000),
	1067	PIN_RSEL(131, 132, 0x1, 10000, 75000),
	1068	PIN_RSEL(131, 132, 0x2, 5000, 5000),
	1069	PIN_RSEL(131, 132, 0x3, 1000, 5000),
	1070	PIN_RSEL(133, 134, 0x0, 75000, 75000),
	1071	PIN_RSEL(133, 134, 0x1, 10000, 75000),
	1072	PIN_RSEL(133, 134, 0x2, 5000, 5000),
	1073	PIN_RSEL(133, 134, 0x3, 1000, 5000),
	1074	PIN_RSEL(135, 136, 0x0, 75000, 75000),
	1075	PIN_RSEL(135, 136, 0x1, 10000, 75000),
	1076	PIN_RSEL(135, 136, 0x2, 5000, 5000),
	1077	PIN_RSEL(135, 136, 0x3, 1000, 5000),
	1078	PIN_RSEL(137, 138, 0x0, 75000, 75000),
	1079	PIN_RSEL(137, 138, 0x1, 10000, 75000),
	1080	PIN_RSEL(137, 138, 0x2, 5000, 5000),
	1081	PIN_RSEL(137, 138, 0x3, 1000, 5000),
	1082	PIN_RSEL(139, 140, 0x0, 75000, 75000),
	1083	PIN_RSEL(139, 140, 0x1, 10000, 75000),
	1084	PIN_RSEL(139, 140, 0x2, 5000, 5000),
	1085	PIN_RSEL(139, 140, 0x3, 1000, 5000),
	1086	PIN_RSEL(141, 142, 0x0, 75000, 75000),
	1087	PIN_RSEL(141, 142, 0x1, 10000, 75000),
	1088	PIN_RSEL(141, 142, 0x2, 5000, 5000),
	1089	PIN_RSEL(141, 142, 0x3, 1000, 5000),
	1090	PIN_RSEL(143, 144, 0x0, 75000, 75000),
	1091	PIN_RSEL(143, 144, 0x1, 10000, 75000),
	1092	PIN_RSEL(143, 144, 0x2, 5000, 5000),
	1093	PIN_RSEL(143, 144, 0x3, 1000, 5000),
	1094	PIN_RSEL(145, 146, 0x0, 75000, 75000),
	1095	PIN_RSEL(145, 146, 0x1, 10000, 75000),
	1096	PIN_RSEL(145, 146, 0x2, 5000, 5000),
	1097	PIN_RSEL(145, 146, 0x3, 1000, 5000),
	1098	};
	1099
	1100	static const unsigned int mt8186_pull_type[] = {
	1101	MTK_PULL_PU_PD_TYPE,/0/ MTK_PULL_PU_PD_TYPE,/1/
	1102	MTK_PULL_PU_PD_TYPE,/2/ MTK_PULL_PU_PD_TYPE,/3/
	1103	MTK_PULL_PU_PD_TYPE,/4/ MTK_PULL_PU_PD_TYPE,/5/
	1104	MTK_PULL_PU_PD_TYPE,/6/ MTK_PULL_PU_PD_TYPE,/7/
	1105	MTK_PULL_PU_PD_TYPE,/8/ MTK_PULL_PU_PD_TYPE,/9/
	1106	MTK_PULL_PU_PD_TYPE,/10/ MTK_PULL_PU_PD_TYPE,/11/
	1107	MTK_PULL_PU_PD_TYPE,/12/ MTK_PULL_PU_PD_TYPE,/13/
	1108	MTK_PULL_PU_PD_TYPE,/14/ MTK_PULL_PU_PD_TYPE,/15/
	1109	MTK_PULL_PU_PD_TYPE,/16/ MTK_PULL_PU_PD_TYPE,/17/
	1110	MTK_PULL_PU_PD_TYPE,/18/ MTK_PULL_PU_PD_TYPE,/19/
	1111	MTK_PULL_PU_PD_TYPE,/20/ MTK_PULL_PU_PD_TYPE,/21/
	1112	MTK_PULL_PU_PD_TYPE,/22/ MTK_PULL_PU_PD_TYPE,/23/
	1113	MTK_PULL_PU_PD_TYPE,/24/ MTK_PULL_PU_PD_TYPE,/25/
	1114	MTK_PULL_PU_PD_TYPE,/26/ MTK_PULL_PU_PD_TYPE,/27/
	1115	MTK_PULL_PU_PD_TYPE,/28/ MTK_PULL_PU_PD_TYPE,/29/
	1116	MTK_PULL_PU_PD_TYPE,/30/ MTK_PULL_PU_PD_TYPE,/31/
	1117	MTK_PULL_PU_PD_TYPE,/32/ MTK_PULL_PU_PD_TYPE,/33/
	1118	MTK_PULL_PU_PD_TYPE,/34/ MTK_PULL_PU_PD_TYPE,/35/
	1119	MTK_PULL_PU_PD_TYPE,/36/ MTK_PULL_PU_PD_TYPE,/37/
	1120	MTK_PULL_PU_PD_TYPE,/38/ MTK_PULL_PU_PD_TYPE,/39/
	1121	MTK_PULL_PU_PD_TYPE,/40/ MTK_PULL_PU_PD_TYPE,/41/
	1122	MTK_PULL_PU_PD_TYPE,/42/ MTK_PULL_PU_PD_TYPE,/43/
	1123	MTK_PULL_PU_PD_TYPE,/44/ MTK_PULL_PU_PD_TYPE,/45/
	1124	MTK_PULL_PU_PD_TYPE,/46/ MTK_PULL_PU_PD_TYPE,/47/
	1125	MTK_PULL_PU_PD_TYPE,/48/ MTK_PULL_PU_PD_TYPE,/49/
	1126	MTK_PULL_PU_PD_TYPE,/50/ MTK_PULL_PU_PD_TYPE,/51/
	1127	MTK_PULL_PU_PD_TYPE,/52/ MTK_PULL_PU_PD_TYPE,/53/
	1128	MTK_PULL_PU_PD_TYPE,/54/ MTK_PULL_PU_PD_TYPE,/55/
	1129	MTK_PULL_PU_PD_TYPE,/56/ MTK_PULL_PU_PD_TYPE,/57/
	1130	MTK_PULL_PU_PD_TYPE,/58/ MTK_PULL_PU_PD_TYPE,/59/
	1131	MTK_PULL_PU_PD_TYPE,/60/ MTK_PULL_PU_PD_TYPE,/61/
	1132	MTK_PULL_PU_PD_TYPE,/62/ MTK_PULL_PU_PD_TYPE,/63/
	1133	MTK_PULL_PU_PD_TYPE,/64/ MTK_PULL_PU_PD_TYPE,/65/
	1134	MTK_PULL_PU_PD_TYPE,/66/ MTK_PULL_PUPD_R1R0_TYPE,/67/
	1135	MTK_PULL_PUPD_R1R0_TYPE,/68/ MTK_PULL_PUPD_R1R0_TYPE,/69/
	1136	MTK_PULL_PUPD_R1R0_TYPE,/70/ MTK_PULL_PUPD_R1R0_TYPE,/71/
	1137	MTK_PULL_PUPD_R1R0_TYPE,/72/ MTK_PULL_PUPD_R1R0_TYPE,/73/
	1138	MTK_PULL_PUPD_R1R0_TYPE,/74/ MTK_PULL_PUPD_R1R0_TYPE,/75/
	1139	MTK_PULL_PUPD_R1R0_TYPE,/76/ MTK_PULL_PUPD_R1R0_TYPE,/77/
	1140	MTK_PULL_PUPD_R1R0_TYPE,/78/ MTK_PULL_PUPD_R1R0_TYPE,/79/
	1141	MTK_PULL_PUPD_R1R0_TYPE,/80/ MTK_PULL_PUPD_R1R0_TYPE,/81/
	1142	MTK_PULL_PUPD_R1R0_TYPE,/82/ MTK_PULL_PU_PD_TYPE,/83/
	1143	MTK_PULL_PUPD_R1R0_TYPE,/84/ MTK_PULL_PUPD_R1R0_TYPE,/85/
	1144	MTK_PULL_PUPD_R1R0_TYPE,/86/ MTK_PULL_PUPD_R1R0_TYPE,/87/
	1145	MTK_PULL_PUPD_R1R0_TYPE,/88/ MTK_PULL_PUPD_R1R0_TYPE,/89/
	1146	MTK_PULL_PU_PD_TYPE,/90/ MTK_PULL_PU_PD_TYPE,/91/
	1147	MTK_PULL_PU_PD_TYPE,/92/ MTK_PULL_PU_PD_TYPE,/93/
	1148	MTK_PULL_PU_PD_TYPE,/94/ MTK_PULL_PU_PD_TYPE,/95/
	1149	MTK_PULL_PU_PD_TYPE,/96/ MTK_PULL_PU_PD_TYPE,/97/
	1150	MTK_PULL_PU_PD_TYPE,/98/ MTK_PULL_PU_PD_TYPE,/99/
	1151	MTK_PULL_PU_PD_TYPE,/100/ MTK_PULL_PU_PD_TYPE,/101/
	1152	MTK_PULL_PU_PD_TYPE,/102/ MTK_PULL_PU_PD_TYPE,/103/
	1153	MTK_PULL_PU_PD_TYPE,/104/ MTK_PULL_PU_PD_TYPE,/105/
	1154	MTK_PULL_PU_PD_TYPE,/106/ MTK_PULL_PU_PD_TYPE,/107/
	1155	MTK_PULL_PU_PD_TYPE,/108/ MTK_PULL_PU_PD_TYPE,/109/
	1156	MTK_PULL_PU_PD_TYPE,/110/ MTK_PULL_PU_PD_TYPE,/111/
	1157	MTK_PULL_PU_PD_TYPE,/112/ MTK_PULL_PU_PD_TYPE,/113/
	1158	MTK_PULL_PU_PD_TYPE,/114/ MTK_PULL_PU_PD_TYPE,/115/
	1159	MTK_PULL_PU_PD_TYPE,/116/ MTK_PULL_PU_PD_TYPE,/117/
	1160	MTK_PULL_PU_PD_TYPE,/118/ MTK_PULL_PU_PD_TYPE,/119/
	1161	MTK_PULL_PU_PD_TYPE,/120/ MTK_PULL_PU_PD_TYPE,/121/
	1162	MTK_PULL_PU_PD_TYPE,/122/ MTK_PULL_PU_PD_TYPE,/123/
	1163	MTK_PULL_PU_PD_TYPE,/124/ MTK_PULL_PU_PD_TYPE,/125/
	1164	MTK_PULL_PU_PD_TYPE,/126/ MTK_PULL_PU_PD_RSEL_TYPE,/127/
	1165	MTK_PULL_PU_PD_RSEL_TYPE,/128/ MTK_PULL_PU_PD_RSEL_TYPE,/129/
	1166	MTK_PULL_PU_PD_RSEL_TYPE,/130/ MTK_PULL_PU_PD_RSEL_TYPE,/131/
	1167	MTK_PULL_PU_PD_RSEL_TYPE,/132/ MTK_PULL_PU_PD_RSEL_TYPE,/133/
	1168	MTK_PULL_PU_PD_RSEL_TYPE,/134/ MTK_PULL_PU_PD_RSEL_TYPE,/135/
	1169	MTK_PULL_PU_PD_RSEL_TYPE,/136/ MTK_PULL_PU_PD_RSEL_TYPE,/137/
	1170	MTK_PULL_PU_PD_RSEL_TYPE,/138/ MTK_PULL_PU_PD_RSEL_TYPE,/139/
	1171	MTK_PULL_PU_PD_RSEL_TYPE,/140/ MTK_PULL_PU_PD_RSEL_TYPE,/141/
	1172	MTK_PULL_PU_PD_RSEL_TYPE,/142/ MTK_PULL_PU_PD_RSEL_TYPE,/143/
	1173	MTK_PULL_PU_PD_RSEL_TYPE,/144/ MTK_PULL_PU_PD_RSEL_TYPE,/145/
	1174	MTK_PULL_PU_PD_RSEL_TYPE,/146/ MTK_PULL_PU_PD_TYPE,/147/
	1175	MTK_PULL_PU_PD_TYPE,/148/ MTK_PULL_PU_PD_TYPE,/149/
	1176	MTK_PULL_PU_PD_TYPE,/150/ MTK_PULL_PU_PD_TYPE,/151/
	1177	MTK_PULL_PU_PD_TYPE,/152/ MTK_PULL_PU_PD_TYPE,/153/
	1178	MTK_PULL_PU_PD_TYPE,/154/ MTK_PULL_PU_PD_TYPE,/155/
	1179	MTK_PULL_PU_PD_TYPE,/156/ MTK_PULL_PU_PD_TYPE,/157/
	1180	MTK_PULL_PU_PD_TYPE,/158/ MTK_PULL_PU_PD_TYPE,/159/
	1181	MTK_PULL_PU_PD_TYPE,/160/ MTK_PULL_PU_PD_TYPE,/161/
	1182	MTK_PULL_PU_PD_TYPE,/162/ MTK_PULL_PU_PD_TYPE,/163/
	1183	MTK_PULL_PU_PD_TYPE,/164/ MTK_PULL_PU_PD_TYPE,/165/
	1184	MTK_PULL_PU_PD_TYPE,/166/ MTK_PULL_PU_PD_TYPE,/167/
	1185	MTK_PULL_PU_PD_TYPE,/168/ MTK_PULL_PU_PD_TYPE,/169/
	1186	MTK_PULL_PU_PD_TYPE,/170/ MTK_PULL_PU_PD_TYPE,/171/
	1187	MTK_PULL_PU_PD_TYPE,/172/ MTK_PULL_PU_PD_TYPE,/173/
	1188	MTK_PULL_PU_PD_TYPE,/174/ MTK_PULL_PU_PD_TYPE,/175/
	1189	MTK_PULL_PU_PD_TYPE,/176/ MTK_PULL_PU_PD_TYPE,/177/
	1190	MTK_PULL_PU_PD_TYPE,/178/ MTK_PULL_PU_PD_TYPE,/179/
	1191	MTK_PULL_PU_PD_TYPE,/180/ MTK_PULL_PU_PD_TYPE,/181/
	1192	MTK_PULL_PU_PD_TYPE,/182/ MTK_PULL_PU_PD_TYPE,/183/
	1193	MTK_PULL_PU_PD_TYPE,/184/
	1194	};
	1195
	1196	static const struct mtk_pin_reg_calc mt8186_reg_cals[PINCTRL_PIN_REG_MAX] = {
	1197	[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8186_pin_mode_range),
	1198	[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8186_pin_dir_range),
	1199	[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8186_pin_di_range),
	1200	[PINCTRL_PIN_REG_DO] = MTK_RANGE(mt8186_pin_do_range),
	1201	[PINCTRL_PIN_REG_SR] = MTK_RANGE(mt8186_pin_dir_range),
	1202	[PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt8186_pin_smt_range),
	1203	[PINCTRL_PIN_REG_IES] = MTK_RANGE(mt8186_pin_ies_range),
	1204	[PINCTRL_PIN_REG_PU] = MTK_RANGE(mt8186_pin_pu_range),
	1205	[PINCTRL_PIN_REG_PD] = MTK_RANGE(mt8186_pin_pd_range),
	1206	[PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt8186_pin_drv_range),
	1207	[PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt8186_pin_pupd_range),
	1208	[PINCTRL_PIN_REG_R0] = MTK_RANGE(mt8186_pin_r0_range),
	1209	[PINCTRL_PIN_REG_R1] = MTK_RANGE(mt8186_pin_r1_range),
	1210	[PINCTRL_PIN_REG_DRV_ADV] = MTK_RANGE(mt8186_pin_drv_adv_range),
	1211	[PINCTRL_PIN_REG_RSEL] = MTK_RANGE(mt8186_pin_rsel_range),
	1212
	1213	};
	1214
	1215	static const char * const mt8186_pinctrl_register_base_names[] = {
	1216	"iocfg0", "iocfg_lt", "iocfg_lm", "iocfg_lb", "iocfg_bl",
	1217	"iocfg_rb", "iocfg_rt",
	1218	};
	1219
	1220	static const struct mtk_eint_hw mt8186_eint_hw = {
	1221	.port_mask = 0xf,
	1222	.ports = 7,
	1223	.ap_num = 217,
	1224	.db_cnt = 32,
	1225	};
	1226
	1227	static const struct mtk_pin_soc mt8186_data = {
	1228	.reg_cal = mt8186_reg_cals,
	1229	.pins = mtk_pins_mt8186,
	1230	.npins = ARRAY_SIZE(mtk_pins_mt8186),
	1231	.ngrps = ARRAY_SIZE(mtk_pins_mt8186),
	1232	.nfuncs = 8,
	1233	.gpio_m = 0,
	1234	.eint_hw = &mt8186_eint_hw,
	1235	.base_names = mt8186_pinctrl_register_base_names,
	1236	.nbase_names = ARRAY_SIZE(mt8186_pinctrl_register_base_names),
	1237	.pull_type = mt8186_pull_type,
	1238	.pin_rsel = mt8186_pin_rsel_val_range,
	1239	.npin_rsel = ARRAY_SIZE(mt8186_pin_rsel_val_range),
	1240	.bias_set_combo = mtk_pinconf_bias_set_combo,
	1241	.bias_get_combo = mtk_pinconf_bias_get_combo,
	1242	.drive_set = mtk_pinconf_drive_set_rev1,
	1243	.drive_get = mtk_pinconf_drive_get_rev1,
	1244	.adv_drive_get = mtk_pinconf_adv_drive_get_raw,
	1245	.adv_drive_set = mtk_pinconf_adv_drive_set_raw,
	1246	};
	1247
	1248	static const struct of_device_id mt8186_pinctrl_of_match[] = {
	1249	{ .compatible = "mediatek,mt8186-pinctrl", .data = &mt8186_data },
	1250	{ }
	1251	};
	1252
	1253	static struct platform_driver mt8186_pinctrl_driver = {
	1254	.driver = {
	1255	.name = "mt8186-pinctrl",
	1256	.of_match_table = mt8186_pinctrl_of_match,
	1257	.pm = &mtk_paris_pinctrl_pm_ops,
	1258	},
	1259	.probe = mtk_paris_pinctrl_probe,
	1260	};
	1261
	1262	static int __init mt8186_pinctrl_init(void)
	1263	{
	1264	return platform_driver_register(&mt8186_pinctrl_driver);
	1265	}
	1266
	1267	arch_initcall(mt8186_pinctrl_init);

drivers/pinctrl/mediatek/pinctrl-mt8192.c+2−7

 };
 static const struct of_device_id mt8192_pinctrl_of_match[] = {
-	{ .compatible = "mediatek,mt8192-pinctrl", },
+	{ .compatible = "mediatek,mt8192-pinctrl", .data = &mt8192_data },
 	{ }
 };
-static int mt8192_pinctrl_probe(struct platform_device *pdev)
-{
-	return mtk_paris_pinctrl_probe(pdev, &mt8192_data);
-}
 static struct platform_driver mt8192_pinctrl_driver = {
 	.driver = {
 		.name = "mt8192-pinctrl",
 		.of_match_table = mt8192_pinctrl_of_match,
 		.pm = &mtk_paris_pinctrl_pm_ops,
 	},
-	.probe = mt8192_pinctrl_probe,
+	.probe = mtk_paris_pinctrl_probe,
 };
 static int __init mt8192_pinctrl_init(void)

drivers/pinctrl/mediatek/pinctrl-mt8195.c+2−7

 };
 static const struct of_device_id mt8195_pinctrl_of_match[] = {
-	{ .compatible = "mediatek,mt8195-pinctrl", },
+	{ .compatible = "mediatek,mt8195-pinctrl", .data = &mt8195_data },
 	{ }
 };
-static int mt8195_pinctrl_probe(struct platform_device *pdev)
-{
-	return mtk_paris_pinctrl_probe(pdev, &mt8195_data);
-}
 static struct platform_driver mt8195_pinctrl_driver = {
 	.driver = {
 		.name = "mt8195-pinctrl",
 		.of_match_table = mt8195_pinctrl_of_match,
 		.pm = &mtk_paris_pinctrl_pm_ops,
 	},
-	.probe = mt8195_pinctrl_probe,
+	.probe = mtk_paris_pinctrl_probe,
 };
 static int __init mt8195_pinctrl_init(void)

drivers/pinctrl/mediatek/pinctrl-mt8365.c+10−30

 	MTK_PIN_IES_SMT_SPEC(144, 144, 0x480, 22),
 };
-static int mt8365_spec_pull_set(struct regmap *regmap, unsigned int pin,
-			unsigned char align, bool isup, unsigned int r1r0)
-{
-	return mtk_pctrl_spec_pull_set_samereg(regmap, mt8365_spec_pupd,
-		ARRAY_SIZE(mt8365_spec_pupd), pin, align, isup, r1r0);
-}
-static int mt8365_ies_smt_set(struct regmap *regmap, unsigned int pin,
-		unsigned char align, int value, enum pin_config_param arg)
-{
-	if (arg == PIN_CONFIG_INPUT_ENABLE)
-		return mtk_pconf_spec_set_ies_smt_range(regmap, mt8365_ies_set,
-			ARRAY_SIZE(mt8365_ies_set), pin, align, value);
-	else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
-		return mtk_pconf_spec_set_ies_smt_range(regmap, mt8365_smt_set,
-			ARRAY_SIZE(mt8365_smt_set), pin, align, value);
-	return -EINVAL;
-}
 static const struct mtk_pinctrl_devdata mt8365_pinctrl_data = {
 	.pins = mtk_pins_mt8365,
 	.npins = ARRAY_SIZE(mtk_pins_mt8365),
 	.n_grp_cls = ARRAY_SIZE(mt8365_drv_grp),
 	.pin_drv_grp = mt8365_pin_drv,
 	.n_pin_drv_grps = ARRAY_SIZE(mt8365_pin_drv),
-	.spec_pull_set = mt8365_spec_pull_set,
+	.spec_ies = mt8365_ies_set,
-	.spec_ies_smt_set = mt8365_ies_smt_set,
+	.n_spec_ies = ARRAY_SIZE(mt8365_ies_set),
+	.spec_smt = mt8365_smt_set,
+	.n_spec_smt = ARRAY_SIZE(mt8365_smt_set),
+	.spec_pupd = mt8365_spec_pupd,
+	.n_spec_pupd = ARRAY_SIZE(mt8365_spec_pupd),
+	.spec_pull_set = mtk_pctrl_spec_pull_set_samereg,
+	.spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range,
 	.dir_offset = 0x0140,
 	.dout_offset = 0x00A0,
 	.din_offset = 0x0000,
 	},
 };
-static int mtk_pinctrl_probe(struct platform_device *pdev)
-{
-	return mtk_pctrl_init(pdev, &mt8365_pinctrl_data, NULL);
-}
 static const struct of_device_id mt8365_pctrl_match[] = {
-	{
+	{ .compatible = "mediatek,mt8365-pinctrl", .data = &mt8365_pinctrl_data },
-		.compatible = "mediatek,mt8365-pinctrl",
-	},
 	{}
 };
 static struct platform_driver mtk_pinctrl_driver = {
-	.probe = mtk_pinctrl_probe,
+	.probe = mtk_pctrl_common_probe,
 	.driver = {
 		.name = "mediatek-mt8365-pinctrl",
 		.of_match_table = mt8365_pctrl_match,

drivers/pinctrl/mediatek/pinctrl-mt8516.c+10−30

 	MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 2, 1, 0),
 };
-static int mt8516_spec_pull_set(struct regmap *regmap, unsigned int pin,
-			unsigned char align, bool isup, unsigned int r1r0)
-{
-	return mtk_pctrl_spec_pull_set_samereg(regmap, mt8516_spec_pupd,
-		ARRAY_SIZE(mt8516_spec_pupd), pin, align, isup, r1r0);
-}
 static const struct mtk_pin_ies_smt_set mt8516_ies_set[] = {
 	MTK_PIN_IES_SMT_SPEC(0, 6, 0x900, 2),
 	MTK_PIN_IES_SMT_SPEC(7, 10, 0x900, 3),
 	MTK_PIN_IES_SMT_SPEC(121, 124, 0xA10, 9),
 };
-static int mt8516_ies_smt_set(struct regmap *regmap, unsigned int pin,
-		unsigned char align, int value, enum pin_config_param arg)
-{
-	if (arg == PIN_CONFIG_INPUT_ENABLE)
-		return mtk_pconf_spec_set_ies_smt_range(regmap, mt8516_ies_set,
-			ARRAY_SIZE(mt8516_ies_set), pin, align, value);
-	else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
-		return mtk_pconf_spec_set_ies_smt_range(regmap, mt8516_smt_set,
-			ARRAY_SIZE(mt8516_smt_set), pin, align, value);
-	return -EINVAL;
-}
 static const struct mtk_pinctrl_devdata mt8516_pinctrl_data = {
 	.pins = mtk_pins_mt8516,
 	.npins = ARRAY_SIZE(mtk_pins_mt8516),
 	.n_grp_cls = ARRAY_SIZE(mt8516_drv_grp),
 	.pin_drv_grp = mt8516_pin_drv,
 	.n_pin_drv_grps = ARRAY_SIZE(mt8516_pin_drv),
-	.spec_pull_set = mt8516_spec_pull_set,
+	.spec_ies = mt8516_ies_set,
-	.spec_ies_smt_set = mt8516_ies_smt_set,
+	.n_spec_ies = ARRAY_SIZE(mt8516_ies_set),
+	.spec_pupd = mt8516_spec_pupd,
+	.n_spec_pupd = ARRAY_SIZE(mt8516_spec_pupd),
+	.spec_smt = mt8516_smt_set,
+	.n_spec_smt = ARRAY_SIZE(mt8516_smt_set),
+	.spec_pull_set = mtk_pctrl_spec_pull_set_samereg,
+	.spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range,
 	.dir_offset = 0x0000,
 	.pullen_offset = 0x0500,
 	.pullsel_offset = 0x0600,
 	},
 };
-static int mt8516_pinctrl_probe(struct platform_device *pdev)
-{
-	return mtk_pctrl_init(pdev, &mt8516_pinctrl_data, NULL);
-}
 static const struct of_device_id mt8516_pctrl_match[] = {
-	{
+	{ .compatible = "mediatek,mt8516-pinctrl", .data = &mt8516_pinctrl_data },
-		.compatible = "mediatek,mt8516-pinctrl",
-	},
 	{}
 };
 MODULE_DEVICE_TABLE(of, mt8516_pctrl_match);
 static struct platform_driver mtk_pinctrl_driver = {
-	.probe = mt8516_pinctrl_probe,
+	.probe = mtk_pctrl_common_probe,
 	.driver = {
 		.name = "mediatek-mt8516-pinctrl",
 		.of_match_table = mt8516_pctrl_match,

drivers/pinctrl/mediatek/pinctrl-mtk-common.c+59−29

 	 */
 	if (pctl->devdata->spec_ies_smt_set) {
 		return pctl->devdata->spec_ies_smt_set(mtk_get_regmap(pctl, pin),
-			pin, pctl->devdata->port_align, value, arg);
+			pctl->devdata, pin, value, arg);
 	}
 	if (arg == PIN_CONFIG_INPUT_ENABLE)
 }
 int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap,
-		const struct mtk_pin_ies_smt_set *ies_smt_infos, unsigned int info_num,
+		const struct mtk_pinctrl_devdata *devdata,
-		unsigned int pin, unsigned char align, int value)
+		unsigned int pin, int value, enum pin_config_param arg)
 {
-	unsigned int i, reg_addr, bit;
+	const struct mtk_pin_ies_smt_set *ies_smt_infos = NULL;
+	unsigned int i, info_num, reg_addr, bit;
+	switch (arg) {
+	case PIN_CONFIG_INPUT_ENABLE:
+		ies_smt_infos = devdata->spec_ies;
+		info_num = devdata->n_spec_ies;
+		break;
+	case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+		ies_smt_infos = devdata->spec_smt;
+		info_num = devdata->n_spec_smt;
+		break;
+	default:
+		break;
+	}
+	if (!ies_smt_infos)
+		return -EINVAL;
 	for (i = 0; i < info_num; i++) {
 		if (pin >= ies_smt_infos[i].start &&
 		return -EINVAL;
 	if (value)
-		reg_addr = ies_smt_infos[i].offset + align;
+		reg_addr = ies_smt_infos[i].offset + devdata->port_align;
 	else
-		reg_addr = ies_smt_infos[i].offset + (align << 1);
+		reg_addr = ies_smt_infos[i].offset + (devdata->port_align << 1);
 	bit = BIT(ies_smt_infos[i].bit);
 	regmap_write(regmap, reg_addr, bit);
 }
 int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap,
-		const struct mtk_pin_spec_pupd_set_samereg *pupd_infos,
+		const struct mtk_pinctrl_devdata *devdata,
-		unsigned int info_num, unsigned int pin,
+		unsigned int pin, bool isup, unsigned int r1r0)
-		unsigned char align, bool isup, unsigned int r1r0)
 {
 	unsigned int i;
 	unsigned int reg_pupd, reg_set, reg_rst;
 	const struct mtk_pin_spec_pupd_set_samereg *spec_pupd_pin;
 	bool find = false;
-	for (i = 0; i < info_num; i++) {
+	if (!devdata->spec_pupd)
-		if (pin == pupd_infos[i].pin) {
+		return -EINVAL;
+	for (i = 0; i < devdata->n_spec_pupd; i++) {
+		if (pin == devdata->spec_pupd[i].pin) {
 			find = true;
 			break;
 		}
 	if (!find)
 		return -EINVAL;
-	spec_pupd_pin = pupd_infos + i;
+	spec_pupd_pin = devdata->spec_pupd + i;
-	reg_set = spec_pupd_pin->offset + align;
+	reg_set = spec_pupd_pin->offset + devdata->port_align;
-	reg_rst = spec_pupd_pin->offset + (align << 1);
+	reg_rst = spec_pupd_pin->offset + (devdata->port_align << 1);
 	if (isup)
 		reg_pupd = reg_rst;
 		 */
 		r1r0 = enable ? arg : MTK_PUPD_SET_R1R0_00;
 		ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl, pin),
-			pin, pctl->devdata->port_align, isup, r1r0);
+						   pctl->devdata, pin, isup,
+						   r1r0);
 		if (!ret)
 			return 0;
 	}
 	return mtk_eint_do_init(pctl->eint);
 }
+/* This is used as a common probe function */
 int mtk_pctrl_init(struct platform_device *pdev,
 		const struct mtk_pinctrl_devdata *data,
 		struct regmap *regmap)
 {
+	struct device *dev = &pdev->dev;
 	struct pinctrl_pin_desc *pins;
 	struct mtk_pinctrl *pctl;
 	struct device_node *np = pdev->dev.of_node, *node;
 	platform_set_drvdata(pdev, pctl);
 	prop = of_find_property(np, "pins-are-numbered", NULL);
-	if (!prop) {
+	if (!prop)
-		dev_err(&pdev->dev, "only support pins-are-numbered format\n");
+		return dev_err_probe(dev, -EINVAL,
-		return -EINVAL;
+				     "only support pins-are-numbered format\n");
-	}
 	node = of_parse_phandle(np, "mediatek,pctl-regmap", 0);
 	if (node) {
 		pctl->regmap1 = syscon_node_to_regmap(node);
+		of_node_put(node);
 		if (IS_ERR(pctl->regmap1))
 			return PTR_ERR(pctl->regmap1);
 	} else if (regmap) {
 		pctl->regmap1  = regmap;
 	} else {
-		dev_err(&pdev->dev, "Pinctrl node has not register regmap.\n");
+		return dev_err_probe(dev, -EINVAL, "Cannot find pinctrl regmap.\n");
-		return -EINVAL;
 	}
 	/* Only 8135 has two base addr, other SoCs have only one. */
 	node = of_parse_phandle(np, "mediatek,pctl-regmap", 1);
 	if (node) {
 		pctl->regmap2 = syscon_node_to_regmap(node);
+		of_node_put(node);
 		if (IS_ERR(pctl->regmap2))
 			return PTR_ERR(pctl->regmap2);
 	}
 	pctl->devdata = data;
 	ret = mtk_pctrl_build_state(pdev);
-	if (ret) {
+	if (ret)
-		dev_err(&pdev->dev, "build state failed: %d\n", ret);
+		return dev_err_probe(dev, ret, "build state failed\n");
-		return -EINVAL;
-	}
 	pins = devm_kcalloc(&pdev->dev, pctl->devdata->npins, sizeof(*pins),
 			    GFP_KERNEL);
 	pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc,
 					       pctl);
-	if (IS_ERR(pctl->pctl_dev)) {
+	if (IS_ERR(pctl->pctl_dev))
-		dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
+		return dev_err_probe(dev, PTR_ERR(pctl->pctl_dev),
-		return PTR_ERR(pctl->pctl_dev);
+				     "Couldn't register pinctrl driver\n");
-	}
 	pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
 	if (!pctl->chip)
 	gpiochip_remove(pctl->chip);
 	return ret;
 }
+int mtk_pctrl_common_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	const struct mtk_pinctrl_devdata *data = device_get_match_data(dev);
+	if (!data)
+		return -ENODEV;
+	return mtk_pctrl_init(pdev, data, NULL);
+}

drivers/pinctrl/mediatek/pinctrl-mtk-common.h+24−9

  *
  * @grp_desc: The driving group info.
  * @pin_drv_grp: The driving group for all pins.
+ * @spec_ies: Special pin setting for input enable
+ * @n_spec_ies: Number of entries in spec_ies
+ * @spec_pupd: Special pull up/down setting
+ * @n_spec_pupd: Number of entries in spec_pupd
+ * @spec_smt: Special pin setting for schmitt
+ * @n_spec_smt: Number of entries in spec_smt
  * @spec_pull_set: Each SoC may have special pins for pull up/down setting,
  *  these pins' pull setting are very different, they have separate pull
  *  up/down bit, R0 and R1 resistor bit, so they need special pull setting.
 	unsigned int	n_grp_cls;
 	const struct mtk_pin_drv_grp	*pin_drv_grp;
 	unsigned int	n_pin_drv_grps;
-	int (*spec_pull_set)(struct regmap *reg, unsigned int pin,
+	const struct mtk_pin_ies_smt_set *spec_ies;
-			unsigned char align, bool isup, unsigned int arg);
+	unsigned int n_spec_ies;
-	int (*spec_ies_smt_set)(struct regmap *reg, unsigned int pin,
+	const struct mtk_pin_spec_pupd_set_samereg *spec_pupd;
-			unsigned char align, int value, enum pin_config_param arg);
+	unsigned int n_spec_pupd;
+	const struct mtk_pin_ies_smt_set *spec_smt;
+	unsigned int n_spec_smt;
+	int (*spec_pull_set)(struct regmap *regmap,
+			const struct mtk_pinctrl_devdata *devdata,
+			unsigned int pin, bool isup, unsigned int r1r0);
+	int (*spec_ies_smt_set)(struct regmap *reg,
+			const struct mtk_pinctrl_devdata *devdata,
+			unsigned int pin, int value, enum pin_config_param arg);
 	void (*spec_pinmux_set)(struct regmap *reg, unsigned int pin,
 			unsigned int mode);
 	void (*spec_dir_set)(unsigned int *reg_addr, unsigned int pin);
 		const struct mtk_pinctrl_devdata *data,
 		struct regmap *regmap);
+int mtk_pctrl_common_probe(struct platform_device *pdev);
 int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap,
-		const struct mtk_pin_spec_pupd_set_samereg *pupd_infos,
+		const struct mtk_pinctrl_devdata *devdata,
-		unsigned int info_num, unsigned int pin,
+		unsigned int pin, bool isup, unsigned int r1r0);
-		unsigned char align, bool isup, unsigned int r1r0);
 int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap,
-		const struct mtk_pin_ies_smt_set *ies_smt_infos, unsigned int info_num,
+		const struct mtk_pinctrl_devdata *devdata,
-		unsigned int pin, unsigned char align, int value);
+		unsigned int pin, int value, enum pin_config_param arg);
 extern const struct dev_pm_ops mtk_eint_pm_ops;

drivers/pinctrl/mediatek/pinctrl-mtk-mt8186.h+2186−0

@@ -0,0 +1,2186 @@
	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	/*
	3	* Copyright (C) 2021 MediaTek Inc.
	4	*
	5	* Author: Guodong Liu <guodong.liu@mediatek.com>
	6	*
	7	*/
	8
	9	#ifndef __PINCTRL_MTK_MT8186_H
	10	#define __PINCTRL_MTK_MT8186_H
	11
	12	#include "pinctrl-paris.h"
	13
	14	static const struct mtk_pin_desc mtk_pins_mt8186[] = {
	15	MTK_PIN(
	16	0, "GPIO0",
	17	MTK_EINT_FUNCTION(0, 0),
	18	DRV_GRP4,
	19	MTK_FUNCTION(0, "GPIO0"),
	20	MTK_FUNCTION(1, "I2S0_MCK"),
	21	MTK_FUNCTION(2, "SPI0_CLK_B"),
	22	MTK_FUNCTION(3, "I2S2_MCK"),
	23	MTK_FUNCTION(4, "CMFLASH0"),
	24	MTK_FUNCTION(5, "SCP_SPI0_CK"),
	25	MTK_FUNCTION(6, "TP_GPIO0_AO"),
	26	MTK_FUNCTION(7, "dbg_mon_a0")
	27	),
	28
	29	MTK_PIN(
	30	1, "GPIO1",
	31	MTK_EINT_FUNCTION(0, 1),
	32	DRV_GRP4,
	33	MTK_FUNCTION(0, "GPIO1"),
	34	MTK_FUNCTION(1, "I2S0_BCK"),
	35	MTK_FUNCTION(2, "SPI0_CSB_B"),
	36	MTK_FUNCTION(3, "I2S2_BCK"),
	37	MTK_FUNCTION(4, "CMFLASH1"),
	38	MTK_FUNCTION(5, "SCP_SPI0_CS"),
	39	MTK_FUNCTION(6, "TP_GPIO1_AO")
	40	),
	41
	42	MTK_PIN(
	43	2, "GPIO2",
	44	MTK_EINT_FUNCTION(0, 2),
	45	DRV_GRP4,
	46	MTK_FUNCTION(0, "GPIO2"),
	47	MTK_FUNCTION(1, "I2S0_LRCK"),
	48	MTK_FUNCTION(2, "SPI0_MO_B"),
	49	MTK_FUNCTION(3, "I2S2_LRCK"),
	50	MTK_FUNCTION(4, "CMFLASH2"),
	51	MTK_FUNCTION(5, "SCP_SPI0_MO"),
	52	MTK_FUNCTION(6, "TP_GPIO2_AO")
	53	),
	54
	55	MTK_PIN(
	56	3, "GPIO3",
	57	MTK_EINT_FUNCTION(0, 3),
	58	DRV_GRP4,
	59	MTK_FUNCTION(0, "GPIO3"),
	60	MTK_FUNCTION(1, "I2S0_DI"),
	61	MTK_FUNCTION(2, "SPI0_MI_B"),
	62	MTK_FUNCTION(3, "I2S2_DI"),
	63	MTK_FUNCTION(4, "SRCLKENAI1"),
	64	MTK_FUNCTION(5, "SCP_SPI0_MI"),
	65	MTK_FUNCTION(6, "TP_GPIO3_AO")
	66	),
	67
	68	MTK_PIN(
	69	4, "GPIO4",
	70	MTK_EINT_FUNCTION(0, 4),
	71	DRV_GRP4,
	72	MTK_FUNCTION(0, "GPIO4"),
	73	MTK_FUNCTION(1, "I2S3_DO"),
	74	MTK_FUNCTION(3, "I2S1_DO"),
	75	MTK_FUNCTION(6, "TP_GPIO4_AO")
	76	),
	77
	78	MTK_PIN(
	79	5, "GPIO5",
	80	MTK_EINT_FUNCTION(0, 5),
	81	DRV_GRP4,
	82	MTK_FUNCTION(0, "GPIO5"),
	83	MTK_FUNCTION(1, "EXT_FRAME_SYNC"),
	84	MTK_FUNCTION(6, "TP_GPIO5_AO")
	85	),
	86
	87	MTK_PIN(
	88	6, "GPIO6",
	89	MTK_EINT_FUNCTION(0, 6),
	90	DRV_GRP4,
	91	MTK_FUNCTION(0, "GPIO6"),
	92	MTK_FUNCTION(1, "I2S3_MCK"),
	93	MTK_FUNCTION(2, "SPI1_CLK_B"),
	94	MTK_FUNCTION(3, "I2S1_MCK"),
	95	MTK_FUNCTION(4, "DPI_DATA22"),
	96	MTK_FUNCTION(6, "TP_GPIO6_AO")
	97	),
	98
	99	MTK_PIN(
	100	7, "GPIO7",
	101	MTK_EINT_FUNCTION(0, 7),
	102	DRV_GRP4,
	103	MTK_FUNCTION(0, "GPIO7"),
	104	MTK_FUNCTION(1, "I2S3_BCK"),
	105	MTK_FUNCTION(2, "SPI1_CSB_B"),
	106	MTK_FUNCTION(3, "I2S1_BCK"),
	107	MTK_FUNCTION(4, "DPI_DATA23"),
	108	MTK_FUNCTION(6, "TP_GPIO7_AO")
	109	),
	110
	111	MTK_PIN(
	112	8, "GPIO8",
	113	MTK_EINT_FUNCTION(0, 8),
	114	DRV_GRP4,
	115	MTK_FUNCTION(0, "GPIO8"),
	116	MTK_FUNCTION(1, "I2S3_LRCK"),
	117	MTK_FUNCTION(2, "SPI1_MO_B"),
	118	MTK_FUNCTION(3, "I2S1_LRCK"),
	119	MTK_FUNCTION(4, "CONN_UART0_RXD"),
	120	MTK_FUNCTION(5, "SSPM_URXD_AO"),
	121	MTK_FUNCTION(6, "ADSP_UART_RX"),
	122	MTK_FUNCTION(7, "CONN_MCU_DBGACK_N")
	123	),
	124
	125	MTK_PIN(
	126	9, "GPIO9",
	127	MTK_EINT_FUNCTION(0, 9),
	128	DRV_GRP4,
	129	MTK_FUNCTION(0, "GPIO9"),
	130	MTK_FUNCTION(1, "I2S3_DO"),
	131	MTK_FUNCTION(2, "SPI1_MI_B"),
	132	MTK_FUNCTION(3, "I2S1_DO"),
	133	MTK_FUNCTION(4, "CONN_UART0_TXD"),
	134	MTK_FUNCTION(5, "SSPM_UTXD_AO"),
	135	MTK_FUNCTION(6, "ADSP_UART_TX"),
	136	MTK_FUNCTION(7, "CONN_MCU_DBGI_N")
	137	),
	138
	139	MTK_PIN(
	140	10, "GPIO10",
	141	MTK_EINT_FUNCTION(0, 10),
	142	DRV_GRP4,
	143	MTK_FUNCTION(0, "GPIO10"),
	144	MTK_FUNCTION(1, "I2S0_MCK"),
	145	MTK_FUNCTION(2, "SPI4_CLK_A"),
	146	MTK_FUNCTION(3, "I2S2_MCK"),
	147	MTK_FUNCTION(4, "SPM_JTAG_TDI"),
	148	MTK_FUNCTION(5, "SCP_JTAG_TDI"),
	149	MTK_FUNCTION(6, "ADSP_JTAG_TDI"),
	150	MTK_FUNCTION(7, "CONN_MCU_TDI")
	151	),
	152
	153	MTK_PIN(
	154	11, "GPIO11",
	155	MTK_EINT_FUNCTION(0, 11),
	156	DRV_GRP4,
	157	MTK_FUNCTION(0, "GPIO11"),
	158	MTK_FUNCTION(1, "I2S0_BCK"),
	159	MTK_FUNCTION(2, "SPI4_CSB_A"),
	160	MTK_FUNCTION(3, "I2S2_BCK"),
	161	MTK_FUNCTION(4, "SPM_JTAG_TRSTN"),
	162	MTK_FUNCTION(5, "SCP_JTAG_TRSTN"),
	163	MTK_FUNCTION(6, "ADSP_JTAG_TRSTN"),
	164	MTK_FUNCTION(7, "CONN_MCU_TRST_B")
	165	),
	166
	167	MTK_PIN(
	168	12, "GPIO12",
	169	MTK_EINT_FUNCTION(0, 12),
	170	DRV_GRP4,
	171	MTK_FUNCTION(0, "GPIO12"),
	172	MTK_FUNCTION(1, "I2S0_LRCK"),
	173	MTK_FUNCTION(2, "SPI4_MO_A"),
	174	MTK_FUNCTION(3, "I2S2_LRCK"),
	175	MTK_FUNCTION(4, "SPM_JTAG_TCK"),
	176	MTK_FUNCTION(5, "SCP_JTAG_TCK"),
	177	MTK_FUNCTION(6, "ADSP_JTAG_TCK"),
	178	MTK_FUNCTION(7, "CONN_MCU_TCK")
	179	),
	180
	181	MTK_PIN(
	182	13, "GPIO13",
	183	MTK_EINT_FUNCTION(0, 13),
	184	DRV_GRP4,
	185	MTK_FUNCTION(0, "GPIO13"),
	186	MTK_FUNCTION(1, "I2S0_DI"),
	187	MTK_FUNCTION(2, "SPI4_MI_A"),
	188	MTK_FUNCTION(3, "I2S2_DI"),
	189	MTK_FUNCTION(4, "SPM_JTAG_TDO"),
	190	MTK_FUNCTION(5, "SCP_JTAG_TDO"),
	191	MTK_FUNCTION(6, "ADSP_JTAG_TDO"),
	192	MTK_FUNCTION(7, "CONN_MCU_TDO")
	193	),
	194
	195	MTK_PIN(
	196	14, "GPIO14",
	197	MTK_EINT_FUNCTION(0, 14),
	198	DRV_GRP4,
	199	MTK_FUNCTION(0, "GPIO14"),
	200	MTK_FUNCTION(3, "CLKM0"),
	201	MTK_FUNCTION(4, "SPM_JTAG_TMS"),
	202	MTK_FUNCTION(5, "SCP_JTAG_TMS"),
	203	MTK_FUNCTION(6, "ADSP_JTAG_TMS"),
	204	MTK_FUNCTION(7, "CONN_MCU_TMS")
	205	),
	206
	207	MTK_PIN(
	208	15, "GPIO15",
	209	MTK_EINT_FUNCTION(0, 15),
	210	DRV_GRP4,
	211	MTK_FUNCTION(0, "GPIO15"),
	212	MTK_FUNCTION(1, "EXT_FRAME_SYNC"),
	213	MTK_FUNCTION(2, "SRCLKENAI1"),
	214	MTK_FUNCTION(3, "CLKM1"),
	215	MTK_FUNCTION(4, "PWM0")
	216	),
	217
	218	MTK_PIN(
	219	16, "GPIO16",
	220	MTK_EINT_FUNCTION(0, 16),
	221	DRV_GRP4,
	222	MTK_FUNCTION(0, "GPIO16"),
	223	MTK_FUNCTION(1, "CONN_WIFI_TXD"),
	224	MTK_FUNCTION(2, "SRCLKENAI0"),
	225	MTK_FUNCTION(3, "CLKM2"),
	226	MTK_FUNCTION(4, "PWM1")
	227	),
	228
	229	MTK_PIN(
	230	17, "GPIO17",
	231	MTK_EINT_FUNCTION(0, 17),
	232	DRV_GRP4,
	233	MTK_FUNCTION(0, "GPIO17"),
	234	MTK_FUNCTION(3, "CLKM3"),
	235	MTK_FUNCTION(4, "PWM2"),
	236	MTK_FUNCTION(7, "dbg_mon_a32")
	237	),
	238
	239	MTK_PIN(
	240	18, "GPIO18",
	241	MTK_EINT_FUNCTION(0, 18),
	242	DRV_GRP4,
	243	MTK_FUNCTION(0, "GPIO18"),
	244	MTK_FUNCTION(2, "CMVREF0"),
	245	MTK_FUNCTION(6, "SPI2_CLK_B"),
	246	MTK_FUNCTION(7, "dbg_mon_a26")
	247	),
	248
	249	MTK_PIN(
	250	19, "GPIO19",
	251	MTK_EINT_FUNCTION(0, 19),
	252	DRV_GRP4,
	253	MTK_FUNCTION(0, "GPIO19"),
	254	MTK_FUNCTION(2, "CMVREF1"),
	255	MTK_FUNCTION(5, "ANT_SEL3"),
	256	MTK_FUNCTION(6, "SPI2_CSB_B"),
	257	MTK_FUNCTION(7, "dbg_mon_a2")
	258	),
	259
	260	MTK_PIN(
	261	20, "GPIO20",
	262	MTK_EINT_FUNCTION(0, 20),
	263	DRV_GRP4,
	264	MTK_FUNCTION(0, "GPIO20"),
	265	MTK_FUNCTION(2, "CMVREF2"),
	266	MTK_FUNCTION(5, "ANT_SEL4"),
	267	MTK_FUNCTION(6, "SPI2_MO_B"),
	268	MTK_FUNCTION(7, "dbg_mon_a3")
	269	),
	270
	271	MTK_PIN(
	272	21, "GPIO21",
	273	MTK_EINT_FUNCTION(0, 21),
	274	DRV_GRP4,
	275	MTK_FUNCTION(0, "GPIO21"),
	276	MTK_FUNCTION(1, "I2S0_MCK"),
	277	MTK_FUNCTION(2, "I2S1_MCK"),
	278	MTK_FUNCTION(3, "I2S3_MCK"),
	279	MTK_FUNCTION(5, "ANT_SEL5"),
	280	MTK_FUNCTION(6, "SPI2_MI_B"),
	281	MTK_FUNCTION(7, "dbg_mon_a4")
	282	),
	283
	284	MTK_PIN(
	285	22, "GPIO22",
	286	MTK_EINT_FUNCTION(0, 22),
	287	DRV_GRP4,
	288	MTK_FUNCTION(0, "GPIO22"),
	289	MTK_FUNCTION(1, "I2S0_BCK"),
	290	MTK_FUNCTION(2, "I2S1_BCK"),
	291	MTK_FUNCTION(3, "I2S3_BCK"),
	292	MTK_FUNCTION(4, "TDM_RX_LRCK"),
	293	MTK_FUNCTION(5, "ANT_SEL6"),
	294	MTK_FUNCTION(7, "dbg_mon_a5")
	295	),
	296
	297	MTK_PIN(
	298	23, "GPIO23",
	299	MTK_EINT_FUNCTION(0, 23),
	300	DRV_GRP4,
	301	MTK_FUNCTION(0, "GPIO23"),
	302	MTK_FUNCTION(1, "I2S0_LRCK"),
	303	MTK_FUNCTION(2, "I2S1_LRCK"),
	304	MTK_FUNCTION(3, "I2S3_LRCK"),
	305	MTK_FUNCTION(4, "TDM_RX_BCK"),
	306	MTK_FUNCTION(5, "ANT_SEL7"),
	307	MTK_FUNCTION(7, "dbg_mon_a6")
	308	),
	309
	310	MTK_PIN(
	311	24, "GPIO24",
	312	MTK_EINT_FUNCTION(0, 24),
	313	DRV_GRP4,
	314	MTK_FUNCTION(0, "GPIO24"),
	315	MTK_FUNCTION(1, "I2S0_DI"),
	316	MTK_FUNCTION(2, "I2S1_DO"),
	317	MTK_FUNCTION(3, "I2S3_DO"),
	318	MTK_FUNCTION(4, "TDM_RX_MCK"),
	319	MTK_FUNCTION(7, "dbg_mon_a7")
	320	),
	321
	322	MTK_PIN(
	323	25, "GPIO25",
	324	MTK_EINT_FUNCTION(0, 25),
	325	DRV_GRP4,
	326	MTK_FUNCTION(0, "GPIO25"),
	327	MTK_FUNCTION(1, "I2S2_MCK"),
	328	MTK_FUNCTION(2, "PCM_CLK"),
	329	MTK_FUNCTION(3, "SPI4_CLK_B"),
	330	MTK_FUNCTION(4, "TDM_RX_DATA0"),
	331	MTK_FUNCTION(7, "dbg_mon_a8")
	332	),
	333
	334	MTK_PIN(
	335	26, "GPIO26",
	336	MTK_EINT_FUNCTION(0, 26),
	337	DRV_GRP4,
	338	MTK_FUNCTION(0, "GPIO26"),
	339	MTK_FUNCTION(1, "I2S2_BCK"),
	340	MTK_FUNCTION(2, "PCM_SYNC"),
	341	MTK_FUNCTION(3, "SPI4_CSB_B"),
	342	MTK_FUNCTION(4, "TDM_RX_DATA1"),
	343	MTK_FUNCTION(7, "dbg_mon_a9")
	344	),
	345
	346	MTK_PIN(
	347	27, "GPIO27",
	348	MTK_EINT_FUNCTION(0, 27),
	349	DRV_GRP4,
	350	MTK_FUNCTION(0, "GPIO27"),
	351	MTK_FUNCTION(1, "I2S2_LRCK"),
	352	MTK_FUNCTION(2, "PCM_DI"),
	353	MTK_FUNCTION(3, "SPI4_MO_B"),
	354	MTK_FUNCTION(4, "TDM_RX_DATA2"),
	355	MTK_FUNCTION(7, "dbg_mon_a10")
	356	),
	357
	358	MTK_PIN(
	359	28, "GPIO28",
	360	MTK_EINT_FUNCTION(0, 28),
	361	DRV_GRP4,
	362	MTK_FUNCTION(0, "GPIO28"),
	363	MTK_FUNCTION(1, "I2S2_DI"),
	364	MTK_FUNCTION(2, "PCM_DO"),
	365	MTK_FUNCTION(3, "SPI4_MI_B"),
	366	MTK_FUNCTION(4, "TDM_RX_DATA3")
	367	),
	368
	369	MTK_PIN(
	370	29, "GPIO29",
	371	MTK_EINT_FUNCTION(0, 29),
	372	DRV_GRP4,
	373	MTK_FUNCTION(0, "GPIO29"),
	374	MTK_FUNCTION(1, "ANT_SEL0"),
	375	MTK_FUNCTION(2, "GPS_L1_ELNA_EN")
	376	),
	377
	378	MTK_PIN(
	379	30, "GPIO30",
	380	MTK_EINT_FUNCTION(0, 30),
	381	DRV_GRP4,
	382	MTK_FUNCTION(0, "GPIO30"),
	383	MTK_FUNCTION(1, "ANT_SEL1")
	384	),
	385
	386	MTK_PIN(
	387	31, "GPIO31",
	388	MTK_EINT_FUNCTION(0, 31),
	389	DRV_GRP4,
	390	MTK_FUNCTION(0, "GPIO31"),
	391	MTK_FUNCTION(1, "ANT_SEL2"),
	392	MTK_FUNCTION(2, "EXT_FRAME_SYNC"),
	393	MTK_FUNCTION(3, "SRCLKENAI1")
	394	),
	395
	396	MTK_PIN(
	397	32, "GPIO32",
	398	MTK_EINT_FUNCTION(0, 32),
	399	DRV_GRP4,
	400	MTK_FUNCTION(0, "GPIO32"),
	401	MTK_FUNCTION(1, "URXD0"),
	402	MTK_FUNCTION(2, "UTXD0"),
	403	MTK_FUNCTION(3, "ADSP_UART_RX"),
	404	MTK_FUNCTION(4, "TP_URXD1_AO")
	405	),
	406
	407	MTK_PIN(
	408	33, "GPIO33",
	409	MTK_EINT_FUNCTION(0, 33),
	410	DRV_GRP4,
	411	MTK_FUNCTION(0, "GPIO33"),
	412	MTK_FUNCTION(1, "UTXD0"),
	413	MTK_FUNCTION(2, "URXD0"),
	414	MTK_FUNCTION(3, "ADSP_UART_TX"),
	415	MTK_FUNCTION(4, "TP_UTXD1_AO")
	416	),
	417
	418	MTK_PIN(
	419	34, "GPIO34",
	420	MTK_EINT_FUNCTION(0, 34),
	421	DRV_GRP4,
	422	MTK_FUNCTION(0, "GPIO34"),
	423	MTK_FUNCTION(1, "URXD1"),
	424	MTK_FUNCTION(2, "TP_URXD2_AO"),
	425	MTK_FUNCTION(3, "SSPM_URXD_AO"),
	426	MTK_FUNCTION(4, "ADSP_UART_RX"),
	427	MTK_FUNCTION(5, "CONN_UART0_RXD")
	428	),
	429
	430	MTK_PIN(
	431	35, "GPIO35",
	432	MTK_EINT_FUNCTION(0, 35),
	433	DRV_GRP4,
	434	MTK_FUNCTION(0, "GPIO35"),
	435	MTK_FUNCTION(1, "UTXD1"),
	436	MTK_FUNCTION(2, "TP_UTXD2_AO"),
	437	MTK_FUNCTION(3, "SSPM_UTXD_AO"),
	438	MTK_FUNCTION(4, "ADSP_UART_TX"),
	439	MTK_FUNCTION(5, "CONN_UART0_TXD"),
	440	MTK_FUNCTION(6, "CONN_WIFI_TXD")
	441	),
	442
	443	MTK_PIN(
	444	36, "GPIO36",
	445	MTK_EINT_FUNCTION(0, 36),
	446	DRV_GRP4,
	447	MTK_FUNCTION(0, "GPIO36"),
	448	MTK_FUNCTION(1, "SPI0_CLK_A"),
	449	MTK_FUNCTION(2, "CLKM0"),
	450	MTK_FUNCTION(4, "SCP_SPI0_CK"),
	451	MTK_FUNCTION(5, "SPINOR_CK"),
	452	MTK_FUNCTION(7, "dbg_mon_a11")
	453	),
	454
	455	MTK_PIN(
	456	37, "GPIO37",
	457	MTK_EINT_FUNCTION(0, 37),
	458	DRV_GRP4,
	459	MTK_FUNCTION(0, "GPIO37"),
	460	MTK_FUNCTION(1, "SPI0_CSB_A"),
	461	MTK_FUNCTION(2, "CLKM1"),
	462	MTK_FUNCTION(3, "PWM0"),
	463	MTK_FUNCTION(4, "SCP_SPI0_CS"),
	464	MTK_FUNCTION(5, "SPINOR_CS"),
	465	MTK_FUNCTION(7, "dbg_mon_a12")
	466	),
	467
	468	MTK_PIN(
	469	38, "GPIO38",
	470	MTK_EINT_FUNCTION(0, 38),
	471	DRV_GRP4,
	472	MTK_FUNCTION(0, "GPIO38"),
	473	MTK_FUNCTION(1, "SPI0_MO_A"),
	474	MTK_FUNCTION(2, "CLKM2"),
	475	MTK_FUNCTION(3, "PWM1"),
	476	MTK_FUNCTION(4, "SCP_SPI0_MO"),
	477	MTK_FUNCTION(5, "SPINOR_IO0"),
	478	MTK_FUNCTION(7, "dbg_mon_a13")
	479	),
	480
	481	MTK_PIN(
	482	39, "GPIO39",
	483	MTK_EINT_FUNCTION(0, 39),
	484	DRV_GRP4,
	485	MTK_FUNCTION(0, "GPIO39"),
	486	MTK_FUNCTION(1, "SPI0_MI_A"),
	487	MTK_FUNCTION(2, "CLKM3"),
	488	MTK_FUNCTION(3, "PWM2"),
	489	MTK_FUNCTION(4, "SCP_SPI0_MI"),
	490	MTK_FUNCTION(5, "SPINOR_IO1"),
	491	MTK_FUNCTION(7, "dbg_mon_a14")
	492	),
	493
	494	MTK_PIN(
	495	40, "GPIO40",
	496	MTK_EINT_FUNCTION(0, 40),
	497	DRV_GRP4,
	498	MTK_FUNCTION(0, "GPIO40"),
	499	MTK_FUNCTION(1, "SPI1_CLK_A"),
	500	MTK_FUNCTION(2, "SCP_SPI1_CK"),
	501	MTK_FUNCTION(4, "UCTS0"),
	502	MTK_FUNCTION(5, "SPINOR_IO2"),
	503	MTK_FUNCTION(6, "TP_UCTS1_AO"),
	504	MTK_FUNCTION(7, "dbg_mon_a15")
	505	),
	506
	507	MTK_PIN(
	508	41, "GPIO41",
	509	MTK_EINT_FUNCTION(0, 41),
	510	DRV_GRP4,
	511	MTK_FUNCTION(0, "GPIO41"),
	512	MTK_FUNCTION(1, "SPI1_CSB_A"),
	513	MTK_FUNCTION(2, "SCP_SPI1_CS"),
	514	MTK_FUNCTION(3, "PWM0"),
	515	MTK_FUNCTION(4, "URTS0"),
	516	MTK_FUNCTION(5, "SPINOR_IO3"),
	517	MTK_FUNCTION(6, "TP_URTS1_AO"),
	518	MTK_FUNCTION(7, "dbg_mon_a16")
	519	),
	520
	521	MTK_PIN(
	522	42, "GPIO42",
	523	MTK_EINT_FUNCTION(0, 42),
	524	DRV_GRP4,
	525	MTK_FUNCTION(0, "GPIO42"),
	526	MTK_FUNCTION(1, "SPI1_MO_A"),
	527	MTK_FUNCTION(2, "SCP_SPI1_MO"),
	528	MTK_FUNCTION(3, "PWM1"),
	529	MTK_FUNCTION(4, "UCTS1"),
	530	MTK_FUNCTION(6, "TP_UCTS2_AO"),
	531	MTK_FUNCTION(7, "dbg_mon_a17")
	532	),
	533
	534	MTK_PIN(
	535	43, "GPIO43",
	536	MTK_EINT_FUNCTION(0, 43),
	537	DRV_GRP4,
	538	MTK_FUNCTION(0, "GPIO43"),
	539	MTK_FUNCTION(1, "SPI1_MI_A"),
	540	MTK_FUNCTION(2, "SCP_SPI1_MI"),
	541	MTK_FUNCTION(3, "PWM2"),
	542	MTK_FUNCTION(4, "URTS1"),
	543	MTK_FUNCTION(6, "TP_URTS2_AO"),
	544	MTK_FUNCTION(7, "dbg_mon_a18")
	545	),
	546
	547	MTK_PIN(
	548	44, "GPIO44",
	549	MTK_EINT_FUNCTION(0, 44),
	550	DRV_GRP4,
	551	MTK_FUNCTION(0, "GPIO44"),
	552	MTK_FUNCTION(1, "SPI2_CLK_A"),
	553	MTK_FUNCTION(2, "SCP_SPI0_CK"),
	554	MTK_FUNCTION(7, "dbg_mon_a19")
	555	),
	556
	557	MTK_PIN(
	558	45, "GPIO45",
	559	MTK_EINT_FUNCTION(0, 45),
	560	DRV_GRP4,
	561	MTK_FUNCTION(0, "GPIO45"),
	562	MTK_FUNCTION(1, "SPI2_CSB_A"),
	563	MTK_FUNCTION(2, "SCP_SPI0_CS"),
	564	MTK_FUNCTION(7, "dbg_mon_a20")
	565	),
	566
	567	MTK_PIN(
	568	46, "GPIO46",
	569	MTK_EINT_FUNCTION(0, 46),
	570	DRV_GRP4,
	571	MTK_FUNCTION(0, "GPIO46"),
	572	MTK_FUNCTION(1, "SPI2_MO_A"),
	573	MTK_FUNCTION(2, "SCP_SPI0_MO"),
	574	MTK_FUNCTION(7, "dbg_mon_a21")
	575	),
	576
	577	MTK_PIN(
	578	47, "GPIO47",
	579	MTK_EINT_FUNCTION(0, 47),
	580	DRV_GRP4,
	581	MTK_FUNCTION(0, "GPIO47"),
	582	MTK_FUNCTION(1, "SPI2_MI_A"),
	583	MTK_FUNCTION(2, "SCP_SPI0_MI"),
	584	MTK_FUNCTION(7, "dbg_mon_a22")
	585	),
	586
	587	MTK_PIN(
	588	48, "GPIO48",
	589	MTK_EINT_FUNCTION(0, 48),
	590	DRV_GRP4,
	591	MTK_FUNCTION(0, "GPIO48"),
	592	MTK_FUNCTION(1, "SPI3_CLK"),
	593	MTK_FUNCTION(2, "TP_URXD1_AO"),
	594	MTK_FUNCTION(3, "TP_URXD2_AO"),
	595	MTK_FUNCTION(4, "URXD1"),
	596	MTK_FUNCTION(5, "I2S2_MCK"),
	597	MTK_FUNCTION(6, "SCP_SPI0_CK")
	598	),
	599
	600	MTK_PIN(
	601	49, "GPIO49",
	602	MTK_EINT_FUNCTION(0, 49),
	603	DRV_GRP4,
	604	MTK_FUNCTION(0, "GPIO49"),
	605	MTK_FUNCTION(1, "SPI3_CSB"),
	606	MTK_FUNCTION(2, "TP_UTXD1_AO"),
	607	MTK_FUNCTION(3, "TP_UTXD2_AO"),
	608	MTK_FUNCTION(4, "UTXD1"),
	609	MTK_FUNCTION(5, "I2S2_BCK"),
	610	MTK_FUNCTION(6, "SCP_SPI0_CS")
	611	),
	612
	613	MTK_PIN(
	614	50, "GPIO50",
	615	MTK_EINT_FUNCTION(0, 50),
	616	DRV_GRP4,
	617	MTK_FUNCTION(0, "GPIO50"),
	618	MTK_FUNCTION(1, "SPI3_MO"),
	619	MTK_FUNCTION(5, "I2S2_LRCK"),
	620	MTK_FUNCTION(6, "SCP_SPI0_MO")
	621	),
	622
	623	MTK_PIN(
	624	51, "GPIO51",
	625	MTK_EINT_FUNCTION(0, 51),
	626	DRV_GRP4,
	627	MTK_FUNCTION(0, "GPIO51"),
	628	MTK_FUNCTION(1, "SPI3_MI"),
	629	MTK_FUNCTION(5, "I2S2_DI"),
	630	MTK_FUNCTION(6, "SCP_SPI0_MI")
	631	),
	632
	633	MTK_PIN(
	634	52, "GPIO52",
	635	MTK_EINT_FUNCTION(0, 52),
	636	DRV_GRP4,
	637	MTK_FUNCTION(0, "GPIO52"),
	638	MTK_FUNCTION(1, "SPI5_CLK"),
	639	MTK_FUNCTION(2, "I2S2_MCK"),
	640	MTK_FUNCTION(3, "I2S1_MCK"),
	641	MTK_FUNCTION(4, "SCP_SPI1_CK"),
	642	MTK_FUNCTION(5, "LVTS_26M"),
	643	MTK_FUNCTION(6, "DFD_TCK_XI"),
	644	MTK_FUNCTION(7, "dbg_mon_b30")
	645	),
	646
	647	MTK_PIN(
	648	53, "GPIO53",
	649	MTK_EINT_FUNCTION(0, 53),
	650	DRV_GRP4,
	651	MTK_FUNCTION(0, "GPIO53"),
	652	MTK_FUNCTION(1, "SPI5_CSB"),
	653	MTK_FUNCTION(2, "I2S2_BCK"),
	654	MTK_FUNCTION(3, "I2S1_BCK"),
	655	MTK_FUNCTION(4, "SCP_SPI1_CS"),
	656	MTK_FUNCTION(5, "LVTS_FOUT"),
	657	MTK_FUNCTION(6, "DFD_TDI"),
	658	MTK_FUNCTION(7, "dbg_mon_b31")
	659	),
	660
	661	MTK_PIN(
	662	54, "GPIO54",
	663	MTK_EINT_FUNCTION(0, 54),
	664	DRV_GRP4,
	665	MTK_FUNCTION(0, "GPIO54"),
	666	MTK_FUNCTION(1, "SPI5_MO"),
	667	MTK_FUNCTION(2, "I2S2_LRCK"),
	668	MTK_FUNCTION(3, "I2S1_LRCK"),
	669	MTK_FUNCTION(4, "SCP_SPI1_MO"),
	670	MTK_FUNCTION(5, "LVTS_SCK"),
	671	MTK_FUNCTION(6, "DFD_TDO"),
	672	MTK_FUNCTION(7, "dbg_mon_a1")
	673	),
	674
	675	MTK_PIN(
	676	55, "GPIO55",
	677	MTK_EINT_FUNCTION(0, 55),
	678	DRV_GRP4,
	679	MTK_FUNCTION(0, "GPIO55"),
	680	MTK_FUNCTION(1, "SPI5_MI"),
	681	MTK_FUNCTION(2, "I2S2_DI"),
	682	MTK_FUNCTION(3, "I2S1_DO"),
	683	MTK_FUNCTION(4, "SCP_SPI1_MI"),
	684	MTK_FUNCTION(5, "LVTS_SDO"),
	685	MTK_FUNCTION(6, "DFD_TMS"),
	686	MTK_FUNCTION(7, "dbg_mon_b32")
	687	),
	688
	689	MTK_PIN(
	690	56, "GPIO56",
	691	MTK_EINT_FUNCTION(0, 56),
	692	DRV_GRP4,
	693	MTK_FUNCTION(0, "GPIO56"),
	694	MTK_FUNCTION(1, "I2S1_DO"),
	695	MTK_FUNCTION(2, "I2S3_DO"),
	696	MTK_FUNCTION(7, "dbg_mon_a23")
	697	),
	698
	699	MTK_PIN(
	700	57, "GPIO57",
	701	MTK_EINT_FUNCTION(0, 57),
	702	DRV_GRP4,
	703	MTK_FUNCTION(0, "GPIO57"),
	704	MTK_FUNCTION(1, "I2S1_BCK"),
	705	MTK_FUNCTION(2, "I2S3_BCK"),
	706	MTK_FUNCTION(7, "dbg_mon_a24")
	707	),
	708
	709	MTK_PIN(
	710	58, "GPIO58",
	711	MTK_EINT_FUNCTION(0, 58),
	712	DRV_GRP4,
	713	MTK_FUNCTION(0, "GPIO58"),
	714	MTK_FUNCTION(1, "I2S1_LRCK"),
	715	MTK_FUNCTION(2, "I2S3_LRCK"),
	716	MTK_FUNCTION(7, "dbg_mon_a25")
	717	),
	718
	719	MTK_PIN(
	720	59, "GPIO59",
	721	MTK_EINT_FUNCTION(0, 59),
	722	DRV_GRP4,
	723	MTK_FUNCTION(0, "GPIO59"),
	724	MTK_FUNCTION(1, "I2S1_MCK"),
	725	MTK_FUNCTION(2, "I2S3_MCK"),
	726	MTK_FUNCTION(7, "dbg_mon_a27")
	727	),
	728
	729	MTK_PIN(
	730	60, "GPIO60",
	731	MTK_EINT_FUNCTION(0, 60),
	732	DRV_GRP4,
	733	MTK_FUNCTION(0, "GPIO60"),
	734	MTK_FUNCTION(1, "TDM_RX_LRCK"),
	735	MTK_FUNCTION(2, "ANT_SEL3"),
	736	MTK_FUNCTION(5, "CONN_MCU_DBGACK_N")
	737	),
	738
	739	MTK_PIN(
	740	61, "GPIO61",
	741	MTK_EINT_FUNCTION(0, 61),
	742	DRV_GRP4,
	743	MTK_FUNCTION(0, "GPIO61"),
	744	MTK_FUNCTION(1, "TDM_RX_BCK"),
	745	MTK_FUNCTION(2, "ANT_SEL4"),
	746	MTK_FUNCTION(4, "SPINOR_CK"),
	747	MTK_FUNCTION(5, "CONN_MCU_DBGI_N")
	748	),
	749
	750	MTK_PIN(
	751	62, "GPIO62",
	752	MTK_EINT_FUNCTION(0, 62),
	753	DRV_GRP4,
	754	MTK_FUNCTION(0, "GPIO62"),
	755	MTK_FUNCTION(1, "TDM_RX_MCK"),
	756	MTK_FUNCTION(2, "ANT_SEL5"),
	757	MTK_FUNCTION(4, "SPINOR_CS"),
	758	MTK_FUNCTION(5, "CONN_MCU_TDI")
	759	),
	760
	761	MTK_PIN(
	762	63, "GPIO63",
	763	MTK_EINT_FUNCTION(0, 63),
	764	DRV_GRP4,
	765	MTK_FUNCTION(0, "GPIO63"),
	766	MTK_FUNCTION(1, "TDM_RX_DATA0"),
	767	MTK_FUNCTION(2, "ANT_SEL6"),
	768	MTK_FUNCTION(4, "SPINOR_IO0"),
	769	MTK_FUNCTION(5, "CONN_MCU_TRST_B")
	770	),
	771
	772	MTK_PIN(
	773	64, "GPIO64",
	774	MTK_EINT_FUNCTION(0, 64),
	775	DRV_GRP4,
	776	MTK_FUNCTION(0, "GPIO64"),
	777	MTK_FUNCTION(1, "TDM_RX_DATA1"),
	778	MTK_FUNCTION(2, "ANT_SEL7"),
	779	MTK_FUNCTION(3, "PWM0"),
	780	MTK_FUNCTION(4, "SPINOR_IO1"),
	781	MTK_FUNCTION(5, "CONN_MCU_TCK")
	782	),
	783
	784	MTK_PIN(
	785	65, "GPIO65",
	786	MTK_EINT_FUNCTION(0, 65),
	787	DRV_GRP4,
	788	MTK_FUNCTION(0, "GPIO65"),
	789	MTK_FUNCTION(1, "TDM_RX_DATA2"),
	790	MTK_FUNCTION(2, "UCTS0"),
	791	MTK_FUNCTION(3, "PWM1"),
	792	MTK_FUNCTION(4, "SPINOR_IO2"),
	793	MTK_FUNCTION(5, "CONN_MCU_TDO"),
	794	MTK_FUNCTION(6, "TP_UCTS1_AO"),
	795	MTK_FUNCTION(7, "TP_UCTS2_AO")
	796	),
	797
	798	MTK_PIN(
	799	66, "GPIO66",
	800	MTK_EINT_FUNCTION(0, 66),
	801	DRV_GRP4,
	802	MTK_FUNCTION(0, "GPIO66"),
	803	MTK_FUNCTION(1, "TDM_RX_DATA3"),
	804	MTK_FUNCTION(2, "URTS0"),
	805	MTK_FUNCTION(3, "PWM2"),
	806	MTK_FUNCTION(4, "SPINOR_IO3"),
	807	MTK_FUNCTION(5, "CONN_MCU_TMS"),
	808	MTK_FUNCTION(6, "TP_URTS1_AO"),
	809	MTK_FUNCTION(7, "TP_URTS2_AO")
	810	),
	811
	812	MTK_PIN(
	813	67, "GPIO67",
	814	MTK_EINT_FUNCTION(0, 67),
	815	DRV_GRP4,
	816	MTK_FUNCTION(0, "GPIO67"),
	817	MTK_FUNCTION(1, "MSDC0_DSL")
	818	),
	819
	820	MTK_PIN(
	821	68, "GPIO68",
	822	MTK_EINT_FUNCTION(0, 68),
	823	DRV_GRP4,
	824	MTK_FUNCTION(0, "GPIO68"),
	825	MTK_FUNCTION(1, "MSDC0_CLK")
	826	),
	827
	828	MTK_PIN(
	829	69, "GPIO69",
	830	MTK_EINT_FUNCTION(0, 69),
	831	DRV_GRP4,
	832	MTK_FUNCTION(0, "GPIO69"),
	833	MTK_FUNCTION(1, "MSDC0_CMD")
	834	),
	835
	836	MTK_PIN(
	837	70, "GPIO70",
	838	MTK_EINT_FUNCTION(0, 70),
	839	DRV_GRP4,
	840	MTK_FUNCTION(0, "GPIO70"),
	841	MTK_FUNCTION(1, "MSDC0_RSTB")
	842	),
	843
	844	MTK_PIN(
	845	71, "GPIO71",
	846	MTK_EINT_FUNCTION(0, 71),
	847	DRV_GRP4,
	848	MTK_FUNCTION(0, "GPIO71"),
	849	MTK_FUNCTION(1, "MSDC0_DAT0")
	850	),
	851
	852	MTK_PIN(
	853	72, "GPIO72",
	854	MTK_EINT_FUNCTION(0, 72),
	855	DRV_GRP4,
	856	MTK_FUNCTION(0, "GPIO72"),
	857	MTK_FUNCTION(1, "MSDC0_DAT1")
	858	),
	859
	860	MTK_PIN(
	861	73, "GPIO73",
	862	MTK_EINT_FUNCTION(0, 73),
	863	DRV_GRP4,
	864	MTK_FUNCTION(0, "GPIO73"),
	865	MTK_FUNCTION(1, "MSDC0_DAT2")
	866	),
	867
	868	MTK_PIN(
	869	74, "GPIO74",
	870	MTK_EINT_FUNCTION(0, 74),
	871	DRV_GRP4,
	872	MTK_FUNCTION(0, "GPIO74"),
	873	MTK_FUNCTION(1, "MSDC0_DAT3")
	874	),
	875
	876	MTK_PIN(
	877	75, "GPIO75",
	878	MTK_EINT_FUNCTION(0, 75),
	879	DRV_GRP4,
	880	MTK_FUNCTION(0, "GPIO75"),
	881	MTK_FUNCTION(1, "MSDC0_DAT4")
	882	),
	883
	884	MTK_PIN(
	885	76, "GPIO76",
	886	MTK_EINT_FUNCTION(0, 76),
	887	DRV_GRP4,
	888	MTK_FUNCTION(0, "GPIO76"),
	889	MTK_FUNCTION(1, "MSDC0_DAT5")
	890	),
	891
	892	MTK_PIN(
	893	77, "GPIO77",
	894	MTK_EINT_FUNCTION(0, 77),
	895	DRV_GRP4,
	896	MTK_FUNCTION(0, "GPIO77"),
	897	MTK_FUNCTION(1, "MSDC0_DAT6")
	898	),
	899
	900	MTK_PIN(
	901	78, "GPIO78",
	902	MTK_EINT_FUNCTION(0, 78),
	903	DRV_GRP4,
	904	MTK_FUNCTION(0, "GPIO78"),
	905	MTK_FUNCTION(1, "MSDC0_DAT7")
	906	),
	907
	908	MTK_PIN(
	909	79, "GPIO79",
	910	MTK_EINT_FUNCTION(0, 79),
	911	DRV_GRP4,
	912	MTK_FUNCTION(0, "GPIO79"),
	913	MTK_FUNCTION(1, "KPCOL0")
	914	),
	915
	916	MTK_PIN(
	917	80, "GPIO80",
	918	MTK_EINT_FUNCTION(0, 80),
	919	DRV_GRP4,
	920	MTK_FUNCTION(0, "GPIO80"),
	921	MTK_FUNCTION(1, "KPCOL1"),
	922	MTK_FUNCTION(2, "GPS_L1_ELNA_EN"),
	923	MTK_FUNCTION(3, "PWM0"),
	924	MTK_FUNCTION(4, "CLKM0")
	925	),
	926
	927	MTK_PIN(
	928	81, "GPIO81",
	929	MTK_EINT_FUNCTION(0, 81),
	930	DRV_GRP4,
	931	MTK_FUNCTION(0, "GPIO81"),
	932	MTK_FUNCTION(1, "KPROW0"),
	933	MTK_FUNCTION(3, "PWM1"),
	934	MTK_FUNCTION(4, "CLKM1")
	935	),
	936
	937	MTK_PIN(
	938	82, "GPIO82",
	939	MTK_EINT_FUNCTION(0, 82),
	940	DRV_GRP4,
	941	MTK_FUNCTION(0, "GPIO82"),
	942	MTK_FUNCTION(1, "KPROW1"),
	943	MTK_FUNCTION(3, "PWM2"),
	944	MTK_FUNCTION(4, "CLKM2")
	945	),
	946
	947	MTK_PIN(
	948	83, "GPIO83",
	949	MTK_EINT_FUNCTION(0, 83),
	950	DRV_GRP4,
	951	MTK_FUNCTION(0, "GPIO83"),
	952	MTK_FUNCTION(1, "AP_GOOD"),
	953	MTK_FUNCTION(2, "GPS_PPS"),
	954	MTK_FUNCTION(4, "EXT_FRAME_SYNC"),
	955	MTK_FUNCTION(7, "dbg_mon_a28")
	956	),
	957
	958	MTK_PIN(
	959	84, "GPIO84",
	960	MTK_EINT_FUNCTION(0, 84),
	961	DRV_GRP4,
	962	MTK_FUNCTION(0, "GPIO84"),
	963	MTK_FUNCTION(1, "MSDC1_CLK"),
	964	MTK_FUNCTION(2, "ADSP_JTAG_TCK"),
	965	MTK_FUNCTION(4, "UDI_TCK"),
	966	MTK_FUNCTION(5, "CONN_DSP_JCK"),
	967	MTK_FUNCTION(6, "SSPM_JTAG_TCK"),
	968	MTK_FUNCTION(7, "DFD_TCK_XI")
	969	),
	970
	971	MTK_PIN(
	972	85, "GPIO85",
	973	MTK_EINT_FUNCTION(0, 85),
	974	DRV_GRP4,
	975	MTK_FUNCTION(0, "GPIO85"),
	976	MTK_FUNCTION(1, "MSDC1_CMD"),
	977	MTK_FUNCTION(2, "ADSP_JTAG_TMS"),
	978	MTK_FUNCTION(3, "CONN_MCU_AICE_TMSC"),
	979	MTK_FUNCTION(4, "UDI_TMS"),
	980	MTK_FUNCTION(5, "CONN_DSP_JMS"),
	981	MTK_FUNCTION(6, "SSPM_JTAG_TMS"),
	982	MTK_FUNCTION(7, "DFD_TMS")
	983	),
	984
	985	MTK_PIN(
	986	86, "GPIO86",
	987	MTK_EINT_FUNCTION(0, 86),
	988	DRV_GRP4,
	989	MTK_FUNCTION(0, "GPIO86"),
	990	MTK_FUNCTION(1, "MSDC1_DAT0"),
	991	MTK_FUNCTION(2, "ADSP_JTAG_TDI"),
	992	MTK_FUNCTION(4, "UDI_TDI"),
	993	MTK_FUNCTION(5, "CONN_DSP_JDI"),
	994	MTK_FUNCTION(6, "SSPM_JTAG_TDI"),
	995	MTK_FUNCTION(7, "DFD_TDI")
	996	),
	997
	998	MTK_PIN(
	999	87, "GPIO87",
	1000	MTK_EINT_FUNCTION(0, 87),
	1001	DRV_GRP4,
	1002	MTK_FUNCTION(0, "GPIO87"),
	1003	MTK_FUNCTION(1, "MSDC1_DAT1"),
	1004	MTK_FUNCTION(2, "ADSP_JTAG_TDO"),
	1005	MTK_FUNCTION(4, "UDI_TDO"),
	1006	MTK_FUNCTION(5, "CONN_DSP_JDO"),
	1007	MTK_FUNCTION(6, "SSPM_JTAG_TDO"),
	1008	MTK_FUNCTION(7, "DFD_TDO")
	1009	),
	1010
	1011	MTK_PIN(
	1012	88, "GPIO88",
	1013	MTK_EINT_FUNCTION(0, 88),
	1014	DRV_GRP4,
	1015	MTK_FUNCTION(0, "GPIO88"),
	1016	MTK_FUNCTION(1, "MSDC1_DAT2"),
	1017	MTK_FUNCTION(2, "ADSP_JTAG_TRSTN"),
	1018	MTK_FUNCTION(3, "CONN_MCU_AICE_TCKC"),
	1019	MTK_FUNCTION(4, "UDI_NTRST"),
	1020	MTK_FUNCTION(5, "CONN_WIFI_TXD"),
	1021	MTK_FUNCTION(6, "SSPM_JTAG_TRSTN")
	1022	),
	1023
	1024	MTK_PIN(
	1025	89, "GPIO89",
	1026	MTK_EINT_FUNCTION(0, 89),
	1027	DRV_GRP4,
	1028	MTK_FUNCTION(0, "GPIO89"),
	1029	MTK_FUNCTION(1, "MSDC1_DAT3"),
	1030	MTK_FUNCTION(5, "CONN_DSP_JINTP")
	1031	),
	1032
	1033	MTK_PIN(
	1034	90, "GPIO90",
	1035	MTK_EINT_FUNCTION(0, 90),
	1036	DRV_GRP4,
	1037	MTK_FUNCTION(0, "GPIO90"),
	1038	MTK_FUNCTION(1, "IDDIG_P0"),
	1039	MTK_FUNCTION(4, "PGD_HV_HSC_PWR4"),
	1040	MTK_FUNCTION(5, "GDU_SUM_TROOP2_2")
	1041	),
	1042
	1043	MTK_PIN(
	1044	91, "GPIO91",
	1045	MTK_EINT_FUNCTION(0, 91),
	1046	DRV_GRP4,
	1047	MTK_FUNCTION(0, "GPIO91"),
	1048	MTK_FUNCTION(1, "USB_DRVVBUS_P0"),
	1049	MTK_FUNCTION(4, "PGD_HV_HSC_PWR5"),
	1050	MTK_FUNCTION(5, "GDU_TROOPS_DET0")
	1051	),
	1052
	1053	MTK_PIN(
	1054	92, "GPIO92",
	1055	MTK_EINT_FUNCTION(0, 92),
	1056	DRV_GRP4,
	1057	MTK_FUNCTION(0, "GPIO92"),
	1058	MTK_FUNCTION(1, "VBUS_VALID_P0"),
	1059	MTK_FUNCTION(4, "PGD_DA_EFUSE_RDY"),
	1060	MTK_FUNCTION(5, "GDU_TROOPS_DET1")
	1061	),
	1062
	1063	MTK_PIN(
	1064	93, "GPIO93",
	1065	MTK_EINT_FUNCTION(0, 93),
	1066	DRV_GRP4,
	1067	MTK_FUNCTION(0, "GPIO93"),
	1068	MTK_FUNCTION(1, "IDDIG_P1"),
	1069	MTK_FUNCTION(2, "PWM0"),
	1070	MTK_FUNCTION(3, "CLKM0"),
	1071	MTK_FUNCTION(4, "PGD_DA_EFUSE_RDY_PRE"),
	1072	MTK_FUNCTION(5, "GDU_TROOPS_DET2")
	1073	),
	1074
	1075	MTK_PIN(
	1076	94, "GPIO94",
	1077	MTK_EINT_FUNCTION(0, 94),
	1078	DRV_GRP4,
	1079	MTK_FUNCTION(0, "GPIO94"),
	1080	MTK_FUNCTION(1, "USB_DRVVBUS_P1"),
	1081	MTK_FUNCTION(2, "PWM1"),
	1082	MTK_FUNCTION(3, "CLKM1"),
	1083	MTK_FUNCTION(4, "PGD_DA_PWRGD_RESET")
	1084	),
	1085
	1086	MTK_PIN(
	1087	95, "GPIO95",
	1088	MTK_EINT_FUNCTION(0, 95),
	1089	DRV_GRP4,
	1090	MTK_FUNCTION(0, "GPIO95"),
	1091	MTK_FUNCTION(1, "VBUS_VALID_P1"),
	1092	MTK_FUNCTION(2, "PWM2"),
	1093	MTK_FUNCTION(3, "CLKM2"),
	1094	MTK_FUNCTION(4, "PGD_DA_PWRGD_ENB")
	1095	),
	1096
	1097	MTK_PIN(
	1098	96, "GPIO96",
	1099	MTK_EINT_FUNCTION(0, 96),
	1100	DRV_GRP4,
	1101	MTK_FUNCTION(0, "GPIO96"),
	1102	MTK_FUNCTION(1, "DSI_TE"),
	1103	MTK_FUNCTION(7, "dbg_mon_a29")
	1104	),
	1105
	1106	MTK_PIN(
	1107	97, "GPIO97",
	1108	MTK_EINT_FUNCTION(0, 97),
	1109	DRV_GRP4,
	1110	MTK_FUNCTION(0, "GPIO97"),
	1111	MTK_FUNCTION(1, "DISP_PWM"),
	1112	MTK_FUNCTION(7, "dbg_mon_a30")
	1113	),
	1114
	1115	MTK_PIN(
	1116	98, "GPIO98",
	1117	MTK_EINT_FUNCTION(0, 98),
	1118	DRV_GRP4,
	1119	MTK_FUNCTION(0, "GPIO98"),
	1120	MTK_FUNCTION(1, "LCM_RST")
	1121	),
	1122
	1123	MTK_PIN(
	1124	99, "GPIO99",
	1125	MTK_EINT_FUNCTION(0, 99),
	1126	DRV_GRP4,
	1127	MTK_FUNCTION(0, "GPIO99"),
	1128	MTK_FUNCTION(1, "DPI_PCLK"),
	1129	MTK_FUNCTION(2, "GPS_L1_ELNA_EN"),
	1130	MTK_FUNCTION(3, "SSPM_JTAG_TCK"),
	1131	MTK_FUNCTION(5, "ANT_SEL0"),
	1132	MTK_FUNCTION(6, "TP_GPIO0_AO"),
	1133	MTK_FUNCTION(7, "PGD_LV_LSC_PWR0")
	1134	),
	1135
	1136	MTK_PIN(
	1137	100, "GPIO100",
	1138	MTK_EINT_FUNCTION(0, 100),
	1139	DRV_GRP4,
	1140	MTK_FUNCTION(0, "GPIO100"),
	1141	MTK_FUNCTION(1, "DPI_VSYNC"),
	1142	MTK_FUNCTION(2, "KPCOL2"),
	1143	MTK_FUNCTION(3, "SSPM_JTAG_TMS"),
	1144	MTK_FUNCTION(5, "ANT_SEL1"),
	1145	MTK_FUNCTION(6, "TP_GPIO1_AO"),
	1146	MTK_FUNCTION(7, "PGD_LV_LSC_PWR1")
	1147	),
	1148
	1149	MTK_PIN(
	1150	101, "GPIO101",
	1151	MTK_EINT_FUNCTION(0, 101),
	1152	DRV_GRP4,
	1153	MTK_FUNCTION(0, "GPIO101"),
	1154	MTK_FUNCTION(1, "DPI_HSYNC"),
	1155	MTK_FUNCTION(2, "KPROW2"),
	1156	MTK_FUNCTION(3, "SSPM_JTAG_TDI"),
	1157	MTK_FUNCTION(5, "ANT_SEL2"),
	1158	MTK_FUNCTION(6, "TP_GPIO2_AO"),
	1159	MTK_FUNCTION(7, "PGD_LV_LSC_PWR2")
	1160	),
	1161
	1162	MTK_PIN(
	1163	102, "GPIO102",
	1164	MTK_EINT_FUNCTION(0, 102),
	1165	DRV_GRP4,
	1166	MTK_FUNCTION(0, "GPIO102"),
	1167	MTK_FUNCTION(1, "DPI_DE"),
	1168	MTK_FUNCTION(3, "SSPM_JTAG_TDO"),
	1169	MTK_FUNCTION(5, "ANT_SEL3"),
	1170	MTK_FUNCTION(6, "TP_GPIO3_AO"),
	1171	MTK_FUNCTION(7, "PGD_LV_LSC_PWR3")
	1172	),
	1173
	1174	MTK_PIN(
	1175	103, "GPIO103",
	1176	MTK_EINT_FUNCTION(0, 103),
	1177	DRV_GRP4,
	1178	MTK_FUNCTION(0, "GPIO103"),
	1179	MTK_FUNCTION(1, "DPI_DATA0"),
	1180	MTK_FUNCTION(3, "SSPM_JTAG_TRSTN"),
	1181	MTK_FUNCTION(4, "CLKM0"),
	1182	MTK_FUNCTION(5, "ANT_SEL4"),
	1183	MTK_FUNCTION(6, "TP_GPIO4_AO"),
	1184	MTK_FUNCTION(7, "PGD_LV_LSC_PWR4")
	1185	),
	1186
	1187	MTK_PIN(
	1188	104, "GPIO104",
	1189	MTK_EINT_FUNCTION(0, 104),
	1190	DRV_GRP4,
	1191	MTK_FUNCTION(0, "GPIO104"),
	1192	MTK_FUNCTION(1, "DPI_DATA1"),
	1193	MTK_FUNCTION(2, "GPS_PPS"),
	1194	MTK_FUNCTION(3, "UCTS2"),
	1195	MTK_FUNCTION(4, "CLKM1"),
	1196	MTK_FUNCTION(5, "ANT_SEL5"),
	1197	MTK_FUNCTION(6, "TP_GPIO5_AO"),
	1198	MTK_FUNCTION(7, "PGD_LV_LSC_PWR5")
	1199	),
	1200
	1201	MTK_PIN(
	1202	105, "GPIO105",
	1203	MTK_EINT_FUNCTION(0, 105),
	1204	DRV_GRP4,
	1205	MTK_FUNCTION(0, "GPIO105"),
	1206	MTK_FUNCTION(1, "DPI_DATA2"),
	1207	MTK_FUNCTION(2, "CONN_TCXOENA_REQ"),
	1208	MTK_FUNCTION(3, "URTS2"),
	1209	MTK_FUNCTION(4, "CLKM2"),
	1210	MTK_FUNCTION(5, "ANT_SEL6"),
	1211	MTK_FUNCTION(6, "TP_GPIO6_AO"),
	1212	MTK_FUNCTION(7, "PGD_LV_HSC_PWR0")
	1213	),
	1214
	1215	MTK_PIN(
	1216	106, "GPIO106",
	1217	MTK_EINT_FUNCTION(0, 106),
	1218	DRV_GRP4,
	1219	MTK_FUNCTION(0, "GPIO106"),
	1220	MTK_FUNCTION(1, "DPI_DATA3"),
	1221	MTK_FUNCTION(2, "TP_UTXD1_AO"),
	1222	MTK_FUNCTION(3, "UTXD2"),
	1223	MTK_FUNCTION(4, "PWM0"),
	1224	MTK_FUNCTION(5, "ANT_SEL7"),
	1225	MTK_FUNCTION(6, "TP_GPIO7_AO"),
	1226	MTK_FUNCTION(7, "PGD_LV_HSC_PWR1")
	1227	),
	1228
	1229	MTK_PIN(
	1230	107, "GPIO107",
	1231	MTK_EINT_FUNCTION(0, 107),
	1232	DRV_GRP4,
	1233	MTK_FUNCTION(0, "GPIO107"),
	1234	MTK_FUNCTION(1, "DPI_DATA4"),
	1235	MTK_FUNCTION(2, "TP_URXD1_AO"),
	1236	MTK_FUNCTION(3, "URXD2"),
	1237	MTK_FUNCTION(4, "PWM1"),
	1238	MTK_FUNCTION(6, "GDU_SUM_TROOP0_0"),
	1239	MTK_FUNCTION(7, "PGD_LV_HSC_PWR2")
	1240	),
	1241
	1242	MTK_PIN(
	1243	108, "GPIO108",
	1244	MTK_EINT_FUNCTION(0, 108),
	1245	DRV_GRP4,
	1246	MTK_FUNCTION(0, "GPIO108"),
	1247	MTK_FUNCTION(1, "DPI_DATA5"),
	1248	MTK_FUNCTION(2, "TP_UCTS1_AO"),
	1249	MTK_FUNCTION(3, "UCTS0"),
	1250	MTK_FUNCTION(4, "PWM2"),
	1251	MTK_FUNCTION(6, "GDU_SUM_TROOP0_1"),
	1252	MTK_FUNCTION(7, "PGD_LV_HSC_PWR3")
	1253	),
	1254
	1255	MTK_PIN(
	1256	109, "GPIO109",
	1257	MTK_EINT_FUNCTION(0, 109),
	1258	DRV_GRP4,
	1259	MTK_FUNCTION(0, "GPIO109"),
	1260	MTK_FUNCTION(1, "DPI_DATA6"),
	1261	MTK_FUNCTION(2, "TP_URTS1_AO"),
	1262	MTK_FUNCTION(3, "URTS0"),
	1263	MTK_FUNCTION(4, "I2S0_DI"),
	1264	MTK_FUNCTION(5, "I2S2_DI"),
	1265	MTK_FUNCTION(6, "GDU_SUM_TROOP0_2"),
	1266	MTK_FUNCTION(7, "PGD_LV_HSC_PWR4")
	1267	),
	1268
	1269	MTK_PIN(
	1270	110, "GPIO110",
	1271	MTK_EINT_FUNCTION(0, 110),
	1272	DRV_GRP4,
	1273	MTK_FUNCTION(0, "GPIO110"),
	1274	MTK_FUNCTION(1, "DPI_DATA7"),
	1275	MTK_FUNCTION(2, "TP_UCTS2_AO"),
	1276	MTK_FUNCTION(3, "UCTS1"),
	1277	MTK_FUNCTION(4, "I2S3_BCK"),
	1278	MTK_FUNCTION(5, "I2S1_BCK"),
	1279	MTK_FUNCTION(6, "GDU_SUM_TROOP1_0"),
	1280	MTK_FUNCTION(7, "PGD_LV_HSC_PWR5")
	1281	),
	1282
	1283	MTK_PIN(
	1284	111, "GPIO111",
	1285	MTK_EINT_FUNCTION(0, 111),
	1286	DRV_GRP4,
	1287	MTK_FUNCTION(0, "GPIO111"),
	1288	MTK_FUNCTION(1, "DPI_DATA8"),
	1289	MTK_FUNCTION(2, "TP_URTS2_AO"),
	1290	MTK_FUNCTION(3, "URTS1"),
	1291	MTK_FUNCTION(4, "I2S3_MCK"),
	1292	MTK_FUNCTION(5, "I2S1_MCK"),
	1293	MTK_FUNCTION(6, "GDU_SUM_TROOP1_1"),
	1294	MTK_FUNCTION(7, "PGD_HV_HSC_PWR0")
	1295	),
	1296
	1297	MTK_PIN(
	1298	112, "GPIO112",
	1299	MTK_EINT_FUNCTION(0, 112),
	1300	DRV_GRP4,
	1301	MTK_FUNCTION(0, "GPIO112"),
	1302	MTK_FUNCTION(1, "DPI_DATA9"),
	1303	MTK_FUNCTION(2, "TP_URXD2_AO"),
	1304	MTK_FUNCTION(3, "URXD1"),
	1305	MTK_FUNCTION(4, "I2S3_LRCK"),
	1306	MTK_FUNCTION(5, "I2S1_LRCK"),
	1307	MTK_FUNCTION(6, "GDU_SUM_TROOP1_2"),
	1308	MTK_FUNCTION(7, "PGD_HV_HSC_PWR1")
	1309	),
	1310
	1311	MTK_PIN(
	1312	113, "GPIO113",
	1313	MTK_EINT_FUNCTION(0, 113),
	1314	DRV_GRP4,
	1315	MTK_FUNCTION(0, "GPIO113"),
	1316	MTK_FUNCTION(1, "DPI_DATA10"),
	1317	MTK_FUNCTION(2, "TP_UTXD2_AO"),
	1318	MTK_FUNCTION(3, "UTXD1"),
	1319	MTK_FUNCTION(4, "I2S3_DO"),
	1320	MTK_FUNCTION(5, "I2S1_DO"),
	1321	MTK_FUNCTION(6, "GDU_SUM_TROOP2_0"),
	1322	MTK_FUNCTION(7, "PGD_HV_HSC_PWR2")
	1323	),
	1324
	1325	MTK_PIN(
	1326	114, "GPIO114",
	1327	MTK_EINT_FUNCTION(0, 114),
	1328	DRV_GRP4,
	1329	MTK_FUNCTION(0, "GPIO114"),
	1330	MTK_FUNCTION(1, "DPI_DATA11"),
	1331	MTK_FUNCTION(6, "GDU_SUM_TROOP2_1"),
	1332	MTK_FUNCTION(7, "PGD_HV_HSC_PWR3")
	1333	),
	1334
	1335	MTK_PIN(
	1336	115, "GPIO115",
	1337	MTK_EINT_FUNCTION(0, 115),
	1338	DRV_GRP4,
	1339	MTK_FUNCTION(0, "GPIO115"),
	1340	MTK_FUNCTION(1, "PCM_CLK"),
	1341	MTK_FUNCTION(2, "I2S0_BCK"),
	1342	MTK_FUNCTION(3, "I2S2_BCK")
	1343	),
	1344
	1345	MTK_PIN(
	1346	116, "GPIO116",
	1347	MTK_EINT_FUNCTION(0, 116),
	1348	DRV_GRP4,
	1349	MTK_FUNCTION(0, "GPIO116"),
	1350	MTK_FUNCTION(1, "PCM_SYNC"),
	1351	MTK_FUNCTION(2, "I2S0_LRCK"),
	1352	MTK_FUNCTION(3, "I2S2_LRCK")
	1353	),
	1354
	1355	MTK_PIN(
	1356	117, "GPIO117",
	1357	MTK_EINT_FUNCTION(0, 117),
	1358	DRV_GRP4,
	1359	MTK_FUNCTION(0, "GPIO117"),
	1360	MTK_FUNCTION(1, "PCM_DI"),
	1361	MTK_FUNCTION(2, "I2S0_DI"),
	1362	MTK_FUNCTION(3, "I2S2_DI")
	1363	),
	1364
	1365	MTK_PIN(
	1366	118, "GPIO118",
	1367	MTK_EINT_FUNCTION(0, 118),
	1368	DRV_GRP4,
	1369	MTK_FUNCTION(0, "GPIO118"),
	1370	MTK_FUNCTION(1, "PCM_DO"),
	1371	MTK_FUNCTION(2, "I2S0_MCK"),
	1372	MTK_FUNCTION(3, "I2S2_MCK"),
	1373	MTK_FUNCTION(4, "I2S3_DO"),
	1374	MTK_FUNCTION(5, "I2S1_DO")
	1375	),
	1376
	1377	MTK_PIN(
	1378	119, "GPIO119",
	1379	MTK_EINT_FUNCTION(0, 119),
	1380	DRV_GRP4,
	1381	MTK_FUNCTION(0, "GPIO119"),
	1382	MTK_FUNCTION(1, "JTMS_SEL1"),
	1383	MTK_FUNCTION(2, "UDI_TMS"),
	1384	MTK_FUNCTION(3, "DFD_TMS"),
	1385	MTK_FUNCTION(4, "SPM_JTAG_TMS"),
	1386	MTK_FUNCTION(5, "SCP_JTAG_TMS"),
	1387	MTK_FUNCTION(6, "ADSP_JTAG_TMS")
	1388	),
	1389
	1390	MTK_PIN(
	1391	120, "GPIO120",
	1392	MTK_EINT_FUNCTION(0, 120),
	1393	DRV_GRP4,
	1394	MTK_FUNCTION(0, "GPIO120"),
	1395	MTK_FUNCTION(1, "JTCK_SEL1"),
	1396	MTK_FUNCTION(2, "UDI_TCK"),
	1397	MTK_FUNCTION(3, "DFD_TCK_XI"),
	1398	MTK_FUNCTION(4, "SPM_JTAG_TCK"),
	1399	MTK_FUNCTION(5, "SCP_JTAG_TCK"),
	1400	MTK_FUNCTION(6, "ADSP_JTAG_TCK")
	1401	),
	1402
	1403	MTK_PIN(
	1404	121, "GPIO121",
	1405	MTK_EINT_FUNCTION(0, 121),
	1406	DRV_GRP4,
	1407	MTK_FUNCTION(0, "GPIO121"),
	1408	MTK_FUNCTION(1, "JTDI_SEL1"),
	1409	MTK_FUNCTION(2, "UDI_TDI"),
	1410	MTK_FUNCTION(3, "DFD_TDI"),
	1411	MTK_FUNCTION(4, "SPM_JTAG_TDI"),
	1412	MTK_FUNCTION(5, "SCP_JTAG_TDI"),
	1413	MTK_FUNCTION(6, "ADSP_JTAG_TDI")
	1414	),
	1415
	1416	MTK_PIN(
	1417	122, "GPIO122",
	1418	MTK_EINT_FUNCTION(0, 122),
	1419	DRV_GRP4,
	1420	MTK_FUNCTION(0, "GPIO122"),
	1421	MTK_FUNCTION(1, "JTDO_SEL1"),
	1422	MTK_FUNCTION(2, "UDI_TDO"),
	1423	MTK_FUNCTION(3, "DFD_TDO"),
	1424	MTK_FUNCTION(4, "SPM_JTAG_TDO"),
	1425	MTK_FUNCTION(5, "SCP_JTAG_TDO"),
	1426	MTK_FUNCTION(6, "ADSP_JTAG_TDO")
	1427	),
	1428
	1429	MTK_PIN(
	1430	123, "GPIO123",
	1431	MTK_EINT_FUNCTION(0, 123),
	1432	DRV_GRP4,
	1433	MTK_FUNCTION(0, "GPIO123"),
	1434	MTK_FUNCTION(1, "JTRSTN_SEL1"),
	1435	MTK_FUNCTION(2, "UDI_NTRST"),
	1436	MTK_FUNCTION(4, "SPM_JTAG_TRSTN"),
	1437	MTK_FUNCTION(5, "SCP_JTAG_TRSTN"),
	1438	MTK_FUNCTION(6, "ADSP_JTAG_TRSTN")
	1439	),
	1440
	1441	MTK_PIN(
	1442	124, "GPIO124",
	1443	MTK_EINT_FUNCTION(0, 124),
	1444	DRV_GRP4,
	1445	MTK_FUNCTION(0, "GPIO124"),
	1446	MTK_FUNCTION(1, "CMMCLK0"),
	1447	MTK_FUNCTION(2, "CLKM0"),
	1448	MTK_FUNCTION(3, "PWM0")
	1449	),
	1450
	1451	MTK_PIN(
	1452	125, "GPIO125",
	1453	MTK_EINT_FUNCTION(0, 125),
	1454	DRV_GRP4,
	1455	MTK_FUNCTION(0, "GPIO125"),
	1456	MTK_FUNCTION(1, "CMMCLK1"),
	1457	MTK_FUNCTION(2, "CLKM1"),
	1458	MTK_FUNCTION(3, "PWM1"),
	1459	MTK_FUNCTION(7, "dbg_mon_b0")
	1460	),
	1461
	1462	MTK_PIN(
	1463	126, "GPIO126",
	1464	MTK_EINT_FUNCTION(0, 126),
	1465	DRV_GRP4,
	1466	MTK_FUNCTION(0, "GPIO126"),
	1467	MTK_FUNCTION(1, "CMMCLK2"),
	1468	MTK_FUNCTION(2, "CLKM2"),
	1469	MTK_FUNCTION(3, "PWM2"),
	1470	MTK_FUNCTION(7, "dbg_mon_b1")
	1471	),
	1472
	1473	MTK_PIN(
	1474	127, "GPIO127",
	1475	MTK_EINT_FUNCTION(0, 127),
	1476	DRV_GRP4,
	1477	MTK_FUNCTION(0, "GPIO127"),
	1478	MTK_FUNCTION(1, "SCL0"),
	1479	MTK_FUNCTION(4, "SCP_SCL0"),
	1480	MTK_FUNCTION(5, "SCP_SCL1")
	1481	),
	1482
	1483	MTK_PIN(
	1484	128, "GPIO128",
	1485	MTK_EINT_FUNCTION(0, 128),
	1486	DRV_GRP4,
	1487	MTK_FUNCTION(0, "GPIO128"),
	1488	MTK_FUNCTION(1, "SDA0"),
	1489	MTK_FUNCTION(4, "SCP_SDA0"),
	1490	MTK_FUNCTION(5, "SCP_SDA1")
	1491	),
	1492
	1493	MTK_PIN(
	1494	129, "GPIO129",
	1495	MTK_EINT_FUNCTION(0, 129),
	1496	DRV_GRP4,
	1497	MTK_FUNCTION(0, "GPIO129"),
	1498	MTK_FUNCTION(1, "SCL1"),
	1499	MTK_FUNCTION(4, "SCP_SCL0"),
	1500	MTK_FUNCTION(5, "SCP_SCL1"),
	1501	MTK_FUNCTION(7, "dbg_mon_b4")
	1502	),
	1503
	1504	MTK_PIN(
	1505	130, "GPIO130",
	1506	MTK_EINT_FUNCTION(0, 130),
	1507	DRV_GRP4,
	1508	MTK_FUNCTION(0, "GPIO130"),
	1509	MTK_FUNCTION(1, "SDA1"),
	1510	MTK_FUNCTION(4, "SCP_SDA0"),
	1511	MTK_FUNCTION(5, "SCP_SDA1"),
	1512	MTK_FUNCTION(7, "dbg_mon_b5")
	1513	),
	1514
	1515	MTK_PIN(
	1516	131, "GPIO131",
	1517	MTK_EINT_FUNCTION(0, 131),
	1518	DRV_GRP4,
	1519	MTK_FUNCTION(0, "GPIO131"),
	1520	MTK_FUNCTION(1, "SCL2"),
	1521	MTK_FUNCTION(2, "SSPM_UTXD_AO"),
	1522	MTK_FUNCTION(3, "CONN_UART0_TXD"),
	1523	MTK_FUNCTION(4, "SCP_SCL0"),
	1524	MTK_FUNCTION(5, "SCP_SCL1"),
	1525	MTK_FUNCTION(7, "dbg_mon_b6")
	1526	),
	1527
	1528	MTK_PIN(
	1529	132, "GPIO132",
	1530	MTK_EINT_FUNCTION(0, 132),
	1531	DRV_GRP4,
	1532	MTK_FUNCTION(0, "GPIO132"),
	1533	MTK_FUNCTION(1, "SDA2"),
	1534	MTK_FUNCTION(2, "SSPM_URXD_AO"),
	1535	MTK_FUNCTION(3, "CONN_UART0_RXD"),
	1536	MTK_FUNCTION(4, "SCP_SDA0"),
	1537	MTK_FUNCTION(5, "SCP_SDA1"),
	1538	MTK_FUNCTION(7, "dbg_mon_b7")
	1539	),
	1540
	1541	MTK_PIN(
	1542	133, "GPIO133",
	1543	MTK_EINT_FUNCTION(0, 133),
	1544	DRV_GRP4,
	1545	MTK_FUNCTION(0, "GPIO133"),
	1546	MTK_FUNCTION(1, "SCL3"),
	1547	MTK_FUNCTION(4, "SCP_SCL0"),
	1548	MTK_FUNCTION(5, "SCP_SCL1"),
	1549	MTK_FUNCTION(7, "dbg_mon_b8")
	1550	),
	1551
	1552	MTK_PIN(
	1553	134, "GPIO134",
	1554	MTK_EINT_FUNCTION(0, 134),
	1555	DRV_GRP4,
	1556	MTK_FUNCTION(0, "GPIO134"),
	1557	MTK_FUNCTION(1, "SDA3"),
	1558	MTK_FUNCTION(3, "GPS_PPS"),
	1559	MTK_FUNCTION(4, "SCP_SDA0"),
	1560	MTK_FUNCTION(5, "SCP_SDA1"),
	1561	MTK_FUNCTION(7, "dbg_mon_b9")
	1562	),
	1563
	1564	MTK_PIN(
	1565	135, "GPIO135",
	1566	MTK_EINT_FUNCTION(0, 135),
	1567	DRV_GRP4,
	1568	MTK_FUNCTION(0, "GPIO135"),
	1569	MTK_FUNCTION(1, "SCL4"),
	1570	MTK_FUNCTION(2, "TP_UTXD1_AO"),
	1571	MTK_FUNCTION(3, "UTXD1"),
	1572	MTK_FUNCTION(4, "SCP_SCL0"),
	1573	MTK_FUNCTION(5, "SCP_SCL1"),
	1574	MTK_FUNCTION(7, "dbg_mon_b10")
	1575	),
	1576
	1577	MTK_PIN(
	1578	136, "GPIO136",
	1579	MTK_EINT_FUNCTION(0, 136),
	1580	DRV_GRP4,
	1581	MTK_FUNCTION(0, "GPIO136"),
	1582	MTK_FUNCTION(1, "SDA4"),
	1583	MTK_FUNCTION(2, "TP_URXD1_AO"),
	1584	MTK_FUNCTION(3, "URXD1"),
	1585	MTK_FUNCTION(4, "SCP_SDA0"),
	1586	MTK_FUNCTION(5, "SCP_SDA1"),
	1587	MTK_FUNCTION(7, "dbg_mon_b11")
	1588	),
	1589
	1590	MTK_PIN(
	1591	137, "GPIO137",
	1592	MTK_EINT_FUNCTION(0, 137),
	1593	DRV_GRP4,
	1594	MTK_FUNCTION(0, "GPIO137"),
	1595	MTK_FUNCTION(1, "SCL5"),
	1596	MTK_FUNCTION(2, "UTXD2"),
	1597	MTK_FUNCTION(3, "UCTS1"),
	1598	MTK_FUNCTION(4, "SCP_SCL0"),
	1599	MTK_FUNCTION(5, "SCP_SCL1")
	1600	),
	1601
	1602	MTK_PIN(
	1603	138, "GPIO138",
	1604	MTK_EINT_FUNCTION(0, 138),
	1605	DRV_GRP4,
	1606	MTK_FUNCTION(0, "GPIO138"),
	1607	MTK_FUNCTION(1, "SDA5"),
	1608	MTK_FUNCTION(2, "URXD2"),
	1609	MTK_FUNCTION(3, "URTS1"),
	1610	MTK_FUNCTION(4, "SCP_SDA0"),
	1611	MTK_FUNCTION(5, "SCP_SDA1")
	1612	),
	1613
	1614	MTK_PIN(
	1615	139, "GPIO139",
	1616	MTK_EINT_FUNCTION(0, 139),
	1617	DRV_GRP4,
	1618	MTK_FUNCTION(0, "GPIO139"),
	1619	MTK_FUNCTION(1, "SCL6"),
	1620	MTK_FUNCTION(2, "UTXD1"),
	1621	MTK_FUNCTION(3, "TP_UTXD1_AO"),
	1622	MTK_FUNCTION(4, "SCP_SCL0"),
	1623	MTK_FUNCTION(5, "SCP_SCL1"),
	1624	MTK_FUNCTION(7, "dbg_mon_b12")
	1625	),
	1626
	1627	MTK_PIN(
	1628	140, "GPIO140",
	1629	MTK_EINT_FUNCTION(0, 140),
	1630	DRV_GRP4,
	1631	MTK_FUNCTION(0, "GPIO140"),
	1632	MTK_FUNCTION(1, "SDA6"),
	1633	MTK_FUNCTION(2, "URXD1"),
	1634	MTK_FUNCTION(3, "TP_URXD1_AO"),
	1635	MTK_FUNCTION(4, "SCP_SDA0"),
	1636	MTK_FUNCTION(5, "SCP_SDA1"),
	1637	MTK_FUNCTION(7, "dbg_mon_b13")
	1638	),
	1639
	1640	MTK_PIN(
	1641	141, "GPIO141",
	1642	MTK_EINT_FUNCTION(0, 141),
	1643	DRV_GRP4,
	1644	MTK_FUNCTION(0, "GPIO141"),
	1645	MTK_FUNCTION(1, "SCL7"),
	1646	MTK_FUNCTION(2, "URTS0"),
	1647	MTK_FUNCTION(3, "TP_URTS1_AO"),
	1648	MTK_FUNCTION(4, "SCP_SCL0"),
	1649	MTK_FUNCTION(5, "SCP_SCL1"),
	1650	MTK_FUNCTION(6, "UDI_TCK"),
	1651	MTK_FUNCTION(7, "dbg_mon_b14")
	1652	),
	1653
	1654	MTK_PIN(
	1655	142, "GPIO142",
	1656	MTK_EINT_FUNCTION(0, 142),
	1657	DRV_GRP4,
	1658	MTK_FUNCTION(0, "GPIO142"),
	1659	MTK_FUNCTION(1, "SDA7"),
	1660	MTK_FUNCTION(2, "UCTS0"),
	1661	MTK_FUNCTION(3, "TP_UCTS1_AO"),
	1662	MTK_FUNCTION(4, "SCP_SDA0"),
	1663	MTK_FUNCTION(5, "SCP_SDA1")
	1664	),
	1665
	1666	MTK_PIN(
	1667	143, "GPIO143",
	1668	MTK_EINT_FUNCTION(0, 143),
	1669	DRV_GRP4,
	1670	MTK_FUNCTION(0, "GPIO143"),
	1671	MTK_FUNCTION(1, "SCL8"),
	1672	MTK_FUNCTION(4, "SCP_SCL0"),
	1673	MTK_FUNCTION(5, "SCP_SCL1"),
	1674	MTK_FUNCTION(7, "dbg_mon_b16")
	1675	),
	1676
	1677	MTK_PIN(
	1678	144, "GPIO144",
	1679	MTK_EINT_FUNCTION(0, 144),
	1680	DRV_GRP4,
	1681	MTK_FUNCTION(0, "GPIO144"),
	1682	MTK_FUNCTION(1, "SDA8"),
	1683	MTK_FUNCTION(4, "SCP_SDA0"),
	1684	MTK_FUNCTION(5, "SCP_SDA1"),
	1685	MTK_FUNCTION(7, "dbg_mon_b17")
	1686	),
	1687
	1688	MTK_PIN(
	1689	145, "GPIO145",
	1690	MTK_EINT_FUNCTION(0, 145),
	1691	DRV_GRP4,
	1692	MTK_FUNCTION(0, "GPIO145"),
	1693	MTK_FUNCTION(1, "SCL9"),
	1694	MTK_FUNCTION(2, "CMVREF1"),
	1695	MTK_FUNCTION(3, "GPS_PPS"),
	1696	MTK_FUNCTION(4, "SCP_SCL0"),
	1697	MTK_FUNCTION(5, "SCP_SCL1"),
	1698	MTK_FUNCTION(7, "dbg_mon_b18")
	1699	),
	1700
	1701	MTK_PIN(
	1702	146, "GPIO146",
	1703	MTK_EINT_FUNCTION(0, 146),
	1704	DRV_GRP4,
	1705	MTK_FUNCTION(0, "GPIO146"),
	1706	MTK_FUNCTION(1, "SDA9"),
	1707	MTK_FUNCTION(2, "CMVREF0"),
	1708	MTK_FUNCTION(4, "SCP_SDA0"),
	1709	MTK_FUNCTION(5, "SCP_SDA1"),
	1710	MTK_FUNCTION(7, "dbg_mon_b19")
	1711	),
	1712
	1713	MTK_PIN(
	1714	147, "GPIO147",
	1715	MTK_EINT_FUNCTION(0, 147),
	1716	DRV_GRP4,
	1717	MTK_FUNCTION(0, "GPIO147"),
	1718	MTK_FUNCTION(1, "CMFLASH0"),
	1719	MTK_FUNCTION(2, "LVTS_SDI"),
	1720	MTK_FUNCTION(3, "DPI_DATA12"),
	1721	MTK_FUNCTION(4, "TP_GPIO0_AO"),
	1722	MTK_FUNCTION(5, "ANT_SEL3"),
	1723	MTK_FUNCTION(6, "DFD_TCK_XI"),
	1724	MTK_FUNCTION(7, "dbg_mon_b20")
	1725	),
	1726
	1727	MTK_PIN(
	1728	148, "GPIO148",
	1729	MTK_EINT_FUNCTION(0, 148),
	1730	DRV_GRP4,
	1731	MTK_FUNCTION(0, "GPIO148"),
	1732	MTK_FUNCTION(1, "CMFLASH1"),
	1733	MTK_FUNCTION(2, "LVTS_SCF"),
	1734	MTK_FUNCTION(3, "DPI_DATA13"),
	1735	MTK_FUNCTION(4, "TP_GPIO1_AO"),
	1736	MTK_FUNCTION(5, "ANT_SEL4"),
	1737	MTK_FUNCTION(6, "DFD_TMS"),
	1738	MTK_FUNCTION(7, "dbg_mon_b21")
	1739	),
	1740
	1741	MTK_PIN(
	1742	149, "GPIO149",
	1743	MTK_EINT_FUNCTION(0, 149),
	1744	DRV_GRP4,
	1745	MTK_FUNCTION(0, "GPIO149"),
	1746	MTK_FUNCTION(1, "CMFLASH2"),
	1747	MTK_FUNCTION(2, "CLKM0"),
	1748	MTK_FUNCTION(3, "DPI_DATA14"),
	1749	MTK_FUNCTION(4, "TP_GPIO2_AO"),
	1750	MTK_FUNCTION(5, "ANT_SEL5"),
	1751	MTK_FUNCTION(6, "DFD_TDI"),
	1752	MTK_FUNCTION(7, "dbg_mon_b22")
	1753	),
	1754
	1755	MTK_PIN(
	1756	150, "GPIO150",
	1757	MTK_EINT_FUNCTION(0, 150),
	1758	DRV_GRP4,
	1759	MTK_FUNCTION(0, "GPIO150"),
	1760	MTK_FUNCTION(2, "CLKM1"),
	1761	MTK_FUNCTION(3, "DPI_DATA15"),
	1762	MTK_FUNCTION(4, "TP_GPIO3_AO"),
	1763	MTK_FUNCTION(5, "ANT_SEL6"),
	1764	MTK_FUNCTION(6, "DFD_TDO"),
	1765	MTK_FUNCTION(7, "dbg_mon_b23")
	1766	),
	1767
	1768	MTK_PIN(
	1769	151, "GPIO151",
	1770	MTK_EINT_FUNCTION(0, 151),
	1771	DRV_GRP4,
	1772	MTK_FUNCTION(0, "GPIO151"),
	1773	MTK_FUNCTION(1, "GPS_L1_ELNA_EN"),
	1774	MTK_FUNCTION(2, "CLKM2"),
	1775	MTK_FUNCTION(3, "DPI_DATA16"),
	1776	MTK_FUNCTION(4, "TP_GPIO4_AO"),
	1777	MTK_FUNCTION(5, "ANT_SEL7"),
	1778	MTK_FUNCTION(6, "UDI_TMS"),
	1779	MTK_FUNCTION(7, "dbg_mon_b24")
	1780	),
	1781
	1782	MTK_PIN(
	1783	152, "GPIO152",
	1784	MTK_EINT_FUNCTION(0, 152),
	1785	DRV_GRP4,
	1786	MTK_FUNCTION(0, "GPIO152"),
	1787	MTK_FUNCTION(2, "CLKM3"),
	1788	MTK_FUNCTION(3, "DPI_DATA17"),
	1789	MTK_FUNCTION(4, "TP_GPIO5_AO")
	1790	),
	1791
	1792	MTK_PIN(
	1793	153, "GPIO153",
	1794	MTK_EINT_FUNCTION(0, 153),
	1795	DRV_GRP4,
	1796	MTK_FUNCTION(0, "GPIO153"),
	1797	MTK_FUNCTION(1, "CONN_TCXOENA_REQ"),
	1798	MTK_FUNCTION(3, "DPI_DATA18"),
	1799	MTK_FUNCTION(4, "TP_GPIO6_AO"),
	1800	MTK_FUNCTION(6, "UDI_TDI"),
	1801	MTK_FUNCTION(7, "dbg_mon_b26")
	1802	),
	1803
	1804	MTK_PIN(
	1805	154, "GPIO154",
	1806	MTK_EINT_FUNCTION(0, 154),
	1807	DRV_GRP4,
	1808	MTK_FUNCTION(0, "GPIO154"),
	1809	MTK_FUNCTION(1, "PWM0"),
	1810	MTK_FUNCTION(2, "CMVREF2"),
	1811	MTK_FUNCTION(3, "DPI_DATA19"),
	1812	MTK_FUNCTION(4, "TP_GPIO7_AO"),
	1813	MTK_FUNCTION(6, "UDI_TDO"),
	1814	MTK_FUNCTION(7, "dbg_mon_b27")
	1815	),
	1816
	1817	MTK_PIN(
	1818	155, "GPIO155",
	1819	MTK_EINT_FUNCTION(0, 155),
	1820	DRV_GRP4,
	1821	MTK_FUNCTION(0, "GPIO155"),
	1822	MTK_FUNCTION(1, "PWM1"),
	1823	MTK_FUNCTION(2, "CMVREF1"),
	1824	MTK_FUNCTION(3, "DPI_DATA20"),
	1825	MTK_FUNCTION(6, "UDI_NTRST"),
	1826	MTK_FUNCTION(7, "dbg_mon_b28")
	1827	),
	1828
	1829	MTK_PIN(
	1830	156, "GPIO156",
	1831	MTK_EINT_FUNCTION(0, 156),
	1832	DRV_GRP4,
	1833	MTK_FUNCTION(0, "GPIO156"),
	1834	MTK_FUNCTION(1, "PWM2"),
	1835	MTK_FUNCTION(2, "CMVREF0"),
	1836	MTK_FUNCTION(3, "DPI_DATA21")
	1837	),
	1838
	1839	MTK_PIN(
	1840	157, "GPIO157",
	1841	MTK_EINT_FUNCTION(0, 157),
	1842	DRV_GRP4,
	1843	MTK_FUNCTION(0, "GPIO157"),
	1844	MTK_FUNCTION(1, "PWRAP_SPI0_CSN")
	1845	),
	1846
	1847	MTK_PIN(
	1848	158, "GPIO158",
	1849	MTK_EINT_FUNCTION(0, 158),
	1850	DRV_GRP4,
	1851	MTK_FUNCTION(0, "GPIO158"),
	1852	MTK_FUNCTION(1, "PWRAP_SPI0_CK")
	1853	),
	1854
	1855	MTK_PIN(
	1856	159, "GPIO159",
	1857	MTK_EINT_FUNCTION(0, 159),
	1858	DRV_GRP4,
	1859	MTK_FUNCTION(0, "GPIO159"),
	1860	MTK_FUNCTION(1, "PWRAP_SPI0_MO"),
	1861	MTK_FUNCTION(2, "PWRAP_SPI0_MI")
	1862	),
	1863
	1864	MTK_PIN(
	1865	160, "GPIO160",
	1866	MTK_EINT_FUNCTION(0, 160),
	1867	DRV_GRP4,
	1868	MTK_FUNCTION(0, "GPIO160"),
	1869	MTK_FUNCTION(1, "PWRAP_SPI0_MI"),
	1870	MTK_FUNCTION(2, "PWRAP_SPI0_MO")
	1871	),
	1872
	1873	MTK_PIN(
	1874	161, "GPIO161",
	1875	MTK_EINT_FUNCTION(0, 161),
	1876	DRV_GRP4,
	1877	MTK_FUNCTION(0, "GPIO161"),
	1878	MTK_FUNCTION(1, "SRCLKENA0")
	1879	),
	1880
	1881	MTK_PIN(
	1882	162, "GPIO162",
	1883	MTK_EINT_FUNCTION(0, 162),
	1884	DRV_GRP4,
	1885	MTK_FUNCTION(0, "GPIO162"),
	1886	MTK_FUNCTION(1, "SRCLKENA1"),
	1887	MTK_FUNCTION(7, "dbg_mon_a31")
	1888	),
	1889
	1890	MTK_PIN(
	1891	163, "GPIO163",
	1892	MTK_EINT_FUNCTION(0, 163),
	1893	DRV_GRP4,
	1894	MTK_FUNCTION(0, "GPIO163"),
	1895	MTK_FUNCTION(1, "SCP_VREQ_VAO"),
	1896	MTK_FUNCTION(2, "DVFSRC_EXT_REQ")
	1897	),
	1898
	1899	MTK_PIN(
	1900	164, "GPIO164",
	1901	MTK_EINT_FUNCTION(0, 164),
	1902	DRV_GRP4,
	1903	MTK_FUNCTION(0, "GPIO164"),
	1904	MTK_FUNCTION(1, "RTC32K_CK")
	1905	),
	1906
	1907	MTK_PIN(
	1908	165, "GPIO165",
	1909	MTK_EINT_FUNCTION(0, 165),
	1910	DRV_GRP4,
	1911	MTK_FUNCTION(0, "GPIO165"),
	1912	MTK_FUNCTION(1, "WATCHDOG")
	1913	),
	1914
	1915	MTK_PIN(
	1916	166, "GPIO166",
	1917	MTK_EINT_FUNCTION(0, 166),
	1918	DRV_GRP4,
	1919	MTK_FUNCTION(0, "GPIO166"),
	1920	MTK_FUNCTION(1, "AUD_CLK_MOSI"),
	1921	MTK_FUNCTION(2, "AUD_CLK_MISO"),
	1922	MTK_FUNCTION(3, "I2S1_MCK")
	1923	),
	1924
	1925	MTK_PIN(
	1926	167, "GPIO167",
	1927	MTK_EINT_FUNCTION(0, 167),
	1928	DRV_GRP4,
	1929	MTK_FUNCTION(0, "GPIO167"),
	1930	MTK_FUNCTION(1, "AUD_SYNC_MOSI"),
	1931	MTK_FUNCTION(2, "AUD_SYNC_MISO"),
	1932	MTK_FUNCTION(3, "I2S1_BCK")
	1933	),
	1934
	1935	MTK_PIN(
	1936	168, "GPIO168",
	1937	MTK_EINT_FUNCTION(0, 168),
	1938	DRV_GRP4,
	1939	MTK_FUNCTION(0, "GPIO168"),
	1940	MTK_FUNCTION(1, "AUD_DAT_MOSI0"),
	1941	MTK_FUNCTION(2, "AUD_DAT_MISO0"),
	1942	MTK_FUNCTION(3, "I2S1_LRCK")
	1943	),
	1944
	1945	MTK_PIN(
	1946	169, "GPIO169",
	1947	MTK_EINT_FUNCTION(0, 169),
	1948	DRV_GRP4,
	1949	MTK_FUNCTION(0, "GPIO169"),
	1950	MTK_FUNCTION(1, "AUD_DAT_MOSI1"),
	1951	MTK_FUNCTION(2, "AUD_DAT_MISO1"),
	1952	MTK_FUNCTION(3, "I2S1_DO")
	1953	),
	1954
	1955	MTK_PIN(
	1956	170, "GPIO170",
	1957	MTK_EINT_FUNCTION(0, 170),
	1958	DRV_GRP4,
	1959	MTK_FUNCTION(0, "GPIO170"),
	1960	MTK_FUNCTION(1, "AUD_CLK_MISO"),
	1961	MTK_FUNCTION(2, "AUD_CLK_MOSI"),
	1962	MTK_FUNCTION(3, "I2S2_MCK")
	1963	),
	1964
	1965	MTK_PIN(
	1966	171, "GPIO171",
	1967	MTK_EINT_FUNCTION(0, 171),
	1968	DRV_GRP4,
	1969	MTK_FUNCTION(0, "GPIO171"),
	1970	MTK_FUNCTION(1, "AUD_SYNC_MISO"),
	1971	MTK_FUNCTION(2, "AUD_SYNC_MOSI"),
	1972	MTK_FUNCTION(3, "I2S2_BCK")
	1973	),
	1974
	1975	MTK_PIN(
	1976	172, "GPIO172",
	1977	MTK_EINT_FUNCTION(0, 172),
	1978	DRV_GRP4,
	1979	MTK_FUNCTION(0, "GPIO172"),
	1980	MTK_FUNCTION(1, "AUD_DAT_MISO0"),
	1981	MTK_FUNCTION(2, "AUD_DAT_MOSI0"),
	1982	MTK_FUNCTION(3, "I2S2_LRCK"),
	1983	MTK_FUNCTION(4, "VOW_DAT_MISO")
	1984	),
	1985
	1986	MTK_PIN(
	1987	173, "GPIO173",
	1988	MTK_EINT_FUNCTION(0, 173),
	1989	DRV_GRP4,
	1990	MTK_FUNCTION(0, "GPIO173"),
	1991	MTK_FUNCTION(1, "AUD_DAT_MISO1"),
	1992	MTK_FUNCTION(2, "AUD_DAT_MOSI1"),
	1993	MTK_FUNCTION(3, "I2S2_DI"),
	1994	MTK_FUNCTION(4, "VOW_CLK_MISO")
	1995	),
	1996
	1997	MTK_PIN(
	1998	174, "GPIO174",
	1999	MTK_EINT_FUNCTION(0, 174),
	2000	DRV_GRP4,
	2001	MTK_FUNCTION(0, "GPIO174"),
	2002	MTK_FUNCTION(1, "CONN_TOP_CLK"),
	2003	MTK_FUNCTION(2, "AUXIF_CLK"),
	2004	MTK_FUNCTION(3, "DFD_TCK_XI"),
	2005	MTK_FUNCTION(7, "dbg_mon_b3")
	2006	),
	2007
	2008	MTK_PIN(
	2009	175, "GPIO175",
	2010	MTK_EINT_FUNCTION(0, 175),
	2011	DRV_GRP4,
	2012	MTK_FUNCTION(0, "GPIO175"),
	2013	MTK_FUNCTION(1, "CONN_TOP_DATA"),
	2014	MTK_FUNCTION(2, "AUXIF_ST"),
	2015	MTK_FUNCTION(3, "DFD_TMS"),
	2016	MTK_FUNCTION(7, "dbg_mon_b15")
	2017	),
	2018
	2019	MTK_PIN(
	2020	176, "GPIO176",
	2021	MTK_EINT_FUNCTION(0, 176),
	2022	DRV_GRP4,
	2023	MTK_FUNCTION(0, "GPIO176"),
	2024	MTK_FUNCTION(1, "CONN_BT_CLK"),
	2025	MTK_FUNCTION(3, "DFD_TDI"),
	2026	MTK_FUNCTION(7, "dbg_mon_b2")
	2027	),
	2028
	2029	MTK_PIN(
	2030	177, "GPIO177",
	2031	MTK_EINT_FUNCTION(0, 177),
	2032	DRV_GRP4,
	2033	MTK_FUNCTION(0, "GPIO177"),
	2034	MTK_FUNCTION(1, "CONN_BT_DATA"),
	2035	MTK_FUNCTION(3, "DFD_TDO")
	2036	),
	2037
	2038	MTK_PIN(
	2039	178, "GPIO178",
	2040	MTK_EINT_FUNCTION(0, 178),
	2041	DRV_GRP4,
	2042	MTK_FUNCTION(0, "GPIO178"),
	2043	MTK_FUNCTION(1, "CONN_HRST_B"),
	2044	MTK_FUNCTION(3, "UDI_TMS"),
	2045	MTK_FUNCTION(7, "dbg_mon_b25")
	2046	),
	2047
	2048	MTK_PIN(
	2049	179, "GPIO179",
	2050	MTK_EINT_FUNCTION(0, 179),
	2051	DRV_GRP4,
	2052	MTK_FUNCTION(0, "GPIO179"),
	2053	MTK_FUNCTION(1, "CONN_WB_PTA"),
	2054	MTK_FUNCTION(3, "UDI_TCK"),
	2055	MTK_FUNCTION(7, "dbg_mon_b29")
	2056	),
	2057
	2058	MTK_PIN(
	2059	180, "GPIO180",
	2060	MTK_EINT_FUNCTION(0, 180),
	2061	DRV_GRP4,
	2062	MTK_FUNCTION(0, "GPIO180"),
	2063	MTK_FUNCTION(1, "CONN_WF_CTRL0"),
	2064	MTK_FUNCTION(3, "UDI_TDI")
	2065	),
	2066
	2067	MTK_PIN(
	2068	181, "GPIO181",
	2069	MTK_EINT_FUNCTION(0, 181),
	2070	DRV_GRP4,
	2071	MTK_FUNCTION(0, "GPIO181"),
	2072	MTK_FUNCTION(1, "CONN_WF_CTRL1"),
	2073	MTK_FUNCTION(3, "UDI_TDO")
	2074	),
	2075
	2076	MTK_PIN(
	2077	182, "GPIO182",
	2078	MTK_EINT_FUNCTION(0, 182),
	2079	DRV_GRP4,
	2080	MTK_FUNCTION(0, "GPIO182"),
	2081	MTK_FUNCTION(1, "CONN_WF_CTRL2"),
	2082	MTK_FUNCTION(3, "UDI_NTRST")
	2083	),
	2084
	2085	MTK_PIN(
	2086	183, "GPIO183",
	2087	MTK_EINT_FUNCTION(0, 183),
	2088	DRV_GRP4,
	2089	MTK_FUNCTION(0, "GPIO183"),
	2090	MTK_FUNCTION(1, "SPMI_SCL")
	2091	),
	2092
	2093	MTK_PIN(
	2094	184, "GPIO184",
	2095	MTK_EINT_FUNCTION(0, 184),
	2096	DRV_GRP4,
	2097	MTK_FUNCTION(0, "GPIO184"),
	2098	MTK_FUNCTION(1, "SPMI_SDA")
	2099	),
	2100
	2101	MTK_PIN(
	2102	185, "GPIO185",
	2103	MTK_EINT_FUNCTION(0, 197),
	2104	DRV_FIXED,
	2105	MTK_FUNCTION(0, NULL)
	2106	),
	2107
	2108	MTK_PIN(
	2109	186, "GPIO186",
	2110	MTK_EINT_FUNCTION(0, 198),
	2111	DRV_FIXED,
	2112	MTK_FUNCTION(0, NULL)
	2113	),
	2114
	2115	MTK_PIN(
	2116	187, "GPIO187",
	2117	MTK_EINT_FUNCTION(0, 199),
	2118	DRV_FIXED,
	2119	MTK_FUNCTION(0, NULL)
	2120	),
	2121
	2122	MTK_PIN(
	2123	188, "GPIO188",
	2124	MTK_EINT_FUNCTION(0, 200),
	2125	DRV_FIXED,
	2126	MTK_FUNCTION(0, NULL)
	2127	),
	2128
	2129	MTK_PIN(
	2130	189, "GPIO189",
	2131	MTK_EINT_FUNCTION(0, 201),
	2132	DRV_FIXED,
	2133	MTK_FUNCTION(0, NULL)
	2134	),
	2135
	2136	MTK_PIN(
	2137	190, "GPIO190",
	2138	MTK_EINT_FUNCTION(0, 202),
	2139	DRV_FIXED,
	2140	MTK_FUNCTION(0, NULL)
	2141	),
	2142
	2143	MTK_PIN(
	2144	191, "GPIO191",
	2145	MTK_EINT_FUNCTION(0, 203),
	2146	DRV_FIXED,
	2147	MTK_FUNCTION(0, NULL)
	2148	),
	2149
	2150	MTK_PIN(
	2151	192, "GPIO192",
	2152	MTK_EINT_FUNCTION(0, 204),
	2153	DRV_FIXED,
	2154	MTK_FUNCTION(0, NULL)
	2155	),
	2156
	2157	MTK_PIN(
	2158	193, "GPIO193",
	2159	MTK_EINT_FUNCTION(0, 205),
	2160	DRV_FIXED,
	2161	MTK_FUNCTION(0, NULL)
	2162	),
	2163
	2164	MTK_PIN(
	2165	194, "GPIO194",
	2166	MTK_EINT_FUNCTION(0, 206),
	2167	DRV_FIXED,
	2168	MTK_FUNCTION(0, NULL)
	2169	),
	2170
	2171	MTK_PIN(
	2172	195, "GPIO195",
	2173	MTK_EINT_FUNCTION(0, 207),
	2174	DRV_FIXED,
	2175	MTK_FUNCTION(0, NULL)
	2176	),
	2177
	2178	MTK_PIN(
	2179	196, "GPIO196",
	2180	MTK_EINT_FUNCTION(0, 208),
	2181	DRV_FIXED,
	2182	MTK_FUNCTION(0, NULL)
	2183	)
	2184	};
	2185
	2186	#endif /* __PINCTRL_MTK_MT8186_H */

drivers/pinctrl/mediatek/pinctrl-paris.c+184−117

@@ -48,6 +48,53 @@ static const char * const mtk_gpio_functions[] = { · 47 unmodified lines
48	"func12", "func13", "func14", "func15",	48	"func12", "func13", "func14", "func15",
49	};	49	};
50		50
		51	/*
		52	* This section supports converting to/from custom MTK_PIN_CONFIG_DRV_ADV
		53	* and standard PIN_CONFIG_DRIVE_STRENGTH_UA pin configs.
		54	*
		55	* The custom value encodes three hardware bits as follows:
		56	*
		57	* \| Bits \|
		58	* \| 2 (E1) \| 1 (E0) \| 0 (EN) \| drive strength (uA)
		59	* ------------------------------------------------
		60	* \| x \| x \| 0 \| disabled, use standard drive strength
		61	* -------------------------------------
		62	* \| 0 \| 0 \| 1 \| 125 uA
		63	* \| 0 \| 1 \| 1 \| 250 uA
		64	* \| 1 \| 0 \| 1 \| 500 uA
		65	* \| 1 \| 1 \| 1 \| 1000 uA
		66	*/
		67	static const int mtk_drv_adv_uA[] = { 125, 250, 500, 1000 };
		68
		69	static int mtk_drv_adv_to_uA(int val)
		70	{
		71	/* This should never happen. */
		72	if (WARN_ON_ONCE(val < 0 \|\| val > 7))
		73	return -EINVAL;
		74
		75	/* Bit 0 simply enables this hardware part */
		76	if (!(val & BIT(0)))
		77	return -EINVAL;
		78
		79	return mtk_drv_adv_uA[(val >> 1)];
		80	}
		81
		82	static int mtk_drv_uA_to_adv(int val)
		83	{
		84	switch (val) {
		85	case 125:
		86	return 0x1;
		87	case 250:
		88	return 0x3;
		89	case 500:
		90	return 0x5;
		91	case 1000:
		92	return 0x7;
		93	}
		94
		95	return -EINVAL;
		96	}
		97
51	static int mtk_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,	98	static int mtk_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
52	struct pinctrl_gpio_range *range,	99	struct pinctrl_gpio_range *range,
53	unsigned int pin)	100	unsigned int pin)
@@ -79,41 +126,34 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctldev, · 25 unmodified lines
79	{	126	{
80	struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);	127	struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
81	u32 param = pinconf_to_config_param(*config);	128	u32 param = pinconf_to_config_param(*config);
82	int pullup, err, reg, ret = 1;	129	int pullup, reg, err = -ENOTSUPP, ret = 1;
83	const struct mtk_pin_desc *desc;	130	const struct mtk_pin_desc *desc;
84		131
85	if (pin >= hw->soc->npins) {	132	if (pin >= hw->soc->npins)
86	err = -EINVAL;	133	return -EINVAL;
87	goto out;	134
88	}
89	desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];	135	desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
90		136
91	switch (param) {	137	switch (param) {
92	case PIN_CONFIG_BIAS_DISABLE:	138	case PIN_CONFIG_BIAS_DISABLE:
93	case PIN_CONFIG_BIAS_PULL_UP:	139	case PIN_CONFIG_BIAS_PULL_UP:
94	case PIN_CONFIG_BIAS_PULL_DOWN:	140	case PIN_CONFIG_BIAS_PULL_DOWN:
95	if (hw->soc->bias_get_combo) {	141	if (!hw->soc->bias_get_combo)
96	err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret);	142	break;
97	if (err)	143	err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret);
98	goto out;	144	if (err)
99	if (param == PIN_CONFIG_BIAS_DISABLE) {	145	break;
100	if (ret == MTK_PUPD_SET_R1R0_00)	146	if (ret == MTK_PUPD_SET_R1R0_00)
101	ret = MTK_DISABLE;	147	ret = MTK_DISABLE;
102	} else if (param == PIN_CONFIG_BIAS_PULL_UP) {	148	if (param == PIN_CONFIG_BIAS_DISABLE) {
103	/* When desire to get pull-up value, return	149	if (ret != MTK_DISABLE)
104	* error if current setting is pull-down	150	err = -EINVAL;
105	*/	151	} else if (param == PIN_CONFIG_BIAS_PULL_UP) {
106	if (!pullup)	152	if (!pullup \|\| ret == MTK_DISABLE)
107	err = -EINVAL;	153	err = -EINVAL;
108	} else if (param == PIN_CONFIG_BIAS_PULL_DOWN) {	154	} else if (param == PIN_CONFIG_BIAS_PULL_DOWN) {
109	/* When desire to get pull-down value, return	155	if (pullup \|\| ret == MTK_DISABLE)
110	* error if current setting is pull-up	156	err = -EINVAL;
111	*/
112	if (pullup)
113	err = -EINVAL;
114	}
115	} else {
116	err = -ENOTSUPP;
117	}	157	}
118	break;	158	break;
119	case PIN_CONFIG_SLEW_RATE:	159	case PIN_CONFIG_SLEW_RATE:
@@ -123,7 +163,7 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctldev, · 3 unmodified lines
123	case PIN_CONFIG_OUTPUT_ENABLE:	163	case PIN_CONFIG_OUTPUT_ENABLE:
124	err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &ret);	164	err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &ret);
125	if (err)	165	if (err)
126	goto out;	166	break;
127	/* CONFIG Current direction return value	167	/* CONFIG Current direction return value
128	* ------------- ----------------- ----------------------	168	* ------------- ----------------- ----------------------
129	* OUTPUT_ENABLE output 1 (= HW value)	169	* OUTPUT_ENABLE output 1 (= HW value)
@@ -138,23 +178,48 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctldev, · 8 unmodified lines
138	case PIN_CONFIG_INPUT_SCHMITT_ENABLE:	178	case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
139	err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &ret);	179	err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &ret);
140	if (err)	180	if (err)
141	goto out;	181	break;
142	/* return error when in output mode	182	/* return error when in output mode
143	* because schmitt trigger only work in input mode	183	* because schmitt trigger only work in input mode
144	*/	184	*/
145	if (ret) {	185	if (ret) {
146	err = -EINVAL;	186	err = -EINVAL;
147	goto out;	187	break;
148	}	188	}
149		189
150	err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SMT, &ret);	190	err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SMT, &ret);
151
152	break;	191	break;
153	case PIN_CONFIG_DRIVE_STRENGTH:	192	case PIN_CONFIG_DRIVE_STRENGTH:
154	if (hw->soc->drive_get)	193	if (!hw->soc->drive_get)
155	err = hw->soc->drive_get(hw, desc, &ret);	194	break;
156	else	195
157	err = -ENOTSUPP;	196	if (hw->soc->adv_drive_get) {
		197	err = hw->soc->adv_drive_get(hw, desc, &ret);
		198	if (!err) {
		199	err = mtk_drv_adv_to_uA(ret);
		200	if (err > 0) {
		201	/* PIN_CONFIG_DRIVE_STRENGTH_UA used */
		202	err = -EINVAL;
		203	break;
		204	}
		205	}
		206	}
		207
		208	err = hw->soc->drive_get(hw, desc, &ret);
		209	break;
		210	case PIN_CONFIG_DRIVE_STRENGTH_UA:
		211	if (!hw->soc->adv_drive_get)
		212	break;
		213
		214	err = hw->soc->adv_drive_get(hw, desc, &ret);
		215	if (err)
		216	break;
		217	err = mtk_drv_adv_to_uA(ret);
		218	if (err < 0)
		219	break;
		220
		221	ret = err;
		222	err = 0;
158	break;	223	break;
159	case MTK_PIN_CONFIG_TDSEL:	224	case MTK_PIN_CONFIG_TDSEL:
160	case MTK_PIN_CONFIG_RDSEL:	225	case MTK_PIN_CONFIG_RDSEL:
@@ -164,23 +229,18 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctldev, · 3 unmodified lines
164	break;	229	break;
165	case MTK_PIN_CONFIG_PU_ADV:	230	case MTK_PIN_CONFIG_PU_ADV:
166	case MTK_PIN_CONFIG_PD_ADV:	231	case MTK_PIN_CONFIG_PD_ADV:
167	if (hw->soc->adv_pull_get) {	232	if (!hw->soc->adv_pull_get)
168	pullup = param == MTK_PIN_CONFIG_PU_ADV;	233	break;
169	err = hw->soc->adv_pull_get(hw, desc, pullup, &ret);	234	pullup = param == MTK_PIN_CONFIG_PU_ADV;
170	} else	235	err = hw->soc->adv_pull_get(hw, desc, pullup, &ret);
171	err = -ENOTSUPP;
172	break;	236	break;
173	case MTK_PIN_CONFIG_DRV_ADV:	237	case MTK_PIN_CONFIG_DRV_ADV:
174	if (hw->soc->adv_drive_get)	238	if (!hw->soc->adv_drive_get)
175	err = hw->soc->adv_drive_get(hw, desc, &ret);	239	break;
176	else	240	err = hw->soc->adv_drive_get(hw, desc, &ret);
177	err = -ENOTSUPP;
178	break;	241	break;
179	default:
180	err = -ENOTSUPP;
181	}	242	}
182		243
183	out:
184	if (!err)	244	if (!err)
185	*config = pinconf_to_config_packed(param, ret);	245	*config = pinconf_to_config_packed(param, ret);
186		246
@@ -188,38 +248,33 @@ out: · 1 unmodified line
188	}	248	}
189		249
190	static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,	250	static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
191	enum pin_config_param param,	251	enum pin_config_param param, u32 arg)
192	enum pin_config_param arg)
193	{	252	{
194	struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);	253	struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
195	const struct mtk_pin_desc *desc;	254	const struct mtk_pin_desc *desc;
196	int err = 0;	255	int err = -ENOTSUPP;
197	u32 reg;	256	u32 reg;
198		257
199	if (pin >= hw->soc->npins) {	258	if (pin >= hw->soc->npins)
200	err = -EINVAL;	259	return -EINVAL;
201	goto err;	260
202	}
203	desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];	261	desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
204		262
205	switch ((u32)param) {	263	switch ((u32)param) {
206	case PIN_CONFIG_BIAS_DISABLE:	264	case PIN_CONFIG_BIAS_DISABLE:
207	if (hw->soc->bias_set_combo)	265	if (!hw->soc->bias_set_combo)
208	err = hw->soc->bias_set_combo(hw, desc, 0, MTK_DISABLE);	266	break;
209	else	267	err = hw->soc->bias_set_combo(hw, desc, 0, MTK_DISABLE);
210	err = -ENOTSUPP;
211	break;	268	break;
212	case PIN_CONFIG_BIAS_PULL_UP:	269	case PIN_CONFIG_BIAS_PULL_UP:
213	if (hw->soc->bias_set_combo)	270	if (!hw->soc->bias_set_combo)
214	err = hw->soc->bias_set_combo(hw, desc, 1, arg);	271	break;
215	else	272	err = hw->soc->bias_set_combo(hw, desc, 1, arg);
216	err = -ENOTSUPP;
217	break;	273	break;
218	case PIN_CONFIG_BIAS_PULL_DOWN:	274	case PIN_CONFIG_BIAS_PULL_DOWN:
219	if (hw->soc->bias_set_combo)	275	if (!hw->soc->bias_set_combo)
220	err = hw->soc->bias_set_combo(hw, desc, 0, arg);	276	break;
221	else	277	err = hw->soc->bias_set_combo(hw, desc, 0, arg);
222	err = -ENOTSUPP;
223	break;	278	break;
224	case PIN_CONFIG_OUTPUT_ENABLE:	279	case PIN_CONFIG_OUTPUT_ENABLE:
225	err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT,	280	err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT,
@@ -228,7 +283,7 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, · 2 unmodified lines
228	* does not have SMT control	283	* does not have SMT control
229	*/	284	*/
230	if (err != -ENOTSUPP)	285	if (err != -ENOTSUPP)
231	goto err;	286	break;
232		287
233	err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,	288	err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
234	MTK_OUTPUT);	289	MTK_OUTPUT);
@@ -237,7 +292,7 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, · 2 unmodified lines
237	/* regard all non-zero value as enable */	292	/* regard all non-zero value as enable */
238	err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_IES, !!arg);	293	err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_IES, !!arg);
239	if (err)	294	if (err)
240	goto err;	295	break;
241		296
242	err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,	297	err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
243	MTK_INPUT);	298	MTK_INPUT);
@@ -250,7 +305,7 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, · 6 unmodified lines
250	err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO,	305	err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO,
251	arg);	306	arg);
252	if (err)	307	if (err)
253	goto err;	308	break;
254		309
255	err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,	310	err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
256	MTK_OUTPUT);	311	MTK_OUTPUT);
@@ -262,15 +317,23 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, · 5 unmodified lines
262	*/	317	*/
263	err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, !arg);	318	err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, !arg);
264	if (err)	319	if (err)
265	goto err;	320	break;
266		321
267	err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT, !!arg);	322	err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT, !!arg);
268	break;	323	break;
269	case PIN_CONFIG_DRIVE_STRENGTH:	324	case PIN_CONFIG_DRIVE_STRENGTH:
270	if (hw->soc->drive_set)	325	if (!hw->soc->drive_set)
271	err = hw->soc->drive_set(hw, desc, arg);	326	break;
272	else	327	err = hw->soc->drive_set(hw, desc, arg);
273	err = -ENOTSUPP;	328	break;
		329	case PIN_CONFIG_DRIVE_STRENGTH_UA:
		330	if (!hw->soc->adv_drive_set)
		331	break;
		332
		333	err = mtk_drv_uA_to_adv(arg);
		334	if (err < 0)
		335	break;
		336	err = hw->soc->adv_drive_set(hw, desc, err);
274	break;	337	break;
275	case MTK_PIN_CONFIG_TDSEL:	338	case MTK_PIN_CONFIG_TDSEL:
276	case MTK_PIN_CONFIG_RDSEL:	339	case MTK_PIN_CONFIG_RDSEL:
@@ -280,26 +343,19 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, · 3 unmodified lines
280	break;	343	break;
281	case MTK_PIN_CONFIG_PU_ADV:	344	case MTK_PIN_CONFIG_PU_ADV:
282	case MTK_PIN_CONFIG_PD_ADV:	345	case MTK_PIN_CONFIG_PD_ADV:
283	if (hw->soc->adv_pull_set) {	346	if (!hw->soc->adv_pull_set)
284	bool pullup;	347	break;
285		348	err = hw->soc->adv_pull_set(hw, desc,
286	pullup = param == MTK_PIN_CONFIG_PU_ADV;	349	(param == MTK_PIN_CONFIG_PU_ADV),
287	err = hw->soc->adv_pull_set(hw, desc, pullup,	350	arg);
288	arg);
289	} else
290	err = -ENOTSUPP;
291	break;	351	break;
292	case MTK_PIN_CONFIG_DRV_ADV:	352	case MTK_PIN_CONFIG_DRV_ADV:
293	if (hw->soc->adv_drive_set)	353	if (!hw->soc->adv_drive_set)
294	err = hw->soc->adv_drive_set(hw, desc, arg);	354	break;
295	else	355	err = hw->soc->adv_drive_set(hw, desc, arg);
296	err = -ENOTSUPP;
297	break;	356	break;
298	default:
299	err = -ENOTSUPP;
300	}	357	}
301		358
302	err:
303	return err;	359	return err;
304	}	360	}
305		361
@@ -586,6 +642,9 @@ ssize_t mtk_pctrl_show_one_pin(struct mtk_pinctrl *hw, · 280 unmodified lines
586	if (gpio >= hw->soc->npins)	642	if (gpio >= hw->soc->npins)
587	return -EINVAL;	643	return -EINVAL;
588		644
		645	if (mtk_is_virt_gpio(hw, gpio))
		646	return -EINVAL;
		647
589	desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];	648	desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
590	pinmux = mtk_pctrl_get_pinmux(hw, gpio);	649	pinmux = mtk_pctrl_get_pinmux(hw, gpio);
591	if (pinmux >= hw->soc->nfuncs)	650	if (pinmux >= hw->soc->nfuncs)
@@ -639,14 +698,10 @@ ssize_t mtk_pctrl_show_one_pin(struct mtk_pinctrl *hw, · 47 unmodified lines
639	pullen,	698	pullen,
640	pullup);	699	pullup);
641		700
642	if (r1 != -1) {	701	if (r1 != -1)
643	len += scnprintf(buf + len, buf_len - len, " (%1d %1d)\n",	702	len += scnprintf(buf + len, buf_len - len, " (%1d %1d)", r1, r0);
644	r1, r0);	703	else if (rsel != -1)
645	} else if (rsel != -1) {	704	len += scnprintf(buf + len, buf_len - len, " (%1d)", rsel);
646	len += scnprintf(buf + len, buf_len - len, " (%1d)\n", rsel);
647	} else {
648	len += scnprintf(buf + len, buf_len - len, "\n");
649	}
650		705
651	return len;	706	return len;
652	}	707	}
@@ -737,10 +792,10 @@ static int mtk_pconf_group_get(struct pinctrl_dev *pctldev, unsigned group, · 84 unmodified lines
737	unsigned long *config)	792	unsigned long *config)
738	{	793	{
739	struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);	794	struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
		795	struct mtk_pinctrl_group *grp = &hw->groups[group];
740		796
741	*config = hw->groups[group].config;	797	/* One pin per group only */
742		798	return mtk_pinconf_get(pctldev, grp->pin, config);
743	return 0;
744	}	799	}
745		800
746	static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,	801	static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
@@ -748,6 +803,8 @@ static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, · 1 unmodified line
748	{	803	{
749	struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);	804	struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
750	struct mtk_pinctrl_group *grp = &hw->groups[group];	805	struct mtk_pinctrl_group *grp = &hw->groups[group];
		806	bool drive_strength_uA_found = false;
		807	bool adv_drve_strength_found = false;
751	int i, ret;	808	int i, ret;
752		809
753	for (i = 0; i < num_configs; i++) {	810	for (i = 0; i < num_configs; i++) {
@@ -757,9 +814,21 @@ static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, · 3 unmodified lines
757	if (ret < 0)	814	if (ret < 0)
758	return ret;	815	return ret;
759		816
760	grp->config = configs[i];	817	if (pinconf_to_config_param(configs[i]) == PIN_CONFIG_DRIVE_STRENGTH_UA)
		818	drive_strength_uA_found = true;
		819	if (pinconf_to_config_param(configs[i]) == MTK_PIN_CONFIG_DRV_ADV)
		820	adv_drve_strength_found = true;
761	}	821	}
762		822
		823	/*
		824	* Disable advanced drive strength mode if drive-strength-microamp
		825	* is not set. However, mediatek,drive-strength-adv takes precedence
		826	* as its value can explicitly request the mode be enabled or not.
		827	*/
		828	if (hw->soc->adv_drive_set && !drive_strength_uA_found &&
		829	!adv_drve_strength_found)
		830	hw->soc->adv_drive_set(hw, &hw->soc->pins[grp->pin], 0);
		831
763	return 0;	832	return 0;
764	}	833	}
765		834
@@ -952,9 +1021,9 @@ static int mtk_pctrl_build_state(struct platform_device *pdev) · 186 unmodified lines
952	return 0;	1021	return 0;
953	}	1022	}
954		1023
955	int mtk_paris_pinctrl_probe(struct platform_device *pdev,	1024	int mtk_paris_pinctrl_probe(struct platform_device *pdev)
956	const struct mtk_pin_soc *soc)
957	{	1025	{
		1026	struct device *dev = &pdev->dev;
958	struct pinctrl_pin_desc *pins;	1027	struct pinctrl_pin_desc *pins;
959	struct mtk_pinctrl *hw;	1028	struct mtk_pinctrl *hw;
960	int err, i;	1029	int err, i;
@@ -964,14 +1033,16 @@ int mtk_paris_pinctrl_probe(struct platform_device *pdev, · 3 unmodified lines
964	return -ENOMEM;	1033	return -ENOMEM;
965		1034
966	platform_set_drvdata(pdev, hw);	1035	platform_set_drvdata(pdev, hw);
967	hw->soc = soc;	1036
		1037	hw->soc = device_get_match_data(dev);
		1038	if (!hw->soc)
		1039	return -ENOENT;
		1040
968	hw->dev = &pdev->dev;	1041	hw->dev = &pdev->dev;
969		1042
970	if (!hw->soc->nbase_names) {	1043	if (!hw->soc->nbase_names)
971	dev_err(&pdev->dev,	1044	return dev_err_probe(dev, -EINVAL,
972	"SoC should be assigned at least one register base\n");	1045	"SoC should be assigned at least one register base\n");
973	return -EINVAL;
974	}
975		1046
976	hw->base = devm_kmalloc_array(&pdev->dev, hw->soc->nbase_names,	1047	hw->base = devm_kmalloc_array(&pdev->dev, hw->soc->nbase_names,
977	sizeof(*hw->base), GFP_KERNEL);	1048	sizeof(*hw->base), GFP_KERNEL);
@@ -988,7 +1059,7 @@ int mtk_paris_pinctrl_probe(struct platform_device *pdev, · 10 unmodified lines
988	hw->nbase = hw->soc->nbase_names;	1059	hw->nbase = hw->soc->nbase_names;
989		1060
990	if (of_find_property(hw->dev->of_node,	1061	if (of_find_property(hw->dev->of_node,
991	"mediatek,rsel_resistance_in_si_unit", NULL))	1062	"mediatek,rsel-resistance-in-si-unit", NULL))
992	hw->rsel_si_unit = true;	1063	hw->rsel_si_unit = true;
993	else	1064	else
994	hw->rsel_si_unit = false;	1065	hw->rsel_si_unit = false;
@@ -996,10 +1067,8 @@ int mtk_paris_pinctrl_probe(struct platform_device *pdev, · 1 unmodified line
996	spin_lock_init(&hw->lock);	1067	spin_lock_init(&hw->lock);
997		1068
998	err = mtk_pctrl_build_state(pdev);	1069	err = mtk_pctrl_build_state(pdev);
999	if (err) {	1070	if (err)
1000	dev_err(&pdev->dev, "build state failed: %d\n", err);	1071	return dev_err_probe(dev, err, "build state failed\n");
1001	return -EINVAL;
1002	}
1003		1072
1004	/* Copy from internal struct mtk_pin_desc to register to the core */	1073	/* Copy from internal struct mtk_pin_desc to register to the core */
1005	pins = devm_kmalloc_array(&pdev->dev, hw->soc->npins, sizeof(*pins),	1074	pins = devm_kmalloc_array(&pdev->dev, hw->soc->npins, sizeof(*pins),
@@ -1037,10 +1106,8 @@ int mtk_paris_pinctrl_probe(struct platform_device *pdev, · 31 unmodified lines
1037		1106
1038	/* Build gpiochip should be after pinctrl_enable is done */	1107	/* Build gpiochip should be after pinctrl_enable is done */
1039	err = mtk_build_gpiochip(hw);	1108	err = mtk_build_gpiochip(hw);
1040	if (err) {	1109	if (err)
1041	dev_err(&pdev->dev, "Failed to add gpio_chip\n");	1110	return dev_err_probe(dev, err, "Failed to add gpio_chip\n");
1042	return err;
1043	}
1044		1111
1045	platform_set_drvdata(pdev, hw);	1112	platform_set_drvdata(pdev, hw);
1046		1113

drivers/pinctrl/mediatek/pinctrl-paris.h+1−2

@@ -57,8 +57,7 @@ · 56 unmodified lines
57	id##_funcs, \	57	id##_funcs, \
58	}	58	}
59		59
60	int mtk_paris_pinctrl_probe(struct platform_device *pdev,	60	int mtk_paris_pinctrl_probe(struct platform_device *pdev);
61	const struct mtk_pin_soc *soc);
62		61
63	ssize_t mtk_pctrl_show_one_pin(struct mtk_pinctrl *hw,	62	ssize_t mtk_pctrl_show_one_pin(struct mtk_pinctrl *hw,
64	unsigned int gpio, char *buf, unsigned int bufLen);	63	unsigned int gpio, char *buf, unsigned int bufLen);

drivers/pinctrl/meson/Kconfig+6−0

@@ -61,4 +61,10 @@ config PINCTRL_MESON_A1 · 60 unmodified lines
61	select PINCTRL_MESON_AXG_PMX	61	select PINCTRL_MESON_AXG_PMX
62	default y	62	default y
63		63
		64	config PINCTRL_MESON_S4
		65	tristate "Meson s4 Soc pinctrl driver"
		66	depends on ARM64
		67	select PINCTRL_MESON_AXG_PMX
		68	default y
		69
64	endif	70	endif

drivers/pinctrl/meson/Makefile+1−0

@@ -9,3 +9,4 @@ obj-$(CONFIG_PINCTRL_MESON_AXG_PMX) += pinctrl-meson-axg-pmx.o · 8 unmodified lines
9	obj-$(CONFIG_PINCTRL_MESON_AXG) += pinctrl-meson-axg.o	9	obj-$(CONFIG_PINCTRL_MESON_AXG) += pinctrl-meson-axg.o
10	obj-$(CONFIG_PINCTRL_MESON_G12A) += pinctrl-meson-g12a.o	10	obj-$(CONFIG_PINCTRL_MESON_G12A) += pinctrl-meson-g12a.o
11	obj-$(CONFIG_PINCTRL_MESON_A1) += pinctrl-meson-a1.o	11	obj-$(CONFIG_PINCTRL_MESON_A1) += pinctrl-meson-a1.o
		12	obj-$(CONFIG_PINCTRL_MESON_S4) += pinctrl-meson-s4.o

drivers/pinctrl/meson/pinctrl-meson-g12a.c+5−1

 static const unsigned int pwm_e_pins[]			= { GPIOX_16 };
 /* pwm_f */
+static const unsigned int pwm_f_z_pins[]		= { GPIOZ_12 };
+static const unsigned int pwm_f_a_pins[]		= { GPIOA_11 };
 static const unsigned int pwm_f_x_pins[]		= { GPIOX_7 };
 static const unsigned int pwm_f_h_pins[]		= { GPIOH_5 };
 	GROUP(tdm_c_dout2_z,		4),
 	GROUP(tdm_c_dout3_z,		4),
 	GROUP(mclk1_z,			4),
+	GROUP(pwm_f_z,			5),
 	/* bank GPIOX */
 	GROUP(sdio_d0,			1),
 	GROUP(tdm_c_dout3_a,		2),
 	GROUP(mclk0_a,			1),
 	GROUP(mclk1_a,			2),
+	GROUP(pwm_f_a,			3),
 };
 /* uart_ao_a */
 };
 static const char * const pwm_f_groups[] = {
-	"pwm_f_x", "pwm_f_h",
+	"pwm_f_z", "pwm_f_a", "pwm_f_x", "pwm_f_h",
 };
 static const char * const cec_ao_a_h_groups[] = {

drivers/pinctrl/meson/pinctrl-meson-s4.c+1232−0

@@ -0,0 +1,1232 @@
	1	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	2	/*
	3	* Pin controller and GPIO driver for Amlogic Meson S4 SoC.
	4	*
	5	* Copyright (c) 2021 Amlogic, Inc. All rights reserved.
	6	* Author: Qianggui Song <qianggui.song@amlogic.com>
	7	*/
	8
	9	#include <dt-bindings/gpio/meson-s4-gpio.h>
	10	#include "pinctrl-meson.h"
	11	#include "pinctrl-meson-axg-pmx.h"
	12
	13	static const struct pinctrl_pin_desc meson_s4_periphs_pins[] = {
	14	MESON_PIN(GPIOE_0),
	15	MESON_PIN(GPIOE_1),
	16
	17	MESON_PIN(GPIOB_0),
	18	MESON_PIN(GPIOB_1),
	19	MESON_PIN(GPIOB_2),
	20	MESON_PIN(GPIOB_3),
	21	MESON_PIN(GPIOB_4),
	22	MESON_PIN(GPIOB_5),
	23	MESON_PIN(GPIOB_6),
	24	MESON_PIN(GPIOB_7),
	25	MESON_PIN(GPIOB_8),
	26	MESON_PIN(GPIOB_9),
	27	MESON_PIN(GPIOB_10),
	28	MESON_PIN(GPIOB_11),
	29	MESON_PIN(GPIOB_12),
	30	MESON_PIN(GPIOB_13),
	31
	32	MESON_PIN(GPIOC_0),
	33	MESON_PIN(GPIOC_1),
	34	MESON_PIN(GPIOC_2),
	35	MESON_PIN(GPIOC_3),
	36	MESON_PIN(GPIOC_4),
	37	MESON_PIN(GPIOC_5),
	38	MESON_PIN(GPIOC_6),
	39	MESON_PIN(GPIOC_7),
	40
	41	MESON_PIN(GPIOD_0),
	42	MESON_PIN(GPIOD_1),
	43	MESON_PIN(GPIOD_2),
	44	MESON_PIN(GPIOD_3),
	45	MESON_PIN(GPIOD_4),
	46	MESON_PIN(GPIOD_5),
	47	MESON_PIN(GPIOD_6),
	48	MESON_PIN(GPIOD_7),
	49	MESON_PIN(GPIOD_8),
	50	MESON_PIN(GPIOD_9),
	51	MESON_PIN(GPIOD_10),
	52	MESON_PIN(GPIOD_11),
	53
	54	MESON_PIN(GPIOH_0),
	55	MESON_PIN(GPIOH_1),
	56	MESON_PIN(GPIOH_2),
	57	MESON_PIN(GPIOH_3),
	58	MESON_PIN(GPIOH_4),
	59	MESON_PIN(GPIOH_5),
	60	MESON_PIN(GPIOH_6),
	61	MESON_PIN(GPIOH_7),
	62	MESON_PIN(GPIOH_8),
	63	MESON_PIN(GPIOH_9),
	64	MESON_PIN(GPIOH_10),
	65	MESON_PIN(GPIOH_11),
	66
	67	MESON_PIN(GPIOX_0),
	68	MESON_PIN(GPIOX_1),
	69	MESON_PIN(GPIOX_2),
	70	MESON_PIN(GPIOX_3),
	71	MESON_PIN(GPIOX_4),
	72	MESON_PIN(GPIOX_5),
	73	MESON_PIN(GPIOX_6),
	74	MESON_PIN(GPIOX_7),
	75	MESON_PIN(GPIOX_8),
	76	MESON_PIN(GPIOX_9),
	77	MESON_PIN(GPIOX_10),
	78	MESON_PIN(GPIOX_11),
	79	MESON_PIN(GPIOX_12),
	80	MESON_PIN(GPIOX_13),
	81	MESON_PIN(GPIOX_14),
	82	MESON_PIN(GPIOX_15),
	83	MESON_PIN(GPIOX_16),
	84	MESON_PIN(GPIOX_17),
	85	MESON_PIN(GPIOX_18),
	86	MESON_PIN(GPIOX_19),
	87
	88	MESON_PIN(GPIOZ_0),
	89	MESON_PIN(GPIOZ_1),
	90	MESON_PIN(GPIOZ_2),
	91	MESON_PIN(GPIOZ_3),
	92	MESON_PIN(GPIOZ_4),
	93	MESON_PIN(GPIOZ_5),
	94	MESON_PIN(GPIOZ_6),
	95	MESON_PIN(GPIOZ_7),
	96	MESON_PIN(GPIOZ_8),
	97	MESON_PIN(GPIOZ_9),
	98	MESON_PIN(GPIOZ_10),
	99	MESON_PIN(GPIOZ_11),
	100	MESON_PIN(GPIOZ_12),
	101
	102	MESON_PIN(GPIO_TEST_N),
	103	};
	104
	105	/* BANK E func1 */
	106	static const unsigned int i2c0_sda_pins[] = { GPIOE_0 };
	107	static const unsigned int i2c0_scl_pins[] = { GPIOE_1 };
	108
	109	/* BANK E func2 */
	110	static const unsigned int uart_b_tx_e_pins[] = { GPIOE_0 };
	111	static const unsigned int uart_b_rx_e_pins[] = { GPIOE_1 };
	112
	113	/* BANK E func3 */
	114	static const unsigned int pwm_h_pins[] = { GPIOE_0 };
	115	static const unsigned int pwm_j_pins[] = { GPIOE_1 };
	116
	117	/* BANK B func1 */
	118	static const unsigned int emmc_nand_d0_pins[] = { GPIOB_0 };
	119	static const unsigned int emmc_nand_d1_pins[] = { GPIOB_1 };
	120	static const unsigned int emmc_nand_d2_pins[] = { GPIOB_2 };
	121	static const unsigned int emmc_nand_d3_pins[] = { GPIOB_3 };
	122	static const unsigned int emmc_nand_d4_pins[] = { GPIOB_4 };
	123	static const unsigned int emmc_nand_d5_pins[] = { GPIOB_5 };
	124	static const unsigned int emmc_nand_d6_pins[] = { GPIOB_6 };
	125	static const unsigned int emmc_nand_d7_pins[] = { GPIOB_7 };
	126	static const unsigned int emmc_clk_pins[] = { GPIOB_8 };
	127	static const unsigned int emmc_rst_pins[] = { GPIOB_9 };
	128	static const unsigned int emmc_cmd_pins[] = { GPIOB_10 };
	129	static const unsigned int emmc_nand_ds_pins[] = { GPIOB_11 };
	130
	131	/* Bank B func2 */
	132	static const unsigned int nand_wen_clk_pins[] = { GPIOB_8 };
	133	static const unsigned int nand_ale_pins[] = { GPIOB_9 };
	134	static const unsigned int nand_ren_wr_pins[] = { GPIOB_10 };
	135	static const unsigned int nand_cle_pins[] = { GPIOB_11 };
	136	static const unsigned int nand_ce0_pins[] = { GPIOB_12 };
	137
	138	/* Bank B func3 */
	139	static const unsigned int spif_hold_pins[] = { GPIOB_3 };
	140	static const unsigned int spif_mo_pins[] = { GPIOB_4 };
	141	static const unsigned int spif_mi_pins[] = { GPIOB_5 };
	142	static const unsigned int spif_clk_pins[] = { GPIOB_6 };
	143	static const unsigned int spif_wp_pins[] = { GPIOB_7 };
	144	static const unsigned int spif_cs_pins[] = { GPIOB_13 };
	145
	146	/* Bank C func1 */
	147	static const unsigned int sdcard_d0_c_pins[] = { GPIOC_0 };
	148	static const unsigned int sdcard_d1_c_pins[] = { GPIOC_1 };
	149	static const unsigned int sdcard_d2_c_pins[] = { GPIOC_2 };
	150	static const unsigned int sdcard_d3_c_pins[] = { GPIOC_3 };
	151	static const unsigned int sdcard_clk_c_pins[] = { GPIOC_4 };
	152	static const unsigned int sdcard_cmd_c_pins[] = { GPIOC_5 };
	153	static const unsigned int sdcard_cd_pins[] = { GPIOC_6 };
	154
	155	/* Bank C func2 */
	156	static const unsigned int jtag_2_tdo_pins[] = { GPIOC_0 };
	157	static const unsigned int jtag_2_tdi_pins[] = { GPIOC_1 };
	158	static const unsigned int uart_b_rx_c_pins[] = { GPIOC_2 };
	159	static const unsigned int uart_b_tx_c_pins[] = { GPIOC_3 };
	160	static const unsigned int jtag_2_clk_pins[] = { GPIOC_4 };
	161	static const unsigned int jtag_2_tms_pins[] = { GPIOC_5 };
	162	static const unsigned int i2c1_sda_c_pins[] = { GPIOC_6 };
	163	static const unsigned int i2c1_scl_c_pins[] = { GPIOC_7 };
	164
	165	/* Bank C func3 */
	166	static const unsigned int pdm_din1_c_pins[] = { GPIOC_0 };
	167	static const unsigned int pdm_din0_c_pins[] = { GPIOC_1 };
	168	static const unsigned int i2c4_sda_c_pins[] = { GPIOC_2 };
	169	static const unsigned int i2c4_scl_c_pins[] = { GPIOC_3 };
	170	static const unsigned int pdm_dclk_c_pins[] = { GPIOC_4 };
	171	static const unsigned int iso7816_clk_c_pins[] = { GPIOC_5 };
	172	static const unsigned int iso7816_data_c_pins[] = { GPIOC_6 };
	173
	174	/* Bank C func4 */
	175	static const unsigned int tdm_d2_c_pins[] = { GPIOC_0 };
	176	static const unsigned int tdm_d3_c_pins[] = { GPIOC_1 };
	177	static const unsigned int tdm_fs1_c_pins[] = { GPIOC_2 };
	178	static const unsigned int tdm_sclk1_c_pins[] = { GPIOC_3 };
	179	static const unsigned int mclk_1_c_pins[] = { GPIOC_4 };
	180	static const unsigned int tdm_d4_c_pins[] = { GPIOC_5 };
	181	static const unsigned int tdm_d5_c_pins[] = { GPIOC_6 };
	182
	183	/* Bank D func1 */
	184	static const unsigned int uart_b_tx_d_pins[] = { GPIOD_0 };
	185	static const unsigned int uart_b_rx_d_pins[] = { GPIOD_1 };
	186	static const unsigned int uart_b_cts_d_pins[] = { GPIOD_2 };
	187	static const unsigned int uart_b_rts_d_pins[] = { GPIOD_3 };
	188	static const unsigned int remote_out_pins[] = { GPIOD_4 };
	189	static const unsigned int remote_in_pins[] = { GPIOD_5 };
	190	static const unsigned int jtag_1_clk_pins[] = { GPIOD_6 };
	191	static const unsigned int jtag_1_tms_pins[] = { GPIOD_7 };
	192	static const unsigned int jtag_1_tdi_pins[] = { GPIOD_8 };
	193	static const unsigned int jtag_1_tdo_pins[] = { GPIOD_9 };
	194	static const unsigned int clk12_24_pins[] = { GPIOD_10 };
	195	static const unsigned int pwm_g_hiz_pins[] = { GPIOD_11 };
	196
	197	/* Bank D func2 */
	198	static const unsigned int i2c4_sda_d_pins[] = { GPIOD_2 };
	199	static const unsigned int i2c4_scl_d_pins[] = { GPIOD_3 };
	200	static const unsigned int mclk_1_d_pins[] = { GPIOD_4 };
	201	static const unsigned int tdm_sclk1_d_pins[] = { GPIOD_6 };
	202	static const unsigned int tdm_fs1_d_pins[] = { GPIOD_7 };
	203	static const unsigned int tdm_d4_d_pins[] = { GPIOD_8 };
	204	static const unsigned int tdm_d3_d_pins[] = { GPIOD_9 };
	205	static const unsigned int tdm_d2_d_pins[] = { GPIOD_10 };
	206	static const unsigned int pwm_g_d_pins[] = { GPIOD_11 };
	207
	208	/* Bank D func3 */
	209	static const unsigned int uart_c_tx_pins[] = { GPIOD_2 };
	210	static const unsigned int uart_c_rx_pins[] = { GPIOD_3 };
	211	static const unsigned int pwm_b_d_pins[] = { GPIOD_4 };
	212	static const unsigned int pwm_a_d_pins[] = { GPIOD_6 };
	213	static const unsigned int pwm_c_d_pins[] = { GPIOD_7 };
	214	static const unsigned int pwm_d_d_pins[] = { GPIOD_8 };
	215	static const unsigned int pwm_i_d_pins[] = { GPIOD_9 };
	216
	217	/* Bank D func4 */
	218	static const unsigned int clk_32k_in_pins[] = { GPIOD_2 };
	219	static const unsigned int pwm_b_hiz_pins[] = { GPIOD_4 };
	220	static const unsigned int pwm_a_hiz_pins[] = { GPIOD_6 };
	221	static const unsigned int pwm_c_hiz_pins[] = { GPIOD_7 };
	222	static const unsigned int pdm_dclk_d_pins[] = { GPIOD_8 };
	223	static const unsigned int pdm_din0_d_pins[] = { GPIOD_9 };
	224	static const unsigned int pdm_din1_d_pins[] = { GPIOD_10 };
	225
	226	/* Bank D func5 */
	227	static const unsigned int mic_mute_en_pins[] = { GPIOD_2 };
	228	static const unsigned int mic_mute_key_pins[] = { GPIOD_3 };
	229	static const unsigned int i2c1_sda_d_pins[] = { GPIOD_6 };
	230	static const unsigned int i2c1_scl_d_pins[] = { GPIOD_7 };
	231	static const unsigned int i2c2_sda_d_pins[] = { GPIOD_10 };
	232	static const unsigned int i2c2_scl_d_pins[] = { GPIOD_11 };
	233
	234	/* Bank D func6 */
	235	static const unsigned int gen_clk_d_pins[] = { GPIOD_10 };
	236	static const unsigned int tsin_b_clk_c_pins[] = { GPIOD_6 };
	237	static const unsigned int tsin_b_sop_c_pins[] = { GPIOD_7 };
	238	static const unsigned int tsin_b_valid_c_pins[] = { GPIOD_8 };
	239	static const unsigned int tsin_b_d0_c_pins[] = { GPIOD_9 };
	240
	241	/* Bank H func1 */
	242	static const unsigned int hdmitx_sda_pins[] = { GPIOH_0 };
	243	static const unsigned int hdmitx_sck_pins[] = { GPIOH_1 };
	244	static const unsigned int hdmitx_hpd_in_pins[] = { GPIOH_2 };
	245	static const unsigned int ao_cec_a_pins[] = { GPIOH_3 };
	246	static const unsigned int spdif_out_h_pins[] = { GPIOH_4 };
	247	static const unsigned int spdif_in_pins[] = { GPIOH_5 };
	248	static const unsigned int i2c1_sda_h_pins[] = { GPIOH_6 };
	249	static const unsigned int i2c1_scl_h_pins[] = { GPIOH_7 };
	250	static const unsigned int i2c2_sda_h8_pins[] = { GPIOH_8 };
	251	static const unsigned int i2c2_scl_h9_pins[] = { GPIOH_9 };
	252	static const unsigned int eth_link_led_pins[] = { GPIOH_10 };
	253	static const unsigned int eth_act_led_pins[] = { GPIOH_11 };
	254
	255	/* Bank H func2 */
	256	static const unsigned int i2c2_sda_h0_pins[] = { GPIOH_0 };
	257	static const unsigned int i2c2_scl_h1_pins[] = { GPIOH_1 };
	258	static const unsigned int ao_cec_b_pins[] = { GPIOH_3 };
	259	static const unsigned int uart_d_tx_h_pins[] = { GPIOH_4 };
	260	static const unsigned int uart_d_rx_h_pins[] = { GPIOH_5 };
	261	static const unsigned int uart_d_cts_h_pins[] = { GPIOH_6 };
	262	static const unsigned int uart_d_rts_h_pins[] = { GPIOH_7 };
	263	static const unsigned int iso7816_clk_h_pins[] = { GPIOH_8 };
	264	static const unsigned int iso7816_data_h_pins[] = { GPIOH_9 };
	265	static const unsigned int uart_e_tx_h_pins[] = { GPIOH_10 };
	266	static const unsigned int uart_e_rx_h_pins[] = { GPIOH_11 };
	267
	268	/* Bank H func3 */
	269	static const unsigned int pwm_d_h_pins[] = { GPIOH_6 };
	270	static const unsigned int pwm_i_h_pins[] = { GPIOH_7 };
	271	static const unsigned int pdm_dclk_h_pins[] = { GPIOH_8 };
	272	static const unsigned int pdm_din0_h_pins[] = { GPIOH_9 };
	273	static const unsigned int pdm_din1_h_pins[] = { GPIOH_10 };
	274
	275	/* Bank H func4 */
	276	static const unsigned int mclk_1_h_pins[] = { GPIOH_4 };
	277	static const unsigned int tdm_sclk1_h_pins[] = { GPIOH_5 };
	278	static const unsigned int tdm_fs1_h_pins[] = { GPIOH_6 };
	279	static const unsigned int tdm_d2_h_pins[] = { GPIOH_7 };
	280	static const unsigned int tdm_d3_h_pins[] = { GPIOH_8 };
	281	static const unsigned int tdm_d4_h_pins[] = { GPIOH_9 };
	282
	283	/* Bank H func5 */
	284	static const unsigned int spi_a_miso_h_pins[] = { GPIOH_4 };
	285	static const unsigned int spi_a_mosi_h_pins[] = { GPIOH_5 };
	286	static const unsigned int spi_a_clk_h_pins[] = { GPIOH_6 };
	287	static const unsigned int spi_a_ss0_h_pins[] = { GPIOH_7 };
	288
	289	/* Bank H func6 */
	290	static const unsigned int gen_clk_h_pins[] = { GPIOH_11 };
	291	static const unsigned int tsin_b1_clk_pins[] = { GPIOH_4 };
	292	static const unsigned int tsin_b1_sop_pins[] = { GPIOH_5 };
	293	static const unsigned int tsin_b1_valid_pins[] = { GPIOH_6 };
	294	static const unsigned int tsin_b1_d0_pins[] = { GPIOH_7 };
	295
	296	/* Bank X func1 */
	297	static const unsigned int sdio_d0_pins[] = { GPIOX_0 };
	298	static const unsigned int sdio_d1_pins[] = { GPIOX_1 };
	299	static const unsigned int sdio_d2_pins[] = { GPIOX_2 };
	300	static const unsigned int sdio_d3_pins[] = { GPIOX_3 };
	301	static const unsigned int sdio_clk_pins[] = { GPIOX_4 };
	302	static const unsigned int sdio_cmd_pins[] = { GPIOX_5 };
	303	static const unsigned int pwm_a_x_pins[] = { GPIOX_6 };
	304	static const unsigned int pwm_f_x_pins[] = { GPIOX_7 };
	305	static const unsigned int tdm_d1_pins[] = { GPIOX_8 };
	306	static const unsigned int tdm_d0_pins[] = { GPIOX_9 };
	307	static const unsigned int tdm_fs0_pins[] = { GPIOX_10 };
	308	static const unsigned int tdm_sclk0_pins[] = { GPIOX_11 };
	309	static const unsigned int uart_a_tx_pins[] = { GPIOX_12 };
	310	static const unsigned int uart_a_rx_pins[] = { GPIOX_13 };
	311	static const unsigned int uart_a_cts_pins[] = { GPIOX_14 };
	312	static const unsigned int uart_a_rts_pins[] = { GPIOX_15 };
	313	static const unsigned int pwm_e_x_pins[] = { GPIOX_16 };
	314	static const unsigned int i2c1_sda_x_pins[] = { GPIOX_17 };
	315	static const unsigned int i2c1_scl_x_pins[] = { GPIOX_18 };
	316	static const unsigned int pwm_b_x_pins[] = { GPIOX_19 };
	317
	318	/* Bank X func2 */
	319	static const unsigned int pdm_din0_x_pins[] = { GPIOX_8 };
	320	static const unsigned int pdm_din1_x_pins[] = { GPIOX_9 };
	321	static const unsigned int pdm_dclk_x_pins[] = { GPIOX_11 };
	322
	323	/* Bank X func3 */
	324	static const unsigned int spi_a_mosi_x_pins[] = { GPIOX_8 };
	325	static const unsigned int spi_a_miso_x_pins[] = { GPIOX_9 };
	326	static const unsigned int spi_a_ss0_x_pins[] = { GPIOX_10 };
	327	static const unsigned int spi_a_clk_x_pins[] = { GPIOX_11 };
	328
	329	/* Bank X func4 */
	330	static const unsigned int pwm_c_x_pins[] = { GPIOX_8 };
	331	static const unsigned int i2c_slave_scl_pins[] = { GPIOX_10 };
	332	static const unsigned int i2c_slave_sda_pins[] = { GPIOX_11 };
	333
	334	/* Bank X func5 */
	335	static const unsigned int i2c3_sda_x_pins[] = { GPIOX_10 };
	336	static const unsigned int i2c3_scl_x_pins[] = { GPIOX_11 };
	337
	338	/* Bank Z func1 */
	339	static const unsigned int tdm_fs2_pins[] = { GPIOZ_0 };
	340	static const unsigned int tdm_sclk2_pins[] = { GPIOZ_1 };
	341	static const unsigned int tdm_d4_z_pins[] = { GPIOZ_2 };
	342	static const unsigned int tdm_d5_z_pins[] = { GPIOZ_3 };
	343	static const unsigned int tdm_d6_pins[] = { GPIOZ_4 };
	344	static const unsigned int tdm_d7_pins[] = { GPIOZ_5 };
	345	static const unsigned int mclk_2_pins[] = { GPIOZ_6 };
	346	static const unsigned int spdif_out_z_pins[] = { GPIOZ_9 };
	347	static const unsigned int dtv_a_if_agc_z10_pins[] = { GPIOZ_10 };
	348	static const unsigned int uart_e_tx_z11_pins[] = { GPIOZ_11 };
	349	static const unsigned int uart_e_rx_z12_pins[] = { GPIOZ_12 };
	350
	351	/* Bank Z func2 */
	352	static const unsigned int tsin_a_clk_pins[] = { GPIOZ_0 };
	353	static const unsigned int tsin_a_sop_pins[] = { GPIOZ_1 };
	354	static const unsigned int tsin_a_valid_pins[] = { GPIOZ_2 };
	355	static const unsigned int tsin_a_din0_pins[] = { GPIOZ_3 };
	356	static const unsigned int dtv_a_if_agc_z6_pins[] = { GPIOZ_6 };
	357	static const unsigned int dtv_b_if_agc_pins[] = { GPIOZ_7 };
	358	static const unsigned int i2c3_sda_z_pins[] = { GPIOZ_8 };
	359	static const unsigned int i2c3_scl_z_pins[] = { GPIOZ_9 };
	360	static const unsigned int dtv_a_rf_agc_pins[] = { GPIOZ_10 };
	361	static const unsigned int dtv_b_rf_agc_pins[] = { GPIOZ_11 };
	362
	363	/* Bank Z func3 */
	364	static const unsigned int sdcard_d0_z_pins[] = { GPIOZ_0 };
	365	static const unsigned int sdcard_d1_z_pins[] = { GPIOZ_1 };
	366	static const unsigned int sdcard_d2_z_pins[] = { GPIOZ_2 };
	367	static const unsigned int sdcard_d3_z_pins[] = { GPIOZ_3 };
	368	static const unsigned int sdcard_clk_z_pins[] = { GPIOZ_4 };
	369	static const unsigned int sdcard_cmd_z_pins[] = { GPIOZ_5 };
	370	static const unsigned int uart_e_tx_z8_pins[] = { GPIOZ_8 };
	371	static const unsigned int uart_e_rx_z9_pins[] = { GPIOZ_9 };
	372	static const unsigned int pdm_din1_z_pins[] = { GPIOZ_10 };
	373	static const unsigned int pdm_din0_z_pins[] = { GPIOZ_11 };
	374	static const unsigned int pdm_dclk_z_pins[] = { GPIOZ_12 };
	375
	376	/* Bank Z func4 */
	377	static const unsigned int spi_a_miso_z_pins[] = { GPIOZ_0 };
	378	static const unsigned int spi_a_mosi_z_pins[] = { GPIOZ_1 };
	379	static const unsigned int spi_a_clk_z_pins[] = { GPIOZ_2 };
	380	static const unsigned int spi_a_ss0_z_pins[] = { GPIOZ_3 };
	381	static const unsigned int spi_a_ss1_z_pins[] = { GPIOZ_4 };
	382	static const unsigned int spi_a_ss2_z_pins[] = { GPIOZ_5 };
	383	static const unsigned int i2c4_scl_z_pins[] = { GPIOZ_11 };
	384	static const unsigned int i2c4_sda_z_pins[] = { GPIOZ_12 };
	385
	386	/* Bank Z func5 */
	387	static const unsigned int uart_d_tx_z_pins[] = { GPIOZ_0 };
	388	static const unsigned int uart_d_rx_z_pins[] = { GPIOZ_1 };
	389	static const unsigned int uart_d_cts_z_pins[] = { GPIOZ_2 };
	390	static const unsigned int uart_d_rts_z_pins[] = { GPIOZ_3 };
	391	static const unsigned int pwm_g_z_pins[] = { GPIOZ_4 };
	392	static const unsigned int pwm_f_z_pins[] = { GPIOZ_5 };
	393	static const unsigned int pwm_e_z_pins[] = { GPIOZ_6 };
	394	static const unsigned int tsin_b_clk_z_pins[] = { GPIOZ_7 };
	395	static const unsigned int tsin_b_sop_z_pins[] = { GPIOZ_10 };
	396	static const unsigned int tsin_b_valid_z_pins[] = { GPIOZ_11 };
	397	static const unsigned int tsin_b_d0_z_pins[] = { GPIOZ_12 };
	398
	399	/* Bank Z func6 */
	400	static const unsigned int s2_demod_gpio7_pins[] = { GPIOZ_0 };
	401	static const unsigned int s2_demod_gpio6_pins[] = { GPIOZ_1 };
	402	static const unsigned int s2_demod_gpio5_pins[] = { GPIOZ_2 };
	403	static const unsigned int s2_demod_gpio4_pins[] = { GPIOZ_3 };
	404	static const unsigned int s2_demod_gpio3_pins[] = { GPIOZ_4 };
	405	static const unsigned int s2_demod_gpio2_pins[] = { GPIOZ_5 };
	406	static const unsigned int diseqc_out_pins[] = { GPIOZ_7 };
	407	static const unsigned int s2_demod_gpio1_pins[] = { GPIOZ_8 };
	408	static const unsigned int s2_demod_gpio0_pins[] = { GPIOZ_12 };
	409
	410	/* Bank Z func7 */
	411	static const unsigned int gen_clk_z9_pins[] = { GPIOZ_9 };
	412	static const unsigned int gen_clk_z12_pins[] = { GPIOZ_12 };
	413
	414	static struct meson_pmx_group meson_s4_periphs_groups[] = {
	415	GPIO_GROUP(GPIOE_0),
	416	GPIO_GROUP(GPIOE_1),
	417
	418	GPIO_GROUP(GPIOB_0),
	419	GPIO_GROUP(GPIOB_1),
	420	GPIO_GROUP(GPIOB_2),
	421	GPIO_GROUP(GPIOB_3),
	422	GPIO_GROUP(GPIOB_4),
	423	GPIO_GROUP(GPIOB_5),
	424	GPIO_GROUP(GPIOB_6),
	425	GPIO_GROUP(GPIOB_7),
	426	GPIO_GROUP(GPIOB_8),
	427	GPIO_GROUP(GPIOB_9),
	428	GPIO_GROUP(GPIOB_10),
	429	GPIO_GROUP(GPIOB_11),
	430	GPIO_GROUP(GPIOB_12),
	431	GPIO_GROUP(GPIOB_13),
	432
	433	GPIO_GROUP(GPIOC_0),
	434	GPIO_GROUP(GPIOC_1),
	435	GPIO_GROUP(GPIOC_2),
	436	GPIO_GROUP(GPIOC_3),
	437	GPIO_GROUP(GPIOC_4),
	438	GPIO_GROUP(GPIOC_5),
	439	GPIO_GROUP(GPIOC_6),
	440	GPIO_GROUP(GPIOC_7),
	441
	442	GPIO_GROUP(GPIOD_0),
	443	GPIO_GROUP(GPIOD_1),
	444	GPIO_GROUP(GPIOD_2),
	445	GPIO_GROUP(GPIOD_3),
	446	GPIO_GROUP(GPIOD_4),
	447	GPIO_GROUP(GPIOD_5),
	448	GPIO_GROUP(GPIOD_6),
	449	GPIO_GROUP(GPIOD_7),
	450	GPIO_GROUP(GPIOD_8),
	451	GPIO_GROUP(GPIOD_9),
	452	GPIO_GROUP(GPIOD_10),
	453	GPIO_GROUP(GPIOD_11),
	454
	455	GPIO_GROUP(GPIOH_0),
	456	GPIO_GROUP(GPIOH_1),
	457	GPIO_GROUP(GPIOH_2),
	458	GPIO_GROUP(GPIOH_3),
	459	GPIO_GROUP(GPIOH_4),
	460	GPIO_GROUP(GPIOH_5),
	461	GPIO_GROUP(GPIOH_6),
	462	GPIO_GROUP(GPIOH_7),
	463	GPIO_GROUP(GPIOH_8),
	464	GPIO_GROUP(GPIOH_9),
	465	GPIO_GROUP(GPIOH_10),
	466	GPIO_GROUP(GPIOH_11),
	467
	468	GPIO_GROUP(GPIOX_0),
	469	GPIO_GROUP(GPIOX_1),
	470	GPIO_GROUP(GPIOX_2),
	471	GPIO_GROUP(GPIOX_3),
	472	GPIO_GROUP(GPIOX_4),
	473	GPIO_GROUP(GPIOX_5),
	474	GPIO_GROUP(GPIOX_6),
	475	GPIO_GROUP(GPIOX_7),
	476	GPIO_GROUP(GPIOX_8),
	477	GPIO_GROUP(GPIOX_9),
	478	GPIO_GROUP(GPIOX_10),
	479	GPIO_GROUP(GPIOX_11),
	480	GPIO_GROUP(GPIOX_12),
	481	GPIO_GROUP(GPIOX_13),
	482	GPIO_GROUP(GPIOX_14),
	483	GPIO_GROUP(GPIOX_15),
	484	GPIO_GROUP(GPIOX_16),
	485	GPIO_GROUP(GPIOX_17),
	486	GPIO_GROUP(GPIOX_18),
	487	GPIO_GROUP(GPIOX_19),
	488
	489	GPIO_GROUP(GPIOZ_0),
	490	GPIO_GROUP(GPIOZ_1),
	491	GPIO_GROUP(GPIOZ_2),
	492	GPIO_GROUP(GPIOZ_3),
	493	GPIO_GROUP(GPIOZ_4),
	494	GPIO_GROUP(GPIOZ_5),
	495	GPIO_GROUP(GPIOZ_6),
	496	GPIO_GROUP(GPIOZ_7),
	497	GPIO_GROUP(GPIOZ_8),
	498	GPIO_GROUP(GPIOZ_9),
	499	GPIO_GROUP(GPIOZ_10),
	500	GPIO_GROUP(GPIOZ_11),
	501	GPIO_GROUP(GPIOZ_12),
	502
	503	GPIO_GROUP(GPIO_TEST_N),
	504
	505	/* BANK E func1 */
	506	GROUP(i2c0_sda, 1),
	507	GROUP(i2c0_scl, 1),
	508
	509	/* BANK E func2 */
	510	GROUP(uart_b_tx_e, 2),
	511	GROUP(uart_b_rx_e, 2),
	512
	513	/* BANK E func3 */
	514	GROUP(pwm_h, 3),
	515	GROUP(pwm_j, 3),
	516
	517	/* BANK B func1 */
	518	GROUP(emmc_nand_d0, 1),
	519	GROUP(emmc_nand_d1, 1),
	520	GROUP(emmc_nand_d2, 1),
	521	GROUP(emmc_nand_d3, 1),
	522	GROUP(emmc_nand_d4, 1),
	523	GROUP(emmc_nand_d5, 1),
	524	GROUP(emmc_nand_d6, 1),
	525	GROUP(emmc_nand_d7, 1),
	526	GROUP(emmc_clk, 1),
	527	GROUP(emmc_rst, 1),
	528	GROUP(emmc_cmd, 1),
	529	GROUP(emmc_nand_ds, 1),
	530
	531	/* Bank B func2 */
	532	GROUP(nand_wen_clk, 2),
	533	GROUP(nand_ale, 2),
	534	GROUP(nand_ren_wr, 2),
	535	GROUP(nand_cle, 2),
	536	GROUP(nand_ce0, 2),
	537
	538	/* Bank B func3 */
	539	GROUP(spif_hold, 3),
	540	GROUP(spif_mo, 3),
	541	GROUP(spif_mi, 3),
	542	GROUP(spif_clk, 3),
	543	GROUP(spif_wp, 3),
	544	GROUP(spif_cs, 3),
	545
	546	/* Bank C func1 */
	547	GROUP(sdcard_d0_c, 1),
	548	GROUP(sdcard_d1_c, 1),
	549	GROUP(sdcard_d2_c, 1),
	550	GROUP(sdcard_d3_c, 1),
	551	GROUP(sdcard_clk_c, 1),
	552	GROUP(sdcard_cmd_c, 1),
	553	GROUP(sdcard_cd, 1),
	554
	555	/* Bank C func2 */
	556	GROUP(jtag_2_tdo, 2),
	557	GROUP(jtag_2_tdi, 2),
	558	GROUP(uart_b_rx_c, 2),
	559	GROUP(uart_b_tx_c, 2),
	560	GROUP(jtag_2_clk, 2),
	561	GROUP(jtag_2_tms, 2),
	562	GROUP(i2c1_sda_c, 2),
	563	GROUP(i2c1_scl_c, 2),
	564
	565	/* Bank C func3 */
	566	GROUP(pdm_din1_c, 3),
	567	GROUP(pdm_din0_c, 3),
	568	GROUP(i2c4_sda_c, 3),
	569	GROUP(i2c4_scl_c, 3),
	570	GROUP(pdm_dclk_c, 3),
	571	GROUP(iso7816_clk_c, 3),
	572	GROUP(iso7816_data_c, 3),
	573
	574	/* Bank C func4 */
	575	GROUP(tdm_d2_c, 4),
	576	GROUP(tdm_d3_c, 4),
	577	GROUP(tdm_fs1_c, 4),
	578	GROUP(mclk_1_c, 4),
	579	GROUP(tdm_d4_c, 4),
	580	GROUP(tdm_d5_c, 4),
	581
	582	/* Bank D func1 */
	583	GROUP(uart_b_tx_d, 1),
	584	GROUP(uart_b_rx_d, 1),
	585	GROUP(uart_b_cts_d, 1),
	586	GROUP(uart_b_rts_d, 1),
	587	GROUP(remote_out, 1),
	588	GROUP(remote_in, 1),
	589	GROUP(jtag_1_clk, 1),
	590	GROUP(jtag_1_tms, 1),
	591	GROUP(jtag_1_tdi, 1),
	592	GROUP(jtag_1_tdo, 1),
	593	GROUP(clk12_24, 1),
	594	GROUP(pwm_g_hiz, 1),
	595
	596	/* Bank D func2 */
	597	GROUP(i2c4_sda_d, 2),
	598	GROUP(i2c4_scl_d, 2),
	599	GROUP(mclk_1_d, 2),
	600	GROUP(tdm_sclk1_d, 2),
	601	GROUP(tdm_fs1_d, 2),
	602	GROUP(tdm_d4_d, 2),
	603	GROUP(tdm_d3_d, 2),
	604	GROUP(tdm_d2_d, 2),
	605	GROUP(pwm_g_d, 2),
	606
	607	/* Bank D func3 */
	608	GROUP(uart_c_tx, 3),
	609	GROUP(uart_c_rx, 3),
	610	GROUP(pwm_b_d, 3),
	611	GROUP(pwm_a_d, 3),
	612	GROUP(pwm_c_d, 3),
	613	GROUP(pwm_d_d, 3),
	614	GROUP(pwm_i_d, 3),
	615
	616	/* Bank D func4 */
	617	GROUP(clk_32k_in, 4),
	618	GROUP(pwm_b_hiz, 4),
	619	GROUP(pwm_a_hiz, 4),
	620	GROUP(pwm_c_hiz, 4),
	621	GROUP(pdm_dclk_d, 4),
	622	GROUP(pdm_din0_d, 4),
	623	GROUP(pdm_din1_d, 4),
	624
	625	/* Bank D func5 */
	626	GROUP(mic_mute_en, 5),
	627	GROUP(mic_mute_key, 5),
	628	GROUP(i2c1_sda_d, 5),
	629	GROUP(i2c1_scl_d, 5),
	630	GROUP(i2c2_sda_d, 5),
	631	GROUP(i2c2_scl_d, 5),
	632
	633	/* Bank D func6 */
	634	GROUP(gen_clk_d, 6),
	635	GROUP(tsin_b_clk_c, 6),
	636	GROUP(tsin_b_sop_c, 6),
	637	GROUP(tsin_b_valid_c, 6),
	638	GROUP(tsin_b_d0_c, 6),
	639
	640	/* Bank H func1 */
	641	GROUP(hdmitx_sda, 1),
	642	GROUP(hdmitx_sck, 1),
	643	GROUP(hdmitx_hpd_in, 1),
	644	GROUP(ao_cec_a, 1),
	645	GROUP(spdif_out_h, 1),
	646	GROUP(spdif_in, 1),
	647	GROUP(i2c1_sda_h, 1),
	648	GROUP(i2c1_scl_h, 1),
	649	GROUP(i2c2_sda_h8, 1),
	650	GROUP(i2c2_scl_h9, 1),
	651	GROUP(eth_link_led, 1),
	652	GROUP(eth_act_led, 1),
	653
	654	/* Bank H func2 */
	655	GROUP(i2c2_sda_h0, 2),
	656	GROUP(i2c2_scl_h1, 2),
	657	GROUP(ao_cec_b, 2),
	658	GROUP(uart_d_tx_h, 2),
	659	GROUP(uart_d_rx_h, 2),
	660	GROUP(uart_d_cts_h, 2),
	661	GROUP(uart_d_rts_h, 2),
	662	GROUP(iso7816_clk_h, 2),
	663	GROUP(iso7816_data_h, 2),
	664	GROUP(uart_e_tx_h, 2),
	665	GROUP(uart_e_rx_h, 2),
	666
	667	/* Bank H func3 */
	668	GROUP(pwm_d_h, 3),
	669	GROUP(pwm_i_h, 3),
	670	GROUP(pdm_dclk_h, 3),
	671	GROUP(pdm_din0_h, 3),
	672	GROUP(pdm_din1_h, 3),
	673
	674	/* Bank H func4 */
	675	GROUP(mclk_1_h, 4),
	676	GROUP(tdm_sclk1_h, 4),
	677	GROUP(tdm_fs1_h, 4),
	678	GROUP(tdm_d2_h, 4),
	679	GROUP(tdm_d3_h, 4),
	680	GROUP(tdm_d4_h, 4),
	681
	682	/* Bank H func5 */
	683	GROUP(spi_a_miso_h, 5),
	684	GROUP(spi_a_mosi_h, 5),
	685	GROUP(spi_a_clk_h, 5),
	686	GROUP(spi_a_ss0_h, 5),
	687
	688	/* Bank H func6 */
	689	GROUP(gen_clk_h, 6),
	690	GROUP(tsin_b1_clk, 6),
	691	GROUP(tsin_b1_sop, 6),
	692	GROUP(tsin_b1_valid, 6),
	693	GROUP(tsin_b1_d0, 6),
	694
	695	/* Bank X func1 */
	696	GROUP(sdio_d0, 1),
	697	GROUP(sdio_d1, 1),
	698	GROUP(sdio_d2, 1),
	699	GROUP(sdio_d3, 1),
	700	GROUP(sdio_clk, 1),
	701	GROUP(sdio_cmd, 1),
	702	GROUP(pwm_a_x, 1),
	703	GROUP(pwm_f_x, 1),
	704	GROUP(tdm_d1, 1),
	705	GROUP(tdm_d0, 1),
	706	GROUP(tdm_fs0, 1),
	707	GROUP(tdm_sclk0, 1),
	708	GROUP(uart_a_tx, 1),
	709	GROUP(uart_a_rx, 1),
	710	GROUP(uart_a_cts, 1),
	711	GROUP(uart_a_rts, 1),
	712	GROUP(pwm_e_x, 1),
	713	GROUP(i2c1_sda_x, 1),
	714	GROUP(i2c1_scl_x, 1),
	715	GROUP(pwm_b_x, 1),
	716
	717	/* Bank X func2 */
	718	GROUP(pdm_din0_x, 2),
	719	GROUP(pdm_din1_x, 2),
	720	GROUP(pdm_dclk_x, 2),
	721
	722	/* Bank X func3 */
	723	GROUP(spi_a_mosi_x, 3),
	724	GROUP(spi_a_miso_x, 3),
	725	GROUP(spi_a_ss0_x, 3),
	726	GROUP(spi_a_clk_x, 3),
	727
	728	/* Bank X func4 */
	729	GROUP(pwm_c_x, 4),
	730	GROUP(i2c_slave_scl, 4),
	731	GROUP(i2c_slave_sda, 4),
	732
	733	/* Bank X func5 */
	734	GROUP(i2c3_sda_x, 5),
	735	GROUP(i2c3_scl_x, 5),
	736
	737	/* Bank Z func1 */
	738	GROUP(tdm_fs2, 1),
	739	GROUP(tdm_sclk2, 1),
	740	GROUP(tdm_d4_z, 1),
	741	GROUP(tdm_d5_z, 1),
	742	GROUP(tdm_d6, 1),
	743	GROUP(tdm_d7, 1),
	744	GROUP(mclk_2, 1),
	745	GROUP(spdif_out_z, 1),
	746	GROUP(dtv_a_if_agc_z10, 1),
	747	GROUP(uart_e_tx_z11, 1),
	748	GROUP(uart_e_rx_z12, 1),
	749
	750	/* Bank Z func2 */
	751	GROUP(tsin_a_clk, 2),
	752	GROUP(tsin_a_sop, 2),
	753	GROUP(tsin_a_valid, 2),
	754	GROUP(tsin_a_din0, 2),
	755	GROUP(dtv_a_if_agc_z6, 2),
	756	GROUP(dtv_b_if_agc, 2),
	757	GROUP(i2c3_sda_z, 2),
	758	GROUP(i2c3_scl_z, 2),
	759	GROUP(dtv_a_rf_agc, 2),
	760	GROUP(dtv_b_rf_agc, 2),
	761
	762	/* Bank Z func3 */
	763	GROUP(sdcard_d0_z, 3),
	764	GROUP(sdcard_d1_z, 3),
	765	GROUP(sdcard_d2_z, 3),
	766	GROUP(sdcard_d3_z, 3),
	767	GROUP(sdcard_clk_z, 3),
	768	GROUP(sdcard_cmd_z, 3),
	769	GROUP(uart_e_tx_z8, 3),
	770	GROUP(uart_e_rx_z9, 3),
	771	GROUP(pdm_din1_z, 3),
	772	GROUP(pdm_din0_z, 3),
	773	GROUP(pdm_dclk_z, 3),
	774
	775	/* Bank Z func4 */
	776	GROUP(spi_a_miso_z, 4),
	777	GROUP(spi_a_mosi_z, 4),
	778	GROUP(spi_a_clk_z, 4),
	779	GROUP(spi_a_ss0_z, 4),
	780	GROUP(spi_a_ss1_z, 4),
	781	GROUP(spi_a_ss2_z, 4),
	782	GROUP(i2c4_scl_z, 4),
	783	GROUP(i2c4_sda_z, 4),
	784
	785	/* Bank Z func5 */
	786	GROUP(uart_d_tx_z, 5),
	787	GROUP(uart_d_rx_z, 5),
	788	GROUP(uart_d_cts_z, 5),
	789	GROUP(uart_d_rts_z, 5),
	790	GROUP(pwm_g_z, 5),
	791	GROUP(pwm_f_z, 5),
	792	GROUP(pwm_e_z, 5),
	793	GROUP(tsin_b_clk_z, 5),
	794	GROUP(tsin_b_sop_z, 5),
	795	GROUP(tsin_b_valid_z, 5),
	796	GROUP(tsin_b_d0_z, 5),
	797
	798	/* Bank Z func6 */
	799	GROUP(s2_demod_gpio7, 6),
	800	GROUP(s2_demod_gpio6, 6),
	801	GROUP(s2_demod_gpio5, 6),
	802	GROUP(s2_demod_gpio4, 6),
	803	GROUP(s2_demod_gpio3, 6),
	804	GROUP(s2_demod_gpio2, 6),
	805	GROUP(diseqc_out, 6),
	806	GROUP(s2_demod_gpio1, 6),
	807	GROUP(s2_demod_gpio0, 6),
	808
	809	/* Bank Z func7 */
	810	GROUP(gen_clk_z9, 7),
	811	GROUP(gen_clk_z12, 7),
	812	};
	813
	814	static const char * const gpio_periphs_groups[] = {
	815	"GPIOE_0", "GPIOE_1",
	816
	817	"GPIOB_0", "GPIOB_1", "GPIOB_2", "GPIOB_3", "GPIOB_4", "GPIOB_5",
	818	"GPIOB_6", "GPIOB_7", "GPIOB_8", "GPIOB_9", "GPIOB_10", "GPIOB_11",
	819	"GPIOB_12", "GPIOB_13",
	820
	821	"GPIOC_0", "GPIOC_1", "GPIOC_2", "GPIOC_3", "GPIOC_4", "GPIOC_5",
	822	"GPIOC_6", "GPIOC_7",
	823
	824	"GPIOD_0", "GPIOD_1", "GPIOD_2", "GPIOD_3", "GPIOD_4", "GPIOD_5",
	825	"GPIOD_6", "GPIOD_7", "GPIOD_8", "GPIOD_9", "GPIOD_10", "GPIOD_11",
	826
	827	"GPIOH_0", "GPIOH_1", "GPIOH_2", "GPIOH_3", "GPIOH_4", "GPIOH_5",
	828	"GPIOH_6", "GPIOH_7", "GPIOH_8", "GPIOH_9", "GPIOH_10", "GPIOH_11",
	829
	830	"GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4", "GPIOX_5",
	831	"GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9", "GPIOX_10", "GPIOX_11",
	832	"GPIOX_12", "GPIOX_13", "GPIOX_14", "GPIOX_15", "GPIOX_16", "GPIOX_17",
	833	"GPIOX_18", "GPIOX_19",
	834
	835	"GPIOZ_0", "GPIOZ_1", "GPIOZ_2", "GPIOZ_3", "GPIOZ_4", "GPIOZ_5",
	836	"GPIOZ_6", "GPIOZ_7", "GPIOZ_8", "GPIOZ_9", "GPIOZ_10",
	837	"GPIOZ_11", "GPIOZ_12",
	838
	839	"GPIO_TEST_N",
	840	};
	841
	842	static const char * const i2c0_groups[] = {
	843	"i2c0_sda", "i2c0_scl",
	844	};
	845
	846	static const char * const i2c1_groups[] = {
	847	"i2c1_sda_c", "i2c1_scl_c",
	848	"i2c1_sda_d", "i2c1_scl_d",
	849	"i2c1_sda_h", "i2c1_scl_h",
	850	"i2c1_sda_x", "i2c1_scl_x",
	851	};
	852
	853	static const char * const i2c2_groups[] = {
	854	"i2c2_sda_d", "i2c2_scl_d",
	855	"i2c2_sda_h8", "i2c2_scl_h9",
	856	"i2c2_sda_h0", "i2c2_scl_h1l,"
	857	};
	858
	859	static const char * const i2c3_groups[] = {
	860	"i2c3_sda_x", "i2c3_scl_x",
	861	"i2c3_sda_z", "i2c3_scl_z",
	862	};
	863
	864	static const char * const i2c4_groups[] = {
	865	"i2c4_sda_c", "i2c4_scl_c",
	866	"i2c4_sda_d", "i2c4_scl_d",
	867	"i2c4_scl_z", "i2c4_sda_z",
	868	};
	869
	870	static const char * const uart_a_groups[] = {
	871	"uart_a_tx", "uart_a_rx", "uart_a_cts", "uart_a_rts",
	872	};
	873
	874	static const char * const uart_b_groups[] = {
	875	"uart_b_tx_e", "uart_b_rx_e", "uart_b_rx_c", "uart_b_tx_c",
	876	"uart_b_tx_d", "uart_b_rx_d", "uart_b_cts_d", "uart_b_rts_d",
	877	};
	878
	879	static const char * const uart_c_groups[] = {
	880	"uart_c_tx", "uart_c_rx",
	881	};
	882
	883	static const char * const uart_d_groups[] = {
	884	"uart_d_tx_h", "uart_d_rx_h", "uart_d_cts_h", "uart_d_rts_h",
	885	"uart_d_tx_z", "uart_d_rx_z", "uart_d_cts_z", "uart_d_rts_z",
	886	};
	887
	888	static const char * const uart_e_groups[] = {
	889	"uart_e_tx_h", "uart_e_rx_h", "uart_e_tx_z11", "uart_e_rx_z12",
	890	"uart_e_tx_z8", "uart_e_rx_z9",
	891	};
	892
	893	static const char * const emmc_groups[] = {
	894	"emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", "emmc_nand_d3",
	895	"emmc_nand_d4", "emmc_nand_d5", "emmc_nand_d6", "emmc_nand_d7",
	896	"emmc_clk", "emmc_rst", "emmc_cmd", "emmc_nand_ds",
	897	};
	898
	899	static const char * const nand_groups[] = {
	900	"emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", "emmc_nand_d3",
	901	"emmc_nand_d4", "emmc_nand_d5", "emmc_nand_d6", "emmc_nand_d7",
	902	"nand_wen_clk", "nand_ale", "nand_ren_wr", "nand_cle", "nand_ce0",
	903	};
	904
	905	static const char * const spif_groups[] = {
	906	"spif_hold", "spif_mo", "spif_mi", "spif_clk", "spif_wp",
	907	"spif_cs",
	908	};
	909
	910	static const char * const sdcard_groups[] = {
	911	"sdcard_d0_c", "sdcard_d1_c", "sdcard_d2_c", "sdcard_d3_c",
	912	"sdcard_clk_c", "sdcard_cmd_c", "sdcard_cd",
	913	"sdcard_d0_z", "sdcard_d1_z", "sdcard_d2_z", "sdcard_d3_z",
	914	"sdcard_clk_z", "sdcard_cmd_z",
	915	};
	916
	917	static const char * const jtag_1_groups[] = {
	918	"jtag_1_clk", "jtag_1_tms", "jtag_1_tdi", "jtag_1_tdo",
	919	};
	920
	921	static const char * const jtag_2_groups[] = {
	922	"jtag_2_tdo", "jtag_2_tdi", "jtag_2_clk", "jtag_2_tms",
	923	};
	924
	925	static const char * const pdm_groups[] = {
	926	"pdm_din1_c", "pdm_din0_c", "pdm_dclk_c",
	927	"pdm_dclk_d", "pdm_din0_d", "pdm_din1_d",
	928	"pdm_dclk_h", "pdm_din0_h", "pdm_din1_h",
	929	"pdm_din0_x", "pdm_din1_x", "pdm_dclk_x",
	930	"pdm_din1_z", "pdm_din0_z", "pdm_dclk_z",
	931	};
	932
	933	static const char * const iso7816_groups[] = {
	934	"iso7816_clk_c", "iso7816_data_c",
	935	"iso7816_clk_h", "iso7816_data_h",
	936	};
	937
	938	static const char * const tdm_groups[] = {
	939	"tdm_d2_c", "tdm_d3_c", "tdm_fs1_c", "tdm_d4_c", "tdm_d5_c",
	940	"tdm_fs1_d", "tdm_d4_d", "tdm_d3_d", "tdm_d2_d", "tdm_sclk1_d",
	941	"tdm_sclk1_h", "tdm_fs1_h", "tdm_d2_h", "tdm_d3_h", "tdm_d4_h",
	942	"tdm_d1", "tdm_d0", "tdm_fs0", "tdm_sclk0", "tdm_fs2", "tdm_sclk2",
	943	"tdm_d4_z", "tdm_d5_z", "tdm_d6", "tdm_d7",
	944	};
	945
	946	static const char * const mclk_1_groups[] = {
	947	"mclk_1_c", "mclk_1_d", "mclk_1_h", "mclk_2",
	948	};
	949
	950	static const char * const mclk_2_groups[] = {
	951	"mclk_2",
	952	};
	953
	954	static const char * const remote_out_groups[] = {
	955	"remote_out",
	956	};
	957
	958	static const char * const remote_in_groups[] = {
	959	"remote_in",
	960	};
	961
	962	static const char * const clk12_24_groups[] = {
	963	"clk12_24",
	964	};
	965
	966	static const char * const clk_32k_in_groups[] = {
	967	"clk_32k_in",
	968	};
	969
	970	static const char * const pwm_a_hiz_groups[] = {
	971	"pwm_a_hiz",
	972	};
	973
	974	static const char * const pwm_b_hiz_groups[] = {
	975	"pwm_b_hiz",
	976	};
	977
	978	static const char * const pwm_c_hiz_groups[] = {
	979	"pwm_c_hiz",
	980	};
	981
	982	static const char * const pwm_g_hiz_groups[] = {
	983	"pwm_g_hiz",
	984	};
	985
	986	static const char * const pwm_a_groups[] = {
	987	"pwm_a_d",
	988	};
	989
	990	static const char * const pwm_b_groups[] = {
	991	"pwm_b_d", "pwm_b_x",
	992	};
	993
	994	static const char * const pwm_c_groups[] = {
	995	"pwm_c_d", "pwm_c_x",
	996	};
	997
	998	static const char * const pwm_d_groups[] = {
	999	"pwm_d_d", "pwm_d_h",
	1000	};
	1001
	1002	static const char * const pwm_e_groups[] = {
	1003	"pwm_e_x", "pwm_e_z",
	1004	};
	1005
	1006	static const char * const pwm_f_groups[] = {
	1007	"pwm_f_x", "pwm_f_z",
	1008	};
	1009
	1010	static const char * const pwm_g_groups[] = {
	1011	"pwm_g_d", "pwm_g_z",
	1012	};
	1013
	1014	static const char * const pwm_h_groups[] = {
	1015	"pwm_h",
	1016	};
	1017
	1018	static const char * const pwm_i_groups[] = {
	1019	"pwm_i_d", "pwm_i_h"
	1020	};
	1021
	1022	static const char * const pwm_j_groups[] = {
	1023	"pwm_j",
	1024	};
	1025
	1026	static const char * const mic_mute_groups[] = {
	1027	"mic_mute_en", "mic_mute_key",
	1028	};
	1029
	1030	static const char * const hdmitx_groups[] = {
	1031	"hdmitx_sda", "hdmitx_sck", "hdmitx_hpd_in",
	1032	};
	1033
	1034	static const char * const ao_cec_a_groups[] = {
	1035	"ao_cec_a",
	1036	};
	1037
	1038	static const char * const ao_cec_b_groups[] = {
	1039	"ao_cec_b",
	1040	};
	1041
	1042	static const char * const spdif_out_groups[] = {
	1043	"spdif_out_h", "spdif_out_z",
	1044	};
	1045
	1046	static const char * const spdif_in_groups[] = {
	1047	"spdif_in",
	1048	};
	1049
	1050	static const char * const eth_groups[] = {
	1051	"eth_link_led", "eth_act_led",
	1052	};
	1053
	1054	static const char * const spi_a_groups[] = {
	1055	"spi_a_miso_h", "spi_a_mosi_h", "spi_a_clk_h", "spi_a_ss0_h",
	1056
	1057	"spi_a_mosi_x", "spi_a_miso_x", "spi_a_ss0_x", "spi_a_clk_x",
	1058
	1059	"spi_a_miso_z", "spi_a_mosi_z", "spi_a_clk_z", "spi_a_ss0_z",
	1060	"spi_a_ss1_z", "spi_a_ss2_z",
	1061	};
	1062
	1063	static const char * const gen_clk_groups[] = {
	1064	"gen_clk_h", "gen_clk_z9", "gen_clk_z12",
	1065	};
	1066
	1067	static const char * const sdio_groups[] = {
	1068	"sdio_d0", "sdio_d1", "sdio_d2", "sdio_d3", "sdio_clk", "sdio_cmd",
	1069	};
	1070
	1071	static const char * const i2c_slave_groups[] = {
	1072	"i2c_slave_scl", "i2c_slave_sda",
	1073	};
	1074
	1075	static const char * const dtv_groups[] = {
	1076	"dtv_a_if_agc_z10", "dtv_a_if_agc_z6", "dtv_b_if_agc",
	1077	"dtv_a_rf_agc", "dtv_b_rf_agc",
	1078	};
	1079
	1080	static const char * const tsin_a_groups[] = {
	1081	"tsin_a_clk", "tsin_a_sop", "tsin_a_valid", "tsin_a_din0",
	1082	};
	1083
	1084	static const char * const tsin_b_groups[] = {
	1085	"tsin_b_clk_c", "tsin_b_sop_c", "tsin_b_valid_c", "tsin_b_d0_c",
	1086	"tsin_b_clk_z", "tsin_b_sop_z", "tsin_b_valid_z", "tsin_b_d0_z",
	1087	};
	1088
	1089	static const char * const tsin_b1_groups[] = {
	1090	"tsin_b1_clk", "tsin_b1_sop", "tsin_b1_valid", "tsin_b1_d0",
	1091	};
	1092
	1093	static const char * const diseqc_out_groups[] = {
	1094	"diseqc_out",
	1095	};
	1096
	1097	static const char * const s2_demod_groups[] = {
	1098	"s2_demod_gpio7", "s2_demod_gpio6", "s2_demod_gpio5", "s2_demod_gpio4",
	1099	"s2_demod_gpio3", "s2_demod_gpio2", "s2_demod_gpio1", "s2_demod_gpio0",
	1100	};
	1101
	1102	static struct meson_pmx_func meson_s4_periphs_functions[] = {
	1103	FUNCTION(gpio_periphs),
	1104	FUNCTION(i2c0),
	1105	FUNCTION(i2c1),
	1106	FUNCTION(i2c2),
	1107	FUNCTION(i2c3),
	1108	FUNCTION(i2c4),
	1109	FUNCTION(uart_a),
	1110	FUNCTION(uart_b),
	1111	FUNCTION(uart_c),
	1112	FUNCTION(uart_d),
	1113	FUNCTION(uart_e),
	1114	FUNCTION(emmc),
	1115	FUNCTION(nand),
	1116	FUNCTION(spif),
	1117	FUNCTION(sdcard),
	1118	FUNCTION(jtag_1),
	1119	FUNCTION(jtag_2),
	1120	FUNCTION(pdm),
	1121	FUNCTION(iso7816),
	1122	FUNCTION(tdm),
	1123	FUNCTION(mclk_1),
	1124	FUNCTION(mclk_2),
	1125	FUNCTION(remote_out),
	1126	FUNCTION(remote_in),
	1127	FUNCTION(clk12_24),
	1128	FUNCTION(clk_32k_in),
	1129	FUNCTION(pwm_a_hiz),
	1130	FUNCTION(pwm_b_hiz),
	1131	FUNCTION(pwm_c_hiz),
	1132	FUNCTION(pwm_g_hiz),
	1133	FUNCTION(pwm_a),
	1134	FUNCTION(pwm_b),
	1135	FUNCTION(pwm_c),
	1136	FUNCTION(pwm_d),
	1137	FUNCTION(pwm_e),
	1138	FUNCTION(pwm_f),
	1139	FUNCTION(pwm_g),
	1140	FUNCTION(pwm_h),
	1141	FUNCTION(pwm_i),
	1142	FUNCTION(pwm_j),
	1143	FUNCTION(mic_mute),
	1144	FUNCTION(hdmitx),
	1145	FUNCTION(ao_cec_a),
	1146	FUNCTION(ao_cec_b),
	1147	FUNCTION(spdif_out),
	1148	FUNCTION(spdif_in),
	1149	FUNCTION(eth),
	1150	FUNCTION(spi_a),
	1151	FUNCTION(gen_clk),
	1152	FUNCTION(sdio),
	1153	FUNCTION(i2c_slave),
	1154	FUNCTION(dtv),
	1155	FUNCTION(tsin_a),
	1156	FUNCTION(tsin_b),
	1157	FUNCTION(tsin_b1),
	1158	FUNCTION(diseqc_out),
	1159	FUNCTION(s2_demod),
	1160	};
	1161
	1162	static struct meson_bank meson_s4_periphs_banks[] = {
	1163	/* name first last irq pullen pull dir out in */
	1164	BANK_DS("B", GPIOB_0, GPIOB_13, 0, 13,
	1165	0x63, 0, 0x64, 0, 0x62, 0, 0x61, 0, 0x60, 0, 0x67, 0),
	1166	BANK_DS("C", GPIOC_0, GPIOC_7, 14, 21,
	1167	0x53, 0, 0x54, 0, 0x52, 0, 0x51, 0, 0x50, 0, 0x57, 0),
	1168	BANK_DS("E", GPIOE_0, GPIOE_1, 22, 23,
	1169	0x43, 0, 0x44, 0, 0x42, 0, 0x41, 0, 0x40, 0, 0x47, 0),
	1170	BANK_DS("D", GPIOD_0, GPIOD_11, 24, 35,
	1171	0x33, 0, 0x34, 0, 0x32, 0, 0x31, 0, 0x30, 0, 0x37, 0),
	1172	BANK_DS("H", GPIOH_0, GPIOH_11, 36, 47,
	1173	0x23, 0, 0x24, 0, 0x22, 0, 0x21, 0, 0x20, 0, 0x27, 0),
	1174	BANK_DS("X", GPIOX_0, GPIOX_19, 48, 67,
	1175	0x13, 0, 0x14, 0, 0x12, 0, 0x11, 0, 0x10, 0, 0x17, 0),
	1176	BANK_DS("Z", GPIOZ_0, GPIOZ_12, 68, 80,
	1177	0x03, 0, 0x04, 0, 0x02, 0, 0x01, 0, 0x00, 0, 0x07, 0),
	1178	BANK_DS("TEST_N", GPIO_TEST_N, GPIO_TEST_N, -1, -1,
	1179	0x83, 0, 0x84, 0, 0x82, 0, 0x81, 0, 0x80, 0, 0x87, 0),
	1180	};
	1181
	1182	static struct meson_pmx_bank meson_s4_periphs_pmx_banks[] = {
	1183	/name first lask reg offset/
	1184	BANK_PMX("B", GPIOB_0, GPIOB_13, 0x00, 0),
	1185	BANK_PMX("C", GPIOC_0, GPIOC_7, 0x9, 0),
	1186	BANK_PMX("E", GPIOE_0, GPIOE_1, 0x12, 0),
	1187	BANK_PMX("D", GPIOD_0, GPIOD_11, 0x10, 0),
	1188	BANK_PMX("H", GPIOH_0, GPIOH_11, 0xb, 0),
	1189	BANK_PMX("X", GPIOX_0, GPIOX_19, 0x3, 0),
	1190	BANK_PMX("Z", GPIOZ_0, GPIOZ_12, 0x6, 0),
	1191	BANK_PMX("TEST_N", GPIO_TEST_N, GPIO_TEST_N, 0xf, 0)
	1192	};
	1193
	1194	static struct meson_axg_pmx_data meson_s4_periphs_pmx_banks_data = {
	1195	.pmx_banks = meson_s4_periphs_pmx_banks,
	1196	.num_pmx_banks = ARRAY_SIZE(meson_s4_periphs_pmx_banks),
	1197	};
	1198
	1199	static struct meson_pinctrl_data meson_s4_periphs_pinctrl_data = {
	1200	.name = "periphs-banks",
	1201	.pins = meson_s4_periphs_pins,
	1202	.groups = meson_s4_periphs_groups,
	1203	.funcs = meson_s4_periphs_functions,
	1204	.banks = meson_s4_periphs_banks,
	1205	.num_pins = ARRAY_SIZE(meson_s4_periphs_pins),
	1206	.num_groups = ARRAY_SIZE(meson_s4_periphs_groups),
	1207	.num_funcs = ARRAY_SIZE(meson_s4_periphs_functions),
	1208	.num_banks = ARRAY_SIZE(meson_s4_periphs_banks),
	1209	.pmx_ops = &meson_axg_pmx_ops,
	1210	.pmx_data = &meson_s4_periphs_pmx_banks_data,
	1211	.parse_dt = &meson_a1_parse_dt_extra,
	1212	};
	1213
	1214	static const struct of_device_id meson_s4_pinctrl_dt_match[] = {
	1215	{
	1216	.compatible = "amlogic,meson-s4-periphs-pinctrl",
	1217	.data = &meson_s4_periphs_pinctrl_data,
	1218	},
	1219	{ }
	1220	};
	1221	MODULE_DEVICE_TABLE(of, meson_s4_pinctrl_dt_match);
	1222
	1223	static struct platform_driver meson_s4_pinctrl_driver = {
	1224	.probe = meson_pinctrl_probe,
	1225	.driver = {
	1226	.name = "meson-s4-pinctrl",
	1227	.of_match_table = meson_s4_pinctrl_dt_match,
	1228	},
	1229	};
	1230	module_platform_driver(meson_s4_pinctrl_driver);
	1231
	1232	MODULE_LICENSE("Dual BSD/GPL");

drivers/pinctrl/nomadik/pinctrl-nomadik.c+3−1

 	}
 	prcm_np = of_parse_phandle(np, "prcm", 0);
-	if (prcm_np)
+	if (prcm_np) {
 		npct->prcm_base = of_iomap(prcm_np, 0);
+		of_node_put(prcm_np);
+	}
 	if (!npct->prcm_base) {
 		if (version == PINCTRL_NMK_STN8815) {
 			dev_info(&pdev->dev,

drivers/pinctrl/nuvoton/Kconfig+20−0

@@ -1,4 +1,24 @@
1	# SPDX-License-Identifier: GPL-2.0-only	1	# SPDX-License-Identifier: GPL-2.0-only
		2
		3	config PINCTRL_WPCM450
		4	tristate "Pinctrl and GPIO driver for Nuvoton WPCM450"
		5	depends on ARCH_WPCM450 \|\| COMPILE_TEST
		6	depends on OF
		7	select PINMUX
		8	select PINCONF
		9	select GENERIC_PINCONF
		10	select GENERIC_PINCTRL_GROUPS
		11	select GPIOLIB
		12	select GPIO_GENERIC
		13	select GPIOLIB_IRQCHIP
		14	help
		15	Say Y or M here to enable pin controller and GPIO support for
		16	the Nuvoton WPCM450 SoC. This is strongly recommended when
		17	building a kernel that will run on this chip.
		18
		19	If this driver is compiled as a module, it will be named
		20	pinctrl-wpcm450.
		21
2	config PINCTRL_NPCM7XX	22	config PINCTRL_NPCM7XX
3	bool "Pinctrl and GPIO driver for Nuvoton NPCM7XX"	23	bool "Pinctrl and GPIO driver for Nuvoton NPCM7XX"
4	depends on (ARCH_NPCM7XX \|\| COMPILE_TEST) && OF	24	depends on (ARCH_NPCM7XX \|\| COMPILE_TEST) && OF

drivers/pinctrl/nuvoton/Makefile+1−0

@@ -1,4 +1,5 @@
1	# SPDX-License-Identifier: GPL-2.0	1	# SPDX-License-Identifier: GPL-2.0
2	# Nuvoton pinctrl support	2	# Nuvoton pinctrl support
3		3
		4	obj-$(CONFIG_PINCTRL_WPCM450) += pinctrl-wpcm450.o
4	obj-$(CONFIG_PINCTRL_NPCM7XX) += pinctrl-npcm7xx.o	5	obj-$(CONFIG_PINCTRL_NPCM7XX) += pinctrl-npcm7xx.o

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c+84−84

drivers/pinctrl/nuvoton/pinctrl-wpcm450.c+1151−0

@@ -0,0 +1,1151 @@
	1	// SPDX-License-Identifier: GPL-2.0
	2	// Copyright (c) 2016-2018 Nuvoton Technology corporation.
	3	// Copyright (c) 2016, Dell Inc
	4	// Copyright (c) 2021-2022 Jonathan Neuschäfer
	5	//
	6	// This driver uses the following registers:
	7	// - Pin mux registers, in the GCR (general control registers) block
	8	// - GPIO registers, specific to each GPIO bank
	9	// - GPIO event (interrupt) registers, located centrally in the GPIO register
	10	// block, shared between all GPIO banks
	11
	12	#include <linux/device.h>
	13	#include <linux/fwnode.h>
	14	#include <linux/gpio/driver.h>
	15	#include <linux/interrupt.h>
	16	#include <linux/irq.h>
	17	#include <linux/mfd/syscon.h>
	18	#include <linux/module.h>
	19	#include <linux/mod_devicetable.h>
	20	#include <linux/platform_device.h>
	21	#include <linux/regmap.h>
	22
	23	#include <linux/pinctrl/pinconf.h>
	24	#include <linux/pinctrl/pinconf-generic.h>
	25	#include <linux/pinctrl/pinctrl.h>
	26	#include <linux/pinctrl/pinmux.h>
	27
	28	#include "../core.h"
	29
	30	/* GCR registers */
	31	#define WPCM450_GCR_MFSEL1 0x0c
	32	#define WPCM450_GCR_MFSEL2 0x10
	33	#define WPCM450_GCR_NONE 0
	34
	35	/* GPIO event (interrupt) registers */
	36	#define WPCM450_GPEVTYPE 0x00
	37	#define WPCM450_GPEVPOL 0x04
	38	#define WPCM450_GPEVDBNC 0x08
	39	#define WPCM450_GPEVEN 0x0c
	40	#define WPCM450_GPEVST 0x10
	41
	42	#define WPCM450_NUM_BANKS 8
	43	#define WPCM450_NUM_GPIOS 128
	44	#define WPCM450_NUM_GPIO_IRQS 4
	45
	46	struct wpcm450_pinctrl;
	47	struct wpcm450_bank;
	48
	49	struct wpcm450_gpio {
	50	struct gpio_chip gc;
	51	struct wpcm450_pinctrl *pctrl;
	52	struct irq_chip irqc;
	53	const struct wpcm450_bank *bank;
	54	};
	55
	56	struct wpcm450_pinctrl {
	57	struct pinctrl_dev *pctldev;
	58	struct device *dev;
	59	struct irq_domain *domain;
	60	struct regmap *gcr_regmap;
	61	void __iomem *gpio_base;
	62	struct wpcm450_gpio gpio_bank[WPCM450_NUM_BANKS];
	63	unsigned long both_edges;
	64
	65	/*
	66	* This spin lock protects registers and struct wpcm450_pinctrl fields
	67	* against concurrent access.
	68	*/
	69	raw_spinlock_t lock;
	70	};
	71
	72	struct wpcm450_bank {
	73	/* Range of GPIOs in this port */
	74	u8 base;
	75	u8 length;
	76
	77	/* Register offsets (0 = register doesn't exist in this port) */
	78	u8 cfg0, cfg1, cfg2;
	79	u8 blink;
	80	u8 dataout, datain;
	81
	82	/* Interrupt bit mapping */
	83	u8 first_irq_bit; /* First bit in GPEVST that belongs to this bank */
	84	u8 num_irqs; /* Number of IRQ-capable GPIOs in this bank */
	85	u8 first_irq_gpio; /* First IRQ-capable GPIO in this bank */
	86	};
	87
	88	static const struct wpcm450_bank wpcm450_banks[WPCM450_NUM_BANKS] = {
	89	/* range cfg0 cfg1 cfg2 blink out in IRQ map */
	90	{ 0, 16, 0x14, 0x18, 0, 0, 0x1c, 0x20, 0, 16, 0 },
	91	{ 16, 16, 0x24, 0x28, 0x2c, 0x30, 0x34, 0x38, 16, 2, 8 },
	92	{ 32, 16, 0x3c, 0x40, 0x44, 0, 0x48, 0x4c, 0, 0, 0 },
	93	{ 48, 16, 0x50, 0x54, 0x58, 0, 0x5c, 0x60, 0, 0, 0 },
	94	{ 64, 16, 0x64, 0x68, 0x6c, 0, 0x70, 0x74, 0, 0, 0 },
	95	{ 80, 16, 0x78, 0x7c, 0x80, 0, 0x84, 0x88, 0, 0, 0 },
	96	{ 96, 18, 0, 0, 0, 0, 0, 0x8c, 0, 0, 0 },
	97	{ 114, 14, 0x90, 0x94, 0x98, 0, 0x9c, 0xa0, 0, 0, 0 },
	98	};
	99
	100	static int wpcm450_gpio_irq_bitnum(struct wpcm450_gpio gpio, struct irq_data d)
	101	{
	102	const struct wpcm450_bank *bank = gpio->bank;
	103	int hwirq = irqd_to_hwirq(d);
	104
	105	if (hwirq < bank->first_irq_gpio)
	106	return -EINVAL;
	107
	108	if (hwirq - bank->first_irq_gpio >= bank->num_irqs)
	109	return -EINVAL;
	110
	111	return hwirq - bank->first_irq_gpio + bank->first_irq_bit;
	112	}
	113
	114	static int wpcm450_irq_bitnum_to_gpio(struct wpcm450_gpio *gpio, int bitnum)
	115	{
	116	const struct wpcm450_bank *bank = gpio->bank;
	117
	118	if (bitnum < bank->first_irq_bit)
	119	return -EINVAL;
	120
	121	if (bitnum - bank->first_irq_bit > bank->num_irqs)
	122	return -EINVAL;
	123
	124	return bitnum - bank->first_irq_bit + bank->first_irq_gpio;
	125	}
	126
	127	static void wpcm450_gpio_irq_ack(struct irq_data *d)
	128	{
	129	struct wpcm450_gpio *gpio = gpiochip_get_data(irq_data_get_irq_chip_data(d));
	130	struct wpcm450_pinctrl *pctrl = gpio->pctrl;
	131	unsigned long flags;
	132	int bit;
	133
	134	bit = wpcm450_gpio_irq_bitnum(gpio, d);
	135	if (bit < 0)
	136	return;
	137
	138	raw_spin_lock_irqsave(&pctrl->lock, flags);
	139	iowrite32(BIT(bit), pctrl->gpio_base + WPCM450_GPEVST);
	140	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
	141	}
	142
	143	static void wpcm450_gpio_irq_mask(struct irq_data *d)
	144	{
	145	struct wpcm450_gpio *gpio = gpiochip_get_data(irq_data_get_irq_chip_data(d));
	146	struct wpcm450_pinctrl *pctrl = gpio->pctrl;
	147	unsigned long flags;
	148	unsigned long even;
	149	int bit;
	150
	151	bit = wpcm450_gpio_irq_bitnum(gpio, d);
	152	if (bit < 0)
	153	return;
	154
	155	raw_spin_lock_irqsave(&pctrl->lock, flags);
	156	even = ioread32(pctrl->gpio_base + WPCM450_GPEVEN);
	157	__assign_bit(bit, &even, 0);
	158	iowrite32(even, pctrl->gpio_base + WPCM450_GPEVEN);
	159	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
	160	}
	161
	162	static void wpcm450_gpio_irq_unmask(struct irq_data *d)
	163	{
	164	struct wpcm450_gpio *gpio = gpiochip_get_data(irq_data_get_irq_chip_data(d));
	165	struct wpcm450_pinctrl *pctrl = gpio->pctrl;
	166	unsigned long flags;
	167	unsigned long even;
	168	int bit;
	169
	170	bit = wpcm450_gpio_irq_bitnum(gpio, d);
	171	if (bit < 0)
	172	return;
	173
	174	raw_spin_lock_irqsave(&pctrl->lock, flags);
	175	even = ioread32(pctrl->gpio_base + WPCM450_GPEVEN);
	176	__assign_bit(bit, &even, 1);
	177	iowrite32(even, pctrl->gpio_base + WPCM450_GPEVEN);
	178	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
	179	}
	180
	181	/*
	182	* This is an implementation of the gpio_chip->get() function, for use in
	183	* wpcm450_gpio_fix_evpol. Unfortunately, we can't use the bgpio-provided
	184	* implementation there, because it would require taking gpio_chip->bgpio_lock,
	185	* which is a spin lock, but wpcm450_gpio_fix_evpol must work in contexts where
	186	* a raw spin lock is held.
	187	*/
	188	static int wpcm450_gpio_get(struct wpcm450_gpio *gpio, int offset)
	189	{
	190	void __iomem *reg = gpio->pctrl->gpio_base + gpio->bank->datain;
	191	unsigned long flags;
	192	u32 level;
	193
	194	raw_spin_lock_irqsave(&gpio->pctrl->lock, flags);
	195	level = !!(ioread32(reg) & BIT(offset));
	196	raw_spin_unlock_irqrestore(&gpio->pctrl->lock, flags);
	197
	198	return level;
	199	}
	200
	201	/*
	202	* Since the GPIO controller does not support dual-edge triggered interrupts
	203	* (IRQ_TYPE_EDGE_BOTH), they are emulated using rising/falling edge triggered
	204	* interrupts. wpcm450_gpio_fix_evpol sets the interrupt polarity for the
	205	* specified emulated dual-edge triggered interrupts, so that the next edge can
	206	* be detected.
	207	*/
	208	static void wpcm450_gpio_fix_evpol(struct wpcm450_gpio *gpio, unsigned long all)
	209	{
	210	struct wpcm450_pinctrl *pctrl = gpio->pctrl;
	211	unsigned int bit;
	212
	213	for_each_set_bit(bit, &all, 32) {
	214	int offset = wpcm450_irq_bitnum_to_gpio(gpio, bit);
	215	unsigned long evpol;
	216	unsigned long flags;
	217	int level;
	218
	219	do {
	220	level = wpcm450_gpio_get(gpio, offset);
	221
	222	/* Switch event polarity to the opposite of the current level */
	223	raw_spin_lock_irqsave(&pctrl->lock, flags);
	224	evpol = ioread32(pctrl->gpio_base + WPCM450_GPEVPOL);
	225	__assign_bit(bit, &evpol, !level);
	226	iowrite32(evpol, pctrl->gpio_base + WPCM450_GPEVPOL);
	227	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
	228
	229	} while (wpcm450_gpio_get(gpio, offset) != level);
	230	}
	231	}
	232
	233	static int wpcm450_gpio_set_irq_type(struct irq_data *d, unsigned int flow_type)
	234	{
	235	struct wpcm450_gpio *gpio = gpiochip_get_data(irq_data_get_irq_chip_data(d));
	236	struct wpcm450_pinctrl *pctrl = gpio->pctrl;
	237	unsigned long evtype, evpol;
	238	unsigned long flags;
	239	int ret = 0;
	240	int bit;
	241
	242	bit = wpcm450_gpio_irq_bitnum(gpio, d);
	243	if (bit < 0)
	244	return bit;
	245
	246	irq_set_handler_locked(d, handle_level_irq);
	247
	248	raw_spin_lock_irqsave(&pctrl->lock, flags);
	249	evtype = ioread32(pctrl->gpio_base + WPCM450_GPEVTYPE);
	250	evpol = ioread32(pctrl->gpio_base + WPCM450_GPEVPOL);
	251	__assign_bit(bit, &pctrl->both_edges, 0);
	252	switch (flow_type) {
	253	case IRQ_TYPE_LEVEL_LOW:
	254	__assign_bit(bit, &evtype, 1);
	255	__assign_bit(bit, &evpol, 0);
	256	break;
	257	case IRQ_TYPE_LEVEL_HIGH:
	258	__assign_bit(bit, &evtype, 1);
	259	__assign_bit(bit, &evpol, 1);
	260	break;
	261	case IRQ_TYPE_EDGE_FALLING:
	262	__assign_bit(bit, &evtype, 0);
	263	__assign_bit(bit, &evpol, 0);
	264	break;
	265	case IRQ_TYPE_EDGE_RISING:
	266	__assign_bit(bit, &evtype, 0);
	267	__assign_bit(bit, &evpol, 1);
	268	break;
	269	case IRQ_TYPE_EDGE_BOTH:
	270	__assign_bit(bit, &evtype, 0);
	271	__assign_bit(bit, &pctrl->both_edges, 1);
	272	break;
	273	default:
	274	ret = -EINVAL;
	275	}
	276	iowrite32(evtype, pctrl->gpio_base + WPCM450_GPEVTYPE);
	277	iowrite32(evpol, pctrl->gpio_base + WPCM450_GPEVPOL);
	278
	279	/* clear the event status for good measure */
	280	iowrite32(BIT(bit), pctrl->gpio_base + WPCM450_GPEVST);
	281
	282	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
	283
	284	/* fix event polarity after clearing event status */
	285	wpcm450_gpio_fix_evpol(gpio, BIT(bit));
	286
	287	return ret;
	288	}
	289
	290	static const struct irq_chip wpcm450_gpio_irqchip = {
	291	.name = "WPCM450-GPIO-IRQ",
	292	.irq_ack = wpcm450_gpio_irq_ack,
	293	.irq_unmask = wpcm450_gpio_irq_unmask,
	294	.irq_mask = wpcm450_gpio_irq_mask,
	295	.irq_set_type = wpcm450_gpio_set_irq_type,
	296	};
	297
	298	static void wpcm450_gpio_irqhandler(struct irq_desc *desc)
	299	{
	300	struct wpcm450_gpio *gpio = gpiochip_get_data(irq_desc_get_handler_data(desc));
	301	struct wpcm450_pinctrl *pctrl = gpio->pctrl;
	302	struct irq_chip *chip = irq_desc_get_chip(desc);
	303	unsigned long pending;
	304	unsigned long flags;
	305	unsigned long ours;
	306	unsigned int bit;
	307
	308	ours = GENMASK(gpio->bank->num_irqs - 1, 0) << gpio->bank->first_irq_bit;
	309
	310	raw_spin_lock_irqsave(&pctrl->lock, flags);
	311
	312	pending = ioread32(pctrl->gpio_base + WPCM450_GPEVST);
	313	pending &= ioread32(pctrl->gpio_base + WPCM450_GPEVEN);
	314	pending &= ours;
	315
	316	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
	317
	318	if (pending & pctrl->both_edges)
	319	wpcm450_gpio_fix_evpol(gpio, pending & pctrl->both_edges);
	320
	321	chained_irq_enter(chip, desc);
	322	for_each_set_bit(bit, &pending, 32) {
	323	int offset = wpcm450_irq_bitnum_to_gpio(gpio, bit);
	324
	325	generic_handle_domain_irq(gpio->gc.irq.domain, offset);
	326	}
	327	chained_irq_exit(chip, desc);
	328	}
	329
	330	static int smb0_pins[] = { 115, 114 };
	331	static int smb1_pins[] = { 117, 116 };
	332	static int smb2_pins[] = { 119, 118 };
	333	static int smb3_pins[] = { 30, 31 };
	334	static int smb4_pins[] = { 28, 29 };
	335	static int smb5_pins[] = { 26, 27 };
	336
	337	static int scs1_pins[] = { 32 };
	338	static int scs2_pins[] = { 33 };
	339	static int scs3_pins[] = { 34 };
	340
	341	static int bsp_pins[] = { 41, 42 };
	342	static int hsp1_pins[] = { 43, 44, 45, 46, 47, 61, 62, 63 };
	343	static int hsp2_pins[] = { 48, 49, 50, 51, 52, 53, 54, 55 };
	344
	345	static int r1err_pins[] = { 56 };
	346	static int r1md_pins[] = { 57, 58 };
	347	static int rmii2_pins[] = { 84, 85, 86, 87, 88, 89 };
	348	static int r2err_pins[] = { 90 };
	349	static int r2md_pins[] = { 91, 92 };
	350
	351	static int kbcc_pins[] = { 94, 93 };
	352	static int clko_pins[] = { 96 };
	353	static int smi_pins[] = { 97 };
	354	static int uinc_pins[] = { 19 };
	355	static int mben_pins[] = {};
	356
	357	static int gspi_pins[] = { 12, 13, 14, 15 };
	358	static int sspi_pins[] = { 12, 13, 14, 15 };
	359
	360	static int xcs1_pins[] = { 35 };
	361	static int xcs2_pins[] = { 36 };
	362
	363	static int sdio_pins[] = { 7, 22, 43, 44, 45, 46, 47, 60 };
	364
	365	static int fi0_pins[] = { 64 };
	366	static int fi1_pins[] = { 65 };
	367	static int fi2_pins[] = { 66 };
	368	static int fi3_pins[] = { 67 };
	369	static int fi4_pins[] = { 68 };
	370	static int fi5_pins[] = { 69 };
	371	static int fi6_pins[] = { 70 };
	372	static int fi7_pins[] = { 71 };
	373	static int fi8_pins[] = { 72 };
	374	static int fi9_pins[] = { 73 };
	375	static int fi10_pins[] = { 74 };
	376	static int fi11_pins[] = { 75 };
	377	static int fi12_pins[] = { 76 };
	378	static int fi13_pins[] = { 77 };
	379	static int fi14_pins[] = { 78 };
	380	static int fi15_pins[] = { 79 };
	381
	382	static int pwm0_pins[] = { 80 };
	383	static int pwm1_pins[] = { 81 };
	384	static int pwm2_pins[] = { 82 };
	385	static int pwm3_pins[] = { 83 };
	386	static int pwm4_pins[] = { 20 };
	387	static int pwm5_pins[] = { 21 };
	388	static int pwm6_pins[] = { 16 };
	389	static int pwm7_pins[] = { 17 };
	390
	391	static int hg0_pins[] = { 20 };
	392	static int hg1_pins[] = { 21 };
	393	static int hg2_pins[] = { 22 };
	394	static int hg3_pins[] = { 23 };
	395	static int hg4_pins[] = { 24 };
	396	static int hg5_pins[] = { 25 };
	397	static int hg6_pins[] = { 59 };
	398	static int hg7_pins[] = { 60 };
	399
	400	#define WPCM450_GRPS \
	401	WPCM450_GRP(smb3), \
	402	WPCM450_GRP(smb4), \
	403	WPCM450_GRP(smb5), \
	404	WPCM450_GRP(scs1), \
	405	WPCM450_GRP(scs2), \
	406	WPCM450_GRP(scs3), \
	407	WPCM450_GRP(smb0), \
	408	WPCM450_GRP(smb1), \
	409	WPCM450_GRP(smb2), \
	410	WPCM450_GRP(bsp), \
	411	WPCM450_GRP(hsp1), \
	412	WPCM450_GRP(hsp2), \
	413	WPCM450_GRP(r1err), \
	414	WPCM450_GRP(r1md), \
	415	WPCM450_GRP(rmii2), \
	416	WPCM450_GRP(r2err), \
	417	WPCM450_GRP(r2md), \
	418	WPCM450_GRP(kbcc), \
	419	WPCM450_GRP(clko), \
	420	WPCM450_GRP(smi), \
	421	WPCM450_GRP(uinc), \
	422	WPCM450_GRP(gspi), \
	423	WPCM450_GRP(mben), \
	424	WPCM450_GRP(xcs2), \
	425	WPCM450_GRP(xcs1), \
	426	WPCM450_GRP(sdio), \
	427	WPCM450_GRP(sspi), \
	428	WPCM450_GRP(fi0), \
	429	WPCM450_GRP(fi1), \
	430	WPCM450_GRP(fi2), \
	431	WPCM450_GRP(fi3), \
	432	WPCM450_GRP(fi4), \
	433	WPCM450_GRP(fi5), \
	434	WPCM450_GRP(fi6), \
	435	WPCM450_GRP(fi7), \
	436	WPCM450_GRP(fi8), \
	437	WPCM450_GRP(fi9), \
	438	WPCM450_GRP(fi10), \
	439	WPCM450_GRP(fi11), \
	440	WPCM450_GRP(fi12), \
	441	WPCM450_GRP(fi13), \
	442	WPCM450_GRP(fi14), \
	443	WPCM450_GRP(fi15), \
	444	WPCM450_GRP(pwm0), \
	445	WPCM450_GRP(pwm1), \
	446	WPCM450_GRP(pwm2), \
	447	WPCM450_GRP(pwm3), \
	448	WPCM450_GRP(pwm4), \
	449	WPCM450_GRP(pwm5), \
	450	WPCM450_GRP(pwm6), \
	451	WPCM450_GRP(pwm7), \
	452	WPCM450_GRP(hg0), \
	453	WPCM450_GRP(hg1), \
	454	WPCM450_GRP(hg2), \
	455	WPCM450_GRP(hg3), \
	456	WPCM450_GRP(hg4), \
	457	WPCM450_GRP(hg5), \
	458	WPCM450_GRP(hg6), \
	459	WPCM450_GRP(hg7), \
	460
	461	enum {
	462	#define WPCM450_GRP(x) fn_ ## x
	463	WPCM450_GRPS
	464	/* add placeholder for none/gpio */
	465	WPCM450_GRP(gpio),
	466	WPCM450_GRP(none),
	467	#undef WPCM450_GRP
	468	};
	469
	470	static struct group_desc wpcm450_groups[] = {
	471	#define WPCM450_GRP(x) { .name = #x, .pins = x ## _pins, \
	472	.num_pins = ARRAY_SIZE(x ## _pins) }
	473	WPCM450_GRPS
	474	#undef WPCM450_GRP
	475	};
	476
	477	#define WPCM450_SFUNC(a) WPCM450_FUNC(a, #a)
	478	#define WPCM450_FUNC(a, b...) static const char *a ## _grp[] = { b }
	479	#define WPCM450_MKFUNC(nm) { .name = #nm, .ngroups = ARRAY_SIZE(nm ## _grp), \
	480	.groups = nm ## _grp }
	481	struct wpcm450_func {
	482	const char *name;
	483	const unsigned int ngroups;
	484	const char const groups;
	485	};
	486
	487	WPCM450_SFUNC(smb3);
	488	WPCM450_SFUNC(smb4);
	489	WPCM450_SFUNC(smb5);
	490	WPCM450_SFUNC(scs1);
	491	WPCM450_SFUNC(scs2);
	492	WPCM450_SFUNC(scs3);
	493	WPCM450_SFUNC(smb0);
	494	WPCM450_SFUNC(smb1);
	495	WPCM450_SFUNC(smb2);
	496	WPCM450_SFUNC(bsp);
	497	WPCM450_SFUNC(hsp1);
	498	WPCM450_SFUNC(hsp2);
	499	WPCM450_SFUNC(r1err);
	500	WPCM450_SFUNC(r1md);
	501	WPCM450_SFUNC(rmii2);
	502	WPCM450_SFUNC(r2err);
	503	WPCM450_SFUNC(r2md);
	504	WPCM450_SFUNC(kbcc);
	505	WPCM450_SFUNC(clko);
	506	WPCM450_SFUNC(smi);
	507	WPCM450_SFUNC(uinc);
	508	WPCM450_SFUNC(gspi);
	509	WPCM450_SFUNC(mben);
	510	WPCM450_SFUNC(xcs2);
	511	WPCM450_SFUNC(xcs1);
	512	WPCM450_SFUNC(sdio);
	513	WPCM450_SFUNC(sspi);
	514	WPCM450_SFUNC(fi0);
	515	WPCM450_SFUNC(fi1);
	516	WPCM450_SFUNC(fi2);
	517	WPCM450_SFUNC(fi3);
	518	WPCM450_SFUNC(fi4);
	519	WPCM450_SFUNC(fi5);
	520	WPCM450_SFUNC(fi6);
	521	WPCM450_SFUNC(fi7);
	522	WPCM450_SFUNC(fi8);
	523	WPCM450_SFUNC(fi9);
	524	WPCM450_SFUNC(fi10);
	525	WPCM450_SFUNC(fi11);
	526	WPCM450_SFUNC(fi12);
	527	WPCM450_SFUNC(fi13);
	528	WPCM450_SFUNC(fi14);
	529	WPCM450_SFUNC(fi15);
	530	WPCM450_SFUNC(pwm0);
	531	WPCM450_SFUNC(pwm1);
	532	WPCM450_SFUNC(pwm2);
	533	WPCM450_SFUNC(pwm3);
	534	WPCM450_SFUNC(pwm4);
	535	WPCM450_SFUNC(pwm5);
	536	WPCM450_SFUNC(pwm6);
	537	WPCM450_SFUNC(pwm7);
	538	WPCM450_SFUNC(hg0);
	539	WPCM450_SFUNC(hg1);
	540	WPCM450_SFUNC(hg2);
	541	WPCM450_SFUNC(hg3);
	542	WPCM450_SFUNC(hg4);
	543	WPCM450_SFUNC(hg5);
	544	WPCM450_SFUNC(hg6);
	545	WPCM450_SFUNC(hg7);
	546
	547	#define WPCM450_GRP(x) #x
	548	WPCM450_FUNC(gpio, WPCM450_GRPS);
	549	#undef WPCM450_GRP
	550
	551	/* Function names */
	552	static struct wpcm450_func wpcm450_funcs[] = {
	553	WPCM450_MKFUNC(smb3),
	554	WPCM450_MKFUNC(smb4),
	555	WPCM450_MKFUNC(smb5),
	556	WPCM450_MKFUNC(scs1),
	557	WPCM450_MKFUNC(scs2),
	558	WPCM450_MKFUNC(scs3),
	559	WPCM450_MKFUNC(smb0),
	560	WPCM450_MKFUNC(smb1),
	561	WPCM450_MKFUNC(smb2),
	562	WPCM450_MKFUNC(bsp),
	563	WPCM450_MKFUNC(hsp1),
	564	WPCM450_MKFUNC(hsp2),
	565	WPCM450_MKFUNC(r1err),
	566	WPCM450_MKFUNC(r1md),
	567	WPCM450_MKFUNC(rmii2),
	568	WPCM450_MKFUNC(r2err),
	569	WPCM450_MKFUNC(r2md),
	570	WPCM450_MKFUNC(kbcc),
	571	WPCM450_MKFUNC(clko),
	572	WPCM450_MKFUNC(smi),
	573	WPCM450_MKFUNC(uinc),
	574	WPCM450_MKFUNC(gspi),
	575	WPCM450_MKFUNC(mben),
	576	WPCM450_MKFUNC(xcs2),
	577	WPCM450_MKFUNC(xcs1),
	578	WPCM450_MKFUNC(sdio),
	579	WPCM450_MKFUNC(sspi),
	580	WPCM450_MKFUNC(fi0),
	581	WPCM450_MKFUNC(fi1),
	582	WPCM450_MKFUNC(fi2),
	583	WPCM450_MKFUNC(fi3),
	584	WPCM450_MKFUNC(fi4),
	585	WPCM450_MKFUNC(fi5),
	586	WPCM450_MKFUNC(fi6),
	587	WPCM450_MKFUNC(fi7),
	588	WPCM450_MKFUNC(fi8),
	589	WPCM450_MKFUNC(fi9),
	590	WPCM450_MKFUNC(fi10),
	591	WPCM450_MKFUNC(fi11),
	592	WPCM450_MKFUNC(fi12),
	593	WPCM450_MKFUNC(fi13),
	594	WPCM450_MKFUNC(fi14),
	595	WPCM450_MKFUNC(fi15),
	596	WPCM450_MKFUNC(pwm0),
	597	WPCM450_MKFUNC(pwm1),
	598	WPCM450_MKFUNC(pwm2),
	599	WPCM450_MKFUNC(pwm3),
	600	WPCM450_MKFUNC(pwm4),
	601	WPCM450_MKFUNC(pwm5),
	602	WPCM450_MKFUNC(pwm6),
	603	WPCM450_MKFUNC(pwm7),
	604	WPCM450_MKFUNC(hg0),
	605	WPCM450_MKFUNC(hg1),
	606	WPCM450_MKFUNC(hg2),
	607	WPCM450_MKFUNC(hg3),
	608	WPCM450_MKFUNC(hg4),
	609	WPCM450_MKFUNC(hg5),
	610	WPCM450_MKFUNC(hg6),
	611	WPCM450_MKFUNC(hg7),
	612	WPCM450_MKFUNC(gpio),
	613	};
	614
	615	#define WPCM450_PINCFG(a, b, c, d, e, f, g) \
	616	[a] = { .fn0 = fn_ ## b, .reg0 = WPCM450_GCR_ ## c, .bit0 = d, \
	617	.fn1 = fn_ ## e, .reg1 = WPCM450_GCR_ ## f, .bit1 = g }
	618
	619	struct wpcm450_pincfg {
	620	int fn0, reg0, bit0;
	621	int fn1, reg1, bit1;
	622	};
	623
	624	static const struct wpcm450_pincfg pincfg[] = {
	625	/* PIN FUNCTION 1 FUNCTION 2 */
	626	WPCM450_PINCFG(0, none, NONE, 0, none, NONE, 0),
	627	WPCM450_PINCFG(1, none, NONE, 0, none, NONE, 0),
	628	WPCM450_PINCFG(2, none, NONE, 0, none, NONE, 0),
	629	WPCM450_PINCFG(3, none, NONE, 0, none, NONE, 0),
	630	WPCM450_PINCFG(4, none, NONE, 0, none, NONE, 0),
	631	WPCM450_PINCFG(5, none, NONE, 0, none, NONE, 0),
	632	WPCM450_PINCFG(6, none, NONE, 0, none, NONE, 0),
	633	WPCM450_PINCFG(7, none, NONE, 0, sdio, MFSEL1, 30),
	634	WPCM450_PINCFG(8, none, NONE, 0, none, NONE, 0),
	635	WPCM450_PINCFG(9, none, NONE, 0, none, NONE, 0),
	636	WPCM450_PINCFG(10, none, NONE, 0, none, NONE, 0),
	637	WPCM450_PINCFG(11, none, NONE, 0, none, NONE, 0),
	638	WPCM450_PINCFG(12, gspi, MFSEL1, 24, sspi, MFSEL1, 31),
	639	WPCM450_PINCFG(13, gspi, MFSEL1, 24, sspi, MFSEL1, 31),
	640	WPCM450_PINCFG(14, gspi, MFSEL1, 24, sspi, MFSEL1, 31),
	641	WPCM450_PINCFG(15, gspi, MFSEL1, 24, sspi, MFSEL1, 31),
	642	WPCM450_PINCFG(16, none, NONE, 0, pwm6, MFSEL2, 22),
	643	WPCM450_PINCFG(17, none, NONE, 0, pwm7, MFSEL2, 23),
	644	WPCM450_PINCFG(18, none, NONE, 0, none, NONE, 0),
	645	WPCM450_PINCFG(19, uinc, MFSEL1, 23, none, NONE, 0),
	646	WPCM450_PINCFG(20, hg0, MFSEL2, 24, pwm4, MFSEL2, 20),
	647	WPCM450_PINCFG(21, hg1, MFSEL2, 25, pwm5, MFSEL2, 21),
	648	WPCM450_PINCFG(22, hg2, MFSEL2, 26, none, NONE, 0),
	649	WPCM450_PINCFG(23, hg3, MFSEL2, 27, none, NONE, 0),
	650	WPCM450_PINCFG(24, hg4, MFSEL2, 28, none, NONE, 0),
	651	WPCM450_PINCFG(25, hg5, MFSEL2, 29, none, NONE, 0),
	652	WPCM450_PINCFG(26, smb5, MFSEL1, 2, none, NONE, 0),
	653	WPCM450_PINCFG(27, smb5, MFSEL1, 2, none, NONE, 0),
	654	WPCM450_PINCFG(28, smb4, MFSEL1, 1, none, NONE, 0),
	655	WPCM450_PINCFG(29, smb4, MFSEL1, 1, none, NONE, 0),
	656	WPCM450_PINCFG(30, smb3, MFSEL1, 0, none, NONE, 0),
	657	WPCM450_PINCFG(31, smb3, MFSEL1, 0, none, NONE, 0),
	658
	659	WPCM450_PINCFG(32, scs1, MFSEL1, 3, none, NONE, 0),
	660	WPCM450_PINCFG(33, scs2, MFSEL1, 4, none, NONE, 0),
	661	WPCM450_PINCFG(34, scs3, MFSEL1, 5, none, NONE, 0),
	662	WPCM450_PINCFG(35, xcs1, MFSEL1, 29, none, NONE, 0),
	663	WPCM450_PINCFG(36, xcs2, MFSEL1, 28, none, NONE, 0),
	664	WPCM450_PINCFG(37, none, NONE, 0, none, NONE, 0), /* DVO */
	665	WPCM450_PINCFG(38, none, NONE, 0, none, NONE, 0), /* DVO */
	666	WPCM450_PINCFG(39, none, NONE, 0, none, NONE, 0), /* DVO */
	667	WPCM450_PINCFG(40, none, NONE, 0, none, NONE, 0), /* DVO */
	668	WPCM450_PINCFG(41, bsp, MFSEL1, 9, none, NONE, 0),
	669	WPCM450_PINCFG(42, bsp, MFSEL1, 9, none, NONE, 0),
	670	WPCM450_PINCFG(43, hsp1, MFSEL1, 10, sdio, MFSEL1, 30),
	671	WPCM450_PINCFG(44, hsp1, MFSEL1, 10, sdio, MFSEL1, 30),
	672	WPCM450_PINCFG(45, hsp1, MFSEL1, 10, sdio, MFSEL1, 30),
	673	WPCM450_PINCFG(46, hsp1, MFSEL1, 10, sdio, MFSEL1, 30),
	674	WPCM450_PINCFG(47, hsp1, MFSEL1, 10, sdio, MFSEL1, 30),
	675	WPCM450_PINCFG(48, hsp2, MFSEL1, 11, none, NONE, 0),
	676	WPCM450_PINCFG(49, hsp2, MFSEL1, 11, none, NONE, 0),
	677	WPCM450_PINCFG(50, hsp2, MFSEL1, 11, none, NONE, 0),
	678	WPCM450_PINCFG(51, hsp2, MFSEL1, 11, none, NONE, 0),
	679	WPCM450_PINCFG(52, hsp2, MFSEL1, 11, none, NONE, 0),
	680	WPCM450_PINCFG(53, hsp2, MFSEL1, 11, none, NONE, 0),
	681	WPCM450_PINCFG(54, hsp2, MFSEL1, 11, none, NONE, 0),
	682	WPCM450_PINCFG(55, hsp2, MFSEL1, 11, none, NONE, 0),
	683	WPCM450_PINCFG(56, r1err, MFSEL1, 12, none, NONE, 0),
	684	WPCM450_PINCFG(57, r1md, MFSEL1, 13, none, NONE, 0),
	685	WPCM450_PINCFG(58, r1md, MFSEL1, 13, none, NONE, 0),
	686	WPCM450_PINCFG(59, hg6, MFSEL2, 30, none, NONE, 0),
	687	WPCM450_PINCFG(60, hg7, MFSEL2, 31, sdio, MFSEL1, 30),
	688	WPCM450_PINCFG(61, hsp1, MFSEL1, 10, none, NONE, 0),
	689	WPCM450_PINCFG(62, hsp1, MFSEL1, 10, none, NONE, 0),
	690	WPCM450_PINCFG(63, hsp1, MFSEL1, 10, none, NONE, 0),
	691
	692	WPCM450_PINCFG(64, fi0, MFSEL2, 0, none, NONE, 0),
	693	WPCM450_PINCFG(65, fi1, MFSEL2, 1, none, NONE, 0),
	694	WPCM450_PINCFG(66, fi2, MFSEL2, 2, none, NONE, 0),
	695	WPCM450_PINCFG(67, fi3, MFSEL2, 3, none, NONE, 0),
	696	WPCM450_PINCFG(68, fi4, MFSEL2, 4, none, NONE, 0),
	697	WPCM450_PINCFG(69, fi5, MFSEL2, 5, none, NONE, 0),
	698	WPCM450_PINCFG(70, fi6, MFSEL2, 6, none, NONE, 0),
	699	WPCM450_PINCFG(71, fi7, MFSEL2, 7, none, NONE, 0),
	700	WPCM450_PINCFG(72, fi8, MFSEL2, 8, none, NONE, 0),
	701	WPCM450_PINCFG(73, fi9, MFSEL2, 9, none, NONE, 0),
	702	WPCM450_PINCFG(74, fi10, MFSEL2, 10, none, NONE, 0),
	703	WPCM450_PINCFG(75, fi11, MFSEL2, 11, none, NONE, 0),
	704	WPCM450_PINCFG(76, fi12, MFSEL2, 12, none, NONE, 0),
	705	WPCM450_PINCFG(77, fi13, MFSEL2, 13, none, NONE, 0),
	706	WPCM450_PINCFG(78, fi14, MFSEL2, 14, none, NONE, 0),
	707	WPCM450_PINCFG(79, fi15, MFSEL2, 15, none, NONE, 0),
	708	WPCM450_PINCFG(80, pwm0, MFSEL2, 16, none, NONE, 0),
	709	WPCM450_PINCFG(81, pwm1, MFSEL2, 17, none, NONE, 0),
	710	WPCM450_PINCFG(82, pwm2, MFSEL2, 18, none, NONE, 0),
	711	WPCM450_PINCFG(83, pwm3, MFSEL2, 19, none, NONE, 0),
	712	WPCM450_PINCFG(84, rmii2, MFSEL1, 14, none, NONE, 0),
	713	WPCM450_PINCFG(85, rmii2, MFSEL1, 14, none, NONE, 0),
	714	WPCM450_PINCFG(86, rmii2, MFSEL1, 14, none, NONE, 0),
	715	WPCM450_PINCFG(87, rmii2, MFSEL1, 14, none, NONE, 0),
	716	WPCM450_PINCFG(88, rmii2, MFSEL1, 14, none, NONE, 0),
	717	WPCM450_PINCFG(89, rmii2, MFSEL1, 14, none, NONE, 0),
	718	WPCM450_PINCFG(90, r2err, MFSEL1, 15, none, NONE, 0),
	719	WPCM450_PINCFG(91, r2md, MFSEL1, 16, none, NONE, 0),
	720	WPCM450_PINCFG(92, r2md, MFSEL1, 16, none, NONE, 0),
	721	WPCM450_PINCFG(93, kbcc, MFSEL1, 17, none, NONE, 0),
	722	WPCM450_PINCFG(94, kbcc, MFSEL1, 17, none, NONE, 0),
	723	WPCM450_PINCFG(95, none, NONE, 0, none, NONE, 0),
	724
	725	WPCM450_PINCFG(96, none, NONE, 0, none, NONE, 0),
	726	WPCM450_PINCFG(97, none, NONE, 0, none, NONE, 0),
	727	WPCM450_PINCFG(98, none, NONE, 0, none, NONE, 0),
	728	WPCM450_PINCFG(99, none, NONE, 0, none, NONE, 0),
	729	WPCM450_PINCFG(100, none, NONE, 0, none, NONE, 0),
	730	WPCM450_PINCFG(101, none, NONE, 0, none, NONE, 0),
	731	WPCM450_PINCFG(102, none, NONE, 0, none, NONE, 0),
	732	WPCM450_PINCFG(103, none, NONE, 0, none, NONE, 0),
	733	WPCM450_PINCFG(104, none, NONE, 0, none, NONE, 0),
	734	WPCM450_PINCFG(105, none, NONE, 0, none, NONE, 0),
	735	WPCM450_PINCFG(106, none, NONE, 0, none, NONE, 0),
	736	WPCM450_PINCFG(107, none, NONE, 0, none, NONE, 0),
	737	WPCM450_PINCFG(108, none, NONE, 0, none, NONE, 0), /* DVO */
	738	WPCM450_PINCFG(109, none, NONE, 0, none, NONE, 0), /* DVO */
	739	WPCM450_PINCFG(110, none, NONE, 0, none, NONE, 0), /* DVO */
	740	WPCM450_PINCFG(111, none, NONE, 0, none, NONE, 0), /* DVO */
	741	WPCM450_PINCFG(112, none, NONE, 0, none, NONE, 0), /* DVO */
	742	WPCM450_PINCFG(113, none, NONE, 0, none, NONE, 0), /* DVO */
	743	WPCM450_PINCFG(114, smb0, MFSEL1, 6, none, NONE, 0),
	744	WPCM450_PINCFG(115, smb0, MFSEL1, 6, none, NONE, 0),
	745	WPCM450_PINCFG(116, smb1, MFSEL1, 7, none, NONE, 0),
	746	WPCM450_PINCFG(117, smb1, MFSEL1, 7, none, NONE, 0),
	747	WPCM450_PINCFG(118, smb2, MFSEL1, 8, none, NONE, 0),
	748	WPCM450_PINCFG(119, smb2, MFSEL1, 8, none, NONE, 0),
	749	WPCM450_PINCFG(120, none, NONE, 0, none, NONE, 0), /* DVO */
	750	WPCM450_PINCFG(121, none, NONE, 0, none, NONE, 0), /* DVO */
	751	WPCM450_PINCFG(122, none, NONE, 0, none, NONE, 0), /* DVO */
	752	WPCM450_PINCFG(123, none, NONE, 0, none, NONE, 0), /* DVO */
	753	WPCM450_PINCFG(124, none, NONE, 0, none, NONE, 0), /* DVO */
	754	WPCM450_PINCFG(125, none, NONE, 0, none, NONE, 0), /* DVO */
	755	WPCM450_PINCFG(126, none, NONE, 0, none, NONE, 0), /* DVO */
	756	WPCM450_PINCFG(127, none, NONE, 0, none, NONE, 0), /* DVO */
	757	};
	758
	759	#define WPCM450_PIN(n) PINCTRL_PIN(n, "gpio" #n)
	760
	761	static const struct pinctrl_pin_desc wpcm450_pins[] = {
	762	WPCM450_PIN(0), WPCM450_PIN(1), WPCM450_PIN(2), WPCM450_PIN(3),
	763	WPCM450_PIN(4), WPCM450_PIN(5), WPCM450_PIN(6), WPCM450_PIN(7),
	764	WPCM450_PIN(8), WPCM450_PIN(9), WPCM450_PIN(10), WPCM450_PIN(11),
	765	WPCM450_PIN(12), WPCM450_PIN(13), WPCM450_PIN(14), WPCM450_PIN(15),
	766	WPCM450_PIN(16), WPCM450_PIN(17), WPCM450_PIN(18), WPCM450_PIN(19),
	767	WPCM450_PIN(20), WPCM450_PIN(21), WPCM450_PIN(22), WPCM450_PIN(23),
	768	WPCM450_PIN(24), WPCM450_PIN(25), WPCM450_PIN(26), WPCM450_PIN(27),
	769	WPCM450_PIN(28), WPCM450_PIN(29), WPCM450_PIN(30), WPCM450_PIN(31),
	770	WPCM450_PIN(32), WPCM450_PIN(33), WPCM450_PIN(34), WPCM450_PIN(35),
	771	WPCM450_PIN(36), WPCM450_PIN(37), WPCM450_PIN(38), WPCM450_PIN(39),
	772	WPCM450_PIN(40), WPCM450_PIN(41), WPCM450_PIN(42), WPCM450_PIN(43),
	773	WPCM450_PIN(44), WPCM450_PIN(45), WPCM450_PIN(46), WPCM450_PIN(47),
	774	WPCM450_PIN(48), WPCM450_PIN(49), WPCM450_PIN(50), WPCM450_PIN(51),
	775	WPCM450_PIN(52), WPCM450_PIN(53), WPCM450_PIN(54), WPCM450_PIN(55),
	776	WPCM450_PIN(56), WPCM450_PIN(57), WPCM450_PIN(58), WPCM450_PIN(59),
	777	WPCM450_PIN(60), WPCM450_PIN(61), WPCM450_PIN(62), WPCM450_PIN(63),
	778	WPCM450_PIN(64), WPCM450_PIN(65), WPCM450_PIN(66), WPCM450_PIN(67),
	779	WPCM450_PIN(68), WPCM450_PIN(69), WPCM450_PIN(70), WPCM450_PIN(71),
	780	WPCM450_PIN(72), WPCM450_PIN(73), WPCM450_PIN(74), WPCM450_PIN(75),
	781	WPCM450_PIN(76), WPCM450_PIN(77), WPCM450_PIN(78), WPCM450_PIN(79),
	782	WPCM450_PIN(80), WPCM450_PIN(81), WPCM450_PIN(82), WPCM450_PIN(83),
	783	WPCM450_PIN(84), WPCM450_PIN(85), WPCM450_PIN(86), WPCM450_PIN(87),
	784	WPCM450_PIN(88), WPCM450_PIN(89), WPCM450_PIN(90), WPCM450_PIN(91),
	785	WPCM450_PIN(92), WPCM450_PIN(93), WPCM450_PIN(94), WPCM450_PIN(95),
	786	WPCM450_PIN(96), WPCM450_PIN(97), WPCM450_PIN(98), WPCM450_PIN(99),
	787	WPCM450_PIN(100), WPCM450_PIN(101), WPCM450_PIN(102), WPCM450_PIN(103),
	788	WPCM450_PIN(104), WPCM450_PIN(105), WPCM450_PIN(106), WPCM450_PIN(107),
	789	WPCM450_PIN(108), WPCM450_PIN(109), WPCM450_PIN(110), WPCM450_PIN(111),
	790	WPCM450_PIN(112), WPCM450_PIN(113), WPCM450_PIN(114), WPCM450_PIN(115),
	791	WPCM450_PIN(116), WPCM450_PIN(117), WPCM450_PIN(118), WPCM450_PIN(119),
	792	WPCM450_PIN(120), WPCM450_PIN(121), WPCM450_PIN(122), WPCM450_PIN(123),
	793	WPCM450_PIN(124), WPCM450_PIN(125), WPCM450_PIN(126), WPCM450_PIN(127),
	794	};
	795
	796	/* Enable mode in pin group */
	797	static void wpcm450_setfunc(struct regmap gcr_regmap, const unsigned int pin,
	798	int npins, int func)
	799	{
	800	const struct wpcm450_pincfg *cfg;
	801	int i;
	802
	803	for (i = 0; i < npins; i++) {
	804	cfg = &pincfg[pin[i]];
	805	if (func == fn_gpio \|\| cfg->fn0 == func \|\| cfg->fn1 == func) {
	806	if (cfg->reg0)
	807	regmap_update_bits(gcr_regmap, cfg->reg0,
	808	BIT(cfg->bit0),
	809	(cfg->fn0 == func) ? BIT(cfg->bit0) : 0);
	810	if (cfg->reg1)
	811	regmap_update_bits(gcr_regmap, cfg->reg1,
	812	BIT(cfg->bit1),
	813	(cfg->fn1 == func) ? BIT(cfg->bit1) : 0);
	814	}
	815	}
	816	}
	817
	818	static int wpcm450_get_groups_count(struct pinctrl_dev *pctldev)
	819	{
	820	return ARRAY_SIZE(wpcm450_groups);
	821	}
	822
	823	static const char wpcm450_get_group_name(struct pinctrl_dev pctldev,
	824	unsigned int selector)
	825	{
	826	return wpcm450_groups[selector].name;
	827	}
	828
	829	static int wpcm450_get_group_pins(struct pinctrl_dev *pctldev,
	830	unsigned int selector,
	831	const unsigned int **pins,
	832	unsigned int *npins)
	833	{
	834	*npins = wpcm450_groups[selector].num_pins;
	835	*pins = wpcm450_groups[selector].pins;
	836
	837	return 0;
	838	}
	839
	840	static int wpcm450_dt_node_to_map(struct pinctrl_dev *pctldev,
	841	struct device_node *np_config,
	842	struct pinctrl_map **map,
	843	u32 *num_maps)
	844	{
	845	return pinconf_generic_dt_node_to_map(pctldev, np_config,
	846	map, num_maps,
	847	PIN_MAP_TYPE_INVALID);
	848	}
	849
	850	static void wpcm450_dt_free_map(struct pinctrl_dev *pctldev,
	851	struct pinctrl_map *map, u32 num_maps)
	852	{
	853	kfree(map);
	854	}
	855
	856	static const struct pinctrl_ops wpcm450_pinctrl_ops = {
	857	.get_groups_count = wpcm450_get_groups_count,
	858	.get_group_name = wpcm450_get_group_name,
	859	.get_group_pins = wpcm450_get_group_pins,
	860	.dt_node_to_map = wpcm450_dt_node_to_map,
	861	.dt_free_map = wpcm450_dt_free_map,
	862	};
	863
	864	static int wpcm450_get_functions_count(struct pinctrl_dev *pctldev)
	865	{
	866	return ARRAY_SIZE(wpcm450_funcs);
	867	}
	868
	869	static const char wpcm450_get_function_name(struct pinctrl_dev pctldev,
	870	unsigned int function)
	871	{
	872	return wpcm450_funcs[function].name;
	873	}
	874
	875	static int wpcm450_get_function_groups(struct pinctrl_dev *pctldev,
	876	unsigned int function,
	877	const char * const **groups,
	878	unsigned int * const ngroups)
	879	{
	880	*ngroups = wpcm450_funcs[function].ngroups;
	881	*groups = wpcm450_funcs[function].groups;
	882
	883	return 0;
	884	}
	885
	886	static int wpcm450_pinmux_set_mux(struct pinctrl_dev *pctldev,
	887	unsigned int function,
	888	unsigned int group)
	889	{
	890	struct wpcm450_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
	891
	892	wpcm450_setfunc(pctrl->gcr_regmap, wpcm450_groups[group].pins,
	893	wpcm450_groups[group].num_pins, function);
	894
	895	return 0;
	896	}
	897
	898	static const struct pinmux_ops wpcm450_pinmux_ops = {
	899	.get_functions_count = wpcm450_get_functions_count,
	900	.get_function_name = wpcm450_get_function_name,
	901	.get_function_groups = wpcm450_get_function_groups,
	902	.set_mux = wpcm450_pinmux_set_mux,
	903	};
	904
	905	static int debounce_bitnum(int gpio)
	906	{
	907	if (gpio >= 0 && gpio < 16)
	908	return gpio;
	909	return -EINVAL;
	910	}
	911
	912	static int wpcm450_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
	913	unsigned long *config)
	914	{
	915	struct wpcm450_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
	916	enum pin_config_param param = pinconf_to_config_param(*config);
	917	unsigned long flags;
	918	int bit;
	919	u32 reg;
	920
	921	switch (param) {
	922	case PIN_CONFIG_INPUT_DEBOUNCE:
	923	bit = debounce_bitnum(pin);
	924	if (bit < 0)
	925	return bit;
	926
	927	raw_spin_lock_irqsave(&pctrl->lock, flags);
	928	reg = ioread32(pctrl->gpio_base + WPCM450_GPEVDBNC);
	929	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
	930
	931	*config = pinconf_to_config_packed(param, !!(reg & BIT(bit)));
	932	return 0;
	933	default:
	934	return -ENOTSUPP;
	935	}
	936	}
	937
	938	static int wpcm450_config_set_one(struct wpcm450_pinctrl *pctrl,
	939	unsigned int pin, unsigned long config)
	940	{
	941	enum pin_config_param param = pinconf_to_config_param(config);
	942	unsigned long flags;
	943	unsigned long reg;
	944	int bit;
	945	int arg;
	946
	947	switch (param) {
	948	case PIN_CONFIG_INPUT_DEBOUNCE:
	949	bit = debounce_bitnum(pin);
	950	if (bit < 0)
	951	return bit;
	952
	953	arg = pinconf_to_config_argument(config);
	954
	955	raw_spin_lock_irqsave(&pctrl->lock, flags);
	956	reg = ioread32(pctrl->gpio_base + WPCM450_GPEVDBNC);
	957	__assign_bit(bit, &reg, arg);
	958	iowrite32(reg, pctrl->gpio_base + WPCM450_GPEVDBNC);
	959	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
	960	return 0;
	961	default:
	962	return -ENOTSUPP;
	963	}
	964	}
	965
	966	static int wpcm450_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
	967	unsigned long *configs, unsigned int num_configs)
	968	{
	969	struct wpcm450_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
	970	int ret;
	971
	972	while (num_configs--) {
	973	ret = wpcm450_config_set_one(pctrl, pin, *configs++);
	974	if (ret)
	975	return ret;
	976	}
	977
	978	return 0;
	979	}
	980
	981	static const struct pinconf_ops wpcm450_pinconf_ops = {
	982	.is_generic = true,
	983	.pin_config_get = wpcm450_config_get,
	984	.pin_config_set = wpcm450_config_set,
	985	};
	986
	987	static struct pinctrl_desc wpcm450_pinctrl_desc = {
	988	.name = "wpcm450-pinctrl",
	989	.pins = wpcm450_pins,
	990	.npins = ARRAY_SIZE(wpcm450_pins),
	991	.pctlops = &wpcm450_pinctrl_ops,
	992	.pmxops = &wpcm450_pinmux_ops,
	993	.confops = &wpcm450_pinconf_ops,
	994	.owner = THIS_MODULE,
	995	};
	996
	997	static int wpcm450_gpio_set_config(struct gpio_chip *chip,
	998	unsigned int offset, unsigned long config)
	999	{
	1000	struct wpcm450_gpio *gpio = gpiochip_get_data(chip);
	1001
	1002	return wpcm450_config_set_one(gpio->pctrl, offset, config);
	1003	}
	1004
	1005	static int wpcm450_gpio_add_pin_ranges(struct gpio_chip *chip)
	1006	{
	1007	struct wpcm450_gpio *gpio = gpiochip_get_data(chip);
	1008	const struct wpcm450_bank *bank = gpio->bank;
	1009
	1010	return gpiochip_add_pin_range(&gpio->gc, dev_name(gpio->pctrl->dev),
	1011	0, bank->base, bank->length);
	1012	}
	1013
	1014	static int wpcm450_gpio_register(struct platform_device *pdev,
	1015	struct wpcm450_pinctrl *pctrl)
	1016	{
	1017	struct device *dev = &pdev->dev;
	1018	struct fwnode_handle *child;
	1019	int ret;
	1020
	1021	pctrl->gpio_base = devm_platform_ioremap_resource(pdev, 0);
	1022	if (IS_ERR(pctrl->gpio_base))
	1023	return dev_err_probe(dev, PTR_ERR(pctrl->gpio_base),
	1024	"Resource fail for GPIO controller\n");
	1025
	1026	device_for_each_child_node(dev, child) {
	1027	void __iomem *dat = NULL;
	1028	void __iomem *set = NULL;
	1029	void __iomem *dirout = NULL;
	1030	unsigned long flags = 0;
	1031	const struct wpcm450_bank *bank;
	1032	struct wpcm450_gpio *gpio;
	1033	struct gpio_irq_chip *girq;
	1034	u32 reg;
	1035	int i;
	1036
	1037	if (!fwnode_property_read_bool(child, "gpio-controller"))
	1038	continue;
	1039
	1040	ret = fwnode_property_read_u32(child, "reg", &reg);
	1041	if (ret < 0)
	1042	return ret;
	1043
	1044	gpio = &pctrl->gpio_bank[reg];
	1045	gpio->pctrl = pctrl;
	1046
	1047	if (reg >= WPCM450_NUM_BANKS)
	1048	return dev_err_probe(dev, -EINVAL,
	1049	"GPIO index %d out of range!\n", reg);
	1050
	1051	bank = &wpcm450_banks[reg];
	1052	gpio->bank = bank;
	1053
	1054	dat = pctrl->gpio_base + bank->datain;
	1055	if (bank->dataout) {
	1056	set = pctrl->gpio_base + bank->dataout;
	1057	dirout = pctrl->gpio_base + bank->cfg0;
	1058	} else {
	1059	flags = BGPIOF_NO_OUTPUT;
	1060	}
	1061	ret = bgpio_init(&gpio->gc, dev, 4,
	1062	dat, set, NULL, dirout, NULL, flags);
	1063	if (ret < 0)
	1064	return dev_err_probe(dev, ret, "GPIO initialization failed\n");
	1065
	1066	gpio->gc.ngpio = bank->length;
	1067	gpio->gc.set_config = wpcm450_gpio_set_config;
	1068	gpio->gc.fwnode = child;
	1069	gpio->gc.add_pin_ranges = wpcm450_gpio_add_pin_ranges;
	1070
	1071	gpio->irqc = wpcm450_gpio_irqchip;
	1072	girq = &gpio->gc.irq;
	1073	girq->chip = &gpio->irqc;
	1074	girq->parent_handler = wpcm450_gpio_irqhandler;
	1075	girq->parents = devm_kcalloc(dev, WPCM450_NUM_GPIO_IRQS,
	1076	sizeof(*girq->parents), GFP_KERNEL);
	1077	if (!girq->parents)
	1078	return -ENOMEM;
	1079	girq->default_type = IRQ_TYPE_NONE;
	1080	girq->handler = handle_bad_irq;
	1081
	1082	girq->num_parents = 0;
	1083	for (i = 0; i < WPCM450_NUM_GPIO_IRQS; i++) {
	1084	int irq = fwnode_irq_get(child, i);
	1085
	1086	if (irq < 0)
	1087	break;
	1088
	1089	girq->parents[i] = irq;
	1090	girq->num_parents++;
	1091	}
	1092
	1093	ret = devm_gpiochip_add_data(dev, &gpio->gc, gpio);
	1094	if (ret)
	1095	return dev_err_probe(dev, ret, "Failed to add GPIO chip\n");
	1096	}
	1097
	1098	return 0;
	1099	}
	1100
	1101	static int wpcm450_pinctrl_probe(struct platform_device *pdev)
	1102	{
	1103	struct device *dev = &pdev->dev;
	1104	struct wpcm450_pinctrl *pctrl;
	1105	int ret;
	1106
	1107	pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
	1108	if (!pctrl)
	1109	return -ENOMEM;
	1110
	1111	pctrl->dev = &pdev->dev;
	1112	raw_spin_lock_init(&pctrl->lock);
	1113	dev_set_drvdata(dev, pctrl);
	1114
	1115	pctrl->gcr_regmap =
	1116	syscon_regmap_lookup_by_compatible("nuvoton,wpcm450-gcr");
	1117	if (IS_ERR(pctrl->gcr_regmap))
	1118	return dev_err_probe(dev, PTR_ERR(pctrl->gcr_regmap),
	1119	"Failed to find nuvoton,wpcm450-gcr\n");
	1120
	1121	pctrl->pctldev = devm_pinctrl_register(dev,
	1122	&wpcm450_pinctrl_desc, pctrl);
	1123	if (IS_ERR(pctrl->pctldev))
	1124	return dev_err_probe(dev, PTR_ERR(pctrl->pctldev),
	1125	"Failed to register pinctrl device\n");
	1126
	1127	ret = wpcm450_gpio_register(pdev, pctrl);
	1128	if (ret < 0)
	1129	return ret;
	1130
	1131	return 0;
	1132	}
	1133
	1134	static const struct of_device_id wpcm450_pinctrl_match[] = {
	1135	{ .compatible = "nuvoton,wpcm450-pinctrl" },
	1136	{ }
	1137	};
	1138	MODULE_DEVICE_TABLE(of, wpcm450_pinctrl_match);
	1139
	1140	static struct platform_driver wpcm450_pinctrl_driver = {
	1141	.probe = wpcm450_pinctrl_probe,
	1142	.driver = {
	1143	.name = "wpcm450-pinctrl",
	1144	.of_match_table = wpcm450_pinctrl_match,
	1145	},
	1146	};
	1147	module_platform_driver(wpcm450_pinctrl_driver);
	1148
	1149	MODULE_LICENSE("GPL v2");
	1150	MODULE_AUTHOR("Jonathan Neuschäfer <j.neuschaefer@gmx.net>");
	1151	MODULE_DESCRIPTION("Nuvoton WPCM450 Pinctrl and GPIO driver");

drivers/pinctrl/pinconf-generic.c+3−3

@@ -30,10 +30,10 @@ static const struct pin_config_item conf_items[] = { · 29 unmodified lines
30	PCONFDUMP(PIN_CONFIG_BIAS_BUS_HOLD, "input bias bus hold", NULL, false),	30	PCONFDUMP(PIN_CONFIG_BIAS_BUS_HOLD, "input bias bus hold", NULL, false),
31	PCONFDUMP(PIN_CONFIG_BIAS_DISABLE, "input bias disabled", NULL, false),	31	PCONFDUMP(PIN_CONFIG_BIAS_DISABLE, "input bias disabled", NULL, false),
32	PCONFDUMP(PIN_CONFIG_BIAS_HIGH_IMPEDANCE, "input bias high impedance", NULL, false),	32	PCONFDUMP(PIN_CONFIG_BIAS_HIGH_IMPEDANCE, "input bias high impedance", NULL, false),
33	PCONFDUMP(PIN_CONFIG_BIAS_PULL_DOWN, "input bias pull down", NULL, false),	33	PCONFDUMP(PIN_CONFIG_BIAS_PULL_DOWN, "input bias pull down", "ohms", true),
34	PCONFDUMP(PIN_CONFIG_BIAS_PULL_PIN_DEFAULT,	34	PCONFDUMP(PIN_CONFIG_BIAS_PULL_PIN_DEFAULT,
35	"input bias pull to pin specific state", NULL, false),	35	"input bias pull to pin specific state", "ohms", true),
36	PCONFDUMP(PIN_CONFIG_BIAS_PULL_UP, "input bias pull up", NULL, false),	36	PCONFDUMP(PIN_CONFIG_BIAS_PULL_UP, "input bias pull up", "ohms", true),
37	PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_DRAIN, "output drive open drain", NULL, false),	37	PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_DRAIN, "output drive open drain", NULL, false),
38	PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_SOURCE, "output drive open source", NULL, false),	38	PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_SOURCE, "output drive open source", NULL, false),
39	PCONFDUMP(PIN_CONFIG_DRIVE_PUSH_PULL, "output drive push pull", NULL, false),	39	PCONFDUMP(PIN_CONFIG_DRIVE_PUSH_PULL, "output drive push pull", NULL, false),

drivers/pinctrl/pinctrl-at91-pio4.c+7−9

 	const char **group_names;
 	const struct of_device_id *match;
 	int i, ret;
-	struct resource	*res;
 	struct atmel_pioctrl *atmel_pioctrl;
 	const struct atmel_pioctrl_data *atmel_pioctrl_data;
 	/* There is one controller but each bank has its own irq line. */
 	for (i = 0; i < atmel_pioctrl->nbanks; i++) {
-		res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
+		ret = platform_get_irq(pdev, i);
-		if (!res) {
+		if (ret < 0) {
-			dev_err(dev, "missing irq resource for group %c\n",
+			dev_dbg(dev, "missing irq resource for group %c\n",
 				'A' + i);
-			return -EINVAL;
+			return ret;
 		}
-		atmel_pioctrl->irqs[i] = res->start;
+		atmel_pioctrl->irqs[i] = ret;
-		irq_set_chained_handler_and_data(res->start,
+		irq_set_chained_handler_and_data(ret, atmel_gpio_irq_handler, atmel_pioctrl);
-			atmel_gpio_irq_handler, atmel_pioctrl);
+		dev_dbg(dev, "bank %i: irq=%d\n", i, ret);
-		dev_dbg(dev, "bank %i: irq=%pr\n", i, res);
 	}
 	atmel_pioctrl->irq_domain = irq_domain_add_linear(dev->of_node,

drivers/pinctrl/pinctrl-ingenic.c+45−1

 	unsigned int num_functions;
 	const u32 *pull_ups, *pull_downs;
+	const struct regmap_access_table *access_table;
 };
 struct ingenic_pinctrl {
 	{ "mac", x1000_mac_groups, ARRAY_SIZE(x1000_mac_groups), },
 };
+static const struct regmap_range x1000_access_ranges[] = {
+	regmap_reg_range(0x000, 0x400 - 4),
+	regmap_reg_range(0x700, 0x800 - 4),
+};
+/* shared with X1500 */
+static const struct regmap_access_table x1000_access_table = {
+	.yes_ranges = x1000_access_ranges,
+	.n_yes_ranges = ARRAY_SIZE(x1000_access_ranges),
+};
 static const struct ingenic_chip_info x1000_chip_info = {
 	.num_chips = 4,
 	.reg_offset = 0x100,
 	.num_functions = ARRAY_SIZE(x1000_functions),
 	.pull_ups = x1000_pull_ups,
 	.pull_downs = x1000_pull_downs,
+	.access_table = &x1000_access_table,
 };
 static int x1500_uart0_data_pins[] = { 0x4a, 0x4b, };
 	.num_functions = ARRAY_SIZE(x1500_functions),
 	.pull_ups = x1000_pull_ups,
 	.pull_downs = x1000_pull_downs,
+	.access_table = &x1000_access_table,
 };
 static const u32 x1830_pull_ups[4] = {
 	{ "mac", x1830_mac_groups, ARRAY_SIZE(x1830_mac_groups), },
 };
+static const struct regmap_range x1830_access_ranges[] = {
+	regmap_reg_range(0x0000, 0x4000 - 4),
+	regmap_reg_range(0x7000, 0x8000 - 4),
+};
+static const struct regmap_access_table x1830_access_table = {
+	.yes_ranges = x1830_access_ranges,
+	.n_yes_ranges = ARRAY_SIZE(x1830_access_ranges),
+};
 static const struct ingenic_chip_info x1830_chip_info = {
 	.num_chips = 4,
 	.reg_offset = 0x1000,
 	.num_functions = ARRAY_SIZE(x1830_functions),
 	.pull_ups = x1830_pull_ups,
 	.pull_downs = x1830_pull_downs,
+	.access_table = &x1830_access_table,
 };
 static const u32 x2000_pull_ups[5] = {
 	{ "otg", x2000_otg_groups, ARRAY_SIZE(x2000_otg_groups), },
 };
+static const struct regmap_range x2000_access_ranges[] = {
+	regmap_reg_range(0x000, 0x500 - 4),
+	regmap_reg_range(0x700, 0x800 - 4),
+};
+/* shared with X2100 */
+static const struct regmap_access_table x2000_access_table = {
+	.yes_ranges = x2000_access_ranges,
+	.n_yes_ranges = ARRAY_SIZE(x2000_access_ranges),
+};
 static const struct ingenic_chip_info x2000_chip_info = {
 	.num_chips = 5,
 	.reg_offset = 0x100,
 	.num_functions = ARRAY_SIZE(x2000_functions),
 	.pull_ups = x2000_pull_ups,
 	.pull_downs = x2000_pull_downs,
+	.access_table = &x2000_access_table,
 };
 static const u32 x2100_pull_ups[5] = {
 	.num_functions = ARRAY_SIZE(x2100_functions),
 	.pull_ups = x2100_pull_ups,
 	.pull_downs = x2100_pull_downs,
+	.access_table = &x2000_access_table,
 };
 static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg)
 		return PTR_ERR(base);
 	regmap_config = ingenic_pinctrl_regmap_config;
-	regmap_config.max_register = chip_info->num_chips * chip_info->reg_offset;
+	if (chip_info->access_table) {
+		regmap_config.rd_table = chip_info->access_table;
+		regmap_config.wr_table = chip_info->access_table;
+	} else {
+		regmap_config.max_register = chip_info->num_chips * chip_info->reg_offset - 4;
+	}
 	jzpc->map = devm_regmap_init_mmio(dev, base, &regmap_config);
 	if (IS_ERR(jzpc->map)) {

drivers/pinctrl/pinctrl-microchip-sgpio.c+97−15

@@ -19,6 +19,7 @@ · 18 unmodified lines
19	#include <linux/property.h>	19	#include <linux/property.h>
20	#include <linux/regmap.h>	20	#include <linux/regmap.h>
21	#include <linux/reset.h>	21	#include <linux/reset.h>
		22	#include <linux/spinlock.h>
22		23
23	#include "core.h"	24	#include "core.h"
24	#include "pinconf.h"	25	#include "pinconf.h"
@@ -63,11 +64,13 @@ struct sgpio_properties { · 38 unmodified lines
63	#define SGPIO_LUTON_BIT_SOURCE GENMASK(11, 0)	64	#define SGPIO_LUTON_BIT_SOURCE GENMASK(11, 0)
64		65
65	#define SGPIO_OCELOT_AUTO_REPEAT BIT(10)	66	#define SGPIO_OCELOT_AUTO_REPEAT BIT(10)
		67	#define SGPIO_OCELOT_SINGLE_SHOT BIT(11)
66	#define SGPIO_OCELOT_PORT_WIDTH GENMASK(8, 7)	68	#define SGPIO_OCELOT_PORT_WIDTH GENMASK(8, 7)
67	#define SGPIO_OCELOT_CLK_FREQ GENMASK(19, 8)	69	#define SGPIO_OCELOT_CLK_FREQ GENMASK(19, 8)
68	#define SGPIO_OCELOT_BIT_SOURCE GENMASK(23, 12)	70	#define SGPIO_OCELOT_BIT_SOURCE GENMASK(23, 12)
69		71
70	#define SGPIO_SPARX5_AUTO_REPEAT BIT(6)	72	#define SGPIO_SPARX5_AUTO_REPEAT BIT(6)
		73	#define SGPIO_SPARX5_SINGLE_SHOT BIT(7)
71	#define SGPIO_SPARX5_PORT_WIDTH GENMASK(4, 3)	74	#define SGPIO_SPARX5_PORT_WIDTH GENMASK(4, 3)
72	#define SGPIO_SPARX5_CLK_FREQ GENMASK(19, 8)	75	#define SGPIO_SPARX5_CLK_FREQ GENMASK(19, 8)
73	#define SGPIO_SPARX5_BIT_SOURCE GENMASK(23, 12)	76	#define SGPIO_SPARX5_BIT_SOURCE GENMASK(23, 12)
@@ -116,6 +119,9 @@ struct sgpio_priv { · 42 unmodified lines
116	u32 clock;	119	u32 clock;
117	struct regmap *regs;	120	struct regmap *regs;
118	const struct sgpio_properties *properties;	121	const struct sgpio_properties *properties;
		122	spinlock_t lock;
		123	/* protects the config register and single shot mode */
		124	struct mutex poll_lock;
119	};	125	};
120		126
121	struct sgpio_port_addr {	127	struct sgpio_port_addr {
@@ -166,12 +172,11 @@ static void sgpio_writel(struct sgpio_priv *priv, · 44 unmodified lines
166	static inline void sgpio_clrsetbits(struct sgpio_priv *priv,	172	static inline void sgpio_clrsetbits(struct sgpio_priv *priv,
167	u32 rno, u32 off, u32 clear, u32 set)	173	u32 rno, u32 off, u32 clear, u32 set)
168	{	174	{
169	u32 val = sgpio_readl(priv, rno, off);	175	u32 addr = sgpio_get_addr(priv, rno, off);
170		176	int ret;
171	val &= ~clear;
172	val \|= set;
173		177
174	sgpio_writel(priv, val, rno, off);	178	ret = regmap_update_bits(priv->regs, addr, clear \| set, set);
		179	WARN_ONCE(ret, "error updating sgpio reg %d\n", ret);
175	}	180	}
176		181
177	static inline void sgpio_configure_bitstream(struct sgpio_priv *priv)	182	static inline void sgpio_configure_bitstream(struct sgpio_priv *priv)
@@ -224,12 +229,64 @@ static inline void sgpio_configure_clock(struct sgpio_priv *priv, u32 clkfrq) · 46 unmodified lines
224	sgpio_clrsetbits(priv, REG_SIO_CLOCK, 0, clr, set);	229	sgpio_clrsetbits(priv, REG_SIO_CLOCK, 0, clr, set);
225	}	230	}
226		231
227	static void sgpio_output_set(struct sgpio_priv *priv,	232	static int sgpio_single_shot(struct sgpio_priv *priv)
228	struct sgpio_port_addr *addr,	233	{
229	int value)	234	u32 addr = sgpio_get_addr(priv, REG_SIO_CONFIG, 0);
		235	int ret, ret2;
		236	u32 ctrl;
		237	unsigned int single_shot;
		238	unsigned int auto_repeat;
		239
		240	switch (priv->properties->arch) {
		241	case SGPIO_ARCH_LUTON:
		242	/* not supported for now */
		243	return 0;
		244	case SGPIO_ARCH_OCELOT:
		245	single_shot = SGPIO_OCELOT_SINGLE_SHOT;
		246	auto_repeat = SGPIO_OCELOT_AUTO_REPEAT;
		247	break;
		248	case SGPIO_ARCH_SPARX5:
		249	single_shot = SGPIO_SPARX5_SINGLE_SHOT;
		250	auto_repeat = SGPIO_SPARX5_AUTO_REPEAT;
		251	break;
		252	default:
		253	return -EINVAL;
		254	}
		255
		256	/*
		257	* Trigger immediate burst. This only works when auto repeat is turned
		258	* off. Otherwise, the single shot bit will never be cleared by the
		259	* hardware. Measurements showed that an update might take as long as
		260	* the burst gap. On a LAN9668 this is about 50ms for the largest
		261	* setting.
		262	* After the manual burst, reenable the auto repeat mode again.
		263	*/
		264	mutex_lock(&priv->poll_lock);
		265	ret = regmap_update_bits(priv->regs, addr, single_shot \| auto_repeat,
		266	single_shot);
		267	if (ret)
		268	goto out;
		269
		270	ret = regmap_read_poll_timeout(priv->regs, addr, ctrl,
		271	!(ctrl & single_shot), 100, 60000);
		272
		273	/* reenable auto repeat mode even if there was an error */
		274	ret2 = regmap_update_bits(priv->regs, addr, auto_repeat, auto_repeat);
		275	out:
		276	mutex_unlock(&priv->poll_lock);
		277
		278	return ret ?: ret2;
		279	}
		280
		281	static int sgpio_output_set(struct sgpio_priv *priv,
		282	struct sgpio_port_addr *addr,
		283	int value)
230	{	284	{
231	unsigned int bit = SGPIO_SRC_BITS * addr->bit;	285	unsigned int bit = SGPIO_SRC_BITS * addr->bit;
		286	u32 reg = sgpio_get_addr(priv, REG_PORT_CONFIG, addr->port);
		287	bool changed;
232	u32 clr, set;	288	u32 clr, set;
		289	int ret;
233		290
234	switch (priv->properties->arch) {	291	switch (priv->properties->arch) {
235	case SGPIO_ARCH_LUTON:	292	case SGPIO_ARCH_LUTON:
@@ -245,9 +302,21 @@ static void sgpio_output_set(struct sgpio_priv *priv, · 9 unmodified lines
245	set = FIELD_PREP(SGPIO_SPARX5_BIT_SOURCE, value << bit);	302	set = FIELD_PREP(SGPIO_SPARX5_BIT_SOURCE, value << bit);
246	break;	303	break;
247	default:	304	default:
248	return;	305	return -EINVAL;
249	}	306	}
250	sgpio_clrsetbits(priv, REG_PORT_CONFIG, addr->port, clr, set);	307
		308	ret = regmap_update_bits_check(priv->regs, reg, clr \| set, set,
		309	&changed);
		310	if (ret)
		311	return ret;
		312
		313	if (changed) {
		314	ret = sgpio_single_shot(priv);
		315	if (ret)
		316	return ret;
		317	}
		318
		319	return 0;
251	}	320	}
252		321
253	static int sgpio_output_get(struct sgpio_priv *priv,	322	static int sgpio_output_get(struct sgpio_priv *priv,
@@ -333,7 +402,7 @@ static int sgpio_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, · 79 unmodified lines
333	case PIN_CONFIG_OUTPUT:	402	case PIN_CONFIG_OUTPUT:
334	if (bank->is_input)	403	if (bank->is_input)
335	return -EINVAL;	404	return -EINVAL;
336	sgpio_output_set(priv, &addr, arg);	405	err = sgpio_output_set(priv, &addr, arg);
337	break;	406	break;
338		407
339	default:	408	default:
@@ -473,9 +542,7 @@ static int microchip_sgpio_direction_output(struct gpio_chip *gc, · 133 unmodified lines
473		542
474	sgpio_pin_to_addr(priv, gpio, &addr);	543	sgpio_pin_to_addr(priv, gpio, &addr);
475		544
476	sgpio_output_set(priv, &addr, value);	545	return sgpio_output_set(priv, &addr, value);
477
478	return 0;
479	}	546	}
480		547
481	static int microchip_sgpio_get_direction(struct gpio_chip *gc, unsigned int gpio)	548	static int microchip_sgpio_get_direction(struct gpio_chip *gc, unsigned int gpio)
@@ -575,10 +642,13 @@ static void microchip_sgpio_irq_settype(struct irq_data *data, · 93 unmodified lines
575	struct sgpio_bank *bank = gpiochip_get_data(chip);	642	struct sgpio_bank *bank = gpiochip_get_data(chip);
576	unsigned int gpio = irqd_to_hwirq(data);	643	unsigned int gpio = irqd_to_hwirq(data);
577	struct sgpio_port_addr addr;	644	struct sgpio_port_addr addr;
		645	unsigned long flags;
578	u32 ena;	646	u32 ena;
579		647
580	sgpio_pin_to_addr(bank->priv, gpio, &addr);	648	sgpio_pin_to_addr(bank->priv, gpio, &addr);
581		649
		650	spin_lock_irqsave(&bank->priv->lock, flags);
		651
582	/* Disable interrupt while changing type */	652	/* Disable interrupt while changing type */
583	ena = sgpio_readl(bank->priv, REG_INT_ENABLE, addr.bit);	653	ena = sgpio_readl(bank->priv, REG_INT_ENABLE, addr.bit);
584	sgpio_writel(bank->priv, ena & ~BIT(addr.port), REG_INT_ENABLE, addr.bit);	654	sgpio_writel(bank->priv, ena & ~BIT(addr.port), REG_INT_ENABLE, addr.bit);
@@ -595,6 +665,8 @@ static void microchip_sgpio_irq_settype(struct irq_data *data, · 10 unmodified lines
595		665
596	/* Possibly re-enable interrupts */	666	/* Possibly re-enable interrupts */
597	sgpio_writel(bank->priv, ena, REG_INT_ENABLE, addr.bit);	667	sgpio_writel(bank->priv, ena, REG_INT_ENABLE, addr.bit);
		668
		669	spin_unlock_irqrestore(&bank->priv->lock, flags);
598	}	670	}
599		671
600	static void microchip_sgpio_irq_setreg(struct irq_data *data,	672	static void microchip_sgpio_irq_setreg(struct irq_data *data,
@@ -626,7 +698,14 @@ static void microchip_sgpio_irq_unmask(struct irq_data *data) · 25 unmodified lines
626		698
627	static void microchip_sgpio_irq_ack(struct irq_data *data)	699	static void microchip_sgpio_irq_ack(struct irq_data *data)
628	{	700	{
629	microchip_sgpio_irq_setreg(data, REG_INT_ACK, false);	701	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
		702	struct sgpio_bank *bank = gpiochip_get_data(chip);
		703	unsigned int gpio = irqd_to_hwirq(data);
		704	struct sgpio_port_addr addr;
		705
		706	sgpio_pin_to_addr(bank->priv, gpio, &addr);
		707
		708	sgpio_writel(bank->priv, BIT(addr.port), REG_INT_ACK, addr.bit);
630	}	709	}
631		710
632	static int microchip_sgpio_irq_set_type(struct irq_data *data, unsigned int type)	711	static int microchip_sgpio_irq_set_type(struct irq_data *data, unsigned int type)
@@ -774,6 +853,7 @@ static int microchip_sgpio_register_bank(struct device *dev, · 141 unmodified lines
774	gc->of_gpio_n_cells = 3;	853	gc->of_gpio_n_cells = 3;
775	gc->base = -1;	854	gc->base = -1;
776	gc->ngpio = ngpios;	855	gc->ngpio = ngpios;
		856	gc->can_sleep = !bank->is_input;
777		857
778	if (bank->is_input && priv->properties->flags & SGPIO_FLAGS_HAS_IRQ) {	858	if (bank->is_input && priv->properties->flags & SGPIO_FLAGS_HAS_IRQ) {
779	int irq = fwnode_irq_get(fwnode, 0);	859	int irq = fwnode_irq_get(fwnode, 0);
@@ -833,6 +913,8 @@ static int microchip_sgpio_probe(struct platform_device *pdev) · 53 unmodified lines
833	return -ENOMEM;	913	return -ENOMEM;
834		914
835	priv->dev = dev;	915	priv->dev = dev;
		916	spin_lock_init(&priv->lock);
		917	mutex_init(&priv->poll_lock);
836		918
837	reset = devm_reset_control_get_optional_shared(&pdev->dev, "switch");	919	reset = devm_reset_control_get_optional_shared(&pdev->dev, "switch");
838	if (IS_ERR(reset))	920	if (IS_ERR(reset))

drivers/pinctrl/pinctrl-ocelot.c+106−3

@@ -695,6 +695,98 @@ static const struct pinctrl_pin_desc jaguar2_pins[] = { · 694 unmodified lines
695	JAGUAR2_PIN(63),	695	JAGUAR2_PIN(63),
696	};	696	};
697		697
		698	#define SERVALT_P(p, f0, f1, f2) \
		699	static struct ocelot_pin_caps servalt_pin_##p = { \
		700	.pin = p, \
		701	.functions = { \
		702	FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2 \
		703	}, \
		704	}
		705
		706	SERVALT_P(0, SG0, NONE, NONE);
		707	SERVALT_P(1, SG0, NONE, NONE);
		708	SERVALT_P(2, SG0, NONE, NONE);
		709	SERVALT_P(3, SG0, NONE, NONE);
		710	SERVALT_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M);
		711	SERVALT_P(5, IRQ1_IN, IRQ1_OUT, TWI_SCL_M);
		712	SERVALT_P(6, UART, NONE, NONE);
		713	SERVALT_P(7, UART, NONE, NONE);
		714	SERVALT_P(8, SI, SFP, TWI_SCL_M);
		715	SERVALT_P(9, PCI_WAKE, SFP, SI);
		716	SERVALT_P(10, PTP0, SFP, TWI_SCL_M);
		717	SERVALT_P(11, PTP1, SFP, TWI_SCL_M);
		718	SERVALT_P(12, REF_CLK, SFP, TWI_SCL_M);
		719	SERVALT_P(13, REF_CLK, SFP, TWI_SCL_M);
		720	SERVALT_P(14, REF_CLK, IRQ0_OUT, SI);
		721	SERVALT_P(15, REF_CLK, IRQ1_OUT, SI);
		722	SERVALT_P(16, TACHO, SFP, SI);
		723	SERVALT_P(17, PWM, NONE, TWI_SCL_M);
		724	SERVALT_P(18, PTP2, SFP, SI);
		725	SERVALT_P(19, PTP3, SFP, SI);
		726	SERVALT_P(20, UART2, SFP, SI);
		727	SERVALT_P(21, UART2, NONE, NONE);
		728	SERVALT_P(22, MIIM, SFP, TWI2);
		729	SERVALT_P(23, MIIM, SFP, TWI2);
		730	SERVALT_P(24, TWI, NONE, NONE);
		731	SERVALT_P(25, TWI, SFP, TWI_SCL_M);
		732	SERVALT_P(26, TWI_SCL_M, SFP, SI);
		733	SERVALT_P(27, TWI_SCL_M, SFP, SI);
		734	SERVALT_P(28, TWI_SCL_M, SFP, SI);
		735	SERVALT_P(29, TWI_SCL_M, NONE, NONE);
		736	SERVALT_P(30, TWI_SCL_M, NONE, NONE);
		737	SERVALT_P(31, TWI_SCL_M, NONE, NONE);
		738	SERVALT_P(32, TWI_SCL_M, NONE, NONE);
		739	SERVALT_P(33, RCVRD_CLK, NONE, NONE);
		740	SERVALT_P(34, RCVRD_CLK, NONE, NONE);
		741	SERVALT_P(35, RCVRD_CLK, NONE, NONE);
		742	SERVALT_P(36, RCVRD_CLK, NONE, NONE);
		743
		744	#define SERVALT_PIN(n) { \
		745	.number = n, \
		746	.name = "GPIO_"#n, \
		747	.drv_data = &servalt_pin_##n \
		748	}
		749
		750	static const struct pinctrl_pin_desc servalt_pins[] = {
		751	SERVALT_PIN(0),
		752	SERVALT_PIN(1),
		753	SERVALT_PIN(2),
		754	SERVALT_PIN(3),
		755	SERVALT_PIN(4),
		756	SERVALT_PIN(5),
		757	SERVALT_PIN(6),
		758	SERVALT_PIN(7),
		759	SERVALT_PIN(8),
		760	SERVALT_PIN(9),
		761	SERVALT_PIN(10),
		762	SERVALT_PIN(11),
		763	SERVALT_PIN(12),
		764	SERVALT_PIN(13),
		765	SERVALT_PIN(14),
		766	SERVALT_PIN(15),
		767	SERVALT_PIN(16),
		768	SERVALT_PIN(17),
		769	SERVALT_PIN(18),
		770	SERVALT_PIN(19),
		771	SERVALT_PIN(20),
		772	SERVALT_PIN(21),
		773	SERVALT_PIN(22),
		774	SERVALT_PIN(23),
		775	SERVALT_PIN(24),
		776	SERVALT_PIN(25),
		777	SERVALT_PIN(26),
		778	SERVALT_PIN(27),
		779	SERVALT_PIN(28),
		780	SERVALT_PIN(29),
		781	SERVALT_PIN(30),
		782	SERVALT_PIN(31),
		783	SERVALT_PIN(32),
		784	SERVALT_PIN(33),
		785	SERVALT_PIN(34),
		786	SERVALT_PIN(35),
		787	SERVALT_PIN(36),
		788	};
		789
698	#define SPARX5_P(p, f0, f1, f2) \	790	#define SPARX5_P(p, f0, f1, f2) \
699	static struct ocelot_pin_caps sparx5_pin_##p = { \	791	static struct ocelot_pin_caps sparx5_pin_##p = { \
700	.pin = p, \	792	.pin = p, \
@@ -1497,6 +1589,15 @@ static struct pinctrl_desc jaguar2_desc = { · 796 unmodified lines
1497	.owner = THIS_MODULE,	1589	.owner = THIS_MODULE,
1498	};	1590	};
1499		1591
		1592	static struct pinctrl_desc servalt_desc = {
		1593	.name = "servalt-pinctrl",
		1594	.pins = servalt_pins,
		1595	.npins = ARRAY_SIZE(servalt_pins),
		1596	.pctlops = &ocelot_pctl_ops,
		1597	.pmxops = &ocelot_pmx_ops,
		1598	.owner = THIS_MODULE,
		1599	};
		1600
1500	static struct pinctrl_desc sparx5_desc = {	1601	static struct pinctrl_desc sparx5_desc = {
1501	.name = "sparx5-pinctrl",	1602	.name = "sparx5-pinctrl",
1502	.pins = sparx5_pins,	1603	.pins = sparx5_pins,
@@ -1750,8 +1851,8 @@ static int ocelot_gpiochip_register(struct platform_device *pdev, · 247 unmodified lines
1750	gc->base = -1;	1851	gc->base = -1;
1751	gc->label = "ocelot-gpio";	1852	gc->label = "ocelot-gpio";
1752		1853
1753	irq = irq_of_parse_and_map(gc->of_node, 0);	1854	irq = platform_get_irq_optional(pdev, 0);
1754	if (irq) {	1855	if (irq > 0) {
1755	girq = &gc->irq;	1856	girq = &gc->irq;
1756	girq->chip = &ocelot_irqchip;	1857	girq->chip = &ocelot_irqchip;
1757	girq->parent_handler = ocelot_irq_handler;	1858	girq->parent_handler = ocelot_irq_handler;
@@ -1774,6 +1875,7 @@ static const struct of_device_id ocelot_pinctrl_of_match[] = { · 16 unmodified lines
1774	{ .compatible = "mscc,serval-pinctrl", .data = &serval_desc },	1875	{ .compatible = "mscc,serval-pinctrl", .data = &serval_desc },
1775	{ .compatible = "mscc,ocelot-pinctrl", .data = &ocelot_desc },	1876	{ .compatible = "mscc,ocelot-pinctrl", .data = &ocelot_desc },
1776	{ .compatible = "mscc,jaguar2-pinctrl", .data = &jaguar2_desc },	1877	{ .compatible = "mscc,jaguar2-pinctrl", .data = &jaguar2_desc },
		1878	{ .compatible = "mscc,servalt-pinctrl", .data = &servalt_desc },
1777	{ .compatible = "microchip,sparx5-pinctrl", .data = &sparx5_desc },	1879	{ .compatible = "microchip,sparx5-pinctrl", .data = &sparx5_desc },
1778	{ .compatible = "microchip,lan966x-pinctrl", .data = &lan966x_desc },	1880	{ .compatible = "microchip,lan966x-pinctrl", .data = &lan966x_desc },
1779	{},	1881	{},
@@ -1788,9 +1890,10 @@ static struct regmap ocelot_pinctrl_create_pincfg(struct platform_device pdev) · 8 unmodified lines
1788	.val_bits = 32,	1890	.val_bits = 32,
1789	.reg_stride = 4,	1891	.reg_stride = 4,
1790	.max_register = 32,	1892	.max_register = 32,
		1893	.name = "pincfg",
1791	};	1894	};
1792		1895
1793	base = devm_platform_ioremap_resource(pdev, 0);	1896	base = devm_platform_ioremap_resource(pdev, 1);
1794	if (IS_ERR(base)) {	1897	if (IS_ERR(base)) {
1795	dev_dbg(&pdev->dev, "Failed to ioremap config registers (no extended pinconf)\n");	1898	dev_dbg(&pdev->dev, "Failed to ioremap config registers (no extended pinconf)\n");
1796	return NULL;	1899	return NULL;

drivers/pinctrl/pinctrl-rockchip.c+2−0

 	node = of_parse_phandle(np, "rockchip,grf", 0);
 	if (node) {
 		info->regmap_base = syscon_node_to_regmap(node);
+		of_node_put(node);
 		if (IS_ERR(info->regmap_base))
 			return PTR_ERR(info->regmap_base);
 	} else {
 	node = of_parse_phandle(np, "rockchip,pmu", 0);
 	if (node) {
 		info->regmap_pmu = syscon_node_to_regmap(node);
+		of_node_put(node);
 		if (IS_ERR(info->regmap_pmu))
 			return PTR_ERR(info->regmap_pmu);
 	}

drivers/pinctrl/pinctrl-starfive.c+1−1

@@ -1026,7 +1026,7 @@ static int starfive_gpio_set_config(struct gpio_chip *gc, unsigned int gpio, · 1025 unmodified lines
1026	break;	1026	break;
1027	default:	1027	default:
1028	return -ENOTSUPP;	1028	return -ENOTSUPP;
1029	};	1029	}
1030		1030
1031	starfive_padctl_rmw(sfp, starfive_gpio_to_pin(sfp, gpio), mask, value);	1031	starfive_padctl_rmw(sfp, starfive_gpio_to_pin(sfp, gpio), mask, value);
1032	return 0;	1032	return 0;

drivers/pinctrl/pinctrl-zynq.c+2−5

  */
 #include <linux/io.h>
 #include <linux/mfd/syscon.h>
+#include <linux/module.h>
 #include <linux/init.h>
 #include <linux/of.h>
 #include <linux/platform_device.h>
 	.probe = zynq_pinctrl_probe,
 };
-static int __init zynq_pinctrl_init(void)
+module_platform_driver(zynq_pinctrl_driver);
-{
-	return platform_driver_register(&zynq_pinctrl_driver);
-}
-arch_initcall(zynq_pinctrl_init);

drivers/pinctrl/pxa/pinctrl-pxa27x.c+2−3

 static int pxa27x_pinctrl_probe(struct platform_device *pdev)
 {
-	int ret, i;
+	int i;
 	void __iomem *base_af[8];
 	void __iomem *base_dir[4];
 	void __iomem *base_sleep[4];
 	for (i = 0; i < ARRAY_SIZE(base_sleep); i++)
 		base_sleep[i] = base_sleep[0] + sizeof(base_af[0]) * i;
-	ret = pxa2xx_pinctrl_init(pdev, pxa27x_pins, ARRAY_SIZE(pxa27x_pins),
+	return pxa2xx_pinctrl_init(pdev, pxa27x_pins, ARRAY_SIZE(pxa27x_pins),
 				  base_af, base_dir, base_sleep);
-	return ret;
 }
 static const struct of_device_id pxa27x_pinctrl_match[] = {

drivers/pinctrl/qcom/Kconfig+9−0

@@ -248,6 +248,15 @@ config PINCTRL_SC8180X · 247 unmodified lines
248	Qualcomm Technologies Inc TLMM block found on the Qualcomm	248	Qualcomm Technologies Inc TLMM block found on the Qualcomm
249	Technologies Inc SC8180x platform.	249	Technologies Inc SC8180x platform.
250		250
		251	config PINCTRL_SC8280XP
		252	tristate "Qualcomm Technologies Inc SC8280xp pin controller driver"
		253	depends on OF
		254	depends on PINCTRL_MSM
		255	help
		256	This is the pinctrl, pinmux, pinconf and gpiolib driver for the
		257	Qualcomm Technologies Inc TLMM block found on the Qualcomm
		258	Technologies Inc SC8280xp platform.
		259
251	config PINCTRL_SDM660	260	config PINCTRL_SDM660
252	tristate "Qualcomm Technologies Inc SDM660 pin controller driver"	261	tristate "Qualcomm Technologies Inc SDM660 pin controller driver"
253	depends on OF	262	depends on OF

drivers/pinctrl/qcom/Makefile+1−0

@@ -29,6 +29,7 @@ obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-mpp.o · 28 unmodified lines
29	obj-$(CONFIG_PINCTRL_SC7180) += pinctrl-sc7180.o	29	obj-$(CONFIG_PINCTRL_SC7180) += pinctrl-sc7180.o
30	obj-$(CONFIG_PINCTRL_SC7280) += pinctrl-sc7280.o	30	obj-$(CONFIG_PINCTRL_SC7280) += pinctrl-sc7280.o
31	obj-$(CONFIG_PINCTRL_SC8180X) += pinctrl-sc8180x.o	31	obj-$(CONFIG_PINCTRL_SC8180X) += pinctrl-sc8180x.o
		32	obj-$(CONFIG_PINCTRL_SC8280XP) += pinctrl-sc8280xp.o
32	obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o	33	obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o
33	obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o	34	obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o
34	obj-$(CONFIG_PINCTRL_SDX55) += pinctrl-sdx55.o	35	obj-$(CONFIG_PINCTRL_SDX55) += pinctrl-sdx55.o

drivers/pinctrl/qcom/pinctrl-msm.c+11−2

 	int drive;
 	int pull;
 	int val;
+	int egpio_enable;
 	u32 ctl_reg, io_reg;
 	static const char * const pulls_keeper[] = {
 	func = (ctl_reg >> g->mux_bit) & 7;
 	drive = (ctl_reg >> g->drv_bit) & 7;
 	pull = (ctl_reg >> g->pull_bit) & 3;
+	egpio_enable = 0;
+	if (pctrl->soc->egpio_func && ctl_reg & BIT(g->egpio_present))
+		egpio_enable = !(ctl_reg & BIT(g->egpio_enable));
 	if (is_out)
 		val = !!(io_reg & BIT(g->out_bit));
 	else
 		val = !!(io_reg & BIT(g->in_bit));
+	if (egpio_enable) {
+		seq_printf(s, " %-8s: egpio\n", g->name);
+		return;
+	}
 	seq_printf(s, " %-8s: %-3s", g->name, is_out ? "out" : "in");
 	seq_printf(s, " %-4s func%d", val ? "high" : "low", func);
 	seq_printf(s, " %dmA", msm_regval_to_drive(drive));
 	if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))
 		return irq_chip_set_affinity_parent(d, dest, force);
-	return 0;
+	return -EINVAL;
 }
 static int msm_gpio_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
 	if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))
 		return irq_chip_set_vcpu_affinity_parent(d, vcpu_info);
-	return 0;
+	return -EINVAL;
 }
 static void msm_gpio_irq_handler(struct irq_desc *desc)

drivers/pinctrl/qcom/pinctrl-qcm2290.c+12−0

 	[133] = SDC_QDSD_PINGROUP(sdc2_data, 0x86000, 9, 0),
 };
+static const struct msm_gpio_wakeirq_map qcm2290_mpm_map[] = {
+	{ 0, 84 }, { 3, 75 }, { 4, 16 }, { 6, 59 }, { 8, 63 }, { 11, 17 },
+	{ 13, 18 }, { 14, 51 }, { 17, 20 }, { 18, 52 }, { 19, 53 }, { 24, 6 },
+	{ 25, 71 }, { 27, 73 }, { 28, 41 }, { 31, 27 }, { 32, 54 }, { 33, 55 },
+	{ 34, 56 }, { 35, 57 }, { 36, 58 }, { 39, 28 }, { 46, 29 }, { 62, 60 },
+	{ 63, 61 }, { 64, 62 }, { 69, 33 }, { 70, 34 }, { 72, 72 }, { 75, 35 },
+	{ 79, 36 }, { 80, 21 }, { 81, 38 }, { 86, 19 }, { 87, 42 }, { 88, 43 },
+	{ 89, 45 }, { 91, 74 }, { 94, 47 }, { 95, 48 }, { 96, 49 }, { 97, 50 },
+};
 static const struct msm_pinctrl_soc_data qcm2290_pinctrl = {
 	.pins = qcm2290_pins,
 	.npins = ARRAY_SIZE(qcm2290_pins),
 	.groups = qcm2290_groups,
 	.ngroups = ARRAY_SIZE(qcm2290_groups),
 	.ngpios = 127,
+	.wakeirq_map = qcm2290_mpm_map,
+	.nwakeirq_map = ARRAY_SIZE(qcm2290_mpm_map),
 };
 static int qcm2290_pinctrl_probe(struct platform_device *pdev)

drivers/pinctrl/qcom/pinctrl-sc8180x.c+2−2

@@ -1622,8 +1622,8 @@ static const struct msm_pinctrl_soc_data sc8180x_acpi_pinctrl = { · 1621 unmodified lines
1622	};	1622	};
1623		1623
1624	/*	1624	/*
1625	* ACPI DSDT has one single memory resource for TLMM, which voilates the	1625	* ACPI DSDT has one single memory resource for TLMM, which violates the
1626	* hardware layout of 3 sepearte tiles. Let's split the memory resource into	1626	* hardware layout of 3 separate tiles. Let's split the memory resource into
1627	* 3 named ones, so that msm_pinctrl_probe() can map memory for ACPI in the	1627	* 3 named ones, so that msm_pinctrl_probe() can map memory for ACPI in the
1628	* same way as for DT probe.	1628	* same way as for DT probe.
1629	*/	1629	*/

drivers/pinctrl/qcom/pinctrl-sc8280xp.c+1953−0

@@ -0,0 +1,1953 @@
	1	// SPDX-License-Identifier: GPL-2.0-only
	2	/*
	3	* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
	4	* Copyright (c) 2022, Linaro Ltd.
	5	*/
	6
	7	#include <linux/module.h>
	8	#include <linux/of.h>
	9	#include <linux/platform_device.h>
	10	#include <linux/pinctrl/pinctrl.h>
	11
	12	#include "pinctrl-msm.h"
	13
	14	#define FUNCTION(fname) \
	15	[msm_mux_##fname] = { \
	16	.name = #fname, \
	17	.groups = fname##_groups, \
	18	.ngroups = ARRAY_SIZE(fname##_groups), \
	19	}
	20
	21	#define REG_SIZE 0x1000
	22	#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7) \
	23	{ \
	24	.name = "gpio" #id, \
	25	.pins = gpio##id##_pins, \
	26	.npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \
	27	.funcs = (int[]){ \
	28	msm_mux_gpio, /* gpio mode */ \
	29	msm_mux_##f1, \
	30	msm_mux_##f2, \
	31	msm_mux_##f3, \
	32	msm_mux_##f4, \
	33	msm_mux_##f5, \
	34	msm_mux_##f6, \
	35	msm_mux_##f7, \
	36	}, \
	37	.nfuncs = 8, \
	38	.ctl_reg = REG_SIZE * id, \
	39	.io_reg = 0x4 + REG_SIZE * id, \
	40	.intr_cfg_reg = 0x8 + REG_SIZE * id, \
	41	.intr_status_reg = 0xc + REG_SIZE * id, \
	42	.intr_target_reg = 0x8 + REG_SIZE * id, \
	43	.mux_bit = 2, \
	44	.pull_bit = 0, \
	45	.drv_bit = 6, \
	46	.oe_bit = 9, \
	47	.in_bit = 0, \
	48	.out_bit = 1, \
	49	.egpio_enable = 12, \
	50	.egpio_present = 11, \
	51	.intr_enable_bit = 0, \
	52	.intr_status_bit = 0, \
	53	.intr_target_bit = 5, \
	54	.intr_target_kpss_val = 3, \
	55	.intr_raw_status_bit = 4, \
	56	.intr_polarity_bit = 1, \
	57	.intr_detection_bit = 2, \
	58	.intr_detection_width = 2, \
	59	}
	60
	61	#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
	62	{ \
	63	.name = #pg_name, \
	64	.pins = pg_name##_pins, \
	65	.npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
	66	.ctl_reg = ctl, \
	67	.io_reg = 0, \
	68	.intr_cfg_reg = 0, \
	69	.intr_status_reg = 0, \
	70	.intr_target_reg = 0, \
	71	.mux_bit = -1, \
	72	.pull_bit = pull, \
	73	.drv_bit = drv, \
	74	.oe_bit = -1, \
	75	.in_bit = -1, \
	76	.out_bit = -1, \
	77	.intr_enable_bit = -1, \
	78	.intr_status_bit = -1, \
	79	.intr_target_bit = -1, \
	80	.intr_raw_status_bit = -1, \
	81	.intr_polarity_bit = -1, \
	82	.intr_detection_bit = -1, \
	83	.intr_detection_width = -1, \
	84	}
	85
	86	#define UFS_RESET(pg_name, offset) \
	87	{ \
	88	.name = #pg_name, \
	89	.pins = pg_name##_pins, \
	90	.npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
	91	.ctl_reg = offset, \
	92	.io_reg = offset + 0x4, \
	93	.intr_cfg_reg = 0, \
	94	.intr_status_reg = 0, \
	95	.intr_target_reg = 0, \
	96	.mux_bit = -1, \
	97	.pull_bit = 3, \
	98	.drv_bit = 0, \
	99	.oe_bit = -1, \
	100	.in_bit = -1, \
	101	.out_bit = 0, \
	102	.intr_enable_bit = -1, \
	103	.intr_status_bit = -1, \
	104	.intr_target_bit = -1, \
	105	.intr_raw_status_bit = -1, \
	106	.intr_polarity_bit = -1, \
	107	.intr_detection_bit = -1, \
	108	.intr_detection_width = -1, \
	109	}
	110	static const struct pinctrl_pin_desc sc8280xp_pins[] = {
	111	PINCTRL_PIN(0, "GPIO_0"),
	112	PINCTRL_PIN(1, "GPIO_1"),
	113	PINCTRL_PIN(2, "GPIO_2"),
	114	PINCTRL_PIN(3, "GPIO_3"),
	115	PINCTRL_PIN(4, "GPIO_4"),
	116	PINCTRL_PIN(5, "GPIO_5"),
	117	PINCTRL_PIN(6, "GPIO_6"),
	118	PINCTRL_PIN(7, "GPIO_7"),
	119	PINCTRL_PIN(8, "GPIO_8"),
	120	PINCTRL_PIN(9, "GPIO_9"),
	121	PINCTRL_PIN(10, "GPIO_10"),
	122	PINCTRL_PIN(11, "GPIO_11"),
	123	PINCTRL_PIN(12, "GPIO_12"),
	124	PINCTRL_PIN(13, "GPIO_13"),
	125	PINCTRL_PIN(14, "GPIO_14"),
	126	PINCTRL_PIN(15, "GPIO_15"),
	127	PINCTRL_PIN(16, "GPIO_16"),
	128	PINCTRL_PIN(17, "GPIO_17"),
	129	PINCTRL_PIN(18, "GPIO_18"),
	130	PINCTRL_PIN(19, "GPIO_19"),
	131	PINCTRL_PIN(20, "GPIO_20"),
	132	PINCTRL_PIN(21, "GPIO_21"),
	133	PINCTRL_PIN(22, "GPIO_22"),
	134	PINCTRL_PIN(23, "GPIO_23"),
	135	PINCTRL_PIN(24, "GPIO_24"),
	136	PINCTRL_PIN(25, "GPIO_25"),
	137	PINCTRL_PIN(26, "GPIO_26"),
	138	PINCTRL_PIN(27, "GPIO_27"),
	139	PINCTRL_PIN(28, "GPIO_28"),
	140	PINCTRL_PIN(29, "GPIO_29"),
	141	PINCTRL_PIN(30, "GPIO_30"),
	142	PINCTRL_PIN(31, "GPIO_31"),
	143	PINCTRL_PIN(32, "GPIO_32"),
	144	PINCTRL_PIN(33, "GPIO_33"),
	145	PINCTRL_PIN(34, "GPIO_34"),
	146	PINCTRL_PIN(35, "GPIO_35"),
	147	PINCTRL_PIN(36, "GPIO_36"),
	148	PINCTRL_PIN(37, "GPIO_37"),
	149	PINCTRL_PIN(38, "GPIO_38"),
	150	PINCTRL_PIN(39, "GPIO_39"),
	151	PINCTRL_PIN(40, "GPIO_40"),
	152	PINCTRL_PIN(41, "GPIO_41"),
	153	PINCTRL_PIN(42, "GPIO_42"),
	154	PINCTRL_PIN(43, "GPIO_43"),
	155	PINCTRL_PIN(44, "GPIO_44"),
	156	PINCTRL_PIN(45, "GPIO_45"),
	157	PINCTRL_PIN(46, "GPIO_46"),
	158	PINCTRL_PIN(47, "GPIO_47"),
	159	PINCTRL_PIN(48, "GPIO_48"),
	160	PINCTRL_PIN(49, "GPIO_49"),
	161	PINCTRL_PIN(50, "GPIO_50"),
	162	PINCTRL_PIN(51, "GPIO_51"),
	163	PINCTRL_PIN(52, "GPIO_52"),
	164	PINCTRL_PIN(53, "GPIO_53"),
	165	PINCTRL_PIN(54, "GPIO_54"),
	166	PINCTRL_PIN(55, "GPIO_55"),
	167	PINCTRL_PIN(56, "GPIO_56"),
	168	PINCTRL_PIN(57, "GPIO_57"),
	169	PINCTRL_PIN(58, "GPIO_58"),
	170	PINCTRL_PIN(59, "GPIO_59"),
	171	PINCTRL_PIN(60, "GPIO_60"),
	172	PINCTRL_PIN(61, "GPIO_61"),
	173	PINCTRL_PIN(62, "GPIO_62"),
	174	PINCTRL_PIN(63, "GPIO_63"),
	175	PINCTRL_PIN(64, "GPIO_64"),
	176	PINCTRL_PIN(65, "GPIO_65"),
	177	PINCTRL_PIN(66, "GPIO_66"),
	178	PINCTRL_PIN(67, "GPIO_67"),
	179	PINCTRL_PIN(68, "GPIO_68"),
	180	PINCTRL_PIN(69, "GPIO_69"),
	181	PINCTRL_PIN(70, "GPIO_70"),
	182	PINCTRL_PIN(71, "GPIO_71"),
	183	PINCTRL_PIN(72, "GPIO_72"),
	184	PINCTRL_PIN(73, "GPIO_73"),
	185	PINCTRL_PIN(74, "GPIO_74"),
	186	PINCTRL_PIN(75, "GPIO_75"),
	187	PINCTRL_PIN(76, "GPIO_76"),
	188	PINCTRL_PIN(77, "GPIO_77"),
	189	PINCTRL_PIN(78, "GPIO_78"),
	190	PINCTRL_PIN(79, "GPIO_79"),
	191	PINCTRL_PIN(80, "GPIO_80"),
	192	PINCTRL_PIN(81, "GPIO_81"),
	193	PINCTRL_PIN(82, "GPIO_82"),
	194	PINCTRL_PIN(83, "GPIO_83"),
	195	PINCTRL_PIN(84, "GPIO_84"),
	196	PINCTRL_PIN(85, "GPIO_85"),
	197	PINCTRL_PIN(86, "GPIO_86"),
	198	PINCTRL_PIN(87, "GPIO_87"),
	199	PINCTRL_PIN(88, "GPIO_88"),
	200	PINCTRL_PIN(89, "GPIO_89"),
	201	PINCTRL_PIN(90, "GPIO_90"),
	202	PINCTRL_PIN(91, "GPIO_91"),
	203	PINCTRL_PIN(92, "GPIO_92"),
	204	PINCTRL_PIN(93, "GPIO_93"),
	205	PINCTRL_PIN(94, "GPIO_94"),
	206	PINCTRL_PIN(95, "GPIO_95"),
	207	PINCTRL_PIN(96, "GPIO_96"),
	208	PINCTRL_PIN(97, "GPIO_97"),
	209	PINCTRL_PIN(98, "GPIO_98"),
	210	PINCTRL_PIN(99, "GPIO_99"),
	211	PINCTRL_PIN(100, "GPIO_100"),
	212	PINCTRL_PIN(101, "GPIO_101"),
	213	PINCTRL_PIN(102, "GPIO_102"),
	214	PINCTRL_PIN(103, "GPIO_103"),
	215	PINCTRL_PIN(104, "GPIO_104"),
	216	PINCTRL_PIN(105, "GPIO_105"),
	217	PINCTRL_PIN(106, "GPIO_106"),
	218	PINCTRL_PIN(107, "GPIO_107"),
	219	PINCTRL_PIN(108, "GPIO_108"),
	220	PINCTRL_PIN(109, "GPIO_109"),
	221	PINCTRL_PIN(110, "GPIO_110"),
	222	PINCTRL_PIN(111, "GPIO_111"),
	223	PINCTRL_PIN(112, "GPIO_112"),
	224	PINCTRL_PIN(113, "GPIO_113"),
	225	PINCTRL_PIN(114, "GPIO_114"),
	226	PINCTRL_PIN(115, "GPIO_115"),
	227	PINCTRL_PIN(116, "GPIO_116"),
	228	PINCTRL_PIN(117, "GPIO_117"),
	229	PINCTRL_PIN(118, "GPIO_118"),
	230	PINCTRL_PIN(119, "GPIO_119"),
	231	PINCTRL_PIN(120, "GPIO_120"),
	232	PINCTRL_PIN(121, "GPIO_121"),
	233	PINCTRL_PIN(122, "GPIO_122"),
	234	PINCTRL_PIN(123, "GPIO_123"),
	235	PINCTRL_PIN(124, "GPIO_124"),
	236	PINCTRL_PIN(125, "GPIO_125"),
	237	PINCTRL_PIN(126, "GPIO_126"),
	238	PINCTRL_PIN(127, "GPIO_127"),
	239	PINCTRL_PIN(128, "GPIO_128"),
	240	PINCTRL_PIN(129, "GPIO_129"),
	241	PINCTRL_PIN(130, "GPIO_130"),
	242	PINCTRL_PIN(131, "GPIO_131"),
	243	PINCTRL_PIN(132, "GPIO_132"),
	244	PINCTRL_PIN(133, "GPIO_133"),
	245	PINCTRL_PIN(134, "GPIO_134"),
	246	PINCTRL_PIN(135, "GPIO_135"),
	247	PINCTRL_PIN(136, "GPIO_136"),
	248	PINCTRL_PIN(137, "GPIO_137"),
	249	PINCTRL_PIN(138, "GPIO_138"),
	250	PINCTRL_PIN(139, "GPIO_139"),
	251	PINCTRL_PIN(140, "GPIO_140"),
	252	PINCTRL_PIN(141, "GPIO_141"),
	253	PINCTRL_PIN(142, "GPIO_142"),
	254	PINCTRL_PIN(143, "GPIO_143"),
	255	PINCTRL_PIN(144, "GPIO_144"),
	256	PINCTRL_PIN(145, "GPIO_145"),
	257	PINCTRL_PIN(146, "GPIO_146"),
	258	PINCTRL_PIN(147, "GPIO_147"),
	259	PINCTRL_PIN(148, "GPIO_148"),
	260	PINCTRL_PIN(149, "GPIO_149"),
	261	PINCTRL_PIN(150, "GPIO_150"),
	262	PINCTRL_PIN(151, "GPIO_151"),
	263	PINCTRL_PIN(152, "GPIO_152"),
	264	PINCTRL_PIN(153, "GPIO_153"),
	265	PINCTRL_PIN(154, "GPIO_154"),
	266	PINCTRL_PIN(155, "GPIO_155"),
	267	PINCTRL_PIN(156, "GPIO_156"),
	268	PINCTRL_PIN(157, "GPIO_157"),
	269	PINCTRL_PIN(158, "GPIO_158"),
	270	PINCTRL_PIN(159, "GPIO_159"),
	271	PINCTRL_PIN(160, "GPIO_160"),
	272	PINCTRL_PIN(161, "GPIO_161"),
	273	PINCTRL_PIN(162, "GPIO_162"),
	274	PINCTRL_PIN(163, "GPIO_163"),
	275	PINCTRL_PIN(164, "GPIO_164"),
	276	PINCTRL_PIN(165, "GPIO_165"),
	277	PINCTRL_PIN(166, "GPIO_166"),
	278	PINCTRL_PIN(167, "GPIO_167"),
	279	PINCTRL_PIN(168, "GPIO_168"),
	280	PINCTRL_PIN(169, "GPIO_169"),
	281	PINCTRL_PIN(170, "GPIO_170"),
	282	PINCTRL_PIN(171, "GPIO_171"),
	283	PINCTRL_PIN(172, "GPIO_172"),
	284	PINCTRL_PIN(173, "GPIO_173"),
	285	PINCTRL_PIN(174, "GPIO_174"),
	286	PINCTRL_PIN(175, "GPIO_175"),
	287	PINCTRL_PIN(176, "GPIO_176"),
	288	PINCTRL_PIN(177, "GPIO_177"),
	289	PINCTRL_PIN(178, "GPIO_178"),
	290	PINCTRL_PIN(179, "GPIO_179"),
	291	PINCTRL_PIN(180, "GPIO_180"),
	292	PINCTRL_PIN(181, "GPIO_181"),
	293	PINCTRL_PIN(182, "GPIO_182"),
	294	PINCTRL_PIN(183, "GPIO_183"),
	295	PINCTRL_PIN(184, "GPIO_184"),
	296	PINCTRL_PIN(185, "GPIO_185"),
	297	PINCTRL_PIN(186, "GPIO_186"),
	298	PINCTRL_PIN(187, "GPIO_187"),
	299	PINCTRL_PIN(188, "GPIO_188"),
	300	PINCTRL_PIN(189, "GPIO_189"),
	301	PINCTRL_PIN(190, "GPIO_190"),
	302	PINCTRL_PIN(191, "GPIO_191"),
	303	PINCTRL_PIN(192, "GPIO_192"),
	304	PINCTRL_PIN(193, "GPIO_193"),
	305	PINCTRL_PIN(194, "GPIO_194"),
	306	PINCTRL_PIN(195, "GPIO_195"),
	307	PINCTRL_PIN(196, "GPIO_196"),
	308	PINCTRL_PIN(197, "GPIO_197"),
	309	PINCTRL_PIN(198, "GPIO_198"),
	310	PINCTRL_PIN(199, "GPIO_199"),
	311	PINCTRL_PIN(200, "GPIO_200"),
	312	PINCTRL_PIN(201, "GPIO_201"),
	313	PINCTRL_PIN(202, "GPIO_202"),
	314	PINCTRL_PIN(203, "GPIO_203"),
	315	PINCTRL_PIN(204, "GPIO_204"),
	316	PINCTRL_PIN(205, "GPIO_205"),
	317	PINCTRL_PIN(206, "GPIO_206"),
	318	PINCTRL_PIN(207, "GPIO_207"),
	319	PINCTRL_PIN(208, "GPIO_208"),
	320	PINCTRL_PIN(209, "GPIO_209"),
	321	PINCTRL_PIN(210, "GPIO_210"),
	322	PINCTRL_PIN(211, "GPIO_211"),
	323	PINCTRL_PIN(212, "GPIO_212"),
	324	PINCTRL_PIN(213, "GPIO_213"),
	325	PINCTRL_PIN(214, "GPIO_214"),
	326	PINCTRL_PIN(215, "GPIO_215"),
	327	PINCTRL_PIN(216, "GPIO_216"),
	328	PINCTRL_PIN(217, "GPIO_217"),
	329	PINCTRL_PIN(218, "GPIO_218"),
	330	PINCTRL_PIN(219, "GPIO_219"),
	331	PINCTRL_PIN(220, "GPIO_220"),
	332	PINCTRL_PIN(221, "GPIO_221"),
	333	PINCTRL_PIN(222, "GPIO_222"),
	334	PINCTRL_PIN(223, "GPIO_223"),
	335	PINCTRL_PIN(224, "GPIO_224"),
	336	PINCTRL_PIN(225, "GPIO_225"),
	337	PINCTRL_PIN(226, "GPIO_226"),
	338	PINCTRL_PIN(227, "GPIO_227"),
	339	PINCTRL_PIN(228, "UFS_RESET"),
	340	PINCTRL_PIN(229, "UFS1_RESET"),
	341	PINCTRL_PIN(230, "SDC2_CLK"),
	342	PINCTRL_PIN(231, "SDC2_CMD"),
	343	PINCTRL_PIN(232, "SDC2_DATA"),
	344	};
	345
	346	#define DECLARE_MSM_GPIO_PINS(pin) \
	347	static const unsigned int gpio##pin##_pins[] = { pin }
	348	DECLARE_MSM_GPIO_PINS(0);
	349	DECLARE_MSM_GPIO_PINS(1);
	350	DECLARE_MSM_GPIO_PINS(2);
	351	DECLARE_MSM_GPIO_PINS(3);
	352	DECLARE_MSM_GPIO_PINS(4);
	353	DECLARE_MSM_GPIO_PINS(5);
	354	DECLARE_MSM_GPIO_PINS(6);
	355	DECLARE_MSM_GPIO_PINS(7);
	356	DECLARE_MSM_GPIO_PINS(8);
	357	DECLARE_MSM_GPIO_PINS(9);
	358	DECLARE_MSM_GPIO_PINS(10);
	359	DECLARE_MSM_GPIO_PINS(11);
	360	DECLARE_MSM_GPIO_PINS(12);
	361	DECLARE_MSM_GPIO_PINS(13);
	362	DECLARE_MSM_GPIO_PINS(14);
	363	DECLARE_MSM_GPIO_PINS(15);
	364	DECLARE_MSM_GPIO_PINS(16);
	365	DECLARE_MSM_GPIO_PINS(17);
	366	DECLARE_MSM_GPIO_PINS(18);
	367	DECLARE_MSM_GPIO_PINS(19);
	368	DECLARE_MSM_GPIO_PINS(20);
	369	DECLARE_MSM_GPIO_PINS(21);
	370	DECLARE_MSM_GPIO_PINS(22);
	371	DECLARE_MSM_GPIO_PINS(23);
	372	DECLARE_MSM_GPIO_PINS(24);
	373	DECLARE_MSM_GPIO_PINS(25);
	374	DECLARE_MSM_GPIO_PINS(26);
	375	DECLARE_MSM_GPIO_PINS(27);
	376	DECLARE_MSM_GPIO_PINS(28);
	377	DECLARE_MSM_GPIO_PINS(29);
	378	DECLARE_MSM_GPIO_PINS(30);
	379	DECLARE_MSM_GPIO_PINS(31);
	380	DECLARE_MSM_GPIO_PINS(32);
	381	DECLARE_MSM_GPIO_PINS(33);
	382	DECLARE_MSM_GPIO_PINS(34);
	383	DECLARE_MSM_GPIO_PINS(35);
	384	DECLARE_MSM_GPIO_PINS(36);
	385	DECLARE_MSM_GPIO_PINS(37);
	386	DECLARE_MSM_GPIO_PINS(38);
	387	DECLARE_MSM_GPIO_PINS(39);
	388	DECLARE_MSM_GPIO_PINS(40);
	389	DECLARE_MSM_GPIO_PINS(41);
	390	DECLARE_MSM_GPIO_PINS(42);
	391	DECLARE_MSM_GPIO_PINS(43);
	392	DECLARE_MSM_GPIO_PINS(44);
	393	DECLARE_MSM_GPIO_PINS(45);
	394	DECLARE_MSM_GPIO_PINS(46);
	395	DECLARE_MSM_GPIO_PINS(47);
	396	DECLARE_MSM_GPIO_PINS(48);
	397	DECLARE_MSM_GPIO_PINS(49);
	398	DECLARE_MSM_GPIO_PINS(50);
	399	DECLARE_MSM_GPIO_PINS(51);
	400	DECLARE_MSM_GPIO_PINS(52);
	401	DECLARE_MSM_GPIO_PINS(53);
	402	DECLARE_MSM_GPIO_PINS(54);
	403	DECLARE_MSM_GPIO_PINS(55);
	404	DECLARE_MSM_GPIO_PINS(56);
	405	DECLARE_MSM_GPIO_PINS(57);
	406	DECLARE_MSM_GPIO_PINS(58);
	407	DECLARE_MSM_GPIO_PINS(59);
	408	DECLARE_MSM_GPIO_PINS(60);
	409	DECLARE_MSM_GPIO_PINS(61);
	410	DECLARE_MSM_GPIO_PINS(62);
	411	DECLARE_MSM_GPIO_PINS(63);
	412	DECLARE_MSM_GPIO_PINS(64);
	413	DECLARE_MSM_GPIO_PINS(65);
	414	DECLARE_MSM_GPIO_PINS(66);
	415	DECLARE_MSM_GPIO_PINS(67);
	416	DECLARE_MSM_GPIO_PINS(68);
	417	DECLARE_MSM_GPIO_PINS(69);
	418	DECLARE_MSM_GPIO_PINS(70);
	419	DECLARE_MSM_GPIO_PINS(71);
	420	DECLARE_MSM_GPIO_PINS(72);
	421	DECLARE_MSM_GPIO_PINS(73);
	422	DECLARE_MSM_GPIO_PINS(74);
	423	DECLARE_MSM_GPIO_PINS(75);
	424	DECLARE_MSM_GPIO_PINS(76);
	425	DECLARE_MSM_GPIO_PINS(77);
	426	DECLARE_MSM_GPIO_PINS(78);
	427	DECLARE_MSM_GPIO_PINS(79);
	428	DECLARE_MSM_GPIO_PINS(80);
	429	DECLARE_MSM_GPIO_PINS(81);
	430	DECLARE_MSM_GPIO_PINS(82);
	431	DECLARE_MSM_GPIO_PINS(83);
	432	DECLARE_MSM_GPIO_PINS(84);
	433	DECLARE_MSM_GPIO_PINS(85);
	434	DECLARE_MSM_GPIO_PINS(86);
	435	DECLARE_MSM_GPIO_PINS(87);
	436	DECLARE_MSM_GPIO_PINS(88);
	437	DECLARE_MSM_GPIO_PINS(89);
	438	DECLARE_MSM_GPIO_PINS(90);
	439	DECLARE_MSM_GPIO_PINS(91);
	440	DECLARE_MSM_GPIO_PINS(92);
	441	DECLARE_MSM_GPIO_PINS(93);
	442	DECLARE_MSM_GPIO_PINS(94);
	443	DECLARE_MSM_GPIO_PINS(95);
	444	DECLARE_MSM_GPIO_PINS(96);
	445	DECLARE_MSM_GPIO_PINS(97);
	446	DECLARE_MSM_GPIO_PINS(98);
	447	DECLARE_MSM_GPIO_PINS(99);
	448	DECLARE_MSM_GPIO_PINS(100);
	449	DECLARE_MSM_GPIO_PINS(101);
	450	DECLARE_MSM_GPIO_PINS(102);
	451	DECLARE_MSM_GPIO_PINS(103);
	452	DECLARE_MSM_GPIO_PINS(104);
	453	DECLARE_MSM_GPIO_PINS(105);
	454	DECLARE_MSM_GPIO_PINS(106);
	455	DECLARE_MSM_GPIO_PINS(107);
	456	DECLARE_MSM_GPIO_PINS(108);
	457	DECLARE_MSM_GPIO_PINS(109);
	458	DECLARE_MSM_GPIO_PINS(110);
	459	DECLARE_MSM_GPIO_PINS(111);
	460	DECLARE_MSM_GPIO_PINS(112);
	461	DECLARE_MSM_GPIO_PINS(113);
	462	DECLARE_MSM_GPIO_PINS(114);
	463	DECLARE_MSM_GPIO_PINS(115);
	464	DECLARE_MSM_GPIO_PINS(116);
	465	DECLARE_MSM_GPIO_PINS(117);
	466	DECLARE_MSM_GPIO_PINS(118);
	467	DECLARE_MSM_GPIO_PINS(119);
	468	DECLARE_MSM_GPIO_PINS(120);
	469	DECLARE_MSM_GPIO_PINS(121);
	470	DECLARE_MSM_GPIO_PINS(122);
	471	DECLARE_MSM_GPIO_PINS(123);
	472	DECLARE_MSM_GPIO_PINS(124);
	473	DECLARE_MSM_GPIO_PINS(125);
	474	DECLARE_MSM_GPIO_PINS(126);
	475	DECLARE_MSM_GPIO_PINS(127);
	476	DECLARE_MSM_GPIO_PINS(128);
	477	DECLARE_MSM_GPIO_PINS(129);
	478	DECLARE_MSM_GPIO_PINS(130);
	479	DECLARE_MSM_GPIO_PINS(131);
	480	DECLARE_MSM_GPIO_PINS(132);
	481	DECLARE_MSM_GPIO_PINS(133);
	482	DECLARE_MSM_GPIO_PINS(134);
	483	DECLARE_MSM_GPIO_PINS(135);
	484	DECLARE_MSM_GPIO_PINS(136);
	485	DECLARE_MSM_GPIO_PINS(137);
	486	DECLARE_MSM_GPIO_PINS(138);
	487	DECLARE_MSM_GPIO_PINS(139);
	488	DECLARE_MSM_GPIO_PINS(140);
	489	DECLARE_MSM_GPIO_PINS(141);
	490	DECLARE_MSM_GPIO_PINS(142);
	491	DECLARE_MSM_GPIO_PINS(143);
	492	DECLARE_MSM_GPIO_PINS(144);
	493	DECLARE_MSM_GPIO_PINS(145);
	494	DECLARE_MSM_GPIO_PINS(146);
	495	DECLARE_MSM_GPIO_PINS(147);
	496	DECLARE_MSM_GPIO_PINS(148);
	497	DECLARE_MSM_GPIO_PINS(149);
	498	DECLARE_MSM_GPIO_PINS(150);
	499	DECLARE_MSM_GPIO_PINS(151);
	500	DECLARE_MSM_GPIO_PINS(152);
	501	DECLARE_MSM_GPIO_PINS(153);
	502	DECLARE_MSM_GPIO_PINS(154);
	503	DECLARE_MSM_GPIO_PINS(155);
	504	DECLARE_MSM_GPIO_PINS(156);
	505	DECLARE_MSM_GPIO_PINS(157);
	506	DECLARE_MSM_GPIO_PINS(158);
	507	DECLARE_MSM_GPIO_PINS(159);
	508	DECLARE_MSM_GPIO_PINS(160);
	509	DECLARE_MSM_GPIO_PINS(161);
	510	DECLARE_MSM_GPIO_PINS(162);
	511	DECLARE_MSM_GPIO_PINS(163);
	512	DECLARE_MSM_GPIO_PINS(164);
	513	DECLARE_MSM_GPIO_PINS(165);
	514	DECLARE_MSM_GPIO_PINS(166);
	515	DECLARE_MSM_GPIO_PINS(167);
	516	DECLARE_MSM_GPIO_PINS(168);
	517	DECLARE_MSM_GPIO_PINS(169);
	518	DECLARE_MSM_GPIO_PINS(170);
	519	DECLARE_MSM_GPIO_PINS(171);
	520	DECLARE_MSM_GPIO_PINS(172);
	521	DECLARE_MSM_GPIO_PINS(173);
	522	DECLARE_MSM_GPIO_PINS(174);
	523	DECLARE_MSM_GPIO_PINS(175);
	524	DECLARE_MSM_GPIO_PINS(176);
	525	DECLARE_MSM_GPIO_PINS(177);
	526	DECLARE_MSM_GPIO_PINS(178);
	527	DECLARE_MSM_GPIO_PINS(179);
	528	DECLARE_MSM_GPIO_PINS(180);
	529	DECLARE_MSM_GPIO_PINS(181);
	530	DECLARE_MSM_GPIO_PINS(182);
	531	DECLARE_MSM_GPIO_PINS(183);
	532	DECLARE_MSM_GPIO_PINS(184);
	533	DECLARE_MSM_GPIO_PINS(185);
	534	DECLARE_MSM_GPIO_PINS(186);
	535	DECLARE_MSM_GPIO_PINS(187);
	536	DECLARE_MSM_GPIO_PINS(188);
	537	DECLARE_MSM_GPIO_PINS(189);
	538	DECLARE_MSM_GPIO_PINS(190);
	539	DECLARE_MSM_GPIO_PINS(191);
	540	DECLARE_MSM_GPIO_PINS(192);
	541	DECLARE_MSM_GPIO_PINS(193);
	542	DECLARE_MSM_GPIO_PINS(194);
	543	DECLARE_MSM_GPIO_PINS(195);
	544	DECLARE_MSM_GPIO_PINS(196);
	545	DECLARE_MSM_GPIO_PINS(197);
	546	DECLARE_MSM_GPIO_PINS(198);
	547	DECLARE_MSM_GPIO_PINS(199);
	548	DECLARE_MSM_GPIO_PINS(200);
	549	DECLARE_MSM_GPIO_PINS(201);
	550	DECLARE_MSM_GPIO_PINS(202);
	551	DECLARE_MSM_GPIO_PINS(203);
	552	DECLARE_MSM_GPIO_PINS(204);
	553	DECLARE_MSM_GPIO_PINS(205);
	554	DECLARE_MSM_GPIO_PINS(206);
	555	DECLARE_MSM_GPIO_PINS(207);
	556	DECLARE_MSM_GPIO_PINS(208);
	557	DECLARE_MSM_GPIO_PINS(209);
	558	DECLARE_MSM_GPIO_PINS(210);
	559	DECLARE_MSM_GPIO_PINS(211);
	560	DECLARE_MSM_GPIO_PINS(212);
	561	DECLARE_MSM_GPIO_PINS(213);
	562	DECLARE_MSM_GPIO_PINS(214);
	563	DECLARE_MSM_GPIO_PINS(215);
	564	DECLARE_MSM_GPIO_PINS(216);
	565	DECLARE_MSM_GPIO_PINS(217);
	566	DECLARE_MSM_GPIO_PINS(218);
	567	DECLARE_MSM_GPIO_PINS(219);
	568	DECLARE_MSM_GPIO_PINS(220);
	569	DECLARE_MSM_GPIO_PINS(221);
	570	DECLARE_MSM_GPIO_PINS(222);
	571	DECLARE_MSM_GPIO_PINS(223);
	572	DECLARE_MSM_GPIO_PINS(224);
	573	DECLARE_MSM_GPIO_PINS(225);
	574	DECLARE_MSM_GPIO_PINS(226);
	575	DECLARE_MSM_GPIO_PINS(227);
	576
	577	static const unsigned int ufs_reset_pins[] = { 228 };
	578	static const unsigned int ufs1_reset_pins[] = { 229 };
	579	static const unsigned int sdc2_clk_pins[] = { 230 };
	580	static const unsigned int sdc2_cmd_pins[] = { 231 };
	581	static const unsigned int sdc2_data_pins[] = { 232 };
	582
	583	enum sc8280xp_functions {
	584	msm_mux_atest_char,
	585	msm_mux_atest_usb,
	586	msm_mux_audio_ref,
	587	msm_mux_cam_mclk,
	588	msm_mux_cci_async,
	589	msm_mux_cci_i2c,
	590	msm_mux_cci_timer0,
	591	msm_mux_cci_timer1,
	592	msm_mux_cci_timer2,
	593	msm_mux_cci_timer3,
	594	msm_mux_cci_timer4,
	595	msm_mux_cci_timer5,
	596	msm_mux_cci_timer6,
	597	msm_mux_cci_timer7,
	598	msm_mux_cci_timer8,
	599	msm_mux_cci_timer9,
	600	msm_mux_cmu_rng,
	601	msm_mux_cri_trng,
	602	msm_mux_cri_trng0,
	603	msm_mux_cri_trng1,
	604	msm_mux_dbg_out,
	605	msm_mux_ddr_bist,
	606	msm_mux_ddr_pxi0,
	607	msm_mux_ddr_pxi1,
	608	msm_mux_ddr_pxi2,
	609	msm_mux_ddr_pxi3,
	610	msm_mux_ddr_pxi4,
	611	msm_mux_ddr_pxi5,
	612	msm_mux_ddr_pxi6,
	613	msm_mux_ddr_pxi7,
	614	msm_mux_dp2_hot,
	615	msm_mux_dp3_hot,
	616	msm_mux_edp0_lcd,
	617	msm_mux_edp1_lcd,
	618	msm_mux_edp2_lcd,
	619	msm_mux_edp3_lcd,
	620	msm_mux_edp_hot,
	621	msm_mux_egpio,
	622	msm_mux_emac0_dll,
	623	msm_mux_emac0_mcg0,
	624	msm_mux_emac0_mcg1,
	625	msm_mux_emac0_mcg2,
	626	msm_mux_emac0_mcg3,
	627	msm_mux_emac0_phy,
	628	msm_mux_emac0_ptp,
	629	msm_mux_emac1_dll0,
	630	msm_mux_emac1_dll1,
	631	msm_mux_emac1_mcg0,
	632	msm_mux_emac1_mcg1,
	633	msm_mux_emac1_mcg2,
	634	msm_mux_emac1_mcg3,
	635	msm_mux_emac1_phy,
	636	msm_mux_emac1_ptp,
	637	msm_mux_gcc_gp1,
	638	msm_mux_gcc_gp2,
	639	msm_mux_gcc_gp3,
	640	msm_mux_gcc_gp4,
	641	msm_mux_gcc_gp5,
	642	msm_mux_gpio,
	643	msm_mux_hs1_mi2s,
	644	msm_mux_hs2_mi2s,
	645	msm_mux_hs3_mi2s,
	646	msm_mux_ibi_i3c,
	647	msm_mux_jitter_bist,
	648	msm_mux_lpass_slimbus,
	649	msm_mux_mdp0_vsync0,
	650	msm_mux_mdp0_vsync1,
	651	msm_mux_mdp0_vsync2,
	652	msm_mux_mdp0_vsync3,
	653	msm_mux_mdp0_vsync4,
	654	msm_mux_mdp0_vsync5,
	655	msm_mux_mdp0_vsync6,
	656	msm_mux_mdp0_vsync7,
	657	msm_mux_mdp0_vsync8,
	658	msm_mux_mdp1_vsync0,
	659	msm_mux_mdp1_vsync1,
	660	msm_mux_mdp1_vsync2,
	661	msm_mux_mdp1_vsync3,
	662	msm_mux_mdp1_vsync4,
	663	msm_mux_mdp1_vsync5,
	664	msm_mux_mdp1_vsync6,
	665	msm_mux_mdp1_vsync7,
	666	msm_mux_mdp1_vsync8,
	667	msm_mux_mdp_vsync,
	668	msm_mux_mi2s0_data0,
	669	msm_mux_mi2s0_data1,
	670	msm_mux_mi2s0_sck,
	671	msm_mux_mi2s0_ws,
	672	msm_mux_mi2s1_data0,
	673	msm_mux_mi2s1_data1,
	674	msm_mux_mi2s1_sck,
	675	msm_mux_mi2s1_ws,
	676	msm_mux_mi2s2_data0,
	677	msm_mux_mi2s2_data1,
	678	msm_mux_mi2s2_sck,
	679	msm_mux_mi2s2_ws,
	680	msm_mux_mi2s_mclk1,
	681	msm_mux_mi2s_mclk2,
	682	msm_mux_pcie2a_clkreq,
	683	msm_mux_pcie2b_clkreq,
	684	msm_mux_pcie3a_clkreq,
	685	msm_mux_pcie3b_clkreq,
	686	msm_mux_pcie4_clkreq,
	687	msm_mux_phase_flag,
	688	msm_mux_pll_bist,
	689	msm_mux_pll_clk,
	690	msm_mux_prng_rosc0,
	691	msm_mux_prng_rosc1,
	692	msm_mux_prng_rosc2,
	693	msm_mux_prng_rosc3,
	694	msm_mux_qdss_cti,
	695	msm_mux_qdss_gpio,
	696	msm_mux_qspi,
	697	msm_mux_qspi_clk,
	698	msm_mux_qspi_cs,
	699	msm_mux_qup0,
	700	msm_mux_qup1,
	701	msm_mux_qup10,
	702	msm_mux_qup11,
	703	msm_mux_qup12,
	704	msm_mux_qup13,
	705	msm_mux_qup14,
	706	msm_mux_qup15,
	707	msm_mux_qup16,
	708	msm_mux_qup17,
	709	msm_mux_qup18,
	710	msm_mux_qup19,
	711	msm_mux_qup2,
	712	msm_mux_qup20,
	713	msm_mux_qup21,
	714	msm_mux_qup22,
	715	msm_mux_qup23,
	716	msm_mux_qup3,
	717	msm_mux_qup4,
	718	msm_mux_qup5,
	719	msm_mux_qup6,
	720	msm_mux_qup7,
	721	msm_mux_qup8,
	722	msm_mux_qup9,
	723	msm_mux_rgmii_0,
	724	msm_mux_rgmii_1,
	725	msm_mux_sd_write,
	726	msm_mux_sdc40,
	727	msm_mux_sdc42,
	728	msm_mux_sdc43,
	729	msm_mux_sdc4_clk,
	730	msm_mux_sdc4_cmd,
	731	msm_mux_tb_trig,
	732	msm_mux_tgu,
	733	msm_mux_tsense_pwm1,
	734	msm_mux_tsense_pwm2,
	735	msm_mux_tsense_pwm3,
	736	msm_mux_tsense_pwm4,
	737	msm_mux_usb0_dp,
	738	msm_mux_usb0_phy,
	739	msm_mux_usb0_sbrx,
	740	msm_mux_usb0_sbtx,
	741	msm_mux_usb0_usb4,
	742	msm_mux_usb1_dp,
	743	msm_mux_usb1_phy,
	744	msm_mux_usb1_sbrx,
	745	msm_mux_usb1_sbtx,
	746	msm_mux_usb1_usb4,
	747	msm_mux_usb2phy_ac,
	748	msm_mux_vsense_trigger,
	749	msm_mux__,
	750	};
	751
	752	static const char * const gpio_groups[] = {
	753	"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
	754	"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
	755	"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
	756	"gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
	757	"gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
	758	"gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
	759	"gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
	760	"gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
	761	"gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
	762	"gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
	763	"gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio78",
	764	"gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", "gpio85",
	765	"gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", "gpio92",
	766	"gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", "gpio99",
	767	"gpio100", "gpio101", "gpio102", "gpio103", "gpio104", "gpio105",
	768	"gpio106", "gpio107", "gpio108", "gpio109", "gpio110", "gpio111",
	769	"gpio112", "gpio113", "gpio114", "gpio115", "gpio116", "gpio117",
	770	"gpio118", "gpio119", "gpio120", "gpio121", "gpio122", "gpio123",
	771	"gpio124", "gpio125", "gpio126", "gpio127", "gpio128", "gpio129",
	772	"gpio130", "gpio131", "gpio132", "gpio133", "gpio134", "gpio135",
	773	"gpio136", "gpio137", "gpio138", "gpio139", "gpio140", "gpio141",
	774	"gpio142", "gpio143", "gpio144", "gpio145", "gpio146", "gpio147",
	775	"gpio148", "gpio149", "gpio150", "gpio151", "gpio152", "gpio153",
	776	"gpio154", "gpio155", "gpio156", "gpio157", "gpio158", "gpio159",
	777	"gpio160", "gpio161", "gpio162", "gpio163", "gpio164", "gpio165",
	778	"gpio166", "gpio167", "gpio168", "gpio169", "gpio170", "gpio171",
	779	"gpio172", "gpio173", "gpio174", "gpio175", "gpio176", "gpio177",
	780	"gpio178", "gpio179", "gpio180", "gpio181", "gpio182", "gpio183",
	781	"gpio184", "gpio185", "gpio186", "gpio187", "gpio188", "gpio189",
	782	"gpio190", "gpio191", "gpio192", "gpio193", "gpio194", "gpio195",
	783	"gpio196", "gpio197", "gpio198", "gpio199", "gpio200", "gpio201",
	784	"gpio202", "gpio203", "gpio204", "gpio205", "gpio206", "gpio207",
	785	"gpio208", "gpio209", "gpio210", "gpio211", "gpio212", "gpio213",
	786	"gpio214", "gpio215", "gpio216", "gpio217", "gpio218", "gpio219",
	787	"gpio220", "gpio221", "gpio222", "gpio223", "gpio224", "gpio225",
	788	"gpio226", "gpio227",
	789	};
	790
	791	static const char * const atest_char_groups[] = {
	792	"gpio134", "gpio139", "gpio140", "gpio142", "gpio143",
	793	};
	794
	795	static const char * const atest_usb_groups[] = {
	796	"gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio78",
	797	"gpio79", "gpio97", "gpio98", "gpio101", "gpio102", "gpio103",
	798	"gpio104", "gpio105", "gpio110", "gpio111", "gpio112", "gpio113",
	799	"gpio114", "gpio121", "gpio122", "gpio130", "gpio131", "gpio135",
	800	"gpio137", "gpio138", "gpio148", "gpio149",
	801	};
	802
	803	static const char * const audio_ref_groups[] = {
	804	"gpio80",
	805	};
	806
	807	static const char * const cam_mclk_groups[] = {
	808	"gpio6", "gpio7", "gpio16", "gpio17", "gpio33", "gpio34", "gpio119",
	809	"gpio120",
	810	};
	811
	812	static const char * const cci_async_groups[] = {
	813	"gpio15", "gpio119", "gpio120", "gpio160", "gpio161", "gpio167",
	814	};
	815
	816	static const char * const cci_i2c_groups[] = {
	817	"gpio10", "gpio11", "gpio12", "gpio13", "gpio113", "gpio114",
	818	"gpio115", "gpio116", "gpio117", "gpio118", "gpio123", "gpio124",
	819	"gpio145", "gpio146", "gpio164", "gpio165",
	820	};
	821
	822	static const char * const cci_timer0_groups[] = {
	823	"gpio119",
	824	};
	825
	826	static const char * const cci_timer1_groups[] = {
	827	"gpio120",
	828	};
	829
	830	static const char * const cci_timer2_groups[] = {
	831	"gpio14",
	832	};
	833
	834	static const char * const cci_timer3_groups[] = {
	835	"gpio15",
	836	};
	837
	838	static const char * const cci_timer4_groups[] = {
	839	"gpio161",
	840	};
	841
	842	static const char * const cci_timer5_groups[] = {
	843	"gpio139",
	844	};
	845
	846	static const char * const cci_timer6_groups[] = {
	847	"gpio162",
	848	};
	849
	850	static const char * const cci_timer7_groups[] = {
	851	"gpio163",
	852	};
	853
	854	static const char * const cci_timer8_groups[] = {
	855	"gpio167",
	856	};
	857
	858	static const char * const cci_timer9_groups[] = {
	859	"gpio160",
	860	};
	861
	862	static const char * const cmu_rng_groups[] = {
	863	"gpio123", "gpio124", "gpio126", "gpio136",
	864	};
	865
	866	static const char * const cri_trng0_groups[] = {
	867	"gpio187",
	868	};
	869
	870	static const char * const cri_trng1_groups[] = {
	871	"gpio188",
	872	};
	873
	874	static const char * const cri_trng_groups[] = {
	875	"gpio190",
	876	};
	877
	878	static const char * const dbg_out_groups[] = {
	879	"gpio125",
	880	};
	881
	882	static const char * const ddr_bist_groups[] = {
	883	"gpio42", "gpio45", "gpio46", "gpio47",
	884	};
	885
	886	static const char * const ddr_pxi0_groups[] = {
	887	"gpio121", "gpio126",
	888	};
	889
	890	static const char * const ddr_pxi1_groups[] = {
	891	"gpio124", "gpio125",
	892	};
	893
	894	static const char * const ddr_pxi2_groups[] = {
	895	"gpio123", "gpio138",
	896	};
	897
	898	static const char * const ddr_pxi3_groups[] = {
	899	"gpio120", "gpio137",
	900	};
	901
	902	static const char * const ddr_pxi4_groups[] = {
	903	"gpio216", "gpio217",
	904	};
	905
	906	static const char * const ddr_pxi5_groups[] = {
	907	"gpio214", "gpio215",
	908	};
	909
	910	static const char * const ddr_pxi6_groups[] = {
	911	"gpio79", "gpio218",
	912	};
	913
	914	static const char * const ddr_pxi7_groups[] = {
	915	"gpio135", "gpio136",
	916	};
	917
	918	static const char * const dp2_hot_groups[] = {
	919	"gpio20",
	920	};
	921
	922	static const char * const dp3_hot_groups[] = {
	923	"gpio45",
	924	};
	925
	926	static const char * const edp0_lcd_groups[] = {
	927	"gpio26",
	928	};
	929
	930	static const char * const edp1_lcd_groups[] = {
	931	"gpio27",
	932	};
	933
	934	static const char * const edp2_lcd_groups[] = {
	935	"gpio28",
	936	};
	937
	938	static const char * const edp3_lcd_groups[] = {
	939	"gpio29",
	940	};
	941
	942	static const char * const edp_hot_groups[] = {
	943	"gpio2", "gpio3", "gpio6", "gpio7",
	944	};
	945
	946	static const char * const egpio_groups[] = {
	947	"gpio189", "gpio190", "gpio191", "gpio192", "gpio193", "gpio194",
	948	"gpio195", "gpio196", "gpio197", "gpio198", "gpio199", "gpio200",
	949	"gpio201", "gpio202", "gpio203", "gpio204", "gpio205", "gpio206",
	950	"gpio207", "gpio208", "gpio209", "gpio210", "gpio211", "gpio212",
	951	"gpio213", "gpio214", "gpio215", "gpio216", "gpio217", "gpio218",
	952	"gpio219", "gpio220", "gpio221", "gpio222", "gpio223", "gpio224",
	953	"gpio225", "gpio226", "gpio227",
	954	};
	955
	956	static const char * const emac0_dll_groups[] = {
	957	"gpio216", "gpio217",
	958	};
	959
	960	static const char * const emac0_mcg0_groups[] = {
	961	"gpio160",
	962	};
	963
	964	static const char * const emac0_mcg1_groups[] = {
	965	"gpio161",
	966	};
	967
	968	static const char * const emac0_mcg2_groups[] = {
	969	"gpio162",
	970	};
	971
	972	static const char * const emac0_mcg3_groups[] = {
	973	"gpio163",
	974	};
	975
	976	static const char * const emac0_phy_groups[] = {
	977	"gpio127",
	978	};
	979
	980	static const char * const emac0_ptp_groups[] = {
	981	"gpio130", "gpio130", "gpio131", "gpio131", "gpio156", "gpio156",
	982	"gpio157", "gpio157", "gpio158", "gpio158", "gpio159", "gpio159",
	983	};
	984
	985	static const char * const emac1_dll0_groups[] = {
	986	"gpio215",
	987	};
	988
	989	static const char * const emac1_dll1_groups[] = {
	990	"gpio218",
	991	};
	992
	993	static const char * const emac1_mcg0_groups[] = {
	994	"gpio57",
	995	};
	996
	997	static const char * const emac1_mcg1_groups[] = {
	998	"gpio58",
	999	};
	1000
	1001	static const char * const emac1_mcg2_groups[] = {
	1002	"gpio68",
	1003	};
	1004
	1005	static const char * const emac1_mcg3_groups[] = {
	1006	"gpio69",
	1007	};
	1008
	1009	static const char * const emac1_phy_groups[] = {
	1010	"gpio54",
	1011	};
	1012
	1013	static const char * const emac1_ptp_groups[] = {
	1014	"gpio55", "gpio55", "gpio56", "gpio56", "gpio93", "gpio93", "gpio94",
	1015	"gpio94", "gpio95", "gpio95", "gpio96", "gpio96",
	1016	};
	1017
	1018	static const char * const gcc_gp1_groups[] = {
	1019	"gpio119", "gpio149",
	1020	};
	1021
	1022	static const char * const gcc_gp2_groups[] = {
	1023	"gpio114", "gpio120",
	1024	};
	1025
	1026	static const char * const gcc_gp3_groups[] = {
	1027	"gpio115", "gpio139",
	1028	};
	1029
	1030	static const char * const gcc_gp4_groups[] = {
	1031	"gpio160", "gpio162",
	1032	};
	1033
	1034	static const char * const gcc_gp5_groups[] = {
	1035	"gpio167", "gpio168",
	1036	};
	1037
	1038	static const char * const hs1_mi2s_groups[] = {
	1039	"gpio208", "gpio209", "gpio210", "gpio211",
	1040	};
	1041
	1042	static const char * const hs2_mi2s_groups[] = {
	1043	"gpio91", "gpio92", "gpio218", "gpio219",
	1044	};
	1045
	1046	static const char * const hs3_mi2s_groups[] = {
	1047	"gpio224", "gpio225", "gpio226", "gpio227",
	1048	};
	1049
	1050	static const char * const ibi_i3c_groups[] = {
	1051	"gpio4", "gpio5", "gpio36", "gpio37", "gpio128", "gpio129", "gpio154",
	1052	"gpio155",
	1053	};
	1054
	1055	static const char * const jitter_bist_groups[] = {
	1056	"gpio140",
	1057	};
	1058
	1059	static const char * const lpass_slimbus_groups[] = {
	1060	"gpio220", "gpio221",
	1061	};
	1062
	1063	static const char * const mdp0_vsync0_groups[] = {
	1064	"gpio1",
	1065	};
	1066
	1067	static const char * const mdp0_vsync1_groups[] = {
	1068	"gpio2",
	1069	};
	1070
	1071	static const char * const mdp0_vsync2_groups[] = {
	1072	"gpio8",
	1073	};
	1074
	1075	static const char * const mdp0_vsync3_groups[] = {
	1076	"gpio9",
	1077	};
	1078
	1079	static const char * const mdp0_vsync4_groups[] = {
	1080	"gpio10",
	1081	};
	1082
	1083	static const char * const mdp0_vsync5_groups[] = {
	1084	"gpio11",
	1085	};
	1086
	1087	static const char * const mdp0_vsync6_groups[] = {
	1088	"gpio12",
	1089	};
	1090
	1091	static const char * const mdp0_vsync7_groups[] = {
	1092	"gpio13",
	1093	};
	1094
	1095	static const char * const mdp0_vsync8_groups[] = {
	1096	"gpio16",
	1097	};
	1098
	1099	static const char * const mdp1_vsync0_groups[] = {
	1100	"gpio17",
	1101	};
	1102
	1103	static const char * const mdp1_vsync1_groups[] = {
	1104	"gpio18",
	1105	};
	1106
	1107	static const char * const mdp1_vsync2_groups[] = {
	1108	"gpio19",
	1109	};
	1110
	1111	static const char * const mdp1_vsync3_groups[] = {
	1112	"gpio20",
	1113	};
	1114
	1115	static const char * const mdp1_vsync4_groups[] = {
	1116	"gpio36",
	1117	};
	1118
	1119	static const char * const mdp1_vsync5_groups[] = {
	1120	"gpio37",
	1121	};
	1122
	1123	static const char * const mdp1_vsync6_groups[] = {
	1124	"gpio38",
	1125	};
	1126
	1127	static const char * const mdp1_vsync7_groups[] = {
	1128	"gpio39",
	1129	};
	1130
	1131	static const char * const mdp1_vsync8_groups[] = {
	1132	"gpio40",
	1133	};
	1134
	1135	static const char * const mdp_vsync_groups[] = {
	1136	"gpio8", "gpio100", "gpio101",
	1137	};
	1138
	1139	static const char * const mi2s0_data0_groups[] = {
	1140	"gpio95",
	1141	};
	1142
	1143	static const char * const mi2s0_data1_groups[] = {
	1144	"gpio96",
	1145	};
	1146
	1147	static const char * const mi2s0_sck_groups[] = {
	1148	"gpio93",
	1149	};
	1150
	1151	static const char * const mi2s0_ws_groups[] = {
	1152	"gpio94",
	1153	};
	1154
	1155	static const char * const mi2s1_data0_groups[] = {
	1156	"gpio222",
	1157	};
	1158
	1159	static const char * const mi2s1_data1_groups[] = {
	1160	"gpio223",
	1161	};
	1162
	1163	static const char * const mi2s1_sck_groups[] = {
	1164	"gpio220",
	1165	};
	1166
	1167	static const char * const mi2s1_ws_groups[] = {
	1168	"gpio221",
	1169	};
	1170
	1171	static const char * const mi2s2_data0_groups[] = {
	1172	"gpio214",
	1173	};
	1174
	1175	static const char * const mi2s2_data1_groups[] = {
	1176	"gpio215",
	1177	};
	1178
	1179	static const char * const mi2s2_sck_groups[] = {
	1180	"gpio212",
	1181	};
	1182
	1183	static const char * const mi2s2_ws_groups[] = {
	1184	"gpio213",
	1185	};
	1186
	1187	static const char * const mi2s_mclk1_groups[] = {
	1188	"gpio80", "gpio216",
	1189	};
	1190
	1191	static const char * const mi2s_mclk2_groups[] = {
	1192	"gpio217",
	1193	};
	1194
	1195	static const char * const pcie2a_clkreq_groups[] = {
	1196	"gpio142",
	1197	};
	1198
	1199	static const char * const pcie2b_clkreq_groups[] = {
	1200	"gpio144",
	1201	};
	1202
	1203	static const char * const pcie3a_clkreq_groups[] = {
	1204	"gpio150",
	1205	};
	1206
	1207	static const char * const pcie3b_clkreq_groups[] = {
	1208	"gpio152",
	1209	};
	1210
	1211	static const char * const pcie4_clkreq_groups[] = {
	1212	"gpio140",
	1213	};
	1214
	1215	static const char * const phase_flag_groups[] = {
	1216	"gpio80", "gpio81", "gpio82", "gpio83", "gpio87", "gpio88", "gpio89",
	1217	"gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio132",
	1218	"gpio144", "gpio145", "gpio146", "gpio147", "gpio195", "gpio196",
	1219	"gpio197", "gpio198", "gpio202", "gpio219", "gpio220", "gpio221",
	1220	"gpio222", "gpio223", "gpio224", "gpio225", "gpio226", "gpio227",
	1221	};
	1222
	1223	static const char * const pll_bist_groups[] = {
	1224	"gpio84",
	1225	};
	1226
	1227	static const char * const pll_clk_groups[] = {
	1228	"gpio84", "gpio86",
	1229	};
	1230
	1231	static const char * const prng_rosc0_groups[] = {
	1232	"gpio189",
	1233	};
	1234
	1235	static const char * const prng_rosc1_groups[] = {
	1236	"gpio191",
	1237	};
	1238
	1239	static const char * const prng_rosc2_groups[] = {
	1240	"gpio193",
	1241	};
	1242
	1243	static const char * const prng_rosc3_groups[] = {
	1244	"gpio194",
	1245	};
	1246
	1247	static const char * const qdss_cti_groups[] = {
	1248	"gpio3", "gpio4", "gpio7", "gpio21", "gpio30", "gpio30", "gpio31",
	1249	"gpio31",
	1250	};
	1251
	1252	static const char * const qdss_gpio_groups[] = {
	1253	"gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15", "gpio16",
	1254	"gpio17", "gpio80", "gpio96", "gpio115", "gpio116", "gpio117",
	1255	"gpio118", "gpio119", "gpio120", "gpio121", "gpio122", "gpio161",
	1256	"gpio162", "gpio195", "gpio196", "gpio197", "gpio198", "gpio201",
	1257	"gpio202", "gpio206", "gpio207", "gpio212", "gpio213", "gpio214",
	1258	"gpio215", "gpio216", "gpio217", "gpio222", "gpio223",
	1259	};
	1260
	1261	static const char * const qspi_clk_groups[] = {
	1262	"gpio74",
	1263	};
	1264
	1265	static const char * const qspi_cs_groups[] = {
	1266	"gpio75", "gpio81",
	1267	};
	1268
	1269	static const char * const qspi_groups[] = {
	1270	"gpio76", "gpio78", "gpio79",
	1271	};
	1272
	1273	static const char * const qup0_groups[] = {
	1274	"gpio135", "gpio136", "gpio137", "gpio138",
	1275	};
	1276
	1277	static const char * const qup10_groups[] = {
	1278	"gpio22", "gpio23", "gpio24", "gpio25",
	1279	};
	1280
	1281	static const char * const qup11_groups[] = {
	1282	"gpio18", "gpio19", "gpio20", "gpio21",
	1283	};
	1284
	1285	static const char * const qup12_groups[] = {
	1286	"gpio0", "gpio1", "gpio2", "gpio3",
	1287	};
	1288
	1289	static const char * const qup13_groups[] = {
	1290	"gpio26", "gpio27", "gpio28", "gpio29",
	1291	};
	1292
	1293	static const char * const qup14_groups[] = {
	1294	"gpio4", "gpio5", "gpio6", "gpio7",
	1295	};
	1296
	1297	static const char * const qup15_groups[] = {
	1298	"gpio36", "gpio37", "gpio38", "gpio39",
	1299	};
	1300
	1301	static const char * const qup16_groups[] = {
	1302	"gpio70", "gpio71", "gpio72", "gpio73",
	1303	};
	1304
	1305	static const char * const qup17_groups[] = {
	1306	"gpio61", "gpio62", "gpio63", "gpio64",
	1307	};
	1308
	1309	static const char * const qup18_groups[] = {
	1310	"gpio66", "gpio67", "gpio68", "gpio69",
	1311	};
	1312
	1313	static const char * const qup19_groups[] = {
	1314	"gpio55", "gpio56", "gpio57", "gpio58",
	1315	};
	1316
	1317	static const char * const qup1_groups[] = {
	1318	"gpio158", "gpio159", "gpio160", "gpio161",
	1319	};
	1320
	1321	static const char * const qup20_groups[] = {
	1322	"gpio87", "gpio88", "gpio89", "gpio90", "gpio91", "gpio92", "gpio110",
	1323	};
	1324
	1325	static const char * const qup21_groups[] = {
	1326	"gpio81", "gpio82", "gpio83", "gpio84",
	1327	};
	1328
	1329	static const char * const qup22_groups[] = {
	1330	"gpio83", "gpio84", "gpio85", "gpio86",
	1331	};
	1332
	1333	static const char * const qup23_groups[] = {
	1334	"gpio59", "gpio60", "gpio61", "gpio62",
	1335	};
	1336
	1337	static const char * const qup2_groups[] = {
	1338	"gpio121", "gpio122", "gpio123", "gpio124",
	1339	};
	1340
	1341	static const char * const qup3_groups[] = {
	1342	"gpio135", "gpio136", "gpio137", "gpio138",
	1343	};
	1344
	1345	static const char * const qup4_groups[] = {
	1346	"gpio111", "gpio112", "gpio171", "gpio172", "gpio173", "gpio174",
	1347	"gpio175",
	1348	};
	1349
	1350	static const char * const qup5_groups[] = {
	1351	"gpio111", "gpio112", "gpio145", "gpio146",
	1352	};
	1353
	1354	static const char * const qup6_groups[] = {
	1355	"gpio154", "gpio155", "gpio156", "gpio157",
	1356	};
	1357
	1358	static const char * const qup7_groups[] = {
	1359	"gpio125", "gpio126", "gpio128", "gpio129",
	1360	};
	1361
	1362	static const char * const qup8_groups[] = {
	1363	"gpio43", "gpio44", "gpio45", "gpio46",
	1364	};
	1365
	1366	static const char * const qup9_groups[] = {
	1367	"gpio41", "gpio42", "gpio43", "gpio44",
	1368	};
	1369
	1370	static const char * const rgmii_0_groups[] = {
	1371	"gpio175", "gpio176", "gpio177", "gpio178", "gpio179", "gpio180",
	1372	"gpio181", "gpio182", "gpio183", "gpio184", "gpio185", "gpio186",
	1373	"gpio187", "gpio188",
	1374	};
	1375
	1376	static const char * const rgmii_1_groups[] = {
	1377	"gpio97", "gpio98", "gpio99", "gpio100", "gpio101", "gpio102",
	1378	"gpio103", "gpio104", "gpio105", "gpio106", "gpio107", "gpio108",
	1379	"gpio109", "gpio110",
	1380	};
	1381
	1382	static const char * const sd_write_groups[] = {
	1383	"gpio130",
	1384	};
	1385
	1386	static const char * const sdc40_groups[] = {
	1387	"gpio76",
	1388	};
	1389
	1390	static const char * const sdc42_groups[] = {
	1391	"gpio78",
	1392	};
	1393
	1394	static const char * const sdc43_groups[] = {
	1395	"gpio79",
	1396	};
	1397
	1398	static const char * const sdc4_clk_groups[] = {
	1399	"gpio74",
	1400	};
	1401
	1402	static const char * const sdc4_cmd_groups[] = {
	1403	"gpio75",
	1404	};
	1405
	1406	static const char * const tb_trig_groups[] = {
	1407	"gpio153", "gpio157",
	1408	};
	1409
	1410	static const char * const tgu_groups[] = {
	1411	"gpio101", "gpio102", "gpio103", "gpio104", "gpio105", "gpio106",
	1412	"gpio107", "gpio108",
	1413	};
	1414
	1415	static const char * const tsense_pwm1_groups[] = {
	1416	"gpio70",
	1417	};
	1418
	1419	static const char * const tsense_pwm2_groups[] = {
	1420	"gpio69",
	1421	};
	1422
	1423	static const char * const tsense_pwm3_groups[] = {
	1424	"gpio67",
	1425	};
	1426
	1427	static const char * const tsense_pwm4_groups[] = {
	1428	"gpio65",
	1429	};
	1430
	1431	static const char * const usb0_dp_groups[] = {
	1432	"gpio21",
	1433	};
	1434
	1435	static const char * const usb0_phy_groups[] = {
	1436	"gpio166",
	1437	};
	1438
	1439	static const char * const usb0_sbrx_groups[] = {
	1440	"gpio170",
	1441	};
	1442
	1443	static const char * const usb0_sbtx_groups[] = {
	1444	"gpio168", "gpio169",
	1445	};
	1446
	1447	static const char * const usb0_usb4_groups[] = {
	1448	"gpio132",
	1449	};
	1450
	1451	static const char * const usb1_dp_groups[] = {
	1452	"gpio9",
	1453	};
	1454
	1455	static const char * const usb1_phy_groups[] = {
	1456	"gpio49",
	1457	};
	1458
	1459	static const char * const usb1_sbrx_groups[] = {
	1460	"gpio53",
	1461	};
	1462
	1463	static const char * const usb1_sbtx_groups[] = {
	1464	"gpio51", "gpio52",
	1465	};
	1466
	1467	static const char * const usb1_usb4_groups[] = {
	1468	"gpio32",
	1469	};
	1470
	1471	static const char * const usb2phy_ac_groups[] = {
	1472	"gpio24", "gpio25", "gpio133", "gpio134", "gpio148", "gpio149",
	1473	};
	1474
	1475	static const char * const vsense_trigger_groups[] = {
	1476	"gpio81",
	1477	};
	1478
	1479	static const struct msm_function sc8280xp_functions[] = {
	1480	FUNCTION(atest_char),
	1481	FUNCTION(atest_usb),
	1482	FUNCTION(audio_ref),
	1483	FUNCTION(cam_mclk),
	1484	FUNCTION(cci_async),
	1485	FUNCTION(cci_i2c),
	1486	FUNCTION(cci_timer0),
	1487	FUNCTION(cci_timer1),
	1488	FUNCTION(cci_timer2),
	1489	FUNCTION(cci_timer3),
	1490	FUNCTION(cci_timer4),
	1491	FUNCTION(cci_timer5),
	1492	FUNCTION(cci_timer6),
	1493	FUNCTION(cci_timer7),
	1494	FUNCTION(cci_timer8),
	1495	FUNCTION(cci_timer9),
	1496	FUNCTION(cmu_rng),
	1497	FUNCTION(cri_trng),
	1498	FUNCTION(cri_trng0),
	1499	FUNCTION(cri_trng1),
	1500	FUNCTION(dbg_out),
	1501	FUNCTION(ddr_bist),
	1502	FUNCTION(ddr_pxi0),
	1503	FUNCTION(ddr_pxi1),
	1504	FUNCTION(ddr_pxi2),
	1505	FUNCTION(ddr_pxi3),
	1506	FUNCTION(ddr_pxi4),
	1507	FUNCTION(ddr_pxi5),
	1508	FUNCTION(ddr_pxi6),
	1509	FUNCTION(ddr_pxi7),
	1510	FUNCTION(dp2_hot),
	1511	FUNCTION(dp3_hot),
	1512	FUNCTION(edp0_lcd),
	1513	FUNCTION(edp1_lcd),
	1514	FUNCTION(edp2_lcd),
	1515	FUNCTION(edp3_lcd),
	1516	FUNCTION(edp_hot),
	1517	FUNCTION(egpio),
	1518	FUNCTION(emac0_dll),
	1519	FUNCTION(emac0_mcg0),
	1520	FUNCTION(emac0_mcg1),
	1521	FUNCTION(emac0_mcg2),
	1522	FUNCTION(emac0_mcg3),
	1523	FUNCTION(emac0_phy),
	1524	FUNCTION(emac0_ptp),
	1525	FUNCTION(emac1_dll0),
	1526	FUNCTION(emac1_dll1),
	1527	FUNCTION(emac1_mcg0),
	1528	FUNCTION(emac1_mcg1),
	1529	FUNCTION(emac1_mcg2),
	1530	FUNCTION(emac1_mcg3),
	1531	FUNCTION(emac1_phy),
	1532	FUNCTION(emac1_ptp),
	1533	FUNCTION(gcc_gp1),
	1534	FUNCTION(gcc_gp2),
	1535	FUNCTION(gcc_gp3),
	1536	FUNCTION(gcc_gp4),
	1537	FUNCTION(gcc_gp5),
	1538	FUNCTION(gpio),
	1539	FUNCTION(hs1_mi2s),
	1540	FUNCTION(hs2_mi2s),
	1541	FUNCTION(hs3_mi2s),
	1542	FUNCTION(ibi_i3c),
	1543	FUNCTION(jitter_bist),
	1544	FUNCTION(lpass_slimbus),
	1545	FUNCTION(mdp0_vsync0),
	1546	FUNCTION(mdp0_vsync1),
	1547	FUNCTION(mdp0_vsync2),
	1548	FUNCTION(mdp0_vsync3),
	1549	FUNCTION(mdp0_vsync4),
	1550	FUNCTION(mdp0_vsync5),
	1551	FUNCTION(mdp0_vsync6),
	1552	FUNCTION(mdp0_vsync7),
	1553	FUNCTION(mdp0_vsync8),
	1554	FUNCTION(mdp1_vsync0),
	1555	FUNCTION(mdp1_vsync1),
	1556	FUNCTION(mdp1_vsync2),
	1557	FUNCTION(mdp1_vsync3),
	1558	FUNCTION(mdp1_vsync4),
	1559	FUNCTION(mdp1_vsync5),
	1560	FUNCTION(mdp1_vsync6),
	1561	FUNCTION(mdp1_vsync7),
	1562	FUNCTION(mdp1_vsync8),
	1563	FUNCTION(mdp_vsync),
	1564	FUNCTION(mi2s0_data0),
	1565	FUNCTION(mi2s0_data1),
	1566	FUNCTION(mi2s0_sck),
	1567	FUNCTION(mi2s0_ws),
	1568	FUNCTION(mi2s1_data0),
	1569	FUNCTION(mi2s1_data1),
	1570	FUNCTION(mi2s1_sck),
	1571	FUNCTION(mi2s1_ws),
	1572	FUNCTION(mi2s2_data0),
	1573	FUNCTION(mi2s2_data1),
	1574	FUNCTION(mi2s2_sck),
	1575	FUNCTION(mi2s2_ws),
	1576	FUNCTION(mi2s_mclk1),
	1577	FUNCTION(mi2s_mclk2),
	1578	FUNCTION(pcie2a_clkreq),
	1579	FUNCTION(pcie2b_clkreq),
	1580	FUNCTION(pcie3a_clkreq),
	1581	FUNCTION(pcie3b_clkreq),
	1582	FUNCTION(pcie4_clkreq),
	1583	FUNCTION(phase_flag),
	1584	FUNCTION(pll_bist),
	1585	FUNCTION(pll_clk),
	1586	FUNCTION(prng_rosc0),
	1587	FUNCTION(prng_rosc1),
	1588	FUNCTION(prng_rosc2),
	1589	FUNCTION(prng_rosc3),
	1590	FUNCTION(qdss_cti),
	1591	FUNCTION(qdss_gpio),
	1592	FUNCTION(qspi),
	1593	FUNCTION(qspi_clk),
	1594	FUNCTION(qspi_cs),
	1595	FUNCTION(qup0),
	1596	FUNCTION(qup1),
	1597	FUNCTION(qup2),
	1598	FUNCTION(qup3),
	1599	FUNCTION(qup4),
	1600	FUNCTION(qup5),
	1601	FUNCTION(qup6),
	1602	FUNCTION(qup7),
	1603	FUNCTION(qup8),
	1604	FUNCTION(qup9),
	1605	FUNCTION(qup10),
	1606	FUNCTION(qup11),
	1607	FUNCTION(qup12),
	1608	FUNCTION(qup13),
	1609	FUNCTION(qup14),
	1610	FUNCTION(qup15),
	1611	FUNCTION(qup16),
	1612	FUNCTION(qup17),
	1613	FUNCTION(qup18),
	1614	FUNCTION(qup19),
	1615	FUNCTION(qup20),
	1616	FUNCTION(qup21),
	1617	FUNCTION(qup22),
	1618	FUNCTION(qup23),
	1619	FUNCTION(rgmii_0),
	1620	FUNCTION(rgmii_1),
	1621	FUNCTION(sd_write),
	1622	FUNCTION(sdc40),
	1623	FUNCTION(sdc42),
	1624	FUNCTION(sdc43),
	1625	FUNCTION(sdc4_clk),
	1626	FUNCTION(sdc4_cmd),
	1627	FUNCTION(tb_trig),
	1628	FUNCTION(tgu),
	1629	FUNCTION(tsense_pwm1),
	1630	FUNCTION(tsense_pwm2),
	1631	FUNCTION(tsense_pwm3),
	1632	FUNCTION(tsense_pwm4),
	1633	FUNCTION(usb0_dp),
	1634	FUNCTION(usb0_phy),
	1635	FUNCTION(usb0_sbrx),
	1636	FUNCTION(usb0_sbtx),
	1637	FUNCTION(usb0_usb4),
	1638	FUNCTION(usb1_dp),
	1639	FUNCTION(usb1_phy),
	1640	FUNCTION(usb1_sbrx),
	1641	FUNCTION(usb1_sbtx),
	1642	FUNCTION(usb1_usb4),
	1643	FUNCTION(usb2phy_ac),
	1644	FUNCTION(vsense_trigger),
	1645	};
	1646
	1647	static const struct msm_pingroup sc8280xp_groups[] = {
	1648	[0] = PINGROUP(0, qup12, _, _, _, _, _, _),
	1649	[1] = PINGROUP(1, qup12, mdp0_vsync0, _, _, _, _, _),
	1650	[2] = PINGROUP(2, edp_hot, qup12, mdp0_vsync1, _, _, _, _),
	1651	[3] = PINGROUP(3, edp_hot, qup12, qdss_cti, _, _, _, _),
	1652	[4] = PINGROUP(4, qup14, ibi_i3c, qdss_cti, _, _, _, _),
	1653	[5] = PINGROUP(5, qup14, ibi_i3c, _, _, _, _, _),
	1654	[6] = PINGROUP(6, edp_hot, qup14, cam_mclk, _, _, _, _),
	1655	[7] = PINGROUP(7, edp_hot, qup14, qdss_cti, cam_mclk, _, _, _),
	1656	[8] = PINGROUP(8, mdp_vsync, mdp0_vsync2, _, _, _, _, _),
	1657	[9] = PINGROUP(9, usb1_dp, mdp0_vsync3, _, _, _, _, _),
	1658	[10] = PINGROUP(10, cci_i2c, mdp0_vsync4, _, qdss_gpio, _, _, _),
	1659	[11] = PINGROUP(11, cci_i2c, mdp0_vsync5, _, qdss_gpio, _, _, _),
	1660	[12] = PINGROUP(12, cci_i2c, mdp0_vsync6, _, qdss_gpio, _, _, _),
	1661	[13] = PINGROUP(13, cci_i2c, mdp0_vsync7, _, qdss_gpio, _, _, _),
	1662	[14] = PINGROUP(14, cci_timer2, qdss_gpio, _, _, _, _, _),
	1663	[15] = PINGROUP(15, cci_timer3, cci_async, _, qdss_gpio, _, _, _),
	1664	[16] = PINGROUP(16, cam_mclk, mdp0_vsync8, _, qdss_gpio, _, _, _),
	1665	[17] = PINGROUP(17, cam_mclk, mdp1_vsync0, _, qdss_gpio, _, _, _),
	1666	[18] = PINGROUP(18, qup11, mdp1_vsync1, _, _, _, _, _),
	1667	[19] = PINGROUP(19, qup11, mdp1_vsync2, _, _, _, _, _),
	1668	[20] = PINGROUP(20, qup11, dp2_hot, mdp1_vsync3, _, _, _, _),
	1669	[21] = PINGROUP(21, qup11, usb0_dp, qdss_cti, _, _, _, _),
	1670	[22] = PINGROUP(22, qup10, _, _, _, _, _, _),
	1671	[23] = PINGROUP(23, qup10, _, _, _, _, _, _),
	1672	[24] = PINGROUP(24, qup10, usb2phy_ac, _, _, _, _, _),
	1673	[25] = PINGROUP(25, qup10, usb2phy_ac, _, _, _, _, _),
	1674	[26] = PINGROUP(26, qup13, edp0_lcd, _, _, _, _, _),
	1675	[27] = PINGROUP(27, qup13, edp1_lcd, _, _, _, _, _),
	1676	[28] = PINGROUP(28, qup13, edp2_lcd, _, _, _, _, _),
	1677	[29] = PINGROUP(29, qup13, edp3_lcd, _, _, _, _, _),
	1678	[30] = PINGROUP(30, qdss_cti, qdss_cti, _, _, _, _, _),
	1679	[31] = PINGROUP(31, qdss_cti, qdss_cti, _, _, _, _, _),
	1680	[32] = PINGROUP(32, usb1_usb4, _, _, _, _, _, _),
	1681	[33] = PINGROUP(33, cam_mclk, _, _, _, _, _, _),
	1682	[34] = PINGROUP(34, cam_mclk, _, _, _, _, _, _),
	1683	[35] = PINGROUP(35, _, _, _, _, _, _, _),
	1684	[36] = PINGROUP(36, qup15, ibi_i3c, mdp1_vsync4, _, _, _, _),
	1685	[37] = PINGROUP(37, qup15, ibi_i3c, mdp1_vsync5, _, _, _, _),
	1686	[38] = PINGROUP(38, qup15, mdp1_vsync6, _, _, _, _, _),
	1687	[39] = PINGROUP(39, qup15, mdp1_vsync7, _, _, _, _, _),
	1688	[40] = PINGROUP(40, mdp1_vsync8, _, _, _, _, _, _),
	1689	[41] = PINGROUP(41, qup9, _, _, _, _, _, _),
	1690	[42] = PINGROUP(42, qup9, ddr_bist, _, _, _, _, _),
	1691	[43] = PINGROUP(43, qup8, qup9, _, _, _, _, _),
	1692	[44] = PINGROUP(44, qup8, qup9, _, _, _, _, _),
	1693	[45] = PINGROUP(45, qup8, dp3_hot, ddr_bist, _, _, _, _),
	1694	[46] = PINGROUP(46, qup8, ddr_bist, _, _, _, _, _),
	1695	[47] = PINGROUP(47, ddr_bist, _, _, _, _, _, _),
	1696	[48] = PINGROUP(48, _, _, _, _, _, _, _),
	1697	[49] = PINGROUP(49, usb1_phy, _, _, _, _, _, _),
	1698	[50] = PINGROUP(50, _, _, _, _, _, _, _),
	1699	[51] = PINGROUP(51, usb1_sbtx, _, _, _, _, _, _),
	1700	[52] = PINGROUP(52, usb1_sbtx, _, _, _, _, _, _),
	1701	[53] = PINGROUP(53, usb1_sbrx, _, _, _, _, _, _),
	1702	[54] = PINGROUP(54, emac1_phy, _, _, _, _, _, _),
	1703	[55] = PINGROUP(55, emac1_ptp, emac1_ptp, qup19, _, _, _, _),
	1704	[56] = PINGROUP(56, emac1_ptp, emac1_ptp, qup19, _, _, _, _),
	1705	[57] = PINGROUP(57, qup19, emac1_mcg0, _, _, _, _, _),
	1706	[58] = PINGROUP(58, qup19, emac1_mcg1, _, _, _, _, _),
	1707	[59] = PINGROUP(59, qup23, _, _, _, _, _, _),
	1708	[60] = PINGROUP(60, qup23, _, _, _, _, _, _),
	1709	[61] = PINGROUP(61, qup23, qup17, _, _, _, _, _),
	1710	[62] = PINGROUP(62, qup23, qup17, _, _, _, _, _),
	1711	[63] = PINGROUP(63, qup17, _, _, _, _, _, _),
	1712	[64] = PINGROUP(64, qup17, _, _, _, _, _, _),
	1713	[65] = PINGROUP(65, tsense_pwm4, _, _, _, _, _, _),
	1714	[66] = PINGROUP(66, qup18, _, _, _, _, _, _),
	1715	[67] = PINGROUP(67, qup18, tsense_pwm3, _, _, _, _, _),
	1716	[68] = PINGROUP(68, qup18, emac1_mcg2, _, _, _, _, _),
	1717	[69] = PINGROUP(69, qup18, emac1_mcg3, tsense_pwm2, _, _, _, _),
	1718	[70] = PINGROUP(70, qup16, tsense_pwm1, _, _, _, _, _),
	1719	[71] = PINGROUP(71, qup16, atest_usb, _, _, _, _, _),
	1720	[72] = PINGROUP(72, qup16, atest_usb, _, _, _, _, _),
	1721	[73] = PINGROUP(73, qup16, atest_usb, _, _, _, _, _),
	1722	[74] = PINGROUP(74, qspi_clk, sdc4_clk, atest_usb, _, _, _, _),
	1723	[75] = PINGROUP(75, qspi_cs, sdc4_cmd, atest_usb, _, _, _, _),
	1724	[76] = PINGROUP(76, qspi, sdc40, atest_usb, _, _, _, _),
	1725	[77] = PINGROUP(77, _, _, _, _, _, _, _),
	1726	[78] = PINGROUP(78, qspi, sdc42, atest_usb, _, _, _, _),
	1727	[79] = PINGROUP(79, qspi, sdc43, atest_usb, ddr_pxi6, _, _, _),
	1728	[80] = PINGROUP(80, mi2s_mclk1, audio_ref, phase_flag, _, qdss_gpio, _, _),
	1729	[81] = PINGROUP(81, qup21, qspi_cs, phase_flag, _, vsense_trigger, _, _),
	1730	[82] = PINGROUP(82, qup21, phase_flag, _, _, _, _, _),
	1731	[83] = PINGROUP(83, qup21, qup22, phase_flag, _, _, _, _),
	1732	[84] = PINGROUP(84, qup21, qup22, pll_bist, pll_clk, _, _, _),
	1733	[85] = PINGROUP(85, qup22, _, _, _, _, _, _),
	1734	[86] = PINGROUP(86, qup22, _, pll_clk, _, _, _, _),
	1735	[87] = PINGROUP(87, qup20, phase_flag, _, _, _, _, _),
	1736	[88] = PINGROUP(88, qup20, phase_flag, _, _, _, _, _),
	1737	[89] = PINGROUP(89, qup20, phase_flag, _, _, _, _, _),
	1738	[90] = PINGROUP(90, qup20, phase_flag, _, _, _, _, _),
	1739	[91] = PINGROUP(91, qup20, hs2_mi2s, phase_flag, _, _, _, _),
	1740	[92] = PINGROUP(92, qup20, hs2_mi2s, phase_flag, _, _, _, _),
	1741	[93] = PINGROUP(93, mi2s0_sck, emac1_ptp, emac1_ptp, phase_flag, _, _, _),
	1742	[94] = PINGROUP(94, mi2s0_ws, emac1_ptp, emac1_ptp, phase_flag, _, _, _),
	1743	[95] = PINGROUP(95, mi2s0_data0, emac1_ptp, emac1_ptp, phase_flag, _, _, _),
	1744	[96] = PINGROUP(96, mi2s0_data1, emac1_ptp, emac1_ptp, qdss_gpio, _, _, _),
	1745	[97] = PINGROUP(97, rgmii_1, atest_usb, _, _, _, _, _),
	1746	[98] = PINGROUP(98, rgmii_1, atest_usb, _, _, _, _, _),
	1747	[99] = PINGROUP(99, rgmii_1, _, _, _, _, _, _),
	1748	[100] = PINGROUP(100, mdp_vsync, rgmii_1, _, _, _, _, _),
	1749	[101] = PINGROUP(101, mdp_vsync, rgmii_1, tgu, atest_usb, _, _, _),
	1750	[102] = PINGROUP(102, rgmii_1, tgu, atest_usb, _, _, _, _),
	1751	[103] = PINGROUP(103, rgmii_1, tgu, atest_usb, _, _, _, _),
	1752	[104] = PINGROUP(104, rgmii_1, tgu, atest_usb, _, _, _, _),
	1753	[105] = PINGROUP(105, rgmii_1, tgu, atest_usb, _, _, _, _),
	1754	[106] = PINGROUP(106, rgmii_1, tgu, _, _, _, _, _),
	1755	[107] = PINGROUP(107, rgmii_1, tgu, _, _, _, _, _),
	1756	[108] = PINGROUP(108, rgmii_1, tgu, _, _, _, _, _),
	1757	[109] = PINGROUP(109, rgmii_1, _, _, _, _, _, _),
	1758	[110] = PINGROUP(110, qup20, rgmii_1, atest_usb, _, _, _, _),
	1759	[111] = PINGROUP(111, qup4, qup5, atest_usb, _, _, _, _),
	1760	[112] = PINGROUP(112, qup4, qup5, atest_usb, _, _, _, _),
	1761	[113] = PINGROUP(113, cci_i2c, atest_usb, _, _, _, _, _),
	1762	[114] = PINGROUP(114, cci_i2c, gcc_gp2, atest_usb, _, _, _, _),
	1763	[115] = PINGROUP(115, cci_i2c, gcc_gp3, qdss_gpio, _, _, _, _),
	1764	[116] = PINGROUP(116, cci_i2c, qdss_gpio, _, _, _, _, _),
	1765	[117] = PINGROUP(117, cci_i2c, _, qdss_gpio, _, _, _, _),
	1766	[118] = PINGROUP(118, cci_i2c, _, qdss_gpio, _, _, _, _),
	1767	[119] = PINGROUP(119, cam_mclk, cci_timer0, cci_async, gcc_gp1, qdss_gpio, _, _),
	1768	[120] = PINGROUP(120, cam_mclk, cci_timer1, cci_async, gcc_gp2, qdss_gpio, ddr_pxi3, _),
	1769	[121] = PINGROUP(121, qup2, qdss_gpio, _, atest_usb, ddr_pxi0, _, _),
	1770	[122] = PINGROUP(122, qup2, qdss_gpio, atest_usb, _, _, _, _),
	1771	[123] = PINGROUP(123, qup2, cci_i2c, cmu_rng, ddr_pxi2, _, _, _),
	1772	[124] = PINGROUP(124, qup2, cci_i2c, cmu_rng, ddr_pxi1, _, _, _),
	1773	[125] = PINGROUP(125, qup7, dbg_out, ddr_pxi1, _, _, _, _),
	1774	[126] = PINGROUP(126, qup7, cmu_rng, ddr_pxi0, _, _, _, _),
	1775	[127] = PINGROUP(127, emac0_phy, _, _, _, _, _, _),
	1776	[128] = PINGROUP(128, qup7, ibi_i3c, _, _, _, _, _),
	1777	[129] = PINGROUP(129, qup7, ibi_i3c, _, _, _, _, _),
	1778	[130] = PINGROUP(130, emac0_ptp, emac0_ptp, sd_write, atest_usb, _, _, _),
	1779	[131] = PINGROUP(131, emac0_ptp, emac0_ptp, atest_usb, _, _, _, _),
	1780	[132] = PINGROUP(132, usb0_usb4, phase_flag, _, _, _, _, _),
	1781	[133] = PINGROUP(133, usb2phy_ac, _, _, _, _, _, _),
	1782	[134] = PINGROUP(134, usb2phy_ac, atest_char, _, _, _, _, _),
	1783	[135] = PINGROUP(135, qup0, qup3, _, atest_usb, ddr_pxi7, _, _),
	1784	[136] = PINGROUP(136, qup0, qup3, cmu_rng, ddr_pxi7, _, _, _),
	1785	[137] = PINGROUP(137, qup3, qup0, _, atest_usb, ddr_pxi3, _, _),
	1786	[138] = PINGROUP(138, qup3, qup0, _, atest_usb, ddr_pxi2, _, _),
	1787	[139] = PINGROUP(139, cci_timer5, gcc_gp3, atest_char, _, _, _, _),
	1788	[140] = PINGROUP(140, pcie4_clkreq, jitter_bist, atest_char, _, _, _, _),
	1789	[141] = PINGROUP(141, _, _, _, _, _, _, _),
	1790	[142] = PINGROUP(142, pcie2a_clkreq, atest_char, _, _, _, _, _),
	1791	[143] = PINGROUP(143, _, atest_char, _, _, _, _, _),
	1792	[144] = PINGROUP(144, pcie2b_clkreq, phase_flag, _, _, _, _, _),
	1793	[145] = PINGROUP(145, qup5, cci_i2c, phase_flag, _, _, _, _),
	1794	[146] = PINGROUP(146, qup5, cci_i2c, phase_flag, _, _, _, _),
	1795	[147] = PINGROUP(147, _, phase_flag, _, _, _, _, _),
	1796	[148] = PINGROUP(148, usb2phy_ac, _, atest_usb, _, _, _, _),
	1797	[149] = PINGROUP(149, usb2phy_ac, gcc_gp1, atest_usb, _, _, _, _),
	1798	[150] = PINGROUP(150, pcie3a_clkreq, _, _, _, _, _, _),
	1799	[151] = PINGROUP(151, _, _, _, _, _, _, _),
	1800	[152] = PINGROUP(152, pcie3b_clkreq, _, _, _, _, _, _),
	1801	[153] = PINGROUP(153, _, tb_trig, _, _, _, _, _),
	1802	[154] = PINGROUP(154, qup6, ibi_i3c, _, _, _, _, _),
	1803	[155] = PINGROUP(155, qup6, ibi_i3c, _, _, _, _, _),
	1804	[156] = PINGROUP(156, qup6, emac0_ptp, emac0_ptp, _, _, _, _),
	1805	[157] = PINGROUP(157, qup6, emac0_ptp, emac0_ptp, tb_trig, _, _, _),
	1806	[158] = PINGROUP(158, qup1, emac0_ptp, emac0_ptp, _, _, _, _),
	1807	[159] = PINGROUP(159, qup1, emac0_ptp, emac0_ptp, _, _, _, _),
	1808	[160] = PINGROUP(160, cci_timer9, qup1, cci_async, emac0_mcg0, gcc_gp4, _, _),
	1809	[161] = PINGROUP(161, cci_timer4, cci_async, qup1, emac0_mcg1, qdss_gpio, _, _),
	1810	[162] = PINGROUP(162, cci_timer6, emac0_mcg2, gcc_gp4, qdss_gpio, _, _, _),
	1811	[163] = PINGROUP(163, cci_timer7, emac0_mcg3, _, _, _, _, _),
	1812	[164] = PINGROUP(164, cci_i2c, _, _, _, _, _, _),
	1813	[165] = PINGROUP(165, cci_i2c, _, _, _, _, _, _),
	1814	[166] = PINGROUP(166, usb0_phy, _, _, _, _, _, _),
	1815	[167] = PINGROUP(167, cci_timer8, cci_async, gcc_gp5, _, _, _, _),
	1816	[168] = PINGROUP(168, usb0_sbtx, gcc_gp5, _, _, _, _, _),
	1817	[169] = PINGROUP(169, usb0_sbtx, _, _, _, _, _, _),
	1818	[170] = PINGROUP(170, usb0_sbrx, _, _, _, _, _, _),
	1819	[171] = PINGROUP(171, qup4, _, _, _, _, _, _),
	1820	[172] = PINGROUP(172, qup4, _, _, _, _, _, _),
	1821	[173] = PINGROUP(173, qup4, _, _, _, _, _, _),
	1822	[174] = PINGROUP(174, qup4, _, _, _, _, _, _),
	1823	[175] = PINGROUP(175, qup4, rgmii_0, _, _, _, _, _),
	1824	[176] = PINGROUP(176, rgmii_0, _, _, _, _, _, _),
	1825	[177] = PINGROUP(177, rgmii_0, _, _, _, _, _, _),
	1826	[178] = PINGROUP(178, rgmii_0, _, _, _, _, _, _),
	1827	[179] = PINGROUP(179, rgmii_0, _, _, _, _, _, _),
	1828	[180] = PINGROUP(180, rgmii_0, _, _, _, _, _, _),
	1829	[181] = PINGROUP(181, rgmii_0, _, _, _, _, _, _),
	1830	[182] = PINGROUP(182, rgmii_0, _, _, _, _, _, _),
	1831	[183] = PINGROUP(183, rgmii_0, _, _, _, _, _, _),
	1832	[184] = PINGROUP(184, rgmii_0, _, _, _, _, _, _),
	1833	[185] = PINGROUP(185, rgmii_0, _, _, _, _, _, _),
	1834	[186] = PINGROUP(186, rgmii_0, _, _, _, _, _, _),
	1835	[187] = PINGROUP(187, rgmii_0, cri_trng0, _, _, _, _, _),
	1836	[188] = PINGROUP(188, rgmii_0, cri_trng1, _, _, _, _, _),
	1837	[189] = PINGROUP(189, prng_rosc0, _, _, _, _, _, egpio),
	1838	[190] = PINGROUP(190, cri_trng, _, _, _, _, _, egpio),
	1839	[191] = PINGROUP(191, prng_rosc1, _, _, _, _, _, egpio),
	1840	[192] = PINGROUP(192, _, _, _, _, _, _, egpio),
	1841	[193] = PINGROUP(193, prng_rosc2, _, _, _, _, _, egpio),
	1842	[194] = PINGROUP(194, prng_rosc3, _, _, _, _, _, egpio),
	1843	[195] = PINGROUP(195, phase_flag, _, qdss_gpio, _, _, _, egpio),
	1844	[196] = PINGROUP(196, phase_flag, _, qdss_gpio, _, _, _, egpio),
	1845	[197] = PINGROUP(197, phase_flag, _, qdss_gpio, _, _, _, egpio),
	1846	[198] = PINGROUP(198, phase_flag, _, qdss_gpio, _, _, _, egpio),
	1847	[199] = PINGROUP(199, _, _, _, _, _, _, egpio),
	1848	[200] = PINGROUP(200, _, _, _, _, _, _, egpio),
	1849	[201] = PINGROUP(201, qdss_gpio, _, _, _, _, _, egpio),
	1850	[202] = PINGROUP(202, phase_flag, _, qdss_gpio, _, _, _, egpio),
	1851	[203] = PINGROUP(203, _, _, _, _, _, _, egpio),
	1852	[204] = PINGROUP(204, _, _, _, _, _, _, egpio),
	1853	[205] = PINGROUP(205, _, _, _, _, _, _, egpio),
	1854	[206] = PINGROUP(206, qdss_gpio, _, _, _, _, _, egpio),
	1855	[207] = PINGROUP(207, qdss_gpio, _, _, _, _, _, egpio),
	1856	[208] = PINGROUP(208, hs1_mi2s, _, _, _, _, _, egpio),
	1857	[209] = PINGROUP(209, hs1_mi2s, _, _, _, _, _, egpio),
	1858	[210] = PINGROUP(210, hs1_mi2s, _, _, _, _, _, egpio),
	1859	[211] = PINGROUP(211, hs1_mi2s, _, _, _, _, _, egpio),
	1860	[212] = PINGROUP(212, mi2s2_sck, qdss_gpio, _, _, _, _, egpio),
	1861	[213] = PINGROUP(213, mi2s2_ws, qdss_gpio, _, _, _, _, egpio),
	1862	[214] = PINGROUP(214, mi2s2_data0, qdss_gpio, ddr_pxi5, _, _, _, egpio),
	1863	[215] = PINGROUP(215, mi2s2_data1, qdss_gpio, emac1_dll0, ddr_pxi5, _, _, egpio),
	1864	[216] = PINGROUP(216, mi2s_mclk1, qdss_gpio, emac0_dll, ddr_pxi4, _, _, egpio),
	1865	[217] = PINGROUP(217, mi2s_mclk2, qdss_gpio, emac0_dll, ddr_pxi4, _, _, egpio),
	1866	[218] = PINGROUP(218, hs2_mi2s, emac1_dll1, ddr_pxi6, _, _, _, egpio),
	1867	[219] = PINGROUP(219, hs2_mi2s, phase_flag, _, _, _, _, egpio),
	1868	[220] = PINGROUP(220, lpass_slimbus, mi2s1_sck, phase_flag, _, _, _, egpio),
	1869	[221] = PINGROUP(221, lpass_slimbus, mi2s1_ws, phase_flag, _, _, _, egpio),
	1870	[222] = PINGROUP(222, mi2s1_data0, phase_flag, _, qdss_gpio, _, _, egpio),
	1871	[223] = PINGROUP(223, mi2s1_data1, phase_flag, _, qdss_gpio, _, _, egpio),
	1872	[224] = PINGROUP(224, hs3_mi2s, phase_flag, _, _, _, _, egpio),
	1873	[225] = PINGROUP(225, hs3_mi2s, phase_flag, _, _, _, _, egpio),
	1874	[226] = PINGROUP(226, hs3_mi2s, phase_flag, _, _, _, _, egpio),
	1875	[227] = PINGROUP(227, hs3_mi2s, phase_flag, _, _, _, _, egpio),
	1876	[228] = UFS_RESET(ufs_reset, 0xf1004),
	1877	[229] = UFS_RESET(ufs1_reset, 0xf3004),
	1878	[230] = SDC_QDSD_PINGROUP(sdc2_clk, 0xe8000, 14, 6),
	1879	[231] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xe8000, 11, 3),
	1880	[232] = SDC_QDSD_PINGROUP(sdc2_data, 0xe8000, 9, 0),
	1881	};
	1882
	1883	static const struct msm_gpio_wakeirq_map sc8280xp_pdc_map[] = {
	1884	{ 3, 245 }, { 4, 263 }, { 7, 254 }, { 21, 220 }, { 25, 244 },
	1885	{ 26, 211 }, { 27, 172 }, { 29, 203 }, { 30, 169 }, { 31, 180 },
	1886	{ 32, 181 }, { 33, 182 }, { 36, 206 }, { 39, 246 }, { 40, 183 },
	1887	{ 42, 179 }, { 46, 247 }, { 53, 248 }, { 54, 190 }, { 55, 249 },
	1888	{ 56, 250 }, { 58, 251 }, { 59, 207 }, { 62, 252 }, { 63, 191 },
	1889	{ 64, 192 }, { 65, 193 }, { 69, 253 }, { 73, 255 }, { 84, 256 },
	1890	{ 85, 208 }, { 90, 257 }, { 102, 214 }, { 103, 215 }, { 104, 216 },
	1891	{ 107, 217 }, { 110, 218 }, { 124, 224 }, { 125, 189 },
	1892	{ 126, 200 }, { 127, 225 }, { 128, 262 }, { 129, 201 },
	1893	{ 130, 209 }, { 131, 173 }, { 132, 202 }, { 136, 210 },
	1894	{ 138, 171 }, { 139, 226 }, { 140, 227 }, { 142, 228 },
	1895	{ 144, 229 }, { 145, 230 }, { 146, 231 }, { 148, 232 },
	1896	{ 149, 233 }, { 150, 234 }, { 152, 235 }, { 154, 212 },
	1897	{ 157, 213 }, { 161, 219 }, { 170, 236 }, { 171, 221 },
	1898	{ 174, 222 }, { 175, 237 }, { 176, 223 }, { 177, 170 },
	1899	{ 180, 238 }, { 181, 239 }, { 182, 240 }, { 183, 241 },
	1900	{ 184, 242 }, { 185, 243 }, { 190, 178 }, { 193, 184 },
	1901	{ 196, 185 }, { 198, 186 }, { 200, 174 }, { 201, 175 },
	1902	{ 205, 176 }, { 206, 177 }, { 208, 187 }, { 210, 198 },
	1903	{ 211, 199 }, { 212, 204 }, { 215, 205 }, { 220, 188 },
	1904	{ 221, 194 }, { 223, 195 }, { 225, 196 }, { 227, 197 },
	1905	};
	1906
	1907	static struct msm_pinctrl_soc_data sc8280xp_pinctrl = {
	1908	.pins = sc8280xp_pins,
	1909	.npins = ARRAY_SIZE(sc8280xp_pins),
	1910	.functions = sc8280xp_functions,
	1911	.nfunctions = ARRAY_SIZE(sc8280xp_functions),
	1912	.groups = sc8280xp_groups,
	1913	.ngroups = ARRAY_SIZE(sc8280xp_groups),
	1914	.ngpios = 230,
	1915	.wakeirq_map = sc8280xp_pdc_map,
	1916	.nwakeirq_map = ARRAY_SIZE(sc8280xp_pdc_map),
	1917	.egpio_func = 7,
	1918	};
	1919
	1920	static int sc8280xp_pinctrl_probe(struct platform_device *pdev)
	1921	{
	1922	return msm_pinctrl_probe(pdev, &sc8280xp_pinctrl);
	1923	}
	1924
	1925	static const struct of_device_id sc8280xp_pinctrl_of_match[] = {
	1926	{ .compatible = "qcom,sc8280xp-tlmm", },
	1927	{ },
	1928	};
	1929	MODULE_DEVICE_TABLE(of, sc8280xp_pinctrl_of_match);
	1930
	1931	static struct platform_driver sc8280xp_pinctrl_driver = {
	1932	.driver = {
	1933	.name = "sc8280xp-tlmm",
	1934	.of_match_table = sc8280xp_pinctrl_of_match,
	1935	},
	1936	.probe = sc8280xp_pinctrl_probe,
	1937	.remove = msm_pinctrl_remove,
	1938	};
	1939
	1940	static int __init sc8280xp_pinctrl_init(void)
	1941	{
	1942	return platform_driver_register(&sc8280xp_pinctrl_driver);
	1943	}
	1944	arch_initcall(sc8280xp_pinctrl_init);
	1945
	1946	static void __exit sc8280xp_pinctrl_exit(void)
	1947	{
	1948	platform_driver_unregister(&sc8280xp_pinctrl_driver);
	1949	}
	1950	module_exit(sc8280xp_pinctrl_exit);
	1951
	1952	MODULE_DESCRIPTION("Qualcomm SC8280XP TLMM pinctrl driver");
	1953	MODULE_LICENSE("GPL");

drivers/pinctrl/qcom/pinctrl-sm6125.c+1−1

@@ -1,4 +1,4 @@
1	//SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)	1	// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2		2
3	#include <linux/module.h>	3	#include <linux/module.h>
4	#include <linux/of.h>	4	#include <linux/of.h>

drivers/pinctrl/qcom/pinctrl-sm8450.c+61−45

@@ -46,6 +46,8 @@ · 45 unmodified lines
46	.mux_bit = 2, \	46	.mux_bit = 2, \
47	.pull_bit = 0, \	47	.pull_bit = 0, \
48	.drv_bit = 6, \	48	.drv_bit = 6, \
		49	.egpio_enable = 12, \
		50	.egpio_present = 11, \
49	.oe_bit = 9, \	51	.oe_bit = 9, \
50	.in_bit = 0, \	52	.in_bit = 0, \
51	.out_bit = 1, \	53	.out_bit = 1, \
@@ -567,6 +569,7 @@ enum sm8450_functions { · 515 unmodified lines
567	msm_mux_ddr_pxi2,	569	msm_mux_ddr_pxi2,
568	msm_mux_ddr_pxi3,	570	msm_mux_ddr_pxi3,
569	msm_mux_dp_hot,	571	msm_mux_dp_hot,
		572	msm_mux_egpio,
570	msm_mux_gcc_gp1,	573	msm_mux_gcc_gp1,
571	msm_mux_gcc_gp2,	574	msm_mux_gcc_gp2,
572	msm_mux_gcc_gp3,	575	msm_mux_gcc_gp3,
@@ -719,6 +722,17 @@ static const char * const gpio_groups[] = { · 146 unmodified lines
719	"gpio207", "gpio208", "gpio209",	722	"gpio207", "gpio208", "gpio209",
720	};	723	};
721		724
		725	static const char * const egpio_groups[] = {
		726	"gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170",
		727	"gpio171", "gpio172", "gpio173", "gpio174", "gpio175", "gpio176",
		728	"gpio177", "gpio178", "gpio179", "gpio180", "gpio181", "gpio182",
		729	"gpio183", "gpio184", "gpio185", "gpio186", "gpio187", "gpio188",
		730	"gpio189", "gpio190", "gpio191", "gpio192", "gpio193", "gpio194",
		731	"gpio195", "gpio196", "gpio197", "gpio198", "gpio199", "gpio200",
		732	"gpio201", "gpio202", "gpio203", "gpio204", "gpio205", "gpio206",
		733	"gpio207", "gpio208", "gpio209",
		734	};
		735
722	static const char * const aon_cam_groups[] = {	736	static const char * const aon_cam_groups[] = {
723	"gpio108",	737	"gpio108",
724	};	738	};
@@ -1285,6 +1299,7 @@ static const struct msm_function sm8450_functions[] = { · 560 unmodified lines
1285	FUNCTION(ddr_pxi2),	1299	FUNCTION(ddr_pxi2),
1286	FUNCTION(ddr_pxi3),	1300	FUNCTION(ddr_pxi3),
1287	FUNCTION(dp_hot),	1301	FUNCTION(dp_hot),
		1302	FUNCTION(egpio),
1288	FUNCTION(gcc_gp1),	1303	FUNCTION(gcc_gp1),
1289	FUNCTION(gcc_gp2),	1304	FUNCTION(gcc_gp2),
1290	FUNCTION(gcc_gp3),	1305	FUNCTION(gcc_gp3),
@@ -1571,51 +1586,51 @@ static const struct msm_pingroup sm8450_groups[] = { · 280 unmodified lines
1571	[162] = PINGROUP(162, qlink2_request, _, _, _, _, _, _, _, _),	1586	[162] = PINGROUP(162, qlink2_request, _, _, _, _, _, _, _, _),
1572	[163] = PINGROUP(163, qlink2_enable, _, _, _, _, _, _, _, _),	1587	[163] = PINGROUP(163, qlink2_enable, _, _, _, _, _, _, _, _),
1573	[164] = PINGROUP(164, qlink2_wmss, _, _, _, _, _, _, _, _),	1588	[164] = PINGROUP(164, qlink2_wmss, _, _, _, _, _, _, _, _),
1574	[165] = PINGROUP(165, _, _, _, _, _, _, _, _, _),	1589	[165] = PINGROUP(165, _, _, _, _, _, _, _, _, egpio),
1575	[166] = PINGROUP(166, _, _, _, _, _, _, _, _, _),	1590	[166] = PINGROUP(166, _, _, _, _, _, _, _, _, egpio),
1576	[167] = PINGROUP(167, _, _, _, _, _, _, _, _, _),	1591	[167] = PINGROUP(167, _, _, _, _, _, _, _, _, egpio),
1577	[168] = PINGROUP(168, _, _, _, _, _, _, _, _, _),	1592	[168] = PINGROUP(168, _, _, _, _, _, _, _, _, egpio),
1578	[169] = PINGROUP(169, _, _, _, _, _, _, _, _, _),	1593	[169] = PINGROUP(169, _, _, _, _, _, _, _, _, egpio),
1579	[170] = PINGROUP(170, _, _, _, _, _, _, _, _, _),	1594	[170] = PINGROUP(170, _, _, _, _, _, _, _, _, egpio),
1580	[171] = PINGROUP(171, _, _, _, _, _, _, _, _, _),	1595	[171] = PINGROUP(171, _, _, _, _, _, _, _, _, egpio),
1581	[172] = PINGROUP(172, _, _, _, _, _, _, _, _, _),	1596	[172] = PINGROUP(172, _, _, _, _, _, _, _, _, egpio),
1582	[173] = PINGROUP(173, _, _, _, _, _, _, _, _, _),	1597	[173] = PINGROUP(173, _, _, _, _, _, _, _, _, egpio),
1583	[174] = PINGROUP(174, _, _, _, _, _, _, _, _, _),	1598	[174] = PINGROUP(174, _, _, _, _, _, _, _, _, egpio),
1584	[175] = PINGROUP(175, _, _, _, _, _, _, _, _, _),	1599	[175] = PINGROUP(175, _, _, _, _, _, _, _, _, egpio),
1585	[176] = PINGROUP(176, _, _, _, _, _, _, _, _, _),	1600	[176] = PINGROUP(176, _, _, _, _, _, _, _, _, egpio),
1586	[177] = PINGROUP(177, _, _, _, _, _, _, _, _, _),	1601	[177] = PINGROUP(177, _, _, _, _, _, _, _, _, egpio),
1587	[178] = PINGROUP(178, _, _, _, _, _, _, _, _, _),	1602	[178] = PINGROUP(178, _, _, _, _, _, _, _, _, egpio),
1588	[179] = PINGROUP(179, _, _, _, _, _, _, _, _, _),	1603	[179] = PINGROUP(179, _, _, _, _, _, _, _, _, egpio),
1589	[180] = PINGROUP(180, _, _, _, _, _, _, _, _, _),	1604	[180] = PINGROUP(180, _, _, _, _, _, _, _, _, egpio),
1590	[181] = PINGROUP(181, _, _, _, _, _, _, _, _, _),	1605	[181] = PINGROUP(181, _, _, _, _, _, _, _, _, egpio),
1591	[182] = PINGROUP(182, _, _, _, _, _, _, _, _, _),	1606	[182] = PINGROUP(182, _, _, _, _, _, _, _, _, egpio),
1592	[183] = PINGROUP(183, _, _, _, _, _, _, _, _, _),	1607	[183] = PINGROUP(183, _, _, _, _, _, _, _, _, egpio),
1593	[184] = PINGROUP(184, _, _, _, _, _, _, _, _, _),	1608	[184] = PINGROUP(184, _, _, _, _, _, _, _, _, egpio),
1594	[185] = PINGROUP(185, _, _, _, _, _, _, _, _, _),	1609	[185] = PINGROUP(185, _, _, _, _, _, _, _, _, egpio),
1595	[186] = PINGROUP(186, _, _, _, _, _, _, _, _, _),	1610	[186] = PINGROUP(186, _, _, _, _, _, _, _, _, egpio),
1596	[187] = PINGROUP(187, _, _, _, _, _, _, _, _, _),	1611	[187] = PINGROUP(187, _, _, _, _, _, _, _, _, egpio),
1597	[188] = PINGROUP(188, _, qdss_gpio, _, _, _, _, _, _, _),	1612	[188] = PINGROUP(188, _, qdss_gpio, _, _, _, _, _, _, egpio),
1598	[189] = PINGROUP(189, _, qdss_gpio, _, _, _, _, _, _, _),	1613	[189] = PINGROUP(189, _, qdss_gpio, _, _, _, _, _, _, egpio),
1599	[190] = PINGROUP(190, qdss_gpio, _, _, _, _, _, _, _, _),	1614	[190] = PINGROUP(190, qdss_gpio, _, _, _, _, _, _, _, egpio),
1600	[191] = PINGROUP(191, qdss_gpio, _, _, _, _, _, _, _, _),	1615	[191] = PINGROUP(191, qdss_gpio, _, _, _, _, _, _, _, egpio),
1601	[192] = PINGROUP(192, _, qdss_gpio, _, _, _, _, _, _, _),	1616	[192] = PINGROUP(192, _, qdss_gpio, _, _, _, _, _, _, egpio),
1602	[193] = PINGROUP(193, _, qdss_gpio, _, _, _, _, _, _, _),	1617	[193] = PINGROUP(193, _, qdss_gpio, _, _, _, _, _, _, egpio),
1603	[194] = PINGROUP(194, _, qdss_gpio, _, _, _, _, _, _, _),	1618	[194] = PINGROUP(194, _, qdss_gpio, _, _, _, _, _, _, egpio),
1604	[195] = PINGROUP(195, _, qdss_gpio, _, _, _, _, _, _, _),	1619	[195] = PINGROUP(195, _, qdss_gpio, _, _, _, _, _, _, egpio),
1605	[196] = PINGROUP(196, _, qdss_gpio, _, _, _, _, _, _, _),	1620	[196] = PINGROUP(196, _, qdss_gpio, _, _, _, _, _, _, egpio),
1606	[197] = PINGROUP(197, _, qdss_gpio, _, _, _, _, _, _, _),	1621	[197] = PINGROUP(197, _, qdss_gpio, _, _, _, _, _, _, egpio),
1607	[198] = PINGROUP(198, _, qdss_gpio, _, _, _, _, _, _, _),	1622	[198] = PINGROUP(198, _, qdss_gpio, _, _, _, _, _, _, egpio),
1608	[199] = PINGROUP(199, _, qdss_gpio, _, _, _, _, _, _, _),	1623	[199] = PINGROUP(199, _, qdss_gpio, _, _, _, _, _, _, egpio),
1609	[200] = PINGROUP(200, _, qdss_gpio, _, _, _, _, _, _, _),	1624	[200] = PINGROUP(200, _, qdss_gpio, _, _, _, _, _, _, egpio),
1610	[201] = PINGROUP(201, _, qdss_gpio, _, _, _, _, _, _, _),	1625	[201] = PINGROUP(201, _, qdss_gpio, _, _, _, _, _, _, egpio),
1611	[202] = PINGROUP(202, qdss_gpio, _, _, _, _, _, _, _, _),	1626	[202] = PINGROUP(202, qdss_gpio, _, _, _, _, _, _, _, egpio),
1612	[203] = PINGROUP(203, qdss_gpio, _, _, _, _, _, _, _, _),	1627	[203] = PINGROUP(203, qdss_gpio, _, _, _, _, _, _, _, egpio),
1613	[204] = PINGROUP(204, qdss_gpio, _, _, _, _, _, _, _, _),	1628	[204] = PINGROUP(204, qdss_gpio, _, _, _, _, _, _, _, egpio),
1614	[205] = PINGROUP(205, qdss_gpio, _, _, _, _, _, _, _, _),	1629	[205] = PINGROUP(205, qdss_gpio, _, _, _, _, _, _, _, egpio),
1615	[206] = PINGROUP(206, qup5, _, _, _, _, _, _, _, _),	1630	[206] = PINGROUP(206, qup5, _, _, _, _, _, _, _, egpio),
1616	[207] = PINGROUP(207, qup5, _, _, _, _, _, _, _, _),	1631	[207] = PINGROUP(207, qup5, _, _, _, _, _, _, _, egpio),
1617	[208] = PINGROUP(208, cci_i2c, _, _, _, _, _, _, _, _),	1632	[208] = PINGROUP(208, cci_i2c, _, _, _, _, _, _, _, egpio),
1618	[209] = PINGROUP(209, cci_i2c, _, _, _, _, _, _, _, _),	1633	[209] = PINGROUP(209, cci_i2c, _, _, _, _, _, _, _, egpio),
1619	[210] = UFS_RESET(ufs_reset, 0xde000),	1634	[210] = UFS_RESET(ufs_reset, 0xde000),
1620	[211] = SDC_QDSD_PINGROUP(sdc2_clk, 0xd6000, 14, 6),	1635	[211] = SDC_QDSD_PINGROUP(sdc2_clk, 0xd6000, 14, 6),
1621	[212] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xd6000, 11, 3),	1636	[212] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xd6000, 11, 3),
@@ -1651,6 +1666,7 @@ static const struct msm_pinctrl_soc_data sm8450_tlmm = { · 29 unmodified lines
1651	.ngpios = 211,	1666	.ngpios = 211,
1652	.wakeirq_map = sm8450_pdc_map,	1667	.wakeirq_map = sm8450_pdc_map,
1653	.nwakeirq_map = ARRAY_SIZE(sm8450_pdc_map),	1668	.nwakeirq_map = ARRAY_SIZE(sm8450_pdc_map),
		1669	.egpio_func = 9,
1654	};	1670	};
1655		1671
1656	static int sm8450_tlmm_probe(struct platform_device *pdev)	1672	static int sm8450_tlmm_probe(struct platform_device *pdev)

drivers/pinctrl/qcom/pinctrl-spmi-gpio.c+1−0

@@ -1164,6 +1164,7 @@ static const struct of_device_id pmic_gpio_of_match[] = { · 1163 unmodified lines
1164	{ .compatible = "qcom,pm8350-gpio", .data = (void *) 10 },	1164	{ .compatible = "qcom,pm8350-gpio", .data = (void *) 10 },
1165	{ .compatible = "qcom,pm8350b-gpio", .data = (void *) 8 },	1165	{ .compatible = "qcom,pm8350b-gpio", .data = (void *) 8 },
1166	{ .compatible = "qcom,pm8350c-gpio", .data = (void *) 9 },	1166	{ .compatible = "qcom,pm8350c-gpio", .data = (void *) 9 },
		1167	{ .compatible = "qcom,pm8450-gpio", .data = (void *) 4 },
1167	{ .compatible = "qcom,pm8916-gpio", .data = (void *) 4 },	1168	{ .compatible = "qcom,pm8916-gpio", .data = (void *) 4 },
1168	{ .compatible = "qcom,pm8941-gpio", .data = (void *) 36 },	1169	{ .compatible = "qcom,pm8941-gpio", .data = (void *) 36 },
1169	/* pm8950 has 8 GPIOs with holes on 3 */	1170	/* pm8950 has 8 GPIOs with holes on 3 */

drivers/pinctrl/qcom/pinctrl-spmi-mpp.c+1−0

@@ -961,6 +961,7 @@ static int pmic_mpp_remove(struct platform_device *pdev) · 960 unmodified lines
961		961
962	static const struct of_device_id pmic_mpp_of_match[] = {	962	static const struct of_device_id pmic_mpp_of_match[] = {
963	{ .compatible = "qcom,pm8019-mpp", .data = (void *) 6 },	963	{ .compatible = "qcom,pm8019-mpp", .data = (void *) 6 },
		964	{ .compatible = "qcom,pm8226-mpp", .data = (void *) 8 },
964	{ .compatible = "qcom,pm8841-mpp", .data = (void *) 4 },	965	{ .compatible = "qcom,pm8841-mpp", .data = (void *) 4 },
965	{ .compatible = "qcom,pm8916-mpp", .data = (void *) 4 },	966	{ .compatible = "qcom,pm8916-mpp", .data = (void *) 4 },
966	{ .compatible = "qcom,pm8941-mpp", .data = (void *) 8 },	967	{ .compatible = "qcom,pm8941-mpp", .data = (void *) 8 },

drivers/pinctrl/renesas/Kconfig+9−2

 	select PINCTRL_PFC_R8A77990 if ARCH_R8A77990
 	select PINCTRL_PFC_R8A77995 if ARCH_R8A77995
 	select PINCTRL_PFC_R8A779A0 if ARCH_R8A779A0
+	select PINCTRL_PFC_R8A779F0 if ARCH_R8A779F0
 	select PINCTRL_RZG2L if ARCH_R9A07G044
+	select PINCTRL_RZG2L if ARCH_R9A07G054
 	select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203
 	select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264
 	select PINCTRL_PFC_SH7269 if CPU_SUBTYPE_SH7269
 	bool "pin control support for R-Car M3-W+" if COMPILE_TEST
 	select PINCTRL_SH_PFC
+config PINCTRL_PFC_R8A779F0
+	bool "pin control support for R-Car S4-8" if COMPILE_TEST
+	select PINCTRL_SH_PFC
 config PINCTRL_PFC_R8A7792
 	bool "pin control support for R-Car V2H" if COMPILE_TEST
 	select PINCTRL_SH_PFC
 	  This selects GPIO and pinctrl driver for Renesas RZ/A2 platforms.
 config PINCTRL_RZG2L
-	bool "pin control support for RZ/G2L" if COMPILE_TEST
+	bool "pin control support for RZ/{G2L,V2L}" if COMPILE_TEST
 	depends on OF
 	select GPIOLIB
 	select GENERIC_PINCTRL_GROUPS
 	select GENERIC_PINMUX_FUNCTIONS
 	select GENERIC_PINCONF
 	help
-	  This selects GPIO and pinctrl driver for Renesas RZ/G2L platforms.
+	  This selects GPIO and pinctrl driver for Renesas RZ/{G2L,V2L}
+	  platforms.
 config PINCTRL_PFC_R8A77470
 	bool "pin control support for RZ/G1C" if COMPILE_TEST

drivers/pinctrl/renesas/Makefile+1−0

@@ -30,6 +30,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A77980) += pfc-r8a77980.o · 29 unmodified lines
30	obj-$(CONFIG_PINCTRL_PFC_R8A77990) += pfc-r8a77990.o	30	obj-$(CONFIG_PINCTRL_PFC_R8A77990) += pfc-r8a77990.o
31	obj-$(CONFIG_PINCTRL_PFC_R8A77995) += pfc-r8a77995.o	31	obj-$(CONFIG_PINCTRL_PFC_R8A77995) += pfc-r8a77995.o
32	obj-$(CONFIG_PINCTRL_PFC_R8A779A0) += pfc-r8a779a0.o	32	obj-$(CONFIG_PINCTRL_PFC_R8A779A0) += pfc-r8a779a0.o
		33	obj-$(CONFIG_PINCTRL_PFC_R8A779F0) += pfc-r8a779f0.o
33	obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o	34	obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o
34	obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o	35	obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o
35	obj-$(CONFIG_PINCTRL_PFC_SH7269) += pfc-sh7269.o	36	obj-$(CONFIG_PINCTRL_PFC_SH7269) += pfc-sh7269.o

drivers/pinctrl/renesas/core.c+199−20

@@ -636,6 +636,12 @@ static const struct of_device_id sh_pfc_of_table[] = { · 635 unmodified lines
636	.data = &r8a779a0_pinmux_info,	636	.data = &r8a779a0_pinmux_info,
637	},	637	},
638	#endif	638	#endif
		639	#ifdef CONFIG_PINCTRL_PFC_R8A779F0
		640	{
		641	.compatible = "renesas,pfc-r8a779f0",
		642	.data = &r8a779f0_pinmux_info,
		643	},
		644	#endif
639	#ifdef CONFIG_PINCTRL_PFC_SH73A0	645	#ifdef CONFIG_PINCTRL_PFC_SH73A0
640	{	646	{
641	.compatible = "renesas,pfc-sh73a0",	647	.compatible = "renesas,pfc-sh73a0",
@@ -741,10 +747,13 @@ static int sh_pfc_suspend_init(struct sh_pfc *pfc) { return 0; } · 99 unmodified lines
741		747
742	#ifdef DEBUG	748	#ifdef DEBUG
743	#define SH_PFC_MAX_REGS 300	749	#define SH_PFC_MAX_REGS 300
744	#define SH_PFC_MAX_ENUMS 3000	750	#define SH_PFC_MAX_ENUMS 5000
745		751
746	static unsigned int sh_pfc_errors __initdata;	752	static unsigned int sh_pfc_errors __initdata;
747	static unsigned int sh_pfc_warnings __initdata;	753	static unsigned int sh_pfc_warnings __initdata;
		754	static bool sh_pfc_bias_done __initdata;
		755	static bool sh_pfc_drive_done __initdata;
		756	static bool sh_pfc_power_done __initdata;
748	static struct {	757	static struct {
749	u32 reg;	758	u32 reg;
750	u32 bits;	759	u32 bits;
@@ -758,6 +767,15 @@ static u32 sh_pfc_num_enums __initdata; · 7 unmodified lines
758	pr_err("%s: " fmt, drvname, ##__VA_ARGS__); \	767	pr_err("%s: " fmt, drvname, ##__VA_ARGS__); \
759	sh_pfc_errors++; \	768	sh_pfc_errors++; \
760	} while (0)	769	} while (0)
		770
		771	#define sh_pfc_err_once(type, fmt, ...) \
		772	do { \
		773	if (!sh_pfc_ ## type ## _done) { \
		774	sh_pfc_ ## type ## _done = true; \
		775	sh_pfc_err(fmt, ##__VA_ARGS__); \
		776	} \
		777	} while (0)
		778
761	#define sh_pfc_warn(fmt, ...) \	779	#define sh_pfc_warn(fmt, ...) \
762	do { \	780	do { \
763	pr_warn("%s: " fmt, drvname, ##__VA_ARGS__); \	781	pr_warn("%s: " fmt, drvname, ##__VA_ARGS__); \
@@ -777,10 +795,7 @@ static bool __init is0s(const u16 *enum_ids, unsigned int n) · 13 unmodified lines
777		795
778	static bool __init same_name(const char a, const char b)	796	static bool __init same_name(const char a, const char b)
779	{	797	{
780	if (!a \|\| !b)	798	return a && b && !strcmp(a, b);
781	return false;
782
783	return !strcmp(a, b);
784	}	799	}
785		800
786	static void __init sh_pfc_check_reg(const char *drvname, u32 reg, u32 bits)	801	static void __init sh_pfc_check_reg(const char *drvname, u32 reg, u32 bits)
@@ -839,21 +854,22 @@ static void __init sh_pfc_check_reg_enums(const char *drvname, u32 reg, · 52 unmodified lines
839	}	854	}
840	}	855	}
841		856
842	static void __init sh_pfc_check_pin(const struct sh_pfc_soc_info *info,	857	static const struct sh_pfc_pin __init *sh_pfc_find_pin(
843	u32 reg, unsigned int pin)	858	const struct sh_pfc_soc_info *info, u32 reg, unsigned int pin)
844	{	859	{
845	const char *drvname = info->name;	860	const char *drvname = info->name;
846	unsigned int i;	861	unsigned int i;
847		862
848	if (pin == SH_PFC_PIN_NONE)	863	if (pin == SH_PFC_PIN_NONE)
849	return;	864	return NULL;
850		865
851	for (i = 0; i < info->nr_pins; i++) {	866	for (i = 0; i < info->nr_pins; i++) {
852	if (pin == info->pins[i].pin)	867	if (pin == info->pins[i].pin)
853	return;	868	return &info->pins[i];
854	}	869	}
855		870
856	sh_pfc_err("reg 0x%x: pin %u not found\n", reg, pin);	871	sh_pfc_err("reg 0x%x: pin %u not found\n", reg, pin);
		872	return NULL;
857	}	873	}
858		874
859	static void __init sh_pfc_check_cfg_reg(const char *drvname,	875	static void __init sh_pfc_check_cfg_reg(const char *drvname,
@@ -865,7 +881,8 @@ static void __init sh_pfc_check_cfg_reg(const char *drvname, · 5 unmodified lines
865	GENMASK(cfg_reg->reg_width - 1, 0));	881	GENMASK(cfg_reg->reg_width - 1, 0));
866		882
867	if (cfg_reg->field_width) {	883	if (cfg_reg->field_width) {
868	n = cfg_reg->reg_width / cfg_reg->field_width;	884	fw = cfg_reg->field_width;
		885	n = (cfg_reg->reg_width / fw) << fw;
869	/* Skip field checks (done at build time) */	886	/* Skip field checks (done at build time) */
870	goto check_enum_ids;	887	goto check_enum_ids;
871	}	888	}
@@ -893,6 +910,8 @@ check_enum_ids: · 21 unmodified lines
893	static void __init sh_pfc_check_drive_reg(const struct sh_pfc_soc_info *info,	910	static void __init sh_pfc_check_drive_reg(const struct sh_pfc_soc_info *info,
894	const struct pinmux_drive_reg *drive)	911	const struct pinmux_drive_reg *drive)
895	{	912	{
		913	const char *drvname = info->name;
		914	const struct sh_pfc_pin *pin;
896	unsigned int i;	915	unsigned int i;
897		916
898	for (i = 0; i < ARRAY_SIZE(drive->fields); i++) {	917	for (i = 0; i < ARRAY_SIZE(drive->fields); i++) {
@@ -905,13 +924,18 @@ static void __init sh_pfc_check_drive_reg(const struct sh_pfc_soc_info *info, · 6 unmodified lines
905	GENMASK(field->offset + field->size - 1,	924	GENMASK(field->offset + field->size - 1,
906	field->offset));	925	field->offset));
907		926
908	sh_pfc_check_pin(info, drive->reg, field->pin);	927	pin = sh_pfc_find_pin(info, drive->reg, field->pin);
		928	if (pin && !(pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH))
		929	sh_pfc_err("drive_reg 0x%x: field %u: pin %s lacks SH_PFC_PIN_CFG_DRIVE_STRENGTH flag\n",
		930	drive->reg, i, pin->name);
909	}	931	}
910	}	932	}
911		933
912	static void __init sh_pfc_check_bias_reg(const struct sh_pfc_soc_info *info,	934	static void __init sh_pfc_check_bias_reg(const struct sh_pfc_soc_info *info,
913	const struct pinmux_bias_reg *bias)	935	const struct pinmux_bias_reg *bias)
914	{	936	{
		937	const char *drvname = info->name;
		938	const struct sh_pfc_pin *pin;
915	unsigned int i;	939	unsigned int i;
916	u32 bits;	940	u32 bits;
917		941
@@ -923,12 +947,66 @@ static void __init sh_pfc_check_bias_reg(const struct sh_pfc_soc_info *info, · 5 unmodified lines
923	sh_pfc_check_reg(info->name, bias->puen, bits);	947	sh_pfc_check_reg(info->name, bias->puen, bits);
924	if (bias->pud)	948	if (bias->pud)
925	sh_pfc_check_reg(info->name, bias->pud, bits);	949	sh_pfc_check_reg(info->name, bias->pud, bits);
926	for (i = 0; i < ARRAY_SIZE(bias->pins); i++)	950	for (i = 0; i < ARRAY_SIZE(bias->pins); i++) {
927	sh_pfc_check_pin(info, bias->puen, bias->pins[i]);	951	pin = sh_pfc_find_pin(info, bias->puen, bias->pins[i]);
		952	if (!pin)
		953	continue;
		954
		955	if (bias->puen && bias->pud) {
		956	/*
		957	* Pull-enable and pull-up/down control registers
		958	* As some SoCs have pins that support only pull-up
		959	* or pull-down, we just check for one of them
		960	*/
		961	if (!(pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN))
		962	sh_pfc_err("bias_reg 0x%x:%u: pin %s lacks one or more SH_PFC_PIN_CFG_PULL_* flags\n",
		963	bias->puen, i, pin->name);
		964	} else if (bias->puen) {
		965	/* Pull-up control register only */
		966	if (!(pin->configs & SH_PFC_PIN_CFG_PULL_UP))
		967	sh_pfc_err("bias_reg 0x%x:%u: pin %s lacks SH_PFC_PIN_CFG_PULL_UP flag\n",
		968	bias->puen, i, pin->name);
		969	} else if (bias->pud) {
		970	/* Pull-down control register only */
		971	if (!(pin->configs & SH_PFC_PIN_CFG_PULL_DOWN))
		972	sh_pfc_err("bias_reg 0x%x:%u: pin %s lacks SH_PFC_PIN_CFG_PULL_DOWN flag\n",
		973	bias->pud, i, pin->name);
		974	}
		975	}
		976	}
		977
		978	static void __init sh_pfc_compare_groups(const char *drvname,
		979	const struct sh_pfc_pin_group *a,
		980	const struct sh_pfc_pin_group *b)
		981	{
		982	unsigned int i;
		983	size_t len;
		984
		985	if (same_name(a->name, b->name))
		986	sh_pfc_err("group %s: name conflict\n", a->name);
		987
		988	if (a->nr_pins > b->nr_pins)
		989	swap(a, b);
		990
		991	len = a->nr_pins * sizeof(a->pins[0]);
		992	for (i = 0; i <= b->nr_pins - a->nr_pins; i++) {
		993	if (a->pins == b->pins + i \|\| a->mux == b->mux + i \|\|
		994	memcmp(a->pins, b->pins + i, len) \|\|
		995	memcmp(a->mux, b->mux + i, len))
		996	continue;
		997
		998	if (a->nr_pins == b->nr_pins)
		999	sh_pfc_warn("group %s can be an alias for %s\n",
		1000	a->name, b->name);
		1001	else
		1002	sh_pfc_warn("group %s is a subset of %s\n", a->name,
		1003	b->name);
		1004	}
928	}	1005	}
929		1006
930	static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info)	1007	static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info)
931	{	1008	{
		1009	const struct pinmux_drive_reg *drive_regs = info->drive_regs;
932	const struct pinmux_bias_reg *bias_regs = info->bias_regs;	1010	const struct pinmux_bias_reg *bias_regs = info->bias_regs;
933	const char *drvname = info->name;	1011	const char *drvname = info->name;
934	unsigned int *refcnts;	1012	unsigned int *refcnts;
@@ -937,10 +1015,14 @@ static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info) · 2 unmodified lines
937	pr_info("sh_pfc: Checking %s\n", drvname);	1015	pr_info("sh_pfc: Checking %s\n", drvname);
938	sh_pfc_num_regs = 0;	1016	sh_pfc_num_regs = 0;
939	sh_pfc_num_enums = 0;	1017	sh_pfc_num_enums = 0;
		1018	sh_pfc_bias_done = false;
		1019	sh_pfc_drive_done = false;
		1020	sh_pfc_power_done = false;
940		1021
941	/* Check pins */	1022	/* Check pins */
942	for (i = 0; i < info->nr_pins; i++) {	1023	for (i = 0; i < info->nr_pins; i++) {
943	const struct sh_pfc_pin *pin = &info->pins[i];	1024	const struct sh_pfc_pin *pin = &info->pins[i];
		1025	unsigned int x;
944		1026
945	if (!pin->name) {	1027	if (!pin->name) {
946	sh_pfc_err("empty pin %u\n", i);	1028	sh_pfc_err("empty pin %u\n", i);
@@ -962,6 +1044,65 @@ static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info) · 15 unmodified lines
962	pin->name, pin2->name,	1044	pin->name, pin2->name,
963	pin->enum_id);	1045	pin->enum_id);
964	}	1046	}
		1047
		1048	if (pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN) {
		1049	if (!info->ops \|\| !info->ops->get_bias \|\|
		1050	!info->ops->set_bias)
		1051	sh_pfc_err_once(bias, "SH_PFC_PIN_CFG_PULL_* flag set but .[gs]et_bias() not implemented\n");
		1052
		1053	if (!bias_regs &&
		1054	(!info->ops \|\| !info->ops->pin_to_portcr))
		1055	sh_pfc_err_once(bias, "SH_PFC_PIN_CFG_PULL_UP flag set but no bias_regs defined and .pin_to_portcr() not implemented\n");
		1056	}
		1057
		1058	if ((pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN) && bias_regs) {
		1059	const struct pinmux_bias_reg *bias_reg =
		1060	rcar_pin_to_bias_reg(info, pin->pin, &x);
		1061
		1062	if (!bias_reg \|\|
		1063	((pin->configs & SH_PFC_PIN_CFG_PULL_UP) &&
		1064	!bias_reg->puen))
		1065	sh_pfc_err("pin %s: SH_PFC_PIN_CFG_PULL_UP flag set but pin not in bias_regs\n",
		1066	pin->name);
		1067
		1068	if (!bias_reg \|\|
		1069	((pin->configs & SH_PFC_PIN_CFG_PULL_DOWN) &&
		1070	!bias_reg->pud))
		1071	sh_pfc_err("pin %s: SH_PFC_PIN_CFG_PULL_DOWN flag set but pin not in bias_regs\n",
		1072	pin->name);
		1073	}
		1074
		1075	if (pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH) {
		1076	if (!drive_regs) {
		1077	sh_pfc_err_once(drive, "SH_PFC_PIN_CFG_DRIVE_STRENGTH flag set but drive_regs missing\n");
		1078	} else {
		1079	for (j = 0; drive_regs[j / 8].reg; j++) {
		1080	if (!drive_regs[j / 8].fields[j % 8].pin &&
		1081	!drive_regs[j / 8].fields[j % 8].offset &&
		1082	!drive_regs[j / 8].fields[j % 8].size)
		1083	continue;
		1084
		1085	if (drive_regs[j / 8].fields[j % 8].pin == pin->pin)
		1086	break;
		1087	}
		1088
		1089	if (!drive_regs[j / 8].reg)
		1090	sh_pfc_err("pin %s: SH_PFC_PIN_CFG_DRIVE_STRENGTH flag set but not in drive_regs\n",
		1091	pin->name);
		1092	}
		1093	}
		1094
		1095	if (pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE) {
		1096	if (!info->ops \|\| !info->ops->pin_to_pocctrl)
		1097	sh_pfc_err_once(power, "SH_PFC_PIN_CFG_IO_VOLTAGE flag set but .pin_to_pocctrl() not implemented\n");
		1098	else if (info->ops->pin_to_pocctrl(pin->pin, &x) < 0)
		1099	sh_pfc_err("pin %s: SH_PFC_PIN_CFG_IO_VOLTAGE set but invalid pin_to_pocctrl()\n",
		1100	pin->name);
		1101	} else if (info->ops && info->ops->pin_to_pocctrl &&
		1102	info->ops->pin_to_pocctrl(pin->pin, &x) >= 0) {
		1103	sh_pfc_warn("pin %s: SH_PFC_PIN_CFG_IO_VOLTAGE not set but valid pin_to_pocctrl()\n",
		1104	pin->name);
		1105	}
965	}	1106	}
966		1107
967	/* Check groups and functions */	1108	/* Check groups and functions */
@@ -1003,11 +1144,9 @@ static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info) · 35 unmodified lines
1003	sh_pfc_err("empty group %u\n", i);	1144	sh_pfc_err("empty group %u\n", i);
1004	continue;	1145	continue;
1005	}	1146	}
1006	for (j = 0; j < i; j++) {	1147	for (j = 0; j < i; j++)
1007	if (same_name(group->name, info->groups[j].name))	1148	sh_pfc_compare_groups(drvname, group, &info->groups[j]);
1008	sh_pfc_err("group %s: name conflict\n",	1149
1009	group->name);
1010	}
1011	if (!refcnts[i])	1150	if (!refcnts[i])
1012	sh_pfc_err("orphan group %s\n", group->name);	1151	sh_pfc_err("orphan group %s\n", group->name);
1013	else if (refcnts[i] > 1)	1152	else if (refcnts[i] > 1)
@@ -1022,13 +1161,53 @@ static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info) · 8 unmodified lines
1022	sh_pfc_check_cfg_reg(drvname, &info->cfg_regs[i]);	1161	sh_pfc_check_cfg_reg(drvname, &info->cfg_regs[i]);
1023		1162
1024	/* Check drive strength registers */	1163	/* Check drive strength registers */
1025	for (i = 0; info->drive_regs && info->drive_regs[i].reg; i++)	1164	for (i = 0; drive_regs && drive_regs[i].reg; i++)
1026	sh_pfc_check_drive_reg(info, &info->drive_regs[i]);	1165	sh_pfc_check_drive_reg(info, &drive_regs[i]);
		1166
		1167	for (i = 0; drive_regs && drive_regs[i / 8].reg; i++) {
		1168	if (!drive_regs[i / 8].fields[i % 8].pin &&
		1169	!drive_regs[i / 8].fields[i % 8].offset &&
		1170	!drive_regs[i / 8].fields[i % 8].size)
		1171	continue;
		1172
		1173	for (j = 0; j < i; j++) {
		1174	if (drive_regs[i / 8].fields[i % 8].pin ==
		1175	drive_regs[j / 8].fields[j % 8].pin &&
		1176	drive_regs[j / 8].fields[j % 8].offset &&
		1177	drive_regs[j / 8].fields[j % 8].size) {
		1178	sh_pfc_err("drive_reg 0x%x:%u/0x%x:%u: pin conflict\n",
		1179	drive_regs[i / 8].reg, i % 8,
		1180	drive_regs[j / 8].reg, j % 8);
		1181	}
		1182	}
		1183	}
1027		1184
1028	/* Check bias registers */	1185	/* Check bias registers */
1029	for (i = 0; bias_regs && (bias_regs[i].puen \|\| bias_regs[i].pud); i++)	1186	for (i = 0; bias_regs && (bias_regs[i].puen \|\| bias_regs[i].pud); i++)
1030	sh_pfc_check_bias_reg(info, &bias_regs[i]);	1187	sh_pfc_check_bias_reg(info, &bias_regs[i]);
1031		1188
		1189	for (i = 0; bias_regs &&
		1190	(bias_regs[i / 32].puen \|\| bias_regs[i / 32].pud); i++) {
		1191	if (bias_regs[i / 32].pins[i % 32] == SH_PFC_PIN_NONE)
		1192	continue;
		1193
		1194	for (j = 0; j < i; j++) {
		1195	if (bias_regs[i / 32].pins[i % 32] !=
		1196	bias_regs[j / 32].pins[j % 32])
		1197	continue;
		1198
		1199	if (bias_regs[i / 32].puen && bias_regs[j / 32].puen)
		1200	sh_pfc_err("bias_reg 0x%x:%u/0x%x:%u: pin conflict\n",
		1201	bias_regs[i / 32].puen, i % 32,
		1202	bias_regs[j / 32].puen, j % 32);
		1203	if (bias_regs[i / 32].pud && bias_regs[j / 32].pud)
		1204	sh_pfc_err("bias_reg 0x%x:%u/0x%x:%u: pin conflict\n",
		1205	bias_regs[i / 32].pud, i % 32,
		1206	bias_regs[j / 32].pud, j % 32);
		1207	}
		1208
		1209	}
		1210
1032	/* Check ioctrl registers */	1211	/* Check ioctrl registers */
1033	for (i = 0; info->ioctrl_regs && info->ioctrl_regs[i].reg; i++)	1212	for (i = 0; info->ioctrl_regs && info->ioctrl_regs[i].reg; i++)
1034	sh_pfc_check_reg(drvname, info->ioctrl_regs[i].reg, U32_MAX);	1213	sh_pfc_check_reg(drvname, info->ioctrl_regs[i].reg, U32_MAX);

drivers/pinctrl/renesas/pfc-emev2.c+17−54

 	CF_CDB2_MARK,
 };
-static const unsigned int cf_data8_pins[] = {
+static const unsigned int cf_data_pins[] = {
-	/* CF_D[0:7] */
-	77, 78, 79, 80,
-	81, 82, 83, 84,
-};
-static const unsigned int cf_data8_mux[] = {
-	CF_D00_MARK, CF_D01_MARK, CF_D02_MARK, CF_D03_MARK,
-	CF_D04_MARK, CF_D05_MARK, CF_D06_MARK, CF_D07_MARK,
-};
-static const unsigned int cf_data16_pins[] = {
 	/* CF_D[0:15] */
 	77, 78, 79, 80,
 	81, 82, 83, 84,
 	85, 86, 87, 88,
 	89, 90, 91, 92,
 };
-static const unsigned int cf_data16_mux[] = {
+static const unsigned int cf_data_mux[] = {
 	CF_D00_MARK, CF_D01_MARK, CF_D02_MARK, CF_D03_MARK,
 	CF_D04_MARK, CF_D05_MARK, CF_D06_MARK, CF_D07_MARK,
 	CF_D08_MARK, CF_D09_MARK, CF_D10_MARK, CF_D11_MARK,
 	SDI0_CKO_MARK, SDI0_CKI_MARK, SDI0_CMD_MARK,
 };
-static const unsigned int sdi0_data1_pins[] = {
+static const unsigned int sdi0_data_pins[] = {
-	/* SDI0_DATA[0] */
-	53,
-};
-static const unsigned int sdi0_data1_mux[] = {
-	SDI0_DATA0_MARK,
-};
-static const unsigned int sdi0_data4_pins[] = {
-	/* SDI0_DATA[0:3] */
-	53, 54, 55, 56,
-};
-static const unsigned int sdi0_data4_mux[] = {
-	SDI0_DATA0_MARK, SDI0_DATA1_MARK, SDI0_DATA2_MARK, SDI0_DATA3_MARK,
-};
-static const unsigned int sdi0_data8_pins[] = {
 	/* SDI0_DATA[0:7] */
 	53, 54, 55, 56,
 	57, 58, 59, 60
 };
-static const unsigned int sdi0_data8_mux[] = {
+static const unsigned int sdi0_data_mux[] = {
 	SDI0_DATA0_MARK, SDI0_DATA1_MARK, SDI0_DATA2_MARK, SDI0_DATA3_MARK,
 	SDI0_DATA4_MARK, SDI0_DATA5_MARK, SDI0_DATA6_MARK, SDI0_DATA7_MARK,
 };
 	SDI1_CKO_MARK, SDI1_CKI_MARK, SDI1_CMD_MARK,
 };
-static const unsigned int sdi1_data1_pins[] = {
+static const unsigned int sdi1_data_pins[] = {
-	/* SDI1_DATA[0] */
-	64,
-};
-static const unsigned int sdi1_data1_mux[] = {
-	SDI1_DATA0_MARK,
-};
-static const unsigned int sdi1_data4_pins[] = {
 	/* SDI1_DATA[0:3] */
 	64, 65, 66, 67,
 };
-static const unsigned int sdi1_data4_mux[] = {
+static const unsigned int sdi1_data_mux[] = {
 	SDI1_DATA0_MARK, SDI1_DATA1_MARK, SDI1_DATA2_MARK, SDI1_DATA3_MARK,
 };
 	SDI2_CKO_MARK, SDI2_CKI_MARK, SDI2_CMD_MARK,
 };
-static const unsigned int sdi2_data1_pins[] = {
+static const unsigned int sdi2_data_pins[] = {
-	/* SDI2_DATA[0] */
-	89,
-};
-static const unsigned int sdi2_data1_mux[] = {
-	SDI2_DATA0_MARK,
-};
-static const unsigned int sdi2_data4_pins[] = {
 	/* SDI2_DATA[0:3] */
 	89, 90, 91, 92,
 };
-static const unsigned int sdi2_data4_mux[] = {
+static const unsigned int sdi2_data_mux[] = {
 	SDI2_DATA0_MARK, SDI2_DATA1_MARK, SDI2_DATA2_MARK, SDI2_DATA3_MARK,
 };
 	SH_PFC_PIN_GROUP(cam),
 	SH_PFC_PIN_GROUP(cf_ctrl),
-	SH_PFC_PIN_GROUP(cf_data8),
+	BUS_DATA_PIN_GROUP(cf_data, 8),
-	SH_PFC_PIN_GROUP(cf_data16),
+	BUS_DATA_PIN_GROUP(cf_data, 16),
 	SH_PFC_PIN_GROUP(dtv_a),
 	SH_PFC_PIN_GROUP(dtv_b),
 	SH_PFC_PIN_GROUP(sd_cki),
 	SH_PFC_PIN_GROUP(sdi0_ctrl),
-	SH_PFC_PIN_GROUP(sdi0_data1),
+	BUS_DATA_PIN_GROUP(sdi0_data, 1),
-	SH_PFC_PIN_GROUP(sdi0_data4),
+	BUS_DATA_PIN_GROUP(sdi0_data, 4),
-	SH_PFC_PIN_GROUP(sdi0_data8),
+	BUS_DATA_PIN_GROUP(sdi0_data, 8),
 	SH_PFC_PIN_GROUP(sdi1_ctrl),
-	SH_PFC_PIN_GROUP(sdi1_data1),
+	BUS_DATA_PIN_GROUP(sdi1_data, 1),
-	SH_PFC_PIN_GROUP(sdi1_data4),
+	BUS_DATA_PIN_GROUP(sdi1_data, 4),
 	SH_PFC_PIN_GROUP(sdi2_ctrl),
-	SH_PFC_PIN_GROUP(sdi2_data1),
+	BUS_DATA_PIN_GROUP(sdi2_data, 1),
-	SH_PFC_PIN_GROUP(sdi2_data4),
+	BUS_DATA_PIN_GROUP(sdi2_data, 4),
 	SH_PFC_PIN_GROUP(tp33),

drivers/pinctrl/renesas/pfc-r8a73a4.c+24−73

 IRQC_PINS_MUX(328, 56);
 IRQC_PINS_MUX(329, 57);
 /* - MMCIF0 ----------------------------------------------------------------- */
-static const unsigned int mmc0_data1_pins[] = {
+static const unsigned int mmc0_data_pins[] = {
-	/* D[0] */
-	164,
-};
-static const unsigned int mmc0_data1_mux[] = {
-	MMCD0_0_MARK,
-};
-static const unsigned int mmc0_data4_pins[] = {
-	/* D[0:3] */
-	164, 165, 166, 167,
-};
-static const unsigned int mmc0_data4_mux[] = {
-	MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
-};
-static const unsigned int mmc0_data8_pins[] = {
 	/* D[0:7] */
 	164, 165, 166, 167, 168, 169, 170, 171,
 };
-static const unsigned int mmc0_data8_mux[] = {
+static const unsigned int mmc0_data_mux[] = {
 	MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
 	MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK,
 };
 	MMCCMD0_MARK, MMCCLK0_MARK,
 };
 /* - MMCIF1 ----------------------------------------------------------------- */
-static const unsigned int mmc1_data1_pins[] = {
+static const unsigned int mmc1_data_pins[] = {
-	/* D[0] */
-	199,
-};
-static const unsigned int mmc1_data1_mux[] = {
-	MMCD1_0_MARK,
-};
-static const unsigned int mmc1_data4_pins[] = {
-	/* D[0:3] */
-	199, 198, 197, 196,
-};
-static const unsigned int mmc1_data4_mux[] = {
-	MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
-};
-static const unsigned int mmc1_data8_pins[] = {
 	/* D[0:7] */
 	199, 198, 197, 196, 195, 194, 193, 192,
 };
-static const unsigned int mmc1_data8_mux[] = {
+static const unsigned int mmc1_data_mux[] = {
 	MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
 	MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK,
 };
 	SCIFB3_RTS_38_MARK, SCIFB3_CTS_39_MARK,
 };
 /* - SDHI0 ------------------------------------------------------------------ */
-static const unsigned int sdhi0_data1_pins[] = {
+static const unsigned int sdhi0_data_pins[] = {
-	/* D0 */
-	302,
-};
-static const unsigned int sdhi0_data1_mux[] = {
-	SDHID0_0_MARK,
-};
-static const unsigned int sdhi0_data4_pins[] = {
 	/* D[0:3] */
 	302, 303, 304, 305,
 };
-static const unsigned int sdhi0_data4_mux[] = {
+static const unsigned int sdhi0_data_mux[] = {
 	SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK,
 };
 static const unsigned int sdhi0_ctrl_pins[] = {
 	SDHIWP0_MARK,
 };
 /* - SDHI1 ------------------------------------------------------------------ */
-static const unsigned int sdhi1_data1_pins[] = {
+static const unsigned int sdhi1_data_pins[] = {
-	/* D0 */
-	289,
-};
-static const unsigned int sdhi1_data1_mux[] = {
-	SDHID1_0_MARK,
-};
-static const unsigned int sdhi1_data4_pins[] = {
 	/* D[0:3] */
 	289, 290, 291, 292,
 };
-static const unsigned int sdhi1_data4_mux[] = {
+static const unsigned int sdhi1_data_mux[] = {
 	SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK,
 };
 static const unsigned int sdhi1_ctrl_pins[] = {
 	SDHICLK1_MARK, SDHICMD1_MARK,
 };
 /* - SDHI2 ------------------------------------------------------------------ */
-static const unsigned int sdhi2_data1_pins[] = {
+static const unsigned int sdhi2_data_pins[] = {
-	/* D0 */
-	295,
-};
-static const unsigned int sdhi2_data1_mux[] = {
-	SDHID2_0_MARK,
-};
-static const unsigned int sdhi2_data4_pins[] = {
 	/* D[0:3] */
 	295, 296, 297, 298,
 };
-static const unsigned int sdhi2_data4_mux[] = {
+static const unsigned int sdhi2_data_mux[] = {
 	SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK,
 };
 static const unsigned int sdhi2_ctrl_pins[] = {
 	SH_PFC_PIN_GROUP(irqc_irq55),
 	SH_PFC_PIN_GROUP(irqc_irq56),
 	SH_PFC_PIN_GROUP(irqc_irq57),
-	SH_PFC_PIN_GROUP(mmc0_data1),
+	BUS_DATA_PIN_GROUP(mmc0_data, 1),
-	SH_PFC_PIN_GROUP(mmc0_data4),
+	BUS_DATA_PIN_GROUP(mmc0_data, 4),
-	SH_PFC_PIN_GROUP(mmc0_data8),
+	BUS_DATA_PIN_GROUP(mmc0_data, 8),
 	SH_PFC_PIN_GROUP(mmc0_ctrl),
-	SH_PFC_PIN_GROUP(mmc1_data1),
+	BUS_DATA_PIN_GROUP(mmc1_data, 1),
-	SH_PFC_PIN_GROUP(mmc1_data4),
+	BUS_DATA_PIN_GROUP(mmc1_data, 4),
-	SH_PFC_PIN_GROUP(mmc1_data8),
+	BUS_DATA_PIN_GROUP(mmc1_data, 8),
 	SH_PFC_PIN_GROUP(mmc1_ctrl),
 	SH_PFC_PIN_GROUP(scifa0_data),
 	SH_PFC_PIN_GROUP(scifa0_clk),
 	SH_PFC_PIN_GROUP(scifb3_data_b),
 	SH_PFC_PIN_GROUP(scifb3_clk_b),
 	SH_PFC_PIN_GROUP(scifb3_ctrl_b),
-	SH_PFC_PIN_GROUP(sdhi0_data1),
+	BUS_DATA_PIN_GROUP(sdhi0_data, 1),
-	SH_PFC_PIN_GROUP(sdhi0_data4),
+	BUS_DATA_PIN_GROUP(sdhi0_data, 4),
 	SH_PFC_PIN_GROUP(sdhi0_ctrl),
 	SH_PFC_PIN_GROUP(sdhi0_cd),
 	SH_PFC_PIN_GROUP(sdhi0_wp),
-	SH_PFC_PIN_GROUP(sdhi1_data1),
+	BUS_DATA_PIN_GROUP(sdhi1_data, 1),
-	SH_PFC_PIN_GROUP(sdhi1_data4),
+	BUS_DATA_PIN_GROUP(sdhi1_data, 4),
 	SH_PFC_PIN_GROUP(sdhi1_ctrl),
-	SH_PFC_PIN_GROUP(sdhi2_data1),
+	BUS_DATA_PIN_GROUP(sdhi2_data, 1),
-	SH_PFC_PIN_GROUP(sdhi2_data4),
+	BUS_DATA_PIN_GROUP(sdhi2_data, 4),
 	SH_PFC_PIN_GROUP(sdhi2_ctrl),
 };
 	0x00002000, 0x00003000, 0x00003000,
 };
-static void __iomem *r8a73a4_pin_to_portcr(struct sh_pfc *pfc, unsigned int pin)
+static int r8a73a4_pin_to_portcr(unsigned int pin)
 {
-	return pfc->windows->virt + r8a73a4_portcr_offsets[pin >> 5] + pin;
+	return r8a73a4_portcr_offsets[pin >> 5] + pin;
 }
 static const struct sh_pfc_soc_operations r8a73a4_pfc_ops = {

drivers/pinctrl/renesas/pfc-r8a7740.c+48−234

 };
 /* - BSC -------------------------------------------------------------------- */
-static const unsigned int bsc_data8_pins[] = {
+static const unsigned int bsc_data_pins[] = {
-	/* D[0:7] */
-	157, 156, 155, 154, 153, 152, 151, 150,
-};
-static const unsigned int bsc_data8_mux[] = {
-	D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
-	D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
-};
-static const unsigned int bsc_data16_pins[] = {
-	/* D[0:15] */
-	157, 156, 155, 154, 153, 152, 151, 150,
-	149, 148, 147, 146, 145, 144, 143, 142,
-};
-static const unsigned int bsc_data16_mux[] = {
-	D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
-	D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
-	D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
-	D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
-};
-static const unsigned int bsc_data32_pins[] = {
 	/* D[0:31] */
 	157, 156, 155, 154, 153, 152, 151, 150,
 	149, 148, 147, 146, 145, 144, 143, 142,
 	171, 170, 169, 168, 167, 166, 173, 172,
 	165, 164, 163, 162, 161, 160, 159, 158,
 };
-static const unsigned int bsc_data32_mux[] = {
+static const unsigned int bsc_data_mux[] = {
 	D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
 	D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
 	D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
 static const unsigned int bsc_cs6a_mux[] = {
 	CS6A_MARK,
 };
-static const unsigned int bsc_rd_we8_pins[] = {
+static const unsigned int bsc_rd_we_pins[] = {
-	/* RD, WE[0] */
-	115, 113,
-};
-static const unsigned int bsc_rd_we8_mux[] = {
-	RD_FSC_MARK, WE0_FWE_MARK,
-};
-static const unsigned int bsc_rd_we16_pins[] = {
-	/* RD, WE[0:1] */
-	115, 113, 112,
-};
-static const unsigned int bsc_rd_we16_mux[] = {
-	RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK,
-};
-static const unsigned int bsc_rd_we32_pins[] = {
 	/* RD, WE[0:3] */
 	115, 113, 112, 108, 107,
 };
-static const unsigned int bsc_rd_we32_mux[] = {
+static const unsigned int bsc_rd_we_mux[] = {
 	RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK, WE2_ICIORD_MARK, WE3_ICIOWR_MARK,
 };
 static const unsigned int bsc_bs_pins[] = {
 IRQC_PINS_MUX(31, 1, 167);
 /* - LCD0 ------------------------------------------------------------------- */
-static const unsigned int lcd0_data8_pins[] = {
-	/* D[0:7] */
-	58, 57, 56, 55, 54, 53, 52, 51,
-};
-static const unsigned int lcd0_data8_mux[] = {
-	LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
-	LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
-};
-static const unsigned int lcd0_data9_pins[] = {
-	/* D[0:8] */
-	58, 57, 56, 55, 54, 53, 52, 51,
-	50,
-};
-static const unsigned int lcd0_data9_mux[] = {
-	LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
-	LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
-	LCD0_D8_MARK,
-};
-static const unsigned int lcd0_data12_pins[] = {
-	/* D[0:11] */
-	58, 57, 56, 55, 54, 53, 52, 51,
-	50, 49, 48, 47,
-};
-static const unsigned int lcd0_data12_mux[] = {
-	LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
-	LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
-	LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
-};
-static const unsigned int lcd0_data16_pins[] = {
-	/* D[0:15] */
-	58, 57, 56, 55, 54, 53, 52, 51,
-	50, 49, 48, 47, 46, 45, 44, 43,
-};
-static const unsigned int lcd0_data16_mux[] = {
-	LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
-	LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
-	LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
-	LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
-};
-static const unsigned int lcd0_data18_pins[] = {
-	/* D[0:17] */
-	58, 57, 56, 55, 54, 53, 52, 51,
-	50, 49, 48, 47, 46, 45, 44, 43,
-	42, 41,
-};
-static const unsigned int lcd0_data18_mux[] = {
-	LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
-	LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
-	LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
-	LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
-	LCD0_D16_MARK, LCD0_D17_MARK,
-};
 static const unsigned int lcd0_data24_0_pins[] = {
 	/* D[0:23] */
 	58, 57, 56, 55, 54, 53, 52, 51,
 	LCD0_CS_MARK, LCD0_WR_MARK, LCD0_RD_MARK, LCD0_RS_MARK,
 };
 /* - LCD1 ------------------------------------------------------------------- */
-static const unsigned int lcd1_data8_pins[] = {
+static const unsigned int lcd1_data_pins[] = {
-	/* D[0:7] */
-	4, 3, 2, 1, 0, 91, 92, 23,
-};
-static const unsigned int lcd1_data8_mux[] = {
-	LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
-	LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
-};
-static const unsigned int lcd1_data9_pins[] = {
-	/* D[0:8] */
-	4, 3, 2, 1, 0, 91, 92, 23,
-	93,
-};
-static const unsigned int lcd1_data9_mux[] = {
-	LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
-	LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
-	LCD1_D8_MARK,
-};
-static const unsigned int lcd1_data12_pins[] = {
-	/* D[0:11] */
-	4, 3, 2, 1, 0, 91, 92, 23,
-	93, 94, 21, 201,
-};
-static const unsigned int lcd1_data12_mux[] = {
-	LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
-	LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
-	LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
-};
-static const unsigned int lcd1_data16_pins[] = {
-	/* D[0:15] */
-	4, 3, 2, 1, 0, 91, 92, 23,
-	93, 94, 21, 201, 200, 199, 196, 195,
-};
-static const unsigned int lcd1_data16_mux[] = {
-	LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
-	LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
-	LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
-	LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
-};
-static const unsigned int lcd1_data18_pins[] = {
-	/* D[0:17] */
-	4, 3, 2, 1, 0, 91, 92, 23,
-	93, 94, 21, 201, 200, 199, 196, 195,
-	194, 193,
-};
-static const unsigned int lcd1_data18_mux[] = {
-	LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
-	LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
-	LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
-	LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
-	LCD1_D16_MARK, LCD1_D17_MARK,
-};
-static const unsigned int lcd1_data24_pins[] = {
 	/* D[0:23] */
 	4, 3, 2, 1, 0, 91, 92, 23,
 	93, 94, 21, 201, 200, 199, 196, 195,
 	194, 193, 198, 197, 75, 74, 15, 14,
 };
-static const unsigned int lcd1_data24_mux[] = {
+static const unsigned int lcd1_data_mux[] = {
 	LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
 	LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
 	LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
 	LCD1_CS_MARK, LCD1_WR_MARK, LCD1_RD_MARK, LCD1_RS_MARK,
 };
 /* - MMCIF ------------------------------------------------------------------ */
-static const unsigned int mmc0_data1_0_pins[] = {
+static const unsigned int mmc0_data_0_pins[] = {
-	/* D[0] */
-	68,
-};
-static const unsigned int mmc0_data1_0_mux[] = {
-	MMC0_D0_PORT68_MARK,
-};
-static const unsigned int mmc0_data4_0_pins[] = {
-	/* D[0:3] */
-	68, 69, 70, 71,
-};
-static const unsigned int mmc0_data4_0_mux[] = {
-	MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
-};
-static const unsigned int mmc0_data8_0_pins[] = {
 	/* D[0:7] */
 	68, 69, 70, 71, 72, 73, 74, 75,
 };
-static const unsigned int mmc0_data8_0_mux[] = {
+static const unsigned int mmc0_data_0_mux[] = {
 	MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
 	MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK, MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK,
 };
 	MMC0_CMD_PORT67_MARK, MMC0_CLK_PORT66_MARK,
 };
-static const unsigned int mmc0_data1_1_pins[] = {
+static const unsigned int mmc0_data_1_pins[] = {
-	/* D[0] */
-	149,
-};
-static const unsigned int mmc0_data1_1_mux[] = {
-	MMC1_D0_PORT149_MARK,
-};
-static const unsigned int mmc0_data4_1_pins[] = {
-	/* D[0:3] */
-	149, 148, 147, 146,
-};
-static const unsigned int mmc0_data4_1_mux[] = {
-	MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
-};
-static const unsigned int mmc0_data8_1_pins[] = {
 	/* D[0:7] */
 	149, 148, 147, 146, 145, 144, 143, 142,
 };
-static const unsigned int mmc0_data8_1_mux[] = {
+static const unsigned int mmc0_data_1_mux[] = {
 	MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
 	MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK, MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK,
 };
 	SCIFB_RTS_PORT172_MARK, SCIFB_CTS_PORT173_MARK,
 };
 /* - SDHI0 ------------------------------------------------------------------ */
-static const unsigned int sdhi0_data1_pins[] = {
+static const unsigned int sdhi0_data_pins[] = {
-	/* D0 */
-	77,
-};
-static const unsigned int sdhi0_data1_mux[] = {
-	SDHI0_D0_MARK,
-};
-static const unsigned int sdhi0_data4_pins[] = {
 	/* D[0:3] */
 	77, 78, 79, 80,
 };
-static const unsigned int sdhi0_data4_mux[] = {
+static const unsigned int sdhi0_data_mux[] = {
 	SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK,
 };
 static const unsigned int sdhi0_ctrl_pins[] = {
 	SDHI0_WP_MARK,
 };
 /* - SDHI1 ------------------------------------------------------------------ */
-static const unsigned int sdhi1_data1_pins[] = {
+static const unsigned int sdhi1_data_pins[] = {
-	/* D0 */
-	68,
-};
-static const unsigned int sdhi1_data1_mux[] = {
-	SDHI1_D0_MARK,
-};
-static const unsigned int sdhi1_data4_pins[] = {
 	/* D[0:3] */
 	68, 69, 70, 71,
 };
-static const unsigned int sdhi1_data4_mux[] = {
+static const unsigned int sdhi1_data_mux[] = {
 	SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK,
 };
 static const unsigned int sdhi1_ctrl_pins[] = {
 	SDHI1_WP_MARK,
 };
 /* - SDHI2 ------------------------------------------------------------------ */
-static const unsigned int sdhi2_data1_pins[] = {
+static const unsigned int sdhi2_data_pins[] = {
-	/* D0 */
-	205,
-};
-static const unsigned int sdhi2_data1_mux[] = {
-	SDHI2_D0_MARK,
-};
-static const unsigned int sdhi2_data4_pins[] = {
 	/* D[0:3] */
 	205, 206, 207, 208,
 };
-static const unsigned int sdhi2_data4_mux[] = {
+static const unsigned int sdhi2_data_mux[] = {
 	SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK,
 };
 static const unsigned int sdhi2_ctrl_pins[] = {
 };
 static const struct sh_pfc_pin_group pinmux_groups[] = {
-	SH_PFC_PIN_GROUP(bsc_data8),
+	BUS_DATA_PIN_GROUP(bsc_data, 8),
-	SH_PFC_PIN_GROUP(bsc_data16),
+	BUS_DATA_PIN_GROUP(bsc_data, 16),
-	SH_PFC_PIN_GROUP(bsc_data32),
+	BUS_DATA_PIN_GROUP(bsc_data, 32),
 	SH_PFC_PIN_GROUP(bsc_cs0),
 	SH_PFC_PIN_GROUP(bsc_cs2),
 	SH_PFC_PIN_GROUP(bsc_cs4),
 	SH_PFC_PIN_GROUP(bsc_cs5a_1),
 	SH_PFC_PIN_GROUP(bsc_cs5b),
 	SH_PFC_PIN_GROUP(bsc_cs6a),
-	SH_PFC_PIN_GROUP(bsc_rd_we8),
+	SH_PFC_PIN_GROUP_SUBSET(bsc_rd_we8, bsc_rd_we, 0, 2),
-	SH_PFC_PIN_GROUP(bsc_rd_we16),
+	SH_PFC_PIN_GROUP_SUBSET(bsc_rd_we16, bsc_rd_we, 0, 3),
-	SH_PFC_PIN_GROUP(bsc_rd_we32),
+	SH_PFC_PIN_GROUP_SUBSET(bsc_rd_we32, bsc_rd_we, 0, 5),
 	SH_PFC_PIN_GROUP(bsc_bs),
 	SH_PFC_PIN_GROUP(bsc_rdwr),
 	SH_PFC_PIN_GROUP(ceu0_data_0_7),
 	SH_PFC_PIN_GROUP(intc_irq30_1),
 	SH_PFC_PIN_GROUP(intc_irq31_0),
 	SH_PFC_PIN_GROUP(intc_irq31_1),
-	SH_PFC_PIN_GROUP(lcd0_data8),
+	SH_PFC_PIN_GROUP_SUBSET(lcd0_data8, lcd0_data24_0, 0, 8),
-	SH_PFC_PIN_GROUP(lcd0_data9),
+	SH_PFC_PIN_GROUP_SUBSET(lcd0_data9, lcd0_data24_0, 0, 9),
-	SH_PFC_PIN_GROUP(lcd0_data12),
+	SH_PFC_PIN_GROUP_SUBSET(lcd0_data12, lcd0_data24_0, 0, 12),
-	SH_PFC_PIN_GROUP(lcd0_data16),
+	SH_PFC_PIN_GROUP_SUBSET(lcd0_data16, lcd0_data24_0, 0, 16),
-	SH_PFC_PIN_GROUP(lcd0_data18),
+	SH_PFC_PIN_GROUP_SUBSET(lcd0_data18, lcd0_data24_0, 0, 18),
 	SH_PFC_PIN_GROUP(lcd0_data24_0),
 	SH_PFC_PIN_GROUP(lcd0_data24_1),
 	SH_PFC_PIN_GROUP(lcd0_display),
 	SH_PFC_PIN_GROUP(lcd0_lclk_1),
 	SH_PFC_PIN_GROUP(lcd0_sync),
 	SH_PFC_PIN_GROUP(lcd0_sys),
-	SH_PFC_PIN_GROUP(lcd1_data8),
+	BUS_DATA_PIN_GROUP(lcd1_data, 8),
-	SH_PFC_PIN_GROUP(lcd1_data9),
+	BUS_DATA_PIN_GROUP(lcd1_data, 9),
-	SH_PFC_PIN_GROUP(lcd1_data12),
+	BUS_DATA_PIN_GROUP(lcd1_data, 12),
-	SH_PFC_PIN_GROUP(lcd1_data16),
+	BUS_DATA_PIN_GROUP(lcd1_data, 16),
-	SH_PFC_PIN_GROUP(lcd1_data18),
+	BUS_DATA_PIN_GROUP(lcd1_data, 18),
-	SH_PFC_PIN_GROUP(lcd1_data24),
+	BUS_DATA_PIN_GROUP(lcd1_data, 24),
 	SH_PFC_PIN_GROUP(lcd1_display),
 	SH_PFC_PIN_GROUP(lcd1_lclk),
 	SH_PFC_PIN_GROUP(lcd1_sync),
 	SH_PFC_PIN_GROUP(lcd1_sys),
-	SH_PFC_PIN_GROUP(mmc0_data1_0),
+	BUS_DATA_PIN_GROUP(mmc0_data, 1, _0),
-	SH_PFC_PIN_GROUP(mmc0_data4_0),
+	BUS_DATA_PIN_GROUP(mmc0_data, 4, _0),
-	SH_PFC_PIN_GROUP(mmc0_data8_0),
+	BUS_DATA_PIN_GROUP(mmc0_data, 8, _0),
 	SH_PFC_PIN_GROUP(mmc0_ctrl_0),
-	SH_PFC_PIN_GROUP(mmc0_data1_1),
+	BUS_DATA_PIN_GROUP(mmc0_data, 1, _1),
-	SH_PFC_PIN_GROUP(mmc0_data4_1),
+	BUS_DATA_PIN_GROUP(mmc0_data, 4, _1),
-	SH_PFC_PIN_GROUP(mmc0_data8_1),
+	BUS_DATA_PIN_GROUP(mmc0_data, 8, _1),
 	SH_PFC_PIN_GROUP(mmc0_ctrl_1),
 	SH_PFC_PIN_GROUP(scifa0_data),
 	SH_PFC_PIN_GROUP(scifa0_clk),
 	SH_PFC_PIN_GROUP(scifb_data_1),
 	SH_PFC_PIN_GROUP(scifb_clk_1),
 	SH_PFC_PIN_GROUP(scifb_ctrl_1),
-	SH_PFC_PIN_GROUP(sdhi0_data1),
+	BUS_DATA_PIN_GROUP(sdhi0_data, 1),
-	SH_PFC_PIN_GROUP(sdhi0_data4),
+	BUS_DATA_PIN_GROUP(sdhi0_data, 4),
 	SH_PFC_PIN_GROUP(sdhi0_ctrl),
 	SH_PFC_PIN_GROUP(sdhi0_cd),
 	SH_PFC_PIN_GROUP(sdhi0_wp),
-	SH_PFC_PIN_GROUP(sdhi1_data1),
+	BUS_DATA_PIN_GROUP(sdhi1_data, 1),
-	SH_PFC_PIN_GROUP(sdhi1_data4),
+	BUS_DATA_PIN_GROUP(sdhi1_data, 4),
 	SH_PFC_PIN_GROUP(sdhi1_ctrl),
 	SH_PFC_PIN_GROUP(sdhi1_cd),
 	SH_PFC_PIN_GROUP(sdhi1_wp),
-	SH_PFC_PIN_GROUP(sdhi2_data1),
+	BUS_DATA_PIN_GROUP(sdhi2_data, 1),
-	SH_PFC_PIN_GROUP(sdhi2_data4),
+	BUS_DATA_PIN_GROUP(sdhi2_data, 4),
 	SH_PFC_PIN_GROUP(sdhi2_ctrl),
 	SH_PFC_PIN_GROUP(sdhi2_cd_0),
 	SH_PFC_PIN_GROUP(sdhi2_wp_0),
 	{ 83, 0x0000 }, { 114, 0x1000 }, { 209, 0x2000 }, { 211, 0x3000 },
 };
-static void __iomem *r8a7740_pin_to_portcr(struct sh_pfc *pfc, unsigned int pin)
+static int r8a7740_pin_to_portcr(unsigned int pin)
 {
 	unsigned int i;
 			&r8a7740_portcr_offsets[i];
 		if (pin <= group->end_pin)
-			return pfc->windows->virt + group->offset + pin;
+			return group->offset + pin;
 	}
-	return NULL;
+	return -1;
 }
 static const struct sh_pfc_soc_operations r8a7740_pfc_ops = {

drivers/pinctrl/renesas/pfc-r8a77470.c+82−158

 	SCL4_E_MARK, SDA4_E_MARK,
 };
 /* - MMC -------------------------------------------------------------------- */
-static const unsigned int mmc_data1_pins[] = {
+static const unsigned int mmc_data_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(0, 15),
-};
-static const unsigned int mmc_data1_mux[] = {
-	MMC0_D0_SDHI1_D0_MARK,
-};
-static const unsigned int mmc_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
-	RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 18),
-};
-static const unsigned int mmc_data4_mux[] = {
-	MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK,
-	MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK,
-};
-static const unsigned int mmc_data8_pins[] = {
 	/* D[0:3] */
 	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
 	RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 18),
 	RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20),
 	RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22),
 };
-static const unsigned int mmc_data8_mux[] = {
+static const unsigned int mmc_data_mux[] = {
 	MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK,
 	MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK,
 	MMC0_D4_MARK, MMC0_D5_MARK,
 static const unsigned int qspi0_ctrl_mux[] = {
 	QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
 };
-static const unsigned int qspi0_data2_pins[] = {
+static const unsigned int qspi0_data_pins[] = {
-	/* MOSI_IO0, MISO_IO1 */
-	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
-};
-static const unsigned int qspi0_data2_mux[] = {
-	QSPI0_MOSI_QSPI0_IO0_MARK, QSPI0_MISO_QSPI0_IO1_MARK,
-};
-static const unsigned int qspi0_data4_pins[] = {
 	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
 	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
 	RCAR_GP_PIN(1, 20),
 };
-static const unsigned int qspi0_data4_mux[] = {
+static const unsigned int qspi0_data_mux[] = {
 	QSPI0_MOSI_QSPI0_IO0_MARK, QSPI0_MISO_QSPI0_IO1_MARK,
 	QSPI0_IO2_MARK, QSPI0_IO3_MARK,
 };
 static const unsigned int qspi1_ctrl_mux[] = {
 	QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
 };
-static const unsigned int qspi1_data2_pins[] = {
+static const unsigned int qspi1_data_pins[] = {
-	/* MOSI_IO0, MISO_IO1 */
-	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
-};
-static const unsigned int qspi1_data2_mux[] = {
-	QSPI1_MOSI_QSPI1_IO0_MARK, QSPI1_MISO_QSPI1_IO1_MARK,
-};
-static const unsigned int qspi1_data4_pins[] = {
 	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
 	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 7),
 	RCAR_GP_PIN(4, 8),
 };
-static const unsigned int qspi1_data4_mux[] = {
+static const unsigned int qspi1_data_mux[] = {
 	QSPI1_MOSI_QSPI1_IO0_MARK, QSPI1_MISO_QSPI1_IO1_MARK,
 	QSPI1_IO2_MARK, QSPI1_IO3_MARK,
 };
 	SCIF_CLK_B_MARK,
 };
 /* - SDHI0 ------------------------------------------------------------------ */
-static const unsigned int sdhi0_data1_pins[] = {
+static const unsigned int sdhi0_data_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(0, 7),
-};
-static const unsigned int sdhi0_data1_mux[] = {
-	SD0_DAT0_MARK,
-};
-static const unsigned int sdhi0_data4_pins[] = {
 	/* D[0:3] */
 	RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
 	RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
 };
-static const unsigned int sdhi0_data4_mux[] = {
+static const unsigned int sdhi0_data_mux[] = {
 	SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
 };
 static const unsigned int sdhi0_ctrl_pins[] = {
 	SD0_WP_MARK,
 };
 /* - SDHI1 ------------------------------------------------------------------ */
-static const unsigned int sdhi1_data1_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(0, 15),
-};
-static const unsigned int sdhi1_data1_mux[] = {
-	MMC0_D0_SDHI1_D0_MARK,
-};
-static const unsigned int sdhi1_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
-	RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 18),
-};
-static const unsigned int sdhi1_data4_mux[] = {
-	MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK,
-	MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK,
-};
-static const unsigned int sdhi1_ctrl_pins[] = {
-	/* CLK, CMD */
-	RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
-};
-static const unsigned int sdhi1_ctrl_mux[] = {
-	MMC0_CLK_SDHI1_CLK_MARK, MMC0_CMD_SDHI1_CMD_MARK,
-};
 static const unsigned int sdhi1_cd_pins[] = {
 	/* CD */
 	RCAR_GP_PIN(0, 19),
 	SD1_WP_MARK,
 };
 /* - SDHI2 ------------------------------------------------------------------ */
-static const unsigned int sdhi2_data1_pins[] = {
+static const unsigned int sdhi2_data_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(4, 16),
-};
-static const unsigned int sdhi2_data1_mux[] = {
-	SD2_DAT0_MARK,
-};
-static const unsigned int sdhi2_data4_pins[] = {
 	/* D[0:3] */
 	RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
 	RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19),
 };
-static const unsigned int sdhi2_data4_mux[] = {
+static const unsigned int sdhi2_data_mux[] = {
 	SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
 };
 static const unsigned int sdhi2_ctrl_pins[] = {
 	USB1_OVC_MARK,
 };
 /* - VIN0 ------------------------------------------------------------------- */
-static const union vin_data vin0_data_pins = {
+static const unsigned int vin0_data_pins[] = {
-	.data24 = {
+	/* B */
-		/* B */
+	RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
-		RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
+	RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
-		RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
+	RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
-		RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
+	RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
-		RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
+	/* G */
-		/* G */
+	RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
-		RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
+	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
-		RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
+	RCAR_GP_PIN(4, 6), RCAR_GP_PIN(5, 8),
-		RCAR_GP_PIN(4, 6), RCAR_GP_PIN(5, 8),
+	RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
-		RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
+	/* R */
-		/* R */
+	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
-		RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
+	RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
-		RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
+	RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
-		RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
+	RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19),
-		RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19),
-	},
 };
-static const union vin_data vin0_data_mux = {
+static const unsigned int vin0_data_mux[] = {
-	.data24 = {
+	/* B */
-		/* B */
+	VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
-		VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
+	VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
-		VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
+	VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
-		VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
+	VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
-		VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
+	/* G */
-		/* G */
+	VI0_G0_MARK, VI0_G1_MARK,
-		VI0_G0_MARK, VI0_G1_MARK,
+	VI0_G2_MARK, VI0_G3_MARK,
-		VI0_G2_MARK, VI0_G3_MARK,
+	VI0_G4_MARK, VI0_G5_MARK,
-		VI0_G4_MARK, VI0_G5_MARK,
+	VI0_G6_MARK, VI0_G7_MARK,
-		VI0_G6_MARK, VI0_G7_MARK,
+	/* R */
-		/* R */
+	VI0_R0_MARK, VI0_R1_MARK,
-		VI0_R0_MARK, VI0_R1_MARK,
+	VI0_R2_MARK, VI0_R3_MARK,
-		VI0_R2_MARK, VI0_R3_MARK,
+	VI0_R4_MARK, VI0_R5_MARK,
-		VI0_R4_MARK, VI0_R5_MARK,
+	VI0_R6_MARK, VI0_R7_MARK,
-		VI0_R6_MARK, VI0_R7_MARK,
-	},
 };
 static const unsigned int vin0_data18_pins[] = {
 	/* B */
 	VI0_CLK_MARK,
 };
 /* - VIN1 ------------------------------------------------------------------- */
-static const union vin_data vin1_data_pins = {
+static const unsigned int vin1_data_pins[] = {
-	.data12 = {
+	RCAR_GP_PIN(3,  1), RCAR_GP_PIN(3, 2),
-		RCAR_GP_PIN(3,  1), RCAR_GP_PIN(3, 2),
+	RCAR_GP_PIN(3,  3), RCAR_GP_PIN(3, 4),
-		RCAR_GP_PIN(3,  3), RCAR_GP_PIN(3, 4),
+	RCAR_GP_PIN(3,  5), RCAR_GP_PIN(3, 6),
-		RCAR_GP_PIN(3,  5), RCAR_GP_PIN(3, 6),
+	RCAR_GP_PIN(3,  7), RCAR_GP_PIN(3, 8),
-		RCAR_GP_PIN(3,  7), RCAR_GP_PIN(3, 8),
+	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
-		RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
+	RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
-		RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
-	},
 };
-static const union vin_data vin1_data_mux = {
+static const unsigned int vin1_data_mux[] = {
-	.data12 = {
+	VI1_DATA0_MARK, VI1_DATA1_MARK,
-		VI1_DATA0_MARK, VI1_DATA1_MARK,
+	VI1_DATA2_MARK, VI1_DATA3_MARK,
-		VI1_DATA2_MARK, VI1_DATA3_MARK,
+	VI1_DATA4_MARK, VI1_DATA5_MARK,
-		VI1_DATA4_MARK, VI1_DATA5_MARK,
+	VI1_DATA6_MARK, VI1_DATA7_MARK,
-		VI1_DATA6_MARK, VI1_DATA7_MARK,
+	VI1_DATA8_MARK, VI1_DATA9_MARK,
-		VI1_DATA8_MARK, VI1_DATA9_MARK,
+	VI1_DATA10_MARK, VI1_DATA11_MARK,
-		VI1_DATA10_MARK, VI1_DATA11_MARK,
-	},
 };
 static const unsigned int vin1_sync_pins[] = {
 	RCAR_GP_PIN(3, 11), /* HSYNC */
 	SH_PFC_PIN_GROUP(i2c4_c),
 	SH_PFC_PIN_GROUP(i2c4_d),
 	SH_PFC_PIN_GROUP(i2c4_e),
-	SH_PFC_PIN_GROUP(mmc_data1),
+	BUS_DATA_PIN_GROUP(mmc_data, 1),
-	SH_PFC_PIN_GROUP(mmc_data4),
+	BUS_DATA_PIN_GROUP(mmc_data, 4),
-	SH_PFC_PIN_GROUP(mmc_data8),
+	BUS_DATA_PIN_GROUP(mmc_data, 8),
 	SH_PFC_PIN_GROUP(mmc_ctrl),
 	SH_PFC_PIN_GROUP(qspi0_ctrl),
-	SH_PFC_PIN_GROUP(qspi0_data2),
+	BUS_DATA_PIN_GROUP(qspi0_data, 2),
-	SH_PFC_PIN_GROUP(qspi0_data4),
+	BUS_DATA_PIN_GROUP(qspi0_data, 4),
 	SH_PFC_PIN_GROUP(qspi1_ctrl),
-	SH_PFC_PIN_GROUP(qspi1_data2),
+	BUS_DATA_PIN_GROUP(qspi1_data, 2),
-	SH_PFC_PIN_GROUP(qspi1_data4),
+	BUS_DATA_PIN_GROUP(qspi1_data, 4),
 	SH_PFC_PIN_GROUP(scif0_data_a),
 	SH_PFC_PIN_GROUP(scif0_data_b),
 	SH_PFC_PIN_GROUP(scif0_data_c),
 	SH_PFC_PIN_GROUP(scif5_data_f),
 	SH_PFC_PIN_GROUP(scif_clk_a),
 	SH_PFC_PIN_GROUP(scif_clk_b),
-	SH_PFC_PIN_GROUP(sdhi0_data1),
+	BUS_DATA_PIN_GROUP(sdhi0_data, 1),
-	SH_PFC_PIN_GROUP(sdhi0_data4),
+	BUS_DATA_PIN_GROUP(sdhi0_data, 4),
 	SH_PFC_PIN_GROUP(sdhi0_ctrl),
 	SH_PFC_PIN_GROUP(sdhi0_cd),
 	SH_PFC_PIN_GROUP(sdhi0_wp),
-	SH_PFC_PIN_GROUP(sdhi1_data1),
+	SH_PFC_PIN_GROUP_SUBSET(sdhi1_data1, mmc_data, 0, 1),
-	SH_PFC_PIN_GROUP(sdhi1_data4),
+	SH_PFC_PIN_GROUP_SUBSET(sdhi1_data4, mmc_data, 0, 4),
-	SH_PFC_PIN_GROUP(sdhi1_ctrl),
+	SH_PFC_PIN_GROUP_ALIAS(sdhi1_ctrl, mmc_ctrl),
 	SH_PFC_PIN_GROUP(sdhi1_cd),
 	SH_PFC_PIN_GROUP(sdhi1_wp),
-	SH_PFC_PIN_GROUP(sdhi2_data1),
+	BUS_DATA_PIN_GROUP(sdhi2_data, 1),
-	SH_PFC_PIN_GROUP(sdhi2_data4),
+	BUS_DATA_PIN_GROUP(sdhi2_data, 4),
 	SH_PFC_PIN_GROUP(sdhi2_ctrl),
 	SH_PFC_PIN_GROUP(sdhi2_cd),
 	SH_PFC_PIN_GROUP(sdhi2_wp),
 	SH_PFC_PIN_GROUP(usb0),
 	SH_PFC_PIN_GROUP(usb1),
-	VIN_DATA_PIN_GROUP(vin0_data, 24),
+	BUS_DATA_PIN_GROUP(vin0_data, 24),
-	VIN_DATA_PIN_GROUP(vin0_data, 20),
+	BUS_DATA_PIN_GROUP(vin0_data, 20),
 	SH_PFC_PIN_GROUP(vin0_data18),
-	VIN_DATA_PIN_GROUP(vin0_data, 16),
+	BUS_DATA_PIN_GROUP(vin0_data, 16),
-	VIN_DATA_PIN_GROUP(vin0_data, 12),
+	BUS_DATA_PIN_GROUP(vin0_data, 12),
-	VIN_DATA_PIN_GROUP(vin0_data, 10),
+	BUS_DATA_PIN_GROUP(vin0_data, 10),
-	VIN_DATA_PIN_GROUP(vin0_data, 8),
+	BUS_DATA_PIN_GROUP(vin0_data, 8),
 	SH_PFC_PIN_GROUP(vin0_sync),
 	SH_PFC_PIN_GROUP(vin0_field),
 	SH_PFC_PIN_GROUP(vin0_clkenb),
 	SH_PFC_PIN_GROUP(vin0_clk),
-	VIN_DATA_PIN_GROUP(vin1_data, 12),
+	BUS_DATA_PIN_GROUP(vin1_data, 12),
-	VIN_DATA_PIN_GROUP(vin1_data, 10),
+	BUS_DATA_PIN_GROUP(vin1_data, 10),
-	VIN_DATA_PIN_GROUP(vin1_data, 8),
+	BUS_DATA_PIN_GROUP(vin1_data, 8),
 	SH_PFC_PIN_GROUP(vin1_sync),
 	SH_PFC_PIN_GROUP(vin1_field),
 	SH_PFC_PIN_GROUP(vin1_clkenb),
 	{ },
 };
-static int r8a77470_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
+static int r8a77470_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
-				   u32 *pocctrl)
 {
 	int bit = -EINVAL;
 	{ /* sentinel */ }
 };
-static const struct sh_pfc_soc_operations r8a77470_pinmux_ops = {
+static const struct sh_pfc_soc_operations r8a77470_pfc_ops = {
 	.pin_to_pocctrl = r8a77470_pin_to_pocctrl,
 	.get_bias = rcar_pinmux_get_bias,
 	.set_bias = rcar_pinmux_set_bias,
 #ifdef CONFIG_PINCTRL_PFC_R8A77470
 const struct sh_pfc_soc_info r8a77470_pinmux_info = {
 	.name = "r8a77470_pfc",
-	.ops = &r8a77470_pinmux_ops,
+	.ops = &r8a77470_pfc_ops,
 	.unlock_reg = 0xe6060000, /* PMMR */
 	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },

drivers/pinctrl/renesas/pfc-r8a7778.c+25−44

 /* - MMC macro -------------------------------------------------------------- */
 #define MMC_PFC_PINS(name, args...)		SH_PFC_PINS(name, args)
 #define MMC_PFC_CTRL(name, clk, cmd)		SH_PFC_MUX2(name, clk, cmd)
-#define MMC_PFC_DAT1(name, d0)			SH_PFC_MUX1(name, d0)
-#define MMC_PFC_DAT4(name, d0, d1, d2, d3)	SH_PFC_MUX4(name, d0, d1, d2, d3)
 #define MMC_PFC_DAT8(name, d0, d1, d2, d3, d4, d5, d6, d7)	\
 			SH_PFC_MUX8(name, d0, d1, d2, d3, d4, d5, d6, d7)
 /* - MMC -------------------------------------------------------------------- */
 MMC_PFC_PINS(mmc_ctrl,		RCAR_GP_PIN(1, 5),	RCAR_GP_PIN(1, 6));
 MMC_PFC_CTRL(mmc_ctrl,		MMC_CLK,		MMC_CMD);
-MMC_PFC_PINS(mmc_data1,		RCAR_GP_PIN(1, 7));
+MMC_PFC_PINS(mmc_data,		RCAR_GP_PIN(1, 7),	RCAR_GP_PIN(1, 8),
-MMC_PFC_DAT1(mmc_data1,		MMC_D0);
-MMC_PFC_PINS(mmc_data4,		RCAR_GP_PIN(1, 7),	RCAR_GP_PIN(1, 8),
-				RCAR_GP_PIN(0, 5),	RCAR_GP_PIN(0, 6));
-MMC_PFC_DAT4(mmc_data4,		MMC_D0,			MMC_D1,
-				MMC_D2,			MMC_D3);
-MMC_PFC_PINS(mmc_data8,		RCAR_GP_PIN(1, 7),	RCAR_GP_PIN(1, 8),
 				RCAR_GP_PIN(0, 5),	RCAR_GP_PIN(0, 6),
 				RCAR_GP_PIN(1, 4),	RCAR_GP_PIN(1, 0),
 				RCAR_GP_PIN(0, 30),	RCAR_GP_PIN(0, 31));
-MMC_PFC_DAT8(mmc_data8,		MMC_D0,			MMC_D1,
+MMC_PFC_DAT8(mmc_data,		MMC_D0,			MMC_D1,
 				MMC_D2,			MMC_D3,
 				MMC_D4,			MMC_D5,
 				MMC_D6,			MMC_D7);
 /* - SDHI macro ------------------------------------------------------------- */
 #define SDHI_PFC_PINS(name, args...)		SH_PFC_PINS(name, args)
-#define SDHI_PFC_DAT1(name, d0)			SH_PFC_MUX1(name, d0)
 #define SDHI_PFC_DAT4(name, d0, d1, d2, d3)	SH_PFC_MUX4(name, d0, d1, d2, d3)
 #define SDHI_PFC_CTRL(name, clk, cmd)		SH_PFC_MUX2(name, clk, cmd)
 #define SDHI_PFC_CDPN(name, cd)			SH_PFC_MUX1(name, cd)
 SDHI_PFC_CDPN(sdhi0_cd,		SD0_CD);
 SDHI_PFC_PINS(sdhi0_ctrl,	RCAR_GP_PIN(3, 11),	RCAR_GP_PIN(3, 12));
 SDHI_PFC_CTRL(sdhi0_ctrl,	SD0_CLK,		SD0_CMD);
-SDHI_PFC_PINS(sdhi0_data1,	RCAR_GP_PIN(3, 13));
+SDHI_PFC_PINS(sdhi0_data,	RCAR_GP_PIN(3, 13),	RCAR_GP_PIN(3, 14),
-SDHI_PFC_DAT1(sdhi0_data1,	SD0_DAT0);
-SDHI_PFC_PINS(sdhi0_data4,	RCAR_GP_PIN(3, 13),	RCAR_GP_PIN(3, 14),
 				RCAR_GP_PIN(3, 15),	RCAR_GP_PIN(3, 16));
-SDHI_PFC_DAT4(sdhi0_data4,	SD0_DAT0,		SD0_DAT1,
+SDHI_PFC_DAT4(sdhi0_data,	SD0_DAT0,		SD0_DAT1,
 				SD0_DAT2,		SD0_DAT3);
 SDHI_PFC_PINS(sdhi0_wp,		RCAR_GP_PIN(3, 18));
 SDHI_PFC_WPPN(sdhi0_wp,		SD0_WP);
 SDHI_PFC_CTRL(sdhi1_ctrl_a,	SD1_CLK_A,		SD1_CMD_A);
 SDHI_PFC_PINS(sdhi1_ctrl_b,	RCAR_GP_PIN(1, 17),	RCAR_GP_PIN(1, 16));
 SDHI_PFC_CTRL(sdhi1_ctrl_b,	SD1_CLK_B,		SD1_CMD_B);
-SDHI_PFC_PINS(sdhi1_data1_a,	RCAR_GP_PIN(1, 7));
+SDHI_PFC_PINS(sdhi1_data_a,	RCAR_GP_PIN(1, 7),	RCAR_GP_PIN(1, 8),
-SDHI_PFC_DAT1(sdhi1_data1_a,	SD1_DAT0_A);
-SDHI_PFC_PINS(sdhi1_data1_b,	RCAR_GP_PIN(1, 18));
-SDHI_PFC_DAT1(sdhi1_data1_b,	SD1_DAT0_B);
-SDHI_PFC_PINS(sdhi1_data4_a,	RCAR_GP_PIN(1, 7),	RCAR_GP_PIN(1, 8),
 				RCAR_GP_PIN(0, 5),	RCAR_GP_PIN(0, 6));
-SDHI_PFC_DAT4(sdhi1_data4_a,	SD1_DAT0_A,		SD1_DAT1_A,
+SDHI_PFC_DAT4(sdhi1_data_a,	SD1_DAT0_A,		SD1_DAT1_A,
 				SD1_DAT2_A,		SD1_DAT3_A);
-SDHI_PFC_PINS(sdhi1_data4_b,	RCAR_GP_PIN(1, 18),	RCAR_GP_PIN(1, 19),
+SDHI_PFC_PINS(sdhi1_data_b,	RCAR_GP_PIN(1, 18),	RCAR_GP_PIN(1, 19),
 				RCAR_GP_PIN(1, 20),	RCAR_GP_PIN(1, 21));
-SDHI_PFC_DAT4(sdhi1_data4_b,	SD1_DAT0_B,		SD1_DAT1_B,
+SDHI_PFC_DAT4(sdhi1_data_b,	SD1_DAT0_B,		SD1_DAT1_B,
 				SD1_DAT2_B,		SD1_DAT3_B);
 SDHI_PFC_PINS(sdhi1_wp_a,	RCAR_GP_PIN(0, 31));
 SDHI_PFC_WPPN(sdhi1_wp_a,	SD1_WP_A);
 SDHI_PFC_CTRL(sdhi2_ctrl_a,	SD2_CLK_A,		SD2_CMD_A);
 SDHI_PFC_PINS(sdhi2_ctrl_b,	RCAR_GP_PIN(4, 5),	RCAR_GP_PIN(4, 6));
 SDHI_PFC_CTRL(sdhi2_ctrl_b,	SD2_CLK_B,		SD2_CMD_B);
-SDHI_PFC_PINS(sdhi2_data1_a,	RCAR_GP_PIN(4, 19));
+SDHI_PFC_PINS(sdhi2_data_a,	RCAR_GP_PIN(4, 19),	RCAR_GP_PIN(4, 20),
-SDHI_PFC_DAT1(sdhi2_data1_a,	SD2_DAT0_A);
-SDHI_PFC_PINS(sdhi2_data1_b,	RCAR_GP_PIN(4, 7));
-SDHI_PFC_DAT1(sdhi2_data1_b,	SD2_DAT0_B);
-SDHI_PFC_PINS(sdhi2_data4_a,	RCAR_GP_PIN(4, 19),	RCAR_GP_PIN(4, 20),
 				RCAR_GP_PIN(4, 21),	RCAR_GP_PIN(4, 22));
-SDHI_PFC_DAT4(sdhi2_data4_a,	SD2_DAT0_A,		SD2_DAT1_A,
+SDHI_PFC_DAT4(sdhi2_data_a,	SD2_DAT0_A,		SD2_DAT1_A,
 				SD2_DAT2_A,		SD2_DAT3_A);
-SDHI_PFC_PINS(sdhi2_data4_b,	RCAR_GP_PIN(4, 7),	RCAR_GP_PIN(4, 8),
+SDHI_PFC_PINS(sdhi2_data_b,	RCAR_GP_PIN(4, 7),	RCAR_GP_PIN(4, 8),
 				RCAR_GP_PIN(3, 25),	RCAR_GP_PIN(3, 26));
-SDHI_PFC_DAT4(sdhi2_data4_b,	SD2_DAT0_B,		SD2_DAT1_B,
+SDHI_PFC_DAT4(sdhi2_data_b,	SD2_DAT0_B,		SD2_DAT1_B,
 				SD2_DAT2_B,		SD2_DAT3_B);
 SDHI_PFC_PINS(sdhi2_wp_a,	RCAR_GP_PIN(4, 24));
 SDHI_PFC_WPPN(sdhi2_wp_a,	SD2_WP_A);
 	SH_PFC_PIN_GROUP(i2c3_b),
 	SH_PFC_PIN_GROUP(i2c3_c),
 	SH_PFC_PIN_GROUP(mmc_ctrl),
-	SH_PFC_PIN_GROUP(mmc_data1),
+	BUS_DATA_PIN_GROUP(mmc_data, 1),
-	SH_PFC_PIN_GROUP(mmc_data4),
+	BUS_DATA_PIN_GROUP(mmc_data, 4),
-	SH_PFC_PIN_GROUP(mmc_data8),
+	BUS_DATA_PIN_GROUP(mmc_data, 8),
 	SH_PFC_PIN_GROUP(scif_clk),
 	SH_PFC_PIN_GROUP(scif0_data_a),
 	SH_PFC_PIN_GROUP(scif0_data_b),
 	SH_PFC_PIN_GROUP(scif5_data_b),
 	SH_PFC_PIN_GROUP(sdhi0_cd),
 	SH_PFC_PIN_GROUP(sdhi0_ctrl),
-	SH_PFC_PIN_GROUP(sdhi0_data1),
+	BUS_DATA_PIN_GROUP(sdhi0_data, 1),
-	SH_PFC_PIN_GROUP(sdhi0_data4),
+	BUS_DATA_PIN_GROUP(sdhi0_data, 4),
 	SH_PFC_PIN_GROUP(sdhi0_wp),
 	SH_PFC_PIN_GROUP(sdhi1_cd_a),
 	SH_PFC_PIN_GROUP(sdhi1_cd_b),
 	SH_PFC_PIN_GROUP(sdhi1_ctrl_a),
 	SH_PFC_PIN_GROUP(sdhi1_ctrl_b),
-	SH_PFC_PIN_GROUP(sdhi1_data1_a),
+	BUS_DATA_PIN_GROUP(sdhi1_data, 1, _a),
-	SH_PFC_PIN_GROUP(sdhi1_data1_b),
+	BUS_DATA_PIN_GROUP(sdhi1_data, 1, _b),
-	SH_PFC_PIN_GROUP(sdhi1_data4_a),
+	BUS_DATA_PIN_GROUP(sdhi1_data, 4, _a),
-	SH_PFC_PIN_GROUP(sdhi1_data4_b),
+	BUS_DATA_PIN_GROUP(sdhi1_data, 4, _b),
 	SH_PFC_PIN_GROUP(sdhi1_wp_a),
 	SH_PFC_PIN_GROUP(sdhi1_wp_b),
 	SH_PFC_PIN_GROUP(sdhi2_cd_a),
 	SH_PFC_PIN_GROUP(sdhi2_cd_b),
 	SH_PFC_PIN_GROUP(sdhi2_ctrl_a),
 	SH_PFC_PIN_GROUP(sdhi2_ctrl_b),
-	SH_PFC_PIN_GROUP(sdhi2_data1_a),
+	BUS_DATA_PIN_GROUP(sdhi2_data, 1, _a),
-	SH_PFC_PIN_GROUP(sdhi2_data1_b),
+	BUS_DATA_PIN_GROUP(sdhi2_data, 1, _b),
-	SH_PFC_PIN_GROUP(sdhi2_data4_a),
+	BUS_DATA_PIN_GROUP(sdhi2_data, 4, _a),
-	SH_PFC_PIN_GROUP(sdhi2_data4_b),
+	BUS_DATA_PIN_GROUP(sdhi2_data, 4, _b),
 	SH_PFC_PIN_GROUP(sdhi2_wp_a),
 	SH_PFC_PIN_GROUP(sdhi2_wp_b),
 	SH_PFC_PIN_GROUP(ssi012_ctrl),

drivers/pinctrl/renesas/pfc-r8a7779.c+30−88

 	EX_CS5_MARK,
 };
 /* - MMCIF ------------------------------------------------------------------ */
-static const unsigned int mmc0_data1_pins[] = {
+static const unsigned int mmc0_data_pins[] = {
-	/* D[0] */
-	RCAR_GP_PIN(0, 19),
-};
-static const unsigned int mmc0_data1_mux[] = {
-	MMC0_D0_MARK,
-};
-static const unsigned int mmc0_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21),
-	RCAR_GP_PIN(0, 2),
-};
-static const unsigned int mmc0_data4_mux[] = {
-	MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
-};
-static const unsigned int mmc0_data8_pins[] = {
 	/* D[0:7] */
 	RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21),
 	RCAR_GP_PIN(0, 2),  RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
 	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
 };
-static const unsigned int mmc0_data8_mux[] = {
+static const unsigned int mmc0_data_mux[] = {
 	MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
 	MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK,
 };
 static const unsigned int mmc0_ctrl_mux[] = {
 	MMC0_CMD_MARK, MMC0_CLK_MARK,
 };
-static const unsigned int mmc1_data1_pins[] = {
+static const unsigned int mmc1_data_pins[] = {
-	/* D[0] */
-	RCAR_GP_PIN(2, 8),
-};
-static const unsigned int mmc1_data1_mux[] = {
-	MMC1_D0_MARK,
-};
-static const unsigned int mmc1_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
-	RCAR_GP_PIN(2, 11),
-};
-static const unsigned int mmc1_data4_mux[] = {
-	MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
-};
-static const unsigned int mmc1_data8_pins[] = {
 	/* D[0:7] */
 	RCAR_GP_PIN(2, 8),  RCAR_GP_PIN(2, 9),  RCAR_GP_PIN(2, 10),
 	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
 	RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
 };
-static const unsigned int mmc1_data8_mux[] = {
+static const unsigned int mmc1_data_mux[] = {
 	MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
 	MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK,
 };
 	SCIF_CLK_D_MARK,
 };
 /* - SDHI0 ------------------------------------------------------------------ */
-static const unsigned int sdhi0_data1_pins[] = {
+static const unsigned int sdhi0_data_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(3, 21),
-};
-static const unsigned int sdhi0_data1_mux[] = {
-	SD0_DAT0_MARK,
-};
-static const unsigned int sdhi0_data4_pins[] = {
 	/* D[0:3] */
 	RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
 	RCAR_GP_PIN(3, 24),
 };
-static const unsigned int sdhi0_data4_mux[] = {
+static const unsigned int sdhi0_data_mux[] = {
 	SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
 };
 static const unsigned int sdhi0_ctrl_pins[] = {
 	SD0_WP_MARK,
 };
 /* - SDHI1 ------------------------------------------------------------------ */
-static const unsigned int sdhi1_data1_pins[] = {
+static const unsigned int sdhi1_data_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(0, 19),
-};
-static const unsigned int sdhi1_data1_mux[] = {
-	SD1_DAT0_MARK,
-};
-static const unsigned int sdhi1_data4_pins[] = {
 	/* D[0:3] */
 	RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21),
 	RCAR_GP_PIN(0, 2),
 };
-static const unsigned int sdhi1_data4_mux[] = {
+static const unsigned int sdhi1_data_mux[] = {
 	SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
 };
 static const unsigned int sdhi1_ctrl_pins[] = {
 	SD1_WP_MARK,
 };
 /* - SDHI2 ------------------------------------------------------------------ */
-static const unsigned int sdhi2_data1_pins[] = {
+static const unsigned int sdhi2_data_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(3, 1),
-};
-static const unsigned int sdhi2_data1_mux[] = {
-	SD2_DAT0_MARK,
-};
-static const unsigned int sdhi2_data4_pins[] = {
 	/* D[0:3] */
 	RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
 	RCAR_GP_PIN(3, 4),
 };
-static const unsigned int sdhi2_data4_mux[] = {
+static const unsigned int sdhi2_data_mux[] = {
 	SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
 };
 static const unsigned int sdhi2_ctrl_pins[] = {
 	SD2_WP_MARK,
 };
 /* - SDHI3 ------------------------------------------------------------------ */
-static const unsigned int sdhi3_data1_pins[] = {
+static const unsigned int sdhi3_data_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(1, 18),
-};
-static const unsigned int sdhi3_data1_mux[] = {
-	SD3_DAT0_MARK,
-};
-static const unsigned int sdhi3_data4_pins[] = {
 	/* D[0:3] */
 	RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 20),
 	RCAR_GP_PIN(1, 21),
 };
-static const unsigned int sdhi3_data4_mux[] = {
+static const unsigned int sdhi3_data_mux[] = {
 	SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
 };
 static const unsigned int sdhi3_ctrl_pins[] = {
 	SH_PFC_PIN_GROUP(lbsc_ex_cs3),
 	SH_PFC_PIN_GROUP(lbsc_ex_cs4),
 	SH_PFC_PIN_GROUP(lbsc_ex_cs5),
-	SH_PFC_PIN_GROUP(mmc0_data1),
+	BUS_DATA_PIN_GROUP(mmc0_data, 1),
-	SH_PFC_PIN_GROUP(mmc0_data4),
+	BUS_DATA_PIN_GROUP(mmc0_data, 4),
-	SH_PFC_PIN_GROUP(mmc0_data8),
+	BUS_DATA_PIN_GROUP(mmc0_data, 8),
 	SH_PFC_PIN_GROUP(mmc0_ctrl),
-	SH_PFC_PIN_GROUP(mmc1_data1),
+	BUS_DATA_PIN_GROUP(mmc1_data, 1),
-	SH_PFC_PIN_GROUP(mmc1_data4),
+	BUS_DATA_PIN_GROUP(mmc1_data, 4),
-	SH_PFC_PIN_GROUP(mmc1_data8),
+	BUS_DATA_PIN_GROUP(mmc1_data, 8),
 	SH_PFC_PIN_GROUP(mmc1_ctrl),
 	SH_PFC_PIN_GROUP(scif0_data),
 	SH_PFC_PIN_GROUP(scif0_clk),
 	SH_PFC_PIN_GROUP(scif_clk_b),
 	SH_PFC_PIN_GROUP(scif_clk_c),
 	SH_PFC_PIN_GROUP(scif_clk_d),
-	SH_PFC_PIN_GROUP(sdhi0_data1),
+	BUS_DATA_PIN_GROUP(sdhi0_data, 1),
-	SH_PFC_PIN_GROUP(sdhi0_data4),
+	BUS_DATA_PIN_GROUP(sdhi0_data, 4),
 	SH_PFC_PIN_GROUP(sdhi0_ctrl),
 	SH_PFC_PIN_GROUP(sdhi0_cd),
 	SH_PFC_PIN_GROUP(sdhi0_wp),
-	SH_PFC_PIN_GROUP(sdhi1_data1),
+	BUS_DATA_PIN_GROUP(sdhi1_data, 1),
-	SH_PFC_PIN_GROUP(sdhi1_data4),
+	BUS_DATA_PIN_GROUP(sdhi1_data, 4),
 	SH_PFC_PIN_GROUP(sdhi1_ctrl),
 	SH_PFC_PIN_GROUP(sdhi1_cd),
 	SH_PFC_PIN_GROUP(sdhi1_wp),
-	SH_PFC_PIN_GROUP(sdhi2_data1),
+	BUS_DATA_PIN_GROUP(sdhi2_data, 1),
-	SH_PFC_PIN_GROUP(sdhi2_data4),
+	BUS_DATA_PIN_GROUP(sdhi2_data, 4),
 	SH_PFC_PIN_GROUP(sdhi2_ctrl),
 	SH_PFC_PIN_GROUP(sdhi2_cd),
 	SH_PFC_PIN_GROUP(sdhi2_wp),
-	SH_PFC_PIN_GROUP(sdhi3_data1),
+	BUS_DATA_PIN_GROUP(sdhi3_data, 1),
-	SH_PFC_PIN_GROUP(sdhi3_data4),
+	BUS_DATA_PIN_GROUP(sdhi3_data, 4),
 	SH_PFC_PIN_GROUP(sdhi3_ctrl),
 	SH_PFC_PIN_GROUP(sdhi3_cd),
 	SH_PFC_PIN_GROUP(sdhi3_wp),
 	SH_PFC_FUNCTION(lbsc),
 	SH_PFC_FUNCTION(mmc0),
 	SH_PFC_FUNCTION(mmc1),
-	SH_PFC_FUNCTION(sdhi0),
-	SH_PFC_FUNCTION(sdhi1),
-	SH_PFC_FUNCTION(sdhi2),
-	SH_PFC_FUNCTION(sdhi3),
 	SH_PFC_FUNCTION(scif0),
 	SH_PFC_FUNCTION(scif1),
 	SH_PFC_FUNCTION(scif2),
 	SH_PFC_FUNCTION(scif4),
 	SH_PFC_FUNCTION(scif5),
 	SH_PFC_FUNCTION(scif_clk),
+	SH_PFC_FUNCTION(sdhi0),
+	SH_PFC_FUNCTION(sdhi1),
+	SH_PFC_FUNCTION(sdhi2),
+	SH_PFC_FUNCTION(sdhi3),
 	SH_PFC_FUNCTION(usb0),
 	SH_PFC_FUNCTION(usb1),
 	SH_PFC_FUNCTION(usb2),

drivers/pinctrl/renesas/pfc-r8a7790.c+208−322

 	FN_CAN1_TX, FN_DRACK0, FN_IETX_C, FN_RD_N,
 	FN_CAN0_TX, FN_SCIFA0_SCK_B, FN_RD_WR_N, FN_VI1_G3,
 	FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
-	FN_INTC_IRQ4_N, FN_WE0_N, FN_IECLK, FN_CAN_CLK,
+	FN_WE0_N, FN_IECLK, FN_CAN_CLK,
 	FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B,
 	FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
 	FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B,
-	FN_IERX_C, FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
+	FN_IERX_C, FN_EX_WAIT0, FN_IRQ3,
 	FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
 	FN_MSIOF0_SCK_B, FN_DREQ0_N, FN_VI1_HSYNC_N,
 	FN_VI1_HSYNC_N_B, FN_VI2_R7, FN_SSI_SCK78_C,
 	FN_SSI_WS78_B,
 	/* IPSR6 */
-	FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
+	FN_DACK0, FN_IRQ0, FN_SSI_SCK6_B,
 	FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C,
 	FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
 	FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1,
-	FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C,
+	FN_SSI_WS6_B, FN_SSI_SDATA8_C,
 	FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B,
-	FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
+	FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2,
 	FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B,
 	FN_ETH_CRS_DV, FN_STP_ISCLK_0_B,
 	FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,
 	CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK,
 	CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK,
 	VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK,
-	INTC_IRQ4_N_MARK, WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK,
+	WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK,
 	VI2_VSYNC_N_MARK, SCIFA0_TXD_B_MARK, VI2_VSYNC_N_B_MARK,
 	WE1_N_MARK, IERX_MARK, CAN1_RX_MARK, VI1_G4_MARK,
 	VI1_G4_B_MARK, VI2_R6_MARK, SCIFA0_CTS_N_B_MARK,
-	IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK, INTC_IRQ3_N_MARK,
+	IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK,
 	VI3_CLK_MARK, SCIFA0_RTS_N_B_MARK, HRX0_B_MARK,
 	MSIOF0_SCK_B_MARK, DREQ0_N_MARK, VI1_HSYNC_N_MARK,
 	VI1_HSYNC_N_B_MARK, VI2_R7_MARK, SSI_SCK78_C_MARK,
 	SSI_WS78_B_MARK,
-	DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK,
+	DACK0_MARK, IRQ0_MARK, SSI_SCK6_B_MARK,
 	VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK,
 	DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK,
 	SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK,
-	INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK,
+	SSI_WS6_B_MARK, SSI_SDATA8_C_MARK,
 	DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK,
-	MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK,
+	MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK,
 	SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK,
 	ETH_CRS_DV_MARK, STP_ISCLK_0_B_MARK,
 	TS_SDEN0_D_MARK, GLO_Q0_C_MARK, IIC2_SCL_E_MARK,
 	PINMUX_IPSR_MSEL(IP5_17_15, VI1_G3_B, SEL_VI1_1),
 	PINMUX_IPSR_GPSR(IP5_17_15, VI2_R5),
 	PINMUX_IPSR_MSEL(IP5_17_15, SCIFA0_RXD_B, SEL_SCFA_1),
-	PINMUX_IPSR_GPSR(IP5_17_15, INTC_IRQ4_N),
 	PINMUX_IPSR_GPSR(IP5_20_18, WE0_N),
 	PINMUX_IPSR_MSEL(IP5_20_18, IECLK, SEL_IEB_0),
 	PINMUX_IPSR_MSEL(IP5_20_18, CAN_CLK, SEL_CANCLK_0),
 	PINMUX_IPSR_MSEL(IP5_23_21, IERX_C, SEL_IEB_2),
 	PINMUX_IPSR_MSEL(IP5_26_24, EX_WAIT0, SEL_LBS_0),
 	PINMUX_IPSR_GPSR(IP5_26_24, IRQ3),
-	PINMUX_IPSR_GPSR(IP5_26_24, INTC_IRQ3_N),
 	PINMUX_IPSR_MSEL(IP5_26_24, VI3_CLK, SEL_VI3_0),
 	PINMUX_IPSR_MSEL(IP5_26_24, SCIFA0_RTS_N_B, SEL_SCFA_1),
 	PINMUX_IPSR_MSEL(IP5_26_24, HRX0_B, SEL_HSCIF0_1),
 	PINMUX_IPSR_GPSR(IP6_2_0, DACK0),
 	PINMUX_IPSR_GPSR(IP6_2_0, IRQ0),
-	PINMUX_IPSR_GPSR(IP6_2_0, INTC_IRQ0_N),
 	PINMUX_IPSR_MSEL(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1),
 	PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0),
 	PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1),
 	PINMUX_IPSR_MSEL(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1),
 	PINMUX_IPSR_GPSR(IP6_8_6, DACK1),
 	PINMUX_IPSR_GPSR(IP6_8_6, IRQ1),
-	PINMUX_IPSR_GPSR(IP6_8_6, INTC_IRQ1_N),
 	PINMUX_IPSR_MSEL(IP6_8_6, SSI_WS6_B, SEL_SSI6_1),
 	PINMUX_IPSR_MSEL(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2),
 	PINMUX_IPSR_GPSR(IP6_10_9, DREQ2_N),
 	PINMUX_IPSR_MSEL(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1),
 	PINMUX_IPSR_GPSR(IP6_13_11, DACK2),
 	PINMUX_IPSR_GPSR(IP6_13_11, IRQ2),
-	PINMUX_IPSR_GPSR(IP6_13_11, INTC_IRQ2_N),
 	PINMUX_IPSR_MSEL(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1),
 	PINMUX_IPSR_MSEL(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1),
 	PINMUX_IPSR_MSEL(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1),
 #endif /* CONFIG_PINCTRL_PFC_R8A7790 */
 /* - MMCIF0 ----------------------------------------------------------------- */
-static const unsigned int mmc0_data1_pins[] = {
+static const unsigned int mmc0_data_pins[] = {
-	/* D[0] */
-	RCAR_GP_PIN(3, 18),
-};
-static const unsigned int mmc0_data1_mux[] = {
-	MMC0_D0_MARK,
-};
-static const unsigned int mmc0_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
-	RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
-};
-static const unsigned int mmc0_data4_mux[] = {
-	MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
-};
-static const unsigned int mmc0_data8_pins[] = {
 	/* D[0:7] */
 	RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
 	RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
 	RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
 	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
 };
-static const unsigned int mmc0_data8_mux[] = {
+static const unsigned int mmc0_data_mux[] = {
 	MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
 	MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK,
 };
 	MMC0_CLK_MARK, MMC0_CMD_MARK,
 };
 /* - MMCIF1 ----------------------------------------------------------------- */
-static const unsigned int mmc1_data1_pins[] = {
+static const unsigned int mmc1_data_pins[] = {
-	/* D[0] */
-	RCAR_GP_PIN(3, 26),
-};
-static const unsigned int mmc1_data1_mux[] = {
-	MMC1_D0_MARK,
-};
-static const unsigned int mmc1_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
-	RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
-};
-static const unsigned int mmc1_data4_mux[] = {
-	MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
-};
-static const unsigned int mmc1_data8_pins[] = {
 	/* D[0:7] */
 	RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
 	RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
 	RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
 	RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
 };
-static const unsigned int mmc1_data8_mux[] = {
+static const unsigned int mmc1_data_mux[] = {
 	MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
 	MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK,
 };
 static const unsigned int qspi_ctrl_mux[] = {
 	SPCLK_MARK, SSL_MARK,
 };
-static const unsigned int qspi_data2_pins[] = {
+static const unsigned int qspi_data_pins[] = {
-	/* MOSI_IO0, MISO_IO1 */
-	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
-};
-static const unsigned int qspi_data2_mux[] = {
-	MOSI_IO0_MARK, MISO_IO1_MARK,
-};
-static const unsigned int qspi_data4_pins[] = {
 	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
 	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
 	RCAR_GP_PIN(1, 8),
 };
-static const unsigned int qspi_data4_mux[] = {
+static const unsigned int qspi_data_mux[] = {
 	MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
 };
 /* - SCIF0 ------------------------------------------------------------------ */
 	SCIF_CLK_B_MARK,
 };
 /* - SDHI0 ------------------------------------------------------------------ */
-static const unsigned int sdhi0_data1_pins[] = {
+static const unsigned int sdhi0_data_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(3, 2),
-};
-static const unsigned int sdhi0_data1_mux[] = {
-	SD0_DAT0_MARK,
-};
-static const unsigned int sdhi0_data4_pins[] = {
 	/* D[0:3] */
 	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
 };
-static const unsigned int sdhi0_data4_mux[] = {
+static const unsigned int sdhi0_data_mux[] = {
 	SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
 };
 static const unsigned int sdhi0_ctrl_pins[] = {
 	SD0_WP_MARK,
 };
 /* - SDHI1 ------------------------------------------------------------------ */
-static const unsigned int sdhi1_data1_pins[] = {
+static const unsigned int sdhi1_data_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(3, 10),
-};
-static const unsigned int sdhi1_data1_mux[] = {
-	SD1_DAT0_MARK,
-};
-static const unsigned int sdhi1_data4_pins[] = {
 	/* D[0:3] */
 	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
 };
-static const unsigned int sdhi1_data4_mux[] = {
+static const unsigned int sdhi1_data_mux[] = {
 	SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
 };
 static const unsigned int sdhi1_ctrl_pins[] = {
 	SD1_WP_MARK,
 };
 /* - SDHI2 ------------------------------------------------------------------ */
-static const unsigned int sdhi2_data1_pins[] = {
+static const unsigned int sdhi2_data_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(3, 18),
-};
-static const unsigned int sdhi2_data1_mux[] = {
-	SD2_DAT0_MARK,
-};
-static const unsigned int sdhi2_data4_pins[] = {
 	/* D[0:3] */
 	RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
 };
-static const unsigned int sdhi2_data4_mux[] = {
+static const unsigned int sdhi2_data_mux[] = {
 	SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
 };
 static const unsigned int sdhi2_ctrl_pins[] = {
 	SD2_WP_MARK,
 };
 /* - SDHI3 ------------------------------------------------------------------ */
-static const unsigned int sdhi3_data1_pins[] = {
+static const unsigned int sdhi3_data_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(3, 26),
-};
-static const unsigned int sdhi3_data1_mux[] = {
-	SD3_DAT0_MARK,
-};
-static const unsigned int sdhi3_data4_pins[] = {
 	/* D[0:3] */
 	RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
 };
-static const unsigned int sdhi3_data4_mux[] = {
+static const unsigned int sdhi3_data_mux[] = {
 	SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
 };
 static const unsigned int sdhi3_ctrl_pins[] = {
 };
 /* - USB0 ------------------------------------------------------------------- */
 static const unsigned int usb0_pins[] = {
-	/* PWEN, OVC/VBUS */
+	/* OVC/VBUS, PWEN */
-	RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
+	RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 18),
 };
 static const unsigned int usb0_mux[] = {
-	USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
+	USB0_OVC_VBUS_MARK, USB0_PWEN_MARK,
-};
-static const unsigned int usb0_ovc_vbus_pins[] = {
-	/* OVC/VBUS */
-	RCAR_GP_PIN(5, 19),
-};
-static const unsigned int usb0_ovc_vbus_mux[] = {
-	USB0_OVC_VBUS_MARK,
 };
 /* - USB1 ------------------------------------------------------------------- */
 static const unsigned int usb1_pins[] = {
 static const unsigned int usb1_mux[] = {
 	USB1_PWEN_MARK, USB1_OVC_MARK,
 };
-static const unsigned int usb1_pwen_pins[] = {
-	/* PWEN */
-	RCAR_GP_PIN(5, 20),
-};
-static const unsigned int usb1_pwen_mux[] = {
-	USB1_PWEN_MARK,
-};
 /* - USB2 ------------------------------------------------------------------- */
 static const unsigned int usb2_pins[] = {
 	/* PWEN, OVC */
 	USB2_PWEN_MARK, USB2_OVC_MARK,
 };
 /* - VIN0 ------------------------------------------------------------------- */
-static const union vin_data vin0_data_pins = {
+static const unsigned int vin0_data_pins[] = {
-	.data24 = {
+	/* B */
-		/* B */
+	RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
-		RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
+	RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
-		RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
+	RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
-		RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
+	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
-		RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
+	/* G */
-		/* G */
+	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
-		RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
+	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
-		RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
-		RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
-		RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+	/* R */
-		/* R */
+	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
-		RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
-		RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
+	RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
-		RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
+	RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
-		RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
-	},
 };
-static const union vin_data vin0_data_mux = {
+static const unsigned int vin0_data_mux[] = {
-	.data24 = {
+	/* B */
-		/* B */
+	VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
-		VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
+	VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
-		VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
+	VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
-		VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
+	VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
-		VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
+	/* G */
-		/* G */
+	VI0_G0_MARK, VI0_G1_MARK,
-		VI0_G0_MARK, VI0_G1_MARK,
+	VI0_G2_MARK, VI0_G3_MARK,
-		VI0_G2_MARK, VI0_G3_MARK,
+	VI0_G4_MARK, VI0_G5_MARK,
-		VI0_G4_MARK, VI0_G5_MARK,
+	VI0_G6_MARK, VI0_G7_MARK,
-		VI0_G6_MARK, VI0_G7_MARK,
+	/* R */
-		/* R */
+	VI0_R0_MARK, VI0_R1_MARK,
-		VI0_R0_MARK, VI0_R1_MARK,
+	VI0_R2_MARK, VI0_R3_MARK,
-		VI0_R2_MARK, VI0_R3_MARK,
+	VI0_R4_MARK, VI0_R5_MARK,
-		VI0_R4_MARK, VI0_R5_MARK,
+	VI0_R6_MARK, VI0_R7_MARK,
-		VI0_R6_MARK, VI0_R7_MARK,
-	},
 };
 static const unsigned int vin0_data18_pins[] = {
 	/* B */
 	VI0_CLK_MARK,
 };
 /* - VIN1 ------------------------------------------------------------------- */
-static const union vin_data vin1_data_pins = {
+static const unsigned int vin1_data_pins[] = {
-	.data24 = {
+	/* B */
-		/* B */
+	RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
-		RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
+	RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
-		RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
+	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
-		RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
+	RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
-		RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
+	/* G */
-		/* G */
+	RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
-		RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
+	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
-		RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
+	RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
-		RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
+	RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
-		RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
+	/* R */
-		/* R */
+	RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
-		RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
+	RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
-		RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
+	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
-		RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
+	RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
-		RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
-	},
 };
-static const union vin_data vin1_data_mux = {
+static const unsigned int vin1_data_mux[] = {
-	.data24 = {
+	/* B */
-		/* B */
+	VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK,
-		VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK,
+	VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK,
-		VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK,
+	VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
-		VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
+	VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
-		VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
+	/* G */
-		/* G */
+	VI1_G0_MARK, VI1_G1_MARK,
-		VI1_G0_MARK, VI1_G1_MARK,
+	VI1_G2_MARK, VI1_G3_MARK,
-		VI1_G2_MARK, VI1_G3_MARK,
+	VI1_G4_MARK, VI1_G5_MARK,
-		VI1_G4_MARK, VI1_G5_MARK,
+	VI1_G6_MARK, VI1_G7_MARK,
-		VI1_G6_MARK, VI1_G7_MARK,
+	/* R */
-		/* R */
+	VI1_R0_MARK, VI1_R1_MARK,
-		VI1_R0_MARK, VI1_R1_MARK,
+	VI1_R2_MARK, VI1_R3_MARK,
-		VI1_R2_MARK, VI1_R3_MARK,
+	VI1_R4_MARK, VI1_R5_MARK,
-		VI1_R4_MARK, VI1_R5_MARK,
+	VI1_R6_MARK, VI1_R7_MARK,
-		VI1_R6_MARK, VI1_R7_MARK,
-	},
 };
 static const unsigned int vin1_data18_pins[] = {
 	/* B */
 	VI1_R4_MARK, VI1_R5_MARK,
 	VI1_R6_MARK, VI1_R7_MARK,
 };
-static const union vin_data vin1_data_b_pins = {
+static const unsigned int vin1_data_b_pins[] = {
-	.data24 = {
+	/* B */
-		/* B */
+	RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
-		RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
+	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
-		RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
+	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
-		RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
+	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
-		RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
+	/* G */
-		/* G */
+	RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
-		RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
+	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
-		RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
+	RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
-		RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
+	RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
-		RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
+	/* R */
-		/* R */
+	RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
-		RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
+	RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
-		RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
+	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
-		RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
+	RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
-		RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
-	},
 };
-static const union vin_data vin1_data_b_mux = {
+static const unsigned int vin1_data_b_mux[] = {
-	.data24 = {
+	/* B */
-		/* B */
+	VI1_DATA0_VI1_B0_B_MARK, VI1_DATA1_VI1_B1_B_MARK,
-		VI1_DATA0_VI1_B0_B_MARK, VI1_DATA1_VI1_B1_B_MARK,
+	VI1_DATA2_VI1_B2_B_MARK, VI1_DATA3_VI1_B3_B_MARK,
-		VI1_DATA2_VI1_B2_B_MARK, VI1_DATA3_VI1_B3_B_MARK,
+	VI1_DATA4_VI1_B4_B_MARK, VI1_DATA5_VI1_B5_B_MARK,
-		VI1_DATA4_VI1_B4_B_MARK, VI1_DATA5_VI1_B5_B_MARK,
+	VI1_DATA6_VI1_B6_B_MARK, VI1_DATA7_VI1_B7_B_MARK,
-		VI1_DATA6_VI1_B6_B_MARK, VI1_DATA7_VI1_B7_B_MARK,
+	/* G */
-		/* G */
+	VI1_G0_B_MARK, VI1_G1_B_MARK,
-		VI1_G0_B_MARK, VI1_G1_B_MARK,
+	VI1_G2_B_MARK, VI1_G3_B_MARK,
-		VI1_G2_B_MARK, VI1_G3_B_MARK,
+	VI1_G4_B_MARK, VI1_G5_B_MARK,
-		VI1_G4_B_MARK, VI1_G5_B_MARK,
+	VI1_G6_B_MARK, VI1_G7_B_MARK,
-		VI1_G6_B_MARK, VI1_G7_B_MARK,
+	/* R */
-		/* R */
+	VI1_R0_B_MARK, VI1_R1_B_MARK,
-		VI1_R0_B_MARK, VI1_R1_B_MARK,
+	VI1_R2_B_MARK, VI1_R3_B_MARK,
-		VI1_R2_B_MARK, VI1_R3_B_MARK,
+	VI1_R4_B_MARK, VI1_R5_B_MARK,
-		VI1_R4_B_MARK, VI1_R5_B_MARK,
+	VI1_R6_B_MARK, VI1_R7_B_MARK,
-		VI1_R6_B_MARK, VI1_R7_B_MARK,
-	},
 };
 static const unsigned int vin1_data18_b_pins[] = {
 	/* B */
 	VI1_CLK_B_MARK,
 };
 /* - VIN2 ----------------------------------------------------------------- */
-static const union vin_data vin2_data_pins = {
+static const unsigned int vin2_data_pins[] = {
-	.data24 = {
-		/* B */
-		RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
-		RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
-		RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
-		RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
-		/* G */
-		RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
-		RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
-		RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
-		RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
-		/* R */
-		RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
-		RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
-		RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
-		RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
-	},
-};
-static const union vin_data vin2_data_mux = {
-	.data24 = {
-		/* B */
-		VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK,
-		VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK,
-		VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
-		VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
-		/* G */
-		VI2_G0_MARK, VI2_G1_MARK,
-		VI2_G2_MARK, VI2_G3_MARK,
-		VI2_G4_MARK, VI2_G5_MARK,
-		VI2_G6_MARK, VI2_G7_MARK,
-		/* R */
-		VI2_R0_MARK, VI2_R1_MARK,
-		VI2_R2_MARK, VI2_R3_MARK,
-		VI2_R4_MARK, VI2_R5_MARK,
-		VI2_R6_MARK, VI2_R7_MARK,
-	},
-};
-static const unsigned int vin2_data18_pins[] = {
 	/* B */
+	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
 	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
 	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
 	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
 	/* G */
+	RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
 	RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
 	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
 	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
 	/* R */
+	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
 	RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
 	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
 	RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
 };
-static const unsigned int vin2_data18_mux[] = {
+static const unsigned int vin2_data_mux[] = {
 	/* B */
+	VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK,
 	VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK,
 	VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
 	VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
 	/* G */
+	VI2_G0_MARK, VI2_G1_MARK,
 	VI2_G2_MARK, VI2_G3_MARK,
 	VI2_G4_MARK, VI2_G5_MARK,
 	VI2_G6_MARK, VI2_G7_MARK,
 	/* R */
+	VI2_R0_MARK, VI2_R1_MARK,
 	VI2_R2_MARK, VI2_R3_MARK,
 	VI2_R4_MARK, VI2_R5_MARK,
 	VI2_R6_MARK, VI2_R7_MARK,
 };
-static const unsigned int vin2_g8_pins[] = {
+static const unsigned int vin2_data18_pins[] = {
-	RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
+	/* B */
+	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
+	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+	/* G */
 	RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
 	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
 	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+	/* R */
+	RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
+	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
+	RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
 };
-static const unsigned int vin2_g8_mux[] = {
+static const unsigned int vin2_data18_mux[] = {
-	VI2_G0_MARK, VI2_G1_MARK,
+	/* B */
+	VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK,
+	VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
+	VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
+	/* G */
 	VI2_G2_MARK, VI2_G3_MARK,
 	VI2_G4_MARK, VI2_G5_MARK,
 	VI2_G6_MARK, VI2_G7_MARK,
+	/* R */
+	VI2_R2_MARK, VI2_R3_MARK,
+	VI2_R4_MARK, VI2_R5_MARK,
+	VI2_R6_MARK, VI2_R7_MARK,
 };
 static const unsigned int vin2_sync_pins[] = {
 	RCAR_GP_PIN(1, 16), /* HSYNC */
 		SH_PFC_PIN_GROUP(intc_irq1),
 		SH_PFC_PIN_GROUP(intc_irq2),
 		SH_PFC_PIN_GROUP(intc_irq3),
-		SH_PFC_PIN_GROUP(mmc0_data1),
+		BUS_DATA_PIN_GROUP(mmc0_data, 1),
-		SH_PFC_PIN_GROUP(mmc0_data4),
+		BUS_DATA_PIN_GROUP(mmc0_data, 4),
-		SH_PFC_PIN_GROUP(mmc0_data8),
+		BUS_DATA_PIN_GROUP(mmc0_data, 8),
 		SH_PFC_PIN_GROUP(mmc0_ctrl),
-		SH_PFC_PIN_GROUP(mmc1_data1),
+		BUS_DATA_PIN_GROUP(mmc1_data, 1),
-		SH_PFC_PIN_GROUP(mmc1_data4),
+		BUS_DATA_PIN_GROUP(mmc1_data, 4),
-		SH_PFC_PIN_GROUP(mmc1_data8),
+		BUS_DATA_PIN_GROUP(mmc1_data, 8),
 		SH_PFC_PIN_GROUP(mmc1_ctrl),
 		SH_PFC_PIN_GROUP(msiof0_clk),
 		SH_PFC_PIN_GROUP(msiof0_sync),
 		SH_PFC_PIN_GROUP(pwm5),
 		SH_PFC_PIN_GROUP(pwm6),
 		SH_PFC_PIN_GROUP(qspi_ctrl),
-		SH_PFC_PIN_GROUP(qspi_data2),
+		BUS_DATA_PIN_GROUP(qspi_data, 2),
-		SH_PFC_PIN_GROUP(qspi_data4),
+		BUS_DATA_PIN_GROUP(qspi_data, 4),
 		SH_PFC_PIN_GROUP(scif0_data),
 		SH_PFC_PIN_GROUP(scif0_clk),
 		SH_PFC_PIN_GROUP(scif0_ctrl),
 		SH_PFC_PIN_GROUP(scifb2_data_c),
 		SH_PFC_PIN_GROUP(scif_clk),
 		SH_PFC_PIN_GROUP(scif_clk_b),
-		SH_PFC_PIN_GROUP(sdhi0_data1),
+		BUS_DATA_PIN_GROUP(sdhi0_data, 1),
-		SH_PFC_PIN_GROUP(sdhi0_data4),
+		BUS_DATA_PIN_GROUP(sdhi0_data, 4),
 		SH_PFC_PIN_GROUP(sdhi0_ctrl),
 		SH_PFC_PIN_GROUP(sdhi0_cd),
 		SH_PFC_PIN_GROUP(sdhi0_wp),
-		SH_PFC_PIN_GROUP(sdhi1_data1),
+		BUS_DATA_PIN_GROUP(sdhi1_data, 1),
-		SH_PFC_PIN_GROUP(sdhi1_data4),
+		BUS_DATA_PIN_GROUP(sdhi1_data, 4),
 		SH_PFC_PIN_GROUP(sdhi1_ctrl),
 		SH_PFC_PIN_GROUP(sdhi1_cd),
 		SH_PFC_PIN_GROUP(sdhi1_wp),
-		SH_PFC_PIN_GROUP(sdhi2_data1),
+		BUS_DATA_PIN_GROUP(sdhi2_data, 1),
-		SH_PFC_PIN_GROUP(sdhi2_data4),
+		BUS_DATA_PIN_GROUP(sdhi2_data, 4),
 		SH_PFC_PIN_GROUP(sdhi2_ctrl),
 		SH_PFC_PIN_GROUP(sdhi2_cd),
 		SH_PFC_PIN_GROUP(sdhi2_wp),
-		SH_PFC_PIN_GROUP(sdhi3_data1),
+		BUS_DATA_PIN_GROUP(sdhi3_data, 1),
-		SH_PFC_PIN_GROUP(sdhi3_data4),
+		BUS_DATA_PIN_GROUP(sdhi3_data, 4),
 		SH_PFC_PIN_GROUP(sdhi3_ctrl),
 		SH_PFC_PIN_GROUP(sdhi3_cd),
 		SH_PFC_PIN_GROUP(sdhi3_wp),
 		SH_PFC_PIN_GROUP(tpu0_to2),
 		SH_PFC_PIN_GROUP(tpu0_to3),
 		SH_PFC_PIN_GROUP(usb0),
-		SH_PFC_PIN_GROUP(usb0_ovc_vbus),
+		SH_PFC_PIN_GROUP_SUBSET(usb0_ovc_vbus, usb0, 0, 1),
 		SH_PFC_PIN_GROUP(usb1),
-		SH_PFC_PIN_GROUP(usb1_pwen),
+		SH_PFC_PIN_GROUP_SUBSET(usb1_pwen, usb1, 0, 1),
 		SH_PFC_PIN_GROUP(usb2),
-		VIN_DATA_PIN_GROUP(vin0_data, 24),
+		BUS_DATA_PIN_GROUP(vin0_data, 24),
-		VIN_DATA_PIN_GROUP(vin0_data, 20),
+		BUS_DATA_PIN_GROUP(vin0_data, 20),
 		SH_PFC_PIN_GROUP(vin0_data18),
-		VIN_DATA_PIN_GROUP(vin0_data, 16),
+		BUS_DATA_PIN_GROUP(vin0_data, 16),
-		VIN_DATA_PIN_GROUP(vin0_data, 12),
+		BUS_DATA_PIN_GROUP(vin0_data, 12),
-		VIN_DATA_PIN_GROUP(vin0_data, 10),
+		BUS_DATA_PIN_GROUP(vin0_data, 10),
-		VIN_DATA_PIN_GROUP(vin0_data, 8),
+		BUS_DATA_PIN_GROUP(vin0_data, 8),
-		VIN_DATA_PIN_GROUP(vin0_data, 4),
+		BUS_DATA_PIN_GROUP(vin0_data, 4),
 		SH_PFC_PIN_GROUP(vin0_sync),
 		SH_PFC_PIN_GROUP(vin0_field),
 		SH_PFC_PIN_GROUP(vin0_clkenb),
 		SH_PFC_PIN_GROUP(vin0_clk),
-		VIN_DATA_PIN_GROUP(vin1_data, 24),
+		BUS_DATA_PIN_GROUP(vin1_data, 24),
-		VIN_DATA_PIN_GROUP(vin1_data, 20),
+		BUS_DATA_PIN_GROUP(vin1_data, 20),
 		SH_PFC_PIN_GROUP(vin1_data18),
-		VIN_DATA_PIN_GROUP(vin1_data, 16),
+		BUS_DATA_PIN_GROUP(vin1_data, 16),
-		VIN_DATA_PIN_GROUP(vin1_data, 12),
+		BUS_DATA_PIN_GROUP(vin1_data, 12),
-		VIN_DATA_PIN_GROUP(vin1_data, 10),
+		BUS_DATA_PIN_GROUP(vin1_data, 10),
-		VIN_DATA_PIN_GROUP(vin1_data, 8),
+		BUS_DATA_PIN_GROUP(vin1_data, 8),
-		VIN_DATA_PIN_GROUP(vin1_data, 4),
+		BUS_DATA_PIN_GROUP(vin1_data, 4),
-		VIN_DATA_PIN_GROUP(vin1_data, 24, _b),
+		BUS_DATA_PIN_GROUP(vin1_data, 24, _b),
-		VIN_DATA_PIN_GROUP(vin1_data, 20, _b),
+		BUS_DATA_PIN_GROUP(vin1_data, 20, _b),
 		SH_PFC_PIN_GROUP(vin1_data18_b),
-		VIN_DATA_PIN_GROUP(vin1_data, 16, _b),
+		BUS_DATA_PIN_GROUP(vin1_data, 16, _b),
-		VIN_DATA_PIN_GROUP(vin1_data, 12, _b),
+		BUS_DATA_PIN_GROUP(vin1_data, 12, _b),
-		VIN_DATA_PIN_GROUP(vin1_data, 10, _b),
+		BUS_DATA_PIN_GROUP(vin1_data, 10, _b),
-		VIN_DATA_PIN_GROUP(vin1_data, 8, _b),
+		BUS_DATA_PIN_GROUP(vin1_data, 8, _b),
-		VIN_DATA_PIN_GROUP(vin1_data, 4, _b),
+		BUS_DATA_PIN_GROUP(vin1_data, 4, _b),
 		SH_PFC_PIN_GROUP(vin1_sync),
 		SH_PFC_PIN_GROUP(vin1_sync_b),
 		SH_PFC_PIN_GROUP(vin1_field),
 		SH_PFC_PIN_GROUP(vin1_clkenb_b),
 		SH_PFC_PIN_GROUP(vin1_clk),
 		SH_PFC_PIN_GROUP(vin1_clk_b),
-		VIN_DATA_PIN_GROUP(vin2_data, 24),
+		BUS_DATA_PIN_GROUP(vin2_data, 24),
 		SH_PFC_PIN_GROUP(vin2_data18),
-		VIN_DATA_PIN_GROUP(vin2_data, 16),
+		BUS_DATA_PIN_GROUP(vin2_data, 16),
-		VIN_DATA_PIN_GROUP(vin2_data, 8),
+		BUS_DATA_PIN_GROUP(vin2_data, 8),
-		VIN_DATA_PIN_GROUP(vin2_data, 4),
+		BUS_DATA_PIN_GROUP(vin2_data, 4),
-		SH_PFC_PIN_GROUP(vin2_g8),
+		SH_PFC_PIN_GROUP_SUBSET(vin2_g8, vin2_data, 8, 8),
 		SH_PFC_PIN_GROUP(vin2_sync),
 		SH_PFC_PIN_GROUP(vin2_field),
 		SH_PFC_PIN_GROUP(vin2_clkenb),
 	.common = {
 		SH_PFC_FUNCTION(audio_clk),
 		SH_PFC_FUNCTION(avb),
-		SH_PFC_FUNCTION(du),
 		SH_PFC_FUNCTION(can0),
 		SH_PFC_FUNCTION(can1),
 		SH_PFC_FUNCTION(can_clk),
+		SH_PFC_FUNCTION(du),
 		SH_PFC_FUNCTION(du0),
 		SH_PFC_FUNCTION(du1),
 		SH_PFC_FUNCTION(du2),
 		FN_DREQ0_N, FN_VI1_HSYNC_N, FN_VI1_HSYNC_N_B, FN_VI2_R7,
 		FN_SSI_SCK78_C, FN_SSI_WS78_B, 0, 0,
 		/* IP5_26_24 [3] */
-		FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
+		FN_EX_WAIT0, FN_IRQ3, 0, FN_VI3_CLK, FN_SCIFA0_RTS_N_B,
-		FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
+		FN_HRX0_B, FN_MSIOF0_SCK_B, 0,
-		FN_MSIOF0_SCK_B, 0,
 		/* IP5_23_21 [3] */
 		FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
 		FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, FN_IERX_C,
 		FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 0, 0,
 		/* IP5_17_15 [3] */
 		FN_RD_WR_N, FN_VI1_G3, FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
-		FN_INTC_IRQ4_N, 0, 0,
+		0, 0, 0,
 		/* IP5_14_13 [2] */
 		FN_RD_N, FN_CAN0_TX, FN_SCIFA0_SCK_B, 0,
 		/* IP5_12_10 [3] */
 		FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,
 		FN_I2C2_SCL_E, 0,
 		/* IP6_13_11 [3] */
-		FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
+		FN_DACK2, FN_IRQ2, 0, FN_SSI_SDATA6_B, FN_HRTS0_N_B,
-		FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0,
+		FN_MSIOF0_RXD_B, 0, 0,
 		/* IP6_10_9 [2] */
 		FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B,
 		/* IP6_8_6 [3] */
-		FN_DACK1, FN_IRQ1, FN_INTC_IRQ1_N, FN_SSI_WS6_B,
+		FN_DACK1, FN_IRQ1, 0, FN_SSI_WS6_B, FN_SSI_SDATA8_C, 0, 0, 0,
-		FN_SSI_SDATA8_C, 0, 0, 0,
 		/* IP6_5_3 [3] */
 		FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
 		FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0,
 		/* IP6_2_0 [3] */
-		FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
+		FN_DACK0, FN_IRQ0, 0, FN_SSI_SCK6_B, FN_VI1_VSYNC_N,
-		FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, ))
+		FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, ))
 	},
 	{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
 			     GROUP(1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3),
 	{ },
 };
-static int r8a7790_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
+static int r8a7790_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
 {
 	if (pin < RCAR_GP_PIN(3, 0) || pin > RCAR_GP_PIN(3, 31))
 		return -EINVAL;
 	return 0;
 }
-static const struct sh_pfc_soc_operations r8a7790_pinmux_ops = {
+static const struct sh_pfc_soc_operations r8a7790_pfc_ops = {
 	.init = r8a7790_pinmux_soc_init,
 	.pin_to_pocctrl = r8a7790_pin_to_pocctrl,
 	.get_bias = rcar_pinmux_get_bias,
 #ifdef CONFIG_PINCTRL_PFC_R8A7742
 const struct sh_pfc_soc_info r8a7742_pinmux_info = {
 	.name = "r8a77420_pfc",
-	.ops = &r8a7790_pinmux_ops,
+	.ops = &r8a7790_pfc_ops,
 	.unlock_reg = 0xe6060000, /* PMMR */
 	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
 #ifdef CONFIG_PINCTRL_PFC_R8A7790
 const struct sh_pfc_soc_info r8a7790_pinmux_info = {
 	.name = "r8a77900_pfc",
-	.ops = &r8a7790_pinmux_ops,
+	.ops = &r8a7790_pfc_ops,
 	.unlock_reg = 0xe6060000, /* PMMR */
 	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },

drivers/pinctrl/renesas/pfc-r8a7791.c+126−196

 	FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
 	FN_SCIFA2_RXD, FN_FMIN_E,
 	FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
-	FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N,
+	FN_IRQ0, FN_SCIFB1_RXD_D,
-	FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N,
+	FN_IRQ1, FN_SCIFB1_SCK_C,
-	FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N,
+	FN_IRQ2, FN_SCIFB1_TXD_D,
-	FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
+	FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E,
-	FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N,
+	FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E,
 	FN_IRQ5, FN_HTX1_C, FN_I2C1_SCL_E, FN_MSIOF2_SCK_E,
 	FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, FN_I2C1_SDA_E, FN_MSIOF2_SYNC_E,
 	FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, FN_GPS_CLK_C, FN_GPS_CLK_D,
 	AUDIO_CLKC_MARK, SCIFB0_SCK_C_MARK, MSIOF1_SYNC_B_MARK, RX2_MARK,
 	SCIFA2_RXD_MARK, FMIN_E_MARK,
 	AUDIO_CLKOUT_MARK, MSIOF1_SS1_B_MARK, TX2_MARK, SCIFA2_TXD_MARK,
-	IRQ0_MARK, SCIFB1_RXD_D_MARK, INTC_IRQ0_N_MARK,
+	IRQ0_MARK, SCIFB1_RXD_D_MARK,
-	IRQ1_MARK, SCIFB1_SCK_C_MARK, INTC_IRQ1_N_MARK,
+	IRQ1_MARK, SCIFB1_SCK_C_MARK,
-	IRQ2_MARK, SCIFB1_TXD_D_MARK, INTC_IRQ2_N_MARK,
+	IRQ2_MARK, SCIFB1_TXD_D_MARK,
-	IRQ3_MARK, I2C4_SCL_C_MARK, MSIOF2_TXD_E_MARK, INTC_IRQ3_N_MARK,
+	IRQ3_MARK, I2C4_SCL_C_MARK, MSIOF2_TXD_E_MARK,
 	IRQ4_MARK, HRX1_C_MARK, I2C4_SDA_C_MARK,
-	MSIOF2_RXD_E_MARK, INTC_IRQ4_N_MARK,
+	MSIOF2_RXD_E_MARK,
 	IRQ5_MARK, HTX1_C_MARK, I2C1_SCL_E_MARK, MSIOF2_SCK_E_MARK,
 	IRQ6_MARK, HSCK1_C_MARK, MSIOF1_SS2_B_MARK,
 	I2C1_SDA_E_MARK, MSIOF2_SYNC_E_MARK,
 	PINMUX_IPSR_MSEL(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0),
 	PINMUX_IPSR_GPSR(IP6_9_8, IRQ0),
 	PINMUX_IPSR_MSEL(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3),
-	PINMUX_IPSR_GPSR(IP6_9_8, INTC_IRQ0_N),
 	PINMUX_IPSR_GPSR(IP6_11_10, IRQ1),
 	PINMUX_IPSR_MSEL(IP6_11_10, SCIFB1_SCK_C, SEL_SCIFB1_2),
-	PINMUX_IPSR_GPSR(IP6_11_10, INTC_IRQ1_N),
 	PINMUX_IPSR_GPSR(IP6_13_12, IRQ2),
 	PINMUX_IPSR_MSEL(IP6_13_12, SCIFB1_TXD_D, SEL_SCIFB1_3),
-	PINMUX_IPSR_GPSR(IP6_13_12, INTC_IRQ2_N),
 	PINMUX_IPSR_GPSR(IP6_15_14, IRQ3),
 	PINMUX_IPSR_MSEL(IP6_15_14, I2C4_SCL_C, SEL_I2C4_2),
 	PINMUX_IPSR_MSEL(IP6_15_14, MSIOF2_TXD_E, SEL_SOF2_4),
-	PINMUX_IPSR_GPSR(IP6_15_14, INTC_IRQ4_N),
 	PINMUX_IPSR_GPSR(IP6_18_16, IRQ4),
 	PINMUX_IPSR_MSEL(IP6_18_16, HRX1_C, SEL_HSCIF1_2),
 	PINMUX_IPSR_MSEL(IP6_18_16, I2C4_SDA_C, SEL_I2C4_2),
 	PINMUX_IPSR_MSEL(IP6_18_16, MSIOF2_RXD_E, SEL_SOF2_4),
-	PINMUX_IPSR_GPSR(IP6_18_16, INTC_IRQ4_N),
 	PINMUX_IPSR_GPSR(IP6_20_19, IRQ5),
 	PINMUX_IPSR_MSEL(IP6_20_19, HTX1_C, SEL_HSCIF1_2),
 	PINMUX_IPSR_MSEL(IP6_20_19, I2C1_SCL_E, SEL_I2C1_4),
 static const unsigned int hscif1_data_d_mux[] = {
 	HRX1_D_MARK, HTX1_D_MARK,
 };
-static const unsigned int hscif1_data_e_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
-};
-static const unsigned int hscif1_data_e_mux[] = {
-	HRX1_C_MARK, HTX1_C_MARK,
-};
 static const unsigned int hscif1_clk_e_pins[] = {
 	/* SCK */
 	RCAR_GP_PIN(2, 6),
 #endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */
 /* - MMCIF ------------------------------------------------------------------ */
-static const unsigned int mmc_data1_pins[] = {
+static const unsigned int mmc_data_pins[] = {
-	/* D[0] */
-	RCAR_GP_PIN(6, 18),
-};
-static const unsigned int mmc_data1_mux[] = {
-	MMC_D0_MARK,
-};
-static const unsigned int mmc_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
-	RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
-};
-static const unsigned int mmc_data4_mux[] = {
-	MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
-};
-static const unsigned int mmc_data8_pins[] = {
 	/* D[0:7] */
 	RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
 	RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
 	RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
 	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
 };
-static const unsigned int mmc_data8_mux[] = {
+static const unsigned int mmc_data_mux[] = {
 	MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
 	MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
 };
-static const unsigned int mmc_data8_b_pins[] = {
+static const unsigned int mmc_data_b_pins[] = {
 	/* D[0:7] */
 	RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
 	RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
 	RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
 	RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
 };
-static const unsigned int mmc_data8_b_mux[] = {
+static const unsigned int mmc_data_b_mux[] = {
 	MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
 	MMC_D4_MARK, MMC_D5_MARK, MMC_D6_B_MARK, MMC_D7_B_MARK,
 };
 static const unsigned int qspi_ctrl_mux[] = {
 	SPCLK_MARK, SSL_MARK,
 };
-static const unsigned int qspi_data2_pins[] = {
+static const unsigned int qspi_data_pins[] = {
-	/* MOSI_IO0, MISO_IO1 */
-	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
-};
-static const unsigned int qspi_data2_mux[] = {
-	MOSI_IO0_MARK, MISO_IO1_MARK,
-};
-static const unsigned int qspi_data4_pins[] = {
 	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
 	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
 	RCAR_GP_PIN(1, 8),
 };
-static const unsigned int qspi_data4_mux[] = {
+static const unsigned int qspi_data_mux[] = {
 	MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
 };
 static const unsigned int qspi_ctrl_b_mux[] = {
 	SPCLK_B_MARK, SSL_B_MARK,
 };
-static const unsigned int qspi_data2_b_pins[] = {
+static const unsigned int qspi_data_b_pins[] = {
-	/* MOSI_IO0, MISO_IO1 */
-	RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2),
-};
-static const unsigned int qspi_data2_b_mux[] = {
-	MOSI_IO0_B_MARK, MISO_IO1_B_MARK,
-};
-static const unsigned int qspi_data4_b_pins[] = {
 	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
 	RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
 	RCAR_GP_PIN(6, 4),
 };
-static const unsigned int qspi_data4_b_mux[] = {
+static const unsigned int qspi_data_b_mux[] = {
 	MOSI_IO0_B_MARK, MISO_IO1_B_MARK, IO2_B_MARK, IO3_B_MARK,
 };
 /* - SCIF0 ------------------------------------------------------------------ */
 };
 /* - SDHI0 ------------------------------------------------------------------ */
-static const unsigned int sdhi0_data1_pins[] = {
+static const unsigned int sdhi0_data_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(6, 2),
-};
-static const unsigned int sdhi0_data1_mux[] = {
-	SD0_DATA0_MARK,
-};
-static const unsigned int sdhi0_data4_pins[] = {
 	/* D[0:3] */
 	RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
 	RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
 };
-static const unsigned int sdhi0_data4_mux[] = {
+static const unsigned int sdhi0_data_mux[] = {
 	SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK,
 };
 static const unsigned int sdhi0_ctrl_pins[] = {
 	SD0_WP_MARK,
 };
 /* - SDHI1 ------------------------------------------------------------------ */
-static const unsigned int sdhi1_data1_pins[] = {
+static const unsigned int sdhi1_data_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(6, 10),
-};
-static const unsigned int sdhi1_data1_mux[] = {
-	SD1_DATA0_MARK,
-};
-static const unsigned int sdhi1_data4_pins[] = {
 	/* D[0:3] */
 	RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
 	RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
 };
-static const unsigned int sdhi1_data4_mux[] = {
+static const unsigned int sdhi1_data_mux[] = {
 	SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK,
 };
 static const unsigned int sdhi1_ctrl_pins[] = {
 	SD1_WP_MARK,
 };
 /* - SDHI2 ------------------------------------------------------------------ */
-static const unsigned int sdhi2_data1_pins[] = {
+static const unsigned int sdhi2_data_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(6, 18),
-};
-static const unsigned int sdhi2_data1_mux[] = {
-	SD2_DATA0_MARK,
-};
-static const unsigned int sdhi2_data4_pins[] = {
 	/* D[0:3] */
 	RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
 	RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
 };
-static const unsigned int sdhi2_data4_mux[] = {
+static const unsigned int sdhi2_data_mux[] = {
 	SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK,
 };
 static const unsigned int sdhi2_ctrl_pins[] = {
 	USB1_OVC_MARK,
 };
 /* - VIN0 ------------------------------------------------------------------- */
-static const union vin_data vin0_data_pins = {
+static const unsigned int vin0_data_pins[] = {
-	.data24 = {
+	/* B */
-		/* B */
+	RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6),
-		RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6),
+	RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
-		RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
+	RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
-		RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
+	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
-		RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
+	/* G */
-		/* G */
+	RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
-		RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
+	RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
-		RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
+	RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
-		RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
+	RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
-		RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
+	/* R */
-		/* R */
+	RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22),
-		RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22),
+	RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
-		RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
+	RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
-		RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
+	RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
-		RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
-	},
 };
-static const union vin_data vin0_data_mux = {
+static const unsigned int vin0_data_mux[] = {
-	.data24 = {
+	/* B */
-		/* B */
+	VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
-		VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
+	VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
-		VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
+	VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
-		VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
+	VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
-		VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
+	/* G */
-		/* G */
+	VI0_G0_MARK, VI0_G1_MARK,
-		VI0_G0_MARK, VI0_G1_MARK,
+	VI0_G2_MARK, VI0_G3_MARK,
-		VI0_G2_MARK, VI0_G3_MARK,
+	VI0_G4_MARK, VI0_G5_MARK,
-		VI0_G4_MARK, VI0_G5_MARK,
+	VI0_G6_MARK, VI0_G7_MARK,
-		VI0_G6_MARK, VI0_G7_MARK,
+	/* R */
-		/* R */
+	VI0_R0_MARK, VI0_R1_MARK,
-		VI0_R0_MARK, VI0_R1_MARK,
+	VI0_R2_MARK, VI0_R3_MARK,
-		VI0_R2_MARK, VI0_R3_MARK,
+	VI0_R4_MARK, VI0_R5_MARK,
-		VI0_R4_MARK, VI0_R5_MARK,
+	VI0_R6_MARK, VI0_R7_MARK,
-		VI0_R6_MARK, VI0_R7_MARK,
-	},
 };
 static const unsigned int vin0_data18_pins[] = {
 	/* B */
 static const unsigned int vin1_clk_mux[] = {
 	VI1_CLK_MARK,
 };
-static const union vin_data vin1_data_b_pins = {
+static const unsigned int vin1_data_b_pins[] = {
-	.data24 = {
+	/* B */
-		/* B */
+	RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
-		RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
+	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
-		RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
+	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
-		RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
+	RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
-		RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
+	/* G */
-		/* G */
+	RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
-		RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
+	RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
-		RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
+	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
-		RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
+	RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
-		RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
+	/* R */
-		/* R */
+	RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
-		RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
+	RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
-		RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
+	RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
-		RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
+	RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
-		RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
-	},
 };
-static const union vin_data vin1_data_b_mux = {
+static const unsigned int vin1_data_b_mux[] = {
-	.data24 = {
+	/* B */
-		/* B */
+	VI1_DATA0_B_MARK, VI1_DATA1_B_MARK,
-		VI1_DATA0_B_MARK, VI1_DATA1_B_MARK,
+	VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
-		VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
+	VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
-		VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
+	VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
-		VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
+	/* G */
-		/* G */
+	VI1_G0_B_MARK, VI1_G1_B_MARK,
-		VI1_G0_B_MARK, VI1_G1_B_MARK,
+	VI1_G2_B_MARK, VI1_G3_B_MARK,
-		VI1_G2_B_MARK, VI1_G3_B_MARK,
+	VI1_G4_B_MARK, VI1_G5_B_MARK,
-		VI1_G4_B_MARK, VI1_G5_B_MARK,
+	VI1_G6_B_MARK, VI1_G7_B_MARK,
-		VI1_G6_B_MARK, VI1_G7_B_MARK,
+	/* R */
-		/* R */
+	VI1_R0_B_MARK, VI1_R1_B_MARK,
-		VI1_R0_B_MARK, VI1_R1_B_MARK,
+	VI1_R2_B_MARK, VI1_R3_B_MARK,
-		VI1_R2_B_MARK, VI1_R3_B_MARK,
+	VI1_R4_B_MARK, VI1_R5_B_MARK,
-		VI1_R4_B_MARK, VI1_R5_B_MARK,
+	VI1_R6_B_MARK, VI1_R7_B_MARK,
-		VI1_R6_B_MARK, VI1_R7_B_MARK,
-	},
 };
 static const unsigned int vin1_data18_b_pins[] = {
 	/* B */
 		SH_PFC_PIN_GROUP(hscif1_clk_c),
 		SH_PFC_PIN_GROUP(hscif1_ctrl_c),
 		SH_PFC_PIN_GROUP(hscif1_data_d),
-		SH_PFC_PIN_GROUP(hscif1_data_e),
+		SH_PFC_PIN_GROUP_ALIAS(hscif1_data_e, hscif1_data_c),
 		SH_PFC_PIN_GROUP(hscif1_clk_e),
 		SH_PFC_PIN_GROUP(hscif1_ctrl_e),
 		SH_PFC_PIN_GROUP(hscif2_data),
 		SH_PFC_PIN_GROUP(intc_irq1),
 		SH_PFC_PIN_GROUP(intc_irq2),
 		SH_PFC_PIN_GROUP(intc_irq3),
-		SH_PFC_PIN_GROUP(mmc_data1),
+		BUS_DATA_PIN_GROUP(mmc_data, 1),
-		SH_PFC_PIN_GROUP(mmc_data4),
+		BUS_DATA_PIN_GROUP(mmc_data, 4),
-		SH_PFC_PIN_GROUP(mmc_data8),
+		BUS_DATA_PIN_GROUP(mmc_data, 8),
-		SH_PFC_PIN_GROUP(mmc_data8_b),
+		BUS_DATA_PIN_GROUP(mmc_data, 8, _b),
 		SH_PFC_PIN_GROUP(mmc_ctrl),
 		SH_PFC_PIN_GROUP(msiof0_clk),
 		SH_PFC_PIN_GROUP(msiof0_sync),
 		SH_PFC_PIN_GROUP(pwm5_b),
 		SH_PFC_PIN_GROUP(pwm6),
 		SH_PFC_PIN_GROUP(qspi_ctrl),
-		SH_PFC_PIN_GROUP(qspi_data2),
+		BUS_DATA_PIN_GROUP(qspi_data, 2),
-		SH_PFC_PIN_GROUP(qspi_data4),
+		BUS_DATA_PIN_GROUP(qspi_data, 4),
 		SH_PFC_PIN_GROUP(qspi_ctrl_b),
-		SH_PFC_PIN_GROUP(qspi_data2_b),
+		BUS_DATA_PIN_GROUP(qspi_data, 2, _b),
-		SH_PFC_PIN_GROUP(qspi_data4_b),
+		BUS_DATA_PIN_GROUP(qspi_data, 4, _b),
 		SH_PFC_PIN_GROUP(scif0_data),
 		SH_PFC_PIN_GROUP(scif0_data_b),
 		SH_PFC_PIN_GROUP(scif0_data_c),
 		SH_PFC_PIN_GROUP(scifb2_data_d),
 		SH_PFC_PIN_GROUP(scif_clk),
 		SH_PFC_PIN_GROUP(scif_clk_b),
-		SH_PFC_PIN_GROUP(sdhi0_data1),
+		BUS_DATA_PIN_GROUP(sdhi0_data, 1),
-		SH_PFC_PIN_GROUP(sdhi0_data4),
+		BUS_DATA_PIN_GROUP(sdhi0_data, 4),
 		SH_PFC_PIN_GROUP(sdhi0_ctrl),
 		SH_PFC_PIN_GROUP(sdhi0_cd),
 		SH_PFC_PIN_GROUP(sdhi0_wp),
-		SH_PFC_PIN_GROUP(sdhi1_data1),
+		BUS_DATA_PIN_GROUP(sdhi1_data, 1),
-		SH_PFC_PIN_GROUP(sdhi1_data4),
+		BUS_DATA_PIN_GROUP(sdhi1_data, 4),
 		SH_PFC_PIN_GROUP(sdhi1_ctrl),
 		SH_PFC_PIN_GROUP(sdhi1_cd),
 		SH_PFC_PIN_GROUP(sdhi1_wp),
-		SH_PFC_PIN_GROUP(sdhi2_data1),
+		BUS_DATA_PIN_GROUP(sdhi2_data, 1),
-		SH_PFC_PIN_GROUP(sdhi2_data4),
+		BUS_DATA_PIN_GROUP(sdhi2_data, 4),
 		SH_PFC_PIN_GROUP(sdhi2_ctrl),
 		SH_PFC_PIN_GROUP(sdhi2_cd),
 		SH_PFC_PIN_GROUP(sdhi2_wp),
 		SH_PFC_PIN_GROUP(tpu_to3),
 		SH_PFC_PIN_GROUP(usb0),
 		SH_PFC_PIN_GROUP(usb1),
-		VIN_DATA_PIN_GROUP(vin0_data, 24),
+		BUS_DATA_PIN_GROUP(vin0_data, 24),
-		VIN_DATA_PIN_GROUP(vin0_data, 20),
+		BUS_DATA_PIN_GROUP(vin0_data, 20),
 		SH_PFC_PIN_GROUP(vin0_data18),
-		VIN_DATA_PIN_GROUP(vin0_data, 16),
+		BUS_DATA_PIN_GROUP(vin0_data, 16),
-		VIN_DATA_PIN_GROUP(vin0_data, 12),
+		BUS_DATA_PIN_GROUP(vin0_data, 12),
-		VIN_DATA_PIN_GROUP(vin0_data, 10),
+		BUS_DATA_PIN_GROUP(vin0_data, 10),
-		VIN_DATA_PIN_GROUP(vin0_data, 8),
+		BUS_DATA_PIN_GROUP(vin0_data, 8),
 		SH_PFC_PIN_GROUP(vin0_sync),
 		SH_PFC_PIN_GROUP(vin0_field),
 		SH_PFC_PIN_GROUP(vin0_clkenb),
 		SH_PFC_PIN_GROUP(vin1_field),
 		SH_PFC_PIN_GROUP(vin1_clkenb),
 		SH_PFC_PIN_GROUP(vin1_clk),
-		VIN_DATA_PIN_GROUP(vin1_data, 24, _b),
+		BUS_DATA_PIN_GROUP(vin1_data, 24, _b),
-		VIN_DATA_PIN_GROUP(vin1_data, 20, _b),
+		BUS_DATA_PIN_GROUP(vin1_data, 20, _b),
 		SH_PFC_PIN_GROUP(vin1_data18_b),
-		VIN_DATA_PIN_GROUP(vin1_data, 16, _b),
+		BUS_DATA_PIN_GROUP(vin1_data, 16, _b),
-		VIN_DATA_PIN_GROUP(vin1_data, 12, _b),
+		BUS_DATA_PIN_GROUP(vin1_data, 12, _b),
-		VIN_DATA_PIN_GROUP(vin1_data, 10, _b),
+		BUS_DATA_PIN_GROUP(vin1_data, 10, _b),
-		VIN_DATA_PIN_GROUP(vin1_data, 8, _b),
+		BUS_DATA_PIN_GROUP(vin1_data, 8, _b),
 		SH_PFC_PIN_GROUP(vin1_sync_b),
 		SH_PFC_PIN_GROUP(vin1_field_b),
 		SH_PFC_PIN_GROUP(vin1_clkenb_b),
 		FN_IRQ5, FN_HTX1_C, FN_I2C1_SCL_E, FN_MSIOF2_SCK_E,
 		/* IP6_18_16 [3] */
 		FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E,
-		FN_INTC_IRQ4_N,	0, 0, 0,
+		0, 0, 0, 0,
 		/* IP6_15_14 [2] */
-		FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
+		FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, 0,
 		/* IP6_13_12 [2] */
-		FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, 0,
+		FN_IRQ2, FN_SCIFB1_TXD_D, 0, 0,
 		/* IP6_11_10 [2] */
-		FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N, 0,
+		FN_IRQ1, FN_SCIFB1_SCK_C, 0, 0,
 		/* IP6_9_8 [2] */
-		FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N, 0,
+		FN_IRQ0, FN_SCIFB1_RXD_D, 0, 0,
 		/* IP6_7_6 [2] */
 		FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
 		/* IP6_5_3 [3] */
 	{ },
 };
-static int r8a7791_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
+static int r8a7791_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
 {
 	if (pin < RCAR_GP_PIN(6, 0) || pin > RCAR_GP_PIN(6, 23))
 		return -EINVAL;
 	{ /* sentinel */ },
 };
-static const struct sh_pfc_soc_operations r8a7791_pinmux_ops = {
+static const struct sh_pfc_soc_operations r8a7791_pfc_ops = {
 	.pin_to_pocctrl = r8a7791_pin_to_pocctrl,
 	.get_bias = rcar_pinmux_get_bias,
 	.set_bias = rcar_pinmux_set_bias,
 #ifdef CONFIG_PINCTRL_PFC_R8A7743
 const struct sh_pfc_soc_info r8a7743_pinmux_info = {
 	.name = "r8a77430_pfc",
-	.ops = &r8a7791_pinmux_ops,
+	.ops = &r8a7791_pfc_ops,
 	.unlock_reg = 0xe6060000, /* PMMR */
 	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
 #ifdef CONFIG_PINCTRL_PFC_R8A7744
 const struct sh_pfc_soc_info r8a7744_pinmux_info = {
 	.name = "r8a77440_pfc",
-	.ops = &r8a7791_pinmux_ops,
+	.ops = &r8a7791_pfc_ops,
 	.unlock_reg = 0xe6060000, /* PMMR */
 	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
 #ifdef CONFIG_PINCTRL_PFC_R8A7791
 const struct sh_pfc_soc_info r8a7791_pinmux_info = {
 	.name = "r8a77910_pfc",
-	.ops = &r8a7791_pinmux_ops,
+	.ops = &r8a7791_pfc_ops,
 	.unlock_reg = 0xe6060000, /* PMMR */
 	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
 #ifdef CONFIG_PINCTRL_PFC_R8A7793
 const struct sh_pfc_soc_info r8a7793_pinmux_info = {
 	.name = "r8a77930_pfc",
-	.ops = &r8a7791_pinmux_ops,
+	.ops = &r8a7791_pfc_ops,
 	.unlock_reg = 0xe6060000, /* PMMR */
 	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },

drivers/pinctrl/renesas/pfc-r8a7792.c+202−244

@@ -1116,19 +1116,12 @@ static const unsigned int qspi_ctrl_pins[] = { · 1115 unmodified lines
1116	static const unsigned int qspi_ctrl_mux[] = {	1116	static const unsigned int qspi_ctrl_mux[] = {
1117	SPCLK_MARK, SSL_MARK,	1117	SPCLK_MARK, SSL_MARK,
1118	};	1118	};
1119	static const unsigned int qspi_data2_pins[] = {	1119	static const unsigned int qspi_data_pins[] = {
1120	/* MOSI_IO0, MISO_IO1 */
1121	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1122	};
1123	static const unsigned int qspi_data2_mux[] = {
1124	MOSI_IO0_MARK, MISO_IO1_MARK,
1125	};
1126	static const unsigned int qspi_data4_pins[] = {
1127	/* MOSI_IO0, MISO_IO1, IO2, IO3 */	1120	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
1128	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 23),	1121	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 23),
1129	RCAR_GP_PIN(3, 24),	1122	RCAR_GP_PIN(3, 24),
1130	};	1123	};
1131	static const unsigned int qspi_data4_mux[] = {	1124	static const unsigned int qspi_data_mux[] = {
1132	MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,	1125	MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
1133	};	1126	};
1134	/* - SCIF0 ------------------------------------------------------------------ */	1127	/* - SCIF0 ------------------------------------------------------------------ */
@@ -1206,19 +1199,12 @@ static const unsigned int scif3_clk_mux[] = { · 71 unmodified lines
1206	SCK3_MARK,	1199	SCK3_MARK,
1207	};	1200	};
1208	/* - SDHI0 ------------------------------------------------------------------ */	1201	/* - SDHI0 ------------------------------------------------------------------ */
1209	static const unsigned int sdhi0_data1_pins[] = {	1202	static const unsigned int sdhi0_data_pins[] = {
1210	/* DAT0 */
1211	RCAR_GP_PIN(11, 7),
1212	};
1213	static const unsigned int sdhi0_data1_mux[] = {
1214	SD0_DAT0_MARK,
1215	};
1216	static const unsigned int sdhi0_data4_pins[] = {
1217	/* DAT[0-3] */	1203	/* DAT[0-3] */
1218	RCAR_GP_PIN(11, 7), RCAR_GP_PIN(11, 8),	1204	RCAR_GP_PIN(11, 7), RCAR_GP_PIN(11, 8),
1219	RCAR_GP_PIN(11, 9), RCAR_GP_PIN(11, 10),	1205	RCAR_GP_PIN(11, 9), RCAR_GP_PIN(11, 10),
1220	};	1206	};
1221	static const unsigned int sdhi0_data4_mux[] = {	1207	static const unsigned int sdhi0_data_mux[] = {
1222	SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,	1208	SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
1223	};	1209	};
1224	static const unsigned int sdhi0_ctrl_pins[] = {	1210	static const unsigned int sdhi0_ctrl_pins[] = {
@@ -1243,43 +1229,39 @@ static const unsigned int sdhi0_wp_mux[] = { · 18 unmodified lines
1243	SD0_WP_MARK,	1229	SD0_WP_MARK,
1244	};	1230	};
1245	/* - VIN0 ------------------------------------------------------------------- */	1231	/* - VIN0 ------------------------------------------------------------------- */
1246	static const union vin_data vin0_data_pins = {	1232	static const unsigned int vin0_data_pins[] = {
1247	.data24 = {	1233	/* B */
1248	/* B */	1234	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1249	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),	1235	RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
1250	RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),	1236	RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1251	RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),	1237	RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1252	RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),	1238	/* G */
1253	/* G */	1239	RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13),
1254	RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13),	1240	RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
1255	RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),	1241	RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 2),
1256	RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 2),	1242	RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 4),
1257	RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 4),	1243	/* R */
1258	/* R */	1244	RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
1259	RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),	1245	RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
1260	RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),	1246	RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
1261	RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),	1247	RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
1262	RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
1263	},
1264	};	1248	};
1265	static const union vin_data vin0_data_mux = {	1249	static const unsigned int vin0_data_mux[] = {
1266	.data24 = {	1250	/* B */
1267	/* B */	1251	VI0_D0_B0_C0_MARK, VI0_D1_B1_C1_MARK,
1268	VI0_D0_B0_C0_MARK, VI0_D1_B1_C1_MARK,	1252	VI0_D2_B2_C2_MARK, VI0_D3_B3_C3_MARK,
1269	VI0_D2_B2_C2_MARK, VI0_D3_B3_C3_MARK,	1253	VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK,
1270	VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK,	1254	VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK,
1271	VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK,	1255	/* G */
1272	/* G */	1256	VI0_D8_G0_Y0_MARK, VI0_D9_G1_Y1_MARK,
1273	VI0_D8_G0_Y0_MARK, VI0_D9_G1_Y1_MARK,	1257	VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,
1274	VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,	1258	VI0_D12_G4_Y4_MARK, VI0_D13_G5_Y5_MARK,
1275	VI0_D12_G4_Y4_MARK, VI0_D13_G5_Y5_MARK,	1259	VI0_D14_G6_Y6_MARK, VI0_D15_G7_Y7_MARK,
1276	VI0_D14_G6_Y6_MARK, VI0_D15_G7_Y7_MARK,	1260	/* R */
1277	/* R */	1261	VI0_D16_R0_MARK, VI0_D17_R1_MARK,
1278	VI0_D16_R0_MARK, VI0_D17_R1_MARK,	1262	VI0_D18_R2_MARK, VI0_D19_R3_MARK,
1279	VI0_D18_R2_MARK, VI0_D19_R3_MARK,	1263	VI0_D20_R4_MARK, VI0_D21_R5_MARK,
1280	VI0_D20_R4_MARK, VI0_D21_R5_MARK,	1264	VI0_D22_R6_MARK, VI0_D23_R7_MARK,
1281	VI0_D22_R6_MARK, VI0_D23_R7_MARK,
1282	},
1283	};	1265	};
1284	static const unsigned int vin0_data18_pins[] = {	1266	static const unsigned int vin0_data18_pins[] = {
1285	/* B */	1267	/* B */
@@ -1335,43 +1317,39 @@ static const unsigned int vin0_clk_mux[] = { · 49 unmodified lines
1335	VI0_CLK_MARK,	1317	VI0_CLK_MARK,
1336	};	1318	};
1337	/* - VIN1 ------------------------------------------------------------------- */	1319	/* - VIN1 ------------------------------------------------------------------- */
1338	static const union vin_data vin1_data_pins = {	1320	static const unsigned int vin1_data_pins[] = {
1339	.data24 = {	1321	/* B */
1340	/* B */	1322	RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1341	RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),	1323	RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1342	RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),	1324	RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1343	RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),	1325	RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1344	RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),	1326	/* G */
1345	/* G */	1327	RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
1346	RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),	1328	RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1347	RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),	1329	RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
1348	RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),	1330	RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
1349	RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),	1331	/* R */
1350	/* R */	1332	RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6),
1351	RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6),	1333	RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
1352	RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),	1334	RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
1353	RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),	1335	RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
1354	RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
1355	},
1356	};	1336	};
1357	static const union vin_data vin1_data_mux = {	1337	static const unsigned int vin1_data_mux[] = {
1358	.data24 = {	1338	/* B */
1359	/* B */	1339	VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK,
1360	VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK,	1340	VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
1361	VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,	1341	VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
1362	VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,	1342	VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
1363	VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,	1343	/* G */
1364	/* G */	1344	VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK,
1365	VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK,	1345	VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
1366	VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,	1346	VI1_D12_G4_Y4_MARK, VI1_D13_G5_Y5_MARK,
1367	VI1_D12_G4_Y4_MARK, VI1_D13_G5_Y5_MARK,	1347	VI1_D14_G6_Y6_MARK, VI1_D15_G7_Y7_MARK,
1368	VI1_D14_G6_Y6_MARK, VI1_D15_G7_Y7_MARK,	1348	/* R */
1369	/* R */	1349	VI1_D16_R0_MARK, VI1_D17_R1_MARK,
1370	VI1_D16_R0_MARK, VI1_D17_R1_MARK,	1350	VI1_D18_R2_MARK, VI1_D19_R3_MARK,
1371	VI1_D18_R2_MARK, VI1_D19_R3_MARK,	1351	VI1_D20_R4_MARK, VI1_D21_R5_MARK,
1372	VI1_D20_R4_MARK, VI1_D21_R5_MARK,	1352	VI1_D22_R6_MARK, VI1_D23_R7_MARK,
1373	VI1_D22_R6_MARK, VI1_D23_R7_MARK,
1374	},
1375	};	1353	};
1376	static const unsigned int vin1_data18_pins[] = {	1354	static const unsigned int vin1_data18_pins[] = {
1377	/* B */	1355	/* B */
@@ -1401,43 +1379,39 @@ static const unsigned int vin1_data18_mux[] = { · 23 unmodified lines
1401	VI1_D20_R4_MARK, VI1_D21_R5_MARK,	1379	VI1_D20_R4_MARK, VI1_D21_R5_MARK,
1402	VI1_D22_R6_MARK, VI1_D23_R7_MARK,	1380	VI1_D22_R6_MARK, VI1_D23_R7_MARK,
1403	};	1381	};
1404	static const union vin_data vin1_data_b_pins = {	1382	static const unsigned int vin1_data_b_pins[] = {
1405	.data24 = {	1383	/* B */
1406	/* B */	1384	RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1407	RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),	1385	RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1408	RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),	1386	RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1409	RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),	1387	RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1410	RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),	1388	/* G */
1411	/* G */	1389	RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
1412	RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),	1390	RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1413	RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),	1391	RCAR_GP_PIN(9, 1), RCAR_GP_PIN(9, 2),
1414	RCAR_GP_PIN(9, 1), RCAR_GP_PIN(9, 2),	1392	RCAR_GP_PIN(9, 3), RCAR_GP_PIN(9, 4),
1415	RCAR_GP_PIN(9, 3), RCAR_GP_PIN(9, 4),	1393	/* R */
1416	/* R */	1394	RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6),
1417	RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6),	1395	RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
1418	RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),	1396	RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
1419	RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),	1397	RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
1420	RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
1421	},
1422	};	1398	};
1423	static const union vin_data vin1_data_b_mux = {	1399	static const unsigned int vin1_data_b_mux[] = {
1424	.data24 = {	1400	/* B */
1425	/* B */	1401	VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK,
1426	VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK,	1402	VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
1427	VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,	1403	VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
1428	VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,	1404	VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
1429	VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,	1405	/* G */
1430	/* G */	1406	VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK,
1431	VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK,	1407	VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
1432	VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,	1408	VI1_D12_G4_Y4_B_MARK, VI1_D13_G5_Y5_B_MARK,
1433	VI1_D12_G4_Y4_B_MARK, VI1_D13_G5_Y5_B_MARK,	1409	VI1_D14_G6_Y6_B_MARK, VI1_D15_G7_Y7_B_MARK,
1434	VI1_D14_G6_Y6_B_MARK, VI1_D15_G7_Y7_B_MARK,	1410	/* R */
1435	/* R */	1411	VI1_D16_R0_MARK, VI1_D17_R1_MARK,
1436	VI1_D16_R0_MARK, VI1_D17_R1_MARK,	1412	VI1_D18_R2_MARK, VI1_D19_R3_MARK,
1437	VI1_D18_R2_MARK, VI1_D19_R3_MARK,	1413	VI1_D20_R4_MARK, VI1_D21_R5_MARK,
1438	VI1_D20_R4_MARK, VI1_D21_R5_MARK,	1414	VI1_D22_R6_MARK, VI1_D23_R7_MARK,
1439	VI1_D22_R6_MARK, VI1_D23_R7_MARK,
1440	},
1441	};	1415	};
1442	static const unsigned int vin1_data18_b_pins[] = {	1416	static const unsigned int vin1_data18_b_pins[] = {
1443	/* B */	1417	/* B */
@@ -1493,29 +1467,25 @@ static const unsigned int vin1_clk_mux[] = { · 49 unmodified lines
1493	VI1_CLK_MARK,	1467	VI1_CLK_MARK,
1494	};	1468	};
1495	/* - VIN2 ------------------------------------------------------------------- */	1469	/* - VIN2 ------------------------------------------------------------------- */
1496	static const union vin_data16 vin2_data_pins = {	1470	static const unsigned int vin2_data_pins[] = {
1497	.data16 = {	1471	RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
1498	RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),	1472	RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
1499	RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),	1473	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1500	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),	1474	RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
1501	RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),	1475	RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
1502	RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),	1476	RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
1503	RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),	1477	RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
1504	RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),	1478	RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
1505	RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
1506	},
1507	};	1479	};
1508	static const union vin_data16 vin2_data_mux = {	1480	static const unsigned int vin2_data_mux[] = {
1509	.data16 = {	1481	VI2_D0_C0_MARK, VI2_D1_C1_MARK,
1510	VI2_D0_C0_MARK, VI2_D1_C1_MARK,	1482	VI2_D2_C2_MARK, VI2_D3_C3_MARK,
1511	VI2_D2_C2_MARK, VI2_D3_C3_MARK,	1483	VI2_D4_C4_MARK, VI2_D5_C5_MARK,
1512	VI2_D4_C4_MARK, VI2_D5_C5_MARK,	1484	VI2_D6_C6_MARK, VI2_D7_C7_MARK,
1513	VI2_D6_C6_MARK, VI2_D7_C7_MARK,	1485	VI2_D8_Y0_MARK, VI2_D9_Y1_MARK,
1514	VI2_D8_Y0_MARK, VI2_D9_Y1_MARK,	1486	VI2_D10_Y2_MARK, VI2_D11_Y3_MARK,
1515	VI2_D10_Y2_MARK, VI2_D11_Y3_MARK,	1487	VI2_D12_Y4_MARK, VI2_D13_Y5_MARK,
1516	VI2_D12_Y4_MARK, VI2_D13_Y5_MARK,	1488	VI2_D14_Y6_MARK, VI2_D15_Y7_MARK,
1517	VI2_D14_Y6_MARK, VI2_D15_Y7_MARK,
1518	},
1519	};	1489	};
1520	static const unsigned int vin2_sync_pins[] = {	1490	static const unsigned int vin2_sync_pins[] = {
1521	/* HSYNC#, VSYNC# */	1491	/* HSYNC#, VSYNC# */
@@ -1543,29 +1513,25 @@ static const unsigned int vin2_clk_mux[] = { · 21 unmodified lines
1543	VI2_CLK_MARK,	1513	VI2_CLK_MARK,
1544	};	1514	};
1545	/* - VIN3 ------------------------------------------------------------------- */	1515	/* - VIN3 ------------------------------------------------------------------- */
1546	static const union vin_data16 vin3_data_pins = {	1516	static const unsigned int vin3_data_pins[] = {
1547	.data16 = {	1517	RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 5),
1548	RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 5),	1518	RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 7),
1549	RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 7),	1519	RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
1550	RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),	1520	RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 11),
1551	RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 11),	1521	RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 13),
1552	RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 13),	1522	RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
1553	RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),	1523	RCAR_GP_PIN(8, 13), RCAR_GP_PIN(8, 14),
1554	RCAR_GP_PIN(8, 13), RCAR_GP_PIN(8, 14),	1524	RCAR_GP_PIN(8, 15), RCAR_GP_PIN(8, 16),
1555	RCAR_GP_PIN(8, 15), RCAR_GP_PIN(8, 16),	1525	};
1556	},	1526	static const unsigned int vin3_data_mux[] = {
1557	};	1527	VI3_D0_C0_MARK, VI3_D1_C1_MARK,
1558	static const union vin_data16 vin3_data_mux = {	1528	VI3_D2_C2_MARK, VI3_D3_C3_MARK,
1559	.data16 = {	1529	VI3_D4_C4_MARK, VI3_D5_C5_MARK,
1560	VI3_D0_C0_MARK, VI3_D1_C1_MARK,	1530	VI3_D6_C6_MARK, VI3_D7_C7_MARK,
1561	VI3_D2_C2_MARK, VI3_D3_C3_MARK,	1531	VI3_D8_Y0_MARK, VI3_D9_Y1_MARK,
1562	VI3_D4_C4_MARK, VI3_D5_C5_MARK,	1532	VI3_D10_Y2_MARK, VI3_D11_Y3_MARK,
1563	VI3_D6_C6_MARK, VI3_D7_C7_MARK,	1533	VI3_D12_Y4_MARK, VI3_D13_Y5_MARK,
1564	VI3_D8_Y0_MARK, VI3_D9_Y1_MARK,	1534	VI3_D14_Y6_MARK, VI3_D15_Y7_MARK,
1565	VI3_D10_Y2_MARK, VI3_D11_Y3_MARK,
1566	VI3_D12_Y4_MARK, VI3_D13_Y5_MARK,
1567	VI3_D14_Y6_MARK, VI3_D15_Y7_MARK,
1568	},
1569	};	1535	};
1570	static const unsigned int vin3_sync_pins[] = {	1536	static const unsigned int vin3_sync_pins[] = {
1571	/* HSYNC#, VSYNC# */	1537	/* HSYNC#, VSYNC# */
@@ -1593,25 +1559,21 @@ static const unsigned int vin3_clk_mux[] = { · 21 unmodified lines
1593	VI3_CLK_MARK,	1559	VI3_CLK_MARK,
1594	};	1560	};
1595	/* - VIN4 ------------------------------------------------------------------- */	1561	/* - VIN4 ------------------------------------------------------------------- */
1596	static const union vin_data12 vin4_data_pins = {	1562	static const unsigned int vin4_data_pins[] = {
1597	.data12 = {	1563	RCAR_GP_PIN(8, 4), RCAR_GP_PIN(8, 5),
1598	RCAR_GP_PIN(8, 4), RCAR_GP_PIN(8, 5),	1564	RCAR_GP_PIN(8, 6), RCAR_GP_PIN(8, 7),
1599	RCAR_GP_PIN(8, 6), RCAR_GP_PIN(8, 7),	1565	RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9),
1600	RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9),	1566	RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 11),
1601	RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 11),	1567	RCAR_GP_PIN(8, 12), RCAR_GP_PIN(8, 13),
1602	RCAR_GP_PIN(8, 12), RCAR_GP_PIN(8, 13),	1568	RCAR_GP_PIN(8, 14), RCAR_GP_PIN(8, 15),
1603	RCAR_GP_PIN(8, 14), RCAR_GP_PIN(8, 15),	1569	};
1604	},	1570	static const unsigned int vin4_data_mux[] = {
1605	};	1571	VI4_D0_C0_MARK, VI4_D1_C1_MARK,
1606	static const union vin_data12 vin4_data_mux = {	1572	VI4_D2_C2_MARK, VI4_D3_C3_MARK,
1607	.data12 = {	1573	VI4_D4_C4_MARK, VI4_D5_C5_MARK,
1608	VI4_D0_C0_MARK, VI4_D1_C1_MARK,	1574	VI4_D6_C6_MARK, VI4_D7_C7_MARK,
1609	VI4_D2_C2_MARK, VI4_D3_C3_MARK,	1575	VI4_D8_Y0_MARK, VI4_D9_Y1_MARK,
1610	VI4_D4_C4_MARK, VI4_D5_C5_MARK,	1576	VI4_D10_Y2_MARK, VI4_D11_Y3_MARK,
1611	VI4_D6_C6_MARK, VI4_D7_C7_MARK,
1612	VI4_D8_Y0_MARK, VI4_D9_Y1_MARK,
1613	VI4_D10_Y2_MARK, VI4_D11_Y3_MARK,
1614	},
1615	};	1577	};
1616	static const unsigned int vin4_sync_pins[] = {	1578	static const unsigned int vin4_sync_pins[] = {
1617	/* HSYNC#, VSYNC# */	1579	/* HSYNC#, VSYNC# */
@@ -1639,25 +1601,21 @@ static const unsigned int vin4_clk_mux[] = { · 21 unmodified lines
1639	VI4_CLK_MARK,	1601	VI4_CLK_MARK,
1640	};	1602	};
1641	/* - VIN5 ------------------------------------------------------------------- */	1603	/* - VIN5 ------------------------------------------------------------------- */
1642	static const union vin_data12 vin5_data_pins = {	1604	static const unsigned int vin5_data_pins[] = {
1643	.data12 = {	1605	RCAR_GP_PIN(9, 4), RCAR_GP_PIN(9, 5),
1644	RCAR_GP_PIN(9, 4), RCAR_GP_PIN(9, 5),	1606	RCAR_GP_PIN(9, 6), RCAR_GP_PIN(9, 7),
1645	RCAR_GP_PIN(9, 6), RCAR_GP_PIN(9, 7),	1607	RCAR_GP_PIN(9, 8), RCAR_GP_PIN(9, 9),
1646	RCAR_GP_PIN(9, 8), RCAR_GP_PIN(9, 9),	1608	RCAR_GP_PIN(9, 10), RCAR_GP_PIN(9, 11),
1647	RCAR_GP_PIN(9, 10), RCAR_GP_PIN(9, 11),	1609	RCAR_GP_PIN(9, 12), RCAR_GP_PIN(9, 13),
1648	RCAR_GP_PIN(9, 12), RCAR_GP_PIN(9, 13),	1610	RCAR_GP_PIN(9, 14), RCAR_GP_PIN(9, 15),
1649	RCAR_GP_PIN(9, 14), RCAR_GP_PIN(9, 15),	1611	};
1650	},	1612	static const unsigned int vin5_data_mux[] = {
1651	};	1613	VI5_D0_C0_MARK, VI5_D1_C1_MARK,
1652	static const union vin_data12 vin5_data_mux = {	1614	VI5_D2_C2_MARK, VI5_D3_C3_MARK,
1653	.data12 = {	1615	VI5_D4_C4_MARK, VI5_D5_C5_MARK,
1654	VI5_D0_C0_MARK, VI5_D1_C1_MARK,	1616	VI5_D6_C6_MARK, VI5_D7_C7_MARK,
1655	VI5_D2_C2_MARK, VI5_D3_C3_MARK,	1617	VI5_D8_Y0_MARK, VI5_D9_Y1_MARK,
1656	VI5_D4_C4_MARK, VI5_D5_C5_MARK,	1618	VI5_D10_Y2_MARK, VI5_D11_Y3_MARK,
1657	VI5_D6_C6_MARK, VI5_D7_C7_MARK,
1658	VI5_D8_Y0_MARK, VI5_D9_Y1_MARK,
1659	VI5_D10_Y2_MARK, VI5_D11_Y3_MARK,
1660	},
1661	};	1619	};
1662	static const unsigned int vin5_sync_pins[] = {	1620	static const unsigned int vin5_sync_pins[] = {
1663	/* HSYNC#, VSYNC# */	1621	/* HSYNC#, VSYNC# */
@@ -1728,8 +1686,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { · 64 unmodified lines
1728	SH_PFC_PIN_GROUP(msiof1_rx),	1686	SH_PFC_PIN_GROUP(msiof1_rx),
1729	SH_PFC_PIN_GROUP(msiof1_tx),	1687	SH_PFC_PIN_GROUP(msiof1_tx),
1730	SH_PFC_PIN_GROUP(qspi_ctrl),	1688	SH_PFC_PIN_GROUP(qspi_ctrl),
1731	SH_PFC_PIN_GROUP(qspi_data2),	1689	BUS_DATA_PIN_GROUP(qspi_data, 2),
1732	SH_PFC_PIN_GROUP(qspi_data4),	1690	BUS_DATA_PIN_GROUP(qspi_data, 4),
1733	SH_PFC_PIN_GROUP(scif0_data),	1691	SH_PFC_PIN_GROUP(scif0_data),
1734	SH_PFC_PIN_GROUP(scif0_clk),	1692	SH_PFC_PIN_GROUP(scif0_clk),
1735	SH_PFC_PIN_GROUP(scif0_ctrl),	1693	SH_PFC_PIN_GROUP(scif0_ctrl),
@@ -1740,63 +1698,63 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { · 4 unmodified lines
1740	SH_PFC_PIN_GROUP(scif2_clk),	1698	SH_PFC_PIN_GROUP(scif2_clk),
1741	SH_PFC_PIN_GROUP(scif3_data),	1699	SH_PFC_PIN_GROUP(scif3_data),
1742	SH_PFC_PIN_GROUP(scif3_clk),	1700	SH_PFC_PIN_GROUP(scif3_clk),
1743	SH_PFC_PIN_GROUP(sdhi0_data1),	1701	BUS_DATA_PIN_GROUP(sdhi0_data, 1),
1744	SH_PFC_PIN_GROUP(sdhi0_data4),	1702	BUS_DATA_PIN_GROUP(sdhi0_data, 4),
1745	SH_PFC_PIN_GROUP(sdhi0_ctrl),	1703	SH_PFC_PIN_GROUP(sdhi0_ctrl),
1746	SH_PFC_PIN_GROUP(sdhi0_cd),	1704	SH_PFC_PIN_GROUP(sdhi0_cd),
1747	SH_PFC_PIN_GROUP(sdhi0_wp),	1705	SH_PFC_PIN_GROUP(sdhi0_wp),
1748	VIN_DATA_PIN_GROUP(vin0_data, 24),	1706	BUS_DATA_PIN_GROUP(vin0_data, 24),
1749	VIN_DATA_PIN_GROUP(vin0_data, 20),	1707	BUS_DATA_PIN_GROUP(vin0_data, 20),
1750	SH_PFC_PIN_GROUP(vin0_data18),	1708	SH_PFC_PIN_GROUP(vin0_data18),
1751	VIN_DATA_PIN_GROUP(vin0_data, 16),	1709	BUS_DATA_PIN_GROUP(vin0_data, 16),
1752	VIN_DATA_PIN_GROUP(vin0_data, 12),	1710	BUS_DATA_PIN_GROUP(vin0_data, 12),
1753	VIN_DATA_PIN_GROUP(vin0_data, 10),	1711	BUS_DATA_PIN_GROUP(vin0_data, 10),
1754	VIN_DATA_PIN_GROUP(vin0_data, 8),	1712	BUS_DATA_PIN_GROUP(vin0_data, 8),
1755	SH_PFC_PIN_GROUP(vin0_sync),	1713	SH_PFC_PIN_GROUP(vin0_sync),
1756	SH_PFC_PIN_GROUP(vin0_field),	1714	SH_PFC_PIN_GROUP(vin0_field),
1757	SH_PFC_PIN_GROUP(vin0_clkenb),	1715	SH_PFC_PIN_GROUP(vin0_clkenb),
1758	SH_PFC_PIN_GROUP(vin0_clk),	1716	SH_PFC_PIN_GROUP(vin0_clk),
1759	VIN_DATA_PIN_GROUP(vin1_data, 24),	1717	BUS_DATA_PIN_GROUP(vin1_data, 24),
1760	VIN_DATA_PIN_GROUP(vin1_data, 20),	1718	BUS_DATA_PIN_GROUP(vin1_data, 20),
1761	SH_PFC_PIN_GROUP(vin1_data18),	1719	SH_PFC_PIN_GROUP(vin1_data18),
1762	VIN_DATA_PIN_GROUP(vin1_data, 16),	1720	BUS_DATA_PIN_GROUP(vin1_data, 16),
1763	VIN_DATA_PIN_GROUP(vin1_data, 12),	1721	BUS_DATA_PIN_GROUP(vin1_data, 12),
1764	VIN_DATA_PIN_GROUP(vin1_data, 10),	1722	BUS_DATA_PIN_GROUP(vin1_data, 10),
1765	VIN_DATA_PIN_GROUP(vin1_data, 8),	1723	BUS_DATA_PIN_GROUP(vin1_data, 8),
1766	VIN_DATA_PIN_GROUP(vin1_data, 24, _b),	1724	BUS_DATA_PIN_GROUP(vin1_data, 24, _b),
1767	VIN_DATA_PIN_GROUP(vin1_data, 20, _b),	1725	BUS_DATA_PIN_GROUP(vin1_data, 20, _b),
1768	SH_PFC_PIN_GROUP(vin1_data18_b),	1726	SH_PFC_PIN_GROUP(vin1_data18_b),
1769	VIN_DATA_PIN_GROUP(vin1_data, 16, _b),	1727	BUS_DATA_PIN_GROUP(vin1_data, 16, _b),
1770	SH_PFC_PIN_GROUP(vin1_sync),	1728	SH_PFC_PIN_GROUP(vin1_sync),
1771	SH_PFC_PIN_GROUP(vin1_field),	1729	SH_PFC_PIN_GROUP(vin1_field),
1772	SH_PFC_PIN_GROUP(vin1_clkenb),	1730	SH_PFC_PIN_GROUP(vin1_clkenb),
1773	SH_PFC_PIN_GROUP(vin1_clk),	1731	SH_PFC_PIN_GROUP(vin1_clk),
1774	VIN_DATA_PIN_GROUP(vin2_data, 16),	1732	BUS_DATA_PIN_GROUP(vin2_data, 16),
1775	VIN_DATA_PIN_GROUP(vin2_data, 12),	1733	BUS_DATA_PIN_GROUP(vin2_data, 12),
1776	VIN_DATA_PIN_GROUP(vin2_data, 10),	1734	BUS_DATA_PIN_GROUP(vin2_data, 10),
1777	VIN_DATA_PIN_GROUP(vin2_data, 8),	1735	BUS_DATA_PIN_GROUP(vin2_data, 8),
1778	SH_PFC_PIN_GROUP(vin2_sync),	1736	SH_PFC_PIN_GROUP(vin2_sync),
1779	SH_PFC_PIN_GROUP(vin2_field),	1737	SH_PFC_PIN_GROUP(vin2_field),
1780	SH_PFC_PIN_GROUP(vin2_clkenb),	1738	SH_PFC_PIN_GROUP(vin2_clkenb),
1781	SH_PFC_PIN_GROUP(vin2_clk),	1739	SH_PFC_PIN_GROUP(vin2_clk),
1782	VIN_DATA_PIN_GROUP(vin3_data, 16),	1740	BUS_DATA_PIN_GROUP(vin3_data, 16),
1783	VIN_DATA_PIN_GROUP(vin3_data, 12),	1741	BUS_DATA_PIN_GROUP(vin3_data, 12),
1784	VIN_DATA_PIN_GROUP(vin3_data, 10),	1742	BUS_DATA_PIN_GROUP(vin3_data, 10),
1785	VIN_DATA_PIN_GROUP(vin3_data, 8),	1743	BUS_DATA_PIN_GROUP(vin3_data, 8),
1786	SH_PFC_PIN_GROUP(vin3_sync),	1744	SH_PFC_PIN_GROUP(vin3_sync),
1787	SH_PFC_PIN_GROUP(vin3_field),	1745	SH_PFC_PIN_GROUP(vin3_field),
1788	SH_PFC_PIN_GROUP(vin3_clkenb),	1746	SH_PFC_PIN_GROUP(vin3_clkenb),
1789	SH_PFC_PIN_GROUP(vin3_clk),	1747	SH_PFC_PIN_GROUP(vin3_clk),
1790	VIN_DATA_PIN_GROUP(vin4_data, 12),	1748	BUS_DATA_PIN_GROUP(vin4_data, 12),
1791	VIN_DATA_PIN_GROUP(vin4_data, 10),	1749	BUS_DATA_PIN_GROUP(vin4_data, 10),
1792	VIN_DATA_PIN_GROUP(vin4_data, 8),	1750	BUS_DATA_PIN_GROUP(vin4_data, 8),
1793	SH_PFC_PIN_GROUP(vin4_sync),	1751	SH_PFC_PIN_GROUP(vin4_sync),
1794	SH_PFC_PIN_GROUP(vin4_field),	1752	SH_PFC_PIN_GROUP(vin4_field),
1795	SH_PFC_PIN_GROUP(vin4_clkenb),	1753	SH_PFC_PIN_GROUP(vin4_clkenb),
1796	SH_PFC_PIN_GROUP(vin4_clk),	1754	SH_PFC_PIN_GROUP(vin4_clk),
1797	VIN_DATA_PIN_GROUP(vin5_data, 12),	1755	BUS_DATA_PIN_GROUP(vin5_data, 12),
1798	VIN_DATA_PIN_GROUP(vin5_data, 10),	1756	BUS_DATA_PIN_GROUP(vin5_data, 10),
1799	VIN_DATA_PIN_GROUP(vin5_data, 8),	1757	BUS_DATA_PIN_GROUP(vin5_data, 8),
1800	SH_PFC_PIN_GROUP(vin5_sync),	1758	SH_PFC_PIN_GROUP(vin5_sync),
1801	SH_PFC_PIN_GROUP(vin5_field),	1759	SH_PFC_PIN_GROUP(vin5_field),
1802	SH_PFC_PIN_GROUP(vin5_clkenb),	1760	SH_PFC_PIN_GROUP(vin5_clkenb),
@@ -3281,14 +3239,14 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { · 1478 unmodified lines
3281	{ /* sentinel */ }	3239	{ /* sentinel */ }
3282	};	3240	};
3283		3241
3284	static const struct sh_pfc_soc_operations r8a7792_pinmux_ops = {	3242	static const struct sh_pfc_soc_operations r8a7792_pfc_ops = {
3285	.get_bias = rcar_pinmux_get_bias,	3243	.get_bias = rcar_pinmux_get_bias,
3286	.set_bias = rcar_pinmux_set_bias,	3244	.set_bias = rcar_pinmux_set_bias,
3287	};	3245	};
3288		3246
3289	const struct sh_pfc_soc_info r8a7792_pinmux_info = {	3247	const struct sh_pfc_soc_info r8a7792_pinmux_info = {
3290	.name = "r8a77920_pfc",	3248	.name = "r8a77920_pfc",
3291	.ops = &r8a7792_pinmux_ops,	3249	.ops = &r8a7792_pfc_ops,
3292	.unlock_reg = 0xe6060000, /* PMMR */	3250	.unlock_reg = 0xe6060000, /* PMMR */
3293		3251
3294	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },	3252	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },

drivers/pinctrl/renesas/pfc-r8a7794.c+83−131

 	IRQ9_MARK,
 };
 /* - MMCIF ------------------------------------------------------------------ */
-static const unsigned int mmc_data1_pins[] = {
+static const unsigned int mmc_data_pins[] = {
-	/* D[0] */
-	RCAR_GP_PIN(6, 18),
-};
-static const unsigned int mmc_data1_mux[] = {
-	MMC_D0_MARK,
-};
-static const unsigned int mmc_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
-	RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
-};
-static const unsigned int mmc_data4_mux[] = {
-	MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
-};
-static const unsigned int mmc_data8_pins[] = {
 	/* D[0:7] */
 	RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
 	RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
 	RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
 	RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
 };
-static const unsigned int mmc_data8_mux[] = {
+static const unsigned int mmc_data_mux[] = {
 	MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
 	MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
 };
 static const unsigned int qspi_ctrl_mux[] = {
 	SPCLK_MARK, SSL_MARK,
 };
-static const unsigned int qspi_data2_pins[] = {
+static const unsigned int qspi_data_pins[] = {
-	/* MOSI_IO0, MISO_IO1 */
-	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
-};
-static const unsigned int qspi_data2_mux[] = {
-	MOSI_IO0_MARK, MISO_IO1_MARK,
-};
-static const unsigned int qspi_data4_pins[] = {
 	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
 	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
 	RCAR_GP_PIN(1, 8),
 };
-static const unsigned int qspi_data4_mux[] = {
+static const unsigned int qspi_data_mux[] = {
 	MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
 };
 /* - SCIF0 ------------------------------------------------------------------ */
 	SCIF_CLK_B_MARK,
 };
 /* - SDHI0 ------------------------------------------------------------------ */
-static const unsigned int sdhi0_data1_pins[] = {
+static const unsigned int sdhi0_data_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(6, 2),
-};
-static const unsigned int sdhi0_data1_mux[] = {
-	SD0_DATA0_MARK,
-};
-static const unsigned int sdhi0_data4_pins[] = {
 	/* D[0:3] */
 	RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
 	RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
 };
-static const unsigned int sdhi0_data4_mux[] = {
+static const unsigned int sdhi0_data_mux[] = {
 	SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK,
 };
 static const unsigned int sdhi0_ctrl_pins[] = {
 	SD0_WP_MARK,
 };
 /* - SDHI1 ------------------------------------------------------------------ */
-static const unsigned int sdhi1_data1_pins[] = {
+static const unsigned int sdhi1_data_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(6, 10),
-};
-static const unsigned int sdhi1_data1_mux[] = {
-	SD1_DATA0_MARK,
-};
-static const unsigned int sdhi1_data4_pins[] = {
 	/* D[0:3] */
 	RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
 	RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
 };
-static const unsigned int sdhi1_data4_mux[] = {
+static const unsigned int sdhi1_data_mux[] = {
 	SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK,
 };
 static const unsigned int sdhi1_ctrl_pins[] = {
 	SD1_WP_MARK,
 };
 /* - SDHI2 ------------------------------------------------------------------ */
-static const unsigned int sdhi2_data1_pins[] = {
+static const unsigned int sdhi2_data_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(6, 18),
-};
-static const unsigned int sdhi2_data1_mux[] = {
-	SD2_DATA0_MARK,
-};
-static const unsigned int sdhi2_data4_pins[] = {
 	/* D[0:3] */
 	RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
 	RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
 };
-static const unsigned int sdhi2_data4_mux[] = {
+static const unsigned int sdhi2_data_mux[] = {
 	SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK,
 };
 static const unsigned int sdhi2_ctrl_pins[] = {
 	USB1_OVC_MARK,
 };
 /* - VIN0 ------------------------------------------------------------------- */
-static const union vin_data vin0_data_pins = {
+static const unsigned int vin0_data_pins[] = {
-	.data24 = {
+	/* B */
-		/* B */
+	RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
-		RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
+	RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
-		RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
+	RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
-		RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
+	RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
-		RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
+	/* G */
-		/* G */
+	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
-		RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
+	RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
-		RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
+	RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
-		RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
+	RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
-		RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
+	/* R */
-		/* R */
+	RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22),
-		RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22),
+	RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
-		RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
+	RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
-		RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
+	RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
-		RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
-	},
 };
-static const union vin_data vin0_data_mux = {
+static const unsigned int vin0_data_mux[] = {
-	.data24 = {
+	/* B */
-		/* B */
+	VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
-		VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
+	VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
-		VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
+	VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
-		VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
+	VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
-		VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
+	/* G */
-		/* G */
+	VI0_G0_MARK, VI0_G1_MARK,
-		VI0_G0_MARK, VI0_G1_MARK,
+	VI0_G2_MARK, VI0_G3_MARK,
-		VI0_G2_MARK, VI0_G3_MARK,
+	VI0_G4_MARK, VI0_G5_MARK,
-		VI0_G4_MARK, VI0_G5_MARK,
+	VI0_G6_MARK, VI0_G7_MARK,
-		VI0_G6_MARK, VI0_G7_MARK,
+	/* R */
-		/* R */
+	VI0_R0_MARK, VI0_R1_MARK,
-		VI0_R0_MARK, VI0_R1_MARK,
+	VI0_R2_MARK, VI0_R3_MARK,
-		VI0_R2_MARK, VI0_R3_MARK,
+	VI0_R4_MARK, VI0_R5_MARK,
-		VI0_R4_MARK, VI0_R5_MARK,
+	VI0_R6_MARK, VI0_R7_MARK,
-		VI0_R6_MARK, VI0_R7_MARK,
-	},
 };
 static const unsigned int vin0_data18_pins[] = {
 	/* B */
 	VI0_CLK_MARK,
 };
 /* - VIN1 ------------------------------------------------------------------- */
-static const union vin_data12 vin1_data_pins = {
+static const unsigned int vin1_data_pins[] = {
-	.data12 = {
+	RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
-		RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
+	RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
-		RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
+	RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17),
-		RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17),
+	RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
-		RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
+	RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
-		RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
+	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
-		RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
-	},
 };
-static const union vin_data12 vin1_data_mux = {
+static const unsigned int vin1_data_mux[] = {
-	.data12 = {
+	VI1_DATA0_MARK, VI1_DATA1_MARK,
-		VI1_DATA0_MARK, VI1_DATA1_MARK,
+	VI1_DATA2_MARK, VI1_DATA3_MARK,
-		VI1_DATA2_MARK, VI1_DATA3_MARK,
+	VI1_DATA4_MARK, VI1_DATA5_MARK,
-		VI1_DATA4_MARK, VI1_DATA5_MARK,
+	VI1_DATA6_MARK, VI1_DATA7_MARK,
-		VI1_DATA6_MARK, VI1_DATA7_MARK,
+	VI1_DATA8_MARK, VI1_DATA9_MARK,
-		VI1_DATA8_MARK, VI1_DATA9_MARK,
+	VI1_DATA10_MARK, VI1_DATA11_MARK,
-		VI1_DATA10_MARK, VI1_DATA11_MARK,
-	},
 };
 static const unsigned int vin1_sync_pins[] = {
 	RCAR_GP_PIN(5, 22), /* HSYNC */
 	SH_PFC_PIN_GROUP(intc_irq7),
 	SH_PFC_PIN_GROUP(intc_irq8),
 	SH_PFC_PIN_GROUP(intc_irq9),
-	SH_PFC_PIN_GROUP(mmc_data1),
+	BUS_DATA_PIN_GROUP(mmc_data, 1),
-	SH_PFC_PIN_GROUP(mmc_data4),
+	BUS_DATA_PIN_GROUP(mmc_data, 4),
-	SH_PFC_PIN_GROUP(mmc_data8),
+	BUS_DATA_PIN_GROUP(mmc_data, 8),
 	SH_PFC_PIN_GROUP(mmc_ctrl),
 	SH_PFC_PIN_GROUP(msiof0_clk),
 	SH_PFC_PIN_GROUP(msiof0_sync),
 	SH_PFC_PIN_GROUP(pwm6),
 	SH_PFC_PIN_GROUP(pwm6_b),
 	SH_PFC_PIN_GROUP(qspi_ctrl),
-	SH_PFC_PIN_GROUP(qspi_data2),
+	BUS_DATA_PIN_GROUP(qspi_data, 2),
-	SH_PFC_PIN_GROUP(qspi_data4),
+	BUS_DATA_PIN_GROUP(qspi_data, 4),
 	SH_PFC_PIN_GROUP(scif0_data),
 	SH_PFC_PIN_GROUP(scif0_data_b),
 	SH_PFC_PIN_GROUP(scif0_data_c),
 	SH_PFC_PIN_GROUP(scifb2_ctrl),
 	SH_PFC_PIN_GROUP(scif_clk),
 	SH_PFC_PIN_GROUP(scif_clk_b),
-	SH_PFC_PIN_GROUP(sdhi0_data1),
+	BUS_DATA_PIN_GROUP(sdhi0_data, 1),
-	SH_PFC_PIN_GROUP(sdhi0_data4),
+	BUS_DATA_PIN_GROUP(sdhi0_data, 4),
 	SH_PFC_PIN_GROUP(sdhi0_ctrl),
 	SH_PFC_PIN_GROUP(sdhi0_cd),
 	SH_PFC_PIN_GROUP(sdhi0_wp),
-	SH_PFC_PIN_GROUP(sdhi1_data1),
+	BUS_DATA_PIN_GROUP(sdhi1_data, 1),
-	SH_PFC_PIN_GROUP(sdhi1_data4),
+	BUS_DATA_PIN_GROUP(sdhi1_data, 4),
 	SH_PFC_PIN_GROUP(sdhi1_ctrl),
 	SH_PFC_PIN_GROUP(sdhi1_cd),
 	SH_PFC_PIN_GROUP(sdhi1_wp),
-	SH_PFC_PIN_GROUP(sdhi2_data1),
+	BUS_DATA_PIN_GROUP(sdhi2_data, 1),
-	SH_PFC_PIN_GROUP(sdhi2_data4),
+	BUS_DATA_PIN_GROUP(sdhi2_data, 4),
 	SH_PFC_PIN_GROUP(sdhi2_ctrl),
 	SH_PFC_PIN_GROUP(sdhi2_cd),
 	SH_PFC_PIN_GROUP(sdhi2_wp),
 	SH_PFC_PIN_GROUP(tpu_to3_c),
 	SH_PFC_PIN_GROUP(usb0),
 	SH_PFC_PIN_GROUP(usb1),
-	VIN_DATA_PIN_GROUP(vin0_data, 24),
+	BUS_DATA_PIN_GROUP(vin0_data, 24),
-	VIN_DATA_PIN_GROUP(vin0_data, 20),
+	BUS_DATA_PIN_GROUP(vin0_data, 20),
 	SH_PFC_PIN_GROUP(vin0_data18),
-	VIN_DATA_PIN_GROUP(vin0_data, 16),
+	BUS_DATA_PIN_GROUP(vin0_data, 16),
-	VIN_DATA_PIN_GROUP(vin0_data, 12),
+	BUS_DATA_PIN_GROUP(vin0_data, 12),
-	VIN_DATA_PIN_GROUP(vin0_data, 10),
+	BUS_DATA_PIN_GROUP(vin0_data, 10),
-	VIN_DATA_PIN_GROUP(vin0_data, 8),
+	BUS_DATA_PIN_GROUP(vin0_data, 8),
 	SH_PFC_PIN_GROUP(vin0_sync),
 	SH_PFC_PIN_GROUP(vin0_field),
 	SH_PFC_PIN_GROUP(vin0_clkenb),
 	SH_PFC_PIN_GROUP(vin0_clk),
-	VIN_DATA_PIN_GROUP(vin1_data, 12),
+	BUS_DATA_PIN_GROUP(vin1_data, 12),
-	VIN_DATA_PIN_GROUP(vin1_data, 10),
+	BUS_DATA_PIN_GROUP(vin1_data, 10),
-	VIN_DATA_PIN_GROUP(vin1_data, 8),
+	BUS_DATA_PIN_GROUP(vin1_data, 8),
 	SH_PFC_PIN_GROUP(vin1_sync),
 	SH_PFC_PIN_GROUP(vin1_field),
 	SH_PFC_PIN_GROUP(vin1_clkenb),
 	{ },
 };
-static int r8a7794_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
+static int r8a7794_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
 {
+	if (pin < RCAR_GP_PIN(6, 0) || pin > RCAR_GP_PIN(6, 23))
+		return -EINVAL;
 	*pocctrl = 0xe606006c;
 	switch (pin & 0x1f) {
 	return 0;
 }
-static const struct sh_pfc_soc_operations r8a7794_pinmux_ops = {
+static const struct sh_pfc_soc_operations r8a7794_pfc_ops = {
 	.init = r8a7794_pinmux_soc_init,
 	.pin_to_pocctrl = r8a7794_pin_to_pocctrl,
 	.get_bias = rcar_pinmux_get_bias,
 #ifdef CONFIG_PINCTRL_PFC_R8A7745
 const struct sh_pfc_soc_info r8a7745_pinmux_info = {
 	.name = "r8a77450_pfc",
-	.ops = &r8a7794_pinmux_ops,
+	.ops = &r8a7794_pfc_ops,
 	.unlock_reg = 0xe6060000, /* PMMR */
 	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
 #ifdef CONFIG_PINCTRL_PFC_R8A7794
 const struct sh_pfc_soc_info r8a7794_pinmux_info = {
 	.name = "r8a77940_pfc",
-	.ops = &r8a7794_pinmux_ops,
+	.ops = &r8a7794_pfc_ops,
 	.unlock_reg = 0xe6060000, /* PMMR */
 	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },

drivers/pinctrl/renesas/pfc-r8a77950.c+29−90

 static const unsigned int qspi0_ctrl_mux[] = {
 	QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
 };
-static const unsigned int qspi0_data2_pins[] = {
+static const unsigned int qspi0_data_pins[] = {
-	/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
-	PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
-};
-static const unsigned int qspi0_data2_mux[] = {
-	QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
-};
-static const unsigned int qspi0_data4_pins[] = {
 	/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1, QSPI0_IO2, QSPI0_IO3 */
 	PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, PIN_QSPI0_IO2, PIN_QSPI0_IO3,
 };
-static const unsigned int qspi0_data4_mux[] = {
+static const unsigned int qspi0_data_mux[] = {
 	QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
 	QSPI0_IO2_MARK, QSPI0_IO3_MARK,
 };
 static const unsigned int qspi1_ctrl_mux[] = {
 	QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
 };
-static const unsigned int qspi1_data2_pins[] = {
+static const unsigned int qspi1_data_pins[] = {
-	/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
-	PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
-};
-static const unsigned int qspi1_data2_mux[] = {
-	QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
-};
-static const unsigned int qspi1_data4_pins[] = {
 	/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1, QSPI1_IO2, QSPI1_IO3 */
 	PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, PIN_QSPI1_IO2, PIN_QSPI1_IO3,
 };
-static const unsigned int qspi1_data4_mux[] = {
+static const unsigned int qspi1_data_mux[] = {
 	QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
 	QSPI1_IO2_MARK, QSPI1_IO3_MARK,
 };
 };
 /* - SDHI0 ------------------------------------------------------------------ */
-static const unsigned int sdhi0_data1_pins[] = {
+static const unsigned int sdhi0_data_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(3, 2),
-};
-static const unsigned int sdhi0_data1_mux[] = {
-	SD0_DAT0_MARK,
-};
-static const unsigned int sdhi0_data4_pins[] = {
 	/* D[0:3] */
 	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
 	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
 };
-static const unsigned int sdhi0_data4_mux[] = {
+static const unsigned int sdhi0_data_mux[] = {
 	SD0_DAT0_MARK, SD0_DAT1_MARK,
 	SD0_DAT2_MARK, SD0_DAT3_MARK,
 };
 	SD0_WP_MARK,
 };
 /* - SDHI1 ------------------------------------------------------------------ */
-static const unsigned int sdhi1_data1_pins[] = {
+static const unsigned int sdhi1_data_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(3, 8),
-};
-static const unsigned int sdhi1_data1_mux[] = {
-	SD1_DAT0_MARK,
-};
-static const unsigned int sdhi1_data4_pins[] = {
 	/* D[0:3] */
 	RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
 	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
 };
-static const unsigned int sdhi1_data4_mux[] = {
+static const unsigned int sdhi1_data_mux[] = {
 	SD1_DAT0_MARK, SD1_DAT1_MARK,
 	SD1_DAT2_MARK, SD1_DAT3_MARK,
 };
 	SD1_WP_MARK,
 };
 /* - SDHI2 ------------------------------------------------------------------ */
-static const unsigned int sdhi2_data1_pins[] = {
+static const unsigned int sdhi2_data_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(4, 2),
-};
-static const unsigned int sdhi2_data1_mux[] = {
-	SD2_DAT0_MARK,
-};
-static const unsigned int sdhi2_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
-	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
-};
-static const unsigned int sdhi2_data4_mux[] = {
-	SD2_DAT0_MARK, SD2_DAT1_MARK,
-	SD2_DAT2_MARK, SD2_DAT3_MARK,
-};
-static const unsigned int sdhi2_data8_pins[] = {
 	/* D[0:7] */
 	RCAR_GP_PIN(4, 2),  RCAR_GP_PIN(4, 3),
 	RCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 5),
 	RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
 	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
 };
-static const unsigned int sdhi2_data8_mux[] = {
+static const unsigned int sdhi2_data_mux[] = {
 	SD2_DAT0_MARK, SD2_DAT1_MARK,
 	SD2_DAT2_MARK, SD2_DAT3_MARK,
 	SD2_DAT4_MARK, SD2_DAT5_MARK,
 	SD2_DS_MARK,
 };
 /* - SDHI3 ------------------------------------------------------------------ */
-static const unsigned int sdhi3_data1_pins[] = {
+static const unsigned int sdhi3_data_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(4, 9),
-};
-static const unsigned int sdhi3_data1_mux[] = {
-	SD3_DAT0_MARK,
-};
-static const unsigned int sdhi3_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
-	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
-};
-static const unsigned int sdhi3_data4_mux[] = {
-	SD3_DAT0_MARK, SD3_DAT1_MARK,
-	SD3_DAT2_MARK, SD3_DAT3_MARK,
-};
-static const unsigned int sdhi3_data8_pins[] = {
 	/* D[0:7] */
 	RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
 	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
 	RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
 	RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
 };
-static const unsigned int sdhi3_data8_mux[] = {
+static const unsigned int sdhi3_data_mux[] = {
 	SD3_DAT0_MARK, SD3_DAT1_MARK,
 	SD3_DAT2_MARK, SD3_DAT3_MARK,
 	SD3_DAT4_MARK, SD3_DAT5_MARK,
 	SH_PFC_PIN_GROUP(pwm6_a),
 	SH_PFC_PIN_GROUP(pwm6_b),
 	SH_PFC_PIN_GROUP(qspi0_ctrl),
-	SH_PFC_PIN_GROUP(qspi0_data2),
+	BUS_DATA_PIN_GROUP(qspi0_data, 2),
-	SH_PFC_PIN_GROUP(qspi0_data4),
+	BUS_DATA_PIN_GROUP(qspi0_data, 4),
 	SH_PFC_PIN_GROUP(qspi1_ctrl),
-	SH_PFC_PIN_GROUP(qspi1_data2),
+	BUS_DATA_PIN_GROUP(qspi1_data, 2),
-	SH_PFC_PIN_GROUP(qspi1_data4),
+	BUS_DATA_PIN_GROUP(qspi1_data, 4),
 	SH_PFC_PIN_GROUP(sata0_devslp_a),
 	SH_PFC_PIN_GROUP(sata0_devslp_b),
 	SH_PFC_PIN_GROUP(scif0_data),
 	SH_PFC_PIN_GROUP(scif5_clk),
 	SH_PFC_PIN_GROUP(scif_clk_a),
 	SH_PFC_PIN_GROUP(scif_clk_b),
-	SH_PFC_PIN_GROUP(sdhi0_data1),
+	BUS_DATA_PIN_GROUP(sdhi0_data, 1),
-	SH_PFC_PIN_GROUP(sdhi0_data4),
+	BUS_DATA_PIN_GROUP(sdhi0_data, 4),
 	SH_PFC_PIN_GROUP(sdhi0_ctrl),
 	SH_PFC_PIN_GROUP(sdhi0_cd),
 	SH_PFC_PIN_GROUP(sdhi0_wp),
-	SH_PFC_PIN_GROUP(sdhi1_data1),
+	BUS_DATA_PIN_GROUP(sdhi1_data, 1),
-	SH_PFC_PIN_GROUP(sdhi1_data4),
+	BUS_DATA_PIN_GROUP(sdhi1_data, 4),
 	SH_PFC_PIN_GROUP(sdhi1_ctrl),
 	SH_PFC_PIN_GROUP(sdhi1_cd),
 	SH_PFC_PIN_GROUP(sdhi1_wp),
-	SH_PFC_PIN_GROUP(sdhi2_data1),
+	BUS_DATA_PIN_GROUP(sdhi2_data, 1),
-	SH_PFC_PIN_GROUP(sdhi2_data4),
+	BUS_DATA_PIN_GROUP(sdhi2_data, 4),
-	SH_PFC_PIN_GROUP(sdhi2_data8),
+	BUS_DATA_PIN_GROUP(sdhi2_data, 8),
 	SH_PFC_PIN_GROUP(sdhi2_ctrl),
 	SH_PFC_PIN_GROUP(sdhi2_cd_a),
 	SH_PFC_PIN_GROUP(sdhi2_wp_a),
 	SH_PFC_PIN_GROUP(sdhi2_cd_b),
 	SH_PFC_PIN_GROUP(sdhi2_wp_b),
 	SH_PFC_PIN_GROUP(sdhi2_ds),
-	SH_PFC_PIN_GROUP(sdhi3_data1),
+	BUS_DATA_PIN_GROUP(sdhi3_data, 1),
-	SH_PFC_PIN_GROUP(sdhi3_data4),
+	BUS_DATA_PIN_GROUP(sdhi3_data, 4),
-	SH_PFC_PIN_GROUP(sdhi3_data8),
+	BUS_DATA_PIN_GROUP(sdhi3_data, 8),
 	SH_PFC_PIN_GROUP(sdhi3_ctrl),
 	SH_PFC_PIN_GROUP(sdhi3_cd),
 	SH_PFC_PIN_GROUP(sdhi3_wp),
 	{ /* sentinel */ },
 };
-static int r8a77950_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
+static int r8a77950_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
-				   u32 *pocctrl)
 {
 	int bit = -EINVAL;
 	{ /* sentinel */ },
 };
-static const struct sh_pfc_soc_operations r8a77950_pinmux_ops = {
+static const struct sh_pfc_soc_operations r8a77950_pfc_ops = {
 	.pin_to_pocctrl = r8a77950_pin_to_pocctrl,
 	.get_bias = rcar_pinmux_get_bias,
 	.set_bias = rcar_pinmux_set_bias,
 const struct sh_pfc_soc_info r8a77950_pinmux_info = {
 	.name = "r8a77950_pfc",
-	.ops = &r8a77950_pinmux_ops,
+	.ops = &r8a77950_pfc_ops,
 	.unlock_reg = 0xe6060000, /* PMMR */
 	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },

drivers/pinctrl/renesas/pfc-r8a77951.c+108−205

 static const unsigned int qspi0_ctrl_mux[] = {
 	QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
 };
-static const unsigned int qspi0_data2_pins[] = {
+static const unsigned int qspi0_data_pins[] = {
-	/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
-	PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
-};
-static const unsigned int qspi0_data2_mux[] = {
-	QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
-};
-static const unsigned int qspi0_data4_pins[] = {
 	/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
 	PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
 	/* QSPI0_IO2, QSPI0_IO3 */
 	PIN_QSPI0_IO2, PIN_QSPI0_IO3,
 };
-static const unsigned int qspi0_data4_mux[] = {
+static const unsigned int qspi0_data_mux[] = {
 	QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
 	QSPI0_IO2_MARK, QSPI0_IO3_MARK,
 };
 static const unsigned int qspi1_ctrl_mux[] = {
 	QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
 };
-static const unsigned int qspi1_data2_pins[] = {
+static const unsigned int qspi1_data_pins[] = {
-	/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
-	PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
-};
-static const unsigned int qspi1_data2_mux[] = {
-	QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
-};
-static const unsigned int qspi1_data4_pins[] = {
 	/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
 	PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
 	/* QSPI1_IO2, QSPI1_IO3 */
 	PIN_QSPI1_IO2, PIN_QSPI1_IO3,
 };
-static const unsigned int qspi1_data4_mux[] = {
+static const unsigned int qspi1_data_mux[] = {
 	QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
 	QSPI1_IO2_MARK, QSPI1_IO3_MARK,
 };
 };
 /* - SDHI0 ------------------------------------------------------------------ */
-static const unsigned int sdhi0_data1_pins[] = {
+static const unsigned int sdhi0_data_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(3, 2),
-};
-static const unsigned int sdhi0_data1_mux[] = {
-	SD0_DAT0_MARK,
-};
-static const unsigned int sdhi0_data4_pins[] = {
 	/* D[0:3] */
 	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
 	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
 };
-static const unsigned int sdhi0_data4_mux[] = {
+static const unsigned int sdhi0_data_mux[] = {
 	SD0_DAT0_MARK, SD0_DAT1_MARK,
 	SD0_DAT2_MARK, SD0_DAT3_MARK,
 };
 	SD0_WP_MARK,
 };
 /* - SDHI1 ------------------------------------------------------------------ */
-static const unsigned int sdhi1_data1_pins[] = {
+static const unsigned int sdhi1_data_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(3, 8),
-};
-static const unsigned int sdhi1_data1_mux[] = {
-	SD1_DAT0_MARK,
-};
-static const unsigned int sdhi1_data4_pins[] = {
 	/* D[0:3] */
 	RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
 	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
 };
-static const unsigned int sdhi1_data4_mux[] = {
+static const unsigned int sdhi1_data_mux[] = {
 	SD1_DAT0_MARK, SD1_DAT1_MARK,
 	SD1_DAT2_MARK, SD1_DAT3_MARK,
 };
 	SD1_WP_MARK,
 };
 /* - SDHI2 ------------------------------------------------------------------ */
-static const unsigned int sdhi2_data1_pins[] = {
+static const unsigned int sdhi2_data_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(4, 2),
-};
-static const unsigned int sdhi2_data1_mux[] = {
-	SD2_DAT0_MARK,
-};
-static const unsigned int sdhi2_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
-	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
-};
-static const unsigned int sdhi2_data4_mux[] = {
-	SD2_DAT0_MARK, SD2_DAT1_MARK,
-	SD2_DAT2_MARK, SD2_DAT3_MARK,
-};
-static const unsigned int sdhi2_data8_pins[] = {
 	/* D[0:7] */
 	RCAR_GP_PIN(4, 2),  RCAR_GP_PIN(4, 3),
 	RCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 5),
 	RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
 	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
 };
-static const unsigned int sdhi2_data8_mux[] = {
+static const unsigned int sdhi2_data_mux[] = {
 	SD2_DAT0_MARK, SD2_DAT1_MARK,
 	SD2_DAT2_MARK, SD2_DAT3_MARK,
 	SD2_DAT4_MARK, SD2_DAT5_MARK,
 	SD2_DS_MARK,
 };
 /* - SDHI3 ------------------------------------------------------------------ */
-static const unsigned int sdhi3_data1_pins[] = {
+static const unsigned int sdhi3_data_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(4, 9),
-};
-static const unsigned int sdhi3_data1_mux[] = {
-	SD3_DAT0_MARK,
-};
-static const unsigned int sdhi3_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
-	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
-};
-static const unsigned int sdhi3_data4_mux[] = {
-	SD3_DAT0_MARK, SD3_DAT1_MARK,
-	SD3_DAT2_MARK, SD3_DAT3_MARK,
-};
-static const unsigned int sdhi3_data8_pins[] = {
 	/* D[0:7] */
 	RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
 	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
 	RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
 	RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
 };
-static const unsigned int sdhi3_data8_mux[] = {
+static const unsigned int sdhi3_data_mux[] = {
 	SD3_DAT0_MARK, SD3_DAT1_MARK,
 	SD3_DAT2_MARK, SD3_DAT3_MARK,
 	SD3_DAT4_MARK, SD3_DAT5_MARK,
 	VI4_DATA20_MARK, VI4_DATA21_MARK,
 	VI4_DATA22_MARK, VI4_DATA23_MARK,
 };
-static const union vin_data vin4_data_a_pins = {
+static const unsigned int vin4_data_a_pins[] = {
-	.data24 = {
+	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
-		RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
+	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
-		RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
-		RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
+	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
-		RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
-		RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
+	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
-		RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
-		RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
-		RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
-		RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
-		RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
-		RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
-		RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
-	},
-};
-static const union vin_data vin4_data_a_mux = {
-	.data24 = {
-		VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
-		VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
-		VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
-		VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
-		VI4_DATA8_MARK,  VI4_DATA9_MARK,
-		VI4_DATA10_MARK, VI4_DATA11_MARK,
-		VI4_DATA12_MARK, VI4_DATA13_MARK,
-		VI4_DATA14_MARK, VI4_DATA15_MARK,
-		VI4_DATA16_MARK, VI4_DATA17_MARK,
-		VI4_DATA18_MARK, VI4_DATA19_MARK,
-		VI4_DATA20_MARK, VI4_DATA21_MARK,
-		VI4_DATA22_MARK, VI4_DATA23_MARK,
-	},
-};
-static const union vin_data vin4_data_b_pins = {
-	.data24 = {
-		RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
-		RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
-		RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
-		RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
-		RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
-		RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
-		RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
-		RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
-		RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
-		RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
-		RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
-		RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
-	},
 };
-static const union vin_data vin4_data_b_mux = {
+static const unsigned int vin4_data_a_mux[] = {
-	.data24 = {
+	VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
-		VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
+	VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
-		VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
+	VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
-		VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
+	VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
-		VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
+	VI4_DATA8_MARK,  VI4_DATA9_MARK,
-		VI4_DATA8_MARK,  VI4_DATA9_MARK,
+	VI4_DATA10_MARK, VI4_DATA11_MARK,
-		VI4_DATA10_MARK, VI4_DATA11_MARK,
+	VI4_DATA12_MARK, VI4_DATA13_MARK,
-		VI4_DATA12_MARK, VI4_DATA13_MARK,
+	VI4_DATA14_MARK, VI4_DATA15_MARK,
-		VI4_DATA14_MARK, VI4_DATA15_MARK,
+	VI4_DATA16_MARK, VI4_DATA17_MARK,
-		VI4_DATA16_MARK, VI4_DATA17_MARK,
+	VI4_DATA18_MARK, VI4_DATA19_MARK,
-		VI4_DATA18_MARK, VI4_DATA19_MARK,
+	VI4_DATA20_MARK, VI4_DATA21_MARK,
-		VI4_DATA20_MARK, VI4_DATA21_MARK,
+	VI4_DATA22_MARK, VI4_DATA23_MARK,
-		VI4_DATA22_MARK, VI4_DATA23_MARK,
-	},
 };
-static const unsigned int vin4_g8_pins[] = {
+static const unsigned int vin4_data_b_pins[] = {
-	RCAR_GP_PIN(1, 0),  RCAR_GP_PIN(1, 1),
+	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
-	RCAR_GP_PIN(1, 2),  RCAR_GP_PIN(1, 3),
+	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
-	RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 5),
+	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
-	RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 7),
+	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
+	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
+	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
 };
-static const unsigned int vin4_g8_mux[] = {
+static const unsigned int vin4_data_b_mux[] = {
+	VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
+	VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
+	VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
+	VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
 	VI4_DATA8_MARK,  VI4_DATA9_MARK,
 	VI4_DATA10_MARK, VI4_DATA11_MARK,
 	VI4_DATA12_MARK, VI4_DATA13_MARK,
 	VI4_DATA14_MARK, VI4_DATA15_MARK,
+	VI4_DATA16_MARK, VI4_DATA17_MARK,
+	VI4_DATA18_MARK, VI4_DATA19_MARK,
+	VI4_DATA20_MARK, VI4_DATA21_MARK,
+	VI4_DATA22_MARK, VI4_DATA23_MARK,
 };
 static const unsigned int vin4_sync_pins[] = {
 	/* HSYNC#, VSYNC# */
 };
 /* - VIN5 ------------------------------------------------------------------- */
-static const union vin_data16 vin5_data_pins = {
+static const unsigned int vin5_data_pins[] = {
-	.data16 = {
+	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
-		RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
-		RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
-		RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
-		RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
-		RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
-		RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
-		RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
-		RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
-	},
-};
-static const union vin_data16 vin5_data_mux = {
-	.data16 = {
-		VI5_DATA0_MARK, VI5_DATA1_MARK,
-		VI5_DATA2_MARK, VI5_DATA3_MARK,
-		VI5_DATA4_MARK, VI5_DATA5_MARK,
-		VI5_DATA6_MARK, VI5_DATA7_MARK,
-		VI5_DATA8_MARK,  VI5_DATA9_MARK,
-		VI5_DATA10_MARK, VI5_DATA11_MARK,
-		VI5_DATA12_MARK, VI5_DATA13_MARK,
-		VI5_DATA14_MARK, VI5_DATA15_MARK,
-	},
-};
-static const unsigned int vin5_high8_pins[] = {
 	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
 	RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
-	RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 5),
+	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
-	RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 7),
+	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
 };
-static const unsigned int vin5_high8_mux[] = {
+static const unsigned int vin5_data_mux[] = {
+	VI5_DATA0_MARK, VI5_DATA1_MARK,
+	VI5_DATA2_MARK, VI5_DATA3_MARK,
+	VI5_DATA4_MARK, VI5_DATA5_MARK,
+	VI5_DATA6_MARK, VI5_DATA7_MARK,
 	VI5_DATA8_MARK,  VI5_DATA9_MARK,
 	VI5_DATA10_MARK, VI5_DATA11_MARK,
 	VI5_DATA12_MARK, VI5_DATA13_MARK,
 		SH_PFC_PIN_GROUP(pwm6_a),
 		SH_PFC_PIN_GROUP(pwm6_b),
 		SH_PFC_PIN_GROUP(qspi0_ctrl),
-		SH_PFC_PIN_GROUP(qspi0_data2),
+		BUS_DATA_PIN_GROUP(qspi0_data, 2),
-		SH_PFC_PIN_GROUP(qspi0_data4),
+		BUS_DATA_PIN_GROUP(qspi0_data, 4),
 		SH_PFC_PIN_GROUP(qspi1_ctrl),
-		SH_PFC_PIN_GROUP(qspi1_data2),
+		BUS_DATA_PIN_GROUP(qspi1_data, 2),
-		SH_PFC_PIN_GROUP(qspi1_data4),
+		BUS_DATA_PIN_GROUP(qspi1_data, 4),
 		SH_PFC_PIN_GROUP(sata0_devslp_a),
 		SH_PFC_PIN_GROUP(sata0_devslp_b),
 		SH_PFC_PIN_GROUP(scif0_data),
 		SH_PFC_PIN_GROUP(scif5_clk_b),
 		SH_PFC_PIN_GROUP(scif_clk_a),
 		SH_PFC_PIN_GROUP(scif_clk_b),
-		SH_PFC_PIN_GROUP(sdhi0_data1),
+		BUS_DATA_PIN_GROUP(sdhi0_data, 1),
-		SH_PFC_PIN_GROUP(sdhi0_data4),
+		BUS_DATA_PIN_GROUP(sdhi0_data, 4),
 		SH_PFC_PIN_GROUP(sdhi0_ctrl),
 		SH_PFC_PIN_GROUP(sdhi0_cd),
 		SH_PFC_PIN_GROUP(sdhi0_wp),
-		SH_PFC_PIN_GROUP(sdhi1_data1),
+		BUS_DATA_PIN_GROUP(sdhi1_data, 1),
-		SH_PFC_PIN_GROUP(sdhi1_data4),
+		BUS_DATA_PIN_GROUP(sdhi1_data, 4),
 		SH_PFC_PIN_GROUP(sdhi1_ctrl),
 		SH_PFC_PIN_GROUP(sdhi1_cd),
 		SH_PFC_PIN_GROUP(sdhi1_wp),
-		SH_PFC_PIN_GROUP(sdhi2_data1),
+		BUS_DATA_PIN_GROUP(sdhi2_data, 1),
-		SH_PFC_PIN_GROUP(sdhi2_data4),
+		BUS_DATA_PIN_GROUP(sdhi2_data, 4),
-		SH_PFC_PIN_GROUP(sdhi2_data8),
+		BUS_DATA_PIN_GROUP(sdhi2_data, 8),
 		SH_PFC_PIN_GROUP(sdhi2_ctrl),
 		SH_PFC_PIN_GROUP(sdhi2_cd_a),
 		SH_PFC_PIN_GROUP(sdhi2_wp_a),
 		SH_PFC_PIN_GROUP(sdhi2_cd_b),
 		SH_PFC_PIN_GROUP(sdhi2_wp_b),
 		SH_PFC_PIN_GROUP(sdhi2_ds),
-		SH_PFC_PIN_GROUP(sdhi3_data1),
+		BUS_DATA_PIN_GROUP(sdhi3_data, 1),
-		SH_PFC_PIN_GROUP(sdhi3_data4),
+		BUS_DATA_PIN_GROUP(sdhi3_data, 4),
-		SH_PFC_PIN_GROUP(sdhi3_data8),
+		BUS_DATA_PIN_GROUP(sdhi3_data, 8),
 		SH_PFC_PIN_GROUP(sdhi3_ctrl),
 		SH_PFC_PIN_GROUP(sdhi3_cd),
 		SH_PFC_PIN_GROUP(sdhi3_wp),
 		SH_PFC_PIN_GROUP(usb2),
 		SH_PFC_PIN_GROUP(usb2_ch3),
 		SH_PFC_PIN_GROUP(usb30),
-		VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
+		BUS_DATA_PIN_GROUP(vin4_data, 8, _a),
-		VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
+		BUS_DATA_PIN_GROUP(vin4_data, 10, _a),
-		VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
+		BUS_DATA_PIN_GROUP(vin4_data, 12, _a),
-		VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
+		BUS_DATA_PIN_GROUP(vin4_data, 16, _a),
 		SH_PFC_PIN_GROUP(vin4_data18_a),
-		VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
+		BUS_DATA_PIN_GROUP(vin4_data, 20, _a),
-		VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
+		BUS_DATA_PIN_GROUP(vin4_data, 24, _a),
-		VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
+		BUS_DATA_PIN_GROUP(vin4_data, 8, _b),
-		VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
+		BUS_DATA_PIN_GROUP(vin4_data, 10, _b),
-		VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
+		BUS_DATA_PIN_GROUP(vin4_data, 12, _b),
-		VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
+		BUS_DATA_PIN_GROUP(vin4_data, 16, _b),
 		SH_PFC_PIN_GROUP(vin4_data18_b),
-		VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
+		BUS_DATA_PIN_GROUP(vin4_data, 20, _b),
-		VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
+		BUS_DATA_PIN_GROUP(vin4_data, 24, _b),
-		SH_PFC_PIN_GROUP(vin4_g8),
+		SH_PFC_PIN_GROUP_SUBSET(vin4_g8, vin4_data_a, 8, 8),
 		SH_PFC_PIN_GROUP(vin4_sync),
 		SH_PFC_PIN_GROUP(vin4_field),
 		SH_PFC_PIN_GROUP(vin4_clkenb),
 		SH_PFC_PIN_GROUP(vin4_clk),
-		VIN_DATA_PIN_GROUP(vin5_data, 8),
+		BUS_DATA_PIN_GROUP(vin5_data, 8),
-		VIN_DATA_PIN_GROUP(vin5_data, 10),
+		BUS_DATA_PIN_GROUP(vin5_data, 10),
-		VIN_DATA_PIN_GROUP(vin5_data, 12),
+		BUS_DATA_PIN_GROUP(vin5_data, 12),
-		VIN_DATA_PIN_GROUP(vin5_data, 16),
+		BUS_DATA_PIN_GROUP(vin5_data, 16),
-		SH_PFC_PIN_GROUP(vin5_high8),
+		SH_PFC_PIN_GROUP_SUBSET(vin5_high8, vin5_data, 8, 8),
 		SH_PFC_PIN_GROUP(vin5_sync),
 		SH_PFC_PIN_GROUP(vin5_field),
 		SH_PFC_PIN_GROUP(vin5_clkenb),
 	{ /* sentinel */ },
 };
-static int r8a77951_pin_to_pocctrl(struct sh_pfc *pfc,
+static int r8a77951_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
-				   unsigned int pin, u32 *pocctrl)
 {
 	int bit = -EINVAL;
 	{ /* sentinel */ },
 };
-static const struct sh_pfc_soc_operations r8a77951_pinmux_ops = {
+static const struct sh_pfc_soc_operations r8a77951_pfc_ops = {
 	.pin_to_pocctrl = r8a77951_pin_to_pocctrl,
 	.get_bias = rcar_pinmux_get_bias,
 	.set_bias = rcar_pinmux_set_bias,
 #ifdef CONFIG_PINCTRL_PFC_R8A774E1
 const struct sh_pfc_soc_info r8a774e1_pinmux_info = {
 	.name = "r8a774e1_pfc",
-	.ops = &r8a77951_pinmux_ops,
+	.ops = &r8a77951_pfc_ops,
 	.unlock_reg = 0xe6060000, /* PMMR */
 	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
 #ifdef CONFIG_PINCTRL_PFC_R8A77951
 const struct sh_pfc_soc_info r8a77951_pinmux_info = {
 	.name = "r8a77951_pfc",
-	.ops = &r8a77951_pinmux_ops,
+	.ops = &r8a77951_pfc_ops,
 	.unlock_reg = 0xe6060000, /* PMMR */
 	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },

drivers/pinctrl/renesas/pfc-r8a7796.c+109−206

 static const unsigned int qspi0_ctrl_mux[] = {
 	QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
 };
-static const unsigned int qspi0_data2_pins[] = {
+static const unsigned int qspi0_data_pins[] = {
-	/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
-	PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
-};
-static const unsigned int qspi0_data2_mux[] = {
-	QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
-};
-static const unsigned int qspi0_data4_pins[] = {
 	/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
 	PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
 	/* QSPI0_IO2, QSPI0_IO3 */
 	PIN_QSPI0_IO2, PIN_QSPI0_IO3,
 };
-static const unsigned int qspi0_data4_mux[] = {
+static const unsigned int qspi0_data_mux[] = {
 	QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
 	QSPI0_IO2_MARK, QSPI0_IO3_MARK,
 };
 static const unsigned int qspi1_ctrl_mux[] = {
 	QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
 };
-static const unsigned int qspi1_data2_pins[] = {
+static const unsigned int qspi1_data_pins[] = {
-	/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
-	PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
-};
-static const unsigned int qspi1_data2_mux[] = {
-	QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
-};
-static const unsigned int qspi1_data4_pins[] = {
 	/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
 	PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
 	/* QSPI1_IO2, QSPI1_IO3 */
 	PIN_QSPI1_IO2, PIN_QSPI1_IO3,
 };
-static const unsigned int qspi1_data4_mux[] = {
+static const unsigned int qspi1_data_mux[] = {
 	QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
 	QSPI1_IO2_MARK, QSPI1_IO3_MARK,
 };
 };
 /* - SDHI0 ------------------------------------------------------------------ */
-static const unsigned int sdhi0_data1_pins[] = {
+static const unsigned int sdhi0_data_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(3, 2),
-};
-static const unsigned int sdhi0_data1_mux[] = {
-	SD0_DAT0_MARK,
-};
-static const unsigned int sdhi0_data4_pins[] = {
 	/* D[0:3] */
 	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
 	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
 };
-static const unsigned int sdhi0_data4_mux[] = {
+static const unsigned int sdhi0_data_mux[] = {
 	SD0_DAT0_MARK, SD0_DAT1_MARK,
 	SD0_DAT2_MARK, SD0_DAT3_MARK,
 };
 	SD0_WP_MARK,
 };
 /* - SDHI1 ------------------------------------------------------------------ */
-static const unsigned int sdhi1_data1_pins[] = {
+static const unsigned int sdhi1_data_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(3, 8),
-};
-static const unsigned int sdhi1_data1_mux[] = {
-	SD1_DAT0_MARK,
-};
-static const unsigned int sdhi1_data4_pins[] = {
 	/* D[0:3] */
 	RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
 	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
 };
-static const unsigned int sdhi1_data4_mux[] = {
+static const unsigned int sdhi1_data_mux[] = {
 	SD1_DAT0_MARK, SD1_DAT1_MARK,
 	SD1_DAT2_MARK, SD1_DAT3_MARK,
 };
 	SD1_WP_MARK,
 };
 /* - SDHI2 ------------------------------------------------------------------ */
-static const unsigned int sdhi2_data1_pins[] = {
+static const unsigned int sdhi2_data_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(4, 2),
-};
-static const unsigned int sdhi2_data1_mux[] = {
-	SD2_DAT0_MARK,
-};
-static const unsigned int sdhi2_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
-	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
-};
-static const unsigned int sdhi2_data4_mux[] = {
-	SD2_DAT0_MARK, SD2_DAT1_MARK,
-	SD2_DAT2_MARK, SD2_DAT3_MARK,
-};
-static const unsigned int sdhi2_data8_pins[] = {
 	/* D[0:7] */
 	RCAR_GP_PIN(4, 2),  RCAR_GP_PIN(4, 3),
 	RCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 5),
 	RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
 	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
 };
-static const unsigned int sdhi2_data8_mux[] = {
+static const unsigned int sdhi2_data_mux[] = {
 	SD2_DAT0_MARK, SD2_DAT1_MARK,
 	SD2_DAT2_MARK, SD2_DAT3_MARK,
 	SD2_DAT4_MARK, SD2_DAT5_MARK,
 	SD2_DS_MARK,
 };
 /* - SDHI3 ------------------------------------------------------------------ */
-static const unsigned int sdhi3_data1_pins[] = {
+static const unsigned int sdhi3_data_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(4, 9),
-};
-static const unsigned int sdhi3_data1_mux[] = {
-	SD3_DAT0_MARK,
-};
-static const unsigned int sdhi3_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
-	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
-};
-static const unsigned int sdhi3_data4_mux[] = {
-	SD3_DAT0_MARK, SD3_DAT1_MARK,
-	SD3_DAT2_MARK, SD3_DAT3_MARK,
-};
-static const unsigned int sdhi3_data8_pins[] = {
 	/* D[0:7] */
 	RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
 	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
 	RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
 	RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
 };
-static const unsigned int sdhi3_data8_mux[] = {
+static const unsigned int sdhi3_data_mux[] = {
 	SD3_DAT0_MARK, SD3_DAT1_MARK,
 	SD3_DAT2_MARK, SD3_DAT3_MARK,
 	SD3_DAT4_MARK, SD3_DAT5_MARK,
 	VI4_DATA20_MARK, VI4_DATA21_MARK,
 	VI4_DATA22_MARK, VI4_DATA23_MARK,
 };
-static const union vin_data vin4_data_a_pins = {
+static const unsigned int vin4_data_a_pins[] = {
-	.data24 = {
+	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
-		RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
+	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
-		RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
-		RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
+	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
-		RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
-		RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
+	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
-		RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
-		RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
-		RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
-		RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
-		RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
-		RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
-		RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
-	},
-};
-static const union vin_data vin4_data_a_mux = {
-	.data24 = {
-		VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
-		VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
-		VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
-		VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
-		VI4_DATA8_MARK,  VI4_DATA9_MARK,
-		VI4_DATA10_MARK, VI4_DATA11_MARK,
-		VI4_DATA12_MARK, VI4_DATA13_MARK,
-		VI4_DATA14_MARK, VI4_DATA15_MARK,
-		VI4_DATA16_MARK, VI4_DATA17_MARK,
-		VI4_DATA18_MARK, VI4_DATA19_MARK,
-		VI4_DATA20_MARK, VI4_DATA21_MARK,
-		VI4_DATA22_MARK, VI4_DATA23_MARK,
-	},
-};
-static const union vin_data vin4_data_b_pins = {
-	.data24 = {
-		RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
-		RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
-		RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
-		RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
-		RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
-		RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
-		RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
-		RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
-		RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
-		RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
-		RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
-		RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
-	},
 };
-static const union vin_data vin4_data_b_mux = {
+static const unsigned int vin4_data_a_mux[] = {
-	.data24 = {
+	VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
-		VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
+	VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
-		VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
+	VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
-		VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
+	VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
-		VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
+	VI4_DATA8_MARK,  VI4_DATA9_MARK,
-		VI4_DATA8_MARK,  VI4_DATA9_MARK,
+	VI4_DATA10_MARK, VI4_DATA11_MARK,
-		VI4_DATA10_MARK, VI4_DATA11_MARK,
+	VI4_DATA12_MARK, VI4_DATA13_MARK,
-		VI4_DATA12_MARK, VI4_DATA13_MARK,
+	VI4_DATA14_MARK, VI4_DATA15_MARK,
-		VI4_DATA14_MARK, VI4_DATA15_MARK,
+	VI4_DATA16_MARK, VI4_DATA17_MARK,
-		VI4_DATA16_MARK, VI4_DATA17_MARK,
+	VI4_DATA18_MARK, VI4_DATA19_MARK,
-		VI4_DATA18_MARK, VI4_DATA19_MARK,
+	VI4_DATA20_MARK, VI4_DATA21_MARK,
-		VI4_DATA20_MARK, VI4_DATA21_MARK,
+	VI4_DATA22_MARK, VI4_DATA23_MARK,
-		VI4_DATA22_MARK, VI4_DATA23_MARK,
-	},
 };
-static const unsigned int vin4_g8_pins[] = {
+static const unsigned int vin4_data_b_pins[] = {
-	RCAR_GP_PIN(1, 0),  RCAR_GP_PIN(1, 1),
+	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
-	RCAR_GP_PIN(1, 2),  RCAR_GP_PIN(1, 3),
+	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
-	RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 5),
+	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
-	RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 7),
+	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
+	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
+	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
 };
-static const unsigned int vin4_g8_mux[] = {
+static const unsigned int vin4_data_b_mux[] = {
+	VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
+	VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
+	VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
+	VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
 	VI4_DATA8_MARK,  VI4_DATA9_MARK,
 	VI4_DATA10_MARK, VI4_DATA11_MARK,
 	VI4_DATA12_MARK, VI4_DATA13_MARK,
 	VI4_DATA14_MARK, VI4_DATA15_MARK,
+	VI4_DATA16_MARK, VI4_DATA17_MARK,
+	VI4_DATA18_MARK, VI4_DATA19_MARK,
+	VI4_DATA20_MARK, VI4_DATA21_MARK,
+	VI4_DATA22_MARK, VI4_DATA23_MARK,
 };
 static const unsigned int vin4_sync_pins[] = {
 	/* HSYNC#, VSYNC# */
 };
 /* - VIN5 ------------------------------------------------------------------- */
-static const union vin_data16 vin5_data_pins = {
+static const unsigned int vin5_data_pins[] = {
-	.data16 = {
+	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
-		RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
-		RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
-		RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
-		RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
-		RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
-		RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
-		RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
-		RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
-	},
-};
-static const union vin_data16 vin5_data_mux = {
-	.data16 = {
-		VI5_DATA0_MARK, VI5_DATA1_MARK,
-		VI5_DATA2_MARK, VI5_DATA3_MARK,
-		VI5_DATA4_MARK, VI5_DATA5_MARK,
-		VI5_DATA6_MARK, VI5_DATA7_MARK,
-		VI5_DATA8_MARK,  VI5_DATA9_MARK,
-		VI5_DATA10_MARK, VI5_DATA11_MARK,
-		VI5_DATA12_MARK, VI5_DATA13_MARK,
-		VI5_DATA14_MARK, VI5_DATA15_MARK,
-	},
-};
-static const unsigned int vin5_high8_pins[] = {
 	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
 	RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
-	RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 5),
+	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
-	RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 7),
+	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
 };
-static const unsigned int vin5_high8_mux[] = {
+static const unsigned int vin5_data_mux[] = {
+	VI5_DATA0_MARK, VI5_DATA1_MARK,
+	VI5_DATA2_MARK, VI5_DATA3_MARK,
+	VI5_DATA4_MARK, VI5_DATA5_MARK,
+	VI5_DATA6_MARK, VI5_DATA7_MARK,
 	VI5_DATA8_MARK,  VI5_DATA9_MARK,
 	VI5_DATA10_MARK, VI5_DATA11_MARK,
 	VI5_DATA12_MARK, VI5_DATA13_MARK,
 		SH_PFC_PIN_GROUP(pwm6_a),
 		SH_PFC_PIN_GROUP(pwm6_b),
 		SH_PFC_PIN_GROUP(qspi0_ctrl),
-		SH_PFC_PIN_GROUP(qspi0_data2),
+		BUS_DATA_PIN_GROUP(qspi0_data, 2),
-		SH_PFC_PIN_GROUP(qspi0_data4),
+		BUS_DATA_PIN_GROUP(qspi0_data, 4),
 		SH_PFC_PIN_GROUP(qspi1_ctrl),
-		SH_PFC_PIN_GROUP(qspi1_data2),
+		BUS_DATA_PIN_GROUP(qspi1_data, 2),
-		SH_PFC_PIN_GROUP(qspi1_data4),
+		BUS_DATA_PIN_GROUP(qspi1_data, 4),
 		SH_PFC_PIN_GROUP(scif0_data),
 		SH_PFC_PIN_GROUP(scif0_clk),
 		SH_PFC_PIN_GROUP(scif0_ctrl),
 		SH_PFC_PIN_GROUP(scif5_clk_b),
 		SH_PFC_PIN_GROUP(scif_clk_a),
 		SH_PFC_PIN_GROUP(scif_clk_b),
-		SH_PFC_PIN_GROUP(sdhi0_data1),
+		BUS_DATA_PIN_GROUP(sdhi0_data, 1),
-		SH_PFC_PIN_GROUP(sdhi0_data4),
+		BUS_DATA_PIN_GROUP(sdhi0_data, 4),
 		SH_PFC_PIN_GROUP(sdhi0_ctrl),
 		SH_PFC_PIN_GROUP(sdhi0_cd),
 		SH_PFC_PIN_GROUP(sdhi0_wp),
-		SH_PFC_PIN_GROUP(sdhi1_data1),
+		BUS_DATA_PIN_GROUP(sdhi1_data, 1),
-		SH_PFC_PIN_GROUP(sdhi1_data4),
+		BUS_DATA_PIN_GROUP(sdhi1_data, 4),
 		SH_PFC_PIN_GROUP(sdhi1_ctrl),
 		SH_PFC_PIN_GROUP(sdhi1_cd),
 		SH_PFC_PIN_GROUP(sdhi1_wp),
-		SH_PFC_PIN_GROUP(sdhi2_data1),
+		BUS_DATA_PIN_GROUP(sdhi2_data, 1),
-		SH_PFC_PIN_GROUP(sdhi2_data4),
+		BUS_DATA_PIN_GROUP(sdhi2_data, 4),
-		SH_PFC_PIN_GROUP(sdhi2_data8),
+		BUS_DATA_PIN_GROUP(sdhi2_data, 8),
 		SH_PFC_PIN_GROUP(sdhi2_ctrl),
 		SH_PFC_PIN_GROUP(sdhi2_cd_a),
 		SH_PFC_PIN_GROUP(sdhi2_wp_a),
 		SH_PFC_PIN_GROUP(sdhi2_cd_b),
 		SH_PFC_PIN_GROUP(sdhi2_wp_b),
 		SH_PFC_PIN_GROUP(sdhi2_ds),
-		SH_PFC_PIN_GROUP(sdhi3_data1),
+		BUS_DATA_PIN_GROUP(sdhi3_data, 1),
-		SH_PFC_PIN_GROUP(sdhi3_data4),
+		BUS_DATA_PIN_GROUP(sdhi3_data, 4),
-		SH_PFC_PIN_GROUP(sdhi3_data8),
+		BUS_DATA_PIN_GROUP(sdhi3_data, 8),
 		SH_PFC_PIN_GROUP(sdhi3_ctrl),
 		SH_PFC_PIN_GROUP(sdhi3_cd),
 		SH_PFC_PIN_GROUP(sdhi3_wp),
 		SH_PFC_PIN_GROUP(usb0),
 		SH_PFC_PIN_GROUP(usb1),
 		SH_PFC_PIN_GROUP(usb30),
-		VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
+		BUS_DATA_PIN_GROUP(vin4_data, 8, _a),
-		VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
+		BUS_DATA_PIN_GROUP(vin4_data, 10, _a),
-		VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
+		BUS_DATA_PIN_GROUP(vin4_data, 12, _a),
-		VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
+		BUS_DATA_PIN_GROUP(vin4_data, 16, _a),
 		SH_PFC_PIN_GROUP(vin4_data18_a),
-		VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
+		BUS_DATA_PIN_GROUP(vin4_data, 20, _a),
-		VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
+		BUS_DATA_PIN_GROUP(vin4_data, 24, _a),
-		VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
+		BUS_DATA_PIN_GROUP(vin4_data, 8, _b),
-		VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
+		BUS_DATA_PIN_GROUP(vin4_data, 10, _b),
-		VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
+		BUS_DATA_PIN_GROUP(vin4_data, 12, _b),
-		VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
+		BUS_DATA_PIN_GROUP(vin4_data, 16, _b),
 		SH_PFC_PIN_GROUP(vin4_data18_b),
-		VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
+		BUS_DATA_PIN_GROUP(vin4_data, 20, _b),
-		VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
+		BUS_DATA_PIN_GROUP(vin4_data, 24, _b),
-		SH_PFC_PIN_GROUP(vin4_g8),
+		SH_PFC_PIN_GROUP_SUBSET(vin4_g8, vin4_data_a, 8, 8),
 		SH_PFC_PIN_GROUP(vin4_sync),
 		SH_PFC_PIN_GROUP(vin4_field),
 		SH_PFC_PIN_GROUP(vin4_clkenb),
 		SH_PFC_PIN_GROUP(vin4_clk),
-		VIN_DATA_PIN_GROUP(vin5_data, 8),
+		BUS_DATA_PIN_GROUP(vin5_data, 8),
-		VIN_DATA_PIN_GROUP(vin5_data, 10),
+		BUS_DATA_PIN_GROUP(vin5_data, 10),
-		VIN_DATA_PIN_GROUP(vin5_data, 12),
+		BUS_DATA_PIN_GROUP(vin5_data, 12),
-		VIN_DATA_PIN_GROUP(vin5_data, 16),
+		BUS_DATA_PIN_GROUP(vin5_data, 16),
-		SH_PFC_PIN_GROUP(vin5_high8),
+		SH_PFC_PIN_GROUP_SUBSET(vin5_high8, vin5_data, 8, 8),
 		SH_PFC_PIN_GROUP(vin5_sync),
 		SH_PFC_PIN_GROUP(vin5_field),
 		SH_PFC_PIN_GROUP(vin5_clkenb),
 	{ /* sentinel */ },
 };
-static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc,
+static int r8a7796_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
-				  unsigned int pin, u32 *pocctrl)
 {
 	int bit = -EINVAL;
 	{ /* sentinel */ },
 };
-static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = {
+static const struct sh_pfc_soc_operations r8a7796_pfc_ops = {
 	.pin_to_pocctrl = r8a7796_pin_to_pocctrl,
 	.get_bias = rcar_pinmux_get_bias,
 	.set_bias = rcar_pinmux_set_bias,
 #ifdef CONFIG_PINCTRL_PFC_R8A774A1
 const struct sh_pfc_soc_info r8a774a1_pinmux_info = {
 	.name = "r8a774a1_pfc",
-	.ops = &r8a7796_pinmux_ops,
+	.ops = &r8a7796_pfc_ops,
 	.unlock_reg = 0xe6060000, /* PMMR */
 	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
 #ifdef CONFIG_PINCTRL_PFC_R8A77960
 const struct sh_pfc_soc_info r8a77960_pinmux_info = {
 	.name = "r8a77960_pfc",
-	.ops = &r8a7796_pinmux_ops,
+	.ops = &r8a7796_pfc_ops,
 	.unlock_reg = 0xe6060000, /* PMMR */
 	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
 #ifdef CONFIG_PINCTRL_PFC_R8A77961
 const struct sh_pfc_soc_info r8a77961_pinmux_info = {
 	.name = "r8a77961_pfc",
-	.ops = &r8a7796_pinmux_ops,
+	.ops = &r8a7796_pfc_ops,
 	.unlock_reg = 0xe6060000, /* PMMR */
 	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },

drivers/pinctrl/renesas/pfc-r8a77965.c+110−223

 static const unsigned int qspi0_ctrl_mux[] = {
 	QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
 };
-static const unsigned int qspi0_data2_pins[] = {
+static const unsigned int qspi0_data_pins[] = {
-	/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
-	PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
-};
-static const unsigned int qspi0_data2_mux[] = {
-	QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
-};
-static const unsigned int qspi0_data4_pins[] = {
 	/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
 	PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
 	/* QSPI0_IO2, QSPI0_IO3 */
 	PIN_QSPI0_IO2, PIN_QSPI0_IO3,
 };
-static const unsigned int qspi0_data4_mux[] = {
+static const unsigned int qspi0_data_mux[] = {
 	QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
 	QSPI0_IO2_MARK, QSPI0_IO3_MARK,
 };
 static const unsigned int qspi1_ctrl_mux[] = {
 	QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
 };
-static const unsigned int qspi1_data2_pins[] = {
+static const unsigned int qspi1_data_pins[] = {
-	/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
-	PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
-};
-static const unsigned int qspi1_data2_mux[] = {
-	QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
-};
-static const unsigned int qspi1_data4_pins[] = {
 	/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
 	PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
 	/* QSPI1_IO2, QSPI1_IO3 */
 	PIN_QSPI1_IO2, PIN_QSPI1_IO3,
 };
-static const unsigned int qspi1_data4_mux[] = {
+static const unsigned int qspi1_data_mux[] = {
 	QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
 	QSPI1_IO2_MARK, QSPI1_IO3_MARK,
 };
 };
 /* - SDHI0 ------------------------------------------------------------------ */
-static const unsigned int sdhi0_data1_pins[] = {
+static const unsigned int sdhi0_data_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(3, 2),
-};
-static const unsigned int sdhi0_data1_mux[] = {
-	SD0_DAT0_MARK,
-};
-static const unsigned int sdhi0_data4_pins[] = {
 	/* D[0:3] */
 	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
 	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
 };
-static const unsigned int sdhi0_data4_mux[] = {
+static const unsigned int sdhi0_data_mux[] = {
 	SD0_DAT0_MARK, SD0_DAT1_MARK,
 	SD0_DAT2_MARK, SD0_DAT3_MARK,
 };
 };
 /* - SDHI1 ------------------------------------------------------------------ */
-static const unsigned int sdhi1_data1_pins[] = {
+static const unsigned int sdhi1_data_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(3, 8),
-};
-static const unsigned int sdhi1_data1_mux[] = {
-	SD1_DAT0_MARK,
-};
-static const unsigned int sdhi1_data4_pins[] = {
 	/* D[0:3] */
 	RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
 	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
 };
-static const unsigned int sdhi1_data4_mux[] = {
+static const unsigned int sdhi1_data_mux[] = {
 	SD1_DAT0_MARK, SD1_DAT1_MARK,
 	SD1_DAT2_MARK, SD1_DAT3_MARK,
 };
 };
 /* - SDHI2 ------------------------------------------------------------------ */
-static const unsigned int sdhi2_data1_pins[] = {
+static const unsigned int sdhi2_data_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(4, 2),
-};
-static const unsigned int sdhi2_data1_mux[] = {
-	SD2_DAT0_MARK,
-};
-static const unsigned int sdhi2_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
-	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
-};
-static const unsigned int sdhi2_data4_mux[] = {
-	SD2_DAT0_MARK, SD2_DAT1_MARK,
-	SD2_DAT2_MARK, SD2_DAT3_MARK,
-};
-static const unsigned int sdhi2_data8_pins[] = {
 	/* D[0:7] */
 	RCAR_GP_PIN(4, 2),  RCAR_GP_PIN(4, 3),
 	RCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 5),
 	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
 };
-static const unsigned int sdhi2_data8_mux[] = {
+static const unsigned int sdhi2_data_mux[] = {
 	SD2_DAT0_MARK, SD2_DAT1_MARK,
 	SD2_DAT2_MARK, SD2_DAT3_MARK,
 	SD2_DAT4_MARK, SD2_DAT5_MARK,
 };
 /* - SDHI3 ------------------------------------------------------------------ */
-static const unsigned int sdhi3_data1_pins[] = {
+static const unsigned int sdhi3_data_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(4, 9),
-};
-static const unsigned int sdhi3_data1_mux[] = {
-	SD3_DAT0_MARK,
-};
-static const unsigned int sdhi3_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
-	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
-};
-static const unsigned int sdhi3_data4_mux[] = {
-	SD3_DAT0_MARK, SD3_DAT1_MARK,
-	SD3_DAT2_MARK, SD3_DAT3_MARK,
-};
-static const unsigned int sdhi3_data8_pins[] = {
 	/* D[0:7] */
 	RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
 	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
 	RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
 };
-static const unsigned int sdhi3_data8_mux[] = {
+static const unsigned int sdhi3_data_mux[] = {
 	SD3_DAT0_MARK, SD3_DAT1_MARK,
 	SD3_DAT2_MARK, SD3_DAT3_MARK,
 	SD3_DAT4_MARK, SD3_DAT5_MARK,
 	VI4_DATA22_MARK, VI4_DATA23_MARK,
 };
-static const union vin_data vin4_data_a_pins = {
+static const unsigned int vin4_data_a_pins[] = {
-	.data24 = {
+	RCAR_GP_PIN(0, 8),  RCAR_GP_PIN(0, 9),
-		RCAR_GP_PIN(0, 8),  RCAR_GP_PIN(0, 9),
+	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
-		RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
-		RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
+	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
-		RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+	RCAR_GP_PIN(1, 0),  RCAR_GP_PIN(1, 1),
-		RCAR_GP_PIN(1, 0),  RCAR_GP_PIN(1, 1),
+	RCAR_GP_PIN(1, 2),  RCAR_GP_PIN(1, 3),
-		RCAR_GP_PIN(1, 2),  RCAR_GP_PIN(1, 3),
+	RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 5),
-		RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 5),
+	RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 7),
-		RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 7),
+	RCAR_GP_PIN(0, 0),  RCAR_GP_PIN(0, 1),
-		RCAR_GP_PIN(0, 0),  RCAR_GP_PIN(0, 1),
+	RCAR_GP_PIN(0, 2),  RCAR_GP_PIN(0, 3),
-		RCAR_GP_PIN(0, 2),  RCAR_GP_PIN(0, 3),
+	RCAR_GP_PIN(0, 4),  RCAR_GP_PIN(0, 5),
-		RCAR_GP_PIN(0, 4),  RCAR_GP_PIN(0, 5),
+	RCAR_GP_PIN(0, 6),  RCAR_GP_PIN(0, 7),
-		RCAR_GP_PIN(0, 6),  RCAR_GP_PIN(0, 7),
-	},
 };
-static const union vin_data vin4_data_a_mux = {
+static const unsigned int vin4_data_a_mux[] = {
-	.data24 = {
+	VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
-		VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
+	VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
-		VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
+	VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
-		VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
+	VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
-		VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
+	VI4_DATA8_MARK,   VI4_DATA9_MARK,
-		VI4_DATA8_MARK,   VI4_DATA9_MARK,
+	VI4_DATA10_MARK,  VI4_DATA11_MARK,
-		VI4_DATA10_MARK,  VI4_DATA11_MARK,
+	VI4_DATA12_MARK,  VI4_DATA13_MARK,
-		VI4_DATA12_MARK,  VI4_DATA13_MARK,
+	VI4_DATA14_MARK,  VI4_DATA15_MARK,
-		VI4_DATA14_MARK,  VI4_DATA15_MARK,
+	VI4_DATA16_MARK,  VI4_DATA17_MARK,
-		VI4_DATA16_MARK,  VI4_DATA17_MARK,
+	VI4_DATA18_MARK,  VI4_DATA19_MARK,
-		VI4_DATA18_MARK,  VI4_DATA19_MARK,
+	VI4_DATA20_MARK,  VI4_DATA21_MARK,
-		VI4_DATA20_MARK,  VI4_DATA21_MARK,
+	VI4_DATA22_MARK,  VI4_DATA23_MARK,
-		VI4_DATA22_MARK,  VI4_DATA23_MARK,
-	},
 };
 static const unsigned int vin4_data18_b_pins[] = {
 	VI4_DATA22_MARK, VI4_DATA23_MARK,
 };
-static const union vin_data vin4_data_b_pins = {
+static const unsigned int vin4_data_b_pins[] = {
-	.data24 = {
+	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
-		RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
+	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
-		RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
+	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
-		RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
+	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
-		RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
+	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
-		RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
+	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
-		RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
-		RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
-		RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
-		RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
-		RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
-		RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
-		RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
-	},
-};
-static const union vin_data vin4_data_b_mux = {
-	.data24 = {
-		VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
-		VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
-		VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
-		VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
-		VI4_DATA8_MARK,   VI4_DATA9_MARK,
-		VI4_DATA10_MARK,  VI4_DATA11_MARK,
-		VI4_DATA12_MARK,  VI4_DATA13_MARK,
-		VI4_DATA14_MARK,  VI4_DATA15_MARK,
-		VI4_DATA16_MARK,  VI4_DATA17_MARK,
-		VI4_DATA18_MARK,  VI4_DATA19_MARK,
-		VI4_DATA20_MARK,  VI4_DATA21_MARK,
-		VI4_DATA22_MARK,  VI4_DATA23_MARK,
-	},
-};
-static const unsigned int vin4_g8_pins[] = {
-	RCAR_GP_PIN(1, 0),  RCAR_GP_PIN(1, 1),
-	RCAR_GP_PIN(1, 2),  RCAR_GP_PIN(1, 3),
-	RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 5),
-	RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 7),
 };
-static const unsigned int vin4_g8_mux[] = {
+static const unsigned int vin4_data_b_mux[] = {
-	VI4_DATA8_MARK,  VI4_DATA9_MARK,
+	VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
-	VI4_DATA10_MARK, VI4_DATA11_MARK,
+	VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
-	VI4_DATA12_MARK, VI4_DATA13_MARK,
+	VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
-	VI4_DATA14_MARK, VI4_DATA15_MARK,
+	VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
+	VI4_DATA8_MARK,   VI4_DATA9_MARK,
+	VI4_DATA10_MARK,  VI4_DATA11_MARK,
+	VI4_DATA12_MARK,  VI4_DATA13_MARK,
+	VI4_DATA14_MARK,  VI4_DATA15_MARK,
+	VI4_DATA16_MARK,  VI4_DATA17_MARK,
+	VI4_DATA18_MARK,  VI4_DATA19_MARK,
+	VI4_DATA20_MARK,  VI4_DATA21_MARK,
+	VI4_DATA22_MARK,  VI4_DATA23_MARK,
 };
 static const unsigned int vin4_sync_pins[] = {
 };
 /* - VIN5 ------------------------------------------------------------------- */
-static const union vin_data16 vin5_data_pins = {
+static const unsigned int vin5_data_pins[] = {
-	.data16 = {
+	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
-		RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
-		RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
-		RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
-		RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
-		RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
-		RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
-		RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 5),
-		RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 7),
-	},
-};
-static const union vin_data16 vin5_data_mux = {
-	.data16 = {
-		VI5_DATA0_MARK, VI5_DATA1_MARK,
-		VI5_DATA2_MARK, VI5_DATA3_MARK,
-		VI5_DATA4_MARK, VI5_DATA5_MARK,
-		VI5_DATA6_MARK, VI5_DATA7_MARK,
-		VI5_DATA8_MARK,  VI5_DATA9_MARK,
-		VI5_DATA10_MARK, VI5_DATA11_MARK,
-		VI5_DATA12_MARK, VI5_DATA13_MARK,
-		VI5_DATA14_MARK, VI5_DATA15_MARK,
-	},
-};
-static const unsigned int vin5_high8_pins[] = {
 	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
 	RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
 	RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 5),
 	RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 7),
 };
-static const unsigned int vin5_high8_mux[] = {
+static const unsigned int vin5_data_mux[] = {
+	VI5_DATA0_MARK, VI5_DATA1_MARK,
+	VI5_DATA2_MARK, VI5_DATA3_MARK,
+	VI5_DATA4_MARK, VI5_DATA5_MARK,
+	VI5_DATA6_MARK, VI5_DATA7_MARK,
 	VI5_DATA8_MARK,  VI5_DATA9_MARK,
 	VI5_DATA10_MARK, VI5_DATA11_MARK,
 	VI5_DATA12_MARK, VI5_DATA13_MARK,
 		SH_PFC_PIN_GROUP(pwm6_a),
 		SH_PFC_PIN_GROUP(pwm6_b),
 		SH_PFC_PIN_GROUP(qspi0_ctrl),
-		SH_PFC_PIN_GROUP(qspi0_data2),
+		BUS_DATA_PIN_GROUP(qspi0_data, 2),
-		SH_PFC_PIN_GROUP(qspi0_data4),
+		BUS_DATA_PIN_GROUP(qspi0_data, 4),
 		SH_PFC_PIN_GROUP(qspi1_ctrl),
-		SH_PFC_PIN_GROUP(qspi1_data2),
+		BUS_DATA_PIN_GROUP(qspi1_data, 2),
-		SH_PFC_PIN_GROUP(qspi1_data4),
+		BUS_DATA_PIN_GROUP(qspi1_data, 4),
 		SH_PFC_PIN_GROUP(sata0_devslp_a),
 		SH_PFC_PIN_GROUP(sata0_devslp_b),
 		SH_PFC_PIN_GROUP(scif0_data),
 		SH_PFC_PIN_GROUP(scif5_clk_b),
 		SH_PFC_PIN_GROUP(scif_clk_a),
 		SH_PFC_PIN_GROUP(scif_clk_b),
-		SH_PFC_PIN_GROUP(sdhi0_data1),
+		BUS_DATA_PIN_GROUP(sdhi0_data, 1),
-		SH_PFC_PIN_GROUP(sdhi0_data4),
+		BUS_DATA_PIN_GROUP(sdhi0_data, 4),
 		SH_PFC_PIN_GROUP(sdhi0_ctrl),
 		SH_PFC_PIN_GROUP(sdhi0_cd),
 		SH_PFC_PIN_GROUP(sdhi0_wp),
-		SH_PFC_PIN_GROUP(sdhi1_data1),
+		BUS_DATA_PIN_GROUP(sdhi1_data, 1),
-		SH_PFC_PIN_GROUP(sdhi1_data4),
+		BUS_DATA_PIN_GROUP(sdhi1_data, 4),
 		SH_PFC_PIN_GROUP(sdhi1_ctrl),
 		SH_PFC_PIN_GROUP(sdhi1_cd),
 		SH_PFC_PIN_GROUP(sdhi1_wp),
-		SH_PFC_PIN_GROUP(sdhi2_data1),
+		BUS_DATA_PIN_GROUP(sdhi2_data, 1),
-		SH_PFC_PIN_GROUP(sdhi2_data4),
+		BUS_DATA_PIN_GROUP(sdhi2_data, 4),
-		SH_PFC_PIN_GROUP(sdhi2_data8),
+		BUS_DATA_PIN_GROUP(sdhi2_data, 8),
 		SH_PFC_PIN_GROUP(sdhi2_ctrl),
 		SH_PFC_PIN_GROUP(sdhi2_cd_a),
 		SH_PFC_PIN_GROUP(sdhi2_wp_a),
 		SH_PFC_PIN_GROUP(sdhi2_cd_b),
 		SH_PFC_PIN_GROUP(sdhi2_wp_b),
 		SH_PFC_PIN_GROUP(sdhi2_ds),
-		SH_PFC_PIN_GROUP(sdhi3_data1),
+		BUS_DATA_PIN_GROUP(sdhi3_data, 1),
-		SH_PFC_PIN_GROUP(sdhi3_data4),
+		BUS_DATA_PIN_GROUP(sdhi3_data, 4),
-		SH_PFC_PIN_GROUP(sdhi3_data8),
+		BUS_DATA_PIN_GROUP(sdhi3_data, 8),
 		SH_PFC_PIN_GROUP(sdhi3_ctrl),
 		SH_PFC_PIN_GROUP(sdhi3_cd),
 		SH_PFC_PIN_GROUP(sdhi3_wp),
 		SH_PFC_PIN_GROUP(usb0),
 		SH_PFC_PIN_GROUP(usb1),
 		SH_PFC_PIN_GROUP(usb30),
-		VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
+		BUS_DATA_PIN_GROUP(vin4_data, 8, _a),
-		VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
+		BUS_DATA_PIN_GROUP(vin4_data, 10, _a),
-		VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
+		BUS_DATA_PIN_GROUP(vin4_data, 12, _a),
-		VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
+		BUS_DATA_PIN_GROUP(vin4_data, 16, _a),
 		SH_PFC_PIN_GROUP(vin4_data18_a),
-		VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
+		BUS_DATA_PIN_GROUP(vin4_data, 20, _a),
-		VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
+		BUS_DATA_PIN_GROUP(vin4_data, 24, _a),
-		VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
+		BUS_DATA_PIN_GROUP(vin4_data, 8, _b),
-		VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
+		BUS_DATA_PIN_GROUP(vin4_data, 10, _b),
-		VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
+		BUS_DATA_PIN_GROUP(vin4_data, 12, _b),
-		VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
+		BUS_DATA_PIN_GROUP(vin4_data, 16, _b),
 		SH_PFC_PIN_GROUP(vin4_data18_b),
-		VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
+		BUS_DATA_PIN_GROUP(vin4_data, 20, _b),
-		VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
+		BUS_DATA_PIN_GROUP(vin4_data, 24, _b),
-		SH_PFC_PIN_GROUP(vin4_g8),
+		SH_PFC_PIN_GROUP_SUBSET(vin4_g8, vin4_data_a, 8, 8),
 		SH_PFC_PIN_GROUP(vin4_sync),
 		SH_PFC_PIN_GROUP(vin4_field),
 		SH_PFC_PIN_GROUP(vin4_clkenb),
 		SH_PFC_PIN_GROUP(vin4_clk),
-		VIN_DATA_PIN_GROUP(vin5_data, 8),
+		BUS_DATA_PIN_GROUP(vin5_data, 8),
-		VIN_DATA_PIN_GROUP(vin5_data, 10),
+		BUS_DATA_PIN_GROUP(vin5_data, 10),
-		VIN_DATA_PIN_GROUP(vin5_data, 12),
+		BUS_DATA_PIN_GROUP(vin5_data, 12),
-		VIN_DATA_PIN_GROUP(vin5_data, 16),
+		BUS_DATA_PIN_GROUP(vin5_data, 16),
-		SH_PFC_PIN_GROUP(vin5_high8),
+		SH_PFC_PIN_GROUP_SUBSET(vin5_high8, vin5_data, 8, 8),
 		SH_PFC_PIN_GROUP(vin5_sync),
 		SH_PFC_PIN_GROUP(vin5_field),
 		SH_PFC_PIN_GROUP(vin5_clkenb),
 	{ /* sentinel */ },
 };
-static int r8a77965_pin_to_pocctrl(struct sh_pfc *pfc,
+static int r8a77965_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
-				   unsigned int pin, u32 *pocctrl)
 {
 	int bit = -EINVAL;
 	{ /* sentinel */ },
 };
-static const struct sh_pfc_soc_operations r8a77965_pinmux_ops = {
+static const struct sh_pfc_soc_operations r8a77965_pfc_ops = {
 	.pin_to_pocctrl = r8a77965_pin_to_pocctrl,
 	.get_bias = rcar_pinmux_get_bias,
 	.set_bias = rcar_pinmux_set_bias,
 #ifdef CONFIG_PINCTRL_PFC_R8A774B1
 const struct sh_pfc_soc_info r8a774b1_pinmux_info = {
 	.name = "r8a774b1_pfc",
-	.ops = &r8a77965_pinmux_ops,
+	.ops = &r8a77965_pfc_ops,
 	.unlock_reg = 0xe6060000, /* PMMR */
 	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
 #ifdef CONFIG_PINCTRL_PFC_R8A77965
 const struct sh_pfc_soc_info r8a77965_pinmux_info = {
 	.name = "r8a77965_pfc",
-	.ops = &r8a77965_pinmux_ops,
+	.ops = &r8a77965_pfc_ops,
 	.unlock_reg = 0xe6060000, /* PMMR */
 	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },

drivers/pinctrl/renesas/pfc-r8a77970.c+51−114

 };
 /* - MMC -------------------------------------------------------------------- */
-static const unsigned int mmc_data1_pins[] = {
+static const unsigned int mmc_data_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(3, 6),
-};
-static const unsigned int mmc_data1_mux[] = {
-	MMC_D0_MARK,
-};
-static const unsigned int mmc_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
-	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
-};
-static const unsigned int mmc_data4_mux[] = {
-	MMC_D0_MARK, MMC_D1_MARK,
-	MMC_D2_MARK, MMC_D3_MARK,
-};
-static const unsigned int mmc_data8_pins[] = {
 	/* D[0:7] */
 	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
 	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
 	RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
 	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
 };
-static const unsigned int mmc_data8_mux[] = {
+static const unsigned int mmc_data_mux[] = {
 	MMC_D0_MARK, MMC_D1_MARK,
 	MMC_D2_MARK, MMC_D3_MARK,
 	MMC_D4_MARK, MMC_D5_MARK,
 static const unsigned int qspi0_ctrl_mux[] = {
 	QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
 };
-static const unsigned int qspi0_data2_pins[] = {
-	/* MOSI_IO0, MISO_IO1 */
-	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
-};
-static const unsigned int qspi0_data2_mux[] = {
-	QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
-};
-static const unsigned int qspi0_data4_pins[] = {
-	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
-	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
-	RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),
-};
-static const unsigned int qspi0_data4_mux[] = {
-	QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
-	QSPI0_IO2_MARK, QSPI0_IO3_MARK
-};
 /* - QSPI1 ------------------------------------------------------------------ */
 static const unsigned int qspi1_ctrl_pins[] = {
 static const unsigned int qspi1_ctrl_mux[] = {
 	QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
 };
-static const unsigned int qspi1_data2_pins[] = {
-	/* MOSI_IO0, MISO_IO1 */
-	RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
-};
-static const unsigned int qspi1_data2_mux[] = {
-	QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
-};
-static const unsigned int qspi1_data4_pins[] = {
-	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
-	RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
-	RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
-};
-static const unsigned int qspi1_data4_mux[] = {
-	QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
-	QSPI1_IO2_MARK, QSPI1_IO3_MARK
-};
 /* - RPC -------------------------------------------------------------------- */
-static const unsigned int rpc_clk1_pins[] = {
+static const unsigned int rpc_clk_pins[] = {
 	/* Octal-SPI flash: C/SCLK */
-	RCAR_GP_PIN(5, 0),
-};
-static const unsigned int rpc_clk1_mux[] = {
-	QSPI0_SPCLK_MARK,
-};
-static const unsigned int rpc_clk2_pins[] = {
 	/* HyperFlash: CK, CK# */
 	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 6),
 };
-static const unsigned int rpc_clk2_mux[] = {
+static const unsigned int rpc_clk_mux[] = {
 	QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK,
 };
 static const unsigned int rpc_ctrl_pins[] = {
 };
 /* - VIN0 ------------------------------------------------------------------- */
-static const union vin_data12 vin0_data_pins = {
+static const unsigned int vin0_data_pins[] = {
-	.data12 = {
+	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
-		RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
+	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
-		RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
+	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
-		RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
+	RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
-		RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
+	RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
-		RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
+	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
-		RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
+};
-	},
+static const unsigned int vin0_data_mux[] = {
-};
+	VI0_DATA0_MARK, VI0_DATA1_MARK,
-static const union vin_data12 vin0_data_mux = {
+	VI0_DATA2_MARK, VI0_DATA3_MARK,
-	.data12 = {
+	VI0_DATA4_MARK, VI0_DATA5_MARK,
-		VI0_DATA0_MARK, VI0_DATA1_MARK,
+	VI0_DATA6_MARK, VI0_DATA7_MARK,
-		VI0_DATA2_MARK, VI0_DATA3_MARK,
+	VI0_DATA8_MARK,  VI0_DATA9_MARK,
-		VI0_DATA4_MARK, VI0_DATA5_MARK,
+	VI0_DATA10_MARK, VI0_DATA11_MARK,
-		VI0_DATA6_MARK, VI0_DATA7_MARK,
-		VI0_DATA8_MARK,  VI0_DATA9_MARK,
-		VI0_DATA10_MARK, VI0_DATA11_MARK,
-	},
 };
 static const unsigned int vin0_sync_pins[] = {
 	/* HSYNC#, VSYNC# */
 };
 /* - VIN1 ------------------------------------------------------------------- */
-static const union vin_data12 vin1_data_pins = {
+static const unsigned int vin1_data_pins[] = {
-	.data12 = {
+	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
-		RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
+	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
-		RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
+	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
-		RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
+	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
-		RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
+	RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
-		RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
+	RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
-		RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
-	},
 };
-static const union vin_data12 vin1_data_mux = {
+static const unsigned int vin1_data_mux[] = {
-	.data12 = {
+	VI1_DATA0_MARK, VI1_DATA1_MARK,
-		VI1_DATA0_MARK, VI1_DATA1_MARK,
+	VI1_DATA2_MARK, VI1_DATA3_MARK,
-		VI1_DATA2_MARK, VI1_DATA3_MARK,
+	VI1_DATA4_MARK, VI1_DATA5_MARK,
-		VI1_DATA4_MARK, VI1_DATA5_MARK,
+	VI1_DATA6_MARK, VI1_DATA7_MARK,
-		VI1_DATA6_MARK, VI1_DATA7_MARK,
+	VI1_DATA8_MARK,  VI1_DATA9_MARK,
-		VI1_DATA8_MARK,  VI1_DATA9_MARK,
+	VI1_DATA10_MARK, VI1_DATA11_MARK,
-		VI1_DATA10_MARK, VI1_DATA11_MARK,
-	},
 };
 static const unsigned int vin1_sync_pins[] = {
 	/* HSYNC#, VSYNC# */
 	SH_PFC_PIN_GROUP(intc_ex_irq3),
 	SH_PFC_PIN_GROUP(intc_ex_irq4),
 	SH_PFC_PIN_GROUP(intc_ex_irq5),
-	SH_PFC_PIN_GROUP(mmc_data1),
+	BUS_DATA_PIN_GROUP(mmc_data, 1),
-	SH_PFC_PIN_GROUP(mmc_data4),
+	BUS_DATA_PIN_GROUP(mmc_data, 4),
-	SH_PFC_PIN_GROUP(mmc_data8),
+	BUS_DATA_PIN_GROUP(mmc_data, 8),
 	SH_PFC_PIN_GROUP(mmc_ctrl),
 	SH_PFC_PIN_GROUP(msiof0_clk),
 	SH_PFC_PIN_GROUP(msiof0_sync),
 	SH_PFC_PIN_GROUP(pwm4_a),
 	SH_PFC_PIN_GROUP(pwm4_b),
 	SH_PFC_PIN_GROUP(qspi0_ctrl),
-	SH_PFC_PIN_GROUP(qspi0_data2),
+	SH_PFC_PIN_GROUP_SUBSET(qspi0_data2, rpc_data, 0, 2),
-	SH_PFC_PIN_GROUP(qspi0_data4),
+	SH_PFC_PIN_GROUP_SUBSET(qspi0_data4, rpc_data, 0, 4),
 	SH_PFC_PIN_GROUP(qspi1_ctrl),
-	SH_PFC_PIN_GROUP(qspi1_data2),
+	SH_PFC_PIN_GROUP_SUBSET(qspi1_data2, rpc_data, 4, 2),
-	SH_PFC_PIN_GROUP(qspi1_data4),
+	SH_PFC_PIN_GROUP_SUBSET(qspi1_data4, rpc_data, 4, 4),
-	SH_PFC_PIN_GROUP(rpc_clk1),
+	BUS_DATA_PIN_GROUP(rpc_clk, 1),
-	SH_PFC_PIN_GROUP(rpc_clk2),
+	BUS_DATA_PIN_GROUP(rpc_clk, 2),
 	SH_PFC_PIN_GROUP(rpc_ctrl),
 	SH_PFC_PIN_GROUP(rpc_data),
 	SH_PFC_PIN_GROUP(rpc_reset),
 	SH_PFC_PIN_GROUP(tmu_tclk1_b),
 	SH_PFC_PIN_GROUP(tmu_tclk2_a),
 	SH_PFC_PIN_GROUP(tmu_tclk2_b),
-	VIN_DATA_PIN_GROUP(vin0_data, 8),
+	BUS_DATA_PIN_GROUP(vin0_data, 8),
-	VIN_DATA_PIN_GROUP(vin0_data, 10),
+	BUS_DATA_PIN_GROUP(vin0_data, 10),
-	VIN_DATA_PIN_GROUP(vin0_data, 12),
+	BUS_DATA_PIN_GROUP(vin0_data, 12),
 	SH_PFC_PIN_GROUP(vin0_sync),
 	SH_PFC_PIN_GROUP(vin0_field),
 	SH_PFC_PIN_GROUP(vin0_clkenb),
 	SH_PFC_PIN_GROUP(vin0_clk),
-	VIN_DATA_PIN_GROUP(vin1_data, 8),
+	BUS_DATA_PIN_GROUP(vin1_data, 8),
-	VIN_DATA_PIN_GROUP(vin1_data, 10),
+	BUS_DATA_PIN_GROUP(vin1_data, 10),
-	VIN_DATA_PIN_GROUP(vin1_data, 12),
+	BUS_DATA_PIN_GROUP(vin1_data, 12),
 	SH_PFC_PIN_GROUP(vin1_sync),
 	SH_PFC_PIN_GROUP(vin1_field),
 	SH_PFC_PIN_GROUP(vin1_clkenb),
 	{ /* sentinel */ },
 };
-static int r8a77970_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
+static int r8a77970_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
-				   u32 *pocctrl)
 {
 	int bit = pin & 0x1f;
 	{ /* sentinel */ }
 };
-static const struct sh_pfc_soc_operations pinmux_ops = {
+static const struct sh_pfc_soc_operations r8a77970_pfc_ops = {
 	.pin_to_pocctrl = r8a77970_pin_to_pocctrl,
 	.get_bias = rcar_pinmux_get_bias,
 	.set_bias = rcar_pinmux_set_bias,
 const struct sh_pfc_soc_info r8a77970_pinmux_info = {
 	.name = "r8a77970_pfc",
-	.ops = &pinmux_ops,
+	.ops = &r8a77970_pfc_ops,
 	.unlock_reg = 0xe6060000, /* PMMR */
 	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },

drivers/pinctrl/renesas/pfc-r8a77980.c+65−128

@@ -1365,30 +1365,14 @@ static const unsigned int intc_ex_irq5_mux[] = { · 1364 unmodified lines
1365	};	1365	};
1366		1366
1367	/* - MMC -------------------------------------------------------------------- */	1367	/* - MMC -------------------------------------------------------------------- */
1368	static const unsigned int mmc_data1_pins[] = {	1368	static const unsigned int mmc_data_pins[] = {
1369	/* MMC_D0 */
1370	RCAR_GP_PIN(3, 8),
1371	};
1372	static const unsigned int mmc_data1_mux[] = {
1373	MMC_D0_MARK,
1374	};
1375	static const unsigned int mmc_data4_pins[] = {
1376	/* MMC_D[0:3] */
1377	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1378	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1379	};
1380	static const unsigned int mmc_data4_mux[] = {
1381	MMC_D0_MARK, MMC_D1_MARK,
1382	MMC_D2_MARK, MMC_D3_MARK,
1383	};
1384	static const unsigned int mmc_data8_pins[] = {
1385	/* MMC_D[0:7] */	1369	/* MMC_D[0:7] */
1386	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),	1370	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1387	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),	1371	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1388	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),	1372	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
1389	RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),	1373	RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
1390	};	1374	};
1391	static const unsigned int mmc_data8_mux[] = {	1375	static const unsigned int mmc_data_mux[] = {
1392	MMC_D0_MARK, MMC_D1_MARK,	1376	MMC_D0_MARK, MMC_D1_MARK,
1393	MMC_D2_MARK, MMC_D3_MARK,	1377	MMC_D2_MARK, MMC_D3_MARK,
1394	MMC_D4_MARK, MMC_D5_MARK,	1378	MMC_D4_MARK, MMC_D5_MARK,
@@ -1687,22 +1671,6 @@ static const unsigned int qspi0_ctrl_pins[] = { · 292 unmodified lines
1687	static const unsigned int qspi0_ctrl_mux[] = {	1671	static const unsigned int qspi0_ctrl_mux[] = {
1688	QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,	1672	QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
1689	};	1673	};
1690	static const unsigned int qspi0_data2_pins[] = {
1691	/* MOSI_IO0, MISO_IO1 */
1692	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1693	};
1694	static const unsigned int qspi0_data2_mux[] = {
1695	QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
1696	};
1697	static const unsigned int qspi0_data4_pins[] = {
1698	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
1699	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1700	RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),
1701	};
1702	static const unsigned int qspi0_data4_mux[] = {
1703	QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
1704	QSPI0_IO2_MARK, QSPI0_IO3_MARK
1705	};
1706		1674
1707	/* - QSPI1 ------------------------------------------------------------------ */	1675	/* - QSPI1 ------------------------------------------------------------------ */
1708	static const unsigned int qspi1_ctrl_pins[] = {	1676	static const unsigned int qspi1_ctrl_pins[] = {
@@ -1712,36 +1680,14 @@ static const unsigned int qspi1_ctrl_pins[] = { · 3 unmodified lines
1712	static const unsigned int qspi1_ctrl_mux[] = {	1680	static const unsigned int qspi1_ctrl_mux[] = {
1713	QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,	1681	QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
1714	};	1682	};