Pull ARM driver updates from Arnd Bergmann: "The drivers branch for 6.1 is a bit larger than for most releases. Most of the changes come from SoC maintainers for the drivers/soc subsystem: - A new driver for error handling on the NVIDIA Tegra 'control backbone' bus. - A new driver for Qualcomm LLCC/DDR bandwidth measurement - New Rockchip rv1126 and rk3588 power domain drivers - DT binding updates for memory controllers, older Rockchip SoCs, various Mediatek devices, Qualcomm SCM firmware - Minor updates to Hisilicon LPC bus, the Allwinner SRAM driver, the Apple rtkit firmware driver, Tegra firmware - Minor updates for SoC drivers (Samsung, Mediatek, Renesas, Tegra, Qualcomm, Broadcom, NXP, ...) There are also some separate subsystem with downstream maintainers that merge updates this way: - Various updates and new drivers in the memory controller subsystem for Mediatek and Broadcom SoCs - Small set of changes in preparation to add support for FF-A v1.1 specification later, in the Arm FF-A firmware subsystem - debugfs support in the PSCI firmware subsystem" * tag 'arm-drivers-6.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (149 commits) ARM: remove check for CONFIG_DEBUG_LL_SER3 firmware/psci: Add debugfs support to ease debugging firmware/psci: Print a warning if PSCI doesn't accept PC mode dt-bindings: memory: snps,dw-umctl2-ddrc: Extend schema with IRQs/resets/clocks props dt-bindings: memory: snps,dw-umctl2-ddrc: Replace opencoded numbers with macros dt-bindings: memory: snps,dw-umctl2-ddrc: Use more descriptive device name dt-bindings: memory: synopsys,ddrc-ecc: Detach Zynq DDRC controller support soc: sunxi: sram: Add support for the D1 system control soc: sunxi: sram: Export the LDO control register soc: sunxi: sram: Save a pointer to the OF match data soc: sunxi: sram: Return void from the release function soc: apple: rtkit: Add apple_rtkit_poll soc: imx: add i.MX93 media blk ctrl driver soc: imx: add i.MX93 SRC power domain driver soc: imx: imx8m-blk-ctrl: Use genpd_xlate_onecell soc: imx: imx8mp-blk-ctrl: handle PCIe PHY resets soc: imx: imx8m-blk-ctrl: add i.MX8MP VPU blk ctrl soc: imx: add i.MX8MP HDMI blk ctrl HDCP/HRV_MWR soc: imx: add icc paths for i.MX8MP hsio/hdmi blk ctrl soc: imx: add icc paths for i.MX8MP media blk ctrl ...
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| @@ -48,12 +48,26 @@ · 47 unmodified lines | ||
| 48 | 48 | #define PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU PSCI_0_2_FN64(7) |
| 49 | 49 | |
| 50 | 50 | #define PSCI_1_0_FN_PSCI_FEATURES PSCI_0_2_FN(10) |
| 51 | +#define PSCI_1_0_FN_CPU_FREEZE PSCI_0_2_FN(11) | |
| 52 | +#define PSCI_1_0_FN_CPU_DEFAULT_SUSPEND PSCI_0_2_FN(12) | |
| 53 | +#define PSCI_1_0_FN_NODE_HW_STATE PSCI_0_2_FN(13) | |
| 51 | 54 | #define PSCI_1_0_FN_SYSTEM_SUSPEND PSCI_0_2_FN(14) |
| 52 | 55 | #define PSCI_1_0_FN_SET_SUSPEND_MODE PSCI_0_2_FN(15) |
| 56 | +#define PSCI_1_0_FN_STAT_RESIDENCY PSCI_0_2_FN(16) | |
| 57 | +#define PSCI_1_0_FN_STAT_COUNT PSCI_0_2_FN(17) | |
| 58 | + | |
| 53 | 59 | #define PSCI_1_1_FN_SYSTEM_RESET2 PSCI_0_2_FN(18) |
| 60 | +#define PSCI_1_1_FN_MEM_PROTECT PSCI_0_2_FN(19) | |
| 61 | +#define PSCI_1_1_FN_MEM_PROTECT_CHECK_RANGE PSCI_0_2_FN(19) | |
| 54 | 62 | |
| 63 | +#define PSCI_1_0_FN64_CPU_DEFAULT_SUSPEND PSCI_0_2_FN64(12) | |
| 64 | +#define PSCI_1_0_FN64_NODE_HW_STATE PSCI_0_2_FN64(13) | |
| 55 | 65 | #define PSCI_1_0_FN64_SYSTEM_SUSPEND PSCI_0_2_FN64(14) |
| 66 | +#define PSCI_1_0_FN64_STAT_RESIDENCY PSCI_0_2_FN64(16) | |
| 67 | +#define PSCI_1_0_FN64_STAT_COUNT PSCI_0_2_FN64(17) | |
| 68 | + | |
| 56 | 69 | #define PSCI_1_1_FN64_SYSTEM_RESET2 PSCI_0_2_FN64(18) |
| 70 | +#define PSCI_1_1_FN64_MEM_PROTECT_CHECK_RANGE PSCI_0_2_FN64(19) | |
| 57 | 71 | |
| 58 | 72 | /* PSCI v0.2 power state encoding for CPU_SUSPEND function */ |
| 59 | 73 | #define PSCI_0_2_POWER_STATE_ID_MASK 0xffff |