lael-labs/linux

Documentation/admin-guide/kernel-parameters.txt+16−0

@@ -866,6 +866,15 @@ · 865 unmodified lines
866		866
867	dscc4.setup= [NET]	867	dscc4.setup= [NET]
868		868
		869	dt_cpu_ftrs= [PPC]
		870	Format: {"off" \| "known"}
		871	Control how the dt_cpu_ftrs device-tree binding is
		872	used for CPU feature discovery and setup (if it
		873	exists).
		874	off: Do not use it, fall back to legacy cpu table.
		875	known: Do not pass through unknown features to guests
		876	or userspace, only those that the kernel is aware of.
		877
869	dump_apple_properties [X86]	878	dump_apple_properties [X86]
870	Dump name and content of EFI device properties on	879	Dump name and content of EFI device properties on
871	x86 Macs. Useful for driver authors to determine	880	x86 Macs. Useful for driver authors to determine
@@ -3802,6 +3811,13 @@ · 2930 unmodified lines
3802	expediting. Set to zero to disable automatic	3811	expediting. Set to zero to disable automatic
3803	expediting.	3812	expediting.
3804		3813
		3814	stack_guard_gap= [MM]
		3815	override the default stack gap protection. The value
		3816	is in page units and it defines how many pages prior
		3817	to (for stacks growing down) resp. after (for stacks
		3818	growing up) the main stack are reserved for no other
		3819	mapping. Default value is 256 pages.
		3820
3805	stacktrace [FTRACE]	3821	stacktrace [FTRACE]
3806	Enabled the stack tracer on boot up.	3822	Enabled the stack tracer on boot up.
3807		3823

Documentation/devicetree/bindings/net/dsa/marvell.txt+4−0

 - interrupt-controller	: Indicates the switch is itself an interrupt
 			  controller. This is used for the PHY interrupts.
 #interrupt-cells = <2>	: Controller uses two cells, number and flag
+- eeprom-length		: Set to the length of an EEPROM connected to the
+			  switch. Must be set if the switch can not detect
+			  the presence and/or size of a connected EEPROM,
+			  otherwise optional.
 - mdio			: Container of PHY and devices on the switches MDIO
 			  bus.
 - mdio?		: Container of PHYs and devices on the external MDIO

Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt+0−2

Documentation/devicetree/bindings/usb/dwc2.txt+1−0

@@ -10,6 +10,7 @@ Required properties: · 9 unmodified lines
10	- "rockchip,rk3288-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3288 Soc;	10	- "rockchip,rk3288-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3288 Soc;
11	- "lantiq,arx100-usb": The DWC2 USB controller instance in Lantiq ARX SoCs;	11	- "lantiq,arx100-usb": The DWC2 USB controller instance in Lantiq ARX SoCs;
12	- "lantiq,xrx200-usb": The DWC2 USB controller instance in Lantiq XRX SoCs;	12	- "lantiq,xrx200-usb": The DWC2 USB controller instance in Lantiq XRX SoCs;
		13	- "amlogic,meson8-usb": The DWC2 USB controller instance in Amlogic Meson8 SoCs;
13	- "amlogic,meson8b-usb": The DWC2 USB controller instance in Amlogic Meson8b SoCs;	14	- "amlogic,meson8b-usb": The DWC2 USB controller instance in Amlogic Meson8b SoCs;
14	- "amlogic,meson-gxbb-usb": The DWC2 USB controller instance in Amlogic S905 SoCs;	15	- "amlogic,meson-gxbb-usb": The DWC2 USB controller instance in Amlogic S905 SoCs;
15	- "amcc,dwc-otg": The DWC2 USB controller instance in AMCC Canyonlands 460EX SoCs;	16	- "amcc,dwc-otg": The DWC2 USB controller instance in AMCC Canyonlands 460EX SoCs;

Documentation/networking/dpaa.txt+194−0

@@ -0,0 +1,194 @@
	1	The QorIQ DPAA Ethernet Driver
	2	==============================
	3
	4	Authors:
	5	Madalin Bucur <madalin.bucur@nxp.com>
	6	Camelia Groza <camelia.groza@nxp.com>
	7
	8	Contents
	9	========
	10
	11	- DPAA Ethernet Overview
	12	- DPAA Ethernet Supported SoCs
	13	- Configuring DPAA Ethernet in your kernel
	14	- DPAA Ethernet Frame Processing
	15	- DPAA Ethernet Features
	16	- Debugging
	17
	18	DPAA Ethernet Overview
	19	======================
	20
	21	DPAA stands for Data Path Acceleration Architecture and it is a
	22	set of networking acceleration IPs that are available on several
	23	generations of SoCs, both on PowerPC and ARM64.
	24
	25	The Freescale DPAA architecture consists of a series of hardware blocks
	26	that support Ethernet connectivity. The Ethernet driver depends upon the
	27	following drivers in the Linux kernel:
	28
	29	- Peripheral Access Memory Unit (PAMU) (* needed only for PPC platforms)
	30	drivers/iommu/fsl_*
	31	- Frame Manager (FMan)
	32	drivers/net/ethernet/freescale/fman
	33	- Queue Manager (QMan), Buffer Manager (BMan)
	34	drivers/soc/fsl/qbman
	35
	36	A simplified view of the dpaa_eth interfaces mapped to FMan MACs:
	37
	38	dpaa_eth /eth0\ ... /ethN\
	39	driver \| \| \| \|
	40	------------- ---- ----------- ---- -------------
	41	-Ports / Tx Rx \ ... / Tx Rx \
	42	FMan \| \| \| \|
	43	-MACs \| MAC0 \| \| MACN \|
	44	/ dtsec0 \ ... / dtsecN \ (or tgec)
	45	/ \ / \(or memac)
	46	--------- -------------- --- -------------- ---------
	47	FMan, FMan Port, FMan SP, FMan MURAM drivers
	48	---------------------------------------------------------
	49	FMan HW blocks: MURAM, MACs, Ports, SP
	50	---------------------------------------------------------
	51
	52	The dpaa_eth relation to the QMan, BMan and FMan:
	53	________________________________
	54	dpaa_eth / eth0 \
	55	driver / \
	56	--------- -^- -^- -^- --- ---------
	57	QMan driver / \ / \ / \ \ / \| BMan \|
	58	\|Rx \| \|Rx \| \|Tx \| \|Tx \| \| driver \|
	59	--------- \|Dfl\| \|Err\| \|Cnf\| \|FQs\| \| \|
	60	QMan HW \|FQ \| \|FQ \| \|FQs\| \| \| \| \|
	61	/ \ / \ / \ \ / \| \|
	62	--------- --- --- --- -v- ---------
	63	\| FMan QMI \| \|
	64	\| FMan HW FMan BMI \| BMan HW \|
	65	----------------------- --------
	66
	67	where the acronyms used above (and in the code) are:
	68	DPAA = Data Path Acceleration Architecture
	69	FMan = DPAA Frame Manager
	70	QMan = DPAA Queue Manager
	71	BMan = DPAA Buffers Manager
	72	QMI = QMan interface in FMan
	73	BMI = BMan interface in FMan
	74	FMan SP = FMan Storage Profiles
	75	MURAM = Multi-user RAM in FMan
	76	FQ = QMan Frame Queue
	77	Rx Dfl FQ = default reception FQ
	78	Rx Err FQ = Rx error frames FQ
	79	Tx Cnf FQ = Tx confirmation FQs
	80	Tx FQs = transmission frame queues
	81	dtsec = datapath three speed Ethernet controller (10/100/1000 Mbps)
	82	tgec = ten gigabit Ethernet controller (10 Gbps)
	83	memac = multirate Ethernet MAC (10/100/1000/10000)
	84
	85	DPAA Ethernet Supported SoCs
	86	============================
	87
	88	The DPAA drivers enable the Ethernet controllers present on the following SoCs:
	89
	90	# PPC
	91	P1023
	92	P2041
	93	P3041
	94	P4080
	95	P5020
	96	P5040
	97	T1023
	98	T1024
	99	T1040
	100	T1042
	101	T2080
	102	T4240
	103	B4860
	104
	105	# ARM
	106	LS1043A
	107	LS1046A
	108
	109	Configuring DPAA Ethernet in your kernel
	110	========================================
	111
	112	To enable the DPAA Ethernet driver, the following Kconfig options are required:
	113
	114	# common for arch/arm64 and arch/powerpc platforms
	115	CONFIG_FSL_DPAA=y
	116	CONFIG_FSL_FMAN=y
	117	CONFIG_FSL_DPAA_ETH=y
	118	CONFIG_FSL_XGMAC_MDIO=y
	119
	120	# for arch/powerpc only
	121	CONFIG_FSL_PAMU=y
	122
	123	# common options needed for the PHYs used on the RDBs
	124	CONFIG_VITESSE_PHY=y
	125	CONFIG_REALTEK_PHY=y
	126	CONFIG_AQUANTIA_PHY=y
	127
	128	DPAA Ethernet Frame Processing
	129	==============================
	130
	131	On Rx, buffers for the incoming frames are retrieved from one of the three
	132	existing buffers pools. The driver initializes and seeds these, each with
	133	buffers of different sizes: 1KB, 2KB and 4KB.
	134
	135	On Tx, all transmitted frames are returned to the driver through Tx
	136	confirmation frame queues. The driver is then responsible for freeing the
	137	buffers. In order to do this properly, a backpointer is added to the buffer
	138	before transmission that points to the skb. When the buffer returns to the
	139	driver on a confirmation FQ, the skb can be correctly consumed.
	140
	141	DPAA Ethernet Features
	142	======================
	143
	144	Currently the DPAA Ethernet driver enables the basic features required for
	145	a Linux Ethernet driver. The support for advanced features will be added
	146	gradually.
	147
	148	The driver has Rx and Tx checksum offloading for UDP and TCP. Currently the Rx
	149	checksum offload feature is enabled by default and cannot be controlled through
	150	ethtool.
	151
	152	The driver has support for multiple prioritized Tx traffic classes. Priorities
	153	range from 0 (lowest) to 3 (highest). These are mapped to HW workqueues with
	154	strict priority levels. Each traffic class contains NR_CPU TX queues. By
	155	default, only one traffic class is enabled and the lowest priority Tx queues
	156	are used. Higher priority traffic classes can be enabled with the mqprio
	157	qdisc. For example, all four traffic classes are enabled on an interface with
	158	the following command. Furthermore, skb priority levels are mapped to traffic
	159	classes as follows:
	160
	161	* priorities 0 to 3 - traffic class 0 (low priority)
	162	* priorities 4 to 7 - traffic class 1 (medium-low priority)
	163	* priorities 8 to 11 - traffic class 2 (medium-high priority)
	164	* priorities 12 to 15 - traffic class 3 (high priority)
	165
	166	tc qdisc add dev <int> root handle 1: \
	167	mqprio num_tc 4 map 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 hw 1
	168
	169	Debugging
	170	=========
	171
	172	The following statistics are exported for each interface through ethtool:
	173
	174	- interrupt count per CPU
	175	- Rx packets count per CPU
	176	- Tx packets count per CPU
	177	- Tx confirmed packets count per CPU
	178	- Tx S/G frames count per CPU
	179	- Tx error count per CPU
	180	- Rx error count per CPU
	181	- Rx error count per type
	182	- congestion related statistics:
	183	- congestion status
	184	- time spent in congestion
	185	- number of time the device entered congestion
	186	- dropped packets count per cause
	187
	188	The driver also exports the following information in sysfs:
	189
	190	- the FQ IDs for each FQ type
	191	/sys/devices/platform/dpaa-ethernet.0/net/<int>/fqids
	192
	193	- the IDs of the buffer pools in use
	194	/sys/devices/platform/dpaa-ethernet.0/net/<int>/bpids

Documentation/networking/scaling.txt+1−1

@@ -122,7 +122,7 @@ associated flow of the packet. The hash is either provided by hardware · 121 unmodified lines
122	or will be computed in the stack. Capable hardware can pass the hash in	122	or will be computed in the stack. Capable hardware can pass the hash in
123	the receive descriptor for the packet; this would usually be the same	123	the receive descriptor for the packet; this would usually be the same
124	hash used for RSS (e.g. computed Toeplitz hash). The hash is saved in	124	hash used for RSS (e.g. computed Toeplitz hash). The hash is saved in
125	skb->rx_hash and can be used elsewhere in the stack as a hash of the	125	skb->hash and can be used elsewhere in the stack as a hash of the
126	packet’s flow.	126	packet’s flow.
127		127
128	Each receive hardware queue has an associated list of CPUs to which	128	Each receive hardware queue has an associated list of CPUs to which

Documentation/networking/tcp.txt+13−18

 TCP protocol
 ============
-Last updated: 9 February 2008
+Last updated: 3 June 2017
 Contents
 ========
 A congestion control mechanism can be registered through functions in
 tcp_cong.c. The functions used by the congestion control mechanism are
 registered via passing a tcp_congestion_ops struct to
-tcp_register_congestion_control. As a minimum name, ssthresh,
+tcp_register_congestion_control. As a minimum, the congestion control
-cong_avoid must be valid.
+mechanism must provide a valid name and must implement either ssthresh,
+cong_avoid and undo_cwnd hooks or the "omnipotent" cong_control hook.
 Private data for a congestion control mechanism is stored in tp->ca_priv.
 tcp_ca(tp) returns a pointer to this space.  This is preallocated space - it
 is important to check the size of your private data will fit this space, or
-alternatively space could be allocated elsewhere and a pointer to it could
+alternatively, space could be allocated elsewhere and a pointer to it could
 be stored here.
 There are three kinds of congestion control algorithms currently: The
 simplest ones are derived from TCP reno (highspeed, scalable) and just
-provide an alternative the congestion window calculation. More complex
+provide an alternative congestion window calculation. More complex
 ones like BIC try to look at other events to provide better
 heuristics.  There are also round trip time based algorithms like
 Vegas and Westwood+.
 needs to maintain fairness and performance. Please review current
 research and RFC's before developing new modules.
-The method that is used to determine which congestion control mechanism is
+The default congestion control mechanism is chosen based on the
-determined by the setting of the sysctl net.ipv4.tcp_congestion_control.
+DEFAULT_TCP_CONG Kconfig parameter. If you really want a particular default
-The default congestion control will be the last one registered (LIFO);
+value then you can set it using sysctl net.ipv4.tcp_congestion_control. The
-so if you built everything as modules, the default will be reno. If you
+module will be autoloaded if needed and you will get the expected protocol. If
-build with the defaults from Kconfig, then CUBIC will be builtin (not a
+you ask for an unknown congestion method, then the sysctl attempt will fail.
-module) and it will end up the default.
-If you really want a particular default value then you will need
+If you remove a TCP congestion control module, then you will get the next
-to set it with the sysctl.  If you use a sysctl, the module will be autoloaded
-if needed and you will get the expected protocol. If you ask for an
-unknown congestion method, then the sysctl attempt will fail.
-If you remove a tcp congestion control module, then you will get the next
 available one. Since reno cannot be built as a module, and cannot be
-deleted, it will always be available.
+removed, it will always be available.
 How the new TCP output machine [nyi] works.
 ===========================================

MAINTAINERS+16−17

 ARM/CIRRUS LOGIC EP93XX ARM ARCHITECTURE
 M:	Hartley Sweeten <hsweeten@visionengravers.com>
-M:	Ryan Mallon <rmallon@gmail.com>
+M:	Alexander Sverdlin <alexander.sverdlin@gmail.com>
 L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 S:	Maintained
 F:	arch/arm/mach-ep93xx/
 M:	Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
 L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 S:	Maintained
-F:	arch/arm/mach-mvebu/
-F:	drivers/rtc/rtc-armada38x.c
 F:	arch/arm/boot/dts/armada*
 F:	arch/arm/boot/dts/kirkwood*
+F:	arch/arm/configs/mvebu_*_defconfig
+F:	arch/arm/mach-mvebu/
 F:	arch/arm64/boot/dts/marvell/armada*
 F:	drivers/cpufreq/mvebu-cpufreq.c
-F:	arch/arm/configs/mvebu_*_defconfig
+F:	drivers/irqchip/irq-armada-370-xp.c
+F:	drivers/irqchip/irq-mvebu-*
+F:	drivers/rtc/rtc-armada38x.c
 ARM/Marvell Berlin SoC support
 M:	Jisheng Zhang <jszhang@marvell.com>
 ARM/SAMSUNG EXYNOS ARM ARCHITECTURES
 M:	Kukjin Kim <kgene@kernel.org>
 M:	Krzysztof Kozlowski <krzk@kernel.org>
-R:	Javier Martinez Canillas <javier@osg.samsung.com>
 L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 L:	linux-samsung-soc@vger.kernel.org (moderated for non-subscribers)
 Q:	https://patchwork.kernel.org/project/linux-samsung-soc/list/
 ARM/STI ARCHITECTURE
 M:	Patrice Chotard <patrice.chotard@st.com>
 L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
-L:	kernel@stlinux.com
 W:	http://www.stlinux.com
 S:	Maintained
 F:	arch/arm/mach-sti/
 GENWQE (IBM Generic Workqueue Card)
 M:	Frank Haverkamp <haver@linux.vnet.ibm.com>
-M:	Gabriel Krisman Bertazi <krisman@linux.vnet.ibm.com>
+M:	Guilherme G. Piccoli <gpiccoli@linux.vnet.ibm.com>
 S:	Supported
 F:	drivers/misc/genwqe/
 GPIO SUBSYSTEM
 M:	Linus Walleij <linus.walleij@linaro.org>
-M:	Alexandre Courbot <gnurou@gmail.com>
 L:	linux-gpio@vger.kernel.org
 T:	git git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio.git
 S:	Maintained
 LIVE PATCHING
 M:	Josh Poimboeuf <jpoimboe@redhat.com>
-M:	Jessica Yu <jeyu@redhat.com>
+M:	Jessica Yu <jeyu@kernel.org>
 M:	Jiri Kosina <jikos@kernel.org>
 M:	Miroslav Benes <mbenes@suse.cz>
 R:	Petr Mladek <pmladek@suse.com>
 F:	drivers/media/radio/radio-miropcm20*
 MELLANOX MLX4 core VPI driver
-M:	Yishai Hadas <yishaih@mellanox.com>
+M:	Tariq Toukan <tariqt@mellanox.com>
 L:	netdev@vger.kernel.org
 L:	linux-rdma@vger.kernel.org
 W:	http://www.mellanox.com
 S:	Supported
 F:	drivers/net/ethernet/mellanox/mlx4/
 F:	include/linux/mlx4/
-F:	include/uapi/rdma/mlx4-abi.h
 MELLANOX MLX4 IB driver
 M:	Yishai Hadas <yishaih@mellanox.com>
 S:	Supported
 F:	drivers/infiniband/hw/mlx4/
 F:	include/linux/mlx4/
+F:	include/uapi/rdma/mlx4-abi.h
 MELLANOX MLX5 core VPI driver
 M:	Saeed Mahameed <saeedm@mellanox.com>
 S:	Supported
 F:	drivers/net/ethernet/mellanox/mlx5/core/
 F:	include/linux/mlx5/
-F:	include/uapi/rdma/mlx5-abi.h
 MELLANOX MLX5 IB driver
 M:	Matan Barak <matanb@mellanox.com>
 S:	Supported
 F:	drivers/infiniband/hw/mlx5/
 F:	include/linux/mlx5/
+F:	include/uapi/rdma/mlx5-abi.h
 MELEXIS MLX90614 DRIVER
 M:	Crt Mori <cmo@melexis.com>
 F:	drivers/media/dvb-frontends/mn88473*
 MODULE SUPPORT
-M:	Jessica Yu <jeyu@redhat.com>
+M:	Jessica Yu <jeyu@kernel.org>
 M:	Rusty Russell <rusty@rustcorp.com.au>
 T:	git git://git.kernel.org/pub/scm/linux/kernel/git/jeyu/linux.git modules-next
 S:	Maintained
 PXA RTC DRIVER
 M:	Robert Jarzmik <robert.jarzmik@free.fr>
-L:	rtc-linux@googlegroups.com
+L:	linux-rtc@vger.kernel.org
 S:	Maintained
 QAT DRIVER
 REAL TIME CLOCK (RTC) SUBSYSTEM
 M:	Alessandro Zummo <a.zummo@towertech.it>
 M:	Alexandre Belloni <alexandre.belloni@free-electrons.com>
-L:	rtc-linux@googlegroups.com
+L:	linux-rtc@vger.kernel.org
 Q:	http://patchwork.ozlabs.org/project/rtc-linux/list/
 T:	git git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux.git
 S:	Maintained
 STI CEC DRIVER
 M:	Benjamin Gaignard <benjamin.gaignard@linaro.org>
-L:	kernel@stlinux.com
 S:	Maintained
 F:	drivers/staging/media/st-cec/
 F:	Documentation/devicetree/bindings/media/stih-cec.txt
 S:	Supported
 F:	arch/arm/mach-davinci/
 F:	drivers/i2c/busses/i2c-davinci.c
+F:	arch/arm/boot/dts/da850*
 TI DAVINCI SERIES MEDIA DRIVER
 M:	"Lad, Prabhakar" <prabhakar.csengg@gmail.com>
 F:	drivers/net/wireless/wl3501*
 WOLFSON MICROELECTRONICS DRIVERS
-L:	patches@opensource.wolfsonmicro.com
+L:	patches@opensource.cirrus.com
 T:	git https://github.com/CirrusLogic/linux-drivers.git
 W:	https://github.com/CirrusLogic/linux-drivers/wiki
 S:	Supported

Makefile+1−1

@@ -1,7 +1,7 @@
1	VERSION = 4	1	VERSION = 4
2	PATCHLEVEL = 12	2	PATCHLEVEL = 12
3	SUBLEVEL = 0	3	SUBLEVEL = 0
4	EXTRAVERSION = -rc3	4	EXTRAVERSION = -rc6
5	NAME = Fearless Coyote	5	NAME = Fearless Coyote
6		6
7	# DOCUMENTATION	7	# DOCUMENTATION

arch/arc/mm/mmap.c+1−1

@@ -65,7 +65,7 @@ arch_get_unmapped_area(struct file *filp, unsigned long addr, · 64 unmodified lines
65		65
66	vma = find_vma(mm, addr);	66	vma = find_vma(mm, addr);
67	if (TASK_SIZE - len >= addr &&	67	if (TASK_SIZE - len >= addr &&
68	(!vma \|\| addr + len <= vma->vm_start))	68	(!vma \|\| addr + len <= vm_start_gap(vma)))
69	return addr;	69	return addr;
70	}	70	}
71		71

arch/arm/boot/compressed/efi-header.S+1−3

 		@ there.
 		.inst	'M' | ('Z' << 8) | (0x1310 << 16)   @ tstne r0, #0x4d000
 #else
-		mov	r0, r0
+		W(mov)	r0, r0
 #endif
 		.endm
 		.macro	__EFI_HEADER
 #ifdef CONFIG_EFI_STUB
-		b	__efi_start
 		.set	start_offset, __efi_start - start
 		.org	start + 0x3c
 		@

arch/arm/boot/compressed/head.S+10−7

 		.rept	7
 		__nop
 		.endr
-   ARM(		mov	r0, r0		)
+#ifndef CONFIG_THUMB2_KERNEL
-   ARM(		b	1f		)
+		mov	r0, r0
- THUMB(		badr	r12, 1f		)
+#else
- THUMB(		bx	r12		)
+ AR_CLASS(	sub	pc, pc, #3	)	@ A/R: switch to Thumb2 mode
+  M_CLASS(	nop.w			)	@ M: already in Thumb2 mode
+		.thumb
+#endif
+		W(b)	1f
 		.word	_magic_sig	@ Magic numbers to help the loader
 		.word	_magic_start	@ absolute load/run zImage address
 		.word	_magic_end	@ zImage end address
 		.word	0x04030201	@ endianness flag
- THUMB(		.thumb			)
+		__EFI_HEADER
-1:		__EFI_HEADER
+1:
  ARM_BE8(	setend	be		)	@ go BE8 if compiled for BE8
  AR_CLASS(	mrs	r9, cpsr	)
 #ifdef CONFIG_ARM_VIRT_EXT

arch/arm/boot/dts/am335x-sl50.dts+2−6

 	mmc1_pins: pinmux_mmc1_pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7)		/* spi0_cs1.gpio0_6 */
+			AM33XX_IOPAD(0x96c, PIN_INPUT | MUX_MODE7)		/* uart0_rtsn.gpio1_9 */
 		>;
 	};
 			AM33XX_IOPAD(0x834, PIN_INPUT_PULLUP | MUX_MODE7)	/* nKbdReset - gpmc_ad13.gpio1_13 */
 			AM33XX_IOPAD(0x838, PIN_INPUT_PULLUP | MUX_MODE7)	/* nDispReset - gpmc_ad14.gpio1_14 */
 			AM33XX_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE7)	/* USB1_enPower - gpmc_a1.gpio1_17 */
-			/* AVR Programming - SPI Bus (bit bang) - Screen and Keyboard */
-			AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE7)	/* Kbd/Disp/BattMOSI spi0_d0.gpio0_3 */
-			AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE7)	/* Kbd/Disp/BattMISO spi0_d1.gpio0_4 */
-			AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE7)	/* Kbd/Disp/BattSCLK spi0_clk.gpio0_2 */
 			/* PDI Bus - Battery system */
 			AM33XX_IOPAD(0x840, PIN_INPUT_PULLUP | MUX_MODE7)	/* nBattReset  gpmc_a0.gpio1_16 */
 			AM33XX_IOPAD(0x83c, PIN_INPUT_PULLUP | MUX_MODE7)	/* BattPDIData gpmc_ad15.gpio1_15 */
 	pinctrl-names = "default";
 	pinctrl-0 = <&mmc1_pins>;
 	bus-width = <4>;
-	cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+	cd-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
 	vmmc-supply = <&vmmcsd_fixed>;
 };

arch/arm/boot/dts/bcm283x.dtsi+5−0

 #include <dt-bindings/clock/bcm2835-aux.h>
 #include <dt-bindings/gpio/gpio.h>
+/* firmware-provided startup stubs live here, where the secondary CPUs are
+ * spinning.
+ */
+/memreserve/ 0x00000000 0x00001000;
 /* This include file covers the common peripherals and configuration between
  * bcm2835 and bcm2836 implementations, leaving the CPU configuration to
  * bcm2835.dtsi and bcm2836.dtsi.

arch/arm/boot/dts/imx6ul-14x14-evk.dts+6−0

 		ethphy0: ethernet-phy@2 {
 			reg = <2>;
+			micrel,led-mode = <1>;
+			clocks = <&clks IMX6UL_CLK_ENET_REF>;
+			clock-names = "rmii-ref";
 		};
 		ethphy1: ethernet-phy@1 {
 			reg = <1>;
+			micrel,led-mode = <1>;
+			clocks = <&clks IMX6UL_CLK_ENET2_REF>;
+			clock-names = "rmii-ref";
 		};
 	};
 };

arch/arm/boot/dts/keystone-k2l-netcp.dtsi+2−2

@@ -137,8 +137,8 @@ netcp: netcp@26000000 { · 136 unmodified lines
137	/* NetCP address range */	137	/* NetCP address range */
138	ranges = <0 0x26000000 0x1000000>;	138	ranges = <0 0x26000000 0x1000000>;
139		139
140	clocks = <&clkpa>, <&clkcpgmac>, <&chipclk12>, <&clkosr>;	140	clocks = <&clkpa>, <&clkcpgmac>, <&chipclk12>;
141	clock-names = "pa_clk", "ethss_clk", "cpts", "osr_clk";	141	clock-names = "pa_clk", "ethss_clk", "cpts";
142	dma-coherent;	142	dma-coherent;
143		143
144	ti,navigator-dmas = <&dma_gbe 0>,	144	ti,navigator-dmas = <&dma_gbe 0>,

arch/arm/boot/dts/keystone-k2l.dtsi+8−0

@@ -232,6 +232,14 @@ · 231 unmodified lines
232	};	232	};
233	};	233	};
234		234
		235	osr: sram@70000000 {
		236	compatible = "mmio-sram";
		237	reg = <0x70000000 0x10000>;
		238	#address-cells = <1>;
		239	#size-cells = <1>;
		240	clocks = <&clkosr>;
		241	};
		242
235	dspgpio0: keystone_dsp_gpio@02620240 {	243	dspgpio0: keystone_dsp_gpio@02620240 {
236	compatible = "ti,keystone-dsp-gpio";	244	compatible = "ti,keystone-dsp-gpio";
237	gpio-controller;	245	gpio-controller;

arch/arm/boot/dts/sunxi-h3-h5.dtsi+4−3

 		};
 		r_ccu: clock@1f01400 {
-			compatible = "allwinner,sun50i-a64-r-ccu";
+			compatible = "allwinner,sun8i-h3-r-ccu";
 			reg = <0x01f01400 0x100>;
-			clocks = <&osc24M>, <&osc32k>, <&iosc>;
+			clocks = <&osc24M>, <&osc32k>, <&iosc>,
-			clock-names = "hosc", "losc", "iosc";
+				 <&ccu 9>;
+			clock-names = "hosc", "losc", "iosc", "pll-periph";
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 		};

arch/arm/boot/dts/versatile-pb.dts+1−1

@@ -1,4 +1,4 @@
1	#include <versatile-ab.dts>	1	#include "versatile-ab.dts"
2		2
3	/ {	3	/ {
4	model = "ARM Versatile PB";	4	model = "ARM Versatile PB";

arch/arm/common/mcpm_entry.c+3−3

@@ -235,7 +235,7 @@ int mcpm_cpu_power_up(unsigned int cpu, unsigned int cluster) · 234 unmodified lines
235	return ret;	235	return ret;
236	}	236	}
237		237
238	typedef void (*phys_reset_t)(unsigned long);	238	typedef typeof(cpu_reset) phys_reset_t;
239		239
240	void mcpm_cpu_power_down(void)	240	void mcpm_cpu_power_down(void)
241	{	241	{
@@ -300,7 +300,7 @@ void mcpm_cpu_power_down(void) · 58 unmodified lines
300	* on the CPU.	300	* on the CPU.
301	*/	301	*/
302	phys_reset = (phys_reset_t)(unsigned long)__pa_symbol(cpu_reset);	302	phys_reset = (phys_reset_t)(unsigned long)__pa_symbol(cpu_reset);
303	phys_reset(__pa_symbol(mcpm_entry_point));	303	phys_reset(__pa_symbol(mcpm_entry_point), false);
304		304
305	/* should never get here */	305	/* should never get here */
306	BUG();	306	BUG();
@@ -389,7 +389,7 @@ static int __init nocache_trampoline(unsigned long _arg) · 82 unmodified lines
389	__mcpm_cpu_down(cpu, cluster);	389	__mcpm_cpu_down(cpu, cluster);
390		390
391	phys_reset = (phys_reset_t)(unsigned long)__pa_symbol(cpu_reset);	391	phys_reset = (phys_reset_t)(unsigned long)__pa_symbol(cpu_reset);
392	phys_reset(__pa_symbol(mcpm_entry_point));	392	phys_reset(__pa_symbol(mcpm_entry_point), false);
393	BUG();	393	BUG();
394	}	394	}
395		395

arch/arm/include/asm/device.h+2−1

@@ -19,7 +19,8 @@ struct dev_archdata { · 18 unmodified lines
19	#ifdef CONFIG_XEN	19	#ifdef CONFIG_XEN
20	const struct dma_map_ops *dev_dma_ops;	20	const struct dma_map_ops *dev_dma_ops;
21	#endif	21	#endif
22	bool dma_coherent;	22	unsigned int dma_coherent:1;
		23	unsigned int dma_ops_setup:1;
23	};	24	};
24		25
25	struct omap_device;	26	struct omap_device;

arch/arm/include/asm/pgtable-nommu.h+1−0

@@ -66,6 +66,7 @@ typedef pte_t *pte_addr_t; · 65 unmodified lines
66	#define pgprot_noncached(prot) (prot)	66	#define pgprot_noncached(prot) (prot)
67	#define pgprot_writecombine(prot) (prot)	67	#define pgprot_writecombine(prot) (prot)
68	#define pgprot_dmacoherent(prot) (prot)	68	#define pgprot_dmacoherent(prot) (prot)
		69	#define pgprot_device(prot) (prot)
69		70
70		71
71	/*	72	/*

arch/arm/kvm/init.S+2−3

 	@  - Write permission implies XN: disabled
 	@  - Instruction cache: enabled
 	@  - Data/Unified cache: enabled
-	@  - Memory alignment checks: enabled
 	@  - MMU: enabled (this code must be run from an identity mapping)
 	mrc	p15, 4, r0, c1, c0, 0	@ HSCR
 	ldr	r2, =HSCTLR_MASK
 	mrc	p15, 0, r1, c1, c0, 0	@ SCTLR
 	ldr	r2, =(HSCTLR_EE | HSCTLR_FI | HSCTLR_I | HSCTLR_C)
 	and	r1, r1, r2
- ARM(	ldr	r2, =(HSCTLR_M | HSCTLR_A)			)
+ ARM(	ldr	r2, =(HSCTLR_M)					)
- THUMB(	ldr	r2, =(HSCTLR_M | HSCTLR_A | HSCTLR_TE)		)
+ THUMB(	ldr	r2, =(HSCTLR_M | HSCTLR_TE)			)
 	orr	r1, r1, r2
 	orr	r0, r0, r1
 	mcr	p15, 4, r0, c1, c0, 0	@ HSCR

arch/arm/mach-at91/Kconfig+1−0

@@ -1,6 +1,7 @@
1	menuconfig ARCH_AT91	1	menuconfig ARCH_AT91
2	bool "Atmel SoCs"	2	bool "Atmel SoCs"
3	depends on ARCH_MULTI_V4T \|\| ARCH_MULTI_V5 \|\| ARCH_MULTI_V7	3	depends on ARCH_MULTI_V4T \|\| ARCH_MULTI_V5 \|\| ARCH_MULTI_V7
		4	select ARM_CPU_SUSPEND if PM
4	select COMMON_CLK_AT91	5	select COMMON_CLK_AT91
5	select GPIOLIB	6	select GPIOLIB
6	select PINCTRL	7	select PINCTRL

arch/arm/mach-davinci/pm.c+6−1

 	davinci_sram_suspend = sram_alloc(davinci_cpu_suspend_sz, NULL);
 	if (!davinci_sram_suspend) {
 		pr_err("PM: cannot allocate SRAM memory\n");
-		return -ENOMEM;
+		ret = -ENOMEM;
+		goto no_sram_mem;
 	}
 	davinci_sram_push(davinci_sram_suspend, davinci_cpu_suspend,
 	suspend_set_ops(&davinci_pm_ops);
+	return 0;
+no_sram_mem:
+	iounmap(pm_config.ddrpsc_reg_base);
 no_ddrpsc_mem:
 	iounmap(pm_config.ddrpll_reg_base);
 no_ddrpll_mem:

arch/arm/mm/dma-mapping.c+14−15

 }
 EXPORT_SYMBOL_GPL(arm_iommu_attach_device);
-static void __arm_iommu_detach_device(struct device *dev)
+/**
+ * arm_iommu_detach_device
+ * @dev: valid struct device pointer
+ *
+ * Detaches the provided device from a previously attached map.
+ * This voids the dma operations (dma_map_ops pointer)
+ */
+void arm_iommu_detach_device(struct device *dev)
 {
 	struct dma_iommu_mapping *mapping;
 	iommu_detach_device(mapping->domain, dev);
 	kref_put(&mapping->kref, release_iommu_mapping);
 	to_dma_iommu_mapping(dev) = NULL;
+	set_dma_ops(dev, NULL);
 	pr_debug("Detached IOMMU controller from %s device.\n", dev_name(dev));
 }
-/**
- * arm_iommu_detach_device
- * @dev: valid struct device pointer
- *
- * Detaches the provided device from a previously attached map.
- * This voids the dma operations (dma_map_ops pointer)
- */
-void arm_iommu_detach_device(struct device *dev)
-{
-	__arm_iommu_detach_device(dev);
-	set_dma_ops(dev, NULL);
-}
 EXPORT_SYMBOL_GPL(arm_iommu_detach_device);
 static const struct dma_map_ops *arm_get_iommu_dma_map_ops(bool coherent)
 	if (!mapping)
 		return;
-	__arm_iommu_detach_device(dev);
+	arm_iommu_detach_device(dev);
 	arm_iommu_release_mapping(mapping);
 }
 		dev->dma_ops = xen_dma_ops;
 	}
 #endif
+	dev->archdata.dma_ops_setup = true;
 }
 void arch_teardown_dma_ops(struct device *dev)
 {
+	if (!dev->archdata.dma_ops_setup)
+		return;
 	arm_teardown_iommu_dma_ops(dev);
 }

arch/arm/mm/mmap.c+2−2

@@ -90,7 +90,7 @@ arch_get_unmapped_area(struct file *filp, unsigned long addr, · 89 unmodified lines
90		90
91	vma = find_vma(mm, addr);	91	vma = find_vma(mm, addr);
92	if (TASK_SIZE - len >= addr &&	92	if (TASK_SIZE - len >= addr &&
93	(!vma \|\| addr + len <= vma->vm_start))	93	(!vma \|\| addr + len <= vm_start_gap(vma)))
94	return addr;	94	return addr;
95	}	95	}
96		96
@@ -141,7 +141,7 @@ arch_get_unmapped_area_topdown(struct file *filp, const unsigned long addr0, · 44 unmodified lines
141	addr = PAGE_ALIGN(addr);	141	addr = PAGE_ALIGN(addr);
142	vma = find_vma(mm, addr);	142	vma = find_vma(mm, addr);
143	if (TASK_SIZE - len >= addr &&	143	if (TASK_SIZE - len >= addr &&
144	(!vma \|\| addr + len <= vma->vm_start))	144	(!vma \|\| addr + len <= vm_start_gap(vma)))
145	return addr;	145	return addr;
146	}	146	}
147		147

arch/arm64/Kconfig+0−4

@@ -1084,10 +1084,6 @@ config SYSVIPC_COMPAT · 1083 unmodified lines
1084	def_bool y	1084	def_bool y
1085	depends on COMPAT && SYSVIPC	1085	depends on COMPAT && SYSVIPC
1086		1086
1087	config KEYS_COMPAT
1088	def_bool y
1089	depends on COMPAT && KEYS
1090
1091	endmenu	1087	endmenu
1092		1088
1093	menu "Power management options"	1089	menu "Power management options"

arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi+3−2

 		r_ccu: clock@1f01400 {
 			compatible = "allwinner,sun50i-a64-r-ccu";
 			reg = <0x01f01400 0x100>;
-			clocks = <&osc24M>, <&osc32k>, <&iosc>;
+			clocks = <&osc24M>, <&osc32k>, <&iosc>,
-			clock-names = "hosc", "losc", "iosc";
+				 <&ccu 11>;
+			clock-names = "hosc", "losc", "iosc", "pll-periph";
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 		};

arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi+1−1

@@ -40,7 +40,7 @@ · 39 unmodified lines
40	* OTHER DEALINGS IN THE SOFTWARE.	40	* OTHER DEALINGS IN THE SOFTWARE.
41	*/	41	*/
42		42
43	#include "sunxi-h3-h5.dtsi"	43	#include <arm/sunxi-h3-h5.dtsi>
44		44
45	/ {	45	/ {
46	cpus {	46	cpus {

arch/arm64/boot/dts/allwinner/sunxi-h3-h5.dtsi+0−1

@@ -1 +0,0 @@
1	../../../../arm/boot/dts/sunxi-h3-h5.dtsi

arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi+1−2

 			cpm_crypto: crypto@800000 {
 				compatible = "inside-secure,safexcel-eip197";
 				reg = <0x800000 0x200000>;
-				interrupts = <GIC_SPI 34 (IRQ_TYPE_EDGE_RISING
+				interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
-				| IRQ_TYPE_LEVEL_HIGH)>,
 					     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,

arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi+1−2

 			cps_crypto: crypto@800000 {
 				compatible = "inside-secure,safexcel-eip197";
 				reg = <0x800000 0x200000>;
-				interrupts = <GIC_SPI 34 (IRQ_TYPE_EDGE_RISING
+				interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
-				| IRQ_TYPE_LEVEL_HIGH)>,
 					     <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,

arch/arm64/configs/defconfig+10−0

 CONFIG_PCIE_ARMADA_8K=y
 CONFIG_PCI_AARDVARK=y
 CONFIG_PCIE_RCAR=y
+CONFIG_PCIE_ROCKCHIP=m
 CONFIG_PCI_HOST_GENERIC=y
 CONFIG_PCI_XGENE=y
 CONFIG_ARM64_VA_BITS_48=y
 CONFIG_WL18XX=m
 CONFIG_WLCORE_SDIO=m
 CONFIG_INPUT_EVDEV=y
+CONFIG_KEYBOARD_ADC=m
+CONFIG_KEYBOARD_CROS_EC=y
 CONFIG_KEYBOARD_GPIO=y
 CONFIG_INPUT_MISC=y
 CONFIG_INPUT_PM8941_PWRKEY=y
 CONFIG_SPI_ORION=y
 CONFIG_SPI_PL022=y
 CONFIG_SPI_QUP=y
+CONFIG_SPI_ROCKCHIP=y
 CONFIG_SPI_S3C64XX=y
 CONFIG_SPI_SPIDEV=m
 CONFIG_SPMI=y
 CONFIG_CPU_THERMAL=y
 CONFIG_THERMAL_EMULATION=y
 CONFIG_EXYNOS_THERMAL=y
+CONFIG_ROCKCHIP_THERMAL=m
 CONFIG_WATCHDOG=y
 CONFIG_S3C2410_WATCHDOG=y
 CONFIG_MESON_GXBB_WATCHDOG=m
 CONFIG_BCM2835_WDT=y
 CONFIG_MFD_CROS_EC=y
 CONFIG_MFD_CROS_EC_I2C=y
+CONFIG_MFD_CROS_EC_SPI=y
 CONFIG_MFD_EXYNOS_LPASS=m
 CONFIG_MFD_HI655X_PMIC=y
 CONFIG_MFD_MAX77620=y
 CONFIG_MFD_SPMI_PMIC=y
 CONFIG_MFD_RK808=y
 CONFIG_MFD_SEC_CORE=y
+CONFIG_REGULATOR_FAN53555=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_REGULATOR_GPIO=y
 CONFIG_REGULATOR_HI655X=y
 CONFIG_EXTCON_USB_GPIO=y
 CONFIG_IIO=y
 CONFIG_EXYNOS_ADC=y
+CONFIG_ROCKCHIP_SARADC=m
 CONFIG_PWM=y
 CONFIG_PWM_BCM2835=m
+CONFIG_PWM_CROS_EC=m
 CONFIG_PWM_MESON=m
 CONFIG_PWM_ROCKCHIP=y
 CONFIG_PWM_SAMSUNG=y
 CONFIG_PHY_SUN4I_USB=y
 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
 CONFIG_PHY_ROCKCHIP_EMMC=y
+CONFIG_PHY_ROCKCHIP_PCIE=m
 CONFIG_PHY_XGENE=y
 CONFIG_PHY_TEGRA_XUSB=y
 CONFIG_ARM_SCPI_PROTOCOL=y

arch/arm64/include/asm/acpi.h+3−3

@@ -23,9 +23,9 @@ · 22 unmodified lines
23	#define ACPI_MADT_GICC_LENGTH \	23	#define ACPI_MADT_GICC_LENGTH \
24	(acpi_gbl_FADT.header.revision < 6 ? 76 : 80)	24	(acpi_gbl_FADT.header.revision < 6 ? 76 : 80)
25		25
26	#define BAD_MADT_GICC_ENTRY(entry, end) \	26	#define BAD_MADT_GICC_ENTRY(entry, end) \
27	(!(entry) \|\| (unsigned long)(entry) + sizeof(*(entry)) > (end) \|\| \	27	(!(entry) \|\| (entry)->header.length != ACPI_MADT_GICC_LENGTH \|\| \
28	(entry)->header.length != ACPI_MADT_GICC_LENGTH)	28	(unsigned long)(entry) + ACPI_MADT_GICC_LENGTH > (end))
29		29
30	/* Basic configuration for ACPI */	30	/* Basic configuration for ACPI */
31	#ifdef CONFIG_ACPI	31	#ifdef CONFIG_ACPI

arch/arm64/include/asm/sysreg.h+4−0

@@ -286,6 +286,10 @@ · 285 unmodified lines
286	#define SCTLR_ELx_A (1 << 1)	286	#define SCTLR_ELx_A (1 << 1)
287	#define SCTLR_ELx_M 1	287	#define SCTLR_ELx_M 1
288		288
		289	#define SCTLR_EL2_RES1 ((1 << 4) \| (1 << 5) \| (1 << 11) \| (1 << 16) \| \
		290	(1 << 16) \| (1 << 18) \| (1 << 22) \| (1 << 23) \| \
		291	(1 << 28) \| (1 << 29))
		292
289	#define SCTLR_ELx_FLAGS (SCTLR_ELx_M \| SCTLR_ELx_A \| SCTLR_ELx_C \| \	293	#define SCTLR_ELx_FLAGS (SCTLR_ELx_M \| SCTLR_ELx_A \| SCTLR_ELx_C \| \
290	SCTLR_ELx_SA \| SCTLR_ELx_I)	294	SCTLR_ELx_SA \| SCTLR_ELx_I)
291		295

arch/arm64/kernel/pci.c+3−1

 		return NULL;
 	root_ops = kzalloc_node(sizeof(*root_ops), GFP_KERNEL, node);
-	if (!root_ops)
+	if (!root_ops) {
+		kfree(ri);
 		return NULL;
+	}
 	ri->cfg = pci_acpi_setup_ecam_mapping(root);
 	if (!ri->cfg) {

arch/arm64/kvm/hyp-init.S+7−4

 	tlbi	alle2
 	dsb	sy
-	mrs	x4, sctlr_el2
+	/*
-	and	x4, x4, #SCTLR_ELx_EE	// preserve endianness of EL2
+	 * Preserve all the RES1 bits while setting the default flags,
-	ldr	x5, =SCTLR_ELx_FLAGS
+	 * as well as the EE bit on BE. Drop the A flag since the compiler
-	orr	x4, x4, x5
+	 * is allowed to generate unaligned accesses.
+	 */
+	ldr	x4, =(SCTLR_EL2_RES1 | (SCTLR_ELx_FLAGS & ~SCTLR_ELx_A))
+CPU_BE(	orr	x4, x4, #SCTLR_ELx_EE)
 	msr	sctlr_el2, x4
 	isb

arch/arm64/kvm/vgic-sys-reg-v3.c+5−5

@@ -65,8 +65,8 @@ static bool access_gic_ctlr(struct kvm_vcpu vcpu, struct sys_reg_params p, · 64 unmodified lines
65	* Here set VMCR.CTLR in ICC_CTLR_EL1 layout.	65	* Here set VMCR.CTLR in ICC_CTLR_EL1 layout.
66	* The vgic_set_vmcr() will convert to ICH_VMCR layout.	66	* The vgic_set_vmcr() will convert to ICH_VMCR layout.
67	*/	67	*/
68	vmcr.ctlr = val & ICC_CTLR_EL1_CBPR_MASK;	68	vmcr.cbpr = (val & ICC_CTLR_EL1_CBPR_MASK) >> ICC_CTLR_EL1_CBPR_SHIFT;
69	vmcr.ctlr \|= val & ICC_CTLR_EL1_EOImode_MASK;	69	vmcr.eoim = (val & ICC_CTLR_EL1_EOImode_MASK) >> ICC_CTLR_EL1_EOImode_SHIFT;
70	vgic_set_vmcr(vcpu, &vmcr);	70	vgic_set_vmcr(vcpu, &vmcr);
71	} else {	71	} else {
72	val = 0;	72	val = 0;
@@ -83,8 +83,8 @@ static bool access_gic_ctlr(struct kvm_vcpu vcpu, struct sys_reg_params p, · 10 unmodified lines
83	* The VMCR.CTLR value is in ICC_CTLR_EL1 layout.	83	* The VMCR.CTLR value is in ICC_CTLR_EL1 layout.
84	* Extract it directly using ICC_CTLR_EL1 reg definitions.	84	* Extract it directly using ICC_CTLR_EL1 reg definitions.
85	*/	85	*/
86	val \|= vmcr.ctlr & ICC_CTLR_EL1_CBPR_MASK;	86	val \|= (vmcr.cbpr << ICC_CTLR_EL1_CBPR_SHIFT) & ICC_CTLR_EL1_CBPR_MASK;
87	val \|= vmcr.ctlr & ICC_CTLR_EL1_EOImode_MASK;	87	val \|= (vmcr.eoim << ICC_CTLR_EL1_EOImode_SHIFT) & ICC_CTLR_EL1_EOImode_MASK;
88		88
89	p->regval = val;	89	p->regval = val;
90	}	90	}
@@ -135,7 +135,7 @@ static bool access_gic_bpr1(struct kvm_vcpu vcpu, struct sys_reg_params p, · 44 unmodified lines
135	p->regval = 0;	135	p->regval = 0;
136		136
137	vgic_get_vmcr(vcpu, &vmcr);	137	vgic_get_vmcr(vcpu, &vmcr);
138	if (!((vmcr.ctlr & ICH_VMCR_CBPR_MASK) >> ICH_VMCR_CBPR_SHIFT)) {	138	if (!vmcr.cbpr) {
139	if (p->is_write) {	139	if (p->is_write) {
140	vmcr.abpr = (p->regval & ICC_BPR1_EL1_MASK) >>	140	vmcr.abpr = (p->regval & ICC_BPR1_EL1_MASK) >>
141	ICC_BPR1_EL1_SHIFT;	141	ICC_BPR1_EL1_SHIFT;

arch/arm64/net/bpf_jit_comp.c+5−2

 #define TMP_REG_1 (MAX_BPF_JIT_REG + 0)
 #define TMP_REG_2 (MAX_BPF_JIT_REG + 1)
 #define TCALL_CNT (MAX_BPF_JIT_REG + 2)
+#define TMP_REG_3 (MAX_BPF_JIT_REG + 3)
 /* Map BPF registers to A64 registers */
 static const int bpf2a64[] = {
 	/* temporary registers for internal BPF JIT */
 	[TMP_REG_1] = A64_R(10),
 	[TMP_REG_2] = A64_R(11),
+	[TMP_REG_3] = A64_R(12),
 	/* tail_call_cnt */
 	[TCALL_CNT] = A64_R(26),
 	/* temporary register for blinding constants */
 	const u8 src = bpf2a64[insn->src_reg];
 	const u8 tmp = bpf2a64[TMP_REG_1];
 	const u8 tmp2 = bpf2a64[TMP_REG_2];
+	const u8 tmp3 = bpf2a64[TMP_REG_3];
 	const s16 off = insn->off;
 	const s32 imm = insn->imm;
 	const int i = insn - ctx->prog->insnsi;
 		emit(A64_PRFM(tmp, PST, L1, STRM), ctx);
 		emit(A64_LDXR(isdw, tmp2, tmp), ctx);
 		emit(A64_ADD(isdw, tmp2, tmp2, src), ctx);
-		emit(A64_STXR(isdw, tmp2, tmp, tmp2), ctx);
+		emit(A64_STXR(isdw, tmp2, tmp, tmp3), ctx);
 		jmp_offset = -3;
 		check_imm19(jmp_offset);
-		emit(A64_CBNZ(0, tmp2, jmp_offset), ctx);
+		emit(A64_CBNZ(0, tmp3, jmp_offset), ctx);
 		break;
 	/* R0 = ntohx(*(size *)(((struct sk_buff *)R6)->data + imm)) */

arch/frv/include/asm/timex.h+6−0

@@ -16,5 +16,11 @@ static inline cycles_t get_cycles(void) · 15 unmodified lines
16	#define vxtime_lock() do {} while (0)	16	#define vxtime_lock() do {} while (0)
17	#define vxtime_unlock() do {} while (0)	17	#define vxtime_unlock() do {} while (0)
18		18
		19	/* This attribute is used in include/linux/jiffies.h alongside with
		20	* __cacheline_aligned_in_smp. It is assumed that __cacheline_aligned_in_smp
		21	* for frv does not contain another section specification.
		22	*/
		23	#define __jiffy_arch_data __attribute__((__section__(".data")))
		24
19	#endif	25	#endif
20		26

arch/frv/mm/elf-fdpic.c+1−1

@@ -75,7 +75,7 @@ unsigned long arch_get_unmapped_area(struct file *filp, unsigned long addr, unsi · 74 unmodified lines
75	addr = PAGE_ALIGN(addr);	75	addr = PAGE_ALIGN(addr);
76	vma = find_vma(current->mm, addr);	76	vma = find_vma(current->mm, addr);
77	if (TASK_SIZE - len >= addr &&	77	if (TASK_SIZE - len >= addr &&
78	(!vma \|\| addr + len <= vma->vm_start))	78	(!vma \|\| addr + len <= vm_start_gap(vma)))
79	goto success;	79	goto success;
80	}	80	}
81		81

arch/hexagon/mm/uaccess.c+2−3

 	long uncleared;
 	while (count > PAGE_SIZE) {
-		uncleared = __copy_to_user_hexagon(dest, &empty_zero_page,
+		uncleared = raw_copy_to_user(dest, &empty_zero_page, PAGE_SIZE);
-						PAGE_SIZE);
 		if (uncleared)
 			return count - (PAGE_SIZE - uncleared);
 		count -= PAGE_SIZE;
 		dest += PAGE_SIZE;
 	}
 	if (count)
-		count = __copy_to_user_hexagon(dest, &empty_zero_page, count);
+		count = raw_copy_to_user(dest, &empty_zero_page, count);
 	return count;
 }

arch/mips/boot/Makefile+5−5

@@ -128,19 +128,19 @@ quiet_cmd_cpp_its_S = ITS $@ · 127 unmodified lines
128	-DADDR_BITS=$(ADDR_BITS) \	128	-DADDR_BITS=$(ADDR_BITS) \
129	-DADDR_CELLS=$(itb_addr_cells)	129	-DADDR_CELLS=$(itb_addr_cells)
130		130
131	$(obj)/vmlinux.its: $(srctree)/arch/mips/$(PLATFORM)/vmlinux.its.S FORCE	131	$(obj)/vmlinux.its: $(srctree)/arch/mips/$(PLATFORM)/vmlinux.its.S $(VMLINUX) FORCE
132	$(call if_changed_dep,cpp_its_S,none,vmlinux.bin)	132	$(call if_changed_dep,cpp_its_S,none,vmlinux.bin)
133		133
134	$(obj)/vmlinux.gz.its: $(srctree)/arch/mips/$(PLATFORM)/vmlinux.its.S FORCE	134	$(obj)/vmlinux.gz.its: $(srctree)/arch/mips/$(PLATFORM)/vmlinux.its.S $(VMLINUX) FORCE
135	$(call if_changed_dep,cpp_its_S,gzip,vmlinux.bin.gz)	135	$(call if_changed_dep,cpp_its_S,gzip,vmlinux.bin.gz)
136		136
137	$(obj)/vmlinux.bz2.its: $(srctree)/arch/mips/$(PLATFORM)/vmlinux.its.S FORCE	137	$(obj)/vmlinux.bz2.its: $(srctree)/arch/mips/$(PLATFORM)/vmlinux.its.S $(VMLINUX) FORCE
138	$(call if_changed_dep,cpp_its_S,bzip2,vmlinux.bin.bz2)	138	$(call if_changed_dep,cpp_its_S,bzip2,vmlinux.bin.bz2)
139		139
140	$(obj)/vmlinux.lzma.its: $(srctree)/arch/mips/$(PLATFORM)/vmlinux.its.S FORCE	140	$(obj)/vmlinux.lzma.its: $(srctree)/arch/mips/$(PLATFORM)/vmlinux.its.S $(VMLINUX) FORCE
141	$(call if_changed_dep,cpp_its_S,lzma,vmlinux.bin.lzma)	141	$(call if_changed_dep,cpp_its_S,lzma,vmlinux.bin.lzma)
142		142
143	$(obj)/vmlinux.lzo.its: $(srctree)/arch/mips/$(PLATFORM)/vmlinux.its.S FORCE	143	$(obj)/vmlinux.lzo.its: $(srctree)/arch/mips/$(PLATFORM)/vmlinux.its.S $(VMLINUX) FORCE
144	$(call if_changed_dep,cpp_its_S,lzo,vmlinux.bin.lzo)	144	$(call if_changed_dep,cpp_its_S,lzo,vmlinux.bin.lzo)
145		145
146	quiet_cmd_itb-image = ITB $@	146	quiet_cmd_itb-image = ITB $@

arch/mips/include/asm/highmem.h+5−0

  * easily, subsequent pte tables have to be allocated in one physical
  * chunk of RAM.
  */
+#ifdef CONFIG_PHYS_ADDR_T_64BIT
+#define LAST_PKMAP 512
+#else
 #define LAST_PKMAP 1024
+#endif
 #define LAST_PKMAP_MASK (LAST_PKMAP-1)
 #define PKMAP_NR(virt)	((virt-PKMAP_BASE) >> PAGE_SHIFT)
 #define PKMAP_ADDR(nr)	(PKMAP_BASE + ((nr) << PAGE_SHIFT))

arch/mips/include/asm/kprobes.h+2−1

@@ -43,7 +43,8 @@ typedef union mips_instruction kprobe_opcode_t; · 42 unmodified lines
43		43
44	#define flush_insn_slot(p) \	44	#define flush_insn_slot(p) \
45	do { \	45	do { \
46	flush_icache_range((unsigned long)p->addr, \	46	if (p->addr) \
		47	flush_icache_range((unsigned long)p->addr, \
47	(unsigned long)p->addr + \	48	(unsigned long)p->addr + \
48	(MAX_INSN_SIZE * sizeof(kprobe_opcode_t))); \	49	(MAX_INSN_SIZE * sizeof(kprobe_opcode_t))); \
49	} while (0)	50	} while (0)

arch/mips/include/asm/pgtable-32.h+6−1

 #define __ARCH_USE_5LEVEL_HACK
 #include <asm-generic/pgtable-nopmd.h>
+#ifdef CONFIG_HIGHMEM
+#include <asm/highmem.h>
+#endif
 extern int temp_tlb_entry;
 /*
 #define VMALLOC_START	  MAP_BASE
-#define PKMAP_BASE		(0xfe000000UL)
+#define PKMAP_END	((FIXADDR_START) & ~((LAST_PKMAP << PAGE_SHIFT)-1))
+#define PKMAP_BASE	(PKMAP_END - PAGE_SIZE * LAST_PKMAP)
 #ifdef CONFIG_HIGHMEM
 # define VMALLOC_END	(PKMAP_BASE-2*PAGE_SIZE)

arch/mips/kernel/branch.c+3−1

 			break;
 		}
 		/* Compact branch: BNEZC || JIALC */
-		if (insn.i_format.rs)
+		if (!insn.i_format.rs) {
+			/* JIALC: set $31/ra */
 			regs->regs[31] = epc + 4;
+		}
 		regs->cp0_epc += 8;
 		break;
 #endif

arch/mips/kernel/ftrace.c+5−19

 #endif
-/*
- * Check if the address is in kernel space
- *
- * Clone core_kernel_text() from kernel/extable.c, but doesn't call
- * init_kernel_text() for Ftrace doesn't trace functions in init sections.
- */
-static inline int in_kernel_space(unsigned long ip)
-{
-	if (ip >= (unsigned long)_stext &&
-	    ip <= (unsigned long)_etext)
-		return 1;
-	return 0;
-}
 #ifdef CONFIG_DYNAMIC_FTRACE
 #define JAL 0x0c000000		/* jump & link: ip --> ra, jump to target */
 	 * If ip is in kernel space, no long call, otherwise, long call is
 	 * needed.
 	 */
-	new = in_kernel_space(ip) ? INSN_NOP : INSN_B_1F;
+	new = core_kernel_text(ip) ? INSN_NOP : INSN_B_1F;
 #ifdef CONFIG_64BIT
 	return ftrace_modify_code(ip, new);
 #else
 	unsigned int new;
 	unsigned long ip = rec->ip;
-	new = in_kernel_space(ip) ? insn_jal_ftrace_caller : insn_la_mcount[0];
+	new = core_kernel_text(ip) ? insn_jal_ftrace_caller : insn_la_mcount[0];
 #ifdef CONFIG_64BIT
 	return ftrace_modify_code(ip, new);
 #else
-	return ftrace_modify_code_2r(ip, new, in_kernel_space(ip) ?
+	return ftrace_modify_code_2r(ip, new, core_kernel_text(ip) ?
 						INSN_NOP : insn_la_mcount[1]);
 #endif
 }
 	 * instruction "lui v1, hi_16bit_of_mcount"(offset is 24), but for
 	 * kernel, move after the instruction "move ra, at"(offset is 16)
 	 */
-	ip = self_ra - (in_kernel_space(self_ra) ? 16 : 24);
+	ip = self_ra - (core_kernel_text(self_ra) ? 16 : 24);
 	/*
 	 * search the text until finding the non-store instruction or "s{d,w}
 	 * entries configured through the tracing/set_graph_function interface.
 	 */
-	insns = in_kernel_space(self_ra) ? 2 : MCOUNT_OFFSET_INSNS + 1;
+	insns = core_kernel_text(self_ra) ? 2 : MCOUNT_OFFSET_INSNS + 1;
 	trace.func = self_ra - (MCOUNT_INSN_SIZE * insns);
 	/* Only trace if the calling function expects to */

arch/mips/kernel/perf_event_mipsxx.c+5−1

 		break;
 	case CPU_P5600:
 	case CPU_P6600:
-	case CPU_I6400:
 		/* 8-bit event numbers */
 		raw_id = config & 0x1ff;
 		base_id = raw_id & 0xff;
 		raw_event.range = P;
 #endif
 		break;
+	case CPU_I6400:
+		/* 8-bit event numbers */
+		base_id = config & 0xff;
+		raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
+		break;
 	case CPU_1004K:
 		if (IS_BOTH_COUNTERS_1004K_EVENT(base_id))
 			raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;

arch/mips/kernel/process.c+0−1

@@ -120,7 +120,6 @@ int copy_thread_tls(unsigned long clone_flags, unsigned long usp, · 119 unmodified lines
120	struct thread_info *ti = task_thread_info(p);	120	struct thread_info *ti = task_thread_info(p);
121	struct pt_regs childregs, regs = current_pt_regs();	121	struct pt_regs childregs, regs = current_pt_regs();
122	unsigned long childksp;	122	unsigned long childksp;
123	p->set_child_tid = p->clear_child_tid = NULL;
124		123
125	childksp = (unsigned long)task_stack_page(p) + THREAD_SIZE - 32;	124	childksp = (unsigned long)task_stack_page(p) + THREAD_SIZE - 32;
126		125

arch/mips/mm/mmap.c+1−1

@@ -93,7 +93,7 @@ static unsigned long arch_get_unmapped_area_common(struct file *filp, · 92 unmodified lines
93		93
94	vma = find_vma(mm, addr);	94	vma = find_vma(mm, addr);
95	if (TASK_SIZE - len >= addr &&	95	if (TASK_SIZE - len >= addr &&
96	(!vma \|\| addr + len <= vma->vm_start))	96	(!vma \|\| addr + len <= vm_start_gap(vma)))
97	return addr;	97	return addr;
98	}	98	}
99		99

arch/mips/mm/pgtable-32.c+3−3

@@ -51,15 +51,15 @@ void __init pagetable_init(void) · 50 unmodified lines
51	/*	51	/*
52	* Fixed mappings:	52	* Fixed mappings:
53	*/	53	*/
54	vaddr = __fix_to_virt(__end_of_fixed_addresses - 1) & PMD_MASK;	54	vaddr = __fix_to_virt(__end_of_fixed_addresses - 1);
55	fixrange_init(vaddr, vaddr + FIXADDR_SIZE, pgd_base);	55	fixrange_init(vaddr & PMD_MASK, vaddr + FIXADDR_SIZE, pgd_base);
56		56
57	#ifdef CONFIG_HIGHMEM	57	#ifdef CONFIG_HIGHMEM
58	/*	58	/*
59	* Permanent kmaps:	59	* Permanent kmaps:
60	*/	60	*/
61	vaddr = PKMAP_BASE;	61	vaddr = PKMAP_BASE;
62	fixrange_init(vaddr, vaddr + PAGE_SIZE*LAST_PKMAP, pgd_base);	62	fixrange_init(vaddr & PMD_MASK, vaddr + PAGE_SIZE*LAST_PKMAP, pgd_base);
63		63
64	pgd = swapper_pg_dir + __pgd_offset(vaddr);	64	pgd = swapper_pg_dir + __pgd_offset(vaddr);
65	pud = pud_offset(pgd, vaddr);	65	pud = pud_offset(pgd, vaddr);

arch/openrisc/kernel/process.c+0−2

@@ -167,8 +167,6 @@ copy_thread(unsigned long clone_flags, unsigned long usp, · 166 unmodified lines
167		167
168	top_of_kernel_stack = sp;	168	top_of_kernel_stack = sp;
169		169
170	p->set_child_tid = p->clear_child_tid = NULL;
171
172	/* Locate userspace context on stack... */	170	/* Locate userspace context on stack... */
173	sp -= STACK_FRAME_OVERHEAD; /* redzone */	171	sp -= STACK_FRAME_OVERHEAD; /* redzone */
174	sp -= sizeof(struct pt_regs);	172	sp -= sizeof(struct pt_regs);

arch/parisc/kernel/sys_parisc.c+9−6

@@ -90,7 +90,7 @@ unsigned long arch_get_unmapped_area(struct file *filp, unsigned long addr, · 89 unmodified lines
90	unsigned long len, unsigned long pgoff, unsigned long flags)	90	unsigned long len, unsigned long pgoff, unsigned long flags)
91	{	91	{
92	struct mm_struct *mm = current->mm;	92	struct mm_struct *mm = current->mm;
93	struct vm_area_struct *vma;	93	struct vm_area_struct vma, prev;
94	unsigned long task_size = TASK_SIZE;	94	unsigned long task_size = TASK_SIZE;
95	int do_color_align, last_mmap;	95	int do_color_align, last_mmap;
96	struct vm_unmapped_area_info info;	96	struct vm_unmapped_area_info info;
@@ -117,9 +117,10 @@ unsigned long arch_get_unmapped_area(struct file *filp, unsigned long addr, · 20 unmodified lines
117	else	117	else
118	addr = PAGE_ALIGN(addr);	118	addr = PAGE_ALIGN(addr);
119		119
120	vma = find_vma(mm, addr);	120	vma = find_vma_prev(mm, addr, &prev);
121	if (task_size - len >= addr &&	121	if (task_size - len >= addr &&
122	(!vma \|\| addr + len <= vma->vm_start))	122	(!vma \|\| addr + len <= vm_start_gap(vma)) &&
		123	(!prev \|\| addr >= vm_end_gap(prev)))
123	goto found_addr;	124	goto found_addr;
124	}	125	}
125		126
@@ -143,7 +144,7 @@ arch_get_unmapped_area_topdown(struct file *filp, const unsigned long addr0, · 17 unmodified lines
143	const unsigned long len, const unsigned long pgoff,	144	const unsigned long len, const unsigned long pgoff,
144	const unsigned long flags)	145	const unsigned long flags)
145	{	146	{
146	struct vm_area_struct *vma;	147	struct vm_area_struct vma, prev;
147	struct mm_struct *mm = current->mm;	148	struct mm_struct *mm = current->mm;
148	unsigned long addr = addr0;	149	unsigned long addr = addr0;
149	int do_color_align, last_mmap;	150	int do_color_align, last_mmap;
@@ -177,9 +178,11 @@ arch_get_unmapped_area_topdown(struct file *filp, const unsigned long addr0, · 27 unmodified lines
177	addr = COLOR_ALIGN(addr, last_mmap, pgoff);	178	addr = COLOR_ALIGN(addr, last_mmap, pgoff);
178	else	179	else
179	addr = PAGE_ALIGN(addr);	180	addr = PAGE_ALIGN(addr);
180	vma = find_vma(mm, addr);	181
		182	vma = find_vma_prev(mm, addr, &prev);
181	if (TASK_SIZE - len >= addr &&	183	if (TASK_SIZE - len >= addr &&
182	(!vma \|\| addr + len <= vma->vm_start))	184	(!vma \|\| addr + len <= vm_start_gap(vma)) &&
		185	(!prev \|\| addr >= vm_end_gap(prev)))
183	goto found_addr;	186	goto found_addr;
184	}	187	}
185		188

arch/powerpc/Kconfig+0−21

@@ -380,22 +380,6 @@ source "arch/powerpc/platforms/Kconfig" · 379 unmodified lines
380		380
381	menu "Kernel options"	381	menu "Kernel options"
382		382
383	config PPC_DT_CPU_FTRS
384	bool "Device-tree based CPU feature discovery & setup"
385	depends on PPC_BOOK3S_64
386	default n
387	help
388	This enables code to use a new device tree binding for describing CPU
389	compatibility and features. Saying Y here will attempt to use the new
390	binding if the firmware provides it. Currently only the skiboot
391	firmware provides this binding.
392	If you're not sure say Y.
393
394	config PPC_CPUFEATURES_ENABLE_UNKNOWN
395	bool "cpufeatures pass through unknown features to guest/userspace"
396	depends on PPC_DT_CPU_FTRS
397	default y
398
399	config HIGHMEM	383	config HIGHMEM
400	bool "High memory support"	384	bool "High memory support"
401	depends on PPC32	385	depends on PPC32
@@ -1215,11 +1199,6 @@ source "arch/powerpc/Kconfig.debug" · 813 unmodified lines
1215		1199
1216	source "security/Kconfig"	1200	source "security/Kconfig"
1217		1201
1218	config KEYS_COMPAT
1219	bool
1220	depends on COMPAT && KEYS
1221	default y
1222
1223	source "crypto/Kconfig"	1202	source "crypto/Kconfig"
1224		1203
1225	config PPC_LIB_RHEAP	1204	config PPC_LIB_RHEAP

arch/powerpc/include/asm/book3s/64/hash-4k.h+1−1

@@ -8,7 +8,7 @@ · 7 unmodified lines
8	#define H_PTE_INDEX_SIZE 9	8	#define H_PTE_INDEX_SIZE 9
9	#define H_PMD_INDEX_SIZE 7	9	#define H_PMD_INDEX_SIZE 7
10	#define H_PUD_INDEX_SIZE 9	10	#define H_PUD_INDEX_SIZE 9
11	#define H_PGD_INDEX_SIZE 12	11	#define H_PGD_INDEX_SIZE 9
12		12
13	#ifndef __ASSEMBLY__	13	#ifndef __ASSEMBLY__
14	#define H_PTE_TABLE_SIZE (sizeof(pte_t) << H_PTE_INDEX_SIZE)	14	#define H_PTE_TABLE_SIZE (sizeof(pte_t) << H_PTE_INDEX_SIZE)

arch/powerpc/include/asm/bug.h+1−1

@@ -104,7 +104,7 @@ · 103 unmodified lines
104	"1: "PPC_TLNEI" %4,0\n" \	104	"1: "PPC_TLNEI" %4,0\n" \
105	_EMIT_BUG_ENTRY \	105	_EMIT_BUG_ENTRY \
106	: : "i" (__FILE__), "i" (__LINE__), \	106	: : "i" (__FILE__), "i" (__LINE__), \
107	"i" (BUGFLAG_TAINT(TAINT_WARN)), \	107	"i" (BUGFLAG_WARNING\|BUGFLAG_TAINT(TAINT_WARN)),\
108	"i" (sizeof(struct bug_entry)), \	108	"i" (sizeof(struct bug_entry)), \
109	"r" (__ret_warn_on)); \	109	"r" (__ret_warn_on)); \
110	} \	110	} \

arch/powerpc/include/asm/cputable.h+1−2

 #define CPU_FTR_DAWR			LONG_ASM_CONST(0x0400000000000000)
 #define CPU_FTR_DABRX			LONG_ASM_CONST(0x0800000000000000)
 #define CPU_FTR_PMAO_BUG		LONG_ASM_CONST(0x1000000000000000)
-#define CPU_FTR_SUBCORE			LONG_ASM_CONST(0x2000000000000000)
 #define CPU_FTR_POWER9_DD1		LONG_ASM_CONST(0x4000000000000000)
 #ifndef __ASSEMBLY__
 	    CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
 	    CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
 	    CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \
-	    CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP | CPU_FTR_SUBCORE)
+	    CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP)
 #define CPU_FTRS_POWER8E (CPU_FTRS_POWER8 | CPU_FTR_PMAO_BUG)
 #define CPU_FTRS_POWER8_DD1 (CPU_FTRS_POWER8 & ~CPU_FTR_DBELL)
 #define CPU_FTRS_POWER9 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

arch/powerpc/include/asm/processor.h+12−13

 #define TASK_SIZE_128TB (0x0000800000000000UL)
 #define TASK_SIZE_512TB (0x0002000000000000UL)
-#ifdef CONFIG_PPC_BOOK3S_64
+/*
+ * For now 512TB is only supported with book3s and 64K linux page size.
+ */
+#if defined(CONFIG_PPC_BOOK3S_64) && defined(CONFIG_PPC_64K_PAGES)
 /*
  * Max value currently used:
  */
-#define TASK_SIZE_USER64	TASK_SIZE_512TB
+#define TASK_SIZE_USER64		TASK_SIZE_512TB
+#define DEFAULT_MAP_WINDOW_USER64	TASK_SIZE_128TB
 #else
-#define TASK_SIZE_USER64	TASK_SIZE_64TB
+#define TASK_SIZE_USER64		TASK_SIZE_64TB
+#define DEFAULT_MAP_WINDOW_USER64	TASK_SIZE_64TB
 #endif
 /*
  * space during mmap's.
  */
 #define TASK_UNMAPPED_BASE_USER32 (PAGE_ALIGN(TASK_SIZE_USER32 / 4))
-#define TASK_UNMAPPED_BASE_USER64 (PAGE_ALIGN(TASK_SIZE_128TB / 4))
+#define TASK_UNMAPPED_BASE_USER64 (PAGE_ALIGN(DEFAULT_MAP_WINDOW_USER64 / 4))
 #define TASK_UNMAPPED_BASE ((is_32bit_task()) ? \
 		TASK_UNMAPPED_BASE_USER32 : TASK_UNMAPPED_BASE_USER64 )
  * with 128TB and conditionally enable upto 512TB
  */
 #ifdef CONFIG_PPC_BOOK3S_64
-#define DEFAULT_MAP_WINDOW	((is_32bit_task()) ? \
+#define DEFAULT_MAP_WINDOW	((is_32bit_task()) ?			\
-				 TASK_SIZE_USER32 : TASK_SIZE_128TB)
+				 TASK_SIZE_USER32 : DEFAULT_MAP_WINDOW_USER64)
 #else
 #define DEFAULT_MAP_WINDOW	TASK_SIZE
 #endif
 #ifdef __powerpc64__
-#ifdef CONFIG_PPC_BOOK3S_64
+#define STACK_TOP_USER64 DEFAULT_MAP_WINDOW_USER64
-/* Limit stack to 128TB */
-#define STACK_TOP_USER64 TASK_SIZE_128TB
-#else
-#define STACK_TOP_USER64 TASK_SIZE_USER64
-#endif
 #define STACK_TOP_USER32 TASK_SIZE_USER32
 #define STACK_TOP (is_32bit_task() ? \

arch/powerpc/include/asm/topology.h+14−0

@@ -44,8 +44,22 @@ extern void __init dump_numa_cpu_topology(void); · 43 unmodified lines
44	extern int sysfs_add_device_to_node(struct device *dev, int nid);	44	extern int sysfs_add_device_to_node(struct device *dev, int nid);
45	extern void sysfs_remove_device_from_node(struct device *dev, int nid);	45	extern void sysfs_remove_device_from_node(struct device *dev, int nid);
46		46
		47	static inline int early_cpu_to_node(int cpu)
		48	{
		49	int nid;
		50
		51	nid = numa_cpu_lookup_table[cpu];
		52
		53	/*
		54	* Fall back to node 0 if nid is unset (it should be, except bugs).
		55	* This allows callers to safely do NODE_DATA(early_cpu_to_node(cpu)).
		56	*/
		57	return (nid < 0) ? 0 : nid;
		58	}
47	#else	59	#else
48		60
		61	static inline int early_cpu_to_node(int cpu) { return 0; }
		62
49	static inline void dump_numa_cpu_topology(void) {}	63	static inline void dump_numa_cpu_topology(void) {}
50		64
51	static inline int sysfs_add_device_to_node(struct device *dev, int nid)	65	static inline int sysfs_add_device_to_node(struct device *dev, int nid)

arch/powerpc/include/asm/xive.h+7−5

@@ -94,11 +94,13 @@ struct xive_q { · 93 unmodified lines
94	* store at 0 and some ESBs support doing a trigger via a	94	* store at 0 and some ESBs support doing a trigger via a
95	* separate trigger page.	95	* separate trigger page.
96	*/	96	*/
97	#define XIVE_ESB_GET 0x800	97	#define XIVE_ESB_STORE_EOI 0x400 /* Store */
98	#define XIVE_ESB_SET_PQ_00 0xc00	98	#define XIVE_ESB_LOAD_EOI 0x000 /* Load */
99	#define XIVE_ESB_SET_PQ_01 0xd00	99	#define XIVE_ESB_GET 0x800 /* Load */
100	#define XIVE_ESB_SET_PQ_10 0xe00	100	#define XIVE_ESB_SET_PQ_00 0xc00 /* Load */
101	#define XIVE_ESB_SET_PQ_11 0xf00	101	#define XIVE_ESB_SET_PQ_01 0xd00 /* Load */
		102	#define XIVE_ESB_SET_PQ_10 0xe00 /* Load */
		103	#define XIVE_ESB_SET_PQ_11 0xf00 /* Load */
102		104
103	#define XIVE_ESB_VAL_P 0x2	105	#define XIVE_ESB_VAL_P 0x2
104	#define XIVE_ESB_VAL_Q 0x1	106	#define XIVE_ESB_VAL_Q 0x1

arch/powerpc/kernel/dt_cpu_ftrs.c+48−10

@@ -8,6 +8,7 @@ · 7 unmodified lines
8	#include <linux/export.h>	8	#include <linux/export.h>
9	#include <linux/init.h>	9	#include <linux/init.h>
10	#include <linux/jump_label.h>	10	#include <linux/jump_label.h>
		11	#include <linux/libfdt.h>
11	#include <linux/memblock.h>	12	#include <linux/memblock.h>
12	#include <linux/printk.h>	13	#include <linux/printk.h>
13	#include <linux/sched.h>	14	#include <linux/sched.h>
@@ -642,7 +643,6 @@ static struct dt_cpu_feature_match __initdata · 628 unmodified lines
642	{"processor-control-facility", feat_enable_dbell, CPU_FTR_DBELL},	643	{"processor-control-facility", feat_enable_dbell, CPU_FTR_DBELL},
643	{"processor-control-facility-v3", feat_enable_dbell, CPU_FTR_DBELL},	644	{"processor-control-facility-v3", feat_enable_dbell, CPU_FTR_DBELL},
644	{"processor-utilization-of-resources-register", feat_enable_purr, 0},	645	{"processor-utilization-of-resources-register", feat_enable_purr, 0},
645	{"subcore", feat_enable, CPU_FTR_SUBCORE},
646	{"no-execute", feat_enable, 0},	646	{"no-execute", feat_enable, 0},
647	{"strong-access-ordering", feat_enable, CPU_FTR_SAO},	647	{"strong-access-ordering", feat_enable, CPU_FTR_SAO},
648	{"cache-inhibited-large-page", feat_enable_large_ci, 0},	648	{"cache-inhibited-large-page", feat_enable_large_ci, 0},
@@ -671,12 +671,24 @@ static struct dt_cpu_feature_match __initdata · 22 unmodified lines
671	{"wait-v3", feat_enable, 0},	671	{"wait-v3", feat_enable, 0},
672	};	672	};
673		673
674	/* XXX: how to configure this? Default + boot time? */	674	static bool __initdata using_dt_cpu_ftrs;
675	#ifdef CONFIG_PPC_CPUFEATURES_ENABLE_UNKNOWN	675	static bool __initdata enable_unknown = true;
676	#define CPU_FEATURE_ENABLE_UNKNOWN 1	676
677	#else	677	static int __init dt_cpu_ftrs_parse(char *str)
678	#define CPU_FEATURE_ENABLE_UNKNOWN 0	678	{
679	#endif	679	if (!str)
		680	return 0;
		681
		682	if (!strcmp(str, "off"))
		683	using_dt_cpu_ftrs = false;
		684	else if (!strcmp(str, "known"))
		685	enable_unknown = false;
		686	else
		687	return 1;
		688
		689	return 0;
		690	}
		691	early_param("dt_cpu_ftrs", dt_cpu_ftrs_parse);
680		692
681	static void __init cpufeatures_setup_start(u32 isa)	693	static void __init cpufeatures_setup_start(u32 isa)
682	{	694	{
@@ -707,7 +719,7 @@ static bool __init cpufeatures_process_feature(struct dt_cpu_feature *f) · 24 unmodified lines
707	}	719	}
708	}	720	}
709		721
710	if (!known && CPU_FEATURE_ENABLE_UNKNOWN) {	722	if (!known && enable_unknown) {
711	if (!feat_try_enable_unknown(f)) {	723	if (!feat_try_enable_unknown(f)) {
712	pr_info("not enabling: %s (unknown and unsupported by kernel)\n",	724	pr_info("not enabling: %s (unknown and unsupported by kernel)\n",
713	f->name);	725	f->name);
@@ -756,6 +768,26 @@ static void __init cpufeatures_setup_finished(void) · 42 unmodified lines
756	cur_cpu_spec->cpu_features, cur_cpu_spec->mmu_features);	768	cur_cpu_spec->cpu_features, cur_cpu_spec->mmu_features);
757	}	769	}
758		770
		771	static int __init disabled_on_cmdline(void)
		772	{
		773	unsigned long root, chosen;
		774	const char *p;
		775
		776	root = of_get_flat_dt_root();
		777	chosen = of_get_flat_dt_subnode_by_name(root, "chosen");
		778	if (chosen == -FDT_ERR_NOTFOUND)
		779	return false;
		780
		781	p = of_get_flat_dt_prop(chosen, "bootargs", NULL);
		782	if (!p)
		783	return false;
		784
		785	if (strstr(p, "dt_cpu_ftrs=off"))
		786	return true;
		787
		788	return false;
		789	}
		790
759	static int __init fdt_find_cpu_features(unsigned long node, const char *uname,	791	static int __init fdt_find_cpu_features(unsigned long node, const char *uname,
760	int depth, void *data)	792	int depth, void *data)
761	{	793	{
@@ -766,8 +798,6 @@ static int __init fdt_find_cpu_features(unsigned long node, const char *uname, · 4 unmodified lines
766	return 0;	798	return 0;
767	}	799	}
768		800
769	static bool __initdata using_dt_cpu_ftrs = false;
770
771	bool __init dt_cpu_ftrs_in_use(void)	801	bool __init dt_cpu_ftrs_in_use(void)
772	{	802	{
773	return using_dt_cpu_ftrs;	803	return using_dt_cpu_ftrs;
@@ -775,6 +805,8 @@ bool __init dt_cpu_ftrs_in_use(void) · 1 unmodified line
775		805
776	bool __init dt_cpu_ftrs_init(void *fdt)	806	bool __init dt_cpu_ftrs_init(void *fdt)
777	{	807	{
		808	using_dt_cpu_ftrs = false;
		809
778	/* Setup and verify the FDT, if it fails we just bail */	810	/* Setup and verify the FDT, if it fails we just bail */
779	if (!early_init_dt_verify(fdt))	811	if (!early_init_dt_verify(fdt))
780	return false;	812	return false;
@@ -782,6 +814,9 @@ bool __init dt_cpu_ftrs_init(void *fdt) · 1 unmodified line
782	if (!of_scan_flat_dt(fdt_find_cpu_features, NULL))	814	if (!of_scan_flat_dt(fdt_find_cpu_features, NULL))
783	return false;	815	return false;
784		816
		817	if (disabled_on_cmdline())
		818	return false;
		819
785	cpufeatures_setup_cpu();	820	cpufeatures_setup_cpu();
786		821
787	using_dt_cpu_ftrs = true;	822	using_dt_cpu_ftrs = true;
@@ -1027,5 +1062,8 @@ static int __init dt_cpu_ftrs_scan_callback(unsigned long node, const char · 239 unmodified lines
1027		1062
1028	void __init dt_cpu_ftrs_scan(void)	1063	void __init dt_cpu_ftrs_scan(void)
1029	{	1064	{
		1065	if (!using_dt_cpu_ftrs)
		1066	return;
		1067
1030	of_scan_flat_dt(dt_cpu_ftrs_scan_callback, NULL);	1068	of_scan_flat_dt(dt_cpu_ftrs_scan_callback, NULL);
1031	}	1069	}

arch/powerpc/kernel/process.c+3−0

 #ifdef CONFIG_VSX
 	current->thread.used_vsr = 0;
 #endif
+	current->thread.load_fp = 0;
 	memset(&current->thread.fp_state, 0, sizeof(current->thread.fp_state));
 	current->thread.fp_save_area = NULL;
 #ifdef CONFIG_ALTIVEC
 	current->thread.vr_save_area = NULL;
 	current->thread.vrsave = 0;
 	current->thread.used_vr = 0;
+	current->thread.load_vec = 0;
 #endif /* CONFIG_ALTIVEC */
 #ifdef CONFIG_SPE
 	memset(current->thread.evr, 0, sizeof(current->thread.evr));
 	current->thread.tm_tfhar = 0;
 	current->thread.tm_texasr = 0;
 	current->thread.tm_tfiar = 0;
+	current->thread.load_tm = 0;
 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
 }
 EXPORT_SYMBOL(start_thread);

arch/powerpc/kernel/setup-common.c+1−1

@@ -928,7 +928,7 @@ void __init setup_arch(char **cmdline_p) · 927 unmodified lines
928		928
929	#ifdef CONFIG_PPC_MM_SLICES	929	#ifdef CONFIG_PPC_MM_SLICES
930	#ifdef CONFIG_PPC64	930	#ifdef CONFIG_PPC64
931	init_mm.context.addr_limit = TASK_SIZE_128TB;	931	init_mm.context.addr_limit = DEFAULT_MAP_WINDOW_USER64;
932	#else	932	#else
933	#error "context.addr_limit not initialized."	933	#error "context.addr_limit not initialized."
934	#endif	934	#endif

arch/powerpc/kernel/setup_64.c+2−2

@@ -661,7 +661,7 @@ void __init emergency_stack_init(void) · 660 unmodified lines
661		661
662	static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size, size_t align)	662	static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size, size_t align)
663	{	663	{
664	return __alloc_bootmem_node(NODE_DATA(cpu_to_node(cpu)), size, align,	664	return __alloc_bootmem_node(NODE_DATA(early_cpu_to_node(cpu)), size, align,
665	__pa(MAX_DMA_ADDRESS));	665	__pa(MAX_DMA_ADDRESS));
666	}	666	}
667		667
@@ -672,7 +672,7 @@ static void __init pcpu_fc_free(void *ptr, size_t size) · 4 unmodified lines
672		672
673	static int pcpu_cpu_distance(unsigned int from, unsigned int to)	673	static int pcpu_cpu_distance(unsigned int from, unsigned int to)
674	{	674	{
675	if (cpu_to_node(from) == cpu_to_node(to))	675	if (early_cpu_to_node(from) == early_cpu_to_node(to))
676	return LOCAL_DISTANCE;	676	return LOCAL_DISTANCE;
677	else	677	else
678	return REMOTE_DISTANCE;	678	return REMOTE_DISTANCE;

arch/powerpc/kvm/book3s_xive_template.c+2−2

@@ -69,7 +69,7 @@ static void GLUE(X_PFX,source_eoi)(u32 hw_irq, struct xive_irq_data *xd) · 68 unmodified lines
69	{	69	{
70	/* If the XIVE supports the new "store EOI facility, use it */	70	/* If the XIVE supports the new "store EOI facility, use it */
71	if (xd->flags & XIVE_IRQ_FLAG_STORE_EOI)	71	if (xd->flags & XIVE_IRQ_FLAG_STORE_EOI)
72	__x_writeq(0, __x_eoi_page(xd));	72	__x_writeq(0, __x_eoi_page(xd) + XIVE_ESB_STORE_EOI);
73	else if (hw_irq && xd->flags & XIVE_IRQ_FLAG_EOI_FW) {	73	else if (hw_irq && xd->flags & XIVE_IRQ_FLAG_EOI_FW) {
74	opal_int_eoi(hw_irq);	74	opal_int_eoi(hw_irq);
75	} else {	75	} else {
@@ -89,7 +89,7 @@ static void GLUE(X_PFX,source_eoi)(u32 hw_irq, struct xive_irq_data *xd) · 13 unmodified lines
89	* properly.	89	* properly.
90	*/	90	*/
91	if (xd->flags & XIVE_IRQ_FLAG_LSI)	91	if (xd->flags & XIVE_IRQ_FLAG_LSI)
92	__x_readq(__x_eoi_page(xd));	92	__x_readq(__x_eoi_page(xd) + XIVE_ESB_LOAD_EOI);
93	else {	93	else {
94	eoi_val = GLUE(X_PFX,esb_load)(xd, XIVE_ESB_SET_PQ_00);	94	eoi_val = GLUE(X_PFX,esb_load)(xd, XIVE_ESB_SET_PQ_00);
95		95

arch/powerpc/mm/hugetlbpage-radix.c+1−1

@@ -68,7 +68,7 @@ radix__hugetlb_get_unmapped_area(struct file *file, unsigned long addr, · 67 unmodified lines
68	addr = ALIGN(addr, huge_page_size(h));	68	addr = ALIGN(addr, huge_page_size(h));
69	vma = find_vma(mm, addr);	69	vma = find_vma(mm, addr);
70	if (mm->task_size - len >= addr &&	70	if (mm->task_size - len >= addr &&
71	(!vma \|\| addr + len <= vma->vm_start))	71	(!vma \|\| addr + len <= vm_start_gap(vma)))
72	return addr;	72	return addr;
73	}	73	}
74	/*	74	/*

arch/powerpc/mm/mmap.c+2−2

@@ -112,7 +112,7 @@ radix__arch_get_unmapped_area(struct file *filp, unsigned long addr, · 111 unmodified lines
112	addr = PAGE_ALIGN(addr);	112	addr = PAGE_ALIGN(addr);
113	vma = find_vma(mm, addr);	113	vma = find_vma(mm, addr);
114	if (mm->task_size - len >= addr && addr >= mmap_min_addr &&	114	if (mm->task_size - len >= addr && addr >= mmap_min_addr &&
115	(!vma \|\| addr + len <= vma->vm_start))	115	(!vma \|\| addr + len <= vm_start_gap(vma)))
116	return addr;	116	return addr;
117	}	117	}
118		118
@@ -157,7 +157,7 @@ radix__arch_get_unmapped_area_topdown(struct file *filp, · 38 unmodified lines
157	addr = PAGE_ALIGN(addr);	157	addr = PAGE_ALIGN(addr);
158	vma = find_vma(mm, addr);	158	vma = find_vma(mm, addr);
159	if (mm->task_size - len >= addr && addr >= mmap_min_addr &&	159	if (mm->task_size - len >= addr && addr >= mmap_min_addr &&
160	(!vma \|\| addr + len <= vma->vm_start))	160	(!vma \|\| addr + len <= vm_start_gap(vma)))
161	return addr;	161	return addr;
162	}	162	}
163		163

arch/powerpc/mm/mmu_context_book3s64.c+1−1

@@ -99,7 +99,7 @@ static int hash__init_new_context(struct mm_struct *mm) · 98 unmodified lines
99	* mm->context.addr_limit. Default to max task size so that we copy the	99	* mm->context.addr_limit. Default to max task size so that we copy the
100	* default values to paca which will help us to handle slb miss early.	100	* default values to paca which will help us to handle slb miss early.
101	*/	101	*/
102	mm->context.addr_limit = TASK_SIZE_128TB;	102	mm->context.addr_limit = DEFAULT_MAP_WINDOW_USER64;
103		103
104	/*	104	/*
105	* The old code would re-promote on fork, we don't do that when using	105	* The old code would re-promote on fork, we don't do that when using

arch/powerpc/mm/slice.c+1−1

@@ -99,7 +99,7 @@ static int slice_area_is_free(struct mm_struct *mm, unsigned long addr, · 98 unmodified lines
99	if ((mm->task_size - len) < addr)	99	if ((mm->task_size - len) < addr)
100	return 0;	100	return 0;
101	vma = find_vma(mm, addr);	101	vma = find_vma(mm, addr);
102	return (!vma \|\| (addr + len) <= vma->vm_start);	102	return (!vma \|\| (addr + len) <= vm_start_gap(vma));
103	}	103	}
104		104
105	static int slice_low_has_vma(struct mm_struct *mm, unsigned long slice)	105	static int slice_low_has_vma(struct mm_struct *mm, unsigned long slice)

arch/powerpc/perf/power9-pmu.c+2−2

arch/powerpc/platforms/Kconfig+11−0

@@ -59,6 +59,17 @@ config PPC_OF_BOOT_TRAMPOLINE · 58 unmodified lines
59		59
60	In case of doubt, say Y	60	In case of doubt, say Y
61		61
		62	config PPC_DT_CPU_FTRS
		63	bool "Device-tree based CPU feature discovery & setup"
		64	depends on PPC_BOOK3S_64
		65	default y
		66	help
		67	This enables code to use a new device tree binding for describing CPU
		68	compatibility and features. Saying Y here will attempt to use the new
		69	binding if the firmware provides it. Currently only the skiboot
		70	firmware provides this binding.
		71	If you're not sure say Y.
		72
62	config UDBG_RTAS_CONSOLE	73	config UDBG_RTAS_CONSOLE
63	bool "RTAS based debug console"	74	bool "RTAS based debug console"
64	depends on PPC_RTAS	75	depends on PPC_RTAS

arch/powerpc/platforms/cell/spufs/coredump.c+2−0

@@ -175,6 +175,8 @@ static int spufs_arch_write_note(struct spu_context *ctx, int i, · 174 unmodified lines
175	skip = roundup(cprm->pos - total + sz, 4) - cprm->pos;	175	skip = roundup(cprm->pos - total + sz, 4) - cprm->pos;
176	if (!dump_skip(cprm, skip))	176	if (!dump_skip(cprm, skip))
177	goto Eio;	177	goto Eio;
		178
		179	rc = 0;
178	out:	180	out:
179	free_page((unsigned long)buf);	181	free_page((unsigned long)buf);
180	return rc;	182	return rc;

arch/powerpc/platforms/powernv/npu-dma.c+2−1

@@ -75,7 +75,8 @@ struct pci_dev pnv_pci_get_npu_dev(struct pci_dev gpdev, int index) · 74 unmodified lines
75	if (WARN_ON(!gpdev))	75	if (WARN_ON(!gpdev))
76	return NULL;	76	return NULL;
77		77
78	if (WARN_ON(!gpdev->dev.of_node))	78	/* Not all PCI devices have device-tree nodes */
		79	if (!gpdev->dev.of_node)
79	return NULL;	80	return NULL;
80		81
81	/* Get assoicated PCI device */	82	/* Get assoicated PCI device */

arch/powerpc/platforms/powernv/subcore.c+7−1

 static int subcore_init(void)
 {
-	if (!cpu_has_feature(CPU_FTR_SUBCORE))
+	unsigned pvr_ver;
+	pvr_ver = PVR_VER(mfspr(SPRN_PVR));
+	if (pvr_ver != PVR_POWER8 &&
+	    pvr_ver != PVR_POWER8E &&
+	    pvr_ver != PVR_POWER8NVL)
 		return 0;
 	/*

arch/powerpc/platforms/pseries/hotplug-memory.c+2−0

 	for (i = 0; i < num_lmbs; i++) {
 		lmbs[i].base_addr = be64_to_cpu(lmbs[i].base_addr);
 		lmbs[i].drc_index = be32_to_cpu(lmbs[i].drc_index);
+		lmbs[i].aa_index = be32_to_cpu(lmbs[i].aa_index);
 		lmbs[i].flags = be32_to_cpu(lmbs[i].flags);
 	}
 	for (i = 0; i < num_lmbs; i++) {
 		lmbs[i].base_addr = cpu_to_be64(lmbs[i].base_addr);
 		lmbs[i].drc_index = cpu_to_be32(lmbs[i].drc_index);
+		lmbs[i].aa_index = cpu_to_be32(lmbs[i].aa_index);
 		lmbs[i].flags = cpu_to_be32(lmbs[i].flags);
 	}

arch/powerpc/sysdev/simple_gpio.c+2−1

@@ -75,7 +75,8 @@ static int u8_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) · 74 unmodified lines
75		75
76	static void u8_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)	76	static void u8_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
77	{	77	{
78	struct u8_gpio_chip *u8_gc = gpiochip_get_data(&mm_gc->gc);	78	struct u8_gpio_chip *u8_gc =
		79	container_of(mm_gc, struct u8_gpio_chip, mm_gc);
79		80
80	u8_gc->data = in_8(mm_gc->regs);	81	u8_gc->data = in_8(mm_gc->regs);
81	}	82	}

arch/powerpc/sysdev/xive/common.c+1−1

@@ -297,7 +297,7 @@ void xive_do_source_eoi(u32 hw_irq, struct xive_irq_data *xd) · 296 unmodified lines
297	{	297	{
298	/* If the XIVE supports the new "store EOI facility, use it */	298	/* If the XIVE supports the new "store EOI facility, use it */
299	if (xd->flags & XIVE_IRQ_FLAG_STORE_EOI)	299	if (xd->flags & XIVE_IRQ_FLAG_STORE_EOI)
300	out_be64(xd->eoi_mmio, 0);	300	out_be64(xd->eoi_mmio + XIVE_ESB_STORE_EOI, 0);
301	else if (hw_irq && xd->flags & XIVE_IRQ_FLAG_EOI_FW) {	301	else if (hw_irq && xd->flags & XIVE_IRQ_FLAG_EOI_FW) {
302	/*	302	/*
303	* The FW told us to call it. This happens for some	303	* The FW told us to call it. This happens for some

arch/s390/Kconfig+0−3

@@ -363,9 +363,6 @@ config COMPAT · 362 unmodified lines
363	config SYSVIPC_COMPAT	363	config SYSVIPC_COMPAT
364	def_bool y if COMPAT && SYSVIPC	364	def_bool y if COMPAT && SYSVIPC
365		365
366	config KEYS_COMPAT
367	def_bool y if COMPAT && KEYS
368
369	config SMP	366	config SMP
370	def_bool y	367	def_bool y
371	prompt "Symmetric multi-processing support"	368	prompt "Symmetric multi-processing support"

arch/s390/configs/default_defconfig+33−6

 CONFIG_SCHED_AUTOGROUP=y
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_EXPERT=y
+# CONFIG_SYSFS_SYSCALL is not set
 CONFIG_BPF_SYSCALL=y
 CONFIG_USERFAULTFD=y
 # CONFIG_COMPAT_BRK is not set
 CONFIG_MODULE_FORCE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_BLK_DEV_INTEGRITY=y
 CONFIG_BLK_DEV_THROTTLING=y
+CONFIG_BLK_WBT=y
+CONFIG_BLK_WBT_SQ=y
 CONFIG_PARTITION_ADVANCED=y
 CONFIG_IBM_PARTITION=y
 CONFIG_BSD_DISKLABEL=y
 CONFIG_UNIX_DIAG=m
 CONFIG_XFRM_USER=m
 CONFIG_NET_KEY=m
+CONFIG_SMC=m
+CONFIG_SMC_DIAG=m
 CONFIG_INET=y
 CONFIG_IP_MULTICAST=y
 CONFIG_IP_ADVANCED_ROUTER=y
 CONFIG_NET_ACT_SKBEDIT=m
 CONFIG_NET_ACT_CSUM=m
 CONFIG_DNS_RESOLVER=y
+CONFIG_NETLINK_DIAG=m
 CONFIG_CGROUP_NET_PRIO=y
 CONFIG_BPF_JIT=y
 CONFIG_NET_PKTGEN=m
 CONFIG_DMA_CMA=y
 CONFIG_CMA_SIZE_MBYTES=0
 CONFIG_CONNECTOR=y
+CONFIG_ZRAM=m
 CONFIG_BLK_DEV_LOOP=m
 CONFIG_BLK_DEV_CRYPTOLOOP=m
+CONFIG_BLK_DEV_DRBD=m
 CONFIG_BLK_DEV_NBD=m
 CONFIG_BLK_DEV_OSD=m
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=32768
-CONFIG_CDROM_PKTCDVD=m
+CONFIG_BLK_DEV_RAM_DAX=y
-CONFIG_ATA_OVER_ETH=m
 CONFIG_VIRTIO_BLK=y
+CONFIG_BLK_DEV_RBD=m
 CONFIG_ENCLOSURE_SERVICES=m
+CONFIG_GENWQE=m
 CONFIG_RAID_ATTRS=m
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 # CONFIG_NET_VENDOR_INTEL is not set
 # CONFIG_NET_VENDOR_MARVELL is not set
 CONFIG_MLX4_EN=m
+CONFIG_MLX5_CORE=m
+CONFIG_MLX5_CORE_EN=y
 # CONFIG_NET_VENDOR_NATSEMI is not set
 CONFIG_PPP=m
 CONFIG_PPP_BSDCOMP=m
 CONFIG_PPPOL2TP=m
 CONFIG_PPP_ASYNC=m
 CONFIG_PPP_SYNC_TTY=m
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_SERIO is not set
 CONFIG_INFINIBAND=m
 CONFIG_INFINIBAND_USER_ACCESS=m
 CONFIG_MLX4_INFINIBAND=m
+CONFIG_MLX5_INFINIBAND=m
 CONFIG_VIRTIO_BALLOON=m
 CONFIG_EXT4_FS=y
 CONFIG_EXT4_FS_POSIX_ACL=y
 CONFIG_XFS_RT=y
 CONFIG_XFS_DEBUG=y
 CONFIG_GFS2_FS=m
+CONFIG_GFS2_FS_LOCKING_DLM=y
 CONFIG_OCFS2_FS=m
 CONFIG_BTRFS_FS=y
 CONFIG_BTRFS_FS_POSIX_ACL=y
+CONFIG_BTRFS_DEBUG=y
 CONFIG_NILFS2_FS=m
+CONFIG_FS_DAX=y
+CONFIG_EXPORTFS_BLOCK_OPS=y
 CONFIG_FANOTIFY=y
+CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y
 CONFIG_QUOTA_NETLINK_INTERFACE=y
+CONFIG_QUOTA_DEBUG=y
 CONFIG_QFMT_V1=m
 CONFIG_QFMT_V2=m
 CONFIG_AUTOFS4_FS=m
 CONFIG_DEBUG_SECTION_MISMATCH=y
 CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_PAGEALLOC=y
+CONFIG_DEBUG_RODATA_TEST=y
 CONFIG_DEBUG_OBJECTS=y
 CONFIG_DEBUG_OBJECTS_SELFTEST=y
 CONFIG_DEBUG_OBJECTS_FREE=y
 CONFIG_WQ_WATCHDOG=y
 CONFIG_PANIC_ON_OOPS=y
 CONFIG_DEBUG_TIMEKEEPING=y
-CONFIG_TIMER_STATS=y
 CONFIG_DEBUG_RT_MUTEXES=y
 CONFIG_DEBUG_WW_MUTEX_SLOWPATH=y
 CONFIG_PROVE_LOCKING=y
 CONFIG_RCU_CPU_STALL_TIMEOUT=300
 CONFIG_NOTIFIER_ERROR_INJECTION=m
 CONFIG_PM_NOTIFIER_ERROR_INJECT=m
+CONFIG_NETDEV_NOTIFIER_ERROR_INJECT=m
 CONFIG_FAULT_INJECTION=y
 CONFIG_FAILSLAB=y
 CONFIG_FAIL_PAGE_ALLOC=y
 CONFIG_TRACE_ENUM_MAP_FILE=y
 CONFIG_LKDTM=m
 CONFIG_TEST_LIST_SORT=y
+CONFIG_TEST_SORT=y
 CONFIG_KPROBES_SANITY_TEST=y
 CONFIG_RBTREE_TEST=y
 CONFIG_INTERVAL_TREE_TEST=m
 CONFIG_PERCPU_TEST=m
 CONFIG_ATOMIC64_SELFTEST=y
-CONFIG_TEST_STRING_HELPERS=y
-CONFIG_TEST_KSTRTOX=y
 CONFIG_DMA_API_DEBUG=y
 CONFIG_TEST_BPF=m
 CONFIG_BUG_ON_DATA_CORRUPTION=y
 CONFIG_ENCRYPTED_KEYS=m
 CONFIG_SECURITY=y
 CONFIG_SECURITY_NETWORK=y
+CONFIG_HARDENED_USERCOPY=y
 CONFIG_SECURITY_SELINUX=y
 CONFIG_SECURITY_SELINUX_BOOTPARAM=y
 CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=0
 CONFIG_CRYPTO_DH=m
 CONFIG_CRYPTO_ECDH=m
 CONFIG_CRYPTO_USER=m
+CONFIG_CRYPTO_PCRYPT=m
 CONFIG_CRYPTO_CRYPTD=m
+CONFIG_CRYPTO_MCRYPTD=m
 CONFIG_CRYPTO_TEST=m
 CONFIG_CRYPTO_CCM=m
 CONFIG_CRYPTO_GCM=m
 CONFIG_CRYPTO_LRW=m
 CONFIG_CRYPTO_PCBC=m
 CONFIG_CRYPTO_KEYWRAP=m
+CONFIG_CRYPTO_CMAC=m
 CONFIG_CRYPTO_XCBC=m
 CONFIG_CRYPTO_VMAC=m
 CONFIG_CRYPTO_CRC32=m
 CONFIG_CRYPTO_RMD256=m
 CONFIG_CRYPTO_RMD320=m
 CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_SHA3=m
 CONFIG_CRYPTO_TGR192=m
 CONFIG_CRYPTO_WP512=m
+CONFIG_CRYPTO_AES_TI=m
 CONFIG_CRYPTO_ANUBIS=m
 CONFIG_CRYPTO_BLOWFISH=m
 CONFIG_CRYPTO_CAMELLIA=m
 CONFIG_CRYPTO_842=m
 CONFIG_CRYPTO_LZ4=m
 CONFIG_CRYPTO_LZ4HC=m
+CONFIG_CRYPTO_ANSI_CPRNG=m
 CONFIG_CRYPTO_USER_API_HASH=m
 CONFIG_CRYPTO_USER_API_SKCIPHER=m
 CONFIG_CRYPTO_USER_API_RNG=m
 CONFIG_CRYPTO_SHA512_S390=m
 CONFIG_CRYPTO_DES_S390=m
 CONFIG_CRYPTO_AES_S390=m
+CONFIG_CRYPTO_PAES_S390=m
 CONFIG_CRYPTO_GHASH_S390=m
 CONFIG_CRYPTO_CRC32_S390=y
 CONFIG_ASYMMETRIC_KEY_TYPE=y
 CONFIG_X509_CERTIFICATE_PARSER=m
 CONFIG_CRC7=m
 CONFIG_CRC8=m
+CONFIG_RANDOM32_SELFTEST=y
 CONFIG_CORDIC=m
 CONFIG_CMM=m
 CONFIG_APPLDATA_BASE=y

arch/s390/configs/gcov_defconfig+24−4

 CONFIG_SCHED_AUTOGROUP=y
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_EXPERT=y
+# CONFIG_SYSFS_SYSCALL is not set
 CONFIG_BPF_SYSCALL=y
 CONFIG_USERFAULTFD=y
 # CONFIG_COMPAT_BRK is not set
 CONFIG_MODULE_FORCE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_BLK_DEV_INTEGRITY=y
 CONFIG_BLK_DEV_THROTTLING=y
+CONFIG_BLK_WBT=y
+CONFIG_BLK_WBT_SQ=y
 CONFIG_PARTITION_ADVANCED=y
 CONFIG_IBM_PARTITION=y
 CONFIG_BSD_DISKLABEL=y
 CONFIG_UNIX_DIAG=m
 CONFIG_XFRM_USER=m
 CONFIG_NET_KEY=m
+CONFIG_SMC=m
+CONFIG_SMC_DIAG=m
 CONFIG_INET=y
 CONFIG_IP_MULTICAST=y
 CONFIG_IP_ADVANCED_ROUTER=y
 CONFIG_NET_ACT_SKBEDIT=m
 CONFIG_NET_ACT_CSUM=m
 CONFIG_DNS_RESOLVER=y
+CONFIG_NETLINK_DIAG=m
 CONFIG_CGROUP_NET_PRIO=y
 CONFIG_BPF_JIT=y
 CONFIG_NET_PKTGEN=m
 CONFIG_DMA_CMA=y
 CONFIG_CMA_SIZE_MBYTES=0
 CONFIG_CONNECTOR=y
+CONFIG_ZRAM=m
 CONFIG_BLK_DEV_LOOP=m
 CONFIG_BLK_DEV_CRYPTOLOOP=m
+CONFIG_BLK_DEV_DRBD=m
 CONFIG_BLK_DEV_NBD=m
 CONFIG_BLK_DEV_OSD=m
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=32768
-CONFIG_CDROM_PKTCDVD=m
+CONFIG_BLK_DEV_RAM_DAX=y
-CONFIG_ATA_OVER_ETH=m
 CONFIG_VIRTIO_BLK=y
 CONFIG_ENCLOSURE_SERVICES=m
+CONFIG_GENWQE=m
 CONFIG_RAID_ATTRS=m
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 # CONFIG_NET_VENDOR_INTEL is not set
 # CONFIG_NET_VENDOR_MARVELL is not set
 CONFIG_MLX4_EN=m
+CONFIG_MLX5_CORE=m
+CONFIG_MLX5_CORE_EN=y
 # CONFIG_NET_VENDOR_NATSEMI is not set
 CONFIG_PPP=m
 CONFIG_PPP_BSDCOMP=m
 CONFIG_PPPOL2TP=m
 CONFIG_PPP_ASYNC=m
 CONFIG_PPP_SYNC_TTY=m
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_SERIO is not set
 CONFIG_INFINIBAND=m
 CONFIG_INFINIBAND_USER_ACCESS=m
 CONFIG_MLX4_INFINIBAND=m
+CONFIG_MLX5_INFINIBAND=m
 CONFIG_VIRTIO_BALLOON=m
 CONFIG_EXT4_FS=y
 CONFIG_EXT4_FS_POSIX_ACL=y
 CONFIG_XFS_POSIX_ACL=y
 CONFIG_XFS_RT=y
 CONFIG_GFS2_FS=m
+CONFIG_GFS2_FS_LOCKING_DLM=y
 CONFIG_OCFS2_FS=m
 CONFIG_BTRFS_FS=y
 CONFIG_BTRFS_FS_POSIX_ACL=y
 CONFIG_NILFS2_FS=m
+CONFIG_FS_DAX=y
+CONFIG_EXPORTFS_BLOCK_OPS=y
 CONFIG_FANOTIFY=y
+CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y
 CONFIG_QUOTA_NETLINK_INTERFACE=y
 CONFIG_QFMT_V1=m
 CONFIG_QFMT_V2=m
 CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_MEMORY_INIT=y
 CONFIG_PANIC_ON_OOPS=y
-CONFIG_TIMER_STATS=y
 CONFIG_RCU_TORTURE_TEST=m
 CONFIG_RCU_CPU_STALL_TIMEOUT=60
 CONFIG_LATENCYTOP=y
 CONFIG_ENCRYPTED_KEYS=m
 CONFIG_SECURITY=y
 CONFIG_SECURITY_NETWORK=y
+CONFIG_HARDENED_USERCOPY=y
 CONFIG_SECURITY_SELINUX=y
 CONFIG_SECURITY_SELINUX_BOOTPARAM=y
 CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=0
 CONFIG_CRYPTO_LRW=m
 CONFIG_CRYPTO_PCBC=m
 CONFIG_CRYPTO_KEYWRAP=m
+CONFIG_CRYPTO_CMAC=m
 CONFIG_CRYPTO_XCBC=m
 CONFIG_CRYPTO_VMAC=m
 CONFIG_CRYPTO_CRC32=m
 CONFIG_CRYPTO_SHA3=m
 CONFIG_CRYPTO_TGR192=m
 CONFIG_CRYPTO_WP512=m
+CONFIG_CRYPTO_AES_TI=m
 CONFIG_CRYPTO_ANUBIS=m
 CONFIG_CRYPTO_BLOWFISH=m
 CONFIG_CRYPTO_CAMELLIA=m
 CONFIG_CRYPTO_842=m
 CONFIG_CRYPTO_LZ4=m
 CONFIG_CRYPTO_LZ4HC=m
+CONFIG_CRYPTO_ANSI_CPRNG=m
 CONFIG_CRYPTO_USER_API_HASH=m
 CONFIG_CRYPTO_USER_API_SKCIPHER=m
 CONFIG_CRYPTO_USER_API_RNG=m
 CONFIG_CRYPTO_USER_API_AEAD=m
 CONFIG_ZCRYPT=m
+CONFIG_PKEY=m
 CONFIG_CRYPTO_SHA1_S390=m
 CONFIG_CRYPTO_SHA256_S390=m
 CONFIG_CRYPTO_SHA512_S390=m
 CONFIG_CRYPTO_DES_S390=m
 CONFIG_CRYPTO_AES_S390=m
+CONFIG_CRYPTO_PAES_S390=m
 CONFIG_CRYPTO_GHASH_S390=m
 CONFIG_CRYPTO_CRC32_S390=y
 CONFIG_CRC7=m

arch/s390/configs/performance_defconfig+23−4

 CONFIG_SCHED_AUTOGROUP=y
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_EXPERT=y
+# CONFIG_SYSFS_SYSCALL is not set
 CONFIG_BPF_SYSCALL=y
 CONFIG_USERFAULTFD=y
 # CONFIG_COMPAT_BRK is not set
 CONFIG_MODULE_FORCE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_BLK_DEV_INTEGRITY=y
 CONFIG_BLK_DEV_THROTTLING=y
+CONFIG_BLK_WBT=y
+CONFIG_BLK_WBT_SQ=y
 CONFIG_PARTITION_ADVANCED=y
 CONFIG_IBM_PARTITION=y
 CONFIG_BSD_DISKLABEL=y
 CONFIG_UNIX_DIAG=m
 CONFIG_XFRM_USER=m
 CONFIG_NET_KEY=m
+CONFIG_SMC=m
+CONFIG_SMC_DIAG=m
 CONFIG_INET=y
 CONFIG_IP_MULTICAST=y
 CONFIG_IP_ADVANCED_ROUTER=y
 CONFIG_NET_ACT_SKBEDIT=m
 CONFIG_NET_ACT_CSUM=m
 CONFIG_DNS_RESOLVER=y
+CONFIG_NETLINK_DIAG=m
 CONFIG_CGROUP_NET_PRIO=y
 CONFIG_BPF_JIT=y
 CONFIG_NET_PKTGEN=m
 CONFIG_DMA_CMA=y
 CONFIG_CMA_SIZE_MBYTES=0
 CONFIG_CONNECTOR=y
+CONFIG_ZRAM=m
 CONFIG_BLK_DEV_LOOP=m
 CONFIG_BLK_DEV_CRYPTOLOOP=m
+CONFIG_BLK_DEV_DRBD=m
 CONFIG_BLK_DEV_NBD=m
 CONFIG_BLK_DEV_OSD=m
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=32768
-CONFIG_CDROM_PKTCDVD=m
+CONFIG_BLK_DEV_RAM_DAX=y
-CONFIG_ATA_OVER_ETH=m
 CONFIG_VIRTIO_BLK=y
 CONFIG_ENCLOSURE_SERVICES=m
+CONFIG_GENWQE=m
 CONFIG_RAID_ATTRS=m
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 # CONFIG_NET_VENDOR_INTEL is not set
 # CONFIG_NET_VENDOR_MARVELL is not set
 CONFIG_MLX4_EN=m
+CONFIG_MLX5_CORE=m
+CONFIG_MLX5_CORE_EN=y
 # CONFIG_NET_VENDOR_NATSEMI is not set
 CONFIG_PPP=m
 CONFIG_PPP_BSDCOMP=m
 CONFIG_PPPOL2TP=m
 CONFIG_PPP_ASYNC=m
 CONFIG_PPP_SYNC_TTY=m
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_SERIO is not set
 CONFIG_INFINIBAND=m
 CONFIG_INFINIBAND_USER_ACCESS=m
 CONFIG_MLX4_INFINIBAND=m
+CONFIG_MLX5_INFINIBAND=m
 CONFIG_VIRTIO_BALLOON=m
 CONFIG_EXT4_FS=y
 CONFIG_EXT4_FS_POSIX_ACL=y
 CONFIG_XFS_POSIX_ACL=y
 CONFIG_XFS_RT=y
 CONFIG_GFS2_FS=m
+CONFIG_GFS2_FS_LOCKING_DLM=y
 CONFIG_OCFS2_FS=m
 CONFIG_BTRFS_FS=y
 CONFIG_BTRFS_FS_POSIX_ACL=y
 CONFIG_NILFS2_FS=m
+CONFIG_FS_DAX=y
+CONFIG_EXPORTFS_BLOCK_OPS=y
 CONFIG_FANOTIFY=y
+CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y
 CONFIG_QUOTA_NETLINK_INTERFACE=y
 CONFIG_QFMT_V1=m
 CONFIG_QFMT_V2=m
 CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_MEMORY_INIT=y
 CONFIG_PANIC_ON_OOPS=y
-CONFIG_TIMER_STATS=y
 CONFIG_RCU_TORTURE_TEST=m
 CONFIG_RCU_CPU_STALL_TIMEOUT=60
 CONFIG_LATENCYTOP=y
 CONFIG_ENCRYPTED_KEYS=m
 CONFIG_SECURITY=y
 CONFIG_SECURITY_NETWORK=y
+CONFIG_HARDENED_USERCOPY=y
 CONFIG_SECURITY_SELINUX=y
 CONFIG_SECURITY_SELINUX_BOOTPARAM=y
 CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=0
 CONFIG_CRYPTO_LRW=m
 CONFIG_CRYPTO_PCBC=m
 CONFIG_CRYPTO_KEYWRAP=m
+CONFIG_CRYPTO_CMAC=m
 CONFIG_CRYPTO_XCBC=m
 CONFIG_CRYPTO_VMAC=m
 CONFIG_CRYPTO_CRC32=m
 CONFIG_CRYPTO_SHA3=m
 CONFIG_CRYPTO_TGR192=m
 CONFIG_CRYPTO_WP512=m
+CONFIG_CRYPTO_AES_TI=m
 CONFIG_CRYPTO_ANUBIS=m
 CONFIG_CRYPTO_BLOWFISH=m
 CONFIG_CRYPTO_CAMELLIA=m
 CONFIG_CRYPTO_842=m
 CONFIG_CRYPTO_LZ4=m
 CONFIG_CRYPTO_LZ4HC=m
+CONFIG_CRYPTO_ANSI_CPRNG=m
 CONFIG_CRYPTO_USER_API_HASH=m
 CONFIG_CRYPTO_USER_API_SKCIPHER=m
 CONFIG_CRYPTO_USER_API_RNG=m
 CONFIG_CRYPTO_SHA512_S390=m
 CONFIG_CRYPTO_DES_S390=m
 CONFIG_CRYPTO_AES_S390=m
+CONFIG_CRYPTO_PAES_S390=m
 CONFIG_CRYPTO_GHASH_S390=m
 CONFIG_CRYPTO_CRC32_S390=y
 CONFIG_CRC7=m

arch/s390/configs/zfcpdump_defconfig+4−2

 CONFIG_NR_CPUS=2
 # CONFIG_HOTPLUG_CPU is not set
 CONFIG_HZ_100=y
+# CONFIG_ARCH_RANDOM is not set
 # CONFIG_COMPACTION is not set
 # CONFIG_MIGRATION is not set
+# CONFIG_BOUNCE is not set
 # CONFIG_CHECK_STACK is not set
 # CONFIG_CHSC_SCH is not set
 # CONFIG_SCM_BUS is not set
 CONFIG_SCSI_LOGGING=y
 CONFIG_SCSI_FC_ATTRS=y
 CONFIG_ZFCP=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_SERIO is not set
 # CONFIG_HVC_IUCV is not set
+# CONFIG_HW_RANDOM_S390 is not set
 CONFIG_RAW_DRIVER=y
 # CONFIG_SCLP_ASYNC is not set
 # CONFIG_HMC_DRV is not set
 # CONFIG_INOTIFY_USER is not set
 CONFIG_CONFIGFS_FS=y
 # CONFIG_MISC_FILESYSTEMS is not set
+# CONFIG_NETWORK_FILESYSTEMS is not set
 CONFIG_PRINTK_TIME=y
 CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_FS=y
 CONFIG_DEBUG_KERNEL=y
 CONFIG_PANIC_ON_OOPS=y
 # CONFIG_SCHED_DEBUG is not set

arch/s390/defconfig+3−5

 CONFIG_USER_NS=y
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_EXPERT=y
+# CONFIG_SYSFS_SYSCALL is not set
 CONFIG_BPF_SYSCALL=y
 CONFIG_USERFAULTFD=y
 # CONFIG_COMPAT_BRK is not set
 CONFIG_SCSI_VIRTIO=y
 CONFIG_MD=y
 CONFIG_MD_LINEAR=m
-CONFIG_MD_RAID0=m
 CONFIG_MD_MULTIPATH=m
 CONFIG_BLK_DEV_DM=y
 CONFIG_DM_CRYPT=m
 CONFIG_VIRTIO_NET=y
 # CONFIG_NET_VENDOR_ALACRITECH is not set
 # CONFIG_NET_VENDOR_SOLARFLARE is not set
+# CONFIG_NET_VENDOR_SYNOPSYS is not set
 # CONFIG_INPUT is not set
 # CONFIG_SERIO is not set
 CONFIG_DEVKMEM=y
 CONFIG_DEBUG_PAGEALLOC=y
 CONFIG_DETECT_HUNG_TASK=y
 CONFIG_PANIC_ON_OOPS=y
-CONFIG_TIMER_STATS=y
 CONFIG_DEBUG_RT_MUTEXES=y
 CONFIG_PROVE_LOCKING=y
 CONFIG_LOCK_STAT=y
 CONFIG_DEBUG_SG=y
 CONFIG_DEBUG_NOTIFIERS=y
 CONFIG_RCU_CPU_STALL_TIMEOUT=60
-CONFIG_RCU_TRACE=y
 CONFIG_LATENCYTOP=y
 CONFIG_SCHED_TRACER=y
 CONFIG_FTRACE_SYSCALLS=y
 CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP=y
 CONFIG_STACK_TRACER=y
 CONFIG_BLK_DEV_IO_TRACE=y
-CONFIG_UPROBE_EVENTS=y
 CONFIG_FUNCTION_PROFILER=y
 CONFIG_TRACE_ENUM_MAP_FILE=y
 CONFIG_KPROBES_SANITY_TEST=y
 CONFIG_CRYPTO_GCM=m
 CONFIG_CRYPTO_CBC=y
 CONFIG_CRYPTO_CTS=m
-CONFIG_CRYPTO_ECB=m
 CONFIG_CRYPTO_LRW=m
 CONFIG_CRYPTO_PCBC=m
 CONFIG_CRYPTO_XTS=m
 CONFIG_CRYPTO_USER_API_RNG=m
 CONFIG_ZCRYPT=m
 CONFIG_PKEY=m
+CONFIG_CRYPTO_PAES_S390=m
 CONFIG_CRYPTO_SHA1_S390=m
 CONFIG_CRYPTO_SHA256_S390=m
 CONFIG_CRYPTO_SHA512_S390=m

arch/s390/include/asm/kvm_host.h+0−1

@@ -541,7 +541,6 @@ struct kvm_s390_float_interrupt { · 540 unmodified lines
541	struct mutex ais_lock;	541	struct mutex ais_lock;
542	u8 simm;	542	u8 simm;
543	u8 nimm;	543	u8 nimm;
544	int ais_enabled;
545	};	544	};
546		545
547	struct kvm_hw_wp_info_arch {	546	struct kvm_hw_wp_info_arch {

arch/s390/kernel/entry.S+13−6

 	lctlg	%c1,%c1,__LC_USER_ASCE		# load primary asce
 .Lsie_done:
 # some program checks are suppressing. C code (e.g. do_protection_exception)
-# will rewind the PSW by the ILC, which is 4 bytes in case of SIE. Other
+# will rewind the PSW by the ILC, which is often 4 bytes in case of SIE. There
-# instructions between sie64a and .Lsie_done should not cause program
+# are some corner cases (e.g. runtime instrumentation) where ILC is unpredictable.
-# interrupts. So lets use a nop (47 00 00 00) as a landing pad.
+# Other instructions between sie64a and .Lsie_done should not cause program
+# interrupts. So lets use 3 nops as a landing pad for all possible rewinds.
 # See also .Lcleanup_sie
-.Lrewind_pad:
+.Lrewind_pad6:
-	nop	0
+	nopr	7
+.Lrewind_pad4:
+	nopr	7
+.Lrewind_pad2:
+	nopr	7
 	.globl sie_exit
 sie_exit:
 	lg	%r14,__SF_EMPTY+8(%r15)		# load guest register save area
 	stg	%r14,__SF_EMPTY+16(%r15)	# set exit reason code
 	j	sie_exit
-	EX_TABLE(.Lrewind_pad,.Lsie_fault)
+	EX_TABLE(.Lrewind_pad6,.Lsie_fault)
+	EX_TABLE(.Lrewind_pad4,.Lsie_fault)
+	EX_TABLE(.Lrewind_pad2,.Lsie_fault)
 	EX_TABLE(sie_exit,.Lsie_fault)
 EXPORT_SYMBOL(sie64a)
 EXPORT_SYMBOL(sie_exit)

arch/s390/kvm/interrupt.c+2−2

@@ -2160,7 +2160,7 @@ static int modify_ais_mode(struct kvm kvm, struct kvm_device_attr attr) · 2159 unmodified lines
2160	struct kvm_s390_ais_req req;	2160	struct kvm_s390_ais_req req;
2161	int ret = 0;	2161	int ret = 0;
2162		2162
2163	if (!fi->ais_enabled)	2163	if (!test_kvm_facility(kvm, 72))
2164	return -ENOTSUPP;	2164	return -ENOTSUPP;
2165		2165
2166	if (copy_from_user(&req, (void __user *)attr->addr, sizeof(req)))	2166	if (copy_from_user(&req, (void __user *)attr->addr, sizeof(req)))
@@ -2204,7 +2204,7 @@ static int kvm_s390_inject_airq(struct kvm *kvm, · 37 unmodified lines
2204	};	2204	};
2205	int ret = 0;	2205	int ret = 0;
2206		2206
2207	if (!fi->ais_enabled \|\| !adapter->suppressible)	2207	if (!test_kvm_facility(kvm, 72) \|\| !adapter->suppressible)
2208	return kvm_s390_inject_vm(kvm, &s390int);	2208	return kvm_s390_inject_vm(kvm, &s390int);
2209		2209
2210	mutex_lock(&fi->ais_lock);	2210	mutex_lock(&fi->ais_lock);

arch/s390/kvm/kvm-s390.c+0−2

 		} else {
 			set_kvm_facility(kvm->arch.model.fac_mask, 72);
 			set_kvm_facility(kvm->arch.model.fac_list, 72);
-			kvm->arch.float_int.ais_enabled = 1;
 			r = 0;
 		}
 		mutex_unlock(&kvm->lock);
 	mutex_init(&kvm->arch.float_int.ais_lock);
 	kvm->arch.float_int.simm = 0;
 	kvm->arch.float_int.nimm = 0;
-	kvm->arch.float_int.ais_enabled = 0;
 	spin_lock_init(&kvm->arch.float_int.lock);
 	for (i = 0; i < FIRQ_LIST_COUNT; i++)
 		INIT_LIST_HEAD(&kvm->arch.float_int.lists[i]);

arch/s390/mm/mmap.c+2−2

@@ -101,7 +101,7 @@ arch_get_unmapped_area(struct file *filp, unsigned long addr, · 100 unmodified lines
101	addr = PAGE_ALIGN(addr);	101	addr = PAGE_ALIGN(addr);
102	vma = find_vma(mm, addr);	102	vma = find_vma(mm, addr);
103	if (TASK_SIZE - len >= addr && addr >= mmap_min_addr &&	103	if (TASK_SIZE - len >= addr && addr >= mmap_min_addr &&
104	(!vma \|\| addr + len <= vma->vm_start))	104	(!vma \|\| addr + len <= vm_start_gap(vma)))
105	goto check_asce_limit;	105	goto check_asce_limit;
106	}	106	}
107		107
@@ -151,7 +151,7 @@ arch_get_unmapped_area_topdown(struct file *filp, const unsigned long addr0, · 43 unmodified lines
151	addr = PAGE_ALIGN(addr);	151	addr = PAGE_ALIGN(addr);
152	vma = find_vma(mm, addr);	152	vma = find_vma(mm, addr);
153	if (TASK_SIZE - len >= addr && addr >= mmap_min_addr &&	153	if (TASK_SIZE - len >= addr && addr >= mmap_min_addr &&
154	(!vma \|\| addr + len <= vma->vm_start))	154	(!vma \|\| addr + len <= vm_start_gap(vma)))
155	goto check_asce_limit;	155	goto check_asce_limit;
156	}	156	}
157		157

arch/sh/mm/mmap.c+2−2

@@ -64,7 +64,7 @@ unsigned long arch_get_unmapped_area(struct file *filp, unsigned long addr, · 63 unmodified lines
64		64
65	vma = find_vma(mm, addr);	65	vma = find_vma(mm, addr);
66	if (TASK_SIZE - len >= addr &&	66	if (TASK_SIZE - len >= addr &&
67	(!vma \|\| addr + len <= vma->vm_start))	67	(!vma \|\| addr + len <= vm_start_gap(vma)))
68	return addr;	68	return addr;
69	}	69	}
70		70
@@ -114,7 +114,7 @@ arch_get_unmapped_area_topdown(struct file *filp, const unsigned long addr0, · 43 unmodified lines
114		114
115	vma = find_vma(mm, addr);	115	vma = find_vma(mm, addr);
116	if (TASK_SIZE - len >= addr &&	116	if (TASK_SIZE - len >= addr &&
117	(!vma \|\| addr + len <= vma->vm_start))	117	(!vma \|\| addr + len <= vm_start_gap(vma)))
118	return addr;	118	return addr;
119	}	119	}
120		120

arch/sparc/Kconfig+8−7

 	int "Maximum number of CPUs"
 	depends on SMP
 	range 2 32 if SPARC32
-	range 2 1024 if SPARC64
+	range 2 4096 if SPARC64
 	default 32 if SPARC32
-	default 64 if SPARC64
+	default 4096 if SPARC64
 source kernel/Kconfig.hz
 	depends on SPARC64 && SMP
 config NODES_SHIFT
-	int
+	int "Maximum NUMA Nodes (as a power of 2)"
-	default "4"
+	range 4 5 if SPARC64
+	default "5"
 	depends on NEED_MULTIPLE_NODES
+	help
+	  Specify the maximum number of NUMA Nodes available on the target
+	  system.  Increases memory reserved to accommodate various tables.
 # Some NUMA nodes have memory ranges that span
 # other nodes.  Even though a pfn is valid and
 	depends on COMPAT && SYSVIPC
 	default y
-config KEYS_COMPAT
-	def_bool y if COMPAT && KEYS
 endmenu
 source "net/Kconfig"

arch/sparc/include/asm/mmu_64.h+1−1

@@ -52,7 +52,7 @@ · 51 unmodified lines
52	#define CTX_NR_MASK TAG_CONTEXT_BITS	52	#define CTX_NR_MASK TAG_CONTEXT_BITS
53	#define CTX_HW_MASK (CTX_NR_MASK \| CTX_PGSZ_MASK)	53	#define CTX_HW_MASK (CTX_NR_MASK \| CTX_PGSZ_MASK)
54		54
55	#define CTX_FIRST_VERSION ((_AC(1,UL) << CTX_VERSION_SHIFT) + _AC(1,UL))	55	#define CTX_FIRST_VERSION BIT(CTX_VERSION_SHIFT)
56	#define CTX_VALID(__ctx) \	56	#define CTX_VALID(__ctx) \
57	(!(((__ctx.sparc64_ctx_val) ^ tlb_context_cache) & CTX_VERSION_MASK))	57	(!(((__ctx.sparc64_ctx_val) ^ tlb_context_cache) & CTX_VERSION_MASK))
58	#define CTX_HWBITS(__ctx) ((__ctx.sparc64_ctx_val) & CTX_HW_MASK)	58	#define CTX_HWBITS(__ctx) ((__ctx.sparc64_ctx_val) & CTX_HW_MASK)

arch/sparc/include/asm/mmu_context_64.h+4−28

@@ -19,13 +19,8 @@ extern spinlock_t ctx_alloc_lock; · 18 unmodified lines
19	extern unsigned long tlb_context_cache;	19	extern unsigned long tlb_context_cache;
20	extern unsigned long mmu_context_bmap[];	20	extern unsigned long mmu_context_bmap[];
21		21
		22	DECLARE_PER_CPU(struct mm_struct *, per_cpu_secondary_mm);
22	void get_new_mmu_context(struct mm_struct *mm);	23	void get_new_mmu_context(struct mm_struct *mm);
23	#ifdef CONFIG_SMP
24	void smp_new_mmu_context_version(void);
25	#else
26	#define smp_new_mmu_context_version() do { } while (0)
27	#endif
28
29	int init_new_context(struct task_struct tsk, struct mm_struct mm);	24	int init_new_context(struct task_struct tsk, struct mm_struct mm);
30	void destroy_context(struct mm_struct *mm);	25	void destroy_context(struct mm_struct *mm);
31		26
@@ -76,8 +71,9 @@ void __flush_tlb_mm(unsigned long, unsigned long); · 44 unmodified lines
76	static inline void switch_mm(struct mm_struct old_mm, struct mm_struct mm, struct task_struct *tsk)	71	static inline void switch_mm(struct mm_struct old_mm, struct mm_struct mm, struct task_struct *tsk)
77	{	72	{
78	unsigned long ctx_valid, flags;	73	unsigned long ctx_valid, flags;
79	int cpu;	74	int cpu = smp_processor_id();
80		75
		76	per_cpu(per_cpu_secondary_mm, cpu) = mm;
81	if (unlikely(mm == &init_mm))	77	if (unlikely(mm == &init_mm))
82	return;	78	return;
83		79
@@ -123,7 +119,6 @@ static inline void switch_mm(struct mm_struct old_mm, struct mm_struct mm, str · 39 unmodified lines
123	* for the first time, we must flush that context out of the	119	* for the first time, we must flush that context out of the
124	* local TLB.	120	* local TLB.
125	*/	121	*/
126	cpu = smp_processor_id();
127	if (!ctx_valid \|\| !cpumask_test_cpu(cpu, mm_cpumask(mm))) {	122	if (!ctx_valid \|\| !cpumask_test_cpu(cpu, mm_cpumask(mm))) {
128	cpumask_set_cpu(cpu, mm_cpumask(mm));	123	cpumask_set_cpu(cpu, mm_cpumask(mm));
129	__flush_tlb_mm(CTX_HWBITS(mm->context),	124	__flush_tlb_mm(CTX_HWBITS(mm->context),
@@ -133,26 +128,7 @@ static inline void switch_mm(struct mm_struct old_mm, struct mm_struct mm, str · 3 unmodified lines
133	}	128	}
134		129
135	#define deactivate_mm(tsk,mm) do { } while (0)	130	#define deactivate_mm(tsk,mm) do { } while (0)
136		131	#define activate_mm(active_mm, mm) switch_mm(active_mm, mm, NULL)
137	/* Activate a new MM instance for the current task. */
138	static inline void activate_mm(struct mm_struct active_mm, struct mm_struct mm)
139	{
140	unsigned long flags;
141	int cpu;
142
143	spin_lock_irqsave(&mm->context.lock, flags);
144	if (!CTX_VALID(mm->context))
145	get_new_mmu_context(mm);
146	cpu = smp_processor_id();
147	if (!cpumask_test_cpu(cpu, mm_cpumask(mm)))
148	cpumask_set_cpu(cpu, mm_cpumask(mm));
149
150	load_secondary_context(mm);
151	__flush_tlb_mm(CTX_HWBITS(mm->context), SECONDARY_CONTEXT);
152	tsb_context_switch(mm);
153	spin_unlock_irqrestore(&mm->context.lock, flags);
154	}
155
156	#endif /* !(__ASSEMBLY__) */	132	#endif /* !(__ASSEMBLY__) */
157		133
158	#endif /* !(__SPARC64_MMU_CONTEXT_H) */	134	#endif /* !(__SPARC64_MMU_CONTEXT_H) */

arch/sparc/include/asm/pil.h+0−1

@@ -20,7 +20,6 @@ · 19 unmodified lines
20	#define PIL_SMP_CALL_FUNC 1	20	#define PIL_SMP_CALL_FUNC 1
21	#define PIL_SMP_RECEIVE_SIGNAL 2	21	#define PIL_SMP_RECEIVE_SIGNAL 2
22	#define PIL_SMP_CAPTURE 3	22	#define PIL_SMP_CAPTURE 3
23	#define PIL_SMP_CTX_NEW_VERSION 4
24	#define PIL_DEVICE_IRQ 5	23	#define PIL_DEVICE_IRQ 5
25	#define PIL_SMP_CALL_FUNC_SNGL 6	24	#define PIL_SMP_CALL_FUNC_SNGL 6
26	#define PIL_DEFERRED_PCR_WORK 7	25	#define PIL_DEFERRED_PCR_WORK 7

arch/sparc/include/asm/vio.h+1−0

@@ -327,6 +327,7 @@ struct vio_dev { · 326 unmodified lines
327	int compat_len;	327	int compat_len;
328		328
329	u64 dev_no;	329	u64 dev_no;
		330	u64 id;
330		331
331	unsigned long channel_id;	332	unsigned long channel_id;
332		333

arch/sparc/kernel/ds.c+1−1

@@ -909,7 +909,7 @@ static int register_services(struct ds_info *dp) · 908 unmodified lines
909	pbuf.req.handle = cp->handle;	909	pbuf.req.handle = cp->handle;
910	pbuf.req.major = 1;	910	pbuf.req.major = 1;
911	pbuf.req.minor = 0;	911	pbuf.req.minor = 0;
912	strcpy(pbuf.req.svc_id, cp->service_id);	912	strcpy(pbuf.id_buf, cp->service_id);
913		913
914	err = __ds_send(lp, &pbuf, msg_len);	914	err = __ds_send(lp, &pbuf, msg_len);
915	if (err > 0)	915	if (err > 0)

arch/sparc/kernel/irq_64.c+13−4

 {
 #ifdef CONFIG_SMP
 	unsigned long page;
+	void *mondo, *p;
-	BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > (PAGE_SIZE - 64));
+	BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > PAGE_SIZE);
+	/* Make sure mondo block is 64byte aligned */
+	p = kzalloc(127, GFP_KERNEL);
+	if (!p) {
+		prom_printf("SUN4V: Error, cannot allocate mondo block.\n");
+		prom_halt();
+	}
+	mondo = (void *)(((unsigned long)p + 63) & ~0x3f);
+	tb->cpu_mondo_block_pa = __pa(mondo);
 	page = get_zeroed_page(GFP_KERNEL);
 	if (!page) {
-		prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n");
+		prom_printf("SUN4V: Error, cannot allocate cpu list page.\n");
 		prom_halt();
 	}
-	tb->cpu_mondo_block_pa = __pa(page);
+	tb->cpu_list_pa = __pa(page);
-	tb->cpu_list_pa = __pa(page + 64);
 #endif
 }

arch/sparc/kernel/kernel.h+0−1

@@ -37,7 +37,6 @@ void handle_stdfmna(struct pt_regs *regs, unsigned long sfar, unsigned long sfsr · 36 unmodified lines
37	/* smp_64.c */	37	/* smp_64.c */
38	void __irq_entry smp_call_function_client(int irq, struct pt_regs *regs);	38	void __irq_entry smp_call_function_client(int irq, struct pt_regs *regs);
39	void __irq_entry smp_call_function_single_client(int irq, struct pt_regs *regs);	39	void __irq_entry smp_call_function_single_client(int irq, struct pt_regs *regs);
40	void __irq_entry smp_new_mmu_context_version_client(int irq, struct pt_regs *regs);
41	void __irq_entry smp_penguin_jailcell(int irq, struct pt_regs *regs);	40	void __irq_entry smp_penguin_jailcell(int irq, struct pt_regs *regs);
42	void __irq_entry smp_receive_signal_client(int irq, struct pt_regs *regs);	41	void __irq_entry smp_receive_signal_client(int irq, struct pt_regs *regs);
43		42

arch/sparc/kernel/smp_64.c+0−31

@@ -964,37 +964,6 @@ void flush_dcache_page_all(struct mm_struct mm, struct page page) · 963 unmodified lines
964	preempt_enable();	964	preempt_enable();
965	}	965	}
966		966
967	void __irq_entry smp_new_mmu_context_version_client(int irq, struct pt_regs *regs)
968	{
969	struct mm_struct *mm;
970	unsigned long flags;
971
972	clear_softint(1 << irq);
973
974	/* See if we need to allocate a new TLB context because
975	* the version of the one we are using is now out of date.
976	*/
977	mm = current->active_mm;
978	if (unlikely(!mm \|\| (mm == &init_mm)))
979	return;
980
981	spin_lock_irqsave(&mm->context.lock, flags);
982
983	if (unlikely(!CTX_VALID(mm->context)))
984	get_new_mmu_context(mm);
985
986	spin_unlock_irqrestore(&mm->context.lock, flags);
987
988	load_secondary_context(mm);
989	__flush_tlb_mm(CTX_HWBITS(mm->context),
990	SECONDARY_CONTEXT);
991	}
992
993	void smp_new_mmu_context_version(void)
994	{
995	smp_cross_call(&xcall_new_mmu_context_version, 0, 0, 0);
996	}
997
998	#ifdef CONFIG_KGDB	967	#ifdef CONFIG_KGDB
999	void kgdb_roundup_cpus(unsigned long flags)	968	void kgdb_roundup_cpus(unsigned long flags)
1000	{	969	{

arch/sparc/kernel/sys_sparc_64.c+2−2

@@ -120,7 +120,7 @@ unsigned long arch_get_unmapped_area(struct file *filp, unsigned long addr, unsi · 119 unmodified lines
120		120
121	vma = find_vma(mm, addr);	121	vma = find_vma(mm, addr);
122	if (task_size - len >= addr &&	122	if (task_size - len >= addr &&
123	(!vma \|\| addr + len <= vma->vm_start))	123	(!vma \|\| addr + len <= vm_start_gap(vma)))
124	return addr;	124	return addr;
125	}	125	}
126		126
@@ -183,7 +183,7 @@ arch_get_unmapped_area_topdown(struct file *filp, const unsigned long addr0, · 56 unmodified lines
183		183
184	vma = find_vma(mm, addr);	184	vma = find_vma(mm, addr);
185	if (task_size - len >= addr &&	185	if (task_size - len >= addr &&
186	(!vma \|\| addr + len <= vma->vm_start))	186	(!vma \|\| addr + len <= vm_start_gap(vma)))
187	return addr;	187	return addr;
188	}	188	}
189		189

arch/sparc/kernel/tsb.S+7−4

 	.type	copy_tsb,#function
 copy_tsb:		/* %o0=old_tsb_base, %o1=old_tsb_size
 			 * %o2=new_tsb_base, %o3=new_tsb_size
+			 * %o4=page_size_shift
 			 */
 	sethi		%uhi(TSB_PASS_BITS), %g7
 	srlx		%o3, 4, %o3
-	add		%o0, %o1, %g1	/* end of old tsb */
+	add		%o0, %o1, %o1	/* end of old tsb */
 	sllx		%g7, 32, %g7
 	sub		%o3, 1, %o3	/* %o3 == new tsb hash mask */
+	mov		%o4, %g1	/* page_size_shift */
 661:	prefetcha	[%o0] ASI_N, #one_read
 	.section	.tsb_phys_patch, "ax"
 	.word		661b
 	/* This can definitely be computed faster... */
 	srlx		%o0, 4, %o5	/* Build index */
 	and		%o5, 511, %o5	/* Mask index */
-	sllx		%o5, PAGE_SHIFT, %o5 /* Put into vaddr position */
+	sllx		%o5, %g1, %o5	/* Put into vaddr position */
 	or		%o4, %o5, %o4	/* Full VADDR. */
-	srlx		%o4, PAGE_SHIFT, %o4 /* Shift down to create index */
+	srlx		%o4, %g1, %o4	/* Shift down to create index */
 	and		%o4, %o3, %o4	/* Mask with new_tsb_nents-1 */
 	sllx		%o4, 4, %o4	/* Shift back up into tsb ent offset */
 	TSB_STORE(%o2 + %o4, %g2)	/* Store TAG */
 	TSB_STORE(%o2 + %o4, %g3)	/* Store TTE */
 80:	add		%o0, 16, %o0
-	cmp		%o0, %g1
+	cmp		%o0, %o1
 	bne,pt		%xcc, 90b
 	 nop

arch/sparc/kernel/ttable_64.S+1−1

@@ -50,7 +50,7 @@ tl0_resv03e: BTRAP(0x3e) BTRAP(0x3f) BTRAP(0x40) · 49 unmodified lines
50	tl0_irq1: TRAP_IRQ(smp_call_function_client, 1)	50	tl0_irq1: TRAP_IRQ(smp_call_function_client, 1)
51	tl0_irq2: TRAP_IRQ(smp_receive_signal_client, 2)	51	tl0_irq2: TRAP_IRQ(smp_receive_signal_client, 2)
52	tl0_irq3: TRAP_IRQ(smp_penguin_jailcell, 3)	52	tl0_irq3: TRAP_IRQ(smp_penguin_jailcell, 3)
53	tl0_irq4: TRAP_IRQ(smp_new_mmu_context_version_client, 4)	53	tl0_irq4: BTRAP(0x44)
54	#else	54	#else
55	tl0_irq1: BTRAP(0x41)	55	tl0_irq1: BTRAP(0x41)
56	tl0_irq2: BTRAP(0x42)	56	tl0_irq2: BTRAP(0x42)

arch/sparc/kernel/vio.c+64−4

@@ -302,13 +302,16 @@ static struct vio_dev vio_create_one(struct mdesc_handle hp, u64 mp, · 301 unmodified lines
302	if (!id) {	302	if (!id) {
303	dev_set_name(&vdev->dev, "%s", bus_id_name);	303	dev_set_name(&vdev->dev, "%s", bus_id_name);
304	vdev->dev_no = ~(u64)0;	304	vdev->dev_no = ~(u64)0;
		305	vdev->id = ~(u64)0;
305	} else if (!cfg_handle) {	306	} else if (!cfg_handle) {
306	dev_set_name(&vdev->dev, "%s-%llu", bus_id_name, *id);	307	dev_set_name(&vdev->dev, "%s-%llu", bus_id_name, *id);
307	vdev->dev_no = *id;	308	vdev->dev_no = *id;
		309	vdev->id = ~(u64)0;
308	} else {	310	} else {
309	dev_set_name(&vdev->dev, "%s-%llu-%llu", bus_id_name,	311	dev_set_name(&vdev->dev, "%s-%llu-%llu", bus_id_name,
310	cfg_handle, id);	312	cfg_handle, id);
311	vdev->dev_no = *cfg_handle;	313	vdev->dev_no = *cfg_handle;
		314	vdev->id = *id;
312	}	315	}
313		316
314	vdev->dev.parent = parent;	317	vdev->dev.parent = parent;
@@ -351,27 +354,84 @@ static void vio_add(struct mdesc_handle *hp, u64 node) · 36 unmodified lines
351	(void) vio_create_one(hp, node, &root_vdev->dev);	354	(void) vio_create_one(hp, node, &root_vdev->dev);
352	}	355	}
353		356
		357	struct vio_md_node_query {
		358	const char *type;
		359	u64 dev_no;
		360	u64 id;
		361	};
		362
354	static int vio_md_node_match(struct device dev, void arg)	363	static int vio_md_node_match(struct device dev, void arg)
355	{	364	{
		365	struct vio_md_node_query query = (struct vio_md_node_query ) arg;
356	struct vio_dev *vdev = to_vio_dev(dev);	366	struct vio_dev *vdev = to_vio_dev(dev);
357		367
358	if (vdev->mp == (u64) arg)	368	if (vdev->dev_no != query->dev_no)
359	return 1;	369	return 0;
		370	if (vdev->id != query->id)
		371	return 0;
		372	if (strcmp(vdev->type, query->type))
		373	return 0;
360		374
361	return 0;	375	return 1;
362	}	376	}
363		377
364	static void vio_remove(struct mdesc_handle *hp, u64 node)	378	static void vio_remove(struct mdesc_handle *hp, u64 node)
365	{	379	{
		380	const char *type;
		381	const u64 id, cfg_handle;
		382	u64 a;
		383	struct vio_md_node_query query;
366	struct device *dev;	384	struct device *dev;
367		385
368	dev = device_find_child(&root_vdev->dev, (void *) node,	386	type = mdesc_get_property(hp, node, "device-type", NULL);
		387	if (!type) {
		388	type = mdesc_get_property(hp, node, "name", NULL);
		389	if (!type)
		390	type = mdesc_node_name(hp, node);
		391	}
		392
		393	query.type = type;
		394
		395	id = mdesc_get_property(hp, node, "id", NULL);
		396	cfg_handle = NULL;
		397	mdesc_for_each_arc(a, hp, node, MDESC_ARC_TYPE_BACK) {
		398	u64 target;
		399
		400	target = mdesc_arc_target(hp, a);
		401	cfg_handle = mdesc_get_property(hp, target,
		402	"cfg-handle", NULL);
		403	if (cfg_handle)
		404	break;
		405	}
		406
		407	if (!id) {
		408	query.dev_no = ~(u64)0;
		409	query.id = ~(u64)0;
		410	} else if (!cfg_handle) {
		411	query.dev_no = *id;
		412	query.id = ~(u64)0;
		413	} else {
		414	query.dev_no = *cfg_handle;
		415	query.id = *id;
		416	}
		417
		418	dev = device_find_child(&root_vdev->dev, &query,
369	vio_md_node_match);	419	vio_md_node_match);
370	if (dev) {	420	if (dev) {
371	printk(KERN_INFO "VIO: Removing device %s\n", dev_name(dev));	421	printk(KERN_INFO "VIO: Removing device %s\n", dev_name(dev));
372		422
373	device_unregister(dev);	423	device_unregister(dev);
374	put_device(dev);	424	put_device(dev);
		425	} else {
		426	if (!id)
		427	printk(KERN_ERR "VIO: Removed unknown %s node.\n",
		428	type);
		429	else if (!cfg_handle)
		430	printk(KERN_ERR "VIO: Removed unknown %s node %llu.\n",
		431	type, *id);
		432	else
		433	printk(KERN_ERR "VIO: Removed unknown %s node %llu-%llu.\n",
		434	type, cfg_handle, id);
375	}	435	}
376	}	436	}
377		437

arch/sparc/lib/Makefile+1−0

@@ -15,6 +15,7 @@ lib-$(CONFIG_SPARC32) += copy_user.o locks.o · 14 unmodified lines
15	lib-$(CONFIG_SPARC64) += atomic_64.o	15	lib-$(CONFIG_SPARC64) += atomic_64.o
16	lib-$(CONFIG_SPARC32) += lshrdi3.o ashldi3.o	16	lib-$(CONFIG_SPARC32) += lshrdi3.o ashldi3.o
17	lib-$(CONFIG_SPARC32) += muldi3.o bitext.o cmpdi2.o	17	lib-$(CONFIG_SPARC32) += muldi3.o bitext.o cmpdi2.o
		18	lib-$(CONFIG_SPARC64) += multi3.o
18		19
19	lib-$(CONFIG_SPARC64) += copy_page.o clear_page.o bzero.o	20	lib-$(CONFIG_SPARC64) += copy_page.o clear_page.o bzero.o
20	lib-$(CONFIG_SPARC64) += csum_copy.o csum_copy_from_user.o csum_copy_to_user.o	21	lib-$(CONFIG_SPARC64) += csum_copy.o csum_copy_from_user.o csum_copy_to_user.o

arch/sparc/lib/multi3.S+35−0

@@ -0,0 +1,35 @@
	1	#include <linux/linkage.h>
	2	#include <asm/export.h>
	3
	4	.text
	5	.align 4
	6	ENTRY(__multi3) /* %o0 = u, %o1 = v */
	7	mov %o1, %g1
	8	srl %o3, 0, %g4
	9	mulx %g4, %g1, %o1
	10	srlx %g1, 0x20, %g3
	11	mulx %g3, %g4, %g5
	12	sllx %g5, 0x20, %o5
	13	srl %g1, 0, %g4
	14	sub %o1, %o5, %o5
	15	srlx %o5, 0x20, %o5
	16	addcc %g5, %o5, %g5
	17	srlx %o3, 0x20, %o5
	18	mulx %g4, %o5, %g4
	19	mulx %g3, %o5, %o5
	20	sethi %hi(0x80000000), %g3
	21	addcc %g5, %g4, %g5
	22	srlx %g5, 0x20, %g5
	23	add %g3, %g3, %g3
	24	movcc %xcc, %g0, %g3
	25	addcc %o5, %g5, %o5
	26	sllx %g4, 0x20, %g4
	27	add %o1, %g4, %o1
	28	add %o5, %g3, %g2
	29	mulx %g1, %o2, %g1
	30	add %g1, %g2, %g1
	31	mulx %o0, %o3, %o0
	32	retl
	33	add %g1, %o0, %o0
	34	ENDPROC(__multi3)
	35	EXPORT_SYMBOL(__multi3)

arch/sparc/mm/hugetlbpage.c+1−1

@@ -120,7 +120,7 @@ hugetlb_get_unmapped_area(struct file *file, unsigned long addr, · 119 unmodified lines
120	addr = ALIGN(addr, huge_page_size(h));	120	addr = ALIGN(addr, huge_page_size(h));
121	vma = find_vma(mm, addr);	121	vma = find_vma(mm, addr);
122	if (task_size - len >= addr &&	122	if (task_size - len >= addr &&
123	(!vma \|\| addr + len <= vma->vm_start))	123	(!vma \|\| addr + len <= vm_start_gap(vma)))
124	return addr;	124	return addr;
125	}	125	}
126	if (mm->get_unmapped_area == arch_get_unmapped_area)	126	if (mm->get_unmapped_area == arch_get_unmapped_area)

arch/sparc/mm/init_64.c+60−29

 	}
 	if ((hv_pgsz_mask & cpu_pgsz_mask) == 0U) {
-		pr_warn("hugepagesz=%llu not supported by MMU.\n",
+		hugetlb_bad_size();
+		pr_err("hugepagesz=%llu not supported by MMU.\n",
 			hugepage_size);
 		goto out;
 	}
 /* get_new_mmu_context() uses "cache + 1".  */
 DEFINE_SPINLOCK(ctx_alloc_lock);
-unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
+unsigned long tlb_context_cache = CTX_FIRST_VERSION;
 #define MAX_CTX_NR	(1UL << CTX_NR_BITS)
 #define CTX_BMAP_SLOTS	BITS_TO_LONGS(MAX_CTX_NR)
 DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
+DEFINE_PER_CPU(struct mm_struct *, per_cpu_secondary_mm) = {0};
+static void mmu_context_wrap(void)
+{
+	unsigned long old_ver = tlb_context_cache & CTX_VERSION_MASK;
+	unsigned long new_ver, new_ctx, old_ctx;
+	struct mm_struct *mm;
+	int cpu;
+	bitmap_zero(mmu_context_bmap, 1 << CTX_NR_BITS);
+	/* Reserve kernel context */
+	set_bit(0, mmu_context_bmap);
+	new_ver = (tlb_context_cache & CTX_VERSION_MASK) + CTX_FIRST_VERSION;
+	if (unlikely(new_ver == 0))
+		new_ver = CTX_FIRST_VERSION;
+	tlb_context_cache = new_ver;
+	/*
+	 * Make sure that any new mm that are added into per_cpu_secondary_mm,
+	 * are going to go through get_new_mmu_context() path.
+	 */
+	mb();
+	/*
+	 * Updated versions to current on those CPUs that had valid secondary
+	 * contexts
+	 */
+	for_each_online_cpu(cpu) {
+		/*
+		 * If a new mm is stored after we took this mm from the array,
+		 * it will go into get_new_mmu_context() path, because we
+		 * already bumped the version in tlb_context_cache.
+		 */
+		mm = per_cpu(per_cpu_secondary_mm, cpu);
+		if (unlikely(!mm || mm == &init_mm))
+			continue;
+		old_ctx = mm->context.sparc64_ctx_val;
+		if (likely((old_ctx & CTX_VERSION_MASK) == old_ver)) {
+			new_ctx = (old_ctx & ~CTX_VERSION_MASK) | new_ver;
+			set_bit(new_ctx & CTX_NR_MASK, mmu_context_bmap);
+			mm->context.sparc64_ctx_val = new_ctx;
+		}
+	}
+}
 /* Caller does TLB context flushing on local CPU if necessary.
  * The caller also ensures that CTX_VALID(mm->context) is false.
 {
 	unsigned long ctx, new_ctx;
 	unsigned long orig_pgsz_bits;
-	int new_version;
 	spin_lock(&ctx_alloc_lock);
+retry:
+	/* wrap might have happened, test again if our context became valid */
+	if (unlikely(CTX_VALID(mm->context)))
+		goto out;
 	orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
 	ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
 	new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
-	new_version = 0;
 	if (new_ctx >= (1 << CTX_NR_BITS)) {
 		new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
 		if (new_ctx >= ctx) {
-			int i;
+			mmu_context_wrap();
-			new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
+			goto retry;
-				CTX_FIRST_VERSION;
-			if (new_ctx == 1)
-				new_ctx = CTX_FIRST_VERSION;
-			/* Don't call memset, for 16 entries that's just
-			 * plain silly...
-			 */
-			mmu_context_bmap[0] = 3;
-			mmu_context_bmap[1] = 0;
-			mmu_context_bmap[2] = 0;
-			mmu_context_bmap[3] = 0;
-			for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
-				mmu_context_bmap[i + 0] = 0;
-				mmu_context_bmap[i + 1] = 0;
-				mmu_context_bmap[i + 2] = 0;
-				mmu_context_bmap[i + 3] = 0;
-			}
-			new_version = 1;
-			goto out;
 		}
 	}
+	if (mm->context.sparc64_ctx_val)
+		cpumask_clear(mm_cpumask(mm));
 	mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
 	new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
-out:
 	tlb_context_cache = new_ctx;
 	mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
+out:
 	spin_unlock(&ctx_alloc_lock);
-	if (unlikely(new_version))
-		smp_new_mmu_context_version();
 }
 static int numa_enabled = 1;

arch/sparc/mm/tsb.c+5−2

 		extern void copy_tsb(unsigned long old_tsb_base,
 				     unsigned long old_tsb_size,
 				     unsigned long new_tsb_base,
-				     unsigned long new_tsb_size);
+				     unsigned long new_tsb_size,
+				     unsigned long page_size_shift);
 		unsigned long old_tsb_base = (unsigned long) old_tsb;
 		unsigned long new_tsb_base = (unsigned long) new_tsb;
 			old_tsb_base = __pa(old_tsb_base);
 			new_tsb_base = __pa(new_tsb_base);
 		}
-		copy_tsb(old_tsb_base, old_size, new_tsb_base, new_size);
+		copy_tsb(old_tsb_base, old_size, new_tsb_base, new_size,
+			tsb_index == MM_TSB_BASE ?
+			PAGE_SHIFT : REAL_HPAGE_SHIFT);
 	}
 	mm->context.tsb_block[tsb_index].tsb = new_tsb;

arch/sparc/mm/ultra.S+0−5

 	wr		%g0, (1 << PIL_SMP_CAPTURE), %set_softint
 	retry
-	.globl		xcall_new_mmu_context_version
-xcall_new_mmu_context_version:
-	wr		%g0, (1 << PIL_SMP_CTX_NEW_VERSION), %set_softint
-	retry
 #ifdef CONFIG_KGDB
 	.globl		xcall_kgdb_capture
 xcall_kgdb_capture:

arch/tile/mm/hugetlbpage.c+1−1

@@ -233,7 +233,7 @@ unsigned long hugetlb_get_unmapped_area(struct file *file, unsigned long addr, · 232 unmodified lines
233	addr = ALIGN(addr, huge_page_size(h));	233	addr = ALIGN(addr, huge_page_size(h));
234	vma = find_vma(mm, addr);	234	vma = find_vma(mm, addr);
235	if (TASK_SIZE - len >= addr &&	235	if (TASK_SIZE - len >= addr &&
236	(!vma \|\| addr + len <= vma->vm_start))	236	(!vma \|\| addr + len <= vm_start_gap(vma)))
237	return addr;	237	return addr;
238	}	238	}
239	if (current->mm->get_unmapped_area == arch_get_unmapped_area)	239	if (current->mm->get_unmapped_area == arch_get_unmapped_area)

arch/x86/Kconfig+0−4

 config SYSVIPC_COMPAT
 	def_bool y
 	depends on SYSVIPC
-config KEYS_COMPAT
-	def_bool y
-	depends on KEYS
 endif
 endmenu

arch/x86/include/asm/extable.h+1−0

@@ -29,6 +29,7 @@ struct pt_regs; · 28 unmodified lines
29	} while (0)	29	} while (0)
30		30
31	extern int fixup_exception(struct pt_regs *regs, int trapnr);	31	extern int fixup_exception(struct pt_regs *regs, int trapnr);
		32	extern int fixup_bug(struct pt_regs *regs, int trapnr);
32	extern bool ex_has_fault_handler(unsigned long ip);	33	extern bool ex_has_fault_handler(unsigned long ip);
33	extern void early_fixup_exception(struct pt_regs *regs, int trapnr);	34	extern void early_fixup_exception(struct pt_regs *regs, int trapnr);
34		35

arch/x86/kernel/cpu/cyrix.c+1−0

@@ -255,6 +255,7 @@ static void init_cyrix(struct cpuinfo_x86 *c) · 254 unmodified lines
255	break;	255	break;
256		256
257	case 4: /* MediaGX/GXm or Geode GXM/GXLV/GX1 */	257	case 4: /* MediaGX/GXm or Geode GXM/GXLV/GX1 */
		258	case 11: /* GX1 with inverted Device ID */
258	#ifdef CONFIG_PCI	259	#ifdef CONFIG_PCI
259	{	260	{
260	u32 vendor, device;	261	u32 vendor, device;

arch/x86/kernel/cpu/microcode/amd.c+8−8

 }
 static enum ucode_state
-load_microcode_amd(int cpu, u8 family, const u8 *data, size_t size);
+load_microcode_amd(bool save, u8 family, const u8 *data, size_t size);
 int __init save_microcode_in_initrd_amd(unsigned int cpuid_1_eax)
 {
 	if (!desc.mc)
 		return -EINVAL;
-	ret = load_microcode_amd(smp_processor_id(), x86_family(cpuid_1_eax),
+	ret = load_microcode_amd(true, x86_family(cpuid_1_eax), desc.data, desc.size);
-				 desc.data, desc.size);
 	if (ret != UCODE_OK)
 		return -EINVAL;
 }
 static enum ucode_state
-load_microcode_amd(int cpu, u8 family, const u8 *data, size_t size)
+load_microcode_amd(bool save, u8 family, const u8 *data, size_t size)
 {
 	enum ucode_state ret;
 #ifdef CONFIG_X86_32
 	/* save BSP's matching patch for early load */
-	if (cpu_data(cpu).cpu_index == boot_cpu_data.cpu_index) {
+	if (save) {
-		struct ucode_patch *p = find_patch(cpu);
+		struct ucode_patch *p = find_patch(0);
 		if (p) {
 			memset(amd_ucode_patch, 0, PATCH_MAX_SIZE);
 			memcpy(amd_ucode_patch, p->data, min_t(u32, ksize(p->data),
 {
 	char fw_name[36] = "amd-ucode/microcode_amd.bin";
 	struct cpuinfo_x86 *c = &cpu_data(cpu);
+	bool bsp = c->cpu_index == boot_cpu_data.cpu_index;
 	enum ucode_state ret = UCODE_NFOUND;
 	const struct firmware *fw;
 	/* reload ucode container only on the boot cpu */
-	if (!refresh_fw || c->cpu_index != boot_cpu_data.cpu_index)
+	if (!refresh_fw || !bsp)
 		return UCODE_OK;
 	if (c->x86 >= 0x15)
 		goto fw_release;
 	}
-	ret = load_microcode_amd(cpu, c->x86, fw->data, fw->size);
+	ret = load_microcode_amd(bsp, c->x86, fw->data, fw->size);
  fw_release:
 	release_firmware(fw);

arch/x86/kernel/cpu/microcode/intel.c+3−0

@@ -619,6 +619,9 @@ int __init save_microcode_in_initrd_intel(void) · 618 unmodified lines
619		619
620	show_saved_mc();	620	show_saved_mc();
621		621
		622	/* initrd is going away, clear patch ptr. */
		623	intel_ucode_patch = NULL;
		624
622	return 0;	625	return 0;
623	}	626	}
624		627

arch/x86/kernel/kvm.c+1−1

 			 */
 			rcu_irq_exit();
 			native_safe_halt();
-			rcu_irq_enter();
 			local_irq_disable();
+			rcu_irq_enter();
 		}
 	}
 	if (!n.halted)

arch/x86/kernel/process_32.c+1−1

@@ -78,7 +78,7 @@ void __show_regs(struct pt_regs *regs, int all) · 77 unmodified lines
78		78
79	printk(KERN_DEFAULT "EIP: %pS\n", (void *)regs->ip);	79	printk(KERN_DEFAULT "EIP: %pS\n", (void *)regs->ip);
80	printk(KERN_DEFAULT "EFLAGS: %08lx CPU: %d\n", regs->flags,	80	printk(KERN_DEFAULT "EFLAGS: %08lx CPU: %d\n", regs->flags,
81	smp_processor_id());	81	raw_smp_processor_id());
82		82
83	printk(KERN_DEFAULT "EAX: %08lx EBX: %08lx ECX: %08lx EDX: %08lx\n",	83	printk(KERN_DEFAULT "EAX: %08lx EBX: %08lx ECX: %08lx EDX: %08lx\n",
84	regs->ax, regs->bx, regs->cx, regs->dx);	84	regs->ax, regs->bx, regs->cx, regs->dx);

arch/x86/kernel/sys_x86_64.c+2−2

@@ -144,7 +144,7 @@ arch_get_unmapped_area(struct file *filp, unsigned long addr, · 143 unmodified lines
144	addr = PAGE_ALIGN(addr);	144	addr = PAGE_ALIGN(addr);
145	vma = find_vma(mm, addr);	145	vma = find_vma(mm, addr);
146	if (end - len >= addr &&	146	if (end - len >= addr &&
147	(!vma \|\| addr + len <= vma->vm_start))	147	(!vma \|\| addr + len <= vm_start_gap(vma)))
148	return addr;	148	return addr;
149	}	149	}
150		150
@@ -187,7 +187,7 @@ arch_get_unmapped_area_topdown(struct file *filp, const unsigned long addr0, · 36 unmodified lines
187	addr = PAGE_ALIGN(addr);	187	addr = PAGE_ALIGN(addr);
188	vma = find_vma(mm, addr);	188	vma = find_vma(mm, addr);
189	if (TASK_SIZE - len >= addr &&	189	if (TASK_SIZE - len >= addr &&
190	(!vma \|\| addr + len <= vma->vm_start))	190	(!vma \|\| addr + len <= vm_start_gap(vma)))
191	return addr;	191	return addr;
192	}	192	}
193		193

arch/x86/kernel/traps.c+1−1

@@ -182,7 +182,7 @@ int is_valid_bugaddr(unsigned long addr) · 181 unmodified lines
182	return ud == INSN_UD0 \|\| ud == INSN_UD2;	182	return ud == INSN_UD0 \|\| ud == INSN_UD2;
183	}	183	}
184		184
185	static int fixup_bug(struct pt_regs *regs, int trapnr)	185	int fixup_bug(struct pt_regs *regs, int trapnr)
186	{	186	{
187	if (trapnr != X86_TRAP_UD)	187	if (trapnr != X86_TRAP_UD)
188	return 0;	188	return 0;

arch/x86/kvm/cpuid.c+11−9

@@ -780,18 +780,20 @@ out: · 779 unmodified lines
780	static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)	780	static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
781	{	781	{
782	struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];	782	struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
783	int j, nent = vcpu->arch.cpuid_nent;	783	struct kvm_cpuid_entry2 *ej;
		784	int j = i;
		785	int nent = vcpu->arch.cpuid_nent;
784		786
785	e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;	787	e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
786	/* when no next entry is found, the current entry[i] is reselected */	788	/* when no next entry is found, the current entry[i] is reselected */
787	for (j = i + 1; ; j = (j + 1) % nent) {	789	do {
788	struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];	790	j = (j + 1) % nent;
789	if (ej->function == e->function) {	791	ej = &vcpu->arch.cpuid_entries[j];
790	ej->flags \|= KVM_CPUID_FLAG_STATE_READ_NEXT;	792	} while (ej->function != e->function);
791	return j;	793
792	}	794	ej->flags \|= KVM_CPUID_FLAG_STATE_READ_NEXT;
793	}	795
794	return 0; /* silence gcc, even though control never reaches here */	796	return j;
795	}	797	}
796		798
797	/* find an entry with matching function, matching index (if needed), and that	799	/* find an entry with matching function, matching index (if needed), and that

arch/x86/kvm/lapic.c+4−1

 static void cancel_hv_timer(struct kvm_lapic *apic)
 {
+	preempt_disable();
 	kvm_x86_ops->cancel_hv_timer(apic->vcpu);
 	apic->lapic_timer.hv_timer_in_use = false;
+	preempt_enable();
 }
 static bool start_hv_timer(struct kvm_lapic *apic)
 	for (i = 0; i < KVM_APIC_LVT_NUM; i++)
 		kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
 	apic_update_lvtt(apic);
-	if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_LINT0_REENABLED))
+	if (kvm_vcpu_is_reset_bsp(vcpu) &&
+	    kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_LINT0_REENABLED))
 		kvm_lapic_set_reg(apic, APIC_LVT0,
 			     SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
 	apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));

arch/x86/kvm/mmu.c+5−2

 	return kvm_setup_async_pf(vcpu, gva, kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch);
 }
-static bool can_do_async_pf(struct kvm_vcpu *vcpu)
+bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
 {
 	if (unlikely(!lapic_in_kernel(vcpu) ||
 		     kvm_event_needs_reinjection(vcpu)))
 		return false;
+	if (is_guest_mode(vcpu))
+		return false;
 	return kvm_x86_ops->interrupt_allowed(vcpu);
 }
 	if (!async)
 		return false; /* *pfn has correct page already */
-	if (!prefault && can_do_async_pf(vcpu)) {
+	if (!prefault && kvm_can_do_async_pf(vcpu)) {
 		trace_kvm_try_async_get_page(gva, gfn);
 		if (kvm_find_async_pf_gfn(vcpu, gfn)) {
 			trace_kvm_async_pf_doublefault(gva, gfn);

arch/x86/kvm/mmu.h+1−0

@@ -76,6 +76,7 @@ int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct); · 75 unmodified lines
76	void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu);	76	void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu);
77	void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly,	77	void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly,
78	bool accessed_dirty);	78	bool accessed_dirty);
		79	bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu);
79		80
80	static inline unsigned int kvm_mmu_available_pages(struct kvm *kvm)	81	static inline unsigned int kvm_mmu_available_pages(struct kvm *kvm)
81	{	82	{

arch/x86/kvm/svm.c+12−14

 	 * AMD's VMCB does not have an explicit unusable field, so emulate it
 	 * for cross vendor migration purposes by "not present"
 	 */
-	var->unusable = !var->present || (var->type == 0);
+	var->unusable = !var->present;
 	switch (seg) {
 	case VCPU_SREG_TR:
 		 */
 		if (var->unusable)
 			var->db = 0;
+		/* This is symmetric with svm_set_segment() */
 		var->dpl = to_svm(vcpu)->vmcb->save.cpl;
 		break;
 	}
 	s->base = var->base;
 	s->limit = var->limit;
 	s->selector = var->selector;
-	if (var->unusable)
+	s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
-		s->attrib = 0;
+	s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
-	else {
+	s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
-		s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
+	s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
-		s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
+	s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
-		s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
+	s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
-		s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
+	s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
-		s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
+	s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
-		s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
-		s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
-		s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
-	}
 	/*
 	 * This is always accurate, except if SYSRET returned to a segment
 	 * would entail passing the CPL to userspace and back.
 	 */
 	if (seg == VCPU_SREG_SS)
-		svm->vmcb->save.cpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
+		/* This is symmetric with svm_get_segment() */
+		svm->vmcb->save.cpl = (var->dpl & 3);
 	mark_dirty(svm->vmcb, VMCB_SEG);
 }

arch/x86/kvm/vmx.c+63−86

 	if (!(vmcs12->exception_bitmap & (1u << nr)))
 		return 0;
-	nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
+	nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
 			  vmcs_read32(VM_EXIT_INTR_INFO),
 			  vmcs_readl(EXIT_QUALIFICATION));
 	return 1;
 	return 0;
 }
-/*
+static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu, gpa_t *vmpointer)
- * This function performs the various checks including
- * - if it's 4KB aligned
- * - No bits beyond the physical address width are set
- * - Returns 0 on success or else 1
- * (Intel SDM Section 30.3)
- */
-static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
-				  gpa_t *vmpointer)
 {
 	gva_t gva;
-	gpa_t vmptr;
 	struct x86_exception e;
-	struct page *page;
-	struct vcpu_vmx *vmx = to_vmx(vcpu);
-	int maxphyaddr = cpuid_maxphyaddr(vcpu);
 	if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
 			vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
 		return 1;
-	if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
+	if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, vmpointer,
-				sizeof(vmptr), &e)) {
+				sizeof(*vmpointer), &e)) {
 		kvm_inject_page_fault(vcpu, &e);
 		return 1;
 	}
-	switch (exit_reason) {
-	case EXIT_REASON_VMON:
-		/*
-		 * SDM 3: 24.11.5
-		 * The first 4 bytes of VMXON region contain the supported
-		 * VMCS revision identifier
-		 *
-		 * Note - IA32_VMX_BASIC[48] will never be 1
-		 * for the nested case;
-		 * which replaces physical address width with 32
-		 *
-		 */
-		if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
-			nested_vmx_failInvalid(vcpu);
-			return kvm_skip_emulated_instruction(vcpu);
-		}
-		page = nested_get_page(vcpu, vmptr);
-		if (page == NULL) {
-			nested_vmx_failInvalid(vcpu);
-			return kvm_skip_emulated_instruction(vcpu);
-		}
-		if (*(u32 *)kmap(page) != VMCS12_REVISION) {
-			kunmap(page);
-			nested_release_page_clean(page);
-			nested_vmx_failInvalid(vcpu);
-			return kvm_skip_emulated_instruction(vcpu);
-		}
-		kunmap(page);
-		nested_release_page_clean(page);
-		vmx->nested.vmxon_ptr = vmptr;
-		break;
-	case EXIT_REASON_VMCLEAR:
-		if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
-			nested_vmx_failValid(vcpu,
-					     VMXERR_VMCLEAR_INVALID_ADDRESS);
-			return kvm_skip_emulated_instruction(vcpu);
-		}
-		if (vmptr == vmx->nested.vmxon_ptr) {
-			nested_vmx_failValid(vcpu,
-					     VMXERR_VMCLEAR_VMXON_POINTER);
-			return kvm_skip_emulated_instruction(vcpu);
-		}
-		break;
-	case EXIT_REASON_VMPTRLD:
-		if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
-			nested_vmx_failValid(vcpu,
-					     VMXERR_VMPTRLD_INVALID_ADDRESS);
-			return kvm_skip_emulated_instruction(vcpu);
-		}
-		if (vmptr == vmx->nested.vmxon_ptr) {
-			nested_vmx_failValid(vcpu,
-					     VMXERR_VMPTRLD_VMXON_POINTER);
-			return kvm_skip_emulated_instruction(vcpu);
-		}
-		break;
-	default:
-		return 1; /* shouldn't happen */
-	}
-	if (vmpointer)
-		*vmpointer = vmptr;
 	return 0;
 }
 static int handle_vmon(struct kvm_vcpu *vcpu)
 {
 	int ret;
+	gpa_t vmptr;
+	struct page *page;
 	struct vcpu_vmx *vmx = to_vmx(vcpu);
 	const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
 		| FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
 		return 1;
 	}
-	if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
+	if (nested_vmx_get_vmptr(vcpu, &vmptr))
 		return 1;
+	/*
+	 * SDM 3: 24.11.5
+	 * The first 4 bytes of VMXON region contain the supported
+	 * VMCS revision identifier
+	 *
+	 * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
+	 * which replaces physical address width with 32
+	 */
+	if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
+		nested_vmx_failInvalid(vcpu);
+		return kvm_skip_emulated_instruction(vcpu);
+	}
+	page = nested_get_page(vcpu, vmptr);
+	if (page == NULL) {
+		nested_vmx_failInvalid(vcpu);
+		return kvm_skip_emulated_instruction(vcpu);
+	}
+	if (*(u32 *)kmap(page) != VMCS12_REVISION) {
+		kunmap(page);
+		nested_release_page_clean(page);
+		nested_vmx_failInvalid(vcpu);
+		return kvm_skip_emulated_instruction(vcpu);
+	}
+	kunmap(page);
+	nested_release_page_clean(page);
+	vmx->nested.vmxon_ptr = vmptr;
 	ret = enter_vmx_operation(vcpu);
 	if (ret)
 		return ret;
 	if (!nested_vmx_check_permission(vcpu))
 		return 1;
-	if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
+	if (nested_vmx_get_vmptr(vcpu, &vmptr))
 		return 1;
+	if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
+		nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
+		return kvm_skip_emulated_instruction(vcpu);
+	}
+	if (vmptr == vmx->nested.vmxon_ptr) {
+		nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_VMXON_POINTER);
+		return kvm_skip_emulated_instruction(vcpu);
+	}
 	if (vmptr == vmx->nested.current_vmptr)
 		nested_release_vmcs12(vmx);
 	if (!nested_vmx_check_permission(vcpu))
 		return 1;
-	if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
+	if (nested_vmx_get_vmptr(vcpu, &vmptr))
 		return 1;
+	if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
+		nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
+		return kvm_skip_emulated_instruction(vcpu);
+	}
+	if (vmptr == vmx->nested.vmxon_ptr) {
+		nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_VMXON_POINTER);
+		return kvm_skip_emulated_instruction(vcpu);
+	}
 	if (vmx->nested.current_vmptr != vmptr) {
 		struct vmcs12 *new_vmcs12;
 		struct page *page;
 {
 	unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
 	int cr = exit_qualification & 15;
-	int reg = (exit_qualification >> 8) & 15;
+	int reg;
-	unsigned long val = kvm_register_readl(vcpu, reg);
+	unsigned long val;
 	switch ((exit_qualification >> 4) & 3) {
 	case 0: /* mov to cr */
+		reg = (exit_qualification >> 8) & 15;
+		val = kvm_register_readl(vcpu, reg);
 		switch (cr) {
 		case 0:
 			if (vmcs12->cr0_guest_host_mask &
 		 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
 		 * cr0. Other attempted changes are ignored, with no exit.
 		 */
+		val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
 		if (vmcs12->cr0_guest_host_mask & 0xe &
 		    (val ^ vmcs12->cr0_read_shadow))
 			return true;

arch/x86/kvm/x86.c+6−4

 	if (vcpu->arch.pv.pv_unhalted)
 		return true;
-	if (atomic_read(&vcpu->arch.nmi_queued))
+	if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
+	    (vcpu->arch.nmi_pending &&
+	     kvm_x86_ops->nmi_allowed(vcpu)))
 		return true;
-	if (kvm_test_request(KVM_REQ_SMI, vcpu))
+	if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
+	    (vcpu->arch.smi_pending && !is_smm(vcpu)))
 		return true;
 	if (kvm_arch_interrupt_allowed(vcpu) &&
 	if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
 		return true;
 	else
-		return !kvm_event_needs_reinjection(vcpu) &&
+		return kvm_can_do_async_pf(vcpu);
-			kvm_x86_ops->interrupt_allowed(vcpu);
 }
 void kvm_arch_start_assignment(struct kvm *kvm)

arch/x86/mm/extable.c+3−0

@@ -162,6 +162,9 @@ void __init early_fixup_exception(struct pt_regs *regs, int trapnr) · 161 unmodified lines
162	if (fixup_exception(regs, trapnr))	162	if (fixup_exception(regs, trapnr))
163	return;	163	return;
164		164
		165	if (fixup_bug(regs, trapnr))
		166	return;
		167
165	fail:	168	fail:
166	early_printk("PANIC: early exception 0x%02x IP %lx:%lx error %lx cr2 0x%lx\n",	169	early_printk("PANIC: early exception 0x%02x IP %lx:%lx error %lx cr2 0x%lx\n",
167	(unsigned)trapnr, (unsigned long)regs->cs, regs->ip,	170	(unsigned)trapnr, (unsigned long)regs->cs, regs->ip,

arch/x86/mm/hugetlbpage.c+1−1

@@ -148,7 +148,7 @@ hugetlb_get_unmapped_area(struct file *file, unsigned long addr, · 147 unmodified lines
148	addr = ALIGN(addr, huge_page_size(h));	148	addr = ALIGN(addr, huge_page_size(h));
149	vma = find_vma(mm, addr);	149	vma = find_vma(mm, addr);
150	if (TASK_SIZE - len >= addr &&	150	if (TASK_SIZE - len >= addr &&
151	(!vma \|\| addr + len <= vma->vm_start))	151	(!vma \|\| addr + len <= vm_start_gap(vma)))
152	return addr;	152	return addr;
153	}	153	}
154	if (mm->get_unmapped_area == arch_get_unmapped_area)	154	if (mm->get_unmapped_area == arch_get_unmapped_area)

arch/x86/mm/init.c+3−3

 static void __init probe_page_size_mask(void)
 {
-#if !defined(CONFIG_KMEMCHECK)
 	/*
 	 * For CONFIG_KMEMCHECK or pagealloc debugging, identity mapping will
 	 * use small pages.
 	 * This will simplify cpa(), which otherwise needs to support splitting
 	 * large pages into small in interrupt context, etc.
 	 */
-	if (boot_cpu_has(X86_FEATURE_PSE) && !debug_pagealloc_enabled())
+	if (boot_cpu_has(X86_FEATURE_PSE) && !debug_pagealloc_enabled() && !IS_ENABLED(CONFIG_KMEMCHECK))
 		page_size_mask |= 1 << PG_LEVEL_2M;
-#endif
+	else
+		direct_gbpages = 0;
 	/* Enable PSE if available */
 	if (boot_cpu_has(X86_FEATURE_PSE))

arch/x86/mm/pat.c+3−6

 }
 early_param("nopat", nopat);
-static bool __read_mostly __pat_initialized = false;
 bool pat_enabled(void)
 {
-	return __pat_initialized;
+	return !!__pat_enabled;
 }
 EXPORT_SYMBOL_GPL(pat_enabled);
 	}
 	wrmsrl(MSR_IA32_CR_PAT, pat);
-	__pat_initialized = true;
 	__init_cache_modes(pat);
 }
 static void pat_ap_init(u64 pat)
 {
-	if (!this_cpu_has(X86_FEATURE_PAT)) {
+	if (!boot_cpu_has(X86_FEATURE_PAT)) {
 		/*
 		 * If this happens we are on a secondary CPU, but switched to
 		 * PAT on the boot CPU. We have no way to undo PAT.
 	u64 pat;
 	struct cpuinfo_x86 *c = &boot_cpu_data;
-	if (!__pat_enabled) {
+	if (!pat_enabled()) {
 		init_cache_modes();
 		return;
 	}

arch/x86/platform/efi/efi.c+4−2

 	/*
 	 * We don't do virtual mode, since we don't do runtime services, on
-	 * non-native EFI
+	 * non-native EFI. With efi=old_map, we don't do runtime services in
+	 * kexec kernel because in the initial boot something else might
+	 * have been mapped at these virtual addresses.
 	 */
-	if (!efi_is_native()) {
+	if (!efi_is_native() || efi_enabled(EFI_OLD_MEMMAP)) {
 		efi_memmap_unmap();
 		clear_bit(EFI_RUNTIME_SERVICES, &efi.flags);
 		return;

arch/x86/platform/efi/efi_64.c+71−8

@@ -71,11 +71,13 @@ static void __init early_code_mapping_set_exec(int executable) · 70 unmodified lines
71		71
72	pgd_t * __init efi_call_phys_prolog(void)	72	pgd_t * __init efi_call_phys_prolog(void)
73	{	73	{
74	unsigned long vaddress;	74	unsigned long vaddr, addr_pgd, addr_p4d, addr_pud;
75	pgd_t *save_pgd;	75	pgd_t save_pgd, pgd_k, *pgd_efi;
		76	p4d_t p4d, p4d_k, *p4d_efi;
		77	pud_t *pud;
76		78
77	int pgd;	79	int pgd;
78	int n_pgds;	80	int n_pgds, i, j;
79		81
80	if (!efi_enabled(EFI_OLD_MEMMAP)) {	82	if (!efi_enabled(EFI_OLD_MEMMAP)) {
81	save_pgd = (pgd_t *)read_cr3();	83	save_pgd = (pgd_t *)read_cr3();
@@ -88,10 +90,49 @@ pgd_t * __init efi_call_phys_prolog(void) · 6 unmodified lines
88	n_pgds = DIV_ROUND_UP((max_pfn << PAGE_SHIFT), PGDIR_SIZE);	90	n_pgds = DIV_ROUND_UP((max_pfn << PAGE_SHIFT), PGDIR_SIZE);
89	save_pgd = kmalloc_array(n_pgds, sizeof(*save_pgd), GFP_KERNEL);	91	save_pgd = kmalloc_array(n_pgds, sizeof(*save_pgd), GFP_KERNEL);
90		92
		93	/*
		94	* Build 1:1 identity mapping for efi=old_map usage. Note that
		95	* PAGE_OFFSET is PGDIR_SIZE aligned when KASLR is disabled, while
		96	* it is PUD_SIZE ALIGNED with KASLR enabled. So for a given physical
		97	* address X, the pud_index(X) != pud_index(__va(X)), we can only copy
		98	* PUD entry of __va(X) to fill in pud entry of X to build 1:1 mapping.
		99	* This means here we can only reuse the PMD tables of the direct mapping.
		100	*/
91	for (pgd = 0; pgd < n_pgds; pgd++) {	101	for (pgd = 0; pgd < n_pgds; pgd++) {
92	save_pgd[pgd] = pgd_offset_k(pgd PGDIR_SIZE);	102	addr_pgd = (unsigned long)(pgd * PGDIR_SIZE);
93	vaddress = (unsigned long)__va(pgd * PGDIR_SIZE);	103	vaddr = (unsigned long)__va(pgd * PGDIR_SIZE);
94	set_pgd(pgd_offset_k(pgd * PGDIR_SIZE), *pgd_offset_k(vaddress));	104	pgd_efi = pgd_offset_k(addr_pgd);
		105	save_pgd[pgd] = *pgd_efi;
		106
		107	p4d = p4d_alloc(&init_mm, pgd_efi, addr_pgd);
		108	if (!p4d) {
		109	pr_err("Failed to allocate p4d table!\n");
		110	goto out;
		111	}
		112
		113	for (i = 0; i < PTRS_PER_P4D; i++) {
		114	addr_p4d = addr_pgd + i * P4D_SIZE;
		115	p4d_efi = p4d + p4d_index(addr_p4d);
		116
		117	pud = pud_alloc(&init_mm, p4d_efi, addr_p4d);
		118	if (!pud) {
		119	pr_err("Failed to allocate pud table!\n");
		120	goto out;
		121	}
		122
		123	for (j = 0; j < PTRS_PER_PUD; j++) {
		124	addr_pud = addr_p4d + j * PUD_SIZE;
		125
		126	if (addr_pud > (max_pfn << PAGE_SHIFT))
		127	break;
		128
		129	vaddr = (unsigned long)__va(addr_pud);
		130
		131	pgd_k = pgd_offset_k(vaddr);
		132	p4d_k = p4d_offset(pgd_k, vaddr);
		133	pud[j] = *pud_offset(p4d_k, vaddr);
		134	}
		135	}
95	}	136	}
96	out:	137	out:
97	__flush_tlb_all();	138	__flush_tlb_all();
@@ -104,8 +145,11 @@ void __init efi_call_phys_epilog(pgd_t *save_pgd) · 6 unmodified lines
104	/*	145	/*
105	* After the lock is released, the original page table is restored.	146	* After the lock is released, the original page table is restored.
106	*/	147	*/
107	int pgd_idx;	148	int pgd_idx, i;
108	int nr_pgds;	149	int nr_pgds;
		150	pgd_t *pgd;
		151	p4d_t *p4d;
		152	pud_t *pud;
109		153
110	if (!efi_enabled(EFI_OLD_MEMMAP)) {	154	if (!efi_enabled(EFI_OLD_MEMMAP)) {
111	write_cr3((unsigned long)save_pgd);	155	write_cr3((unsigned long)save_pgd);
@@ -115,9 +159,28 @@ void __init efi_call_phys_epilog(pgd_t *save_pgd) · 3 unmodified lines
115		159
116	nr_pgds = DIV_ROUND_UP((max_pfn << PAGE_SHIFT) , PGDIR_SIZE);	160	nr_pgds = DIV_ROUND_UP((max_pfn << PAGE_SHIFT) , PGDIR_SIZE);
117		161
118	for (pgd_idx = 0; pgd_idx < nr_pgds; pgd_idx++)	162	for (pgd_idx = 0; pgd_idx < nr_pgds; pgd_idx++) {
		163	pgd = pgd_offset_k(pgd_idx * PGDIR_SIZE);
119	set_pgd(pgd_offset_k(pgd_idx * PGDIR_SIZE), save_pgd[pgd_idx]);	164	set_pgd(pgd_offset_k(pgd_idx * PGDIR_SIZE), save_pgd[pgd_idx]);
120		165
		166	if (!(pgd_val(*pgd) & _PAGE_PRESENT))
		167	continue;
		168
		169	for (i = 0; i < PTRS_PER_P4D; i++) {
		170	p4d = p4d_offset(pgd,
		171	pgd_idx * PGDIR_SIZE + i * P4D_SIZE);
		172
		173	if (!(p4d_val(*p4d) & _PAGE_PRESENT))
		174	continue;
		175
		176	pud = (pud_t )p4d_page_vaddr(p4d);
		177	pud_free(&init_mm, pud);
		178	}
		179
		180	p4d = (p4d_t )pgd_page_vaddr(pgd);
		181	p4d_free(&init_mm, p4d);
		182	}
		183
121	kfree(save_pgd);	184	kfree(save_pgd);
122		185
123	__flush_tlb_all();	186	__flush_tlb_all();

arch/x86/platform/efi/quirks.c+3−0

@@ -360,6 +360,9 @@ void __init efi_free_boot_services(void) · 359 unmodified lines
360	free_bootmem_late(start, size);	360	free_bootmem_late(start, size);
361	}	361	}
362		362
		363	if (!num_entries)
		364	return;
		365
363	new_size = efi.memmap.desc_size * num_entries;	366	new_size = efi.memmap.desc_size * num_entries;
364	new_phys = efi_memmap_alloc(num_entries);	367	new_phys = efi_memmap_alloc(num_entries);
365	if (!new_phys) {	368	if (!new_phys) {

arch/xtensa/include/asm/irq.h+2−1

@@ -29,7 +29,8 @@ static inline void variant_irq_disable(unsigned int irq) { } · 28 unmodified lines
29	# define PLATFORM_NR_IRQS 0	29	# define PLATFORM_NR_IRQS 0
30	#endif	30	#endif
31	#define XTENSA_NR_IRQS XCHAL_NUM_INTERRUPTS	31	#define XTENSA_NR_IRQS XCHAL_NUM_INTERRUPTS
32	#define NR_IRQS (XTENSA_NR_IRQS + VARIANT_NR_IRQS + PLATFORM_NR_IRQS)	32	#define NR_IRQS (XTENSA_NR_IRQS + VARIANT_NR_IRQS + PLATFORM_NR_IRQS + 1)
		33	#define XTENSA_PIC_LINUX_IRQ(hwirq) ((hwirq) + 1)
33		34
34	#if VARIANT_NR_IRQS == 0	35	#if VARIANT_NR_IRQS == 0
35	static inline void variant_init_irq(void) { }	36	static inline void variant_init_irq(void) { }

arch/xtensa/kernel/irq.c+0−5

 {
 	int irq = irq_find_mapping(NULL, hwirq);
-	if (hwirq >= NR_IRQS) {
-		printk(KERN_EMERG "%s: cannot handle IRQ %d\n",
-				__func__, hwirq);
-	}
 #ifdef CONFIG_DEBUG_STACKOVERFLOW
 	/* Debugging check for stack overflow: is there less than 1KB free? */
 	{

arch/xtensa/kernel/setup.c+1−2

@@ -593,8 +593,7 @@ c_show(struct seq_file f, void slot) · 592 unmodified lines
593	(ccount_freq/10000) % 100,	593	(ccount_freq/10000) % 100,
594	loops_per_jiffy/(500000/HZ),	594	loops_per_jiffy/(500000/HZ),
595	(loops_per_jiffy/(5000/HZ)) % 100);	595	(loops_per_jiffy/(5000/HZ)) % 100);
596		596	seq_puts(f, "flags\t\t: "
597	seq_printf(f,"flags\t\t: "
598	#if XCHAL_HAVE_NMI	597	#if XCHAL_HAVE_NMI
599	"nmi "	598	"nmi "
600	#endif	599	#endif

arch/xtensa/kernel/syscall.c+1−1

@@ -88,7 +88,7 @@ unsigned long arch_get_unmapped_area(struct file *filp, unsigned long addr, · 87 unmodified lines
88	/* At this point: (!vmm \|\| addr < vmm->vm_end). */	88	/* At this point: (!vmm \|\| addr < vmm->vm_end). */
89	if (TASK_SIZE - len < addr)	89	if (TASK_SIZE - len < addr)
90	return -ENOMEM;	90	return -ENOMEM;
91	if (!vmm \|\| addr + len <= vmm->vm_start)	91	if (!vmm \|\| addr + len <= vm_start_gap(vmm))
92	return addr;	92	return addr;
93	addr = vmm->vm_end;	93	addr = vmm->vm_end;
94	if (flags & MAP_SHARED)	94	if (flags & MAP_SHARED)

arch/xtensa/kernel/vmlinux.lds.S+3−3

@@ -118,7 +118,7 @@ SECTIONS · 117 unmodified lines
118	SECTION_VECTOR (.KernelExceptionVector.text, KERNEL_VECTOR_VADDR)	118	SECTION_VECTOR (.KernelExceptionVector.text, KERNEL_VECTOR_VADDR)
119	SECTION_VECTOR (.UserExceptionVector.literal, USER_VECTOR_VADDR - 4)	119	SECTION_VECTOR (.UserExceptionVector.literal, USER_VECTOR_VADDR - 4)
120	SECTION_VECTOR (.UserExceptionVector.text, USER_VECTOR_VADDR)	120	SECTION_VECTOR (.UserExceptionVector.text, USER_VECTOR_VADDR)
121	SECTION_VECTOR (.DoubleExceptionVector.literal, DOUBLEEXC_VECTOR_VADDR - 48)	121	SECTION_VECTOR (.DoubleExceptionVector.literal, DOUBLEEXC_VECTOR_VADDR - 20)
122	SECTION_VECTOR (.DoubleExceptionVector.text, DOUBLEEXC_VECTOR_VADDR)	122	SECTION_VECTOR (.DoubleExceptionVector.text, DOUBLEEXC_VECTOR_VADDR)
123	#endif	123	#endif
124		124
@@ -306,13 +306,13 @@ SECTIONS · 181 unmodified lines
306	.UserExceptionVector.literal)	306	.UserExceptionVector.literal)
307	SECTION_VECTOR (_DoubleExceptionVector_literal,	307	SECTION_VECTOR (_DoubleExceptionVector_literal,
308	.DoubleExceptionVector.literal,	308	.DoubleExceptionVector.literal,
309	DOUBLEEXC_VECTOR_VADDR - 48,	309	DOUBLEEXC_VECTOR_VADDR - 20,
310	SIZEOF(.UserExceptionVector.text),	310	SIZEOF(.UserExceptionVector.text),
311	.UserExceptionVector.text)	311	.UserExceptionVector.text)
312	SECTION_VECTOR (_DoubleExceptionVector_text,	312	SECTION_VECTOR (_DoubleExceptionVector_text,
313	.DoubleExceptionVector.text,	313	.DoubleExceptionVector.text,
314	DOUBLEEXC_VECTOR_VADDR,	314	DOUBLEEXC_VECTOR_VADDR,
315	48,	315	20,
316	.DoubleExceptionVector.literal)	316	.DoubleExceptionVector.literal)
317		317
318	. = (LOADADDR( .DoubleExceptionVector.text ) + SIZEOF( .DoubleExceptionVector.text ) + 3) & ~ 3;	318	. = (LOADADDR( .DoubleExceptionVector.text ) + SIZEOF( .DoubleExceptionVector.text ) + 3) & ~ 3;

arch/xtensa/platforms/iss/simdisk.c+1−2

@@ -317,8 +317,7 @@ static int __init simdisk_init(void) · 316 unmodified lines
317	if (simdisk_count > MAX_SIMDISK_COUNT)	317	if (simdisk_count > MAX_SIMDISK_COUNT)
318	simdisk_count = MAX_SIMDISK_COUNT;	318	simdisk_count = MAX_SIMDISK_COUNT;
319		319
320	sddev = kmalloc(simdisk_count * sizeof(struct simdisk),	320	sddev = kmalloc_array(simdisk_count, sizeof(*sddev), GFP_KERNEL);
321	GFP_KERNEL);
322	if (sddev == NULL)	321	if (sddev == NULL)
323	goto out_unregister;	322	goto out_unregister;
324		323

arch/xtensa/platforms/xtfpga/include/platform/hardware.h+4−2

@@ -24,16 +24,18 @@ · 23 unmodified lines
24		24
25	/* Interrupt configuration. */	25	/* Interrupt configuration. */
26		26
27	#define PLATFORM_NR_IRQS 10	27	#define PLATFORM_NR_IRQS 0
28		28
29	/* Default assignment of LX60 devices to external interrupts. */	29	/* Default assignment of LX60 devices to external interrupts. */
30		30
31	#ifdef CONFIG_XTENSA_MX	31	#ifdef CONFIG_XTENSA_MX
32	#define DUART16552_INTNUM XCHAL_EXTINT3_NUM	32	#define DUART16552_INTNUM XCHAL_EXTINT3_NUM
33	#define OETH_IRQ XCHAL_EXTINT4_NUM	33	#define OETH_IRQ XCHAL_EXTINT4_NUM
		34	#define C67X00_IRQ XCHAL_EXTINT8_NUM
34	#else	35	#else
35	#define DUART16552_INTNUM XCHAL_EXTINT0_NUM	36	#define DUART16552_INTNUM XCHAL_EXTINT0_NUM
36	#define OETH_IRQ XCHAL_EXTINT1_NUM	37	#define OETH_IRQ XCHAL_EXTINT1_NUM
		38	#define C67X00_IRQ XCHAL_EXTINT5_NUM
37	#endif	39	#endif
38		40
39	/*	41	/*
@@ -63,5 +65,5 @@ · 23 unmodified lines
63		65
64	#define C67X00_PADDR (XCHAL_KIO_PADDR + 0x0D0D0000)	66	#define C67X00_PADDR (XCHAL_KIO_PADDR + 0x0D0D0000)
65	#define C67X00_SIZE 0x10	67	#define C67X00_SIZE 0x10
66	#define C67X00_IRQ 5	68
67	#endif /* __XTENSA_XTAVNET_HARDWARE_H */	69	#endif /* __XTENSA_XTAVNET_HARDWARE_H */

arch/xtensa/platforms/xtfpga/setup.c+5−5

@@ -175,8 +175,8 @@ static struct resource ethoc_res[] = { · 174 unmodified lines
175	.flags = IORESOURCE_MEM,	175	.flags = IORESOURCE_MEM,
176	},	176	},
177	[2] = { /* IRQ number */	177	[2] = { /* IRQ number */
178	.start = OETH_IRQ,	178	.start = XTENSA_PIC_LINUX_IRQ(OETH_IRQ),
179	.end = OETH_IRQ,	179	.end = XTENSA_PIC_LINUX_IRQ(OETH_IRQ),
180	.flags = IORESOURCE_IRQ,	180	.flags = IORESOURCE_IRQ,
181	},	181	},
182	};	182	};
@@ -213,8 +213,8 @@ static struct resource c67x00_res[] = { · 30 unmodified lines
213	.flags = IORESOURCE_MEM,	213	.flags = IORESOURCE_MEM,
214	},	214	},
215	[1] = { /* IRQ number */	215	[1] = { /* IRQ number */
216	.start = C67X00_IRQ,	216	.start = XTENSA_PIC_LINUX_IRQ(C67X00_IRQ),
217	.end = C67X00_IRQ,	217	.end = XTENSA_PIC_LINUX_IRQ(C67X00_IRQ),
218	.flags = IORESOURCE_IRQ,	218	.flags = IORESOURCE_IRQ,
219	},	219	},
220	};	220	};
@@ -247,7 +247,7 @@ static struct resource serial_resource = { · 26 unmodified lines
247	static struct plat_serial8250_port serial_platform_data[] = {	247	static struct plat_serial8250_port serial_platform_data[] = {
248	[0] = {	248	[0] = {
249	.mapbase = DUART16552_PADDR,	249	.mapbase = DUART16552_PADDR,
250	.irq = DUART16552_INTNUM,	250	.irq = XTENSA_PIC_LINUX_IRQ(DUART16552_INTNUM),
251	.flags = UPF_BOOT_AUTOCONF \| UPF_SKIP_TEST \|	251	.flags = UPF_BOOT_AUTOCONF \| UPF_SKIP_TEST \|
252	UPF_IOREMAP,	252	UPF_IOREMAP,
253	.iotype = XCHAL_HAVE_BE ? UPIO_MEM32BE : UPIO_MEM32,	253	.iotype = XCHAL_HAVE_BE ? UPIO_MEM32BE : UPIO_MEM32,

block/bfq-cgroup.c+93−23

 BFQG_FLAG_FNS(empty)
 #undef BFQG_FLAG_FNS
-/* This should be called with the queue_lock held. */
+/* This should be called with the scheduler lock held. */
 static void bfqg_stats_update_group_wait_time(struct bfqg_stats *stats)
 {
 	unsigned long long now;
 	bfqg_stats_clear_waiting(stats);
 }
-/* This should be called with the queue_lock held. */
+/* This should be called with the scheduler lock held. */
 static void bfqg_stats_set_start_group_wait_time(struct bfq_group *bfqg,
 						 struct bfq_group *curr_bfqg)
 {
 	bfqg_stats_mark_waiting(stats);
 }
-/* This should be called with the queue_lock held. */
+/* This should be called with the scheduler lock held. */
 static void bfqg_stats_end_empty_time(struct bfqg_stats *stats)
 {
 	unsigned long long now;
 static void bfqg_get(struct bfq_group *bfqg)
 {
-	return blkg_get(bfqg_to_blkg(bfqg));
+	bfqg->ref++;
 }
 void bfqg_put(struct bfq_group *bfqg)
 {
-	return blkg_put(bfqg_to_blkg(bfqg));
+	bfqg->ref--;
+	if (bfqg->ref == 0)
+		kfree(bfqg);
+}
+static void bfqg_and_blkg_get(struct bfq_group *bfqg)
+{
+	/* see comments in bfq_bic_update_cgroup for why refcounting bfqg */
+	bfqg_get(bfqg);
+	blkg_get(bfqg_to_blkg(bfqg));
+}
+void bfqg_and_blkg_put(struct bfq_group *bfqg)
+{
+	bfqg_put(bfqg);
+	blkg_put(bfqg_to_blkg(bfqg));
 }
 void bfqg_stats_update_io_add(struct bfq_group *bfqg, struct bfq_queue *bfqq,
 	if (bfqq) {
 		bfqq->ioprio = bfqq->new_ioprio;
 		bfqq->ioprio_class = bfqq->new_ioprio_class;
-		bfqg_get(bfqg);
+		/*
+		 * Make sure that bfqg and its associated blkg do not
+		 * disappear before entity.
+		 */
+		bfqg_and_blkg_get(bfqg);
 	}
 	entity->parent = bfqg->my_entity; /* NULL for root group */
 	entity->sched_data = &bfqg->sched_data;
 		return NULL;
 	}
+	/* see comments in bfq_bic_update_cgroup for why refcounting */
+	bfqg_get(bfqg);
 	return &bfqg->pd;
 }
 	struct bfq_group *bfqg = pd_to_bfqg(pd);
 	bfqg_stats_exit(&bfqg->stats);
-	return kfree(bfqg);
+	bfqg_put(bfqg);
 }
 void bfq_pd_reset_stats(struct blkg_policy_data *pd)
  * Move @bfqq to @bfqg, deactivating it from its old group and reactivating
  * it on the new one.  Avoid putting the entity on the old group idle tree.
  *
- * Must be called under the queue lock; the cgroup owning @bfqg must
+ * Must be called under the scheduler lock, to make sure that the blkg
- * not disappear (by now this just means that we are called under
+ * owning @bfqg does not disappear (see comments in
- * rcu_read_lock()).
+ * bfq_bic_update_cgroup on guaranteeing the consistency of blkg
+ * objects).
  */
 void bfq_bfqq_move(struct bfq_data *bfqd, struct bfq_queue *bfqq,
 		   struct bfq_group *bfqg)
 		bfq_deactivate_bfqq(bfqd, bfqq, false, false);
 	else if (entity->on_st)
 		bfq_put_idle_entity(bfq_entity_service_tree(entity), entity);
-	bfqg_put(bfqq_group(bfqq));
+	bfqg_and_blkg_put(bfqq_group(bfqq));
-	/*
-	 * Here we use a reference to bfqg.  We don't need a refcounter
-	 * as the cgroup reference will not be dropped, so that its
-	 * destroy() callback will not be invoked.
-	 */
 	entity->parent = bfqg->my_entity;
 	entity->sched_data = &bfqg->sched_data;
-	bfqg_get(bfqg);
+	/* pin down bfqg and its associated blkg  */
+	bfqg_and_blkg_get(bfqg);
 	if (bfq_bfqq_busy(bfqq)) {
 		bfq_pos_tree_add_move(bfqd, bfqq);
  * @bic: the bic to move.
  * @blkcg: the blk-cgroup to move to.
  *
- * Move bic to blkcg, assuming that bfqd->queue is locked; the caller
+ * Move bic to blkcg, assuming that bfqd->lock is held; which makes
- * has to make sure that the reference to cgroup is valid across the call.
+ * sure that the reference to cgroup is valid across the call (see
+ * comments in bfq_bic_update_cgroup on this issue)
  *
  * NOTE: an alternative approach might have been to store the current
  * cgroup in bfqq and getting a reference to it, reducing the lookup
 		goto out;
 	bfqg = __bfq_bic_change_cgroup(bfqd, bic, bio_blkcg(bio));
+	/*
+	 * Update blkg_path for bfq_log_* functions. We cache this
+	 * path, and update it here, for the following
+	 * reasons. Operations on blkg objects in blk-cgroup are
+	 * protected with the request_queue lock, and not with the
+	 * lock that protects the instances of this scheduler
+	 * (bfqd->lock). This exposes BFQ to the following sort of
+	 * race.
+	 *
+	 * The blkg_lookup performed in bfq_get_queue, protected
+	 * through rcu, may happen to return the address of a copy of
+	 * the original blkg. If this is the case, then the
+	 * bfqg_and_blkg_get performed in bfq_get_queue, to pin down
+	 * the blkg, is useless: it does not prevent blk-cgroup code
+	 * from destroying both the original blkg and all objects
+	 * directly or indirectly referred by the copy of the
+	 * blkg.
+	 *
+	 * On the bright side, destroy operations on a blkg invoke, as
+	 * a first step, hooks of the scheduler associated with the
+	 * blkg. And these hooks are executed with bfqd->lock held for
+	 * BFQ. As a consequence, for any blkg associated with the
+	 * request queue this instance of the scheduler is attached
+	 * to, we are guaranteed that such a blkg is not destroyed, and
+	 * that all the pointers it contains are consistent, while we
+	 * are holding bfqd->lock. A blkg_lookup performed with
+	 * bfqd->lock held then returns a fully consistent blkg, which
+	 * remains consistent until this lock is held.
+	 *
+	 * Thanks to the last fact, and to the fact that: (1) bfqg has
+	 * been obtained through a blkg_lookup in the above
+	 * assignment, and (2) bfqd->lock is being held, here we can
+	 * safely use the policy data for the involved blkg (i.e., the
+	 * field bfqg->pd) to get to the blkg associated with bfqg,
+	 * and then we can safely use any field of blkg. After we
+	 * release bfqd->lock, even just getting blkg through this
+	 * bfqg may cause dangling references to be traversed, as
+	 * bfqg->pd may not exist any more.
+	 *
+	 * In view of the above facts, here we cache, in the bfqg, any
+	 * blkg data we may need for this bic, and for its associated
+	 * bfq_queue. As of now, we need to cache only the path of the
+	 * blkg, which is used in the bfq_log_* functions.
+	 *
+	 * Finally, note that bfqg itself needs to be protected from
+	 * destruction on the blkg_free of the original blkg (which
+	 * invokes bfq_pd_free). We use an additional private
+	 * refcounter for bfqg, to let it disappear only after no
+	 * bfq_queue refers to it any longer.
+	 */
+	blkg_path(bfqg_to_blkg(bfqg), bfqg->blkg_path, sizeof(bfqg->blkg_path));
 	bic->blkcg_serial_nr = serial_nr;
 out:
 	rcu_read_unlock();
  * @bfqd: the device data structure with the root group.
  * @bfqg: the group to move from.
  * @st: the service tree with the entities.
- *
- * Needs queue_lock to be taken and reference to be valid over the call.
  */
 static void bfq_reparent_active_entities(struct bfq_data *bfqd,
 					 struct bfq_group *bfqg,
 		/*
 		 * The idle tree may still contain bfq_queues belonging
 		 * to exited task because they never migrated to a different
-		 * cgroup from the one being destroyed now.  No one else
+		 * cgroup from the one being destroyed now.
-		 * can access them so it's safe to act without any lock.
 		 */
 		bfq_flush_idle_tree(st);

block/bfq-iosched.c+1−1

@@ -3665,7 +3665,7 @@ void bfq_put_queue(struct bfq_queue *bfqq) · 3664 unmodified lines
3665		3665
3666	kmem_cache_free(bfq_pool, bfqq);	3666	kmem_cache_free(bfq_pool, bfqq);
3667	#ifdef CONFIG_BFQ_GROUP_IOSCHED	3667	#ifdef CONFIG_BFQ_GROUP_IOSCHED
3668	bfqg_put(bfqg);	3668	bfqg_and_blkg_put(bfqg);
3669	#endif	3669	#endif
3670	}	3670	}
3671		3671

block/bfq-iosched.h+11−12

 	/* must be the first member */
 	struct blkg_policy_data pd;
+	/* cached path for this blkg (see comments in bfq_bic_update_cgroup) */
+	char blkg_path[128];
+	/* reference counter (see comments in bfq_bic_update_cgroup) */
+	int ref;
 	struct bfq_entity entity;
 	struct bfq_sched_data sched_data;
 struct blkcg_gq *bfqg_to_blkg(struct bfq_group *bfqg);
 struct bfq_group *bfqq_group(struct bfq_queue *bfqq);
 struct bfq_group *bfq_create_group_hierarchy(struct bfq_data *bfqd, int node);
-void bfqg_put(struct bfq_group *bfqg);
+void bfqg_and_blkg_put(struct bfq_group *bfqg);
 #ifdef CONFIG_BFQ_GROUP_IOSCHED
 extern struct cftype bfq_blkcg_legacy_files[];
 struct bfq_group *bfqq_group(struct bfq_queue *bfqq);
 #define bfq_log_bfqq(bfqd, bfqq, fmt, args...)	do {			\
-	char __pbuf[128];						\
+	blk_add_trace_msg((bfqd)->queue, "bfq%d%c %s " fmt, (bfqq)->pid,\
-									\
-	blkg_path(bfqg_to_blkg(bfqq_group(bfqq)), __pbuf, sizeof(__pbuf)); \
-	blk_add_trace_msg((bfqd)->queue, "bfq%d%c %s " fmt, (bfqq)->pid, \
 			bfq_bfqq_sync((bfqq)) ? 'S' : 'A',		\
-			  __pbuf, ##args);				\
+			bfqq_group(bfqq)->blkg_path, ##args);		\
 } while (0)
-#define bfq_log_bfqg(bfqd, bfqg, fmt, args...)	do {			\
+#define bfq_log_bfqg(bfqd, bfqg, fmt, args...)	\
-	char __pbuf[128];						\
+	blk_add_trace_msg((bfqd)->queue, "%s " fmt, (bfqg)->blkg_path, ##args)
-									\
-	blkg_path(bfqg_to_blkg(bfqg), __pbuf, sizeof(__pbuf));		\
-	blk_add_trace_msg((bfqd)->queue, "%s " fmt, __pbuf, ##args);	\
-} while (0)
 #else /* CONFIG_BFQ_GROUP_IOSCHED */

block/bio-integrity.c+3−0

@@ -175,6 +175,9 @@ bool bio_integrity_enabled(struct bio *bio) · 174 unmodified lines
175	if (bio_op(bio) != REQ_OP_READ && bio_op(bio) != REQ_OP_WRITE)	175	if (bio_op(bio) != REQ_OP_READ && bio_op(bio) != REQ_OP_WRITE)
176	return false;	176	return false;
177		177
		178	if (!bio_sectors(bio))
		179	return false;
		180
178	/* Already protected? */	181	/* Already protected? */
179	if (bio_integrity(bio))	182	if (bio_integrity(bio))
180	return false;	183	return false;

block/blk-cgroup.c+1−1

@@ -74,7 +74,7 @@ static void blkg_free(struct blkcg_gq *blkg) · 73 unmodified lines
74	blkcg_policy[i]->pd_free_fn(blkg->pd[i]);	74	blkcg_policy[i]->pd_free_fn(blkg->pd[i]);
75		75
76	if (blkg->blkcg != &blkcg_root)	76	if (blkg->blkcg != &blkcg_root)
77	blk_exit_rl(&blkg->rl);	77	blk_exit_rl(blkg->q, &blkg->rl);
78		78
79	blkg_rwstat_exit(&blkg->stat_ios);	79	blkg_rwstat_exit(&blkg->stat_ios);
80	blkg_rwstat_exit(&blkg->stat_bytes);	80	blkg_rwstat_exit(&blkg->stat_bytes);

block/blk-core.c+8−2

 	if (!rl->rq_pool)
 		return -ENOMEM;
+	if (rl != &q->root_rl)
+		WARN_ON_ONCE(!blk_get_queue(q));
 	return 0;
 }
-void blk_exit_rl(struct request_list *rl)
+void blk_exit_rl(struct request_queue *q, struct request_list *rl)
 {
-	if (rl->rq_pool)
+	if (rl->rq_pool) {
 		mempool_destroy(rl->rq_pool);
+		if (rl != &q->root_rl)
+			blk_put_queue(q);
+	}
 }
 struct request_queue *blk_alloc_queue(gfp_t gfp_mask)

block/blk-mq.c+26−9

 	return blk_tag_to_qc_t(rq->internal_tag, hctx->queue_num, true);
 }
-static void __blk_mq_try_issue_directly(struct request *rq, blk_qc_t *cookie,
+static void __blk_mq_try_issue_directly(struct blk_mq_hw_ctx *hctx,
-				      bool may_sleep)
+					struct request *rq,
+					blk_qc_t *cookie, bool may_sleep)
 {
 	struct request_queue *q = rq->q;
 	struct blk_mq_queue_data bd = {
 		.rq = rq,
 		.last = true,
 	};
-	struct blk_mq_hw_ctx *hctx;
 	blk_qc_t new_cookie;
 	int ret;
+	bool run_queue = true;
+	if (blk_mq_hctx_stopped(hctx)) {
+		run_queue = false;
+		goto insert;
+	}
 	if (q->elevator)
 		goto insert;
-	if (!blk_mq_get_driver_tag(rq, &hctx, false))
+	if (!blk_mq_get_driver_tag(rq, NULL, false))
 		goto insert;
 	new_cookie = request_to_qc_t(hctx, rq);
 	__blk_mq_requeue_request(rq);
 insert:
-	blk_mq_sched_insert_request(rq, false, true, false, may_sleep);
+	blk_mq_sched_insert_request(rq, false, run_queue, false, may_sleep);
 }
 static void blk_mq_try_issue_directly(struct blk_mq_hw_ctx *hctx,
 {
 	if (!(hctx->flags & BLK_MQ_F_BLOCKING)) {
 		rcu_read_lock();
-		__blk_mq_try_issue_directly(rq, cookie, false);
+		__blk_mq_try_issue_directly(hctx, rq, cookie, false);
 		rcu_read_unlock();
 	} else {
 		unsigned int srcu_idx;
 		might_sleep();
 		srcu_idx = srcu_read_lock(&hctx->queue_rq_srcu);
-		__blk_mq_try_issue_directly(rq, cookie, true);
+		__blk_mq_try_issue_directly(hctx, rq, cookie, true);
 		srcu_read_unlock(&hctx->queue_rq_srcu, srcu_idx);
 	}
 }
 		blk_mq_put_ctx(data.ctx);
-		if (same_queue_rq)
+		if (same_queue_rq) {
+			data.hctx = blk_mq_map_queue(q,
+					same_queue_rq->mq_ctx->cpu);
 			blk_mq_try_issue_directly(data.hctx, same_queue_rq,
 					&cookie);
+		}
 	} else if (q->nr_hw_queues > 1 && is_sync) {
 		blk_mq_put_ctx(data.ctx);
 		blk_mq_bio_to_request(rq, bio);
 	return ret;
 }
-void blk_mq_update_nr_hw_queues(struct blk_mq_tag_set *set, int nr_hw_queues)
+static void __blk_mq_update_nr_hw_queues(struct blk_mq_tag_set *set,
+							int nr_hw_queues)
 {
 	struct request_queue *q;
 	list_for_each_entry(q, &set->tag_list, tag_set_list)
 		blk_mq_unfreeze_queue(q);
 }
+void blk_mq_update_nr_hw_queues(struct blk_mq_tag_set *set, int nr_hw_queues)
+{
+	mutex_lock(&set->tag_list_lock);
+	__blk_mq_update_nr_hw_queues(set, nr_hw_queues);
+	mutex_unlock(&set->tag_list_lock);
+}
 EXPORT_SYMBOL_GPL(blk_mq_update_nr_hw_queues);
 /* Enable polling stats and return whether they were already enabled. */

block/blk-sysfs.c+23−13

 }
 /**
- * blk_release_queue: - release a &struct request_queue when it is no longer needed
+ * __blk_release_queue - release a request queue when it is no longer needed
- * @kobj:    the kobj belonging to the request queue to be released
+ * @work: pointer to the release_work member of the request queue to be released
  *
  * Description:
- *     blk_release_queue is the pair to blk_init_queue() or
+ *     blk_release_queue is the counterpart of blk_init_queue(). It should be
- *     blk_queue_make_request().  It should be called when a request queue is
+ *     called when a request queue is being released; typically when a block
- *     being released; typically when a block device is being de-registered.
+ *     device is being de-registered. Its primary task it to free the queue
- *     Currently, its primary task it to free all the &struct request
+ *     itself.
- *     structures that were allocated to the queue and the queue itself.
  *
- * Note:
+ * Notes:
  *     The low level driver must have finished any outstanding requests first
  *     via blk_cleanup_queue().
- **/
+ *
-static void blk_release_queue(struct kobject *kobj)
+ *     Although blk_release_queue() may be called with preemption disabled,
+ *     __blk_release_queue() may sleep.
+ */
+static void __blk_release_queue(struct work_struct *work)
 {
-	struct request_queue *q =
+	struct request_queue *q = container_of(work, typeof(*q), release_work);
-		container_of(kobj, struct request_queue, kobj);
 	if (test_bit(QUEUE_FLAG_POLL_STATS, &q->queue_flags))
 		blk_stat_remove_callback(q, q->poll_cb);
 	blk_free_queue_stats(q->stats);
-	blk_exit_rl(&q->root_rl);
+	blk_exit_rl(q, &q->root_rl);
 	if (q->queue_tags)
 		__blk_queue_free_tags(q);
 	call_rcu(&q->rcu_head, blk_free_queue_rcu);
 }
+static void blk_release_queue(struct kobject *kobj)
+{
+	struct request_queue *q =
+		container_of(kobj, struct request_queue, kobj);
+	INIT_WORK(&q->release_work, __blk_release_queue);
+	schedule_work(&q->release_work);
+}
 static const struct sysfs_ops queue_sysfs_ops = {
 	.show	= queue_attr_show,
 	.store	= queue_attr_store,

block/blk-throttle.c+18−4

 #define MIN_THROTL_IOPS (10)
 #define DFL_LATENCY_TARGET (-1L)
 #define DFL_IDLE_THRESHOLD (0)
+#define DFL_HD_BASELINE_LATENCY (4000L) /* 4ms */
+#define LATENCY_FILTERED_SSD (0)
+/*
+ * For HD, very small latency comes from sequential IO. Such IO is helpless to
+ * help determine if its IO is impacted by others, hence we ignore the IO
+ */
+#define LATENCY_FILTERED_HD (1000L) /* 1ms */
 #define SKIP_LATENCY (((u64)1) << BLK_STAT_RES_SHIFT)
 	struct avg_latency_bucket avg_buckets[LATENCY_BUCKET_SIZE];
 	struct latency_bucket __percpu *latency_buckets;
 	unsigned long last_calculate_time;
+	unsigned long filtered_latency;
 	bool track_bio_latency;
 };
 static void throtl_schedule_pending_timer(struct throtl_service_queue *sq,
 					  unsigned long expires)
 {
-	unsigned long max_expire = jiffies + 8 * sq_to_tg(sq)->td->throtl_slice;
+	unsigned long max_expire = jiffies + 8 * sq_to_td(sq)->throtl_slice;
 	/*
 	 * Since we are adjusting the throttle limit dynamically, the sleep
 		throtl_track_latency(tg->td, blk_stat_size(&bio->bi_issue_stat),
 			bio_op(bio), lat);
-	if (tg->latency_target) {
+	if (tg->latency_target && lat >= tg->td->filtered_latency) {
 		int bucket;
 		unsigned int threshold;
 void blk_throtl_register_queue(struct request_queue *q)
 {
 	struct throtl_data *td;
+	int i;
 	td = q->td;
 	BUG_ON(!td);
-	if (blk_queue_nonrot(q))
+	if (blk_queue_nonrot(q)) {
 		td->throtl_slice = DFL_THROTL_SLICE_SSD;
-	else
+		td->filtered_latency = LATENCY_FILTERED_SSD;
+	} else {
 		td->throtl_slice = DFL_THROTL_SLICE_HD;
+		td->filtered_latency = LATENCY_FILTERED_HD;
+		for (i = 0; i < LATENCY_BUCKET_SIZE; i++)
+			td->avg_buckets[i].latency = DFL_HD_BASELINE_LATENCY;
+	}
 #ifndef CONFIG_BLK_DEV_THROTTLING_LOW
 	/* if no low limit, use previous default */
 	td->throtl_slice = DFL_THROTL_SLICE_HD;

block/blk.h+1−1

@@ -59,7 +59,7 @@ void blk_free_flush_queue(struct blk_flush_queue *q); · 58 unmodified lines
59		59
60	int blk_init_rl(struct request_list rl, struct request_queue q,	60	int blk_init_rl(struct request_list rl, struct request_queue q,
61	gfp_t gfp_mask);	61	gfp_t gfp_mask);
62	void blk_exit_rl(struct request_list *rl);	62	void blk_exit_rl(struct request_queue q, struct request_list rl);
63	void blk_rq_bio_prep(struct request_queue q, struct request rq,	63	void blk_rq_bio_prep(struct request_queue q, struct request rq,
64	struct bio *bio);	64	struct bio *bio);
65	void blk_queue_bypass_start(struct request_queue *q);	65	void blk_queue_bypass_start(struct request_queue *q);

block/cfq-iosched.c+15−2

 static const int cfq_hist_divisor = 4;
 /*
- * offset from end of service tree
+ * offset from end of queue service tree for idle class
  */
 #define CFQ_IDLE_DELAY		(NSEC_PER_SEC / 5)
+/* offset from end of group service tree under time slice mode */
+#define CFQ_SLICE_MODE_GROUP_DELAY (NSEC_PER_SEC / 5)
+/* offset from end of group service under IOPS mode */
+#define CFQ_IOPS_MODE_GROUP_DELAY (HZ / 5)
 /*
  * below this threshold, we consider thinktime immediate
 	cfqg->vfraction = max_t(unsigned, vfr, 1);
 }
+static inline u64 cfq_get_cfqg_vdisktime_delay(struct cfq_data *cfqd)
+{
+	if (!iops_mode(cfqd))
+		return CFQ_SLICE_MODE_GROUP_DELAY;
+	else
+		return CFQ_IOPS_MODE_GROUP_DELAY;
+}
 static void
 cfq_group_notify_queue_add(struct cfq_data *cfqd, struct cfq_group *cfqg)
 {
 	n = rb_last(&st->rb);
 	if (n) {
 		__cfqg = rb_entry_cfqg(n);
-		cfqg->vdisktime = __cfqg->vdisktime + CFQ_IDLE_DELAY;
+		cfqg->vdisktime = __cfqg->vdisktime +
+			cfq_get_cfqg_vdisktime_delay(cfqd);
 	} else
 		cfqg->vdisktime = st->min_vdisktime;
 	cfq_group_service_tree_add(st, cfqg);

crypto/asymmetric_keys/public_key.c+1−1

@@ -141,7 +141,7 @@ int public_key_verify_signature(const struct public_key *pkey, · 140 unmodified lines
141	* signature and returns that to us.	141	* signature and returns that to us.
142	*/	142	*/
143	ret = crypto_akcipher_verify(req);	143	ret = crypto_akcipher_verify(req);
144	if (ret == -EINPROGRESS) {	144	if ((ret == -EINPROGRESS) \|\| (ret == -EBUSY)) {
145	wait_for_completion(&compl.completion);	145	wait_for_completion(&compl.completion);
146	ret = compl.err;	146	ret = compl.err;
147	}	147	}

crypto/asymmetric_keys/verify_pefile.c+2−2

@@ -381,7 +381,7 @@ static int pefile_digest_pe(const void *pebuf, unsigned int pelen, · 380 unmodified lines
381	}	381	}
382		382
383	error:	383	error:
384	kfree(desc);	384	kzfree(desc);
385	error_no_desc:	385	error_no_desc:
386	crypto_free_shash(tfm);	386	crypto_free_shash(tfm);
387	kleave(" = %d", ret);	387	kleave(" = %d", ret);
@@ -450,6 +450,6 @@ int verify_pefile_signature(const void *pebuf, unsigned pelen, · 62 unmodified lines
450	ret = pefile_digest_pe(pebuf, pelen, &ctx);	450	ret = pefile_digest_pe(pebuf, pelen, &ctx);
451		451
452	error:	452	error:
453	kfree(ctx.digest);	453	kzfree(ctx.digest);
454	return ret;	454	return ret;
455	}	455	}

crypto/asymmetric_keys/x509_cert_parser.c+1−0

@@ -102,6 +102,7 @@ struct x509_certificate x509_cert_parse(const void data, size_t datalen) · 101 unmodified lines
102	}	102	}
103	}	103	}
104		104
		105	ret = -ENOMEM;
105	cert->pub->key = kmemdup(ctx->key, ctx->key_size, GFP_KERNEL);	106	cert->pub->key = kmemdup(ctx->key, ctx->key_size, GFP_KERNEL);
106	if (!cert->pub->key)	107	if (!cert->pub->key)
107	goto error_decode;	108	goto error_decode;

crypto/drbg.c+2−3

 			break;
 		case -EINPROGRESS:
 		case -EBUSY:
-			ret = wait_for_completion_interruptible(
+			wait_for_completion(&drbg->ctr_completion);
-				&drbg->ctr_completion);
+			if (!drbg->ctr_async_err) {
-			if (!ret && !drbg->ctr_async_err) {
 				reinit_completion(&drbg->ctr_completion);
 				break;
 			}

crypto/gcm.c+2−4

 	err = crypto_skcipher_encrypt(&data->req);
 	if (err == -EINPROGRESS || err == -EBUSY) {
-		err = wait_for_completion_interruptible(
+		wait_for_completion(&data->result.completion);
-			&data->result.completion);
+		err = data->result.err;
-		if (!err)
-			err = data->result.err;
 	}
 	if (err)

drivers/acpi/acpica/tbutils.c+25−13

@@ -416,13 +416,18 @@ acpi_tb_get_table(struct acpi_table_desc *table_desc, · 415 unmodified lines
416	}	416	}
417	}	417	}
418		418
419	table_desc->validation_count++;	419	if (table_desc->validation_count < ACPI_MAX_TABLE_VALIDATIONS) {
420	if (table_desc->validation_count == 0) {	420	table_desc->validation_count++;
421	ACPI_ERROR((AE_INFO,	421
422	"Table %p, Validation count is zero after increment\n",	422	/*
423	table_desc));	423	* Detect validation_count overflows to ensure that the warning
424	table_desc->validation_count--;	424	* message will only be printed once.
425	return_ACPI_STATUS(AE_LIMIT);	425	*/
		426	if (table_desc->validation_count >= ACPI_MAX_TABLE_VALIDATIONS) {
		427	ACPI_WARNING((AE_INFO,
		428	"Table %p, Validation count overflows\n",
		429	table_desc));
		430	}
426	}	431	}
427		432
428	*out_table = table_desc->pointer;	433	*out_table = table_desc->pointer;
@@ -449,13 +454,20 @@ void acpi_tb_put_table(struct acpi_table_desc *table_desc) · 20 unmodified lines
449		454
450	ACPI_FUNCTION_TRACE(acpi_tb_put_table);	455	ACPI_FUNCTION_TRACE(acpi_tb_put_table);
451		456
452	if (table_desc->validation_count == 0) {	457	if (table_desc->validation_count < ACPI_MAX_TABLE_VALIDATIONS) {
453	ACPI_WARNING((AE_INFO,	458	table_desc->validation_count--;
454	"Table %p, Validation count is zero before decrement\n",	459
455	table_desc));	460	/*
456	return_VOID;	461	* Detect validation_count underflows to ensure that the warning
		462	* message will only be printed once.
		463	*/
		464	if (table_desc->validation_count >= ACPI_MAX_TABLE_VALIDATIONS) {
		465	ACPI_WARNING((AE_INFO,
		466	"Table %p, Validation count underflows\n",
		467	table_desc));
		468	return_VOID;
		469	}
457	}	470	}
458	table_desc->validation_count--;
459		471
460	if (table_desc->validation_count == 0) {	472	if (table_desc->validation_count == 0) {
461		473

drivers/acpi/acpica/utresrc.c+0−9

@@ -474,15 +474,6 @@ acpi_ut_walk_aml_resources(struct acpi_walk_state *walk_state, · 473 unmodified lines
474	return_ACPI_STATUS(AE_AML_NO_RESOURCE_END_TAG);	474	return_ACPI_STATUS(AE_AML_NO_RESOURCE_END_TAG);
475	}	475	}
476		476
477	/*
478	* The end_tag opcode must be followed by a zero byte.
479	* Although this byte is technically defined to be a checksum,
480	* in practice, all ASL compilers set this byte to zero.
481	*/
482	if (*(aml + 1) != 0) {
483	return_ACPI_STATUS(AE_AML_NO_RESOURCE_END_TAG);
484	}
485
486	/* Return the pointer to the end_tag if requested */	477	/* Return the pointer to the end_tag if requested */
487		478
488	if (!user_function) {	479	if (!user_function) {

drivers/acpi/arm64/iort.c+14−8

 	int ret = -ENODEV;
 	struct fwnode_handle *iort_fwnode;
-	/*
-	 * If we already translated the fwspec there
-	 * is nothing left to do, return the iommu_ops.
-	 */
-	ops = iort_fwspec_iommu_ops(dev->iommu_fwspec);
-	if (ops)
-		return ops;
 	if (node) {
 		iort_fwnode = iort_get_fwnode(node);
 		if (!iort_fwnode)
 	u32 streamid = 0;
 	int err;
+	/*
+	 * If we already translated the fwspec there
+	 * is nothing left to do, return the iommu_ops.
+	 */
+	ops = iort_fwspec_iommu_ops(dev->iommu_fwspec);
+	if (ops)
+		return ops;
 	if (dev_is_pci(dev)) {
 		struct pci_bus *bus = to_pci_dev(dev)->bus;
 		u32 rid;
 	if (err)
 		ops = ERR_PTR(err);
+	/* Ignore all other errors apart from EPROBE_DEFER */
+	if (IS_ERR(ops) && (PTR_ERR(ops) != -EPROBE_DEFER)) {
+		dev_dbg(dev, "Adding to IOMMU failed: %ld\n", PTR_ERR(ops));
+		ops = NULL;
+	}
 	return ops;
 }

drivers/acpi/battery.c+1−1

@@ -782,7 +782,7 @@ static int acpi_battery_update(struct acpi_battery *battery, bool resume) · 781 unmodified lines
782	if ((battery->state & ACPI_BATTERY_STATE_CRITICAL) \|\|	782	if ((battery->state & ACPI_BATTERY_STATE_CRITICAL) \|\|
783	(test_bit(ACPI_BATTERY_ALARM_PRESENT, &battery->flags) &&	783	(test_bit(ACPI_BATTERY_ALARM_PRESENT, &battery->flags) &&
784	(battery->capacity_now <= battery->alarm)))	784	(battery->capacity_now <= battery->alarm)))
785	pm_wakeup_hard_event(&battery->device->dev);	785	pm_wakeup_event(&battery->device->dev, 0);
786		786
787	return result;	787	return result;
788	}	788	}

drivers/acpi/button.c+3−4

 static BLOCKING_NOTIFIER_HEAD(acpi_lid_notifier);
 static struct acpi_device *lid_device;
-static u8 lid_init_state = ACPI_BUTTON_LID_INIT_OPEN;
+static u8 lid_init_state = ACPI_BUTTON_LID_INIT_METHOD;
 static unsigned long lid_report_interval __read_mostly = 500;
 module_param(lid_report_interval, ulong, 0644);
 	}
 	if (state)
-		pm_wakeup_hard_event(&device->dev);
+		pm_wakeup_event(&device->dev, 0);
 	ret = blocking_notifier_call_chain(&acpi_lid_notifier, state, device);
 	if (ret == NOTIFY_DONE)
 		} else {
 			int keycode;
-			pm_wakeup_hard_event(&device->dev);
+			pm_wakeup_event(&device->dev, 0);
 			if (button->suspended)
 				break;
 		lid_device = device;
 	}
-	device_init_wakeup(&device->dev, true);
 	printk(KERN_INFO PREFIX "%s [%s]\n", name, acpi_device_bid(device));
 	return 0;

drivers/acpi/device_pm.c+1−2

 #include <linux/pm_qos.h>
 #include <linux/pm_domain.h>
 #include <linux/pm_runtime.h>
-#include <linux/suspend.h>
 #include "internal.h"
 	mutex_lock(&acpi_pm_notifier_lock);
 	if (adev->wakeup.flags.notifier_present) {
-		pm_wakeup_ws_event(adev->wakeup.ws, 0, true);
+		__pm_wakeup_event(adev->wakeup.ws, 0);
 		if (adev->wakeup.context.work.func)
 			queue_pm_work(&adev->wakeup.context.work);
 	}

drivers/acpi/scan.c+2−2

@@ -1371,8 +1371,8 @@ int acpi_dma_configure(struct device *dev, enum dev_dma_attr attr) · 1370 unmodified lines
1371	iort_set_dma_mask(dev);	1371	iort_set_dma_mask(dev);
1372		1372
1373	iommu = iort_iommu_configure(dev);	1373	iommu = iort_iommu_configure(dev);
1374	if (IS_ERR(iommu))	1374	if (IS_ERR(iommu) && PTR_ERR(iommu) == -EPROBE_DEFER)
1375	return PTR_ERR(iommu);	1375	return -EPROBE_DEFER;
1376		1376
1377	size = max(dev->coherent_dma_mask, dev->coherent_dma_mask + 1);	1377	size = max(dev->coherent_dma_mask, dev->coherent_dma_mask + 1);
1378	/*	1378	/*

drivers/acpi/sleep.c+0−28

@@ -663,40 +663,14 @@ static int acpi_freeze_prepare(void) · 662 unmodified lines
663	acpi_os_wait_events_complete();	663	acpi_os_wait_events_complete();
664	if (acpi_sci_irq_valid())	664	if (acpi_sci_irq_valid())
665	enable_irq_wake(acpi_sci_irq);	665	enable_irq_wake(acpi_sci_irq);
666
667	return 0;	666	return 0;
668	}	667	}
669		668
670	static void acpi_freeze_wake(void)
671	{
672	/*
673	* If IRQD_WAKEUP_ARMED is not set for the SCI at this point, it means
674	* that the SCI has triggered while suspended, so cancel the wakeup in
675	* case it has not been a wakeup event (the GPEs will be checked later).
676	*/
677	if (acpi_sci_irq_valid() &&
678	!irqd_is_wakeup_armed(irq_get_irq_data(acpi_sci_irq)))
679	pm_system_cancel_wakeup();
680	}
681
682	static void acpi_freeze_sync(void)
683	{
684	/*
685	* Process all pending events in case there are any wakeup ones.
686	*
687	* The EC driver uses the system workqueue, so that one needs to be
688	* flushed too.
689	*/
690	acpi_os_wait_events_complete();
691	flush_scheduled_work();
692	}
693
694	static void acpi_freeze_restore(void)	669	static void acpi_freeze_restore(void)
695	{	670	{
696	acpi_disable_wakeup_devices(ACPI_STATE_S0);	671	acpi_disable_wakeup_devices(ACPI_STATE_S0);
697	if (acpi_sci_irq_valid())	672	if (acpi_sci_irq_valid())
698	disable_irq_wake(acpi_sci_irq);	673	disable_irq_wake(acpi_sci_irq);
699
700	acpi_enable_all_runtime_gpes();	674	acpi_enable_all_runtime_gpes();
701	}	675	}
702		676
@@ -708,8 +682,6 @@ static void acpi_freeze_end(void) · 5 unmodified lines
708	static const struct platform_freeze_ops acpi_freeze_ops = {	682	static const struct platform_freeze_ops acpi_freeze_ops = {
709	.begin = acpi_freeze_begin,	683	.begin = acpi_freeze_begin,
710	.prepare = acpi_freeze_prepare,	684	.prepare = acpi_freeze_prepare,
711	.wake = acpi_freeze_wake,
712	.sync = acpi_freeze_sync,
713	.restore = acpi_freeze_restore,	685	.restore = acpi_freeze_restore,
714	.end = acpi_freeze_end,	686	.end = acpi_freeze_end,
715	};	687	};

drivers/acpi/sysfs.c+5−2

 	    container_of(bin_attr, struct acpi_table_attr, attr);
 	struct acpi_table_header *table_header = NULL;
 	acpi_status status;
+	ssize_t rc;
 	status = acpi_get_table(table_attr->name, table_attr->instance,
 				&table_header);
 	if (ACPI_FAILURE(status))
 		return -ENODEV;
-	return memory_read_from_buffer(buf, count, &offset,
+	rc = memory_read_from_buffer(buf, count, &offset, table_header,
-				       table_header, table_header->length);
+			table_header->length);
+	acpi_put_table(table_header);
+	return rc;
 }
 static int acpi_table_attr_init(struct kobject *tables_obj,

drivers/ata/ahci.c+38−0

@@ -1364,6 +1364,40 @@ static inline void ahci_gtf_filter_workaround(struct ata_host *host) · 1363 unmodified lines
1364	{}	1364	{}
1365	#endif	1365	#endif
1366		1366
		1367	/*
		1368	* On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected
		1369	* as DUMMY, or detected but eventually get a "link down" and never get up
		1370	* again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the
		1371	* port_map may hold a value of 0x00.
		1372	*
		1373	* Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports
		1374	* and can significantly reduce the occurrence of the problem.
		1375	*
		1376	* https://bugzilla.kernel.org/show_bug.cgi?id=189471
		1377	*/
		1378	static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
		1379	struct pci_dev *pdev)
		1380	{
		1381	static const struct dmi_system_id sysids[] = {
		1382	{
		1383	.ident = "Acer Switch Alpha 12",
		1384	.matches = {
		1385	DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
		1386	DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
		1387	},
		1388	},
		1389	{ }
		1390	};
		1391
		1392	if (dmi_check_system(sysids)) {
		1393	dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
		1394	if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
		1395	hpriv->port_map = 0x7;
		1396	hpriv->cap = 0xC734FF02;
		1397	}
		1398	}
		1399	}
		1400
1367	#ifdef CONFIG_ARM64	1401	#ifdef CONFIG_ARM64
1368	/*	1402	/*
1369	* Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.	1403	* Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
@@ -1636,6 +1670,10 @@ static int ahci_init_one(struct pci_dev pdev, const struct pci_device_id ent) · 266 unmodified lines
1636	"online status unreliable, applying workaround\n");	1670	"online status unreliable, applying workaround\n");
1637	}	1671	}
1638		1672
		1673
		1674	/* Acer SA5-271 workaround modifies private_data */
		1675	acer_sa5_271_workaround(hpriv, pdev);
		1676
1639	/* CAP.NP sometimes indicate the index of the last enabled	1677	/* CAP.NP sometimes indicate the index of the last enabled
1640	* port, at other times, that of the last possible port, so	1678	* port, at other times, that of the last possible port, so
1641	* determining the maximum port number requires looking at	1679	* determining the maximum port number requires looking at

drivers/ata/libahci_platform.c+3−2

@@ -514,8 +514,9 @@ int ahci_platform_init_host(struct platform_device *pdev, · 513 unmodified lines
514		514
515	irq = platform_get_irq(pdev, 0);	515	irq = platform_get_irq(pdev, 0);
516	if (irq <= 0) {	516	if (irq <= 0) {
517	dev_err(dev, "no irq\n");	517	if (irq != -EPROBE_DEFER)
518	return -EINVAL;	518	dev_err(dev, "no irq\n");
		519	return irq;
519	}	520	}
520		521
521	hpriv->irq = irq;	522	hpriv->irq = irq;

drivers/ata/libata-core.c+1−1

@@ -6800,7 +6800,7 @@ static int __init ata_parse_force_one(char **cur, · 6799 unmodified lines
6800	}	6800	}
6801		6801
6802	force_ent->port = simple_strtoul(id, &endp, 10);	6802	force_ent->port = simple_strtoul(id, &endp, 10);
6803	if (p == endp \|\| *endp != '\0') {	6803	if (id == endp \|\| *endp != '\0') {
6804	*reason = "invalid port/link";	6804	*reason = "invalid port/link";
6805	return -EINVAL;	6805	return -EINVAL;
6806	}	6806	}

drivers/ata/sata_mv.c+8−5

 	struct ata_host *host;
 	struct mv_host_priv *hpriv;
 	struct resource *res;
-	void __iomem *mmio;
 	int n_ports = 0, irq = 0;
 	int rc;
 	int port;
 	 * Get the register base first
 	 */
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	mmio = devm_ioremap_resource(&pdev->dev, res);
+	if (res == NULL)
-	if (IS_ERR(mmio))
+		return -EINVAL;
-		return PTR_ERR(mmio);
 	/* allocate host */
 	if (pdev->dev.of_node) {
 	hpriv->board_idx = chip_soc;
 	host->iomap = NULL;
-	hpriv->base = mmio - SATAHC0_REG_BASE;
+	hpriv->base = devm_ioremap(&pdev->dev, res->start,
+				   resource_size(res));
+	if (!hpriv->base)
+		return -ENOMEM;
+	hpriv->base -= SATAHC0_REG_BASE;
 	hpriv->clk = clk_get(&pdev->dev, NULL);
 	if (IS_ERR(hpriv->clk))

drivers/ata/sata_rcar.c+12−3

@@ -890,7 +890,10 @@ static int sata_rcar_probe(struct platform_device *pdev) · 889 unmodified lines
890	dev_err(&pdev->dev, "failed to get access to sata clock\n");	890	dev_err(&pdev->dev, "failed to get access to sata clock\n");
891	return PTR_ERR(priv->clk);	891	return PTR_ERR(priv->clk);
892	}	892	}
893	clk_prepare_enable(priv->clk);	893
		894	ret = clk_prepare_enable(priv->clk);
		895	if (ret)
		896	return ret;
894		897
895	host = ata_host_alloc(&pdev->dev, 1);	898	host = ata_host_alloc(&pdev->dev, 1);
896	if (!host) {	899	if (!host) {
@@ -970,8 +973,11 @@ static int sata_rcar_resume(struct device *dev) · 73 unmodified lines
970	struct ata_host *host = dev_get_drvdata(dev);	973	struct ata_host *host = dev_get_drvdata(dev);
971	struct sata_rcar_priv *priv = host->private_data;	974	struct sata_rcar_priv *priv = host->private_data;
972	void __iomem *base = priv->base;	975	void __iomem *base = priv->base;
		976	int ret;
973		977
974	clk_prepare_enable(priv->clk);	978	ret = clk_prepare_enable(priv->clk);
		979	if (ret)
		980	return ret;
975		981
976	/* ack and mask */	982	/* ack and mask */
977	iowrite32(0, base + SATAINTSTAT_REG);	983	iowrite32(0, base + SATAINTSTAT_REG);
@@ -988,8 +994,11 @@ static int sata_rcar_restore(struct device *dev) · 10 unmodified lines
988	{	994	{
989	struct ata_host *host = dev_get_drvdata(dev);	995	struct ata_host *host = dev_get_drvdata(dev);
990	struct sata_rcar_priv *priv = host->private_data;	996	struct sata_rcar_priv *priv = host->private_data;
		997	int ret;
991		998
992	clk_prepare_enable(priv->clk);	999	ret = clk_prepare_enable(priv->clk);
		1000	if (ret)
		1001	return ret;
993		1002
994	sata_rcar_setup_port(host);	1003	sata_rcar_setup_port(host);
995		1004

drivers/base/power/main.c+5−0

 	if (async_error)
 		goto Complete;
+	if (pm_wakeup_pending()) {
+		async_error = -EBUSY;
+		goto Complete;
+	}
 	if (dev->power.syscore || dev->power.direct_complete)
 		goto Complete;

drivers/base/power/wakeup.c+6−12

 /* First wakeup IRQ seen by the kernel in the last cycle. */
 unsigned int pm_wakeup_irq __read_mostly;
-/* If greater than 0 and the system is suspending, terminate the suspend. */
+/* If set and the system is suspending, terminate the suspend. */
-static atomic_t pm_abort_suspend __read_mostly;
+static bool pm_abort_suspend __read_mostly;
 /*
  * Combined counters of registered wakeup events and wakeup events in progress.
 		pm_print_active_wakeup_sources();
 	}
-	return ret || atomic_read(&pm_abort_suspend) > 0;
+	return ret || pm_abort_suspend;
 }
 void pm_system_wakeup(void)
 {
-	atomic_inc(&pm_abort_suspend);
+	pm_abort_suspend = true;
 	freeze_wake();
 }
 EXPORT_SYMBOL_GPL(pm_system_wakeup);
-void pm_system_cancel_wakeup(void)
+void pm_wakeup_clear(void)
-{
-	atomic_dec(&pm_abort_suspend);
-}
-void pm_wakeup_clear(bool reset)
 {
+	pm_abort_suspend = false;
 	pm_wakeup_irq = 0;
-	if (reset)
-		atomic_set(&pm_abort_suspend, 0);
 }
 void pm_system_irq_wakeup(unsigned int irq_number)

drivers/block/loop.c+3−0

  */
 static int loop_flush(struct loop_device *lo)
 {
+	/* loop not yet configured, no running thread, nothing to flush */
+	if (lo->lo_state != Lo_bound)
+		return 0;
 	return loop_switch(lo, NULL);
 }

drivers/block/nbd.c+5−10

 	return -ENOSPC;
 }
-/* Reset all properties of an NBD device */
-static void nbd_reset(struct nbd_device *nbd)
-{
-	nbd->config = NULL;
-	nbd->tag_set.timeout = 0;
-	queue_flag_clear_unlocked(QUEUE_FLAG_DISCARD, nbd->disk->queue);
-}
 static void nbd_bdev_reset(struct block_device *bdev)
 {
 	if (bdev->bd_openers > 1)
 			}
 			kfree(config->socks);
 		}
-		nbd_reset(nbd);
+		kfree(nbd->config);
+		nbd->config = NULL;
+		nbd->tag_set.timeout = 0;
+		queue_flag_clear_unlocked(QUEUE_FLAG_DISCARD, nbd->disk->queue);
 		mutex_unlock(&nbd->config_lock);
 		nbd_put(nbd);
 	disk->fops = &nbd_fops;
 	disk->private_data = nbd;
 	sprintf(disk->disk_name, "nbd%d", index);
-	nbd_reset(nbd);
 	add_disk(disk);
 	nbd_total_devices++;
 	return index;

drivers/block/rbd.c+2−0

 	switch (req_op(rq)) {
 	case REQ_OP_DISCARD:
+	case REQ_OP_WRITE_ZEROES:
 		op_type = OBJ_OP_DISCARD;
 		break;
 	case REQ_OP_WRITE:
 	q->limits.discard_granularity = segment_size;
 	q->limits.discard_alignment = segment_size;
 	blk_queue_max_discard_sectors(q, segment_size / SECTOR_SIZE);
+	blk_queue_max_write_zeroes_sectors(q, segment_size / SECTOR_SIZE);
 	if (!ceph_test_opt(rbd_dev->rbd_client->client, NOCRC))
 		q->backing_dev_info->capabilities |= BDI_CAP_STABLE_WRITES;

drivers/char/mem.c+1−1

@@ -343,7 +343,7 @@ static int mmap_mem(struct file file, struct vm_area_struct vma) · 342 unmodified lines
343	phys_addr_t offset = (phys_addr_t)vma->vm_pgoff << PAGE_SHIFT;	343	phys_addr_t offset = (phys_addr_t)vma->vm_pgoff << PAGE_SHIFT;
344		344
345	/* It's illegal to wrap around the end of the physical address space. */	345	/* It's illegal to wrap around the end of the physical address space. */
346	if (offset + (phys_addr_t)size < offset)	346	if (offset + (phys_addr_t)size - 1 < offset)
347	return -EINVAL;	347	return -EINVAL;
348		348
349	if (!valid_mmap_phys_addr_range(vma->vm_pgoff, size))	349	if (!valid_mmap_phys_addr_range(vma->vm_pgoff, size))

drivers/char/pcmcia/cm4040_cs.c+3−3

@@ -374,7 +374,7 @@ static ssize_t cm4040_write(struct file filp, const char __user buf, · 373 unmodified lines
374		374
375	rc = write_sync_reg(SCR_HOST_TO_READER_START, dev);	375	rc = write_sync_reg(SCR_HOST_TO_READER_START, dev);
376	if (rc <= 0) {	376	if (rc <= 0) {
377	DEBUGP(5, dev, "write_sync_reg c=%.2Zx\n", rc);	377	DEBUGP(5, dev, "write_sync_reg c=%.2zx\n", rc);
378	DEBUGP(2, dev, "<- cm4040_write (failed)\n");	378	DEBUGP(2, dev, "<- cm4040_write (failed)\n");
379	if (rc == -ERESTARTSYS)	379	if (rc == -ERESTARTSYS)
380	return rc;	380	return rc;
@@ -387,7 +387,7 @@ static ssize_t cm4040_write(struct file filp, const char __user buf, · 6 unmodified lines
387	for (i = 0; i < bytes_to_write; i++) {	387	for (i = 0; i < bytes_to_write; i++) {
388	rc = wait_for_bulk_out_ready(dev);	388	rc = wait_for_bulk_out_ready(dev);
389	if (rc <= 0) {	389	if (rc <= 0) {
390	DEBUGP(5, dev, "wait_for_bulk_out_ready rc=%.2Zx\n",	390	DEBUGP(5, dev, "wait_for_bulk_out_ready rc=%.2zx\n",
391	rc);	391	rc);
392	DEBUGP(2, dev, "<- cm4040_write (failed)\n");	392	DEBUGP(2, dev, "<- cm4040_write (failed)\n");
393	if (rc == -ERESTARTSYS)	393	if (rc == -ERESTARTSYS)
@@ -403,7 +403,7 @@ static ssize_t cm4040_write(struct file filp, const char __user buf, · 9 unmodified lines
403	rc = write_sync_reg(SCR_HOST_TO_READER_DONE, dev);	403	rc = write_sync_reg(SCR_HOST_TO_READER_DONE, dev);
404		404
405	if (rc <= 0) {	405	if (rc <= 0) {
406	DEBUGP(5, dev, "write_sync_reg c=%.2Zx\n", rc);	406	DEBUGP(5, dev, "write_sync_reg c=%.2zx\n", rc);
407	DEBUGP(2, dev, "<- cm4040_write (failed)\n");	407	DEBUGP(2, dev, "<- cm4040_write (failed)\n");
408	if (rc == -ERESTARTSYS)	408	if (rc == -ERESTARTSYS)
409	return rc;	409	return rc;

drivers/char/random.c+44−3

 /*
  * random.c -- A strong random number generator
  *
+ * Copyright (C) 2017 Jason A. Donenfeld <Jason@zx2c4.com>. All
+ * Rights Reserved.
+ *
  * Copyright Matt Mackall <mpm@selenic.com>, 2003, 2004, 2005
  *
  * Copyright Theodore Ts'o, 1994, 1995, 1996, 1997, 1998, 1999.  All
 static struct crng_state **crng_node_pool __read_mostly;
 #endif
+static void invalidate_batched_entropy(void);
 static void crng_initialize(struct crng_state *crng)
 {
 	int		i;
 		cp++; crng_init_cnt++; len--;
 	}
 	if (crng_init_cnt >= CRNG_INIT_CNT_THRESH) {
+		invalidate_batched_entropy();
 		crng_init = 1;
 		wake_up_interruptible(&crng_init_wait);
 		pr_notice("random: fast init done\n");
 	memzero_explicit(&buf, sizeof(buf));
 	crng->init_time = jiffies;
 	if (crng == &primary_crng && crng_init < 2) {
+		invalidate_batched_entropy();
 		crng_init = 2;
 		process_random_ready_list();
 		wake_up_interruptible(&crng_init_wait);
 static __u32 get_reg(struct fast_pool *f, struct pt_regs *regs)
 {
 	__u32 *ptr = (__u32 *) regs;
+	unsigned int idx;
 	if (regs == NULL)
 		return 0;
-	if (f->reg_idx >= sizeof(struct pt_regs) / sizeof(__u32))
+	idx = READ_ONCE(f->reg_idx);
-		f->reg_idx = 0;
+	if (idx >= sizeof(struct pt_regs) / sizeof(__u32))
-	return *(ptr + f->reg_idx++);
+		idx = 0;
+	ptr += idx++;
+	WRITE_ONCE(f->reg_idx, idx);
+	return *ptr;
 }
 void add_interrupt_randomness(int irq, int irq_flags)
 	};
 	unsigned int position;
 };
+static rwlock_t batched_entropy_reset_lock = __RW_LOCK_UNLOCKED(batched_entropy_reset_lock);
 /*
  * Get a random word for internal kernel use only. The quality of the random
 u64 get_random_u64(void)
 {
 	u64 ret;
+	bool use_lock = crng_init < 2;
+	unsigned long flags;
 	struct batched_entropy *batch;
 #if BITS_PER_LONG == 64
 #endif
 	batch = &get_cpu_var(batched_entropy_u64);
+	if (use_lock)
+		read_lock_irqsave(&batched_entropy_reset_lock, flags);
 	if (batch->position % ARRAY_SIZE(batch->entropy_u64) == 0) {
 		extract_crng((u8 *)batch->entropy_u64);
 		batch->position = 0;
 	}
 	ret = batch->entropy_u64[batch->position++];
+	if (use_lock)
+		read_unlock_irqrestore(&batched_entropy_reset_lock, flags);
 	put_cpu_var(batched_entropy_u64);
 	return ret;
 }
 u32 get_random_u32(void)
 {
 	u32 ret;
+	bool use_lock = crng_init < 2;
+	unsigned long flags;
 	struct batched_entropy *batch;
 	if (arch_get_random_int(&ret))
 		return ret;
 	batch = &get_cpu_var(batched_entropy_u32);
+	if (use_lock)
+		read_lock_irqsave(&batched_entropy_reset_lock, flags);
 	if (batch->position % ARRAY_SIZE(batch->entropy_u32) == 0) {
 		extract_crng((u8 *)batch->entropy_u32);
 		batch->position = 0;
 	}
 	ret = batch->entropy_u32[batch->position++];
+	if (use_lock)
+		read_unlock_irqrestore(&batched_entropy_reset_lock, flags);
 	put_cpu_var(batched_entropy_u32);
 	return ret;
 }
 EXPORT_SYMBOL(get_random_u32);
+/* It's important to invalidate all potential batched entropy that might
+ * be stored before the crng is initialized, which we can do lazily by
+ * simply resetting the counter to zero so that it's re-extracted on the
+ * next usage. */
+static void invalidate_batched_entropy(void)
+{
+	int cpu;
+	unsigned long flags;
+	write_lock_irqsave(&batched_entropy_reset_lock, flags);
+	for_each_possible_cpu (cpu) {
+		per_cpu_ptr(&batched_entropy_u32, cpu)->position = 0;
+		per_cpu_ptr(&batched_entropy_u64, cpu)->position = 0;
+	}
+	write_unlock_irqrestore(&batched_entropy_reset_lock, flags);
+}
 /**
  * randomize_page - Generate a random, page aligned address
  * @start:	The smallest acceptable address the caller will take.

drivers/cpufreq/cpufreq.c+1−0

@@ -2468,6 +2468,7 @@ int cpufreq_register_driver(struct cpufreq_driver *driver_data) · 2467 unmodified lines
2468	if (!(cpufreq_driver->flags & CPUFREQ_STICKY) &&	2468	if (!(cpufreq_driver->flags & CPUFREQ_STICKY) &&
2469	list_empty(&cpufreq_policy_list)) {	2469	list_empty(&cpufreq_policy_list)) {
2470	/* if all ->init() calls failed, unregister */	2470	/* if all ->init() calls failed, unregister */
		2471	ret = -ENODEV;
2471	pr_debug("%s: No CPU initialized for driver %s\n", __func__,	2472	pr_debug("%s: No CPU initialized for driver %s\n", __func__,
2472	driver_data->name);	2473	driver_data->name);
2473	goto err_if_unreg;	2474	goto err_if_unreg;

drivers/cpufreq/cpufreq_conservative.c+2−2

@@ -185,8 +185,8 @@ static ssize_t store_down_threshold(struct gov_attr_set *attr_set, · 184 unmodified lines
185	int ret;	185	int ret;
186	ret = sscanf(buf, "%u", &input);	186	ret = sscanf(buf, "%u", &input);
187		187
188	/* cannot be lower than 11 otherwise freq will not fall */	188	/* cannot be lower than 1 otherwise freq will not fall */
189	if (ret != 1 \|\| input < 11 \|\| input > 100 \|\|	189	if (ret != 1 \|\| input < 1 \|\| input > 100 \|\|
190	input >= dbs_data->up_threshold)	190	input >= dbs_data->up_threshold)
191	return -EINVAL;	191	return -EINVAL;
192		192

drivers/cpufreq/intel_pstate.c+3−2

 static int min_perf_pct_min(void)
 {
 	struct cpudata *cpu = all_cpu_data[0];
+	int turbo_pstate = cpu->pstate.turbo_pstate;
-	return DIV_ROUND_UP(cpu->pstate.min_pstate * 100,
+	return turbo_pstate ?
-			    cpu->pstate.turbo_pstate);
+		DIV_ROUND_UP(cpu->pstate.min_pstate * 100, turbo_pstate) : 0;
 }
 static s16 intel_pstate_get_epb(struct cpudata *cpu_data)

drivers/cpufreq/kirkwood-cpufreq.c+16−3

 		return PTR_ERR(priv.cpu_clk);
 	}
-	clk_prepare_enable(priv.cpu_clk);
+	err = clk_prepare_enable(priv.cpu_clk);
+	if (err) {
+		dev_err(priv.dev, "Unable to prepare cpuclk\n");
+		return err;
+	}
 	kirkwood_freq_table[0].frequency = clk_get_rate(priv.cpu_clk) / 1000;
 	priv.ddr_clk = of_clk_get_by_name(np, "ddrclk");
 		goto out_cpu;
 	}
-	clk_prepare_enable(priv.ddr_clk);
+	err = clk_prepare_enable(priv.ddr_clk);
+	if (err) {
+		dev_err(priv.dev, "Unable to prepare ddrclk\n");
+		goto out_cpu;
+	}
 	kirkwood_freq_table[1].frequency = clk_get_rate(priv.ddr_clk) / 1000;
 	priv.powersave_clk = of_clk_get_by_name(np, "powersave");
 		err = PTR_ERR(priv.powersave_clk);
 		goto out_ddr;
 	}
-	clk_prepare_enable(priv.powersave_clk);
+	err = clk_prepare_enable(priv.powersave_clk);
+	if (err) {
+		dev_err(priv.dev, "Unable to prepare powersave clk\n");
+		goto out_ddr;
+	}
 	of_node_put(np);
 	np = NULL;

drivers/cpuidle/dt_idle_states.c+3−1

 		if (!state_node)
 			break;
-		if (!of_device_is_available(state_node))
+		if (!of_device_is_available(state_node)) {
+			of_node_put(state_node);
 			continue;
+		}
 		if (!idle_state_valid(state_node, i, cpumask)) {
 			pr_warn("%s idle state not valid, bailing out\n",

drivers/dax/super.c+7−2

 static struct inode *dax_alloc_inode(struct super_block *sb)
 {
 	struct dax_device *dax_dev;
+	struct inode *inode;
 	dax_dev = kmem_cache_alloc(dax_cache, GFP_KERNEL);
-	return &dax_dev->inode;
+	inode = &dax_dev->inode;
+	inode->i_rdev = 0;
+	return inode;
 }
 static struct dax_device *to_dax_dev(struct inode *inode)
 	kfree(dax_dev->host);
 	dax_dev->host = NULL;
-	ida_simple_remove(&dax_minor_ida, MINOR(inode->i_rdev));
+	if (inode->i_rdev)
+		ida_simple_remove(&dax_minor_ida, MINOR(inode->i_rdev));
 	kmem_cache_free(dax_cache, dax_dev);
 }
 	struct dax_device *dax_dev = _dax_dev;
 	struct inode *inode = &dax_dev->inode;
+	memset(dax_dev, 0, sizeof(*dax_dev));
 	inode_init_once(inode);
 }

drivers/devfreq/event/exynos-nocp.c+5−1

 	}
 	platform_set_drvdata(pdev, nocp);
-	clk_prepare_enable(nocp->clk);
+	ret = clk_prepare_enable(nocp->clk);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to prepare ppmu clock\n");
+		return ret;
+	}
 	pr_info("exynos-nocp: new NoC Probe device registered: %s\n",
 			dev_name(dev));

drivers/devfreq/event/exynos-ppmu.c+6−2

 	{ "ppmu-event2-"#name, PPMU_PMNCNT2 },	\
 	{ "ppmu-event3-"#name, PPMU_PMNCNT3 }
-struct __exynos_ppmu_events {
+static struct __exynos_ppmu_events {
 	char *name;
 	int id;
 } ppmu_events[] = {
 			dev_name(&pdev->dev), desc[i].name);
 	}
-	clk_prepare_enable(info->ppmu.clk);
+	ret = clk_prepare_enable(info->ppmu.clk);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to prepare ppmu clock\n");
+		return ret;
+	}
 	return 0;
 }

drivers/dma/ep93xx_dma.c+35−4

 	struct dma_device	dma_dev;
 	bool			m2m;
 	int			(*hw_setup)(struct ep93xx_dma_chan *);
+	void			(*hw_synchronize)(struct ep93xx_dma_chan *);
 	void			(*hw_shutdown)(struct ep93xx_dma_chan *);
 	void			(*hw_submit)(struct ep93xx_dma_chan *);
 	int			(*hw_interrupt)(struct ep93xx_dma_chan *);
 		| M2P_CONTROL_ENABLE;
 	m2p_set_control(edmac, control);
+	edmac->buffer = 0;
 	return 0;
 }
 	return (readl(edmac->regs + M2P_STATUS) >> 4) & 0x3;
 }
-static void m2p_hw_shutdown(struct ep93xx_dma_chan *edmac)
+static void m2p_hw_synchronize(struct ep93xx_dma_chan *edmac)
 {
+	unsigned long flags;
 	u32 control;
+	spin_lock_irqsave(&edmac->lock, flags);
 	control = readl(edmac->regs + M2P_CONTROL);
 	control &= ~(M2P_CONTROL_STALLINT | M2P_CONTROL_NFBINT);
 	m2p_set_control(edmac, control);
+	spin_unlock_irqrestore(&edmac->lock, flags);
 	while (m2p_channel_state(edmac) >= M2P_STATE_ON)
-		cpu_relax();
+		schedule();
+}
+static void m2p_hw_shutdown(struct ep93xx_dma_chan *edmac)
+{
 	m2p_set_control(edmac, 0);
-	while (m2p_channel_state(edmac) == M2P_STATE_STALL)
+	while (m2p_channel_state(edmac) != M2P_STATE_IDLE)
-		cpu_relax();
+		dev_warn(chan2dev(edmac), "M2P: Not yet IDLE\n");
 }
 static void m2p_fill_desc(struct ep93xx_dma_chan *edmac)
 	return NULL;
 }
+/**
+ * ep93xx_dma_synchronize - Synchronizes the termination of transfers to the
+ * current context.
+ * @chan: channel
+ *
+ * Synchronizes the DMA channel termination to the current context. When this
+ * function returns it is guaranteed that all transfers for previously issued
+ * descriptors have stopped and and it is safe to free the memory associated
+ * with them. Furthermore it is guaranteed that all complete callback functions
+ * for a previously submitted descriptor have finished running and it is safe to
+ * free resources accessed from within the complete callbacks.
+ */
+static void ep93xx_dma_synchronize(struct dma_chan *chan)
+{
+	struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);
+	if (edmac->edma->hw_synchronize)
+		edmac->edma->hw_synchronize(edmac);
+}
 /**
  * ep93xx_dma_terminate_all - terminate all transactions
  * @chan: channel
 	dma_dev->device_prep_slave_sg = ep93xx_dma_prep_slave_sg;
 	dma_dev->device_prep_dma_cyclic = ep93xx_dma_prep_dma_cyclic;
 	dma_dev->device_config = ep93xx_dma_slave_config;
+	dma_dev->device_synchronize = ep93xx_dma_synchronize;
 	dma_dev->device_terminate_all = ep93xx_dma_terminate_all;
 	dma_dev->device_issue_pending = ep93xx_dma_issue_pending;
 	dma_dev->device_tx_status = ep93xx_dma_tx_status;
 	} else {
 		dma_cap_set(DMA_PRIVATE, dma_dev->cap_mask);
+		edma->hw_synchronize = m2p_hw_synchronize;
 		edma->hw_setup = m2p_hw_setup;
 		edma->hw_shutdown = m2p_hw_shutdown;
 		edma->hw_submit = m2p_hw_submit;

drivers/dma/mv_xor_v2.c+44−65

@@ -161,6 +161,7 @@ struct mv_xor_v2_device { · 160 unmodified lines
161	struct mv_xor_v2_sw_desc *sw_desq;	161	struct mv_xor_v2_sw_desc *sw_desq;
162	int desc_size;	162	int desc_size;
163	unsigned int npendings;	163	unsigned int npendings;
		164	unsigned int hw_queue_idx;
164	};	165	};
165		166
166	/**	167	/**
@@ -213,18 +214,6 @@ static void mv_xor_v2_set_data_buffers(struct mv_xor_v2_device *xor_dev, · 46 unmodified lines
213	}	214	}
214	}	215	}
215		216
216	/*
217	* Return the next available index in the DESQ.
218	*/
219	static int mv_xor_v2_get_desq_write_ptr(struct mv_xor_v2_device *xor_dev)
220	{
221	/* read the index for the next available descriptor in the DESQ */
222	u32 reg = readl(xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_ALLOC_OFF);
223
224	return ((reg >> MV_XOR_V2_DMA_DESQ_ALLOC_WRPTR_SHIFT)
225	& MV_XOR_V2_DMA_DESQ_ALLOC_WRPTR_MASK);
226	}
227
228	/*	217	/*
229	* notify the engine of new descriptors, and update the available index.	218	* notify the engine of new descriptors, and update the available index.
230	*/	219	*/
@@ -257,22 +246,6 @@ static int mv_xor_v2_set_desc_size(struct mv_xor_v2_device *xor_dev) · 26 unmodified lines
257	return MV_XOR_V2_EXT_DESC_SIZE;	246	return MV_XOR_V2_EXT_DESC_SIZE;
258	}	247	}
259		248
260	/*
261	* Set the IMSG threshold
262	*/
263	static inline
264	void mv_xor_v2_set_imsg_thrd(struct mv_xor_v2_device *xor_dev, int thrd_val)
265	{
266	u32 reg;
267
268	reg = readl(xor_dev->dma_base + MV_XOR_V2_DMA_IMSG_THRD_OFF);
269
270	reg &= (~MV_XOR_V2_DMA_IMSG_THRD_MASK << MV_XOR_V2_DMA_IMSG_THRD_SHIFT);
271	reg \|= (thrd_val << MV_XOR_V2_DMA_IMSG_THRD_SHIFT);
272
273	writel(reg, xor_dev->dma_base + MV_XOR_V2_DMA_IMSG_THRD_OFF);
274	}
275
276	static irqreturn_t mv_xor_v2_interrupt_handler(int irq, void *data)	249	static irqreturn_t mv_xor_v2_interrupt_handler(int irq, void *data)
277	{	250	{
278	struct mv_xor_v2_device *xor_dev = data;	251	struct mv_xor_v2_device *xor_dev = data;
@@ -288,12 +261,6 @@ static irqreturn_t mv_xor_v2_interrupt_handler(int irq, void *data) · 9 unmodified lines
288	if (!ndescs)	261	if (!ndescs)
289	return IRQ_NONE;	262	return IRQ_NONE;
290		263
291	/*
292	* Update IMSG threshold, to disable new IMSG interrupts until
293	* end of the tasklet
294	*/
295	mv_xor_v2_set_imsg_thrd(xor_dev, MV_XOR_V2_DESC_NUM);
296
297	/* schedule a tasklet to handle descriptors callbacks */	264	/* schedule a tasklet to handle descriptors callbacks */
298	tasklet_schedule(&xor_dev->irq_tasklet);	265	tasklet_schedule(&xor_dev->irq_tasklet);
299		266
@@ -306,7 +273,6 @@ static irqreturn_t mv_xor_v2_interrupt_handler(int irq, void *data) · 6 unmodified lines
306	static dma_cookie_t	273	static dma_cookie_t
307	mv_xor_v2_tx_submit(struct dma_async_tx_descriptor *tx)	274	mv_xor_v2_tx_submit(struct dma_async_tx_descriptor *tx)
308	{	275	{
309	int desq_ptr;
310	void *dest_hw_desc;	276	void *dest_hw_desc;
311	dma_cookie_t cookie;	277	dma_cookie_t cookie;
312	struct mv_xor_v2_sw_desc *sw_desc =	278	struct mv_xor_v2_sw_desc *sw_desc =
@@ -322,15 +288,15 @@ mv_xor_v2_tx_submit(struct dma_async_tx_descriptor *tx) · 9 unmodified lines
322	spin_lock_bh(&xor_dev->lock);	288	spin_lock_bh(&xor_dev->lock);
323	cookie = dma_cookie_assign(tx);	289	cookie = dma_cookie_assign(tx);
324		290
325	/* get the next available slot in the DESQ */
326	desq_ptr = mv_xor_v2_get_desq_write_ptr(xor_dev);
327
328	/* copy the HW descriptor from the SW descriptor to the DESQ */	291	/* copy the HW descriptor from the SW descriptor to the DESQ */
329	dest_hw_desc = xor_dev->hw_desq_virt + desq_ptr;	292	dest_hw_desc = xor_dev->hw_desq_virt + xor_dev->hw_queue_idx;
330		293
331	memcpy(dest_hw_desc, &sw_desc->hw_desc, xor_dev->desc_size);	294	memcpy(dest_hw_desc, &sw_desc->hw_desc, xor_dev->desc_size);
332		295
333	xor_dev->npendings++;	296	xor_dev->npendings++;
		297	xor_dev->hw_queue_idx++;
		298	if (xor_dev->hw_queue_idx >= MV_XOR_V2_DESC_NUM)
		299	xor_dev->hw_queue_idx = 0;
334		300
335	spin_unlock_bh(&xor_dev->lock);	301	spin_unlock_bh(&xor_dev->lock);
336		302
@@ -344,6 +310,7 @@ static struct mv_xor_v2_sw_desc * · 7 unmodified lines
344	mv_xor_v2_prep_sw_desc(struct mv_xor_v2_device *xor_dev)	310	mv_xor_v2_prep_sw_desc(struct mv_xor_v2_device *xor_dev)
345	{	311	{
346	struct mv_xor_v2_sw_desc *sw_desc;	312	struct mv_xor_v2_sw_desc *sw_desc;
		313	bool found = false;
347		314
348	/* Lock the channel */	315	/* Lock the channel */
349	spin_lock_bh(&xor_dev->lock);	316	spin_lock_bh(&xor_dev->lock);
@@ -355,19 +322,23 @@ mv_xor_v2_prep_sw_desc(struct mv_xor_v2_device *xor_dev) · 5 unmodified lines
355	return NULL;	322	return NULL;
356	}	323	}
357		324
358	/* get a free SW descriptor from the SW DESQ */	325	list_for_each_entry(sw_desc, &xor_dev->free_sw_desc, free_list) {
359	sw_desc = list_first_entry(&xor_dev->free_sw_desc,	326	if (async_tx_test_ack(&sw_desc->async_tx)) {
360	struct mv_xor_v2_sw_desc, free_list);	327	found = true;
		328	break;
		329	}
		330	}
		331
		332	if (!found) {
		333	spin_unlock_bh(&xor_dev->lock);
		334	return NULL;
		335	}
		336
361	list_del(&sw_desc->free_list);	337	list_del(&sw_desc->free_list);
362		338
363	/* Release the channel */	339	/* Release the channel */
364	spin_unlock_bh(&xor_dev->lock);	340	spin_unlock_bh(&xor_dev->lock);
365		341
366	/* set the async tx descriptor */
367	dma_async_tx_descriptor_init(&sw_desc->async_tx, &xor_dev->dmachan);
368	sw_desc->async_tx.tx_submit = mv_xor_v2_tx_submit;
369	async_tx_ack(&sw_desc->async_tx);
370
371	return sw_desc;	342	return sw_desc;
372	}	343	}
373		344
@@ -389,6 +360,8 @@ mv_xor_v2_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, · 15 unmodified lines
389	__func__, len, &src, &dest, flags);	360	__func__, len, &src, &dest, flags);
390		361
391	sw_desc = mv_xor_v2_prep_sw_desc(xor_dev);	362	sw_desc = mv_xor_v2_prep_sw_desc(xor_dev);
		363	if (!sw_desc)
		364	return NULL;
392		365
393	sw_desc->async_tx.flags = flags;	366	sw_desc->async_tx.flags = flags;
394		367
@@ -443,6 +416,8 @@ mv_xor_v2_prep_dma_xor(struct dma_chan chan, dma_addr_t dest, dma_addr_t src, · 48 unmodified lines
443	__func__, src_cnt, len, &dest, flags);	416	__func__, src_cnt, len, &dest, flags);
444		417
445	sw_desc = mv_xor_v2_prep_sw_desc(xor_dev);	418	sw_desc = mv_xor_v2_prep_sw_desc(xor_dev);
		419	if (!sw_desc)
		420	return NULL;
446		421
447	sw_desc->async_tx.flags = flags;	422	sw_desc->async_tx.flags = flags;
448		423
@@ -491,6 +466,8 @@ mv_xor_v2_prep_dma_interrupt(struct dma_chan *chan, unsigned long flags) · 42 unmodified lines
491	container_of(chan, struct mv_xor_v2_device, dmachan);	466	container_of(chan, struct mv_xor_v2_device, dmachan);
492		467
493	sw_desc = mv_xor_v2_prep_sw_desc(xor_dev);	468	sw_desc = mv_xor_v2_prep_sw_desc(xor_dev);
		469	if (!sw_desc)
		470	return NULL;
494		471
495	/* set the HW descriptor */	472	/* set the HW descriptor */
496	hw_descriptor = &sw_desc->hw_desc;	473	hw_descriptor = &sw_desc->hw_desc;
@@ -554,7 +531,6 @@ static void mv_xor_v2_tasklet(unsigned long data) · 57 unmodified lines
554	{	531	{
555	struct mv_xor_v2_device xor_dev = (struct mv_xor_v2_device ) data;	532	struct mv_xor_v2_device xor_dev = (struct mv_xor_v2_device ) data;
556	int pending_ptr, num_of_pending, i;	533	int pending_ptr, num_of_pending, i;
557	struct mv_xor_v2_descriptor *next_pending_hw_desc = NULL;
558	struct mv_xor_v2_sw_desc *next_pending_sw_desc = NULL;	534	struct mv_xor_v2_sw_desc *next_pending_sw_desc = NULL;
559		535
560	dev_dbg(xor_dev->dmadev.dev, "%s %d\n", __func__, __LINE__);	536	dev_dbg(xor_dev->dmadev.dev, "%s %d\n", __func__, __LINE__);
@@ -562,17 +538,10 @@ static void mv_xor_v2_tasklet(unsigned long data) · 1 unmodified line
562	/* get the pending descriptors parameters */	538	/* get the pending descriptors parameters */
563	num_of_pending = mv_xor_v2_get_pending_params(xor_dev, &pending_ptr);	539	num_of_pending = mv_xor_v2_get_pending_params(xor_dev, &pending_ptr);
564		540
565	/* next HW descriptor */
566	next_pending_hw_desc = xor_dev->hw_desq_virt + pending_ptr;
567
568	/* loop over free descriptors */	541	/* loop over free descriptors */
569	for (i = 0; i < num_of_pending; i++) {	542	for (i = 0; i < num_of_pending; i++) {
570		543	struct mv_xor_v2_descriptor *next_pending_hw_desc =
571	if (pending_ptr > MV_XOR_V2_DESC_NUM)	544	xor_dev->hw_desq_virt + pending_ptr;
572	pending_ptr = 0;
573
574	if (next_pending_sw_desc != NULL)
575	next_pending_hw_desc++;
576		545
577	/* get the SW descriptor related to the HW descriptor */	546	/* get the SW descriptor related to the HW descriptor */
578	next_pending_sw_desc =	547	next_pending_sw_desc =
@@ -608,15 +577,14 @@ static void mv_xor_v2_tasklet(unsigned long data) · 29 unmodified lines
608		577
609	/* increment the next descriptor */	578	/* increment the next descriptor */
610	pending_ptr++;	579	pending_ptr++;
		580	if (pending_ptr >= MV_XOR_V2_DESC_NUM)
		581	pending_ptr = 0;
611	}	582	}
612		583
613	if (num_of_pending != 0) {	584	if (num_of_pending != 0) {
614	/* free the descriptores */	585	/* free the descriptores */
615	mv_xor_v2_free_desc_from_desq(xor_dev, num_of_pending);	586	mv_xor_v2_free_desc_from_desq(xor_dev, num_of_pending);
616	}	587	}
617
618	/* Update IMSG threshold, to enable new IMSG interrupts */
619	mv_xor_v2_set_imsg_thrd(xor_dev, 0);
620	}	588	}
621		589
622	/*	590	/*
@@ -648,9 +616,6 @@ static int mv_xor_v2_descq_init(struct mv_xor_v2_device *xor_dev) · 25 unmodified lines
648	writel((xor_dev->hw_desq & 0xFFFF00000000) >> 32,	616	writel((xor_dev->hw_desq & 0xFFFF00000000) >> 32,
649	xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_BAHR_OFF);	617	xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_BAHR_OFF);
650		618
651	/* enable the DMA engine */
652	writel(0, xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_STOP_OFF);
653
654	/*	619	/*
655	* This is a temporary solution, until we activate the	620	* This is a temporary solution, until we activate the
656	* SMMU. Set the attributes for reading & writing data buffers	621	* SMMU. Set the attributes for reading & writing data buffers
@@ -694,6 +659,9 @@ static int mv_xor_v2_descq_init(struct mv_xor_v2_device *xor_dev) · 37 unmodified lines
694	reg \|= MV_XOR_V2_GLOB_PAUSE_AXI_TIME_DIS_VAL;	659	reg \|= MV_XOR_V2_GLOB_PAUSE_AXI_TIME_DIS_VAL;
695	writel(reg, xor_dev->glob_base + MV_XOR_V2_GLOB_PAUSE);	660	writel(reg, xor_dev->glob_base + MV_XOR_V2_GLOB_PAUSE);
696		661
		662	/* enable the DMA engine */
		663	writel(0, xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_STOP_OFF);
		664
697	return 0;	665	return 0;
698	}	666	}
699		667
@@ -725,6 +693,10 @@ static int mv_xor_v2_probe(struct platform_device *pdev) · 25 unmodified lines
725		693
726	platform_set_drvdata(pdev, xor_dev);	694	platform_set_drvdata(pdev, xor_dev);
727		695
		696	ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40));
		697	if (ret)
		698	return ret;
		699
728	xor_dev->clk = devm_clk_get(&pdev->dev, NULL);	700	xor_dev->clk = devm_clk_get(&pdev->dev, NULL);
729	if (IS_ERR(xor_dev->clk) && PTR_ERR(xor_dev->clk) == -EPROBE_DEFER)	701	if (IS_ERR(xor_dev->clk) && PTR_ERR(xor_dev->clk) == -EPROBE_DEFER)
730	return -EPROBE_DEFER;	702	return -EPROBE_DEFER;
@@ -785,8 +757,15 @@ static int mv_xor_v2_probe(struct platform_device *pdev) · 54 unmodified lines
785		757
786	/* add all SW descriptors to the free list */	758	/* add all SW descriptors to the free list */
787	for (i = 0; i < MV_XOR_V2_DESC_NUM; i++) {	759	for (i = 0; i < MV_XOR_V2_DESC_NUM; i++) {
788	xor_dev->sw_desq[i].idx = i;	760	struct mv_xor_v2_sw_desc *sw_desc =
789	list_add(&xor_dev->sw_desq[i].free_list,	761	xor_dev->sw_desq + i;
		762	sw_desc->idx = i;
		763	dma_async_tx_descriptor_init(&sw_desc->async_tx,
		764	&xor_dev->dmachan);
		765	sw_desc->async_tx.tx_submit = mv_xor_v2_tx_submit;
		766	async_tx_ack(&sw_desc->async_tx);
		767
		768	list_add(&sw_desc->free_list,
790	&xor_dev->free_sw_desc);	769	&xor_dev->free_sw_desc);
791	}	770	}
792		771

drivers/dma/pl330.c+2−1

@@ -3008,7 +3008,8 @@ static int pl330_remove(struct amba_device *adev) · 3007 unmodified lines
3008		3008
3009	for (i = 0; i < AMBA_NR_IRQS; i++) {	3009	for (i = 0; i < AMBA_NR_IRQS; i++) {
3010	irq = adev->irq[i];	3010	irq = adev->irq[i];
3011	devm_free_irq(&adev->dev, irq, pl330);	3011	if (irq)
		3012	devm_free_irq(&adev->dev, irq, pl330);
3012	}	3013	}
3013		3014
3014	dma_async_device_unregister(&pl330->ddma);	3015	dma_async_device_unregister(&pl330->ddma);

drivers/dma/sh/rcar-dmac.c+3−0

 	if (desc->hwdescs.use) {
 		dptr = (rcar_dmac_chan_read(chan, RCAR_DMACHCRB) &
 			RCAR_DMACHCRB_DPTR_MASK) >> RCAR_DMACHCRB_DPTR_SHIFT;
+		if (dptr == 0)
+			dptr = desc->nchunks;
+		dptr--;
 		WARN_ON(dptr >= desc->nchunks);
 	} else {
 		running = desc->running;

drivers/dma/sh/usb-dmac.c+1−1

@@ -117,7 +117,7 @@ struct usb_dmac { · 116 unmodified lines
117	#define USB_DMASWR 0x0008	117	#define USB_DMASWR 0x0008
118	#define USB_DMASWR_SWR (1 << 0)	118	#define USB_DMASWR_SWR (1 << 0)
119	#define USB_DMAOR 0x0060	119	#define USB_DMAOR 0x0060
120	#define USB_DMAOR_AE (1 << 2)	120	#define USB_DMAOR_AE (1 << 1)
121	#define USB_DMAOR_DME (1 << 0)	121	#define USB_DMAOR_DME (1 << 0)
122		122
123	#define USB_DMASAR 0x0000	123	#define USB_DMASAR 0x0000

drivers/firmware/dmi-id.c+2−0

 DEFINE_DMI_ATTR_WITH_SHOW(product_version,	0444, DMI_PRODUCT_VERSION);
 DEFINE_DMI_ATTR_WITH_SHOW(product_serial,	0400, DMI_PRODUCT_SERIAL);
 DEFINE_DMI_ATTR_WITH_SHOW(product_uuid,		0400, DMI_PRODUCT_UUID);
+DEFINE_DMI_ATTR_WITH_SHOW(product_family,	0444, DMI_PRODUCT_FAMILY);
 DEFINE_DMI_ATTR_WITH_SHOW(board_vendor,		0444, DMI_BOARD_VENDOR);
 DEFINE_DMI_ATTR_WITH_SHOW(board_name,		0444, DMI_BOARD_NAME);
 DEFINE_DMI_ATTR_WITH_SHOW(board_version,	0444, DMI_BOARD_VERSION);
 	ADD_DMI_ATTR(product_version,   DMI_PRODUCT_VERSION);
 	ADD_DMI_ATTR(product_serial,    DMI_PRODUCT_SERIAL);
 	ADD_DMI_ATTR(product_uuid,      DMI_PRODUCT_UUID);
+	ADD_DMI_ATTR(product_family,    DMI_PRODUCT_FAMILY);
 	ADD_DMI_ATTR(board_vendor,      DMI_BOARD_VENDOR);
 	ADD_DMI_ATTR(board_name,        DMI_BOARD_NAME);
 	ADD_DMI_ATTR(board_version,     DMI_BOARD_VERSION);

drivers/firmware/dmi_scan.c+38−12

 	buf = dmi_early_remap(dmi_base, orig_dmi_len);
 	if (buf == NULL)
-		return -1;
+		return -ENOMEM;
 	dmi_decode_table(buf, decode, NULL);
 	const char *d = (const char *) dm;
 	const char *p;
-	if (dmi_ident[slot])
+	if (dmi_ident[slot] || dm->length <= string)
 		return;
 	p = dmi_string(dm, d[string]);
 static void __init dmi_save_uuid(const struct dmi_header *dm, int slot,
 		int index)
 {
-	const u8 *d = (u8 *) dm + index;
+	const u8 *d;
 	char *s;
 	int is_ff = 1, is_00 = 1, i;
-	if (dmi_ident[slot])
+	if (dmi_ident[slot] || dm->length <= index + 16)
 		return;
+	d = (u8 *) dm + index;
 	for (i = 0; i < 16 && (is_ff || is_00); i++) {
 		if (d[i] != 0x00)
 			is_00 = 0;
 static void __init dmi_save_type(const struct dmi_header *dm, int slot,
 		int index)
 {
-	const u8 *d = (u8 *) dm + index;
+	const u8 *d;
 	char *s;
-	if (dmi_ident[slot])
+	if (dmi_ident[slot] || dm->length <= index)
 		return;
 	s = dmi_alloc(4);
 	if (!s)
 		return;
+	d = (u8 *) dm + index;
 	sprintf(s, "%u", *d & 0x7F);
 	dmi_ident[slot] = s;
 }
 static void __init dmi_save_oem_strings_devices(const struct dmi_header *dm)
 {
-	int i, count = *(u8 *)(dm + 1);
+	int i, count;
 	struct dmi_device *dev;
+	if (dm->length < 0x05)
+		return;
+	count = *(u8 *)(dm + 1);
 	for (i = 1; i <= count; i++) {
 		const char *devname = dmi_string(dm, i);
 	const char *name;
 	const u8 *d = (u8 *)dm;
+	if (dm->length < 0x0B)
+		return;
 	/* Skip disabled device */
 	if ((d[0x5] & 0x80) == 0)
 		return;
 	const char *d = (const char *)dm;
 	static int nr;
-	if (dm->type != DMI_ENTRY_MEM_DEVICE)
+	if (dm->type != DMI_ENTRY_MEM_DEVICE || dm->length < 0x12)
 		return;
 	if (nr >= dmi_memdev_nr) {
 		pr_warn(FW_BUG "Too many DIMM entries in SMBIOS table\n");
 		dmi_save_ident(dm, DMI_PRODUCT_VERSION, 6);
 		dmi_save_ident(dm, DMI_PRODUCT_SERIAL, 7);
 		dmi_save_uuid(dm, DMI_PRODUCT_UUID, 8);
+		dmi_save_ident(dm, DMI_PRODUCT_FAMILY, 26);
 		break;
 	case 2:		/* Base Board Information */
 		dmi_save_ident(dm, DMI_BOARD_VENDOR, 4);
 		if (p == NULL)
 			goto error;
+		/*
+		 * Same logic as above, look for a 64-bit entry point
+		 * first, and if not found, fall back to 32-bit entry point.
+		 */
+		memcpy_fromio(buf, p, 16);
+		for (q = p + 16; q < p + 0x10000; q += 16) {
+			memcpy_fromio(buf + 16, q, 16);
+			if (!dmi_smbios3_present(buf)) {
+				dmi_available = 1;
+				dmi_early_unmap(p, 0x10000);
+				goto out;
+			}
+			memcpy(buf, buf + 16, 16);
+		}
 		/*
 		 * Iterate over all possible DMI header addresses q.
 		 * Maintain the 32 bytes around q in buf.  On the
 		memset(buf, 0, 16);
 		for (q = p; q < p + 0x10000; q += 16) {
 			memcpy_fromio(buf + 16, q, 16);
-			if (!dmi_smbios3_present(buf) || !dmi_present(buf)) {
+			if (!dmi_present(buf)) {
 				dmi_available = 1;
 				dmi_early_unmap(p, 0x10000);
 				goto out;
  *	@decode: Callback function
  *	@private_data: Private data to be passed to the callback function
  *
- *	Returns -1 when the DMI table can't be reached, 0 on success.
+ *	Returns 0 on success, -ENXIO if DMI is not selected or not present,
+ *	or a different negative error code if DMI walking fails.
  */
 int dmi_walk(void (*decode)(const struct dmi_header *, void *),
 	     void *private_data)
 	u8 *buf;
 	if (!dmi_available)
-		return -1;
+		return -ENXIO;
 	buf = dmi_remap(dmi_base, dmi_len);
 	if (buf == NULL)
-		return -1;
+		return -ENOMEM;
 	dmi_decode_table(buf, decode, private_data);

drivers/firmware/efi/efi-bgrt.c+27−0

@@ -27,6 +27,26 @@ struct bmp_header { · 26 unmodified lines
27	u32 size;	27	u32 size;
28	} __packed;	28	} __packed;
29		29
		30	static bool efi_bgrt_addr_valid(u64 addr)
		31	{
		32	efi_memory_desc_t *md;
		33
		34	for_each_efi_memory_desc(md) {
		35	u64 size;
		36	u64 end;
		37
		38	if (md->type != EFI_BOOT_SERVICES_DATA)
		39	continue;
		40
		41	size = md->num_pages << EFI_PAGE_SHIFT;
		42	end = md->phys_addr + size;
		43	if (addr >= md->phys_addr && addr < end)
		44	return true;
		45	}
		46
		47	return false;
		48	}
		49
30	void __init efi_bgrt_init(struct acpi_table_header *table)	50	void __init efi_bgrt_init(struct acpi_table_header *table)
31	{	51	{
32	void *image;	52	void *image;
@@ -36,6 +56,9 @@ void __init efi_bgrt_init(struct acpi_table_header *table) · 3 unmodified lines
36	if (acpi_disabled)	56	if (acpi_disabled)
37	return;	57	return;
38		58
		59	if (!efi_enabled(EFI_MEMMAP))
		60	return;
		61
39	if (table->length < sizeof(bgrt_tab)) {	62	if (table->length < sizeof(bgrt_tab)) {
40	pr_notice("Ignoring BGRT: invalid length %u (expected %zu)\n",	63	pr_notice("Ignoring BGRT: invalid length %u (expected %zu)\n",
41	table->length, sizeof(bgrt_tab));	64	table->length, sizeof(bgrt_tab));
@@ -62,6 +85,10 @@ void __init efi_bgrt_init(struct acpi_table_header *table) · 20 unmodified lines
62	goto out;	85	goto out;
63	}	86	}
64		87
		88	if (!efi_bgrt_addr_valid(bgrt->image_address)) {
		89	pr_notice("Ignoring BGRT: invalid image address\n");
		90	goto out;
		91	}
65	image = early_memremap(bgrt->image_address, sizeof(bmp_header));	92	image = early_memremap(bgrt->image_address, sizeof(bmp_header));
66	if (!image) {	93	if (!image) {
67	pr_notice("Ignoring BGRT: failed to map image header memory\n");	94	pr_notice("Ignoring BGRT: failed to map image header memory\n");

drivers/firmware/efi/libstub/secureboot.c+2−2

@@ -16,10 +16,10 @@ · 15 unmodified lines
16		16
17	/* BIOS variables */	17	/* BIOS variables */
18	static const efi_guid_t efi_variable_guid = EFI_GLOBAL_VARIABLE_GUID;	18	static const efi_guid_t efi_variable_guid = EFI_GLOBAL_VARIABLE_GUID;
19	static const efi_char16_t const efi_SecureBoot_name[] = {	19	static const efi_char16_t efi_SecureBoot_name[] = {
20	'S', 'e', 'c', 'u', 'r', 'e', 'B', 'o', 'o', 't', 0	20	'S', 'e', 'c', 'u', 'r', 'e', 'B', 'o', 'o', 't', 0
21	};	21	};
22	static const efi_char16_t const efi_SetupMode_name[] = {	22	static const efi_char16_t efi_SetupMode_name[] = {
23	'S', 'e', 't', 'u', 'p', 'M', 'o', 'd', 'e', 0	23	'S', 'e', 't', 'u', 'p', 'M', 'o', 'd', 'e', 0
24	};	24	};
25		25

drivers/firmware/google/vpd.c+4−4

 	info->value = value;
 	INIT_LIST_HEAD(&info->list);
-	list_add_tail(&info->list, &sec->attribs);
 	ret = sysfs_create_bin_file(sec->kobj, &info->bin_attr);
 	if (ret)
 		goto free_info_key;
+	list_add_tail(&info->list, &sec->attribs);
 	return 0;
 free_info_key:
 	struct vpd_attrib_info *temp;
 	list_for_each_entry_safe(info, temp, &sec->attribs, list) {
-		kfree(info->key);
 		sysfs_remove_bin_file(sec->kobj, &info->bin_attr);
+		kfree(info->key);
 		kfree(info);
 	}
 }
 {
 	if (sec->enabled) {
 		vpd_section_attrib_destroy(sec);
-		kobject_del(sec->kobj);
+		kobject_put(sec->kobj);
 		sysfs_remove_bin_file(vpd_kobj, &sec->bin_attr);
 		kfree(sec->raw_name);
 		iounmap(sec->baseaddr);
 {
 	vpd_section_destroy(&ro_vpd);
 	vpd_section_destroy(&rw_vpd);
-	kobject_del(vpd_kobj);
+	kobject_put(vpd_kobj);
 }
 module_init(vpd_platform_init);

drivers/gpio/gpio-aspeed.c+3−0

@@ -646,6 +646,9 @@ static int enable_debounce(struct gpio_chip *chip, unsigned int offset, · 645 unmodified lines
646	int rc;	646	int rc;
647	int i;	647	int i;
648		648
		649	if (!gpio->clk)
		650	return -EINVAL;
		651
649	rc = usecs_to_cycles(gpio, usecs, &requested_cycles);	652	rc = usecs_to_cycles(gpio, usecs, &requested_cycles);
650	if (rc < 0) {	653	if (rc < 0) {
651	dev_warn(chip->parent, "Failed to convert %luus to cycles at %luHz: %d\n",	654	dev_warn(chip->parent, "Failed to convert %luus to cycles at %luHz: %d\n",

drivers/gpio/gpio-crystalcove.c+36−18

 {
 	int reg;
-	if (gpio == 94)
+	if (gpio >= CRYSTALCOVE_GPIO_NUM) {
-		return GPIOPANELCTL;
+		/*
+		 * Virtual GPIO called from ACPI, for now we only support
+		 * the panel ctl.
+		 */
+		switch (gpio) {
+		case 0x5e:
+			return GPIOPANELCTL;
+		default:
+			return -EOPNOTSUPP;
+		}
+	}
 	if (reg_type == CTRL_IN) {
 		if (gpio < 8)
 static int crystalcove_gpio_dir_in(struct gpio_chip *chip, unsigned gpio)
 {
 	struct crystalcove_gpio *cg = gpiochip_get_data(chip);
+	int reg = to_reg(gpio, CTRL_OUT);
-	if (gpio > CRYSTALCOVE_VGPIO_NUM)
+	if (reg < 0)
 		return 0;
-	return regmap_write(cg->regmap, to_reg(gpio, CTRL_OUT),
+	return regmap_write(cg->regmap, reg, CTLO_INPUT_SET);
-			    CTLO_INPUT_SET);
 }
 static int crystalcove_gpio_dir_out(struct gpio_chip *chip, unsigned gpio,
 				    int value)
 {
 	struct crystalcove_gpio *cg = gpiochip_get_data(chip);
+	int reg = to_reg(gpio, CTRL_OUT);
-	if (gpio > CRYSTALCOVE_VGPIO_NUM)
+	if (reg < 0)
 		return 0;
-	return regmap_write(cg->regmap, to_reg(gpio, CTRL_OUT),
+	return regmap_write(cg->regmap, reg, CTLO_OUTPUT_SET | value);
-			    CTLO_OUTPUT_SET | value);
 }
 static int crystalcove_gpio_get(struct gpio_chip *chip, unsigned gpio)
 {
 	struct crystalcove_gpio *cg = gpiochip_get_data(chip);
-	int ret;
 	unsigned int val;
+	int ret, reg = to_reg(gpio, CTRL_IN);
-	if (gpio > CRYSTALCOVE_VGPIO_NUM)
+	if (reg < 0)
 		return 0;
-	ret = regmap_read(cg->regmap, to_reg(gpio, CTRL_IN), &val);
+	ret = regmap_read(cg->regmap, reg, &val);
 	if (ret)
 		return ret;
 				 unsigned gpio, int value)
 {
 	struct crystalcove_gpio *cg = gpiochip_get_data(chip);
+	int reg = to_reg(gpio, CTRL_OUT);
-	if (gpio > CRYSTALCOVE_VGPIO_NUM)
+	if (reg < 0)
 		return;
 	if (value)
-		regmap_update_bits(cg->regmap, to_reg(gpio, CTRL_OUT), 1, 1);
+		regmap_update_bits(cg->regmap, reg, 1, 1);
 	else
-		regmap_update_bits(cg->regmap, to_reg(gpio, CTRL_OUT), 1, 0);
+		regmap_update_bits(cg->regmap, reg, 1, 0);
 }
 static int crystalcove_irq_type(struct irq_data *data, unsigned type)
 	struct crystalcove_gpio *cg =
 		gpiochip_get_data(irq_data_get_irq_chip_data(data));
+	if (data->hwirq >= CRYSTALCOVE_GPIO_NUM)
+		return 0;
 	switch (type) {
 	case IRQ_TYPE_NONE:
 		cg->intcnt_value = CTLI_INTCNT_DIS;
 	struct crystalcove_gpio *cg =
 		gpiochip_get_data(irq_data_get_irq_chip_data(data));
-	cg->set_irq_mask = false;
+	if (data->hwirq < CRYSTALCOVE_GPIO_NUM) {
-	cg->update |= UPDATE_IRQ_MASK;
+		cg->set_irq_mask = false;
+		cg->update |= UPDATE_IRQ_MASK;
+	}
 }
 static void crystalcove_irq_mask(struct irq_data *data)
 	struct crystalcove_gpio *cg =
 		gpiochip_get_data(irq_data_get_irq_chip_data(data));
-	cg->set_irq_mask = true;
+	if (data->hwirq < CRYSTALCOVE_GPIO_NUM) {
-	cg->update |= UPDATE_IRQ_MASK;
+		cg->set_irq_mask = true;
+		cg->update |= UPDATE_IRQ_MASK;
+	}
 }
 static struct irq_chip crystalcove_irqchip = {

drivers/gpio/gpio-mvebu.c+8−1

 		set = U32_MAX;
 	else
 		return -EINVAL;
-	writel_relaxed(0, mvebu_gpioreg_blink_counter_select(mvchip));
+	writel_relaxed(set, mvebu_gpioreg_blink_counter_select(mvchip));
 	mvpwm = devm_kzalloc(dev, sizeof(struct mvebu_pwm), GFP_KERNEL);
 	if (!mvpwm)
 	mvpwm->chip.dev = dev;
 	mvpwm->chip.ops = &mvebu_pwm_ops;
 	mvpwm->chip.npwm = mvchip->chip.ngpio;
+	/*
+	 * There may already be some PWM allocated, so we can't force
+	 * mvpwm->chip.base to a fixed point like mvchip->chip.base.
+	 * So, we let pwmchip_add() do the numbering and take the next free
+	 * region.
+	 */
+	mvpwm->chip.base = -1;
 	spin_lock_init(&mvpwm->lock);

drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c+5−5

@@ -220,9 +220,9 @@ static void amdgpu_vram_mgr_debug(struct ttm_mem_type_manager *man, · 219 unmodified lines
220	}	220	}
221		221
222	const struct ttm_mem_type_manager_func amdgpu_vram_mgr_func = {	222	const struct ttm_mem_type_manager_func amdgpu_vram_mgr_func = {
223	amdgpu_vram_mgr_init,	223	.init = amdgpu_vram_mgr_init,
224	amdgpu_vram_mgr_fini,	224	.takedown = amdgpu_vram_mgr_fini,
225	amdgpu_vram_mgr_new,	225	.get_node = amdgpu_vram_mgr_new,
226	amdgpu_vram_mgr_del,	226	.put_node = amdgpu_vram_mgr_del,
227	amdgpu_vram_mgr_debug	227	.debug = amdgpu_vram_mgr_debug
228	};	228	};

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c+5−2

 	u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
 	if (amdgpu_crtc->base.enabled && num_heads && mode) {
-		active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock;
+		active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
-		line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535);
+					    (u32)mode->clock);
+		line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
+					  (u32)mode->clock);
+		line_time = min(line_time, (u32)65535);
 		/* watermark for high clocks */
 		if (adev->pm.dpm_enabled) {

drivers/gpu/drm/amd/amdgpu/dce_v11_0.c+5−2

 	u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
 	if (amdgpu_crtc->base.enabled && num_heads && mode) {
-		active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock;
+		active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
-		line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535);
+					    (u32)mode->clock);
+		line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
+					  (u32)mode->clock);
+		line_time = min(line_time, (u32)65535);
 		/* watermark for high clocks */
 		if (adev->pm.dpm_enabled) {

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c+5−2

 	fixed20_12 a, b, c;
 	if (amdgpu_crtc->base.enabled && num_heads && mode) {
-		active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock;
+		active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
-		line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535);
+					    (u32)mode->clock);
+		line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
+					  (u32)mode->clock);
+		line_time = min(line_time, (u32)65535);
 		priority_a_cnt = 0;
 		priority_b_cnt = 0;

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c+5−2

 	u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
 	if (amdgpu_crtc->base.enabled && num_heads && mode) {
-		active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock;
+		active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
-		line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535);
+					    (u32)mode->clock);
+		line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
+					  (u32)mode->clock);
+		line_time = min(line_time, (u32)65535);
 		/* watermark for high clocks */
 		if (adev->pm.dpm_enabled) {

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c+68−27

 static uint64_t vce_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
 {
 	struct amdgpu_device *adev = ring->adev;
+	u32 v;
+	mutex_lock(&adev->grbm_idx_mutex);
+	if (adev->vce.harvest_config == 0 ||
+		adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE1)
+		WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0));
+	else if (adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0)
+		WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1));
 	if (ring == &adev->vce.ring[0])
-		return RREG32(mmVCE_RB_RPTR);
+		v = RREG32(mmVCE_RB_RPTR);
 	else if (ring == &adev->vce.ring[1])
-		return RREG32(mmVCE_RB_RPTR2);
+		v = RREG32(mmVCE_RB_RPTR2);
 	else
-		return RREG32(mmVCE_RB_RPTR3);
+		v = RREG32(mmVCE_RB_RPTR3);
+	WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);
+	mutex_unlock(&adev->grbm_idx_mutex);
+	return v;
 }
 /**
 static uint64_t vce_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
 {
 	struct amdgpu_device *adev = ring->adev;
+	u32 v;
+	mutex_lock(&adev->grbm_idx_mutex);
+	if (adev->vce.harvest_config == 0 ||
+		adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE1)
+		WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0));
+	else if (adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0)
+		WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1));
 	if (ring == &adev->vce.ring[0])
-		return RREG32(mmVCE_RB_WPTR);
+		v = RREG32(mmVCE_RB_WPTR);
 	else if (ring == &adev->vce.ring[1])
-		return RREG32(mmVCE_RB_WPTR2);
+		v = RREG32(mmVCE_RB_WPTR2);
 	else
-		return RREG32(mmVCE_RB_WPTR3);
+		v = RREG32(mmVCE_RB_WPTR3);
+	WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);
+	mutex_unlock(&adev->grbm_idx_mutex);
+	return v;
 }
 /**
 {
 	struct amdgpu_device *adev = ring->adev;
+	mutex_lock(&adev->grbm_idx_mutex);
+	if (adev->vce.harvest_config == 0 ||
+		adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE1)
+		WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0));
+	else if (adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0)
+		WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1));
 	if (ring == &adev->vce.ring[0])
 		WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
 	else if (ring == &adev->vce.ring[1])
 		WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));
 	else
 		WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr));
+	WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);
+	mutex_unlock(&adev->grbm_idx_mutex);
 }
 static void vce_v3_0_override_vce_clock_gating(struct amdgpu_device *adev, bool override)
 	struct amdgpu_ring *ring;
 	int idx, r;
-	ring = &adev->vce.ring[0];
-	WREG32(mmVCE_RB_RPTR, lower_32_bits(ring->wptr));
-	WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
-	WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr);
-	WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
-	WREG32(mmVCE_RB_SIZE, ring->ring_size / 4);
-	ring = &adev->vce.ring[1];
-	WREG32(mmVCE_RB_RPTR2, lower_32_bits(ring->wptr));
-	WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));
-	WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr);
-	WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
-	WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4);
-	ring = &adev->vce.ring[2];
-	WREG32(mmVCE_RB_RPTR3, lower_32_bits(ring->wptr));
-	WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr));
-	WREG32(mmVCE_RB_BASE_LO3, ring->gpu_addr);
-	WREG32(mmVCE_RB_BASE_HI3, upper_32_bits(ring->gpu_addr));
-	WREG32(mmVCE_RB_SIZE3, ring->ring_size / 4);
 	mutex_lock(&adev->grbm_idx_mutex);
 	for (idx = 0; idx < 2; ++idx) {
 		if (adev->vce.harvest_config & (1 << idx))
 			continue;
 		WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(idx));
+		/* Program instance 0 reg space for two instances or instance 0 case
+		program instance 1 reg space for only instance 1 available case */
+		if (idx != 1 || adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0) {
+			ring = &adev->vce.ring[0];
+			WREG32(mmVCE_RB_RPTR, lower_32_bits(ring->wptr));
+			WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
+			WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr);
+			WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
+			WREG32(mmVCE_RB_SIZE, ring->ring_size / 4);
+			ring = &adev->vce.ring[1];
+			WREG32(mmVCE_RB_RPTR2, lower_32_bits(ring->wptr));
+			WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));
+			WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr);
+			WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
+			WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4);
+			ring = &adev->vce.ring[2];
+			WREG32(mmVCE_RB_RPTR3, lower_32_bits(ring->wptr));
+			WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr));
+			WREG32(mmVCE_RB_BASE_LO3, ring->gpu_addr);
+			WREG32(mmVCE_RB_BASE_HI3, upper_32_bits(ring->gpu_addr));
+			WREG32(mmVCE_RB_SIZE3, ring->ring_size / 4);
+		}
 		vce_v3_0_mc_resume(adev, idx);
 		WREG32_FIELD(VCE_STATUS, JOB_BUSY, 1);

drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c+10−10

@@ -709,17 +709,17 @@ static int tf_vega10_thermal_disable_alert(struct pp_hwmgr *hwmgr, · 708 unmodified lines
709		709
710	static struct phm_master_table_item	710	static struct phm_master_table_item
711	vega10_thermal_start_thermal_controller_master_list[] = {	711	vega10_thermal_start_thermal_controller_master_list[] = {
712	{NULL, tf_vega10_thermal_initialize},	712	{ .tableFunction = tf_vega10_thermal_initialize },
713	{NULL, tf_vega10_thermal_set_temperature_range},	713	{ .tableFunction = tf_vega10_thermal_set_temperature_range },
714	{NULL, tf_vega10_thermal_enable_alert},	714	{ .tableFunction = tf_vega10_thermal_enable_alert },
715	/* We should restrict performance levels to low before we halt the SMC.	715	/* We should restrict performance levels to low before we halt the SMC.
716	* On the other hand we are still in boot state when we do this	716	* On the other hand we are still in boot state when we do this
717	* so it would be pointless.	717	* so it would be pointless.
718	* If this assumption changes we have to revisit this table.	718	* If this assumption changes we have to revisit this table.
719	*/	719	*/
720	{NULL, tf_vega10_thermal_setup_fan_table},	720	{ .tableFunction = tf_vega10_thermal_setup_fan_table },
721	{NULL, tf_vega10_thermal_start_smc_fan_control},	721	{ .tableFunction = tf_vega10_thermal_start_smc_fan_control },
722	{NULL, NULL}	722	{ }
723	};	723	};
724		724
725	static struct phm_master_table_header	725	static struct phm_master_table_header
@@ -731,10 +731,10 @@ vega10_thermal_start_thermal_controller_master = { · 5 unmodified lines
731		731
732	static struct phm_master_table_item	732	static struct phm_master_table_item
733	vega10_thermal_set_temperature_range_master_list[] = {	733	vega10_thermal_set_temperature_range_master_list[] = {
734	{NULL, tf_vega10_thermal_disable_alert},	734	{ .tableFunction = tf_vega10_thermal_disable_alert },
735	{NULL, tf_vega10_thermal_set_temperature_range},	735	{ .tableFunction = tf_vega10_thermal_set_temperature_range },
736	{NULL, tf_vega10_thermal_enable_alert},	736	{ .tableFunction = tf_vega10_thermal_enable_alert },
737	{NULL, NULL}	737	{ }
738	};	738	};
739		739
740	struct phm_master_table_header	740	struct phm_master_table_header

drivers/gpu/drm/bridge/synopsys/Kconfig+1−0

@@ -1,6 +1,7 @@
1	config DRM_DW_HDMI	1	config DRM_DW_HDMI
2	tristate	2	tristate
3	select DRM_KMS_HELPER	3	select DRM_KMS_HELPER
		4	select REGMAP_MMIO
4		5
5	config DRM_DW_HDMI_AHB_AUDIO	6	config DRM_DW_HDMI_AHB_AUDIO
6	tristate "Synopsys Designware AHB Audio interface"	7	tristate "Synopsys Designware AHB Audio interface"

drivers/gpu/drm/drm_atomic_helper.c+11−0

 		bool has_connectors =
 			!!new_crtc_state->connector_mask;
+		WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
 		if (!drm_mode_equal(&old_crtc_state->mode, &new_crtc_state->mode)) {
 			DRM_DEBUG_ATOMIC("[CRTC:%d:%s] mode changed\n",
 					 crtc->base.id, crtc->name);
 	for_each_oldnew_connector_in_state(state, connector, old_connector_state, new_connector_state, i) {
 		const struct drm_connector_helper_funcs *funcs = connector->helper_private;
+		WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
 		/*
 		 * This only sets crtc->connectors_changed for routing changes,
 		 * drivers must set crtc->connectors_changed themselves when
 	for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
 		const struct drm_plane_helper_funcs *funcs;
+		WARN_ON(!drm_modeset_is_locked(&plane->mutex));
 		funcs = plane->helper_private;
 		drm_atomic_helper_plane_changed(state, old_plane_state, new_plane_state, plane);
 	drm_modeset_acquire_init(&ctx, 0);
 	while (1) {
+		err = drm_modeset_lock_all_ctx(dev, &ctx);
+		if (err)
+			goto out;
 		err = drm_atomic_helper_commit_duplicated_state(state, &ctx);
+out:
 		if (err != -EDEADLK)
 			break;

drivers/gpu/drm/drm_dp_helper.c+83−0

@@ -1208,3 +1208,86 @@ int drm_dp_stop_crc(struct drm_dp_aux *aux) · 1207 unmodified lines
1208	return 0;	1208	return 0;
1209	}	1209	}
1210	EXPORT_SYMBOL(drm_dp_stop_crc);	1210	EXPORT_SYMBOL(drm_dp_stop_crc);
		1211
		1212	struct dpcd_quirk {
		1213	u8 oui[3];
		1214	bool is_branch;
		1215	u32 quirks;
		1216	};
		1217
		1218	#define OUI(first, second, third) { (first), (second), (third) }
		1219
		1220	static const struct dpcd_quirk dpcd_quirk_list[] = {
		1221	/* Analogix 7737 needs reduced M and N at HBR2 link rates */
		1222	{ OUI(0x00, 0x22, 0xb9), true, BIT(DP_DPCD_QUIRK_LIMITED_M_N) },
		1223	};
		1224
		1225	#undef OUI
		1226
		1227	/*
		1228	* Get a bit mask of DPCD quirks for the sink/branch device identified by
		1229	* ident. The quirk data is shared but it's up to the drivers to act on the
		1230	* data.
		1231	*
		1232	* For now, only the OUI (first three bytes) is used, but this may be extended
		1233	* to device identification string and hardware/firmware revisions later.
		1234	*/
		1235	static u32
		1236	drm_dp_get_quirks(const struct drm_dp_dpcd_ident *ident, bool is_branch)
		1237	{
		1238	const struct dpcd_quirk *quirk;
		1239	u32 quirks = 0;
		1240	int i;
		1241
		1242	for (i = 0; i < ARRAY_SIZE(dpcd_quirk_list); i++) {
		1243	quirk = &dpcd_quirk_list[i];
		1244
		1245	if (quirk->is_branch != is_branch)
		1246	continue;
		1247
		1248	if (memcmp(quirk->oui, ident->oui, sizeof(ident->oui)) != 0)
		1249	continue;
		1250
		1251	quirks \|= quirk->quirks;
		1252	}
		1253
		1254	return quirks;
		1255	}
		1256
		1257	/**
		1258	* drm_dp_read_desc - read sink/branch descriptor from DPCD
		1259	* @aux: DisplayPort AUX channel
		1260	* @desc: Device decriptor to fill from DPCD
		1261	* @is_branch: true for branch devices, false for sink devices
		1262	*
		1263	* Read DPCD 0x400 (sink) or 0x500 (branch) into @desc. Also debug log the
		1264	* identification.
		1265	*
		1266	* Returns 0 on success or a negative error code on failure.
		1267	*/
		1268	int drm_dp_read_desc(struct drm_dp_aux aux, struct drm_dp_desc desc,
		1269	bool is_branch)
		1270	{
		1271	struct drm_dp_dpcd_ident *ident = &desc->ident;
		1272	unsigned int offset = is_branch ? DP_BRANCH_OUI : DP_SINK_OUI;
		1273	int ret, dev_id_len;
		1274
		1275	ret = drm_dp_dpcd_read(aux, offset, ident, sizeof(*ident));
		1276	if (ret < 0)
		1277	return ret;
		1278
		1279	desc->quirks = drm_dp_get_quirks(ident, is_branch);
		1280
		1281	dev_id_len = strnlen(ident->device_id, sizeof(ident->device_id));
		1282
		1283	DRM_DEBUG_KMS("DP %s: OUI %phD dev-ID %pE HW-rev %d.%d SW-rev %d.%d quirks 0x%04x\n",
		1284	is_branch ? "branch" : "sink",
		1285	(int)sizeof(ident->oui), ident->oui,
		1286	dev_id_len, ident->device_id,
		1287	ident->hw_rev >> 4, ident->hw_rev & 0xf,
		1288	ident->sw_major_rev, ident->sw_minor_rev,
		1289	desc->quirks);
		1290
		1291	return 0;
		1292	}
		1293	EXPORT_SYMBOL(drm_dp_read_desc);

drivers/gpu/drm/drm_drv.c+6−1

 void drm_unplug_dev(struct drm_device *dev)
 {
 	/* for a USB device */
-	drm_dev_unregister(dev);
+	if (drm_core_check_feature(dev, DRIVER_MODESET))
+		drm_modeset_unregister_all(dev);
+	drm_minor_unregister(dev, DRM_MINOR_PRIMARY);
+	drm_minor_unregister(dev, DRM_MINOR_RENDER);
+	drm_minor_unregister(dev, DRM_MINOR_CONTROL);
 	mutex_lock(&drm_global_mutex);

drivers/gpu/drm/exynos/exynos_drm_drv.c+1−7

 	return ret;
 }
-static void exynos_drm_preclose(struct drm_device *dev,
-					struct drm_file *file)
-{
-	exynos_drm_subdrv_close(dev, file);
-}
 static void exynos_drm_postclose(struct drm_device *dev, struct drm_file *file)
 {
+	exynos_drm_subdrv_close(dev, file);
 	kfree(file->driver_priv);
 	file->driver_priv = NULL;
 }
 	.driver_features	= DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME
 				  | DRIVER_ATOMIC | DRIVER_RENDER,
 	.open			= exynos_drm_open,
-	.preclose		= exynos_drm_preclose,
 	.lastclose		= exynos_drm_lastclose,
 	.postclose		= exynos_drm_postclose,
 	.gem_free_object_unlocked = exynos_drm_gem_free_object,

drivers/gpu/drm/exynos/exynos_drm_drv.h+1−4

  *	drm framework doesn't support multiple irq yet.
  *	we can refer to the crtc to current hardware interrupt occurred through
  *	this pipe value.
- * @enabled: if the crtc is enabled or not
- * @event: vblank event that is currently queued for flip
- * @wait_update: wait all pending planes updates to finish
- * @pending_update: number of pending plane updates in this crtc
  * @ops: pointer to callbacks for exynos drm specific functionality
  * @ctx: A pointer to the crtc's implementation specific context
+ * @pipe_clk: A pointer to the crtc's pipeline clock.
  */
 struct exynos_drm_crtc {
 	struct drm_crtc			base;

drivers/gpu/drm/exynos/exynos_drm_dsi.c+9−17

 {
 	struct device *dev = dsi->dev;
 	struct device_node *node = dev->of_node;
-	struct device_node *ep;
 	int ret;
 	ret = exynos_dsi_of_read_u32(node, "samsung,pll-clock-frequency",
 	if (ret < 0)
 		return ret;
-	ep = of_graph_get_endpoint_by_regs(node, DSI_PORT_OUT, 0);
+	ret = exynos_dsi_of_read_u32(node, "samsung,burst-clock-frequency",
-	if (!ep) {
-		dev_err(dev, "no output port with endpoint specified\n");
-		return -EINVAL;
-	}
-	ret = exynos_dsi_of_read_u32(ep, "samsung,burst-clock-frequency",
 				     &dsi->burst_clk_rate);
 	if (ret < 0)
-		goto end;
+		return ret;
-	ret = exynos_dsi_of_read_u32(ep, "samsung,esc-clock-frequency",
+	ret = exynos_dsi_of_read_u32(node, "samsung,esc-clock-frequency",
 				     &dsi->esc_clk_rate);
 	if (ret < 0)
-		goto end;
+		return ret;
-	of_node_put(ep);
 	dsi->bridge_node = of_graph_get_remote_node(node, DSI_PORT_OUT, 0);
 	if (!dsi->bridge_node)
 		return -EINVAL;
-end:
+	return 0;
-	of_node_put(ep);
-	return ret;
 }
 static int exynos_dsi_bind(struct device *dev, struct device *master,
 static int exynos_dsi_remove(struct platform_device *pdev)
 {
+	struct exynos_dsi *dsi = platform_get_drvdata(pdev);
+	of_node_put(dsi->bridge_node);
 	pm_runtime_disable(&pdev->dev);
 	component_del(&pdev->dev, &exynos_dsi_component_ops);

drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c+1−1

@@ -760,7 +760,7 @@ static int dsi_parse_dt(struct platform_device pdev, struct dw_dsi dsi) · 759 unmodified lines
760	* Get the endpoint node. In our case, dsi has one output port1	760	* Get the endpoint node. In our case, dsi has one output port1
761	* to which the external HDMI bridge is connected.	761	* to which the external HDMI bridge is connected.
762	*/	762	*/
763	ret = drm_of_find_panel_or_bridge(np, 0, 0, NULL, &dsi->bridge);	763	ret = drm_of_find_panel_or_bridge(np, 1, 0, NULL, &dsi->bridge);
764	if (ret)	764	if (ret)
765	return ret;	765	return ret;
766		766

drivers/gpu/drm/i915/gvt/execlist.c+20−10

 	vgpu_vreg(vgpu, ctx_status_ptr_reg) = ctx_status_ptr.dw;
 }
+static void clean_workloads(struct intel_vgpu *vgpu, unsigned long engine_mask)
+{
+	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
+	struct intel_engine_cs *engine;
+	struct intel_vgpu_workload *pos, *n;
+	unsigned int tmp;
+	/* free the unsubmited workloads in the queues. */
+	for_each_engine_masked(engine, dev_priv, engine_mask, tmp) {
+		list_for_each_entry_safe(pos, n,
+			&vgpu->workload_q_head[engine->id], list) {
+			list_del_init(&pos->list);
+			free_workload(pos);
+		}
+	}
+}
 void intel_vgpu_clean_execlist(struct intel_vgpu *vgpu)
 {
+	clean_workloads(vgpu, ALL_ENGINES);
 	kmem_cache_destroy(vgpu->workloads);
 }
 {
 	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
 	struct intel_engine_cs *engine;
-	struct intel_vgpu_workload *pos, *n;
 	unsigned int tmp;
-	for_each_engine_masked(engine, dev_priv, engine_mask, tmp) {
+	clean_workloads(vgpu, engine_mask);
-		/* free the unsubmited workload in the queue */
+	for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
-		list_for_each_entry_safe(pos, n,
-			&vgpu->workload_q_head[engine->id], list) {
-			list_del_init(&pos->list);
-			free_workload(pos);
-		}
 		init_vgpu_execlist(vgpu, engine->id);
-	}
 }

drivers/gpu/drm/i915/gvt/handlers.c+21−9

 		void *p_data, unsigned int bytes)
 {
 	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
-	i915_reg_t reg = {.reg = offset};
+	u32 v = *(u32 *)p_data;
+	if (!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv))
+		return intel_vgpu_default_mmio_write(vgpu,
+				offset, p_data, bytes);
 	switch (offset) {
 	case 0x4ddc:
-		vgpu_vreg(vgpu, offset) = 0x8000003c;
+		/* bypass WaCompressedResourceSamplerPbeMediaNewHashMode */
-		/* WaCompressedResourceSamplerPbeMediaNewHashMode:skl */
+		vgpu_vreg(vgpu, offset) = v & ~(1 << 31);
-		I915_WRITE(reg, vgpu_vreg(vgpu, offset));
 		break;
 	case 0x42080:
-		vgpu_vreg(vgpu, offset) = 0x8000;
+		/* bypass WaCompressedResourceDisplayNewHashMode */
-		/* WaCompressedResourceDisplayNewHashMode:skl */
+		vgpu_vreg(vgpu, offset) = v & ~(1 << 15);
-		I915_WRITE(reg, vgpu_vreg(vgpu, offset));
+		break;
+	case 0xe194:
+		/* bypass WaCompressedResourceSamplerPbeMediaNewHashMode */
+		vgpu_vreg(vgpu, offset) = v & ~(1 << 8);
+		break;
+	case 0x7014:
+		/* bypass WaCompressedResourceSamplerPbeMediaNewHashMode */
+		vgpu_vreg(vgpu, offset) = v & ~(1 << 13);
 		break;
 	default:
 		return -EINVAL;
 	MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
 	MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
 		NULL, NULL);
-	MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
+	MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL,
+		 skl_misc_ctl_write);
 	MMIO_DFH(0x9030, D_ALL, F_CMD_ACCESS, NULL, NULL);
 	MMIO_DFH(0x20a0, D_ALL, F_CMD_ACCESS, NULL, NULL);
 	MMIO_DFH(0x2420, D_ALL, F_CMD_ACCESS, NULL, NULL);
 	MMIO_D(0x6e570, D_BDW_PLUS);
 	MMIO_D(0x65f10, D_BDW_PLUS);
-	MMIO_DFH(0xe194, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
+	MMIO_DFH(0xe194, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL,
+		 skl_misc_ctl_write);
 	MMIO_DFH(0xe188, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
 	MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
 	MMIO_DFH(0x2580, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/i915_drv.c+9−4

 		goto out_fini;
 	pci_set_drvdata(pdev, &dev_priv->drm);
+	/*
+	 * Disable the system suspend direct complete optimization, which can
+	 * leave the device suspended skipping the driver's suspend handlers
+	 * if the device was already runtime suspended. This is needed due to
+	 * the difference in our runtime and system suspend sequence and
+	 * becaue the HDA driver may require us to enable the audio power
+	 * domain during system suspend.
+	 */
+	pdev->dev_flags |= PCI_DEV_FLAGS_NEEDS_RESUME;
 	ret = i915_driver_init_early(dev_priv, ent);
 	if (ret < 0)
 	dev_priv->ipc_enabled = false;
-	/* Everything is in place, we can now relax! */
-	DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n",
-		 driver.name, driver.major, driver.minor, driver.patchlevel,
-		 driver.date, pci_name(pdev), dev_priv->drm.primary->index);
 	if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
 		DRM_INFO("DRM_I915_DEBUG enabled\n");
 	if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))

drivers/gpu/drm/i915/i915_drv.h+12−1

 void intel_link_compute_m_n(int bpp, int nlanes,
 			    int pixel_clock, int link_clock,
-			    struct intel_link_m_n *m_n);
+			    struct intel_link_m_n *m_n,
+			    bool reduce_m_n);
 /* Interface history:
  *
 	return false;
 }
+static inline bool
+intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
+{
+#ifdef CONFIG_INTEL_IOMMU
+	if (IS_BROXTON(dev_priv) && intel_iommu_gfx_mapped)
+		return true;
+#endif
+	return false;
+}
 int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
 				int enable_ppgtt);

drivers/gpu/drm/i915/i915_gem.c+4−0

@@ -3298,6 +3298,10 @@ int i915_gem_wait_for_idle(struct drm_i915_private *i915, unsigned int flags) · 3297 unmodified lines
3298	{	3298	{
3299	int ret;	3299	int ret;
3300		3300
		3301	/* If the device is asleep, we have no requests outstanding */
		3302	if (!READ_ONCE(i915->gt.awake))
		3303	return 0;
		3304
3301	if (flags & I915_WAIT_LOCKED) {	3305	if (flags & I915_WAIT_LOCKED) {
3302	struct i915_gem_timeline *tl;	3306	struct i915_gem_timeline *tl;
3303		3307

drivers/gpu/drm/i915/i915_gem_gtt.c+106−2

@@ -2191,6 +2191,101 @@ static void gen8_ggtt_clear_range(struct i915_address_space *vm, · 2190 unmodified lines
2191	gen8_set_pte(&gtt_base[i], scratch_pte);	2191	gen8_set_pte(&gtt_base[i], scratch_pte);
2192	}	2192	}
2193		2193
		2194	static void bxt_vtd_ggtt_wa(struct i915_address_space *vm)
		2195	{
		2196	struct drm_i915_private *dev_priv = vm->i915;
		2197
		2198	/*
		2199	* Make sure the internal GAM fifo has been cleared of all GTT
		2200	* writes before exiting stop_machine(). This guarantees that
		2201	* any aperture accesses waiting to start in another process
		2202	* cannot back up behind the GTT writes causing a hang.
		2203	* The register can be any arbitrary GAM register.
		2204	*/
		2205	POSTING_READ(GFX_FLSH_CNTL_GEN6);
		2206	}
		2207
		2208	struct insert_page {
		2209	struct i915_address_space *vm;
		2210	dma_addr_t addr;
		2211	u64 offset;
		2212	enum i915_cache_level level;
		2213	};
		2214
		2215	static int bxt_vtd_ggtt_insert_page__cb(void *_arg)
		2216	{
		2217	struct insert_page *arg = _arg;
		2218
		2219	gen8_ggtt_insert_page(arg->vm, arg->addr, arg->offset, arg->level, 0);
		2220	bxt_vtd_ggtt_wa(arg->vm);
		2221
		2222	return 0;
		2223	}
		2224
		2225	static void bxt_vtd_ggtt_insert_page__BKL(struct i915_address_space *vm,
		2226	dma_addr_t addr,
		2227	u64 offset,
		2228	enum i915_cache_level level,
		2229	u32 unused)
		2230	{
		2231	struct insert_page arg = { vm, addr, offset, level };
		2232
		2233	stop_machine(bxt_vtd_ggtt_insert_page__cb, &arg, NULL);
		2234	}
		2235
		2236	struct insert_entries {
		2237	struct i915_address_space *vm;
		2238	struct sg_table *st;
		2239	u64 start;
		2240	enum i915_cache_level level;
		2241	};
		2242
		2243	static int bxt_vtd_ggtt_insert_entries__cb(void *_arg)
		2244	{
		2245	struct insert_entries *arg = _arg;
		2246
		2247	gen8_ggtt_insert_entries(arg->vm, arg->st, arg->start, arg->level, 0);
		2248	bxt_vtd_ggtt_wa(arg->vm);
		2249
		2250	return 0;
		2251	}
		2252
		2253	static void bxt_vtd_ggtt_insert_entries__BKL(struct i915_address_space *vm,
		2254	struct sg_table *st,
		2255	u64 start,
		2256	enum i915_cache_level level,
		2257	u32 unused)
		2258	{
		2259	struct insert_entries arg = { vm, st, start, level };
		2260
		2261	stop_machine(bxt_vtd_ggtt_insert_entries__cb, &arg, NULL);
		2262	}
		2263
		2264	struct clear_range {
		2265	struct i915_address_space *vm;
		2266	u64 start;
		2267	u64 length;
		2268	};
		2269
		2270	static int bxt_vtd_ggtt_clear_range__cb(void *_arg)
		2271	{
		2272	struct clear_range *arg = _arg;
		2273
		2274	gen8_ggtt_clear_range(arg->vm, arg->start, arg->length);
		2275	bxt_vtd_ggtt_wa(arg->vm);
		2276
		2277	return 0;
		2278	}
		2279
		2280	static void bxt_vtd_ggtt_clear_range__BKL(struct i915_address_space *vm,
		2281	u64 start,
		2282	u64 length)
		2283	{
		2284	struct clear_range arg = { vm, start, length };
		2285
		2286	stop_machine(bxt_vtd_ggtt_clear_range__cb, &arg, NULL);
		2287	}
		2288
2194	static void gen6_ggtt_clear_range(struct i915_address_space *vm,	2289	static void gen6_ggtt_clear_range(struct i915_address_space *vm,
2195	u64 start, u64 length)	2290	u64 start, u64 length)
2196	{	2291	{
@@ -2313,7 +2408,7 @@ static int aliasing_gtt_bind_vma(struct i915_vma *vma, · 116 unmodified lines
2313	appgtt->base.allocate_va_range) {	2408	appgtt->base.allocate_va_range) {
2314	ret = appgtt->base.allocate_va_range(&appgtt->base,	2409	ret = appgtt->base.allocate_va_range(&appgtt->base,
2315	vma->node.start,	2410	vma->node.start,
2316	vma->node.size);	2411	vma->size);
2317	if (ret)	2412	if (ret)
2318	goto err_pages;	2413	goto err_pages;
2319	}	2414	}
@@ -2785,6 +2880,14 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt) · 465 unmodified lines
2785		2880
2786	ggtt->base.insert_entries = gen8_ggtt_insert_entries;	2881	ggtt->base.insert_entries = gen8_ggtt_insert_entries;
2787		2882
		2883	/* Serialize GTT updates with aperture access on BXT if VT-d is on. */
		2884	if (intel_ggtt_update_needs_vtd_wa(dev_priv)) {
		2885	ggtt->base.insert_entries = bxt_vtd_ggtt_insert_entries__BKL;
		2886	ggtt->base.insert_page = bxt_vtd_ggtt_insert_page__BKL;
		2887	if (ggtt->base.clear_range != nop_clear_range)
		2888	ggtt->base.clear_range = bxt_vtd_ggtt_clear_range__BKL;
		2889	}
		2890
2788	ggtt->invalidate = gen6_ggtt_invalidate;	2891	ggtt->invalidate = gen6_ggtt_invalidate;
2789		2892
2790	return ggtt_probe_common(ggtt, size);	2893	return ggtt_probe_common(ggtt, size);
@@ -2997,7 +3100,8 @@ void i915_ggtt_enable_guc(struct drm_i915_private *i915) · 206 unmodified lines
2997		3100
2998	void i915_ggtt_disable_guc(struct drm_i915_private *i915)	3101	void i915_ggtt_disable_guc(struct drm_i915_private *i915)
2999	{	3102	{
3000	i915->ggtt.invalidate = gen6_ggtt_invalidate;	3103	if (i915->ggtt.invalidate == guc_ggtt_invalidate)
		3104	i915->ggtt.invalidate = gen6_ggtt_invalidate;
3001	}	3105	}
3002		3106
3003	void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv)	3107	void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_gem_shrinker.c+0−5

 		return;
 	mutex_unlock(&dev->struct_mutex);
-	/* expedite the RCU grace period to free some request slabs */
-	synchronize_rcu_expedited();
 }
 static bool any_vma_pinned(struct drm_i915_gem_object *obj)
 				I915_SHRINK_ACTIVE);
 	intel_runtime_pm_put(dev_priv);
-	synchronize_rcu(); /* wait for our earlier RCU delayed slab frees */
 	return freed;
 }

drivers/gpu/drm/i915/i915_gem_tiling.c+1−1

@@ -278,7 +278,7 @@ i915_gem_object_set_tiling(struct drm_i915_gem_object *obj, · 277 unmodified lines
278	obj->mm.quirked = false;	278	obj->mm.quirked = false;
279	}	279	}
280	if (!i915_gem_object_is_tiled(obj)) {	280	if (!i915_gem_object_is_tiled(obj)) {
281	GEM_BUG_ON(!obj->mm.quirked);	281	GEM_BUG_ON(obj->mm.quirked);
282	__i915_gem_object_pin_pages(obj);	282	__i915_gem_object_pin_pages(obj);
283	obj->mm.quirked = true;	283	obj->mm.quirked = true;
284	}	284	}

drivers/gpu/drm/i915/i915_irq.c+6−9

 	u32 pipestat_mask;
 	u32 enable_mask;
 	enum pipe pipe;
-	u32 val;
 	pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
 			PIPE_CRC_DONE_INTERRUPT_STATUS;
 	enable_mask = I915_DISPLAY_PORT_INTERRUPT |
 		I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
-		I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
+		I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
+		I915_LPE_PIPE_A_INTERRUPT |
+		I915_LPE_PIPE_B_INTERRUPT;
 	if (IS_CHERRYVIEW(dev_priv))
-		enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
+		enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT |
+			I915_LPE_PIPE_C_INTERRUPT;
 	WARN_ON(dev_priv->irq_mask != ~0);
-	val = (I915_LPE_PIPE_A_INTERRUPT |
-		I915_LPE_PIPE_B_INTERRUPT |
-		I915_LPE_PIPE_C_INTERRUPT);
-	enable_mask |= val;
 	dev_priv->irq_mask = ~enable_mask;
 	GEN5_IRQ_INIT(VLV_, dev_priv->irq_mask, enable_mask);

drivers/gpu/drm/i915/i915_pci.c+1−2

 static const struct intel_device_info intel_ironlake_m_info = {
 	GEN5_FEATURES,
 	.platform = INTEL_IRONLAKE,
-	.is_mobile = 1,
+	.is_mobile = 1, .has_fbc = 1,
 };
 #define GEN6_FEATURES \
 	.has_hw_contexts = 1, \
 	.has_logical_ring_contexts = 1, \
 	.has_guc = 1, \
-	.has_decoupled_mmio = 1, \
 	.has_aliasing_ppgtt = 1, \
 	.has_full_ppgtt = 1, \
 	.has_full_48bit_ppgtt = 1, \

drivers/gpu/drm/i915/i915_pvinfo.h+2−6

 #define VGT_VERSION_MAJOR 1
 #define VGT_VERSION_MINOR 0
-#define INTEL_VGT_IF_VERSION_ENCODE(major, minor) ((major) << 16 | (minor))
-#define INTEL_VGT_IF_VERSION \
-	INTEL_VGT_IF_VERSION_ENCODE(VGT_VERSION_MAJOR, VGT_VERSION_MINOR)
 /*
  * notifications from guest to vgpu device model
  */
 struct vgt_if {
 	u64 magic;		/* VGT_MAGIC */
-	uint16_t version_major;
+	u16 version_major;
-	uint16_t version_minor;
+	u16 version_minor;
 	u32 vgt_id;		/* ID of vGT instance */
 	u32 rsv1[12];		/* pad to offset 0x40 */
 	/*

drivers/gpu/drm/i915/i915_reg.h+1−1

@@ -8280,7 +8280,7 @@ enum { · 8279 unmodified lines
8280		8280
8281	/* MIPI DSI registers */	8281	/* MIPI DSI registers */
8282		8282
8283	#define _MIPI_PORT(port, a, c) ((port) ? c : a) /* ports A and C only */	8283	#define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c) /* ports A and C only */
8284	#define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c))	8284	#define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c))
8285		8285
8286	#define MIPIO_TXESC_CLK_DIV1 _MMIO(0x160004)	8286	#define MIPIO_TXESC_CLK_DIV1 _MMIO(0x160004)

drivers/gpu/drm/i915/i915_vgpu.c+4−6

  */
 void i915_check_vgpu(struct drm_i915_private *dev_priv)
 {
-	uint64_t magic;
+	u64 magic;
-	uint32_t version;
+	u16 version_major;
 	BUILD_BUG_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
 	if (magic != VGT_MAGIC)
 		return;
-	version = INTEL_VGT_IF_VERSION_ENCODE(
+	version_major = __raw_i915_read16(dev_priv, vgtif_reg(version_major));
-		__raw_i915_read16(dev_priv, vgtif_reg(version_major)),
+	if (version_major < VGT_VERSION_MAJOR) {
-		__raw_i915_read16(dev_priv, vgtif_reg(version_minor)));
-	if (version != INTEL_VGT_IF_VERSION) {
 		DRM_INFO("VGT interface version mismatch!\n");
 		return;
 	}

drivers/gpu/drm/i915/intel_display.c+31−14

 static int
 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
-		  unsigned scaler_user, int *scaler_id, unsigned int rotation,
+		  unsigned int scaler_user, int *scaler_id,
 		  int src_w, int src_h, int dst_w, int dst_h)
 {
 	struct intel_crtc_scaler_state *scaler_state =
 		to_intel_crtc(crtc_state->base.crtc);
 	int need_scaling;
-	need_scaling = drm_rotation_90_or_270(rotation) ?
+	/*
-		(src_h != dst_w || src_w != dst_h):
+	 * Src coordinates are already rotated by 270 degrees for
-		(src_w != dst_w || src_h != dst_h);
+	 * the 90/270 degree plane rotation cases (to match the
+	 * GTT mapping), hence no need to account for rotation here.
+	 */
+	need_scaling = src_w != dst_w || src_h != dst_h;
 	/*
 	 * if plane is being disabled or scaler is no more required or force detach
 	const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
 	return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
-		&state->scaler_state.scaler_id, DRM_ROTATE_0,
+		&state->scaler_state.scaler_id,
 		state->pipe_src_w, state->pipe_src_h,
 		adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
 }
 	ret = skl_update_scaler(crtc_state, force_detach,
 				drm_plane_index(&intel_plane->base),
 				&plane_state->scaler_id,
-				plane_state->base.rotation,
 				drm_rect_width(&plane_state->base.src) >> 16,
 				drm_rect_height(&plane_state->base.src) >> 16,
 				drm_rect_width(&plane_state->base.dst),
 	pipe_config->fdi_lanes = lane;
 	intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
-			       link_bw, &pipe_config->fdi_m_n);
+			       link_bw, &pipe_config->fdi_m_n, false);
 	ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
 	if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
 }
 static void compute_m_n(unsigned int m, unsigned int n,
-			uint32_t *ret_m, uint32_t *ret_n)
+			uint32_t *ret_m, uint32_t *ret_n,
+			bool reduce_m_n)
 {
 	/*
 	 * Reduce M/N as much as possible without loss in precision. Several DP
 	 * values. The passed in values are more likely to have the least
 	 * significant bits zero than M after rounding below, so do this first.
 	 */
-	while ((m & 1) == 0 && (n & 1) == 0) {
+	if (reduce_m_n) {
-		m >>= 1;
+		while ((m & 1) == 0 && (n & 1) == 0) {
-		n >>= 1;
+			m >>= 1;
+			n >>= 1;
+		}
 	}
 	*ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
 void
 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
 		       int pixel_clock, int link_clock,
-		       struct intel_link_m_n *m_n)
+		       struct intel_link_m_n *m_n,
+		       bool reduce_m_n)
 {
 	m_n->tu = 64;
 	compute_m_n(bits_per_pixel * pixel_clock,
 		    link_clock * nlanes * 8,
-		    &m_n->gmch_m, &m_n->gmch_n);
+		    &m_n->gmch_m, &m_n->gmch_n,
+		    reduce_m_n);
 	compute_m_n(pixel_clock, link_clock,
-		    &m_n->link_m, &m_n->link_n);
+		    &m_n->link_m, &m_n->link_n,
+		    reduce_m_n);
 }
 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
 	 * type. For DP ports it behaves like most other platforms, but on HDMI
 	 * there's an extra 1 line difference. So we need to add two instead of
 	 * one to the value.
+	 *
+	 * On VLV/CHV DSI the scanline counter would appear to increment
+	 * approx. 1/3 of a scanline before start of vblank. Unfortunately
+	 * that means we can't tell whether we're in vblank or not while
+	 * we're on that particular line. We must still set scanline_offset
+	 * to 1 so that the vblank timestamps come out correct when we query
+	 * the scanline counter from within the vblank interrupt handler.
+	 * However if queried just before the start of vblank we'll get an
+	 * answer that's slightly in the future.
 	 */
 	if (IS_GEN2(dev_priv)) {
 		const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;

drivers/gpu/drm/i915/intel_dp.c+10−35

 	DRM_DEBUG_KMS("common rates: %s\n", str);
 }
-bool
-__intel_dp_read_desc(struct intel_dp *intel_dp, struct intel_dp_desc *desc)
-{
-	u32 base = drm_dp_is_branch(intel_dp->dpcd) ? DP_BRANCH_OUI :
-						      DP_SINK_OUI;
-	return drm_dp_dpcd_read(&intel_dp->aux, base, desc, sizeof(*desc)) ==
-	       sizeof(*desc);
-}
-bool intel_dp_read_desc(struct intel_dp *intel_dp)
-{
-	struct intel_dp_desc *desc = &intel_dp->desc;
-	bool oui_sup = intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] &
-		       DP_OUI_SUPPORT;
-	int dev_id_len;
-	if (!__intel_dp_read_desc(intel_dp, desc))
-		return false;
-	dev_id_len = strnlen(desc->device_id, sizeof(desc->device_id));
-	DRM_DEBUG_KMS("DP %s: OUI %*phD%s dev-ID %*pE HW-rev %d.%d SW-rev %d.%d\n",
-		      drm_dp_is_branch(intel_dp->dpcd) ? "branch" : "sink",
-		      (int)sizeof(desc->oui), desc->oui, oui_sup ? "" : "(NS)",
-		      dev_id_len, desc->device_id,
-		      desc->hw_rev >> 4, desc->hw_rev & 0xf,
-		      desc->sw_major_rev, desc->sw_minor_rev);
-	return true;
-}
 static int rate_to_index(int find, const int *rates)
 {
 	int i = 0;
 	int common_rates[DP_MAX_SUPPORTED_RATES] = {};
 	int common_len;
 	uint8_t link_bw, rate_select;
+	bool reduce_m_n = drm_dp_has_quirk(&intel_dp->desc,
+					   DP_DPCD_QUIRK_LIMITED_M_N);
 	common_len = intel_dp_common_rates(intel_dp, common_rates);
 	intel_link_compute_m_n(bpp, lane_count,
 			       adjusted_mode->crtc_clock,
 			       pipe_config->port_clock,
-			       &pipe_config->dp_m_n);
+			       &pipe_config->dp_m_n,
+			       reduce_m_n);
 	if (intel_connector->panel.downclock_mode != NULL &&
 		dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
 			intel_link_compute_m_n(bpp, lane_count,
 				intel_connector->panel.downclock_mode->clock,
 				pipe_config->port_clock,
-				&pipe_config->dp_m2_n2);
+				&pipe_config->dp_m2_n2,
+				reduce_m_n);
 	}
 	/*
 	if (!intel_dp_read_dpcd(intel_dp))
 		return false;
-	intel_dp_read_desc(intel_dp);
+	drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
+			 drm_dp_is_branch(intel_dp->dpcd));
 	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
 		dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
 	intel_dp_print_rates(intel_dp);
-	intel_dp_read_desc(intel_dp);
+	drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
+			 drm_dp_is_branch(intel_dp->dpcd));
 	intel_dp_configure_mst(intel_dp);

drivers/gpu/drm/i915/intel_dp_mst.c+4−1

 	int lane_count, slots;
 	const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
 	int mst_pbn;
+	bool reduce_m_n = drm_dp_has_quirk(&intel_dp->desc,
+					   DP_DPCD_QUIRK_LIMITED_M_N);
 	pipe_config->has_pch_encoder = false;
 	bpp = 24;
 	intel_link_compute_m_n(bpp, lane_count,
 			       adjusted_mode->crtc_clock,
 			       pipe_config->port_clock,
-			       &pipe_config->dp_m_n);
+			       &pipe_config->dp_m_n,
+			       reduce_m_n);
 	pipe_config->dp_m_n.tu = slots;

drivers/gpu/drm/i915/intel_drv.h+1−12

 	M2_N2
 };
-struct intel_dp_desc {
-	u8 oui[3];
-	u8 device_id[6];
-	u8 hw_rev;
-	u8 sw_major_rev;
-	u8 sw_minor_rev;
-} __packed;
 struct intel_dp_compliance_data {
 	unsigned long edid;
 	uint8_t video_pattern;
 	/* Max link BW for the sink as per DPCD registers */
 	int max_sink_link_bw;
 	/* sink or branch descriptor */
-	struct intel_dp_desc desc;
+	struct drm_dp_desc desc;
 	struct drm_dp_aux aux;
 	enum intel_display_power_domain aux_power_domain;
 	uint8_t train_set[4];
 }
 bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
-bool __intel_dp_read_desc(struct intel_dp *intel_dp,
-			  struct intel_dp_desc *desc);
-bool intel_dp_read_desc(struct intel_dp *intel_dp);
 int intel_dp_link_required(int pixel_clock, int bpp);
 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,

drivers/gpu/drm/i915/intel_engine_cs.c+17−3

 	return 0;
 }
+static bool ring_is_idle(struct intel_engine_cs *engine)
+{
+	struct drm_i915_private *dev_priv = engine->i915;
+	bool idle = true;
+	intel_runtime_pm_get(dev_priv);
+	/* No bit for gen2, so assume the CS parser is idle */
+	if (INTEL_GEN(dev_priv) > 2 && !(I915_READ_MODE(engine) & MODE_IDLE))
+		idle = false;
+	intel_runtime_pm_put(dev_priv);
+	return idle;
+}
 /**
  * intel_engine_is_idle() - Report if the engine has finished process all work
  * @engine: the intel_engine_cs
  */
 bool intel_engine_is_idle(struct intel_engine_cs *engine)
 {
-	struct drm_i915_private *dev_priv = engine->i915;
 	/* Any inflight/incomplete requests? */
 	if (!i915_seqno_passed(intel_engine_get_seqno(engine),
 			       intel_engine_last_submit(engine)))
 		return false;
 	/* Ring stopped? */
-	if (INTEL_GEN(dev_priv) > 2 && !(I915_READ_MODE(engine) & MODE_IDLE))
+	if (!ring_is_idle(engine))
 		return false;
 	return true;

drivers/gpu/drm/i915/intel_fbc.c+7−12

 static void intel_fbc_get_plane_source_size(struct intel_fbc_state_cache *cache,
 					    int *width, int *height)
 {
-	int w, h;
-	if (drm_rotation_90_or_270(cache->plane.rotation)) {
-		w = cache->plane.src_h;
-		h = cache->plane.src_w;
-	} else {
-		w = cache->plane.src_w;
-		h = cache->plane.src_h;
-	}
 	if (width)
-		*width = w;
+		*width = cache->plane.src_w;
 	if (height)
-		*height = h;
+		*height = cache->plane.src_h;
 }
 static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv,
 		cache->crtc.hsw_bdw_pixel_rate = crtc_state->pixel_rate;
 	cache->plane.rotation = plane_state->base.rotation;
+	/*
+	 * Src coordinates are already rotated by 270 degrees for
+	 * the 90/270 degree plane rotation cases (to match the
+	 * GTT mapping), hence no need to account for rotation here.
+	 */
 	cache->plane.src_w = drm_rect_width(&plane_state->base.src) >> 16;
 	cache->plane.src_h = drm_rect_height(&plane_state->base.src) >> 16;
 	cache->plane.visible = plane_state->base.visible;

drivers/gpu/drm/i915/intel_lpe_audio.c+0−36

@@ -149,44 +149,10 @@ static void lpe_audio_platdev_destroy(struct drm_i915_private *dev_priv) · 148 unmodified lines
149		149
150	static void lpe_audio_irq_unmask(struct irq_data *d)	150	static void lpe_audio_irq_unmask(struct irq_data *d)
151	{	151	{
152	struct drm_i915_private *dev_priv = d->chip_data;
153	unsigned long irqflags;
154	u32 val = (I915_LPE_PIPE_A_INTERRUPT \|
155	I915_LPE_PIPE_B_INTERRUPT);
156
157	if (IS_CHERRYVIEW(dev_priv))
158	val \|= I915_LPE_PIPE_C_INTERRUPT;
159
160	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
161
162	dev_priv->irq_mask &= ~val;
163	I915_WRITE(VLV_IIR, val);
164	I915_WRITE(VLV_IIR, val);
165	I915_WRITE(VLV_IMR, dev_priv->irq_mask);
166	POSTING_READ(VLV_IMR);
167
168	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
169	}	152	}
170		153
171	static void lpe_audio_irq_mask(struct irq_data *d)	154	static void lpe_audio_irq_mask(struct irq_data *d)
172	{	155	{
173	struct drm_i915_private *dev_priv = d->chip_data;
174	unsigned long irqflags;
175	u32 val = (I915_LPE_PIPE_A_INTERRUPT \|
176	I915_LPE_PIPE_B_INTERRUPT);
177
178	if (IS_CHERRYVIEW(dev_priv))
179	val \|= I915_LPE_PIPE_C_INTERRUPT;
180
181	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
182
183	dev_priv->irq_mask \|= val;
184	I915_WRITE(VLV_IMR, dev_priv->irq_mask);
185	I915_WRITE(VLV_IIR, val);
186	I915_WRITE(VLV_IIR, val);
187	POSTING_READ(VLV_IIR);
188
189	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
190	}	156	}
191		157
192	static struct irq_chip lpe_audio_irqchip = {	158	static struct irq_chip lpe_audio_irqchip = {
@@ -330,8 +296,6 @@ void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv) · 137 unmodified lines
330		296
331	desc = irq_to_desc(dev_priv->lpe_audio.irq);	297	desc = irq_to_desc(dev_priv->lpe_audio.irq);
332		298
333	lpe_audio_irq_mask(&desc->irq_data);
334
335	lpe_audio_platdev_destroy(dev_priv);	299	lpe_audio_platdev_destroy(dev_priv);
336		300
337	irq_free_desc(dev_priv->lpe_audio.irq);	301	irq_free_desc(dev_priv->lpe_audio.irq);

drivers/gpu/drm/i915/intel_lrc.c+1−1

@@ -1989,7 +1989,7 @@ static int execlists_context_deferred_alloc(struct i915_gem_context *ctx, · 1988 unmodified lines
1989		1989
1990	ce->ring = ring;	1990	ce->ring = ring;
1991	ce->state = vma;	1991	ce->state = vma;
1992	ce->initialised = engine->init_context == NULL;	1992	ce->initialised \|= engine->init_context == NULL;
1993		1993
1994	return 0;	1994	return 0;
1995		1995

drivers/gpu/drm/i915/intel_lspcon.c+1−1

@@ -240,7 +240,7 @@ bool lspcon_init(struct intel_digital_port *intel_dig_port) · 239 unmodified lines
240	return false;	240	return false;
241	}	241	}
242		242
243	intel_dp_read_desc(dp);	243	drm_dp_read_desc(&dp->aux, &dp->desc, drm_dp_is_branch(dp->dpcd));
244		244
245	DRM_DEBUG_KMS("Success: LSPCON init\n");	245	DRM_DEBUG_KMS("Success: LSPCON init\n");
246	return true;	246	return true;

drivers/gpu/drm/i915/intel_pm.c+33−12

 	/* n.b., src is 16.16 fixed point, dst is whole integer */
 	if (plane->id == PLANE_CURSOR) {
+		/*
+		 * Cursors only support 0/180 degree rotation,
+		 * hence no need to account for rotation here.
+		 */
 		src_w = pstate->base.src_w;
 		src_h = pstate->base.src_h;
 		dst_w = pstate->base.crtc_w;
 		dst_h = pstate->base.crtc_h;
 	} else {
+		/*
+		 * Src coordinates are already rotated by 270 degrees for
+		 * the 90/270 degree plane rotation cases (to match the
+		 * GTT mapping), hence no need to account for rotation here.
+		 */
 		src_w = drm_rect_width(&pstate->base.src);
 		src_h = drm_rect_height(&pstate->base.src);
 		dst_w = drm_rect_width(&pstate->base.dst);
 		dst_h = drm_rect_height(&pstate->base.dst);
 	}
-	if (drm_rotation_90_or_270(pstate->base.rotation))
-		swap(dst_w, dst_h);
 	downscale_h = max(src_h / dst_h, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
 	downscale_w = max(src_w / dst_w, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
 	if (y && format != DRM_FORMAT_NV12)
 		return 0;
+	/*
+	 * Src coordinates are already rotated by 270 degrees for
+	 * the 90/270 degree plane rotation cases (to match the
+	 * GTT mapping), hence no need to account for rotation here.
+	 */
 	width = drm_rect_width(&intel_pstate->base.src) >> 16;
 	height = drm_rect_height(&intel_pstate->base.src) >> 16;
-	if (drm_rotation_90_or_270(pstate->rotation))
-		swap(width, height);
 	/* for planar format */
 	if (format == DRM_FORMAT_NV12) {
 		if (y)  /* y-plane data rate */
 	    fb->modifier != I915_FORMAT_MOD_Yf_TILED)
 		return 8;
+	/*
+	 * Src coordinates are already rotated by 270 degrees for
+	 * the 90/270 degree plane rotation cases (to match the
+	 * GTT mapping), hence no need to account for rotation here.
+	 */
 	src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
 	src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
-	if (drm_rotation_90_or_270(pstate->rotation))
-		swap(src_w, src_h);
 	/* Halve UV plane width and height for NV12 */
 	if (fb->format->format == DRM_FORMAT_NV12 && !y) {
 		src_w /= 2;
 		width = intel_pstate->base.crtc_w;
 		height = intel_pstate->base.crtc_h;
 	} else {
+		/*
+		 * Src coordinates are already rotated by 270 degrees for
+		 * the 90/270 degree plane rotation cases (to match the
+		 * GTT mapping), hence no need to account for rotation here.
+		 */
 		width = drm_rect_width(&intel_pstate->base.src) >> 16;
 		height = drm_rect_height(&intel_pstate->base.src) >> 16;
 	}
-	if (drm_rotation_90_or_270(pstate->rotation))
-		swap(width, height);
 	cpp = fb->format->cpp[0];
 	plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
 	struct drm_crtc_state *cstate;
 	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
 	struct skl_wm_values *results = &intel_state->wm_results;
+	struct drm_device *dev = state->dev;
 	struct skl_pipe_wm *pipe_wm;
 	bool changed = false;
 	int ret, i;
+	/*
+	 * When we distrust bios wm we always need to recompute to set the
+	 * expected DDB allocations for each CRTC.
+	 */
+	if (to_i915(dev)->wm.distrust_bios_wm)
+		changed = true;
 	/*
 	 * If this transaction isn't actually touching any CRTC's, don't
 	 * bother with watermark calculation.  Note that if we pass this
 	 */
 	for_each_new_crtc_in_state(state, crtc, cstate, i)
 		changed = true;
 	if (!changed)
 		return 0;

drivers/gpu/drm/i915/intel_psr.c+3−2

 	}
 	/* PSR2 is restricted to work with panel resolutions upto 3200x2000 */
-	if (intel_crtc->config->pipe_src_w > 3200 ||
+	if (dev_priv->psr.psr2_support &&
-				intel_crtc->config->pipe_src_h > 2000) {
+	    (intel_crtc->config->pipe_src_w > 3200 ||
+	     intel_crtc->config->pipe_src_h > 2000)) {
 		dev_priv->psr.psr2_support = false;
 		return false;
 	}

drivers/gpu/drm/i915/intel_sprite.c+21−0

@@ -83,10 +83,13 @@ int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode, · 82 unmodified lines
83	*/	83	*/
84	void intel_pipe_update_start(struct intel_crtc *crtc)	84	void intel_pipe_update_start(struct intel_crtc *crtc)
85	{	85	{
		86	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
86	const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;	87	const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
87	long timeout = msecs_to_jiffies_timeout(1);	88	long timeout = msecs_to_jiffies_timeout(1);
88	int scanline, min, max, vblank_start;	89	int scanline, min, max, vblank_start;
89	wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);	90	wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
		91	bool need_vlv_dsi_wa = (IS_VALLEYVIEW(dev_priv) \|\| IS_CHERRYVIEW(dev_priv)) &&
		92	intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI);
90	DEFINE_WAIT(wait);	93	DEFINE_WAIT(wait);
91		94
92	vblank_start = adjusted_mode->crtc_vblank_start;	95	vblank_start = adjusted_mode->crtc_vblank_start;
@@ -139,6 +142,24 @@ void intel_pipe_update_start(struct intel_crtc *crtc) · 46 unmodified lines
139		142
140	drm_crtc_vblank_put(&crtc->base);	143	drm_crtc_vblank_put(&crtc->base);
141		144
		145	/*
		146	* On VLV/CHV DSI the scanline counter would appear to
		147	* increment approx. 1/3 of a scanline before start of vblank.
		148	* The registers still get latched at start of vblank however.
		149	* This means we must not write any registers on the first
		150	* line of vblank (since not the whole line is actually in
		151	* vblank). And unfortunately we can't use the interrupt to
		152	* wait here since it will fire too soon. We could use the
		153	* frame start interrupt instead since it will fire after the
		154	* critical scanline, but that would require more changes
		155	* in the interrupt code. So for now we'll just do the nasty
		156	* thing and poll for the bad scanline to pass us by.
		157	*
		158	* FIXME figure out if BXT+ DSI suffers from this as well
		159	*/
		160	while (need_vlv_dsi_wa && scanline == vblank_start)
		161	scanline = intel_get_crtc_scanline(crtc);
		162
142	crtc->debug.scanline_start = scanline;	163	crtc->debug.scanline_start = scanline;
143	crtc->debug.start_vbl_time = ktime_get();	164	crtc->debug.start_vbl_time = ktime_get();
144	crtc->debug.start_vbl_count = intel_crtc_get_vblank_counter(crtc);	165	crtc->debug.start_vbl_count = intel_crtc_get_vblank_counter(crtc);

drivers/gpu/drm/i915/intel_uc.h+0−2

  *                available in the work queue (note, the queue is shared,
  *                not per-engine). It is OK for this to be nonzero, but
  *                it should not be huge!
- *   q_fail: failed to enqueue a work item. This should never happen,
- *           because we check for space beforehand.
  *   b_fail: failed to ring the doorbell. This should never happen, unless
  *           somehow the hardware misbehaves, or maybe if the GuC firmware
  *           crashes? We probably need to reset the GPU to recover.

drivers/gpu/drm/i915/selftests/i915_gem_context.c+5−3

 static int igt_ctx_exec(void *arg)
 {
 	struct drm_i915_private *i915 = arg;
-	struct drm_i915_gem_object *obj;
+	struct drm_i915_gem_object *obj = NULL;
 	struct drm_file *file;
 	IGT_TIMEOUT(end_time);
 	LIST_HEAD(objects);
 		}
 		for_each_engine(engine, i915, id) {
-			if (dw == 0) {
+			if (!obj) {
 				obj = create_test_object(ctx, file, &objects);
 				if (IS_ERR(obj)) {
 					err = PTR_ERR(obj);
 				goto out_unlock;
 			}
-			if (++dw == max_dwords(obj))
+			if (++dw == max_dwords(obj)) {
+				obj = NULL;
 				dw = 0;
+			}
 			ndwords++;
 		}
 		ncontexts++;

drivers/gpu/drm/imx/imx-ldb.c+1−1

@@ -673,7 +673,7 @@ static int imx_ldb_bind(struct device dev, struct device master, void *data) · 672 unmodified lines
673	ret = drm_of_find_panel_or_bridge(child,	673	ret = drm_of_find_panel_or_bridge(child,
674	imx_ldb->lvds_mux ? 4 : 2, 0,	674	imx_ldb->lvds_mux ? 4 : 2, 0,
675	&channel->panel, &channel->bridge);	675	&channel->panel, &channel->bridge);
676	if (ret)	676	if (ret && ret != -ENODEV)
677	return ret;	677	return ret;
678		678
679	/* panel ddc only if there is no bridge */	679	/* panel ddc only if there is no bridge */

drivers/gpu/drm/mediatek/mtk_dsi.c+6−9

@@ -19,6 +19,7 @@ · 18 unmodified lines
19	#include <drm/drm_of.h>	19	#include <drm/drm_of.h>
20	#include <linux/clk.h>	20	#include <linux/clk.h>
21	#include <linux/component.h>	21	#include <linux/component.h>
		22	#include <linux/iopoll.h>
22	#include <linux/irq.h>	23	#include <linux/irq.h>
23	#include <linux/of.h>	24	#include <linux/of.h>
24	#include <linux/of_platform.h>	25	#include <linux/of_platform.h>
@@ -900,16 +901,12 @@ static int mtk_dsi_host_detach(struct mipi_dsi_host *host, · 875 unmodified lines
900		901
901	static void mtk_dsi_wait_for_idle(struct mtk_dsi *dsi)	902	static void mtk_dsi_wait_for_idle(struct mtk_dsi *dsi)
902	{	903	{
903	u32 timeout_ms = 500000; /* total 1s ~ 2s timeout */	904	int ret;
904		905	u32 val;
905	while (timeout_ms--) {
906	if (!(readl(dsi->regs + DSI_INTSTA) & DSI_BUSY))
907	break;
908
909	usleep_range(2, 4);
910	}
911		906
912	if (timeout_ms == 0) {	907	ret = readl_poll_timeout(dsi->regs + DSI_INTSTA, val, !(val & DSI_BUSY),
		908	4, 2000000);
		909	if (ret) {
913	DRM_WARN("polling dsi wait not busy timeout!\n");	910	DRM_WARN("polling dsi wait not busy timeout!\n");
914		911
915	mtk_dsi_enable(dsi);	912	mtk_dsi_enable(dsi);

drivers/gpu/drm/mediatek/mtk_hdmi.c+1−1

@@ -1062,7 +1062,7 @@ static int mtk_hdmi_setup_vendor_specific_infoframe(struct mtk_hdmi *hdmi, · 1061 unmodified lines
1062	}	1062	}
1063		1063
1064	err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));	1064	err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
1065	if (err) {	1065	if (err < 0) {
1066	dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n",	1066	dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n",
1067	err);	1067	err);
1068	return err;	1068	return err;

drivers/gpu/drm/meson/meson_drv.c+15−5

 	.max_register   = 0x1000,
 };
-static int meson_drv_bind(struct device *dev)
+static int meson_drv_bind_master(struct device *dev, bool has_components)
 {
 	struct platform_device *pdev = to_platform_device(dev);
 	struct meson_drm *priv;
 	if (ret)
 		goto free_drm;
-	ret = component_bind_all(drm->dev, drm);
+	if (has_components) {
-	if (ret) {
+		ret = component_bind_all(drm->dev, drm);
-		dev_err(drm->dev, "Couldn't bind all components\n");
+		if (ret) {
-		goto free_drm;
+			dev_err(drm->dev, "Couldn't bind all components\n");
+			goto free_drm;
+		}
 	}
 	ret = meson_plane_create(priv);
 	return ret;
 }
+static int meson_drv_bind(struct device *dev)
+{
+	return meson_drv_bind_master(dev, true);
+}
 static void meson_drv_unbind(struct device *dev)
 {
 	struct drm_device *drm = dev_get_drvdata(dev);
 		count += meson_probe_remote(pdev, &match, np, remote);
 	}
+	if (count && !match)
+		return meson_drv_bind_master(&pdev->dev, false);
 	/* If some endpoints were found, initialize the nodes */
 	if (count) {
 		dev_info(&pdev->dev, "Queued %d outputs on vpu\n", count);

drivers/gpu/drm/mgag200/mgag200_mode.c+8−1

 	if (IS_G200_SE(mdev)) {
-		if (mdev->unique_rev_id >= 0x02) {
+		if  (mdev->unique_rev_id >= 0x04) {
+			WREG8(MGAREG_CRTCEXT_INDEX, 0x06);
+			WREG8(MGAREG_CRTCEXT_DATA, 0);
+		} else if (mdev->unique_rev_id >= 0x02) {
 			u8 hi_pri_lvl;
 			u32 bpp;
 			u32 mb;
 			if (mga_vga_calculate_mode_bandwidth(mode, bpp)
 				> (30100 * 1024))
 				return MODE_BANDWIDTH;
+		} else {
+			if (mga_vga_calculate_mode_bandwidth(mode, bpp)
+				> (55000 * 1024))
+				return MODE_BANDWIDTH;
 		}
 	} else if (mdev->type == G200_WB) {
 		if (mode->hdisplay > 1280)

drivers/gpu/drm/msm/Kconfig+1−0

@@ -13,6 +13,7 @@ config DRM_MSM · 12 unmodified lines
13	select QCOM_SCM	13	select QCOM_SCM
14	select SND_SOC_HDMI_CODEC if SND_SOC	14	select SND_SOC_HDMI_CODEC if SND_SOC
15	select SYNC_FILE	15	select SYNC_FILE
		16	select PM_OPP
16	default y	17	default y
17	help	18	help
18	DRM/KMS driver for MSM/snapdragon.	19	DRM/KMS driver for MSM/snapdragon.

drivers/gpu/drm/msm/mdp/mdp5/mdp5_mdss.c+1−1

@@ -116,7 +116,7 @@ static int mdss_hw_irqdomain_map(struct irq_domain *d, unsigned int irq, · 115 unmodified lines
116	return 0;	116	return 0;
117	}	117	}
118		118
119	static struct irq_domain_ops mdss_hw_irqdomain_ops = {	119	static const struct irq_domain_ops mdss_hw_irqdomain_ops = {
120	.map = mdss_hw_irqdomain_map,	120	.map = mdss_hw_irqdomain_map,
121	.xlate = irq_domain_xlate_onecell,	121	.xlate = irq_domain_xlate_onecell,
122	};	122	};

drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c+7−2

 	mdp5_state = kmemdup(to_mdp5_plane_state(plane->state),
 			sizeof(*mdp5_state), GFP_KERNEL);
+	if (!mdp5_state)
+		return NULL;
-	if (mdp5_state && mdp5_state->base.fb)
+	__drm_atomic_helper_plane_duplicate_state(plane, &mdp5_state->base);
-		drm_framebuffer_reference(mdp5_state->base.fb);
 	return &mdp5_state->base;
 }
 			mdp5_pipe_release(state->state, old_hwpipe);
 			mdp5_pipe_release(state->state, old_right_hwpipe);
 		}
+	} else {
+		mdp5_pipe_release(state->state, mdp5_state->hwpipe);
+		mdp5_pipe_release(state->state, mdp5_state->r_hwpipe);
+		mdp5_state->hwpipe = mdp5_state->r_hwpipe = NULL;
 	}
 	return 0;

drivers/gpu/drm/msm/msm_drv.c+1−0

@@ -830,6 +830,7 @@ static struct drm_driver msm_driver = { · 829 unmodified lines
830	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,	830	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
831	.gem_prime_export = drm_gem_prime_export,	831	.gem_prime_export = drm_gem_prime_export,
832	.gem_prime_import = drm_gem_prime_import,	832	.gem_prime_import = drm_gem_prime_import,
		833	.gem_prime_res_obj = msm_gem_prime_res_obj,
833	.gem_prime_pin = msm_gem_prime_pin,	834	.gem_prime_pin = msm_gem_prime_pin,
834	.gem_prime_unpin = msm_gem_prime_unpin,	835	.gem_prime_unpin = msm_gem_prime_unpin,
835	.gem_prime_get_sg_table = msm_gem_prime_get_sg_table,	836	.gem_prime_get_sg_table = msm_gem_prime_get_sg_table,

drivers/gpu/drm/msm/msm_drv.h+1−0

@@ -224,6 +224,7 @@ struct sg_table msm_gem_prime_get_sg_table(struct drm_gem_object obj); · 223 unmodified lines
224	void msm_gem_prime_vmap(struct drm_gem_object obj);	224	void msm_gem_prime_vmap(struct drm_gem_object obj);
225	void msm_gem_prime_vunmap(struct drm_gem_object obj, void vaddr);	225	void msm_gem_prime_vunmap(struct drm_gem_object obj, void vaddr);
226	int msm_gem_prime_mmap(struct drm_gem_object obj, struct vm_area_struct vma);	226	int msm_gem_prime_mmap(struct drm_gem_object obj, struct vm_area_struct vma);
		227	struct reservation_object msm_gem_prime_res_obj(struct drm_gem_object obj);
227	struct drm_gem_object msm_gem_prime_import_sg_table(struct drm_device dev,	228	struct drm_gem_object msm_gem_prime_import_sg_table(struct drm_device dev,
228	struct dma_buf_attachment attach, struct sg_table sg);	229	struct dma_buf_attachment attach, struct sg_table sg);
229	int msm_gem_prime_pin(struct drm_gem_object *obj);	230	int msm_gem_prime_pin(struct drm_gem_object *obj);

drivers/gpu/drm/msm/msm_fence.c+2−8

 }
 struct msm_fence {
-	struct msm_fence_context *fctx;
 	struct dma_fence base;
+	struct msm_fence_context *fctx;
 };
 static inline struct msm_fence *to_msm_fence(struct dma_fence *fence)
 	return fence_completed(f->fctx, f->base.seqno);
 }
-static void msm_fence_release(struct dma_fence *fence)
-{
-	struct msm_fence *f = to_msm_fence(fence);
-	kfree_rcu(f, base.rcu);
-}
 static const struct dma_fence_ops msm_fence_ops = {
 	.get_driver_name = msm_fence_get_driver_name,
 	.get_timeline_name = msm_fence_get_timeline_name,
 	.enable_signaling = msm_fence_enable_signaling,
 	.signaled = msm_fence_signaled,
 	.wait = dma_fence_default_wait,
-	.release = msm_fence_release,
+	.release = dma_fence_free,
 };
 struct dma_fence *

drivers/gpu/drm/msm/msm_gem.c+6−0

 	struct msm_gem_object *msm_obj;
 	bool use_vram = false;
+	WARN_ON(!mutex_is_locked(&dev->struct_mutex));
 	switch (flags & MSM_BO_CACHE_MASK) {
 	case MSM_BO_UNCACHED:
 	case MSM_BO_CACHED:
 	size = PAGE_ALIGN(dmabuf->size);
+	/* Take mutex so we can modify the inactive list in msm_gem_new_impl */
+	mutex_lock(&dev->struct_mutex);
 	ret = msm_gem_new_impl(dev, size, MSM_BO_WC, dmabuf->resv, &obj);
+	mutex_unlock(&dev->struct_mutex);
 	if (ret)
 		goto fail;

drivers/gpu/drm/msm/msm_gem_prime.c+7−0

@@ -70,3 +70,10 @@ void msm_gem_prime_unpin(struct drm_gem_object *obj) · 69 unmodified lines
70	if (!obj->import_attach)	70	if (!obj->import_attach)
71	msm_gem_put_pages(obj);	71	msm_gem_put_pages(obj);
72	}	72	}
		73
		74	struct reservation_object msm_gem_prime_res_obj(struct drm_gem_object obj)
		75	{
		76	struct msm_gem_object *msm_obj = to_msm_bo(obj);
		77
		78	return msm_obj->resv;
		79	}

drivers/gpu/drm/msm/msm_gem_submit.c+7−7

@@ -410,12 +410,11 @@ int msm_ioctl_gem_submit(struct drm_device dev, void data, · 409 unmodified lines
410	if (!in_fence)	410	if (!in_fence)
411	return -EINVAL;	411	return -EINVAL;
412		412
413	/* TODO if we get an array-fence due to userspace merging multiple	413	/*
414	* fences, we need a way to determine if all the backing fences	414	* Wait if the fence is from a foreign context, or if the fence
415	* are from our own context..	415	* array contains any fence from a foreign context.
416	*/	416	*/
417		417	if (!dma_fence_match_context(in_fence, gpu->fctx->context)) {
418	if (in_fence->context != gpu->fctx->context) {
419	ret = dma_fence_wait(in_fence, true);	418	ret = dma_fence_wait(in_fence, true);
420	if (ret)	419	if (ret)
421	return ret;	420	return ret;
@@ -496,8 +495,9 @@ int msm_ioctl_gem_submit(struct drm_device dev, void data, · 74 unmodified lines
496	goto out;	495	goto out;
497	}	496	}
498		497
499	if ((submit_cmd.size + submit_cmd.submit_offset) >=	498	if (!submit_cmd.size \|\|
500	msm_obj->base.size) {	499	((submit_cmd.size + submit_cmd.submit_offset) >
		500	msm_obj->base.size)) {
501	DRM_ERROR("invalid cmdstream size: %u\n", submit_cmd.size);	501	DRM_ERROR("invalid cmdstream size: %u\n", submit_cmd.size);
502	ret = -EINVAL;	502	ret = -EINVAL;
503	goto out;	503	goto out;

drivers/gpu/drm/msm/msm_gpu.c+2−2

@@ -549,9 +549,9 @@ static int get_clocks(struct platform_device pdev, struct msm_gpu gpu) · 548 unmodified lines
549	gpu->grp_clks[i] = get_clock(dev, name);	549	gpu->grp_clks[i] = get_clock(dev, name);
550		550
551	/* Remember the key clocks that we need to control later */	551	/* Remember the key clocks that we need to control later */
552	if (!strcmp(name, "core"))	552	if (!strcmp(name, "core") \|\| !strcmp(name, "core_clk"))
553	gpu->core_clk = gpu->grp_clks[i];	553	gpu->core_clk = gpu->grp_clks[i];
554	else if (!strcmp(name, "rbbmtimer"))	554	else if (!strcmp(name, "rbbmtimer") \|\| !strcmp(name, "rbbmtimer_clk"))
555	gpu->rbbmtimer_clk = gpu->grp_clks[i];	555	gpu->rbbmtimer_clk = gpu->grp_clks[i];
556		556
557	++i;	557	++i;

drivers/gpu/drm/mxsfb/mxsfb_crtc.c+42−0

@@ -35,6 +35,13 @@ · 34 unmodified lines
35	#include "mxsfb_drv.h"	35	#include "mxsfb_drv.h"
36	#include "mxsfb_regs.h"	36	#include "mxsfb_regs.h"
37		37
		38	#define MXS_SET_ADDR 0x4
		39	#define MXS_CLR_ADDR 0x8
		40	#define MODULE_CLKGATE BIT(30)
		41	#define MODULE_SFTRST BIT(31)
		42	/* 1 second delay should be plenty of time for block reset */
		43	#define RESET_TIMEOUT 1000000
		44
38	static u32 set_hsync_pulse_width(struct mxsfb_drm_private *mxsfb, u32 val)	45	static u32 set_hsync_pulse_width(struct mxsfb_drm_private *mxsfb, u32 val)
39	{	46	{
40	return (val & mxsfb->devdata->hs_wdth_mask) <<	47	return (val & mxsfb->devdata->hs_wdth_mask) <<
@@ -159,6 +166,36 @@ static void mxsfb_disable_controller(struct mxsfb_drm_private *mxsfb) · 118 unmodified lines
159	clk_disable_unprepare(mxsfb->clk_disp_axi);	166	clk_disable_unprepare(mxsfb->clk_disp_axi);
160	}	167	}
161		168
		169	/*
		170	* Clear the bit and poll it cleared. This is usually called with
		171	* a reset address and mask being either SFTRST(bit 31) or CLKGATE
		172	* (bit 30).
		173	*/
		174	static int clear_poll_bit(void __iomem *addr, u32 mask)
		175	{
		176	u32 reg;
		177
		178	writel(mask, addr + MXS_CLR_ADDR);
		179	return readl_poll_timeout(addr, reg, !(reg & mask), 0, RESET_TIMEOUT);
		180	}
		181
		182	static int mxsfb_reset_block(void __iomem *reset_addr)
		183	{
		184	int ret;
		185
		186	ret = clear_poll_bit(reset_addr, MODULE_SFTRST);
		187	if (ret)
		188	return ret;
		189
		190	writel(MODULE_CLKGATE, reset_addr + MXS_CLR_ADDR);
		191
		192	ret = clear_poll_bit(reset_addr, MODULE_SFTRST);
		193	if (ret)
		194	return ret;
		195
		196	return clear_poll_bit(reset_addr, MODULE_CLKGATE);
		197	}
		198
162	static void mxsfb_crtc_mode_set_nofb(struct mxsfb_drm_private *mxsfb)	199	static void mxsfb_crtc_mode_set_nofb(struct mxsfb_drm_private *mxsfb)
163	{	200	{
164	struct drm_display_mode *m = &mxsfb->pipe.crtc.state->adjusted_mode;	201	struct drm_display_mode *m = &mxsfb->pipe.crtc.state->adjusted_mode;
@@ -173,6 +210,11 @@ static void mxsfb_crtc_mode_set_nofb(struct mxsfb_drm_private *mxsfb) · 8 unmodified lines
173	*/	210	*/
174	mxsfb_enable_axi_clk(mxsfb);	211	mxsfb_enable_axi_clk(mxsfb);
175		212
		213	/* Mandatory eLCDIF reset as per the Reference Manual */
		214	err = mxsfb_reset_block(mxsfb->base);
		215	if (err)
		216	return;
		217
176	/* Clear the FIFOs */	218	/* Clear the FIFOs */
177	writel(CTRL1_FIFO_CLEAR, mxsfb->base + LCDC_CTRL1 + REG_SET);	219	writel(CTRL1_FIFO_CLEAR, mxsfb->base + LCDC_CTRL1 + REG_SET);
178		220

drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h+1−0

@@ -4,6 +4,7 @@ · 3 unmodified lines
4		4
5	struct nvkm_alarm {	5	struct nvkm_alarm {
6	struct list_head head;	6	struct list_head head;
		7	struct list_head exec;
7	u64 timestamp;	8	u64 timestamp;
8	void (func)(struct nvkm_alarm );	9	void (func)(struct nvkm_alarm );
9	};	10	};

drivers/gpu/drm/nouveau/nouveau_drm.c+17−21

 module_param_named(modeset, nouveau_modeset, int, 0400);
 MODULE_PARM_DESC(runpm, "disable (0), force enable (1), optimus only default (-1)");
-int nouveau_runtime_pm = -1;
+static int nouveau_runtime_pm = -1;
 module_param_named(runpm, nouveau_runtime_pm, int, 0400);
 static struct drm_driver driver_stub;
 	nouveau_fbcon_init(dev);
 	nouveau_led_init(dev);
-	if (nouveau_runtime_pm != 0) {
+	if (nouveau_pmops_runtime()) {
 		pm_runtime_use_autosuspend(dev->dev);
 		pm_runtime_set_autosuspend_delay(dev->dev, 5000);
 		pm_runtime_set_active(dev->dev);
 {
 	struct nouveau_drm *drm = nouveau_drm(dev);
-	if (nouveau_runtime_pm != 0) {
+	if (nouveau_pmops_runtime()) {
 		pm_runtime_get_sync(dev->dev);
 		pm_runtime_forbid(dev->dev);
 	}
 	return nouveau_do_resume(drm_dev, false);
 }
+bool
+nouveau_pmops_runtime()
+{
+	if (nouveau_runtime_pm == -1)
+		return nouveau_is_optimus() || nouveau_is_v1_dsm();
+	return nouveau_runtime_pm == 1;
+}
 static int
 nouveau_pmops_runtime_suspend(struct device *dev)
 {
 	struct drm_device *drm_dev = pci_get_drvdata(pdev);
 	int ret;
-	if (nouveau_runtime_pm == 0) {
+	if (!nouveau_pmops_runtime()) {
-		pm_runtime_forbid(dev);
-		return -EBUSY;
-	}
-	/* are we optimus enabled? */
-	if (nouveau_runtime_pm == -1 && !nouveau_is_optimus() && !nouveau_is_v1_dsm()) {
-		DRM_DEBUG_DRIVER("failing to power off - not optimus\n");
 		pm_runtime_forbid(dev);
 		return -EBUSY;
 	}
 	struct nvif_device *device = &nouveau_drm(drm_dev)->client.device;
 	int ret;
-	if (nouveau_runtime_pm == 0)
+	if (!nouveau_pmops_runtime()) {
-		return -EINVAL;
+		pm_runtime_forbid(dev);
+		return -EBUSY;
+	}
 	pci_set_power_state(pdev, PCI_D0);
 	pci_restore_state(pdev);
 	struct nouveau_drm *drm = nouveau_drm(drm_dev);
 	struct drm_crtc *crtc;
-	if (nouveau_runtime_pm == 0) {
+	if (!nouveau_pmops_runtime()) {
-		pm_runtime_forbid(dev);
-		return -EBUSY;
-	}
-	/* are we optimus enabled? */
-	if (nouveau_runtime_pm == -1 && !nouveau_is_optimus() && !nouveau_is_v1_dsm()) {
-		DRM_DEBUG_DRIVER("failing to power off - not optimus\n");
 		pm_runtime_forbid(dev);
 		return -EBUSY;
 	}

drivers/gpu/drm/nouveau/nouveau_drv.h+1−2

 #include <nvif/object.h>
 #include <nvif/device.h>
-extern int nouveau_runtime_pm;
 struct nouveau_drm {
 	struct nouveau_cli client;
 	struct drm_device *dev;
 int nouveau_pmops_suspend(struct device *);
 int nouveau_pmops_resume(struct device *);
+bool nouveau_pmops_runtime(void);
 #include <nvkm/core/tegra.h>

drivers/gpu/drm/nouveau/nouveau_vga.c+2−11

 nouveau_vga_init(struct nouveau_drm *drm)
 {
 	struct drm_device *dev = drm->dev;
-	bool runtime = false;
+	bool runtime = nouveau_pmops_runtime();
 	/* only relevant for PCI devices */
 	if (!dev->pdev)
 	if (pci_is_thunderbolt_attached(dev->pdev))
 		return;
-	if (nouveau_runtime_pm == 1)
-		runtime = true;
-	if ((nouveau_runtime_pm == -1) && (nouveau_is_optimus() || nouveau_is_v1_dsm()))
-		runtime = true;
 	vga_switcheroo_register_client(dev->pdev, &nouveau_switcheroo_ops, runtime);
 	if (runtime && nouveau_is_v1_dsm() && !nouveau_is_optimus())
 nouveau_vga_fini(struct nouveau_drm *drm)
 {
 	struct drm_device *dev = drm->dev;
-	bool runtime = false;
+	bool runtime = nouveau_pmops_runtime();
 	vga_client_register(dev->pdev, NULL, NULL, NULL);
 	if (pci_is_thunderbolt_attached(dev->pdev))
 		return;
-	if (nouveau_runtime_pm == 1)
-		runtime = true;
-	if ((nouveau_runtime_pm == -1) && (nouveau_is_optimus() || nouveau_is_v1_dsm()))
-		runtime = true;
 	vga_switcheroo_unregister_client(dev->pdev);
 	if (runtime && nouveau_is_v1_dsm() && !nouveau_is_optimus())
 		vga_switcheroo_fini_domain_pm_ops(drm->dev->dev);

drivers/gpu/drm/nouveau/nv50_display.c+2−1

@@ -2107,7 +2107,8 @@ nv50_head_atomic_check(struct drm_crtc crtc, struct drm_crtc_state state) · 2106 unmodified lines
2107	asyc->set.dither = true;	2107	asyc->set.dither = true;
2108	}	2108	}
2109	} else {	2109	} else {
2110	asyc->set.mask = ~0;	2110	if (asyc)
		2111	asyc->set.mask = ~0;
2111	asyh->set.mask = ~0;	2112	asyh->set.mask = ~0;
2112	}	2113	}
2113		2114

drivers/gpu/drm/nouveau/nvkm/subdev/timer/base.c+4−3

 		/* Move to completed list.  We'll drop the lock before
 		 * executing the callback so it can reschedule itself.
 		 */
-		list_move_tail(&alarm->head, &exec);
+		list_del_init(&alarm->head);
+		list_add(&alarm->exec, &exec);
 	}
 	/* Shut down interrupt if no more pending alarms. */
 	spin_unlock_irqrestore(&tmr->lock, flags);
 	/* Execute completed callbacks. */
-	list_for_each_entry_safe(alarm, atemp, &exec, head) {
+	list_for_each_entry_safe(alarm, atemp, &exec, exec) {
-		list_del_init(&alarm->head);
+		list_del(&alarm->exec);
 		alarm->func(alarm);
 	}
 }

drivers/gpu/drm/radeon/cik.c+5−2

 	u32 tmp, wm_mask;
 	if (radeon_crtc->base.enabled && num_heads && mode) {
-		active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock;
+		active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
-		line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535);
+					    (u32)mode->clock);
+		line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
+					  (u32)mode->clock);
+		line_time = min(line_time, (u32)65535);
 		/* watermark for high clocks */
 		if ((rdev->pm.pm_method == PM_METHOD_DPM) &&

drivers/gpu/drm/radeon/evergreen.c+5−2

 	fixed20_12 a, b, c;
 	if (radeon_crtc->base.enabled && num_heads && mode) {
-		active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock;
+		active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
-		line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535);
+					    (u32)mode->clock);
+		line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
+					  (u32)mode->clock);
+		line_time = min(line_time, (u32)65535);
 		priority_a_cnt = 0;
 		priority_b_cnt = 0;
 		dram_channels = evergreen_get_number_of_dram_channels(rdev);

drivers/gpu/drm/radeon/radeon_uvd.c+1−1

@@ -621,7 +621,7 @@ static int radeon_uvd_cs_reloc(struct radeon_cs_parser *p, · 620 unmodified lines
621	}	621	}
622		622
623	/* TODO: is this still necessary on NI+ ? */	623	/* TODO: is this still necessary on NI+ ? */
624	if ((cmd == 0 \|\| cmd == 1 \|\| cmd == 0x3) &&	624	if ((cmd == 0 \|\| cmd == 0x3) &&
625	(start >> 28) != (p->rdev->uvd.gpu_addr >> 28)) {	625	(start >> 28) != (p->rdev->uvd.gpu_addr >> 28)) {
626	DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",	626	DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
627	start, end);	627	start, end);

drivers/gpu/drm/radeon/si.c+5−2

 	fixed20_12 a, b, c;
 	if (radeon_crtc->base.enabled && num_heads && mode) {
-		active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock;
+		active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
-		line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535);
+					    (u32)mode->clock);
+		line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
+					  (u32)mode->clock);
+		line_time = min(line_time, (u32)65535);
 		priority_a_cnt = 0;
 		priority_b_cnt = 0;

drivers/gpu/drm/rockchip/analogix_dp-rockchip.c+0−12

 				      struct drm_connector_state *conn_state)
 {
 	struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
-	struct rockchip_dp_device *dp = to_dp(encoder);
-	int ret;
 	/*
 	 * The hardware IC designed that VOP must output the RGB10 video
 	s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
 	s->output_type = DRM_MODE_CONNECTOR_eDP;
-	if (dp->data->chip_type == RK3399_EDP) {
-		/*
-		 * For RK3399, VOP Lit must code the out mode to RGB888,
-		 * VOP Big must code the out mode to RGB10.
-		 */
-		ret = drm_of_encoder_active_endpoint_id(dp->dev->of_node,
-							encoder);
-		if (ret > 0)
-			s->output_mode = ROCKCHIP_OUT_MODE_P888;
-	}
 	return 0;
 }

drivers/gpu/drm/rockchip/cdn-dp-core.c+2−7

 {
 	struct cdn_dp_device *dp = encoder_to_dp(encoder);
 	int ret, val;
-	struct rockchip_crtc_state *state;
 	ret = drm_of_encoder_active_endpoint_id(dp->dev->of_node, encoder);
 	if (ret < 0) {
 	DRM_DEV_DEBUG_KMS(dp->dev, "vop %s output to cdn-dp\n",
 			  (ret) ? "LIT" : "BIG");
-	state = to_rockchip_crtc_state(encoder->crtc->state);
+	if (ret)
-	if (ret) {
 		val = DP_SEL_VOP_LIT | (DP_SEL_VOP_LIT << 16);
-		state->output_mode = ROCKCHIP_OUT_MODE_P888;
+	else
-	} else {
 		val = DP_SEL_VOP_LIT << 16;
-		state->output_mode = ROCKCHIP_OUT_MODE_AAAA;
-	}
 	ret = cdn_dp_grf_write(dp, GRF_SOC_CON9, val);
 	if (ret)

drivers/gpu/drm/rockchip/rockchip_drm_vop.c+8−0

 static void vop_crtc_enable(struct drm_crtc *crtc)
 {
 	struct vop *vop = to_vop(crtc);
+	const struct vop_data *vop_data = vop->data;
 	struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
 	struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
 	u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
 		DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n",
 			      s->output_type);
 	}
+	/*
+	 * if vop is not support RGB10 output, need force RGB10 to RGB888.
+	 */
+	if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
+	    !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10))
+		s->output_mode = ROCKCHIP_OUT_MODE_P888;
 	VOP_CTRL_SET(vop, out_mode, s->output_mode);
 	VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);

drivers/gpu/drm/rockchip/rockchip_drm_vop.h+3−0

@@ -142,6 +142,9 @@ struct vop_data { · 141 unmodified lines
142	const struct vop_intr *intr;	142	const struct vop_intr *intr;
143	const struct vop_win_data *win;	143	const struct vop_win_data *win;
144	unsigned int win_size;	144	unsigned int win_size;
		145
		146	#define VOP_FEATURE_OUTPUT_RGB10 BIT(0)
		147	u64 feature;
145	};	148	};
146		149
147	/* interrupt define */	150	/* interrupt define */

drivers/gpu/drm/rockchip/rockchip_vop_reg.c+2−0

 static const struct vop_data rk3288_vop = {
 	.init_table = rk3288_init_reg_table,
 	.table_size = ARRAY_SIZE(rk3288_init_reg_table),
+	.feature = VOP_FEATURE_OUTPUT_RGB10,
 	.intr = &rk3288_vop_intr,
 	.ctrl = &rk3288_ctrl_data,
 	.win = rk3288_vop_win_data,
 static const struct vop_data rk3399_vop_big = {
 	.init_table = rk3399_init_reg_table,
 	.table_size = ARRAY_SIZE(rk3399_init_reg_table),
+	.feature = VOP_FEATURE_OUTPUT_RGB10,
 	.intr = &rk3399_vop_intr,
 	.ctrl = &rk3399_ctrl_data,
 	/*

drivers/gpu/drm/tegra/drm.c+5−17

 #ifdef CONFIG_DRM_TEGRA_STAGING
-static struct tegra_drm_context *
-tegra_drm_file_get_context(struct tegra_drm_file *file, u32 id)
-{
-	struct tegra_drm_context *context;
-	mutex_lock(&file->lock);
-	context = idr_find(&file->contexts, id);
-	mutex_unlock(&file->lock);
-	return context;
-}
 static int tegra_gem_create(struct drm_device *drm, void *data,
 			    struct drm_file *file)
 {
 	if (err < 0)
 		return err;
-	err = idr_alloc(&fpriv->contexts, context, 0, 0, GFP_KERNEL);
+	err = idr_alloc(&fpriv->contexts, context, 1, 0, GFP_KERNEL);
 	if (err < 0) {
 		client->ops->close_channel(context);
 		return err;
 	mutex_lock(&fpriv->lock);
-	context = tegra_drm_file_get_context(fpriv, args->context);
+	context = idr_find(&fpriv->contexts, args->context);
 	if (!context) {
 		err = -EINVAL;
 		goto unlock;
 	mutex_lock(&fpriv->lock);
-	context = tegra_drm_file_get_context(fpriv, args->context);
+	context = idr_find(&fpriv->contexts, args->context);
 	if (!context) {
 		err = -ENODEV;
 		goto unlock;
 	mutex_lock(&fpriv->lock);
-	context = tegra_drm_file_get_context(fpriv, args->context);
+	context = idr_find(&fpriv->contexts, args->context);
 	if (!context) {
 		err = -ENODEV;
 		goto unlock;
 	mutex_lock(&fpriv->lock);
-	context = tegra_drm_file_get_context(fpriv, args->context);
+	context = idr_find(&fpriv->contexts, args->context);
 	if (!context) {
 		err = -ENODEV;
 		goto unlock;

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h+2−2

@@ -41,9 +41,9 @@ · 40 unmodified lines
41	#include <drm/ttm/ttm_module.h>	41	#include <drm/ttm/ttm_module.h>
42	#include "vmwgfx_fence.h"	42	#include "vmwgfx_fence.h"
43		43
44	#define VMWGFX_DRIVER_DATE "20170221"	44	#define VMWGFX_DRIVER_DATE "20170607"
45	#define VMWGFX_DRIVER_MAJOR 2	45	#define VMWGFX_DRIVER_MAJOR 2
46	#define VMWGFX_DRIVER_MINOR 12	46	#define VMWGFX_DRIVER_MINOR 13
47	#define VMWGFX_DRIVER_PATCHLEVEL 0	47	#define VMWGFX_DRIVER_PATCHLEVEL 0
48	#define VMWGFX_FILE_PAGE_OFFSET 0x00100000	48	#define VMWGFX_FILE_PAGE_OFFSET 0x00100000
49	#define VMWGFX_FIFO_STATIC_SIZE (1024*1024)	49	#define VMWGFX_FIFO_STATIC_SIZE (1024*1024)

drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c+2−0

 				return fifo_state->static_buffer;
 			else {
 				fifo_state->dynamic_buffer = vmalloc(bytes);
+				if (!fifo_state->dynamic_buffer)
+					goto out_err;
 				return fifo_state->dynamic_buffer;
 			}
 		}

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c+1−114

@@ -274,108 +274,6 @@ void vmw_kms_cursor_post_execbuf(struct vmw_private *dev_priv) · 273 unmodified lines
274	}	274	}
275		275
276		276
277
278	/**
279	* vmw_du_cursor_plane_update() - Update cursor image and location
280	*
281	* @plane: plane object to update
282	* @crtc: owning CRTC of @plane
283	* @fb: framebuffer to flip onto plane
284	* @crtc_x: x offset of plane on crtc
285	* @crtc_y: y offset of plane on crtc
286	* @crtc_w: width of plane rectangle on crtc
287	* @crtc_h: height of plane rectangle on crtc
288	* @src_x: Not used
289	* @src_y: Not used
290	* @src_w: Not used
291	* @src_h: Not used
292	*
293	*
294	* RETURNS:
295	* Zero on success, error code on failure
296	*/
297	int vmw_du_cursor_plane_update(struct drm_plane *plane,
298	struct drm_crtc *crtc,
299	struct drm_framebuffer *fb,
300	int crtc_x, int crtc_y,
301	unsigned int crtc_w,
302	unsigned int crtc_h,
303	uint32_t src_x, uint32_t src_y,
304	uint32_t src_w, uint32_t src_h)
305	{
306	struct vmw_private *dev_priv = vmw_priv(crtc->dev);
307	struct vmw_display_unit *du = vmw_crtc_to_du(crtc);
308	struct vmw_surface *surface = NULL;
309	struct vmw_dma_buffer *dmabuf = NULL;
310	s32 hotspot_x, hotspot_y;
311	int ret;
312
313	hotspot_x = du->hotspot_x + fb->hot_x;
314	hotspot_y = du->hotspot_y + fb->hot_y;
315
316	/* A lot of the code assumes this */
317	if (crtc_w != 64 \|\| crtc_h != 64) {
318	ret = -EINVAL;
319	goto out;
320	}
321
322	if (vmw_framebuffer_to_vfb(fb)->dmabuf)
323	dmabuf = vmw_framebuffer_to_vfbd(fb)->buffer;
324	else
325	surface = vmw_framebuffer_to_vfbs(fb)->surface;
326
327	if (surface && !surface->snooper.image) {
328	DRM_ERROR("surface not suitable for cursor\n");
329	ret = -EINVAL;
330	goto out;
331	}
332
333	/* setup new image */
334	ret = 0;
335	if (surface) {
336	/* vmw_user_surface_lookup takes one reference */
337	du->cursor_surface = surface;
338
339	du->cursor_age = du->cursor_surface->snooper.age;
340
341	ret = vmw_cursor_update_image(dev_priv, surface->snooper.image,
342	64, 64, hotspot_x, hotspot_y);
343	} else if (dmabuf) {
344	/* vmw_user_surface_lookup takes one reference */
345	du->cursor_dmabuf = dmabuf;
346
347	ret = vmw_cursor_update_dmabuf(dev_priv, dmabuf, crtc_w, crtc_h,
348	hotspot_x, hotspot_y);
349	} else {
350	vmw_cursor_update_position(dev_priv, false, 0, 0);
351	goto out;
352	}
353
354	if (!ret) {
355	du->cursor_x = crtc_x + du->set_gui_x;
356	du->cursor_y = crtc_y + du->set_gui_y;
357
358	vmw_cursor_update_position(dev_priv, true,
359	du->cursor_x + hotspot_x,
360	du->cursor_y + hotspot_y);
361	}
362
363	out:
364	return ret;
365	}
366
367
368	int vmw_du_cursor_plane_disable(struct drm_plane *plane)
369	{
370	if (plane->fb) {
371	drm_framebuffer_unreference(plane->fb);
372	plane->fb = NULL;
373	}
374
375	return -EINVAL;
376	}
377
378
379	void vmw_du_cursor_plane_destroy(struct drm_plane *plane)	277	void vmw_du_cursor_plane_destroy(struct drm_plane *plane)
380	{	278	{
381	vmw_cursor_update_position(plane->dev->dev_private, false, 0, 0);	279	vmw_cursor_update_position(plane->dev->dev_private, false, 0, 0);
@@ -472,18 +370,6 @@ vmw_du_cursor_plane_prepare_fb(struct drm_plane *plane, · 90 unmodified lines
472	}	370	}
473		371
474		372
475	void
476	vmw_du_cursor_plane_atomic_disable(struct drm_plane *plane,
477	struct drm_plane_state *old_state)
478	{
479	struct drm_crtc *crtc = plane->state->crtc ?: old_state->crtc;
480	struct vmw_private *dev_priv = vmw_priv(crtc->dev);
481
482	drm_atomic_set_fb_for_plane(plane->state, NULL);
483	vmw_cursor_update_position(dev_priv, false, 0, 0);
484	}
485
486
487	void	373	void
488	vmw_du_cursor_plane_atomic_update(struct drm_plane *plane,	374	vmw_du_cursor_plane_atomic_update(struct drm_plane *plane,
489	struct drm_plane_state *old_state)	375	struct drm_plane_state *old_state)
@@ -1498,6 +1384,7 @@ vmw_kms_new_framebuffer(struct vmw_private *dev_priv, · 1008 unmodified lines
1498	*/	1384	*/
1499	if (vmw_kms_srf_ok(dev_priv, mode_cmd->width, mode_cmd->height) &&	1385	if (vmw_kms_srf_ok(dev_priv, mode_cmd->width, mode_cmd->height) &&
1500	dmabuf && only_2d &&	1386	dmabuf && only_2d &&
		1387	mode_cmd->width > 64 && /* Don't create a proxy for cursor */
1501	dev_priv->active_display_unit == vmw_du_screen_target) {	1388	dev_priv->active_display_unit == vmw_du_screen_target) {
1502	ret = vmw_create_dmabuf_proxy(dev_priv->dev, mode_cmd,	1389	ret = vmw_create_dmabuf_proxy(dev_priv->dev, mode_cmd,
1503	dmabuf, &surface);	1390	dmabuf, &surface);

drivers/gpu/drm/vmwgfx/vmwgfx_kms.h+0−15

 			   u16 *r, u16 *g, u16 *b,
 			   uint32_t size,
 			   struct drm_modeset_acquire_ctx *ctx);
-int vmw_du_crtc_cursor_set2(struct drm_crtc *crtc, struct drm_file *file_priv,
-			    uint32_t handle, uint32_t width, uint32_t height,
-			    int32_t hot_x, int32_t hot_y);
-int vmw_du_crtc_cursor_move(struct drm_crtc *crtc, int x, int y);
 int vmw_du_connector_set_property(struct drm_connector *connector,
 				  struct drm_property *property,
 				  uint64_t val);
 /* Universal Plane Helpers */
 void vmw_du_primary_plane_destroy(struct drm_plane *plane);
 void vmw_du_cursor_plane_destroy(struct drm_plane *plane);
-int vmw_du_cursor_plane_disable(struct drm_plane *plane);
-int vmw_du_cursor_plane_update(struct drm_plane *plane,
-			       struct drm_crtc *crtc,
-			       struct drm_framebuffer *fb,
-			       int crtc_x, int crtc_y,
-			       unsigned int crtc_w,
-			       unsigned int crtc_h,
-			       uint32_t src_x, uint32_t src_y,
-			       uint32_t src_w, uint32_t src_h);
 /* Atomic Helpers */
 int vmw_du_primary_plane_atomic_check(struct drm_plane *plane,
 				     struct drm_plane_state *state);
 void vmw_du_cursor_plane_atomic_update(struct drm_plane *plane,
 				       struct drm_plane_state *old_state);
-void vmw_du_cursor_plane_atomic_disable(struct drm_plane *plane,
-					struct drm_plane_state *old_state);
 int vmw_du_cursor_plane_prepare_fb(struct drm_plane *plane,
 				   struct drm_plane_state *new_state);
 void vmw_du_plane_cleanup_fb(struct drm_plane *plane,

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c+22−5

  * @right: Right side of bounding box.
  * @top: Top side of bounding box.
  * @bottom: Bottom side of bounding box.
+ * @fb_left: Left side of the framebuffer/content bounding box
+ * @fb_top: Top of the framebuffer/content bounding box
  * @buf: DMA buffer when DMA-ing between buffer and screen targets.
  * @sid: Surface ID when copying between surface and screen targets.
  */
 	struct vmw_kms_dirty base;
 	SVGA3dTransferType  transfer;
 	s32 left, right, top, bottom;
+	s32 fb_left, fb_top;
 	u32 pitch;
 	union {
 		struct vmw_dma_buffer *buf;
  *
  * @dirty: The closure structure.
  *
- * This function calculates the bounding box for all the incoming clips
+ * This function calculates the bounding box for all the incoming clips.
  */
 static void vmw_stdu_dmabuf_cpu_clip(struct vmw_kms_dirty *dirty)
 {
 	dirty->num_hits = 1;
-	/* Calculate bounding box */
+	/* Calculate destination bounding box */
 	ddirty->left = min_t(s32, ddirty->left, dirty->unit_x1);
 	ddirty->top = min_t(s32, ddirty->top, dirty->unit_y1);
 	ddirty->right = max_t(s32, ddirty->right, dirty->unit_x2);
 	ddirty->bottom = max_t(s32, ddirty->bottom, dirty->unit_y2);
+	/*
+	 * Calculate content bounding box.  We only need the top-left
+	 * coordinate because width and height will be the same as the
+	 * destination bounding box above
+	 */
+	ddirty->fb_left = min_t(s32, ddirty->fb_left, dirty->fb_x);
+	ddirty->fb_top  = min_t(s32, ddirty->fb_top, dirty->fb_y);
 }
 	/* Assume we are blitting from Host (display_srf) to Guest (dmabuf) */
 	src_pitch = stdu->display_srf->base_size.width * stdu->cpp;
 	src = ttm_kmap_obj_virtual(&stdu->host_map, &not_used);
-	src += dirty->unit_y1 * src_pitch + dirty->unit_x1 * stdu->cpp;
+	src += ddirty->top * src_pitch + ddirty->left * stdu->cpp;
 	dst_pitch = ddirty->pitch;
 	dst = ttm_kmap_obj_virtual(&stdu->guest_map, &not_used);
-	dst += dirty->fb_y * dst_pitch + dirty->fb_x * stdu->cpp;
+	dst += ddirty->fb_top * dst_pitch + ddirty->fb_left * stdu->cpp;
 	/* Figure out the real direction */
 	}
 out_cleanup:
-	ddirty->left = ddirty->top = S32_MAX;
+	ddirty->left = ddirty->top = ddirty->fb_left = ddirty->fb_top = S32_MAX;
 	ddirty->right = ddirty->bottom = S32_MIN;
 }
 		SVGA3D_READ_HOST_VRAM;
 	ddirty.left = ddirty.top = S32_MAX;
 	ddirty.right = ddirty.bottom = S32_MIN;
+	ddirty.fb_left = ddirty.fb_top = S32_MAX;
 	ddirty.pitch = vfb->base.pitches[0];
 	ddirty.buf = buf;
 	ddirty.base.fifo_commit = vmw_stdu_dmabuf_fifo_commit;
 		DRM_ERROR("Failed to bind surface to STDU.\n");
 	else
 		crtc->primary->fb = plane->state->fb;
+	ret = vmw_stdu_update_st(dev_priv, stdu);
+	if (ret)
+		DRM_ERROR("Failed to update STDU.\n");
 }

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c+15−8

 	struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile;
 	int ret;
 	uint32_t size;
-	uint32_t backup_handle;
+	uint32_t backup_handle = 0;
 	if (req->multisample_count != 0)
 		return -EINVAL;
+	if (req->mip_levels > DRM_VMW_MAX_MIP_LEVELS)
+		return -EINVAL;
 	if (unlikely(vmw_user_surface_size == 0))
 		vmw_user_surface_size = ttm_round_pot(sizeof(*user_srf)) +
 			128;
 		ret = vmw_user_dmabuf_lookup(tfile, req->buffer_handle,
 					     &res->backup,
 					     &user_srf->backup_base);
-		if (ret == 0 && res->backup->base.num_pages * PAGE_SIZE <
+		if (ret == 0) {
-		    res->backup_size) {
+			if (res->backup->base.num_pages * PAGE_SIZE <
-			DRM_ERROR("Surface backup buffer is too small.\n");
+			    res->backup_size) {
-			vmw_dmabuf_unreference(&res->backup);
+				DRM_ERROR("Surface backup buffer is too small.\n");
-			ret = -EINVAL;
+				vmw_dmabuf_unreference(&res->backup);
-			goto out_unlock;
+				ret = -EINVAL;
+				goto out_unlock;
+			} else {
+				backup_handle = req->buffer_handle;
+			}
 		}
 	} else if (req->drm_surface_flags & drm_vmw_surface_flag_create_buffer)
 		ret = vmw_user_dmabuf_alloc(dev_priv, tfile,
 				 dev_priv->stdu_max_height);
 		if (size.width > max_width || size.height > max_height) {
-			DRM_ERROR("%ux%u\n, exeeds max surface size %ux%u",
+			DRM_ERROR("%ux%u\n, exceeds max surface size %ux%u",
 				  size.width, size.height,
 				  max_width, max_height);
 			return -EINVAL;

drivers/gpu/host1x/dev.c+1−1

@@ -172,7 +172,7 @@ static int host1x_probe(struct platform_device *pdev) · 171 unmodified lines
172		172
173	host->rst = devm_reset_control_get(&pdev->dev, "host1x");	173	host->rst = devm_reset_control_get(&pdev->dev, "host1x");
174	if (IS_ERR(host->rst)) {	174	if (IS_ERR(host->rst)) {
175	err = PTR_ERR(host->clk);	175	err = PTR_ERR(host->rst);
176	dev_err(&pdev->dev, "failed to get reset: %d\n", err);	176	dev_err(&pdev->dev, "failed to get reset: %d\n", err);
177	return err;	177	return err;
178	}	178	}

drivers/gpu/ipu-v3/ipu-common.c+8−7

@@ -725,15 +725,16 @@ void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi) · 724 unmodified lines
725	spin_lock_irqsave(&ipu->lock, flags);	725	spin_lock_irqsave(&ipu->lock, flags);
726		726
727	val = ipu_cm_read(ipu, IPU_CONF);	727	val = ipu_cm_read(ipu, IPU_CONF);
728	if (vdi) {	728	if (vdi)
729	val \|= IPU_CONF_IC_INPUT;	729	val \|= IPU_CONF_IC_INPUT;
730	} else {	730	else
731	val &= ~IPU_CONF_IC_INPUT;	731	val &= ~IPU_CONF_IC_INPUT;
732	if (csi_id == 1)	732
733	val \|= IPU_CONF_CSI_SEL;	733	if (csi_id == 1)
734	else	734	val \|= IPU_CONF_CSI_SEL;
735	val &= ~IPU_CONF_CSI_SEL;	735	else
736	}	736	val &= ~IPU_CONF_CSI_SEL;
		737
737	ipu_cm_write(ipu, val, IPU_CONF);	738	ipu_cm_write(ipu, val, IPU_CONF);
738		739
739	spin_unlock_irqrestore(&ipu->lock, flags);	740	spin_unlock_irqrestore(&ipu->lock, flags);

drivers/gpu/ipu-v3/ipu-pre.c+5−8

 	if (pre->in_use)
 		return -EBUSY;
-	clk_prepare_enable(pre->clk_axi);
 	/* first get the engine out of reset and remove clock gating */
 	writel(0, pre->regs + IPU_PRE_CTRL);
 void ipu_pre_put(struct ipu_pre *pre)
 {
-	u32 val;
+	writel(IPU_PRE_CTRL_SFTRST, pre->regs + IPU_PRE_CTRL);
-	val = IPU_PRE_CTRL_SFTRST | IPU_PRE_CTRL_CLKGATE;
-	writel(val, pre->regs + IPU_PRE_CTRL);
-	clk_disable_unprepare(pre->clk_axi);
 	pre->in_use = false;
 }
 	if (!pre->buffer_virt)
 		return -ENOMEM;
+	clk_prepare_enable(pre->clk_axi);
 	pre->dev = dev;
 	platform_set_drvdata(pdev, pre);
 	mutex_lock(&ipu_pre_list_mutex);
 	available_pres--;
 	mutex_unlock(&ipu_pre_list_mutex);
+	clk_disable_unprepare(pre->clk_axi);
 	if (pre->buffer_virt)
 		gen_pool_free(pre->iram, (unsigned long)pre->buffer_virt,
 			      IPU_PRE_MAX_WIDTH * IPU_PRE_NUM_SCANLINES * 4);

drivers/hid/Kconfig+4−2

 	 - Trio Linker Plus II
 config HID_ELECOM
-	tristate "ELECOM BM084 bluetooth mouse"
+	tristate "ELECOM HID devices"
 	depends on HID
 	---help---
-	Support for the ELECOM BM084 (bluetooth mouse).
+	Support for ELECOM devices:
+	  - BM084 Bluetooth Mouse
+	  - DEFT Trackball (Wired and wireless)
 config HID_ELO
 	tristate "ELO USB 4000/4500 touchscreen"

drivers/hid/hid-asus.c+12−0

 #define QUIRK_IS_MULTITOUCH		BIT(3)
 #define QUIRK_NO_CONSUMER_USAGES	BIT(4)
 #define QUIRK_USE_KBD_BACKLIGHT		BIT(5)
+#define QUIRK_T100_KEYBOARD		BIT(6)
 #define I2C_KEYBOARD_QUIRKS			(QUIRK_FIX_NOTEBOOK_REPORT | \
 						 QUIRK_NO_INIT_REPORTS | \
 		drvdata->kbd_backlight->removed = true;
 		cancel_work_sync(&drvdata->kbd_backlight->work);
 	}
+	hid_hw_stop(hdev);
 }
 static __u8 *asus_report_fixup(struct hid_device *hdev, __u8 *rdesc,
 		hid_info(hdev, "Fixing up Asus notebook report descriptor\n");
 		rdesc[55] = 0xdd;
 	}
+	if (drvdata->quirks & QUIRK_T100_KEYBOARD &&
+		 *rsize == 76 && rdesc[73] == 0x81 && rdesc[74] == 0x01) {
+		hid_info(hdev, "Fixing up Asus T100 keyb report descriptor\n");
+		rdesc[74] &= ~HID_MAIN_ITEM_CONSTANT;
+	}
 	return rdesc;
 }
 		USB_DEVICE_ID_ASUSTEK_ROG_KEYBOARD1) },
 	{ HID_USB_DEVICE(USB_VENDOR_ID_ASUSTEK,
 		USB_DEVICE_ID_ASUSTEK_ROG_KEYBOARD2), QUIRK_USE_KBD_BACKLIGHT },
+	{ HID_USB_DEVICE(USB_VENDOR_ID_ASUSTEK,
+		USB_DEVICE_ID_ASUSTEK_T100_KEYBOARD),
+	  QUIRK_T100_KEYBOARD | QUIRK_NO_CONSUMER_USAGES },
 	{ }
 };
 MODULE_DEVICE_TABLE(hid, asus_devices);

drivers/hid/hid-core.c+224−61

@@ -826,11 +826,35 @@ static int hid_scan_report(struct hid_device *hid) · 825 unmodified lines
826	* hid-rmi should take care of them,	826	* hid-rmi should take care of them,
827	* not hid-generic	827	* not hid-generic
828	*/	828	*/
829	if (IS_ENABLED(CONFIG_HID_RMI))	829	hid->group = HID_GROUP_RMI;
830	hid->group = HID_GROUP_RMI;
831	break;	830	break;
832	}	831	}
833		832
		833	/* fall back to generic driver in case specific driver doesn't exist */
		834	switch (hid->group) {
		835	case HID_GROUP_MULTITOUCH_WIN_8:
		836	/* fall-through */
		837	case HID_GROUP_MULTITOUCH:
		838	if (!IS_ENABLED(CONFIG_HID_MULTITOUCH))
		839	hid->group = HID_GROUP_GENERIC;
		840	break;
		841	case HID_GROUP_SENSOR_HUB:
		842	if (!IS_ENABLED(CONFIG_HID_SENSOR_HUB))
		843	hid->group = HID_GROUP_GENERIC;
		844	break;
		845	case HID_GROUP_RMI:
		846	if (!IS_ENABLED(CONFIG_HID_RMI))
		847	hid->group = HID_GROUP_GENERIC;
		848	break;
		849	case HID_GROUP_WACOM:
		850	if (!IS_ENABLED(CONFIG_HID_WACOM))
		851	hid->group = HID_GROUP_GENERIC;
		852	break;
		853	case HID_GROUP_LOGITECH_DJ_DEVICE:
		854	if (!IS_ENABLED(CONFIG_HID_LOGITECH_DJ))
		855	hid->group = HID_GROUP_GENERIC;
		856	break;
		857	}
834	vfree(parser);	858	vfree(parser);
835	return 0;	859	return 0;
836	}	860	}
@@ -1763,15 +1787,23 @@ EXPORT_SYMBOL_GPL(hid_disconnect); · 926 unmodified lines
1763	* used as a driver. See hid_scan_report().	1787	* used as a driver. See hid_scan_report().
1764	*/	1788	*/
1765	static const struct hid_device_id hid_have_special_driver[] = {	1789	static const struct hid_device_id hid_have_special_driver[] = {
		1790	#if IS_ENABLED(CONFIG_HID_A4TECH)
1766	{ HID_USB_DEVICE(USB_VENDOR_ID_A4TECH, USB_DEVICE_ID_A4TECH_WCP32PU) },	1791	{ HID_USB_DEVICE(USB_VENDOR_ID_A4TECH, USB_DEVICE_ID_A4TECH_WCP32PU) },
1767	{ HID_USB_DEVICE(USB_VENDOR_ID_A4TECH, USB_DEVICE_ID_A4TECH_X5_005D) },	1792	{ HID_USB_DEVICE(USB_VENDOR_ID_A4TECH, USB_DEVICE_ID_A4TECH_X5_005D) },
1768	{ HID_USB_DEVICE(USB_VENDOR_ID_A4TECH, USB_DEVICE_ID_A4TECH_RP_649) },	1793	{ HID_USB_DEVICE(USB_VENDOR_ID_A4TECH, USB_DEVICE_ID_A4TECH_RP_649) },
		1794	#endif
		1795	#if IS_ENABLED(CONFIG_HID_ACCUTOUCH)
		1796	{ HID_USB_DEVICE(USB_VENDOR_ID_ELO, USB_DEVICE_ID_ELO_ACCUTOUCH_2216) },
		1797	#endif
		1798	#if IS_ENABLED(CONFIG_HID_ACRUX)
1769	{ HID_USB_DEVICE(USB_VENDOR_ID_ACRUX, 0x0802) },	1799	{ HID_USB_DEVICE(USB_VENDOR_ID_ACRUX, 0x0802) },
1770	{ HID_USB_DEVICE(USB_VENDOR_ID_ACRUX, 0xf705) },	1800	{ HID_USB_DEVICE(USB_VENDOR_ID_ACRUX, 0xf705) },
		1801	#endif
		1802	#if IS_ENABLED(CONFIG_HID_ALPS)
1771	{ HID_DEVICE(HID_BUS_ANY, HID_GROUP_ANY, USB_VENDOR_ID_ALPS_JP, HID_DEVICE_ID_ALPS_U1_DUAL) },	1803	{ HID_DEVICE(HID_BUS_ANY, HID_GROUP_ANY, USB_VENDOR_ID_ALPS_JP, HID_DEVICE_ID_ALPS_U1_DUAL) },
		1804	#endif
		1805	#if IS_ENABLED(CONFIG_HID_APPLE)
1772	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_MIGHTYMOUSE) },	1806	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_MIGHTYMOUSE) },
1773	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_MAGICMOUSE) },
1774	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_MAGICTRACKPAD) },
1775	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_FOUNTAIN_ANSI) },	1807	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_FOUNTAIN_ANSI) },
1776	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_FOUNTAIN_ISO) },	1808	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_FOUNTAIN_ISO) },
1777	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER_ANSI) },	1809	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER_ANSI) },
@@ -1792,11 +1824,6 @@ static const struct hid_device_id hid_have_special_driver[] = { · 14 unmodified lines
1792	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER4_HF_ANSI) },	1824	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER4_HF_ANSI) },
1793	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER4_HF_ISO) },	1825	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER4_HF_ISO) },
1794	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER4_HF_JIS) },	1826	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER4_HF_JIS) },
1795	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_IRCONTROL) },
1796	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_IRCONTROL2) },
1797	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_IRCONTROL3) },
1798	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_IRCONTROL4) },
1799	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_IRCONTROL5) },
1800	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_WIRELESS_ANSI) },	1827	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_WIRELESS_ANSI) },
1801	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_WIRELESS_ISO) },	1828	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_WIRELESS_ISO) },
1802	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_WIRELESS_JIS) },	1829	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_WIRELESS_JIS) },
@@ -1851,59 +1878,100 @@ static const struct hid_device_id hid_have_special_driver[] = { · 48 unmodified lines
1851	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_MAGIC_KEYBOARD_ANSI) },	1878	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_MAGIC_KEYBOARD_ANSI) },
1852	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_FOUNTAIN_TP_ONLY) },	1879	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_FOUNTAIN_TP_ONLY) },
1853	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER1_TP_ONLY) },	1880	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER1_TP_ONLY) },
		1881	#endif
		1882	#if IS_ENABLED(CONFIG_HID_APPLEIR)
		1883	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_IRCONTROL) },
		1884	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_IRCONTROL2) },
		1885	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_IRCONTROL3) },
		1886	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_IRCONTROL4) },
		1887	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_IRCONTROL5) },
		1888	#endif
		1889	#if IS_ENABLED(CONFIG_HID_ASUS)
1854	{ HID_I2C_DEVICE(USB_VENDOR_ID_ASUSTEK, USB_DEVICE_ID_ASUSTEK_I2C_KEYBOARD) },	1890	{ HID_I2C_DEVICE(USB_VENDOR_ID_ASUSTEK, USB_DEVICE_ID_ASUSTEK_I2C_KEYBOARD) },
1855	{ HID_I2C_DEVICE(USB_VENDOR_ID_ASUSTEK, USB_DEVICE_ID_ASUSTEK_I2C_TOUCHPAD) },	1891	{ HID_I2C_DEVICE(USB_VENDOR_ID_ASUSTEK, USB_DEVICE_ID_ASUSTEK_I2C_TOUCHPAD) },
1856	{ HID_USB_DEVICE(USB_VENDOR_ID_ASUSTEK, USB_DEVICE_ID_ASUSTEK_ROG_KEYBOARD1) },	1892	{ HID_USB_DEVICE(USB_VENDOR_ID_ASUSTEK, USB_DEVICE_ID_ASUSTEK_ROG_KEYBOARD1) },
1857	{ HID_USB_DEVICE(USB_VENDOR_ID_ASUSTEK, USB_DEVICE_ID_ASUSTEK_ROG_KEYBOARD2) },	1893	{ HID_USB_DEVICE(USB_VENDOR_ID_ASUSTEK, USB_DEVICE_ID_ASUSTEK_ROG_KEYBOARD2) },
		1894	{ HID_USB_DEVICE(USB_VENDOR_ID_ASUSTEK, USB_DEVICE_ID_ASUSTEK_T100_KEYBOARD) },
		1895	#endif
		1896	#if IS_ENABLED(CONFIG_HID_AUREAL)
1858	{ HID_USB_DEVICE(USB_VENDOR_ID_AUREAL, USB_DEVICE_ID_AUREAL_W01RN) },	1897	{ HID_USB_DEVICE(USB_VENDOR_ID_AUREAL, USB_DEVICE_ID_AUREAL_W01RN) },
		1898	#endif
		1899	#if IS_ENABLED(CONFIG_HID_BELKIN)
1859	{ HID_USB_DEVICE(USB_VENDOR_ID_BELKIN, USB_DEVICE_ID_FLIP_KVM) },	1900	{ HID_USB_DEVICE(USB_VENDOR_ID_BELKIN, USB_DEVICE_ID_FLIP_KVM) },
		1901	{ HID_USB_DEVICE(USB_VENDOR_ID_LABTEC, USB_DEVICE_ID_LABTEC_WIRELESS_KEYBOARD) },
		1902	#endif
		1903	#if IS_ENABLED(CONFIG_HID_BETOP_FF)
1860	{ HID_USB_DEVICE(USB_VENDOR_ID_BETOP_2185BFM, 0x2208) },	1904	{ HID_USB_DEVICE(USB_VENDOR_ID_BETOP_2185BFM, 0x2208) },
1861	{ HID_USB_DEVICE(USB_VENDOR_ID_BETOP_2185PC, 0x5506) },	1905	{ HID_USB_DEVICE(USB_VENDOR_ID_BETOP_2185PC, 0x5506) },
1862	{ HID_USB_DEVICE(USB_VENDOR_ID_BETOP_2185V2PC, 0x1850) },	1906	{ HID_USB_DEVICE(USB_VENDOR_ID_BETOP_2185V2PC, 0x1850) },
1863	{ HID_USB_DEVICE(USB_VENDOR_ID_BETOP_2185V2BFM, 0x5500) },	1907	{ HID_USB_DEVICE(USB_VENDOR_ID_BETOP_2185V2BFM, 0x5500) },
1864	{ HID_USB_DEVICE(USB_VENDOR_ID_BTC, USB_DEVICE_ID_BTC_EMPREX_REMOTE) },	1908	#endif
1865	{ HID_USB_DEVICE(USB_VENDOR_ID_BTC, USB_DEVICE_ID_BTC_EMPREX_REMOTE_2) },	1909	#if IS_ENABLED(CONFIG_HID_CHERRY)
1866	{ HID_USB_DEVICE(USB_VENDOR_ID_CHERRY, USB_DEVICE_ID_CHERRY_CYMOTION) },	1910	{ HID_USB_DEVICE(USB_VENDOR_ID_CHERRY, USB_DEVICE_ID_CHERRY_CYMOTION) },
1867	{ HID_USB_DEVICE(USB_VENDOR_ID_CHERRY, USB_DEVICE_ID_CHERRY_CYMOTION_SOLAR) },	1911	{ HID_USB_DEVICE(USB_VENDOR_ID_CHERRY, USB_DEVICE_ID_CHERRY_CYMOTION_SOLAR) },
		1912	#endif
		1913	#if IS_ENABLED(CONFIG_HID_CHICONY)
1868	{ HID_USB_DEVICE(USB_VENDOR_ID_CHICONY, USB_DEVICE_ID_CHICONY_TACTICAL_PAD) },	1914	{ HID_USB_DEVICE(USB_VENDOR_ID_CHICONY, USB_DEVICE_ID_CHICONY_TACTICAL_PAD) },
1869	{ HID_USB_DEVICE(USB_VENDOR_ID_CHICONY, USB_DEVICE_ID_CHICONY_WIRELESS) },
1870	{ HID_USB_DEVICE(USB_VENDOR_ID_CHICONY, USB_DEVICE_ID_CHICONY_WIRELESS2) },	1915	{ HID_USB_DEVICE(USB_VENDOR_ID_CHICONY, USB_DEVICE_ID_CHICONY_WIRELESS2) },
1871	{ HID_USB_DEVICE(USB_VENDOR_ID_CHICONY, USB_DEVICE_ID_CHICONY_AK1D) },	1916	{ HID_USB_DEVICE(USB_VENDOR_ID_CHICONY, USB_DEVICE_ID_CHICONY_AK1D) },
1872	{ HID_USB_DEVICE(USB_VENDOR_ID_CHICONY, USB_DEVICE_ID_CHICONY_ACER_SWITCH12) },	1917	{ HID_USB_DEVICE(USB_VENDOR_ID_CHICONY, USB_DEVICE_ID_CHICONY_ACER_SWITCH12) },
		1918	{ HID_USB_DEVICE(USB_VENDOR_ID_JESS, USB_DEVICE_ID_JESS_ZEN_AIO_KBD) },
		1919	#endif
		1920	#if IS_ENABLED(CONFIG_HID_CMEDIA)
		1921	{ HID_USB_DEVICE(USB_VENDOR_ID_CMEDIA, USB_DEVICE_ID_CM6533) },
		1922	#endif
		1923	#if IS_ENABLED(CONFIG_HID_CORSAIR)
1873	{ HID_USB_DEVICE(USB_VENDOR_ID_CORSAIR, USB_DEVICE_ID_CORSAIR_K90) },	1924	{ HID_USB_DEVICE(USB_VENDOR_ID_CORSAIR, USB_DEVICE_ID_CORSAIR_K90) },
1874	{ HID_USB_DEVICE(USB_VENDOR_ID_CORSAIR, USB_DEVICE_ID_CORSAIR_SCIMITAR_PRO_RGB) },	1925	{ HID_USB_DEVICE(USB_VENDOR_ID_CORSAIR, USB_DEVICE_ID_CORSAIR_SCIMITAR_PRO_RGB) },
1875	{ HID_USB_DEVICE(USB_VENDOR_ID_CREATIVELABS, USB_DEVICE_ID_PRODIKEYS_PCMIDI) },	1926	#endif
		1927	#if IS_ENABLED(CONFIG_HID_CP2112)
1876	{ HID_USB_DEVICE(USB_VENDOR_ID_CYGNAL, USB_DEVICE_ID_CYGNAL_CP2112) },	1928	{ HID_USB_DEVICE(USB_VENDOR_ID_CYGNAL, USB_DEVICE_ID_CYGNAL_CP2112) },
		1929	#endif
		1930	#if IS_ENABLED(CONFIG_HID_CYPRESS)
1877	{ HID_USB_DEVICE(USB_VENDOR_ID_CYPRESS, USB_DEVICE_ID_CYPRESS_BARCODE_1) },	1931	{ HID_USB_DEVICE(USB_VENDOR_ID_CYPRESS, USB_DEVICE_ID_CYPRESS_BARCODE_1) },
1878	{ HID_USB_DEVICE(USB_VENDOR_ID_CYPRESS, USB_DEVICE_ID_CYPRESS_BARCODE_2) },	1932	{ HID_USB_DEVICE(USB_VENDOR_ID_CYPRESS, USB_DEVICE_ID_CYPRESS_BARCODE_2) },
1879	{ HID_USB_DEVICE(USB_VENDOR_ID_CYPRESS, USB_DEVICE_ID_CYPRESS_BARCODE_3) },	1933	{ HID_USB_DEVICE(USB_VENDOR_ID_CYPRESS, USB_DEVICE_ID_CYPRESS_BARCODE_3) },
1880	{ HID_USB_DEVICE(USB_VENDOR_ID_CYPRESS, USB_DEVICE_ID_CYPRESS_BARCODE_4) },	1934	{ HID_USB_DEVICE(USB_VENDOR_ID_CYPRESS, USB_DEVICE_ID_CYPRESS_BARCODE_4) },
1881	{ HID_USB_DEVICE(USB_VENDOR_ID_CYPRESS, USB_DEVICE_ID_CYPRESS_MOUSE) },	1935	{ HID_USB_DEVICE(USB_VENDOR_ID_CYPRESS, USB_DEVICE_ID_CYPRESS_MOUSE) },
1882	{ HID_USB_DEVICE(USB_VENDOR_ID_DELCOM, USB_DEVICE_ID_DELCOM_VISUAL_IND) },	1936	#endif
		1937	#if IS_ENABLED(CONFIG_HID_DRAGONRISE)
1883	{ HID_USB_DEVICE(USB_VENDOR_ID_DRAGONRISE, 0x0006) },	1938	{ HID_USB_DEVICE(USB_VENDOR_ID_DRAGONRISE, 0x0006) },
1884	{ HID_USB_DEVICE(USB_VENDOR_ID_DRAGONRISE, 0x0011) },	1939	{ HID_USB_DEVICE(USB_VENDOR_ID_DRAGONRISE, 0x0011) },
1885	#if IS_ENABLED(CONFIG_HID_MAYFLASH)
1886	{ HID_USB_DEVICE(USB_VENDOR_ID_DRAGONRISE, USB_DEVICE_ID_DRAGONRISE_PS3) },
1887	{ HID_USB_DEVICE(USB_VENDOR_ID_DRAGONRISE, USB_DEVICE_ID_DRAGONRISE_DOLPHINBAR) },
1888	{ HID_USB_DEVICE(USB_VENDOR_ID_DRAGONRISE, USB_DEVICE_ID_DRAGONRISE_GAMECUBE1) },
1889	{ HID_USB_DEVICE(USB_VENDOR_ID_DRAGONRISE, USB_DEVICE_ID_DRAGONRISE_GAMECUBE2) },
1890	#endif	1940	#endif
1891	{ HID_USB_DEVICE(USB_VENDOR_ID_DREAM_CHEEKY, USB_DEVICE_ID_DREAM_CHEEKY_WN) },	1941	#if IS_ENABLED(CONFIG_HID_ELECOM)
1892	{ HID_USB_DEVICE(USB_VENDOR_ID_DREAM_CHEEKY, USB_DEVICE_ID_DREAM_CHEEKY_FA) },
1893	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_ELECOM, USB_DEVICE_ID_ELECOM_BM084) },	1942	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_ELECOM, USB_DEVICE_ID_ELECOM_BM084) },
		1943	{ HID_USB_DEVICE(USB_VENDOR_ID_ELECOM, USB_DEVICE_ID_ELECOM_DEFT_WIRED) },
		1944	{ HID_USB_DEVICE(USB_VENDOR_ID_ELECOM, USB_DEVICE_ID_ELECOM_DEFT_WIRELESS) },
		1945	#endif
		1946	#if IS_ENABLED(CONFIG_HID_ELO)
1894	{ HID_USB_DEVICE(USB_VENDOR_ID_ELO, 0x0009) },	1947	{ HID_USB_DEVICE(USB_VENDOR_ID_ELO, 0x0009) },
1895	{ HID_USB_DEVICE(USB_VENDOR_ID_ELO, 0x0030) },	1948	{ HID_USB_DEVICE(USB_VENDOR_ID_ELO, 0x0030) },
1896	{ HID_USB_DEVICE(USB_VENDOR_ID_ELO, USB_DEVICE_ID_ELO_ACCUTOUCH_2216) },	1949	#endif
		1950	#if IS_ENABLED(CONFIG_HID_EMS_FF)
1897	{ HID_USB_DEVICE(USB_VENDOR_ID_EMS, USB_DEVICE_ID_EMS_TRIO_LINKER_PLUS_II) },	1951	{ HID_USB_DEVICE(USB_VENDOR_ID_EMS, USB_DEVICE_ID_EMS_TRIO_LINKER_PLUS_II) },
		1952	#endif
		1953	#if IS_ENABLED(CONFIG_HID_EZKEY)
1898	{ HID_USB_DEVICE(USB_VENDOR_ID_EZKEY, USB_DEVICE_ID_BTC_8193) },	1954	{ HID_USB_DEVICE(USB_VENDOR_ID_EZKEY, USB_DEVICE_ID_BTC_8193) },
1899	{ HID_USB_DEVICE(USB_VENDOR_ID_GAMERON, USB_DEVICE_ID_GAMERON_DUAL_PSX_ADAPTOR) },	1955	#endif
1900	{ HID_USB_DEVICE(USB_VENDOR_ID_GAMERON, USB_DEVICE_ID_GAMERON_DUAL_PCS_ADAPTOR) },	1956	#if IS_ENABLED(CONFIG_HID_GEMBIRD)
1901	{ HID_USB_DEVICE(USB_VENDOR_ID_GEMBIRD, USB_DEVICE_ID_GEMBIRD_JPD_DUALFORCE2) },	1957	{ HID_USB_DEVICE(USB_VENDOR_ID_GEMBIRD, USB_DEVICE_ID_GEMBIRD_JPD_DUALFORCE2) },
1902	{ HID_USB_DEVICE(USB_VENDOR_ID_GREENASIA, 0x0003) },	1958	#endif
		1959	#if IS_ENABLED(CONFIG_HID_GFRM)
		1960	{ HID_BLUETOOTH_DEVICE(0x58, 0x2000) },
		1961	{ HID_BLUETOOTH_DEVICE(0x471, 0x2210) },
		1962	#endif
		1963	#if IS_ENABLED(CONFIG_HID_GREENASIA)
1903	{ HID_USB_DEVICE(USB_VENDOR_ID_GREENASIA, 0x0012) },	1964	{ HID_USB_DEVICE(USB_VENDOR_ID_GREENASIA, 0x0012) },
		1965	#endif
		1966	#if IS_ENABLED(CONFIG_HID_GT683R)
		1967	{ HID_USB_DEVICE(USB_VENDOR_ID_MSI, USB_DEVICE_ID_MSI_GT683R_LED_PANEL) },
		1968	#endif
		1969	#if IS_ENABLED(CONFIG_HID_GYRATION)
1904	{ HID_USB_DEVICE(USB_VENDOR_ID_GYRATION, USB_DEVICE_ID_GYRATION_REMOTE) },	1970	{ HID_USB_DEVICE(USB_VENDOR_ID_GYRATION, USB_DEVICE_ID_GYRATION_REMOTE) },
1905	{ HID_USB_DEVICE(USB_VENDOR_ID_GYRATION, USB_DEVICE_ID_GYRATION_REMOTE_2) },	1971	{ HID_USB_DEVICE(USB_VENDOR_ID_GYRATION, USB_DEVICE_ID_GYRATION_REMOTE_2) },
1906	{ HID_USB_DEVICE(USB_VENDOR_ID_GYRATION, USB_DEVICE_ID_GYRATION_REMOTE_3) },	1972	{ HID_USB_DEVICE(USB_VENDOR_ID_GYRATION, USB_DEVICE_ID_GYRATION_REMOTE_3) },
		1973	#endif
		1974	#if IS_ENABLED(CONFIG_HID_HOLTEK)
1907	{ HID_USB_DEVICE(USB_VENDOR_ID_HOLTEK, USB_DEVICE_ID_HOLTEK_ON_LINE_GRIP) },	1975	{ HID_USB_DEVICE(USB_VENDOR_ID_HOLTEK, USB_DEVICE_ID_HOLTEK_ON_LINE_GRIP) },
1908	{ HID_USB_DEVICE(USB_VENDOR_ID_HOLTEK_ALT, USB_DEVICE_ID_HOLTEK_ALT_KEYBOARD) },	1976	{ HID_USB_DEVICE(USB_VENDOR_ID_HOLTEK_ALT, USB_DEVICE_ID_HOLTEK_ALT_KEYBOARD) },
1909	{ HID_USB_DEVICE(USB_VENDOR_ID_HOLTEK_ALT, USB_DEVICE_ID_HOLTEK_ALT_MOUSE_A04A) },	1977	{ HID_USB_DEVICE(USB_VENDOR_ID_HOLTEK_ALT, USB_DEVICE_ID_HOLTEK_ALT_MOUSE_A04A) },
@@ -1912,12 +1980,17 @@ static const struct hid_device_id hid_have_special_driver[] = { · 2 unmodified lines
1912	{ HID_USB_DEVICE(USB_VENDOR_ID_HOLTEK_ALT, USB_DEVICE_ID_HOLTEK_ALT_MOUSE_A072) },	1980	{ HID_USB_DEVICE(USB_VENDOR_ID_HOLTEK_ALT, USB_DEVICE_ID_HOLTEK_ALT_MOUSE_A072) },
1913	{ HID_USB_DEVICE(USB_VENDOR_ID_HOLTEK_ALT, USB_DEVICE_ID_HOLTEK_ALT_MOUSE_A081) },	1981	{ HID_USB_DEVICE(USB_VENDOR_ID_HOLTEK_ALT, USB_DEVICE_ID_HOLTEK_ALT_MOUSE_A081) },
1914	{ HID_USB_DEVICE(USB_VENDOR_ID_HOLTEK_ALT, USB_DEVICE_ID_HOLTEK_ALT_MOUSE_A0C2) },	1982	{ HID_USB_DEVICE(USB_VENDOR_ID_HOLTEK_ALT, USB_DEVICE_ID_HOLTEK_ALT_MOUSE_A0C2) },
1915	{ HID_USB_DEVICE(USB_VENDOR_ID_HUION, USB_DEVICE_ID_HUION_TABLET) },	1983	#endif
1916	{ HID_USB_DEVICE(USB_VENDOR_ID_JESS, USB_DEVICE_ID_JESS_ZEN_AIO_KBD) },	1984	#if IS_ENABLED(CONFIG_HID_ICADE)
1917	{ HID_USB_DEVICE(USB_VENDOR_ID_JESS2, USB_DEVICE_ID_JESS2_COLOR_RUMBLE_PAD) },
1918	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_ION, USB_DEVICE_ID_ICADE) },	1985	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_ION, USB_DEVICE_ID_ICADE) },
		1986	#endif
		1987	#if IS_ENABLED(CONFIG_HID_KENSINGTON)
1919	{ HID_USB_DEVICE(USB_VENDOR_ID_KENSINGTON, USB_DEVICE_ID_KS_SLIMBLADE) },	1988	{ HID_USB_DEVICE(USB_VENDOR_ID_KENSINGTON, USB_DEVICE_ID_KS_SLIMBLADE) },
		1989	#endif
		1990	#if IS_ENABLED(CONFIG_HID_KEYTOUCH)
1920	{ HID_USB_DEVICE(USB_VENDOR_ID_KEYTOUCH, USB_DEVICE_ID_KEYTOUCH_IEC) },	1991	{ HID_USB_DEVICE(USB_VENDOR_ID_KEYTOUCH, USB_DEVICE_ID_KEYTOUCH_IEC) },
		1992	#endif
		1993	#if IS_ENABLED(CONFIG_HID_KYE)
1921	{ HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_GENIUS_GILA_GAMING_MOUSE) },	1994	{ HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_GENIUS_GILA_GAMING_MOUSE) },
1922	{ HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_GENIUS_MANTICORE) },	1995	{ HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_GENIUS_MANTICORE) },
1923	{ HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_GENIUS_GX_IMPERATOR) },	1996	{ HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_GENIUS_GX_IMPERATOR) },
@@ -1927,21 +2000,29 @@ static const struct hid_device_id hid_have_special_driver[] = { · 3 unmodified lines
1927	{ HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_KYE_MOUSEPEN_I608X_V2) },	2000	{ HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_KYE_MOUSEPEN_I608X_V2) },
1928	{ HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_KYE_EASYPEN_M610X) },	2001	{ HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_KYE_EASYPEN_M610X) },
1929	{ HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_KYE_PENSKETCH_M912) },	2002	{ HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_KYE_PENSKETCH_M912) },
1930	{ HID_USB_DEVICE(USB_VENDOR_ID_LABTEC, USB_DEVICE_ID_LABTEC_WIRELESS_KEYBOARD) },	2003	#endif
		2004	#if IS_ENABLED(CONFIG_HID_LCPOWER)
1931	{ HID_USB_DEVICE(USB_VENDOR_ID_LCPOWER, USB_DEVICE_ID_LCPOWER_LC1000 ) },	2005	{ HID_USB_DEVICE(USB_VENDOR_ID_LCPOWER, USB_DEVICE_ID_LCPOWER_LC1000 ) },
		2006	#endif
		2007	#if IS_ENABLED(CONFIG_HID_LED)
		2008	{ HID_USB_DEVICE(USB_VENDOR_ID_DELCOM, USB_DEVICE_ID_DELCOM_VISUAL_IND) },
		2009	{ HID_USB_DEVICE(USB_VENDOR_ID_DREAM_CHEEKY, USB_DEVICE_ID_DREAM_CHEEKY_WN) },
		2010	{ HID_USB_DEVICE(USB_VENDOR_ID_DREAM_CHEEKY, USB_DEVICE_ID_DREAM_CHEEKY_FA) },
		2011	{ HID_USB_DEVICE(USB_VENDOR_ID_MICROCHIP, USB_DEVICE_ID_LUXAFOR) },
		2012	{ HID_USB_DEVICE(USB_VENDOR_ID_RISO_KAGAKU, USB_DEVICE_ID_RI_KA_WEBMAIL) },
		2013	{ HID_USB_DEVICE(USB_VENDOR_ID_THINGM, USB_DEVICE_ID_BLINK1) },
		2014	#endif
1932	#if IS_ENABLED(CONFIG_HID_LENOVO)	2015	#if IS_ENABLED(CONFIG_HID_LENOVO)
1933	{ HID_USB_DEVICE(USB_VENDOR_ID_LENOVO, USB_DEVICE_ID_LENOVO_TPKBD) },	2016	{ HID_USB_DEVICE(USB_VENDOR_ID_LENOVO, USB_DEVICE_ID_LENOVO_TPKBD) },
1934	{ HID_USB_DEVICE(USB_VENDOR_ID_LENOVO, USB_DEVICE_ID_LENOVO_CUSBKBD) },	2017	{ HID_USB_DEVICE(USB_VENDOR_ID_LENOVO, USB_DEVICE_ID_LENOVO_CUSBKBD) },
1935	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_LENOVO, USB_DEVICE_ID_LENOVO_CBTKBD) },	2018	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_LENOVO, USB_DEVICE_ID_LENOVO_CBTKBD) },
1936	{ HID_USB_DEVICE(USB_VENDOR_ID_LENOVO, USB_DEVICE_ID_LENOVO_TPPRODOCK) },	2019	{ HID_USB_DEVICE(USB_VENDOR_ID_LENOVO, USB_DEVICE_ID_LENOVO_TPPRODOCK) },
1937	#endif	2020	#endif
1938	{ HID_USB_DEVICE(USB_VENDOR_ID_LG, USB_DEVICE_ID_LG_MELFAS_MT) },	2021	#if IS_ENABLED(CONFIG_HID_LOGITECH)
1939	{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_MX3000_RECEIVER) },	2022	{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_MX3000_RECEIVER) },
1940	{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_S510_RECEIVER) },	2023	{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_S510_RECEIVER) },
1941	{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_S510_RECEIVER_2) },	2024	{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_S510_RECEIVER_2) },
1942	{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_RECEIVER) },	2025	{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_RECEIVER) },
1943	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_PS3) },
1944	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_T651) },
1945	{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_DINOVO_DESKTOP) },	2026	{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_DINOVO_DESKTOP) },
1946	{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_DINOVO_EDGE) },	2027	{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_DINOVO_EDGE) },
1947	{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_DINOVO_MINI) },	2028	{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_DINOVO_MINI) },
@@ -1954,7 +2035,6 @@ static const struct hid_device_id hid_have_special_driver[] = { · 6 unmodified lines
1954	{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_RUMBLEPAD) },	2035	{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_RUMBLEPAD) },
1955	{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_RUMBLEPAD2_2) },	2036	{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_RUMBLEPAD2_2) },
1956	{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_G29_WHEEL) },	2037	{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_G29_WHEEL) },
1957	{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_G920_WHEEL) },
1958	{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_WINGMAN_F3D) },	2038	{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_WINGMAN_F3D) },
1959	{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_WINGMAN_FFG ) },	2039	{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_WINGMAN_FFG ) },
1960	{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_FORCE3D_PRO) },	2040	{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_FORCE3D_PRO) },
@@ -1966,17 +2046,30 @@ static const struct hid_device_id hid_have_special_driver[] = { · 5 unmodified lines
1966	{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_DFGT_WHEEL) },	2046	{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_DFGT_WHEEL) },
1967	{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_G25_WHEEL) },	2047	{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_G25_WHEEL) },
1968	{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_G27_WHEEL) },	2048	{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_G27_WHEEL) },
1969	#if IS_ENABLED(CONFIG_HID_LOGITECH_DJ)
1970	{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_UNIFYING_RECEIVER) },
1971	{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_UNIFYING_RECEIVER_2) },
1972	#endif
1973	{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_WII_WHEEL) },	2049	{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_WII_WHEEL) },
1974	{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_RUMBLEPAD2) },	2050	{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_RUMBLEPAD2) },
1975	{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_SPACETRAVELLER) },	2051	{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_SPACETRAVELLER) },
1976	{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_SPACENAVIGATOR) },	2052	{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_SPACENAVIGATOR) },
1977	{ HID_USB_DEVICE(USB_VENDOR_ID_MICROCHIP, USB_DEVICE_ID_PICOLCD) },	2053	#endif
1978	{ HID_USB_DEVICE(USB_VENDOR_ID_MICROCHIP, USB_DEVICE_ID_PICOLCD_BOOTLOADER) },	2054	#if IS_ENABLED(CONFIG_HID_LOGITECH_HIDPP)
1979	{ HID_USB_DEVICE(USB_VENDOR_ID_MICROCHIP, USB_DEVICE_ID_LUXAFOR) },	2055	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_T651) },
		2056	{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_G920_WHEEL) },
		2057	#endif
		2058	#if IS_ENABLED(CONFIG_HID_LOGITECH_DJ)
		2059	{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_UNIFYING_RECEIVER) },
		2060	{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_UNIFYING_RECEIVER_2) },
		2061	#endif
		2062	#if IS_ENABLED(CONFIG_HID_MAGICMOUSE)
		2063	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_MAGICMOUSE) },
		2064	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_MAGICTRACKPAD) },
		2065	#endif
		2066	#if IS_ENABLED(CONFIG_HID_MAYFLASH)
		2067	{ HID_USB_DEVICE(USB_VENDOR_ID_DRAGONRISE, USB_DEVICE_ID_DRAGONRISE_PS3) },
		2068	{ HID_USB_DEVICE(USB_VENDOR_ID_DRAGONRISE, USB_DEVICE_ID_DRAGONRISE_DOLPHINBAR) },
		2069	{ HID_USB_DEVICE(USB_VENDOR_ID_DRAGONRISE, USB_DEVICE_ID_DRAGONRISE_GAMECUBE1) },
		2070	{ HID_USB_DEVICE(USB_VENDOR_ID_DRAGONRISE, USB_DEVICE_ID_DRAGONRISE_GAMECUBE2) },
		2071	#endif
		2072	#if IS_ENABLED(CONFIG_HID_MICROSOFT)
1980	{ HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_COMFORT_MOUSE_4500) },	2073	{ HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_COMFORT_MOUSE_4500) },
1981	{ HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_COMFORT_KEYBOARD) },	2074	{ HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_COMFORT_KEYBOARD) },
1982	{ HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_SIDEWINDER_GV) },	2075	{ HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_SIDEWINDER_GV) },
@@ -1992,9 +2085,22 @@ static const struct hid_device_id hid_have_special_driver[] = { · 9 unmodified lines
1992	{ HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_DIGITAL_MEDIA_600) },	2085	{ HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_DIGITAL_MEDIA_600) },
1993	{ HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_DIGITAL_MEDIA_3KV1) },	2086	{ HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_DIGITAL_MEDIA_3KV1) },
1994	{ HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_POWER_COVER) },	2087	{ HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_POWER_COVER) },
		2088	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_PRESENTER_8K_BT) },
		2089	#endif
		2090	#if IS_ENABLED(CONFIG_HID_MONTEREY)
1995	{ HID_USB_DEVICE(USB_VENDOR_ID_MONTEREY, USB_DEVICE_ID_GENIUS_KB29E) },	2091	{ HID_USB_DEVICE(USB_VENDOR_ID_MONTEREY, USB_DEVICE_ID_GENIUS_KB29E) },
1996	{ HID_USB_DEVICE(USB_VENDOR_ID_MSI, USB_DEVICE_ID_MSI_GT683R_LED_PANEL) },	2092	#endif
		2093	#if IS_ENABLED(CONFIG_HID_MULTITOUCH)
		2094	{ HID_USB_DEVICE(USB_VENDOR_ID_LG, USB_DEVICE_ID_LG_MELFAS_MT) },
		2095	#endif
		2096	#if IS_ENABLED(CONFIG_HID_WIIMOTE)
		2097	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_NINTENDO, USB_DEVICE_ID_NINTENDO_WIIMOTE) },
		2098	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_NINTENDO, USB_DEVICE_ID_NINTENDO_WIIMOTE2) },
		2099	#endif
		2100	#if IS_ENABLED(CONFIG_HID_NTI)
1997	{ HID_USB_DEVICE(USB_VENDOR_ID_NTI, USB_DEVICE_ID_USB_SUN) },	2101	{ HID_USB_DEVICE(USB_VENDOR_ID_NTI, USB_DEVICE_ID_USB_SUN) },
		2102	#endif
		2103	#if IS_ENABLED(CONFIG_HID_NTRIG)
1998	{ HID_USB_DEVICE(USB_VENDOR_ID_NTRIG, USB_DEVICE_ID_NTRIG_TOUCH_SCREEN) },	2104	{ HID_USB_DEVICE(USB_VENDOR_ID_NTRIG, USB_DEVICE_ID_NTRIG_TOUCH_SCREEN) },
1999	{ HID_USB_DEVICE(USB_VENDOR_ID_NTRIG, USB_DEVICE_ID_NTRIG_TOUCH_SCREEN_1) },	2105	{ HID_USB_DEVICE(USB_VENDOR_ID_NTRIG, USB_DEVICE_ID_NTRIG_TOUCH_SCREEN_1) },
2000	{ HID_USB_DEVICE(USB_VENDOR_ID_NTRIG, USB_DEVICE_ID_NTRIG_TOUCH_SCREEN_2) },	2106	{ HID_USB_DEVICE(USB_VENDOR_ID_NTRIG, USB_DEVICE_ID_NTRIG_TOUCH_SCREEN_2) },
@@ -2014,13 +2120,41 @@ static const struct hid_device_id hid_have_special_driver[] = { · 13 unmodified lines
2014	{ HID_USB_DEVICE(USB_VENDOR_ID_NTRIG, USB_DEVICE_ID_NTRIG_TOUCH_SCREEN_16) },	2120	{ HID_USB_DEVICE(USB_VENDOR_ID_NTRIG, USB_DEVICE_ID_NTRIG_TOUCH_SCREEN_16) },
2015	{ HID_USB_DEVICE(USB_VENDOR_ID_NTRIG, USB_DEVICE_ID_NTRIG_TOUCH_SCREEN_17) },	2121	{ HID_USB_DEVICE(USB_VENDOR_ID_NTRIG, USB_DEVICE_ID_NTRIG_TOUCH_SCREEN_17) },
2016	{ HID_USB_DEVICE(USB_VENDOR_ID_NTRIG, USB_DEVICE_ID_NTRIG_TOUCH_SCREEN_18) },	2122	{ HID_USB_DEVICE(USB_VENDOR_ID_NTRIG, USB_DEVICE_ID_NTRIG_TOUCH_SCREEN_18) },
		2123	#endif
		2124	#if IS_ENABLED(CONFIG_HID_ORTEK)
2017	{ HID_USB_DEVICE(USB_VENDOR_ID_ORTEK, USB_DEVICE_ID_ORTEK_PKB1700) },	2125	{ HID_USB_DEVICE(USB_VENDOR_ID_ORTEK, USB_DEVICE_ID_ORTEK_PKB1700) },
2018	{ HID_USB_DEVICE(USB_VENDOR_ID_ORTEK, USB_DEVICE_ID_ORTEK_WKB2000) },	2126	{ HID_USB_DEVICE(USB_VENDOR_ID_ORTEK, USB_DEVICE_ID_ORTEK_WKB2000) },
		2127	{ HID_USB_DEVICE(USB_VENDOR_ID_SKYCABLE, USB_DEVICE_ID_SKYCABLE_WIRELESS_PRESENTER) },
		2128	#endif
		2129	#if IS_ENABLED(CONFIG_HID_PANTHERLORD)
		2130	{ HID_USB_DEVICE(USB_VENDOR_ID_GAMERON, USB_DEVICE_ID_GAMERON_DUAL_PSX_ADAPTOR) },
		2131	{ HID_USB_DEVICE(USB_VENDOR_ID_GAMERON, USB_DEVICE_ID_GAMERON_DUAL_PCS_ADAPTOR) },
		2132	{ HID_USB_DEVICE(USB_VENDOR_ID_GREENASIA, 0x0003) },
		2133	{ HID_USB_DEVICE(USB_VENDOR_ID_JESS2, USB_DEVICE_ID_JESS2_COLOR_RUMBLE_PAD) },
		2134	#endif
		2135	#if IS_ENABLED(CONFIG_HID_PENMOUNT)
2019	{ HID_USB_DEVICE(USB_VENDOR_ID_PENMOUNT, USB_DEVICE_ID_PENMOUNT_6000) },	2136	{ HID_USB_DEVICE(USB_VENDOR_ID_PENMOUNT, USB_DEVICE_ID_PENMOUNT_6000) },
		2137	#endif
		2138	#if IS_ENABLED(CONFIG_HID_PETALYNX)
2020	{ HID_USB_DEVICE(USB_VENDOR_ID_PETALYNX, USB_DEVICE_ID_PETALYNX_MAXTER_REMOTE) },	2139	{ HID_USB_DEVICE(USB_VENDOR_ID_PETALYNX, USB_DEVICE_ID_PETALYNX_MAXTER_REMOTE) },
		2140	#endif
		2141	#if IS_ENABLED(CONFIG_HID_PICOLCD)
		2142	{ HID_USB_DEVICE(USB_VENDOR_ID_MICROCHIP, USB_DEVICE_ID_PICOLCD) },
		2143	{ HID_USB_DEVICE(USB_VENDOR_ID_MICROCHIP, USB_DEVICE_ID_PICOLCD_BOOTLOADER) },
		2144	#endif
		2145	#if IS_ENABLED(CONFIG_HID_PLANTRONICS)
2021	{ HID_USB_DEVICE(USB_VENDOR_ID_PLANTRONICS, HID_ANY_ID) },	2146	{ HID_USB_DEVICE(USB_VENDOR_ID_PLANTRONICS, HID_ANY_ID) },
		2147	#endif
		2148	#if IS_ENABLED(CONFIG_HID_PRIMAX)
2022	{ HID_USB_DEVICE(USB_VENDOR_ID_PRIMAX, USB_DEVICE_ID_PRIMAX_KEYBOARD) },	2149	{ HID_USB_DEVICE(USB_VENDOR_ID_PRIMAX, USB_DEVICE_ID_PRIMAX_KEYBOARD) },
2023	{ HID_USB_DEVICE(USB_VENDOR_ID_RISO_KAGAKU, USB_DEVICE_ID_RI_KA_WEBMAIL) },	2150	#endif
		2151	#if IS_ENABLED(CONFIG_HID_PRODIKEYS)
		2152	{ HID_USB_DEVICE(USB_VENDOR_ID_CREATIVELABS, USB_DEVICE_ID_PRODIKEYS_PCMIDI) },
		2153	#endif
		2154	#if IS_ENABLED(CONFIG_HID_RMI)
		2155	{ HID_USB_DEVICE(USB_VENDOR_ID_LENOVO, USB_DEVICE_ID_LENOVO_X1_COVER) },
		2156	{ HID_USB_DEVICE(USB_VENDOR_ID_RAZER, USB_DEVICE_ID_RAZER_BLADE_14) },
		2157	#endif
2024	#if IS_ENABLED(CONFIG_HID_ROCCAT)	2158	#if IS_ENABLED(CONFIG_HID_ROCCAT)
2025	{ HID_USB_DEVICE(USB_VENDOR_ID_ROCCAT, USB_DEVICE_ID_ROCCAT_ARVO) },	2159	{ HID_USB_DEVICE(USB_VENDOR_ID_ROCCAT, USB_DEVICE_ID_ROCCAT_ARVO) },
2026	{ HID_USB_DEVICE(USB_VENDOR_ID_ROCCAT, USB_DEVICE_ID_ROCCAT_ISKU) },	2160	{ HID_USB_DEVICE(USB_VENDOR_ID_ROCCAT, USB_DEVICE_ID_ROCCAT_ISKU) },
@@ -2048,9 +2182,21 @@ static const struct hid_device_id hid_have_special_driver[] = { · 21 unmodified lines
2048	{ HID_USB_DEVICE(USB_VENDOR_ID_MADCATZ, USB_DEVICE_ID_MADCATZ_RAT5) },	2182	{ HID_USB_DEVICE(USB_VENDOR_ID_MADCATZ, USB_DEVICE_ID_MADCATZ_RAT5) },
2049	{ HID_USB_DEVICE(USB_VENDOR_ID_MADCATZ, USB_DEVICE_ID_MADCATZ_RAT9) },	2183	{ HID_USB_DEVICE(USB_VENDOR_ID_MADCATZ, USB_DEVICE_ID_MADCATZ_RAT9) },
2050	#endif	2184	#endif
		2185	#if IS_ENABLED(CONFIG_HID_SAMSUNG)
2051	{ HID_USB_DEVICE(USB_VENDOR_ID_SAMSUNG, USB_DEVICE_ID_SAMSUNG_IR_REMOTE) },	2186	{ HID_USB_DEVICE(USB_VENDOR_ID_SAMSUNG, USB_DEVICE_ID_SAMSUNG_IR_REMOTE) },
2052	{ HID_USB_DEVICE(USB_VENDOR_ID_SAMSUNG, USB_DEVICE_ID_SAMSUNG_WIRELESS_KBD_MOUSE) },	2187	{ HID_USB_DEVICE(USB_VENDOR_ID_SAMSUNG, USB_DEVICE_ID_SAMSUNG_WIRELESS_KBD_MOUSE) },
2053	{ HID_USB_DEVICE(USB_VENDOR_ID_SKYCABLE, USB_DEVICE_ID_SKYCABLE_WIRELESS_PRESENTER) },	2188	#endif
		2189	#if IS_ENABLED(CONFIG_HID_SMARTJOYPLUS)
		2190	{ HID_USB_DEVICE(USB_VENDOR_ID_PLAYDOTCOM, USB_DEVICE_ID_PLAYDOTCOM_EMS_USBII) },
		2191	{ HID_USB_DEVICE(USB_VENDOR_ID_WISEGROUP, USB_DEVICE_ID_SMARTJOY_PLUS) },
		2192	{ HID_USB_DEVICE(USB_VENDOR_ID_WISEGROUP, USB_DEVICE_ID_SUPER_JOY_BOX_3) },
		2193	{ HID_USB_DEVICE(USB_VENDOR_ID_WISEGROUP, USB_DEVICE_ID_DUAL_USB_JOYPAD) },
		2194	{ HID_USB_DEVICE(USB_VENDOR_ID_WISEGROUP_LTD, USB_DEVICE_ID_SUPER_JOY_BOX_3_PRO) },
		2195	{ HID_USB_DEVICE(USB_VENDOR_ID_WISEGROUP_LTD, USB_DEVICE_ID_SUPER_DUAL_BOX_PRO) },
		2196	{ HID_USB_DEVICE(USB_VENDOR_ID_WISEGROUP_LTD, USB_DEVICE_ID_SUPER_JOY_BOX_5_PRO) },
		2197	#endif
		2198	#if IS_ENABLED(CONFIG_HID_SONY)
		2199	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_PS3) },
2054	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_SMK, USB_DEVICE_ID_SMK_PS3_BDREMOTE) },	2200	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_SMK, USB_DEVICE_ID_SMK_PS3_BDREMOTE) },
2055	{ HID_USB_DEVICE(USB_VENDOR_ID_SONY, USB_DEVICE_ID_SONY_BUZZ_CONTROLLER) },	2201	{ HID_USB_DEVICE(USB_VENDOR_ID_SONY, USB_DEVICE_ID_SONY_BUZZ_CONTROLLER) },
2056	{ HID_USB_DEVICE(USB_VENDOR_ID_SONY, USB_DEVICE_ID_SONY_WIRELESS_BUZZ_CONTROLLER) },	2202	{ HID_USB_DEVICE(USB_VENDOR_ID_SONY, USB_DEVICE_ID_SONY_WIRELESS_BUZZ_CONTROLLER) },
@@ -2069,9 +2215,17 @@ static const struct hid_device_id hid_have_special_driver[] = { · 12 unmodified lines
2069	{ HID_USB_DEVICE(USB_VENDOR_ID_SONY, USB_DEVICE_ID_SONY_VAIO_VGX_MOUSE) },	2215	{ HID_USB_DEVICE(USB_VENDOR_ID_SONY, USB_DEVICE_ID_SONY_VAIO_VGX_MOUSE) },
2070	{ HID_USB_DEVICE(USB_VENDOR_ID_SONY, USB_DEVICE_ID_SONY_VAIO_VGP_MOUSE) },	2216	{ HID_USB_DEVICE(USB_VENDOR_ID_SONY, USB_DEVICE_ID_SONY_VAIO_VGP_MOUSE) },
2071	{ HID_USB_DEVICE(USB_VENDOR_ID_SINO_LITE, USB_DEVICE_ID_SINO_LITE_CONTROLLER) },	2217	{ HID_USB_DEVICE(USB_VENDOR_ID_SINO_LITE, USB_DEVICE_ID_SINO_LITE_CONTROLLER) },
		2218	#endif
		2219	#if IS_ENABLED(CONFIG_HID_SPEEDLINK)
		2220	{ HID_USB_DEVICE(USB_VENDOR_ID_X_TENSIONS, USB_DEVICE_ID_SPEEDLINK_VAD_CEZANNE) },
		2221	#endif
		2222	#if IS_ENABLED(CONFIG_HID_STEELSERIES)
2072	{ HID_USB_DEVICE(USB_VENDOR_ID_STEELSERIES, USB_DEVICE_ID_STEELSERIES_SRWS1) },	2223	{ HID_USB_DEVICE(USB_VENDOR_ID_STEELSERIES, USB_DEVICE_ID_STEELSERIES_SRWS1) },
		2224	#endif
		2225	#if IS_ENABLED(CONFIG_HID_SUNPLUS)
2073	{ HID_USB_DEVICE(USB_VENDOR_ID_SUNPLUS, USB_DEVICE_ID_SUNPLUS_WDESKTOP) },	2226	{ HID_USB_DEVICE(USB_VENDOR_ID_SUNPLUS, USB_DEVICE_ID_SUNPLUS_WDESKTOP) },
2074	{ HID_USB_DEVICE(USB_VENDOR_ID_THINGM, USB_DEVICE_ID_BLINK1) },	2227	#endif
		2228	#if IS_ENABLED(CONFIG_HID_THRUSTMASTER)
2075	{ HID_USB_DEVICE(USB_VENDOR_ID_THRUSTMASTER, 0xb300) },	2229	{ HID_USB_DEVICE(USB_VENDOR_ID_THRUSTMASTER, 0xb300) },
2076	{ HID_USB_DEVICE(USB_VENDOR_ID_THRUSTMASTER, 0xb304) },	2230	{ HID_USB_DEVICE(USB_VENDOR_ID_THRUSTMASTER, 0xb304) },
2077	{ HID_USB_DEVICE(USB_VENDOR_ID_THRUSTMASTER, 0xb323) },	2231	{ HID_USB_DEVICE(USB_VENDOR_ID_THRUSTMASTER, 0xb323) },
@@ -2080,12 +2234,25 @@ static const struct hid_device_id hid_have_special_driver[] = { · 2 unmodified lines
2080	{ HID_USB_DEVICE(USB_VENDOR_ID_THRUSTMASTER, 0xb653) },	2234	{ HID_USB_DEVICE(USB_VENDOR_ID_THRUSTMASTER, 0xb653) },
2081	{ HID_USB_DEVICE(USB_VENDOR_ID_THRUSTMASTER, 0xb654) },	2235	{ HID_USB_DEVICE(USB_VENDOR_ID_THRUSTMASTER, 0xb654) },
2082	{ HID_USB_DEVICE(USB_VENDOR_ID_THRUSTMASTER, 0xb65a) },	2236	{ HID_USB_DEVICE(USB_VENDOR_ID_THRUSTMASTER, 0xb65a) },
		2237	#endif
		2238	#if IS_ENABLED(CONFIG_HID_TIVO)
2083	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_TIVO, USB_DEVICE_ID_TIVO_SLIDE_BT) },	2239	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_TIVO, USB_DEVICE_ID_TIVO_SLIDE_BT) },
2084	{ HID_USB_DEVICE(USB_VENDOR_ID_TIVO, USB_DEVICE_ID_TIVO_SLIDE) },	2240	{ HID_USB_DEVICE(USB_VENDOR_ID_TIVO, USB_DEVICE_ID_TIVO_SLIDE) },
2085	{ HID_USB_DEVICE(USB_VENDOR_ID_TIVO, USB_DEVICE_ID_TIVO_SLIDE_PRO) },	2241	{ HID_USB_DEVICE(USB_VENDOR_ID_TIVO, USB_DEVICE_ID_TIVO_SLIDE_PRO) },
		2242	#endif
		2243	#if IS_ENABLED(CONFIG_HID_TOPSEED)
		2244	{ HID_USB_DEVICE(USB_VENDOR_ID_BTC, USB_DEVICE_ID_BTC_EMPREX_REMOTE) },
		2245	{ HID_USB_DEVICE(USB_VENDOR_ID_BTC, USB_DEVICE_ID_BTC_EMPREX_REMOTE_2) },
		2246	{ HID_USB_DEVICE(USB_VENDOR_ID_CHICONY, USB_DEVICE_ID_CHICONY_WIRELESS) },
2086	{ HID_USB_DEVICE(USB_VENDOR_ID_TOPSEED, USB_DEVICE_ID_TOPSEED_CYBERLINK) },	2247	{ HID_USB_DEVICE(USB_VENDOR_ID_TOPSEED, USB_DEVICE_ID_TOPSEED_CYBERLINK) },
2087	{ HID_USB_DEVICE(USB_VENDOR_ID_TOPSEED2, USB_DEVICE_ID_TOPSEED2_RF_COMBO) },	2248	{ HID_USB_DEVICE(USB_VENDOR_ID_TOPSEED2, USB_DEVICE_ID_TOPSEED2_RF_COMBO) },
		2249	#endif
		2250	#if IS_ENABLED(CONFIG_HID_TWINHAN)
2088	{ HID_USB_DEVICE(USB_VENDOR_ID_TWINHAN, USB_DEVICE_ID_TWINHAN_IR_REMOTE) },	2251	{ HID_USB_DEVICE(USB_VENDOR_ID_TWINHAN, USB_DEVICE_ID_TWINHAN_IR_REMOTE) },
		2252	#endif
		2253	#if IS_ENABLED(CONFIG_HID_UCLOGIC)
		2254	{ HID_USB_DEVICE(USB_VENDOR_ID_HUION, USB_DEVICE_ID_HUION_TABLET) },
		2255	{ HID_USB_DEVICE(USB_VENDOR_ID_UCLOGIC, USB_DEVICE_ID_HUION_TABLET) },
2089	{ HID_USB_DEVICE(USB_VENDOR_ID_UCLOGIC, USB_DEVICE_ID_UCLOGIC_TABLET_PF1209) },	2256	{ HID_USB_DEVICE(USB_VENDOR_ID_UCLOGIC, USB_DEVICE_ID_UCLOGIC_TABLET_PF1209) },
2090	{ HID_USB_DEVICE(USB_VENDOR_ID_UCLOGIC, USB_DEVICE_ID_UCLOGIC_TABLET_WP4030U) },	2257	{ HID_USB_DEVICE(USB_VENDOR_ID_UCLOGIC, USB_DEVICE_ID_UCLOGIC_TABLET_WP4030U) },
2091	{ HID_USB_DEVICE(USB_VENDOR_ID_UCLOGIC, USB_DEVICE_ID_UCLOGIC_TABLET_WP5540U) },	2258	{ HID_USB_DEVICE(USB_VENDOR_ID_UCLOGIC, USB_DEVICE_ID_UCLOGIC_TABLET_WP5540U) },
@@ -2093,20 +2260,17 @@ static const struct hid_device_id hid_have_special_driver[] = { · 1 unmodified line
2093	{ HID_USB_DEVICE(USB_VENDOR_ID_UCLOGIC, USB_DEVICE_ID_UCLOGIC_TABLET_WP1062) },	2260	{ HID_USB_DEVICE(USB_VENDOR_ID_UCLOGIC, USB_DEVICE_ID_UCLOGIC_TABLET_WP1062) },
2094	{ HID_USB_DEVICE(USB_VENDOR_ID_UCLOGIC, USB_DEVICE_ID_UCLOGIC_WIRELESS_TABLET_TWHL850) },	2261	{ HID_USB_DEVICE(USB_VENDOR_ID_UCLOGIC, USB_DEVICE_ID_UCLOGIC_WIRELESS_TABLET_TWHL850) },
2095	{ HID_USB_DEVICE(USB_VENDOR_ID_UCLOGIC, USB_DEVICE_ID_UCLOGIC_TABLET_TWHA60) },	2262	{ HID_USB_DEVICE(USB_VENDOR_ID_UCLOGIC, USB_DEVICE_ID_UCLOGIC_TABLET_TWHA60) },
2096	{ HID_USB_DEVICE(USB_VENDOR_ID_THQ, USB_DEVICE_ID_THQ_PS3_UDRAW) },
2097	{ HID_USB_DEVICE(USB_VENDOR_ID_UCLOGIC, USB_DEVICE_ID_YIYNOVA_TABLET) },	2263	{ HID_USB_DEVICE(USB_VENDOR_ID_UCLOGIC, USB_DEVICE_ID_YIYNOVA_TABLET) },
2098	{ HID_USB_DEVICE(USB_VENDOR_ID_UCLOGIC, USB_DEVICE_ID_UGEE_TABLET_81) },	2264	{ HID_USB_DEVICE(USB_VENDOR_ID_UCLOGIC, USB_DEVICE_ID_UGEE_TABLET_81) },
2099	{ HID_USB_DEVICE(USB_VENDOR_ID_UCLOGIC, USB_DEVICE_ID_UGEE_TABLET_45) },	2265	{ HID_USB_DEVICE(USB_VENDOR_ID_UCLOGIC, USB_DEVICE_ID_UGEE_TABLET_45) },
2100	{ HID_USB_DEVICE(USB_VENDOR_ID_UCLOGIC, USB_DEVICE_ID_UCLOGIC_DRAWIMAGE_G3) },	2266	{ HID_USB_DEVICE(USB_VENDOR_ID_UCLOGIC, USB_DEVICE_ID_UCLOGIC_DRAWIMAGE_G3) },
2101	{ HID_USB_DEVICE(USB_VENDOR_ID_UGTIZER, USB_DEVICE_ID_UGTIZER_TABLET_GP0610) },
2102	{ HID_USB_DEVICE(USB_VENDOR_ID_UGEE, USB_DEVICE_ID_UGEE_TABLET_EX07S) },	2267	{ HID_USB_DEVICE(USB_VENDOR_ID_UGEE, USB_DEVICE_ID_UGEE_TABLET_EX07S) },
2103	{ HID_USB_DEVICE(USB_VENDOR_ID_WISEGROUP, USB_DEVICE_ID_SMARTJOY_PLUS) },	2268	{ HID_USB_DEVICE(USB_VENDOR_ID_UGTIZER, USB_DEVICE_ID_UGTIZER_TABLET_GP0610) },
2104	{ HID_USB_DEVICE(USB_VENDOR_ID_WISEGROUP, USB_DEVICE_ID_SUPER_JOY_BOX_3) },	2269	#endif
2105	{ HID_USB_DEVICE(USB_VENDOR_ID_WISEGROUP, USB_DEVICE_ID_DUAL_USB_JOYPAD) },	2270	#if IS_ENABLED(CONFIG_HID_UDRAW_PS3)
2106	{ HID_USB_DEVICE(USB_VENDOR_ID_WISEGROUP_LTD, USB_DEVICE_ID_SUPER_JOY_BOX_3_PRO) },	2271	{ HID_USB_DEVICE(USB_VENDOR_ID_THQ, USB_DEVICE_ID_THQ_PS3_UDRAW) },
2107	{ HID_USB_DEVICE(USB_VENDOR_ID_WISEGROUP_LTD, USB_DEVICE_ID_SUPER_DUAL_BOX_PRO) },	2272	#endif
2108	{ HID_USB_DEVICE(USB_VENDOR_ID_WISEGROUP_LTD, USB_DEVICE_ID_SUPER_JOY_BOX_5_PRO) },	2273	#if IS_ENABLED(CONFIG_HID_WALTOP)
2109	{ HID_USB_DEVICE(USB_VENDOR_ID_PLAYDOTCOM, USB_DEVICE_ID_PLAYDOTCOM_EMS_USBII) },
2110	{ HID_USB_DEVICE(USB_VENDOR_ID_WALTOP, USB_DEVICE_ID_WALTOP_SLIM_TABLET_5_8_INCH) },	2274	{ HID_USB_DEVICE(USB_VENDOR_ID_WALTOP, USB_DEVICE_ID_WALTOP_SLIM_TABLET_5_8_INCH) },
2111	{ HID_USB_DEVICE(USB_VENDOR_ID_WALTOP, USB_DEVICE_ID_WALTOP_SLIM_TABLET_12_1_INCH) },	2275	{ HID_USB_DEVICE(USB_VENDOR_ID_WALTOP, USB_DEVICE_ID_WALTOP_SLIM_TABLET_12_1_INCH) },
2112	{ HID_USB_DEVICE(USB_VENDOR_ID_WALTOP, USB_DEVICE_ID_WALTOP_Q_PAD) },	2276	{ HID_USB_DEVICE(USB_VENDOR_ID_WALTOP, USB_DEVICE_ID_WALTOP_Q_PAD) },
@@ -2114,19 +2278,18 @@ static const struct hid_device_id hid_have_special_driver[] = { · 1 unmodified line
2114	{ HID_USB_DEVICE(USB_VENDOR_ID_WALTOP, USB_DEVICE_ID_WALTOP_MEDIA_TABLET_10_6_INCH) },	2278	{ HID_USB_DEVICE(USB_VENDOR_ID_WALTOP, USB_DEVICE_ID_WALTOP_MEDIA_TABLET_10_6_INCH) },
2115	{ HID_USB_DEVICE(USB_VENDOR_ID_WALTOP, USB_DEVICE_ID_WALTOP_MEDIA_TABLET_14_1_INCH) },	2279	{ HID_USB_DEVICE(USB_VENDOR_ID_WALTOP, USB_DEVICE_ID_WALTOP_MEDIA_TABLET_14_1_INCH) },
2116	{ HID_USB_DEVICE(USB_VENDOR_ID_WALTOP, USB_DEVICE_ID_WALTOP_SIRIUS_BATTERY_FREE_TABLET) },	2280	{ HID_USB_DEVICE(USB_VENDOR_ID_WALTOP, USB_DEVICE_ID_WALTOP_SIRIUS_BATTERY_FREE_TABLET) },
2117	{ HID_USB_DEVICE(USB_VENDOR_ID_X_TENSIONS, USB_DEVICE_ID_SPEEDLINK_VAD_CEZANNE) },	2281	#endif
		2282	#if IS_ENABLED(CONFIG_HID_XINMO)
2118	{ HID_USB_DEVICE(USB_VENDOR_ID_XIN_MO, USB_DEVICE_ID_XIN_MO_DUAL_ARCADE) },	2283	{ HID_USB_DEVICE(USB_VENDOR_ID_XIN_MO, USB_DEVICE_ID_XIN_MO_DUAL_ARCADE) },
2119	{ HID_USB_DEVICE(USB_VENDOR_ID_XIN_MO, USB_DEVICE_ID_THT_2P_ARCADE) },	2284	{ HID_USB_DEVICE(USB_VENDOR_ID_XIN_MO, USB_DEVICE_ID_THT_2P_ARCADE) },
		2285	#endif
		2286	#if IS_ENABLED(CONFIG_HID_ZEROPLUS)
2120	{ HID_USB_DEVICE(USB_VENDOR_ID_ZEROPLUS, 0x0005) },	2287	{ HID_USB_DEVICE(USB_VENDOR_ID_ZEROPLUS, 0x0005) },
2121	{ HID_USB_DEVICE(USB_VENDOR_ID_ZEROPLUS, 0x0030) },	2288	{ HID_USB_DEVICE(USB_VENDOR_ID_ZEROPLUS, 0x0030) },
		2289	#endif
		2290	#if IS_ENABLED(CONFIG_HID_ZYDACRON)
2122	{ HID_USB_DEVICE(USB_VENDOR_ID_ZYDACRON, USB_DEVICE_ID_ZYDACRON_REMOTE_CONTROL) },	2291	{ HID_USB_DEVICE(USB_VENDOR_ID_ZYDACRON, USB_DEVICE_ID_ZYDACRON_REMOTE_CONTROL) },
2123		2292	#endif
2124	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_PRESENTER_8K_BT) },
2125	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_NINTENDO, USB_DEVICE_ID_NINTENDO_WIIMOTE) },
2126	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_NINTENDO, USB_DEVICE_ID_NINTENDO_WIIMOTE2) },
2127	{ HID_USB_DEVICE(USB_VENDOR_ID_RAZER, USB_DEVICE_ID_RAZER_BLADE_14) },
2128	{ HID_USB_DEVICE(USB_VENDOR_ID_CMEDIA, USB_DEVICE_ID_CM6533) },
2129	{ HID_USB_DEVICE(USB_VENDOR_ID_LENOVO, USB_DEVICE_ID_LENOVO_X1_COVER) },
2130	{ }	2293	{ }
2131	};	2294	};
2132		2295

drivers/hid/hid-elecom.c+53−9

@@ -1,10 +1,8 @@
1	/*	1	/*
2	* HID driver for Elecom BM084 (bluetooth mouse).	2	* HID driver for ELECOM devices.
3	* Removes a non-existing horizontal wheel from
4	* the HID descriptor.
5	* (This module is based on "hid-ortek".)
6	*
7	* Copyright (c) 2010 Richard Nauber <Richard.Nauber@gmail.com>	3	* Copyright (c) 2010 Richard Nauber <Richard.Nauber@gmail.com>
		4	* Copyright (c) 2016 Yuxuan Shui <yshuiv7@gmail.com>
		5	* Copyright (c) 2017 Diego Elio Pettenò <flameeyes@flameeyes.eu>
8	*/	6	*/
9		7
10	/*	8	/*
@@ -23,15 +21,61 @@ · 12 unmodified lines
23	static __u8 elecom_report_fixup(struct hid_device hdev, __u8 *rdesc,	21	static __u8 elecom_report_fixup(struct hid_device hdev, __u8 *rdesc,
24	unsigned int *rsize)	22	unsigned int *rsize)
25	{	23	{
26	if (*rsize >= 48 && rdesc[46] == 0x05 && rdesc[47] == 0x0c) {	24	switch (hdev->product) {
27	hid_info(hdev, "Fixing up Elecom BM084 report descriptor\n");	25	case USB_DEVICE_ID_ELECOM_BM084:
28	rdesc[47] = 0x00;	26	/* The BM084 Bluetooth mouse includes a non-existing horizontal
		27	* wheel in the HID descriptor. */
		28	if (*rsize >= 48 && rdesc[46] == 0x05 && rdesc[47] == 0x0c) {
		29	hid_info(hdev, "Fixing up Elecom BM084 report descriptor\n");
		30	rdesc[47] = 0x00;
		31	}
		32	break;
		33	case USB_DEVICE_ID_ELECOM_DEFT_WIRED:
		34	case USB_DEVICE_ID_ELECOM_DEFT_WIRELESS:
		35	/* The DEFT trackball has eight buttons, but its descriptor only
		36	* reports five, disabling the three Fn buttons on the top of
		37	* the mouse.
		38	*
		39	* Apply the following diff to the descriptor:
		40	*
		41	* Collection (Physical), Collection (Physical),
		42	* Report ID (1), Report ID (1),
		43	* Report Count (5), -> Report Count (8),
		44	* Report Size (1), Report Size (1),
		45	* Usage Page (Button), Usage Page (Button),
		46	* Usage Minimum (01h), Usage Minimum (01h),
		47	* Usage Maximum (05h), -> Usage Maximum (08h),
		48	* Logical Minimum (0), Logical Minimum (0),
		49	* Logical Maximum (1), Logical Maximum (1),
		50	* Input (Variable), Input (Variable),
		51	* Report Count (1), -> Report Count (0),
		52	* Report Size (3), Report Size (3),
		53	* Input (Constant), Input (Constant),
		54	* Report Size (16), Report Size (16),
		55	* Report Count (2), Report Count (2),
		56	* Usage Page (Desktop), Usage Page (Desktop),
		57	* Usage (X), Usage (X),
		58	* Usage (Y), Usage (Y),
		59	* Logical Minimum (-32768), Logical Minimum (-32768),
		60	* Logical Maximum (32767), Logical Maximum (32767),
		61	* Input (Variable, Relative), Input (Variable, Relative),
		62	* End Collection, End Collection,
		63	*/
		64	if (*rsize == 213 && rdesc[13] == 5 && rdesc[21] == 5) {
		65	hid_info(hdev, "Fixing up Elecom DEFT Fn buttons\n");
		66	rdesc[13] = 8; /* Button/Variable Report Count */
		67	rdesc[21] = 8; /* Button/Variable Usage Maximum */
		68	rdesc[29] = 0; /* Button/Constant Report Count */
		69	}
		70	break;
29	}	71	}
30	return rdesc;	72	return rdesc;
31	}	73	}
32		74
33	static const struct hid_device_id elecom_devices[] = {	75	static const struct hid_device_id elecom_devices[] = {
34	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_ELECOM, USB_DEVICE_ID_ELECOM_BM084)},	76	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_ELECOM, USB_DEVICE_ID_ELECOM_BM084) },
		77	{ HID_USB_DEVICE(USB_VENDOR_ID_ELECOM, USB_DEVICE_ID_ELECOM_DEFT_WIRED) },
		78	{ HID_USB_DEVICE(USB_VENDOR_ID_ELECOM, USB_DEVICE_ID_ELECOM_DEFT_WIRELESS) },
35	{ }	79	{ }
36	};	80	};
37	MODULE_DEVICE_TABLE(hid, elecom_devices);	81	MODULE_DEVICE_TABLE(hid, elecom_devices);

drivers/hid/hid-ids.h+3−0

 #define USB_VENDOR_ID_ASUSTEK		0x0b05
 #define USB_DEVICE_ID_ASUSTEK_LCM	0x1726
 #define USB_DEVICE_ID_ASUSTEK_LCM2	0x175b
+#define USB_DEVICE_ID_ASUSTEK_T100_KEYBOARD	0x17e0
 #define USB_DEVICE_ID_ASUSTEK_I2C_KEYBOARD	0x8585
 #define USB_DEVICE_ID_ASUSTEK_I2C_TOUCHPAD	0x0101
 #define USB_DEVICE_ID_ASUSTEK_ROG_KEYBOARD1 0x1854
 #define USB_VENDOR_ID_ELECOM		0x056e
 #define USB_DEVICE_ID_ELECOM_BM084	0x0061
+#define USB_DEVICE_ID_ELECOM_DEFT_WIRED	0x00fe
+#define USB_DEVICE_ID_ELECOM_DEFT_WIRELESS	0x00ff
 #define USB_VENDOR_ID_DREAM_CHEEKY	0x1d34
 #define USB_DEVICE_ID_DREAM_CHEEKY_WN	0x0004

drivers/hid/hid-magicmouse.c+8−7

 	if (input->id.product == USB_DEVICE_ID_APPLE_MAGICMOUSE) {
 		magicmouse_emit_buttons(msc, clicks & 3);
+		input_mt_report_pointer_emulation(input, true);
 		input_report_rel(input, REL_X, x);
 		input_report_rel(input, REL_Y, y);
 	} else { /* USB_DEVICE_ID_APPLE_MAGICTRACKPAD */
 		__clear_bit(BTN_RIGHT, input->keybit);
 		__clear_bit(BTN_MIDDLE, input->keybit);
 		__set_bit(BTN_MOUSE, input->keybit);
-		__set_bit(BTN_TOOL_FINGER, input->keybit);
-		__set_bit(BTN_TOOL_DOUBLETAP, input->keybit);
-		__set_bit(BTN_TOOL_TRIPLETAP, input->keybit);
-		__set_bit(BTN_TOOL_QUADTAP, input->keybit);
-		__set_bit(BTN_TOOL_QUINTTAP, input->keybit);
-		__set_bit(BTN_TOUCH, input->keybit);
-		__set_bit(INPUT_PROP_POINTER, input->propbit);
 		__set_bit(INPUT_PROP_BUTTONPAD, input->propbit);
 	}
+	__set_bit(BTN_TOOL_FINGER, input->keybit);
+	__set_bit(BTN_TOOL_DOUBLETAP, input->keybit);
+	__set_bit(BTN_TOOL_TRIPLETAP, input->keybit);
+	__set_bit(BTN_TOOL_QUADTAP, input->keybit);
+	__set_bit(BTN_TOOL_QUINTTAP, input->keybit);
+	__set_bit(BTN_TOUCH, input->keybit);
+	__set_bit(INPUT_PROP_POINTER, input->propbit);
 	__set_bit(EV_ABS, input->evbit);

drivers/hid/i2c-hid/i2c-hid.c+13−0

 	return 0;
 }
+static void i2c_hid_acpi_fix_up_power(struct device *dev)
+{
+	acpi_handle handle = ACPI_HANDLE(dev);
+	struct acpi_device *adev;
+	if (handle && acpi_bus_get_device(handle, &adev) == 0)
+		acpi_device_fix_up_power(adev);
+}
 static const struct acpi_device_id i2c_hid_acpi_match[] = {
 	{"ACPI0C50", 0 },
 	{"PNP0C50", 0 },
 {
 	return -ENODEV;
 }
+static inline void i2c_hid_acpi_fix_up_power(struct device *dev) {}
 #endif
 #ifdef CONFIG_OF
 	if (ret < 0)
 		goto err_regulator;
+	i2c_hid_acpi_fix_up_power(&client->dev);
 	pm_runtime_get_noresume(&client->dev);
 	pm_runtime_set_active(&client->dev);
 	pm_runtime_enable(&client->dev);

drivers/hid/wacom_wac.c+23−22

@@ -1571,37 +1571,38 @@ static int wacom_tpc_irq(struct wacom_wac *wacom, size_t len) · 1570 unmodified lines
1571	{	1571	{
1572	unsigned char *data = wacom->data;	1572	unsigned char *data = wacom->data;
1573		1573
1574	if (wacom->pen_input)	1574	if (wacom->pen_input) {
1575	dev_dbg(wacom->pen_input->dev.parent,	1575	dev_dbg(wacom->pen_input->dev.parent,
1576	"%s: received report #%d\n", __func__, data[0]);	1576	"%s: received report #%d\n", __func__, data[0]);
1577	else if (wacom->touch_input)	1577
		1578	if (len == WACOM_PKGLEN_PENABLED \|\|
		1579	data[0] == WACOM_REPORT_PENABLED)
		1580	return wacom_tpc_pen(wacom);
		1581	}
		1582	else if (wacom->touch_input) {
1578	dev_dbg(wacom->touch_input->dev.parent,	1583	dev_dbg(wacom->touch_input->dev.parent,
1579	"%s: received report #%d\n", __func__, data[0]);	1584	"%s: received report #%d\n", __func__, data[0]);
1580		1585
1581	switch (len) {	1586	switch (len) {
1582	case WACOM_PKGLEN_TPC1FG:	1587	case WACOM_PKGLEN_TPC1FG:
1583	return wacom_tpc_single_touch(wacom, len);	1588	return wacom_tpc_single_touch(wacom, len);
1584		1589
1585	case WACOM_PKGLEN_TPC2FG:	1590	case WACOM_PKGLEN_TPC2FG:
1586	return wacom_tpc_mt_touch(wacom);	1591	return wacom_tpc_mt_touch(wacom);
1587		1592
1588	case WACOM_PKGLEN_PENABLED:	1593	default:
1589	return wacom_tpc_pen(wacom);	1594	switch (data[0]) {
		1595	case WACOM_REPORT_TPC1FG:
		1596	case WACOM_REPORT_TPCHID:
		1597	case WACOM_REPORT_TPCST:
		1598	case WACOM_REPORT_TPC1FGE:
		1599	return wacom_tpc_single_touch(wacom, len);
1590		1600
1591	default:	1601	case WACOM_REPORT_TPCMT:
1592	switch (data[0]) {	1602	case WACOM_REPORT_TPCMT2:
1593	case WACOM_REPORT_TPC1FG:	1603	return wacom_mt_touch(wacom);
1594	case WACOM_REPORT_TPCHID:
1595	case WACOM_REPORT_TPCST:
1596	case WACOM_REPORT_TPC1FGE:
1597	return wacom_tpc_single_touch(wacom, len);
1598
1599	case WACOM_REPORT_TPCMT:
1600	case WACOM_REPORT_TPCMT2:
1601	return wacom_mt_touch(wacom);
1602		1604
1603	case WACOM_REPORT_PENABLED:	1605	}
1604	return wacom_tpc_pen(wacom);
1605	}	1606	}
1606	}	1607	}
1607		1608

drivers/hsi/clients/ssi_protocol.c+1−1

@@ -1066,7 +1066,7 @@ static void ssip_pn_setup(struct net_device *dev) · 1065 unmodified lines
1066	dev->addr_len = 1;	1066	dev->addr_len = 1;
1067	dev->tx_queue_len = SSIP_TXQUEUE_LEN;	1067	dev->tx_queue_len = SSIP_TXQUEUE_LEN;
1068		1068
1069	dev->destructor = free_netdev;	1069	dev->needs_free_netdev = true;
1070	dev->header_ops = &phonet_header_ops;	1070	dev->header_ops = &phonet_header_ops;
1071	}	1071	}
1072		1072

drivers/hwmon/Kconfig+1−0

@@ -343,6 +343,7 @@ config SENSORS_ASB100 · 342 unmodified lines
343		343
344	config SENSORS_ASPEED	344	config SENSORS_ASPEED
345	tristate "ASPEED AST2400/AST2500 PWM and Fan tach driver"	345	tristate "ASPEED AST2400/AST2500 PWM and Fan tach driver"
		346	select REGMAP
346	help	347	help
347	This driver provides support for ASPEED AST2400/AST2500 PWM	348	This driver provides support for ASPEED AST2400/AST2500 PWM
348	and Fan Tacho controllers.	349	and Fan Tacho controllers.

drivers/hwmon/aspeed-pwm-tacho.c+35−30

  */
 #include <linux/clk.h>
+#include <linux/errno.h>
 #include <linux/gpio/consumer.h>
 #include <linux/delay.h>
 #include <linux/hwmon.h>
 	return clk / (clk_unit * div_h * div_l * tacho_div * tacho_unit);
 }
-static u32 aspeed_get_fan_tach_ch_rpm(struct aspeed_pwm_tacho_data *priv,
+static int aspeed_get_fan_tach_ch_rpm(struct aspeed_pwm_tacho_data *priv,
 				      u8 fan_tach_ch)
 {
 	u32 raw_data, tach_div, clk_source, sec, val;
 	msleep(sec);
 	regmap_read(priv->regmap, ASPEED_PTCR_RESULT, &val);
+	if (!(val & RESULT_STATUS_MASK))
+		return -ETIMEDOUT;
 	raw_data = val & RESULT_VALUE_MASK;
 	tach_div = priv->type_fan_tach_clock_division[type];
 	tach_div = 0x4 << (tach_div * 2);
 {
 	struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
 	int index = sensor_attr->index;
-	u32 rpm;
+	int rpm;
 	struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev);
 	rpm = aspeed_get_fan_tach_ch_rpm(priv, index);
+	if (rpm < 0)
+		return rpm;
-	return sprintf(buf, "%u\n", rpm);
+	return sprintf(buf, "%d\n", rpm);
 }
 static umode_t pwm_is_visible(struct kobject *kobj,
 	return a->mode;
 }
-static SENSOR_DEVICE_ATTR(pwm0, 0644,
-			show_pwm, set_pwm, 0);
 static SENSOR_DEVICE_ATTR(pwm1, 0644,
-			show_pwm, set_pwm, 1);
+			show_pwm, set_pwm, 0);
 static SENSOR_DEVICE_ATTR(pwm2, 0644,
-			show_pwm, set_pwm, 2);
+			show_pwm, set_pwm, 1);
 static SENSOR_DEVICE_ATTR(pwm3, 0644,
-			show_pwm, set_pwm, 3);
+			show_pwm, set_pwm, 2);
 static SENSOR_DEVICE_ATTR(pwm4, 0644,
-			show_pwm, set_pwm, 4);
+			show_pwm, set_pwm, 3);
 static SENSOR_DEVICE_ATTR(pwm5, 0644,
-			show_pwm, set_pwm, 5);
+			show_pwm, set_pwm, 4);
 static SENSOR_DEVICE_ATTR(pwm6, 0644,
-			show_pwm, set_pwm, 6);
+			show_pwm, set_pwm, 5);
 static SENSOR_DEVICE_ATTR(pwm7, 0644,
+			show_pwm, set_pwm, 6);
+static SENSOR_DEVICE_ATTR(pwm8, 0644,
 			show_pwm, set_pwm, 7);
 static struct attribute *pwm_dev_attrs[] = {
-	&sensor_dev_attr_pwm0.dev_attr.attr,
 	&sensor_dev_attr_pwm1.dev_attr.attr,
 	&sensor_dev_attr_pwm2.dev_attr.attr,
 	&sensor_dev_attr_pwm3.dev_attr.attr,
 	&sensor_dev_attr_pwm5.dev_attr.attr,
 	&sensor_dev_attr_pwm6.dev_attr.attr,
 	&sensor_dev_attr_pwm7.dev_attr.attr,
+	&sensor_dev_attr_pwm8.dev_attr.attr,
 	NULL,
 };
 	.is_visible = pwm_is_visible,
 };
-static SENSOR_DEVICE_ATTR(fan0_input, 0444,
-		show_rpm, NULL, 0);
 static SENSOR_DEVICE_ATTR(fan1_input, 0444,
-		show_rpm, NULL, 1);
+		show_rpm, NULL, 0);
 static SENSOR_DEVICE_ATTR(fan2_input, 0444,
-		show_rpm, NULL, 2);
+		show_rpm, NULL, 1);
 static SENSOR_DEVICE_ATTR(fan3_input, 0444,
-		show_rpm, NULL, 3);
+		show_rpm, NULL, 2);
 static SENSOR_DEVICE_ATTR(fan4_input, 0444,
-		show_rpm, NULL, 4);
+		show_rpm, NULL, 3);
 static SENSOR_DEVICE_ATTR(fan5_input, 0444,
-		show_rpm, NULL, 5);
+		show_rpm, NULL, 4);
 static SENSOR_DEVICE_ATTR(fan6_input, 0444,
-		show_rpm, NULL, 6);
+		show_rpm, NULL, 5);
 static SENSOR_DEVICE_ATTR(fan7_input, 0444,
-		show_rpm, NULL, 7);
+		show_rpm, NULL, 6);
 static SENSOR_DEVICE_ATTR(fan8_input, 0444,
-		show_rpm, NULL, 8);
+		show_rpm, NULL, 7);
 static SENSOR_DEVICE_ATTR(fan9_input, 0444,
-		show_rpm, NULL, 9);
+		show_rpm, NULL, 8);
 static SENSOR_DEVICE_ATTR(fan10_input, 0444,
-		show_rpm, NULL, 10);
+		show_rpm, NULL, 9);
 static SENSOR_DEVICE_ATTR(fan11_input, 0444,
-		show_rpm, NULL, 11);
+		show_rpm, NULL, 10);
 static SENSOR_DEVICE_ATTR(fan12_input, 0444,
-		show_rpm, NULL, 12);
+		show_rpm, NULL, 11);
 static SENSOR_DEVICE_ATTR(fan13_input, 0444,
-		show_rpm, NULL, 13);
+		show_rpm, NULL, 12);
 static SENSOR_DEVICE_ATTR(fan14_input, 0444,
-		show_rpm, NULL, 14);
+		show_rpm, NULL, 13);
 static SENSOR_DEVICE_ATTR(fan15_input, 0444,
+		show_rpm, NULL, 14);
+static SENSOR_DEVICE_ATTR(fan16_input, 0444,
 		show_rpm, NULL, 15);
 static struct attribute *fan_dev_attrs[] = {
-	&sensor_dev_attr_fan0_input.dev_attr.attr,
 	&sensor_dev_attr_fan1_input.dev_attr.attr,
 	&sensor_dev_attr_fan2_input.dev_attr.attr,
 	&sensor_dev_attr_fan3_input.dev_attr.attr,
 	&sensor_dev_attr_fan13_input.dev_attr.attr,
 	&sensor_dev_attr_fan14_input.dev_attr.attr,
 	&sensor_dev_attr_fan15_input.dev_attr.attr,
+	&sensor_dev_attr_fan16_input.dev_attr.attr,
 	NULL
 };
 		if (ret)
 			return ret;
 	}
-	of_node_put(np);
 	priv->groups[0] = &pwm_dev_group;
 	priv->groups[1] = &fan_dev_group;

drivers/i2c/busses/i2c-ismt.c+1−1

@@ -584,7 +584,7 @@ static int ismt_access(struct i2c_adapter *adap, u16 addr, · 583 unmodified lines
584		584
585	/* unmap the data buffer */	585	/* unmap the data buffer */
586	if (dma_size != 0)	586	if (dma_size != 0)
587	dma_unmap_single(&adap->dev, dma_addr, dma_size, dma_direction);	587	dma_unmap_single(dev, dma_addr, dma_size, dma_direction);
588		588
589	if (unlikely(!time_left)) {	589	if (unlikely(!time_left)) {
590	dev_err(dev, "completion wait timed out\n");	590	dev_err(dev, "completion wait timed out\n");

drivers/i2c/busses/i2c-rcar.c+1−1

@@ -319,7 +319,7 @@ static void rcar_i2c_dma_unmap(struct rcar_i2c_priv *priv) · 318 unmodified lines
319	rcar_i2c_write(priv, ICFBSCR, TCYC06);	319	rcar_i2c_write(priv, ICFBSCR, TCYC06);
320		320
321	dma_unmap_single(chan->device->dev, sg_dma_address(&priv->sg),	321	dma_unmap_single(chan->device->dev, sg_dma_address(&priv->sg),
322	priv->msg->len, priv->dma_direction);	322	sg_dma_len(&priv->sg), priv->dma_direction);
323		323
324	priv->dma_direction = DMA_NONE;	324	priv->dma_direction = DMA_NONE;
325	}	325	}

drivers/iio/adc/bcm_iproc_adc.c+4−4

 	iproc_adc_dbg_reg(dev, adc_priv, IPROC_SOFT_BYPASS_DATA);
 }
-static irqreturn_t iproc_adc_interrupt_handler(int irq, void *data)
+static irqreturn_t iproc_adc_interrupt_thread(int irq, void *data)
 {
 	u32 channel_intr_status;
 	u32 intr_status;
 	return IRQ_NONE;
 }
-static irqreturn_t iproc_adc_interrupt_thread(int irq, void *data)
+static irqreturn_t iproc_adc_interrupt_handler(int irq, void *data)
 {
 	irqreturn_t retval = IRQ_NONE;
 	struct iproc_adc_priv *adc_priv;
 	adc_priv = iio_priv(indio_dev);
 	regmap_read(adc_priv->regmap, IPROC_INTERRUPT_STATUS, &intr_status);
-	dev_dbg(&indio_dev->dev, "iproc_adc_interrupt_thread(),INTRPT_STS:%x\n",
+	dev_dbg(&indio_dev->dev, "iproc_adc_interrupt_handler(),INTRPT_STS:%x\n",
 			intr_status);
 	intr_channels = (intr_status & IPROC_ADC_INTR_MASK) >> IPROC_ADC_INTR;
 	}
 	ret = devm_request_threaded_irq(&pdev->dev, adc_priv->irqno,
-				iproc_adc_interrupt_thread,
 				iproc_adc_interrupt_handler,
+				iproc_adc_interrupt_thread,
 				IRQF_SHARED, "iproc-adc", indio_dev);
 	if (ret) {
 		dev_err(&pdev->dev, "request_irq error %d\n", ret);

drivers/iio/adc/max9611.c+5−5

@@ -438,10 +438,10 @@ static ssize_t max9611_shunt_resistor_show(struct device *dev, · 437 unmodified lines
438	struct max9611_dev *max9611 = iio_priv(dev_to_iio_dev(dev));	438	struct max9611_dev *max9611 = iio_priv(dev_to_iio_dev(dev));
439	unsigned int i, r;	439	unsigned int i, r;
440		440
441	i = max9611->shunt_resistor_uohm / 1000;	441	i = max9611->shunt_resistor_uohm / 1000000;
442	r = max9611->shunt_resistor_uohm % 1000;	442	r = max9611->shunt_resistor_uohm % 1000000;
443		443
444	return sprintf(buf, "%u.%03u\n", i, r);	444	return sprintf(buf, "%u.%06u\n", i, r);
445	}	445	}
446		446
447	static IIO_DEVICE_ATTR(in_power_shunt_resistor, 0444,	447	static IIO_DEVICE_ATTR(in_power_shunt_resistor, 0444,
@@ -536,8 +536,8 @@ static int max9611_probe(struct i2c_client *client, · 88 unmodified lines
536	int ret;	536	int ret;
537		537
538	indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*max9611));	538	indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*max9611));
539	if (IS_ERR(indio_dev))	539	if (!indio_dev)
540	return PTR_ERR(indio_dev);	540	return -ENOMEM;
541		541
542	i2c_set_clientdata(client, indio_dev);	542	i2c_set_clientdata(client, indio_dev);
543		543

drivers/iio/adc/meson_saradc.c+2−2

@@ -468,13 +468,13 @@ static void meson_sar_adc_unlock(struct iio_dev *indio_dev) · 467 unmodified lines
468	static void meson_sar_adc_clear_fifo(struct iio_dev *indio_dev)	468	static void meson_sar_adc_clear_fifo(struct iio_dev *indio_dev)
469	{	469	{
470	struct meson_sar_adc_priv *priv = iio_priv(indio_dev);	470	struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
471	int count;	471	unsigned int count, tmp;
472		472
473	for (count = 0; count < MESON_SAR_ADC_MAX_FIFO_SIZE; count++) {	473	for (count = 0; count < MESON_SAR_ADC_MAX_FIFO_SIZE; count++) {
474	if (!meson_sar_adc_get_fifo_count(indio_dev))	474	if (!meson_sar_adc_get_fifo_count(indio_dev))
475	break;	475	break;
476		476
477	regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, 0);	477	regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, &tmp);
478	}	478	}
479	}	479	}
480		480

drivers/iio/adc/mxs-lradc-adc.c+5−2

 	adc->dev = dev;
 	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!iores)
+		return -EINVAL;
 	adc->base = devm_ioremap(dev, iores->start, resource_size(iores));
-	if (IS_ERR(adc->base))
+	if (!adc->base)
-		return PTR_ERR(adc->base);
+		return -ENOMEM;
 	init_completion(&adc->completion);
 	spin_lock_init(&adc->lock);

drivers/iio/adc/sun4i-gpadc-iio.c+24−14

@@ -105,6 +105,8 @@ struct sun4i_gpadc_iio { · 104 unmodified lines
105	bool no_irq;	105	bool no_irq;
106	/* prevents concurrent reads of temperature and ADC */	106	/* prevents concurrent reads of temperature and ADC */
107	struct mutex mutex;	107	struct mutex mutex;
		108	struct thermal_zone_device *tzd;
		109	struct device *sensor_device;
108	};	110	};
109		111
110	#define SUN4I_GPADC_ADC_CHANNEL(_channel, _name) { \	112	#define SUN4I_GPADC_ADC_CHANNEL(_channel, _name) { \
@@ -502,7 +504,6 @@ static int sun4i_gpadc_probe_dt(struct platform_device *pdev, · 391 unmodified lines
502	{	504	{
503	struct sun4i_gpadc_iio *info = iio_priv(indio_dev);	505	struct sun4i_gpadc_iio *info = iio_priv(indio_dev);
504	const struct of_device_id *of_dev;	506	const struct of_device_id *of_dev;
505	struct thermal_zone_device *tzd;
506	struct resource *mem;	507	struct resource *mem;
507	void __iomem *base;	508	void __iomem *base;
508	int ret;	509	int ret;
@@ -532,13 +533,14 @@ static int sun4i_gpadc_probe_dt(struct platform_device *pdev, · 23 unmodified lines
532	if (!IS_ENABLED(CONFIG_THERMAL_OF))	533	if (!IS_ENABLED(CONFIG_THERMAL_OF))
533	return 0;	534	return 0;
534		535
535	tzd = devm_thermal_zone_of_sensor_register(&pdev->dev, 0, info,	536	info->sensor_device = &pdev->dev;
536	&sun4i_ts_tz_ops);	537	info->tzd = thermal_zone_of_sensor_register(info->sensor_device, 0,
537	if (IS_ERR(tzd))	538	info, &sun4i_ts_tz_ops);
		539	if (IS_ERR(info->tzd))
538	dev_err(&pdev->dev, "could not register thermal sensor: %ld\n",	540	dev_err(&pdev->dev, "could not register thermal sensor: %ld\n",
539	PTR_ERR(tzd));	541	PTR_ERR(info->tzd));
540		542
541	return PTR_ERR_OR_ZERO(tzd);	543	return PTR_ERR_OR_ZERO(info->tzd);
542	}	544	}
543		545
544	static int sun4i_gpadc_probe_mfd(struct platform_device *pdev,	546	static int sun4i_gpadc_probe_mfd(struct platform_device *pdev,
@@ -584,15 +586,15 @@ static int sun4i_gpadc_probe_mfd(struct platform_device *pdev, · 39 unmodified lines
584	* of_node, and the device from this driver as third argument to	586	* of_node, and the device from this driver as third argument to
585	* return the temperature.	587	* return the temperature.
586	*/	588	*/
587	struct thermal_zone_device *tzd;	589	info->sensor_device = pdev->dev.parent;
588	tzd = devm_thermal_zone_of_sensor_register(pdev->dev.parent, 0,	590	info->tzd = thermal_zone_of_sensor_register(info->sensor_device,
589	info,	591	0, info,
590	&sun4i_ts_tz_ops);	592	&sun4i_ts_tz_ops);
591	if (IS_ERR(tzd)) {	593	if (IS_ERR(info->tzd)) {
592	dev_err(&pdev->dev,	594	dev_err(&pdev->dev,
593	"could not register thermal sensor: %ld\n",	595	"could not register thermal sensor: %ld\n",
594	PTR_ERR(tzd));	596	PTR_ERR(info->tzd));
595	return PTR_ERR(tzd);	597	return PTR_ERR(info->tzd);
596	}	598	}
597	} else {	599	} else {
598	indio_dev->num_channels =	600	indio_dev->num_channels =
@@ -688,7 +690,13 @@ static int sun4i_gpadc_remove(struct platform_device *pdev) · 89 unmodified lines
688		690
689	pm_runtime_put(&pdev->dev);	691	pm_runtime_put(&pdev->dev);
690	pm_runtime_disable(&pdev->dev);	692	pm_runtime_disable(&pdev->dev);
691	if (!info->no_irq && IS_ENABLED(CONFIG_THERMAL_OF))	693
		694	if (!IS_ENABLED(CONFIG_THERMAL_OF))
		695	return 0;
		696
		697	thermal_zone_of_sensor_unregister(info->sensor_device, info->tzd);
		698
		699	if (!info->no_irq)
692	iio_map_array_unregister(indio_dev);	700	iio_map_array_unregister(indio_dev);
693		701
694	return 0;	702	return 0;
@@ -700,6 +708,7 @@ static const struct platform_device_id sun4i_gpadc_id[] = { · 5 unmodified lines
700	{ "sun6i-a31-gpadc-iio", (kernel_ulong_t)&sun6i_gpadc_data },	708	{ "sun6i-a31-gpadc-iio", (kernel_ulong_t)&sun6i_gpadc_data },
701	{ /* sentinel */ },	709	{ /* sentinel */ },
702	};	710	};
		711	MODULE_DEVICE_TABLE(platform, sun4i_gpadc_id);
703		712
704	static struct platform_driver sun4i_gpadc_driver = {	713	static struct platform_driver sun4i_gpadc_driver = {
705	.driver = {	714	.driver = {
@@ -711,6 +720,7 @@ static struct platform_driver sun4i_gpadc_driver = { · 5 unmodified lines
711	.probe = sun4i_gpadc_probe,	720	.probe = sun4i_gpadc_probe,
712	.remove = sun4i_gpadc_remove,	721	.remove = sun4i_gpadc_remove,
713	};	722	};
		723	MODULE_DEVICE_TABLE(of, sun4i_gpadc_of_id);
714		724
715	module_platform_driver(sun4i_gpadc_driver);	725	module_platform_driver(sun4i_gpadc_driver);
716		726

drivers/iio/adc/ti_am335x_adc.c+1−1

@@ -614,7 +614,7 @@ static int tiadc_probe(struct platform_device *pdev) · 613 unmodified lines
614	return -EINVAL;	614	return -EINVAL;
615	}	615	}
616		616
617	indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*indio_dev));	617	indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc_dev));
618	if (indio_dev == NULL) {	618	if (indio_dev == NULL) {
619	dev_err(&pdev->dev, "failed to allocate iio device\n");	619	dev_err(&pdev->dev, "failed to allocate iio device\n");
620	return -ENOMEM;	620	return -ENOMEM;

drivers/iio/buffer/industrialio-buffer-dma.c+1−0

@@ -14,6 +14,7 @@ · 13 unmodified lines
14	#include <linux/sched.h>	14	#include <linux/sched.h>
15	#include <linux/poll.h>	15	#include <linux/poll.h>
16	#include <linux/iio/buffer.h>	16	#include <linux/iio/buffer.h>
		17	#include <linux/iio/buffer_impl.h>
17	#include <linux/iio/buffer-dma.h>	18	#include <linux/iio/buffer-dma.h>
18	#include <linux/dma-mapping.h>	19	#include <linux/dma-mapping.h>
19	#include <linux/sizes.h>	20	#include <linux/sizes.h>

drivers/iio/buffer/industrialio-buffer-dmaengine.c+1−0

@@ -14,6 +14,7 @@ · 13 unmodified lines
14		14
15	#include <linux/iio/iio.h>	15	#include <linux/iio/iio.h>
16	#include <linux/iio/buffer.h>	16	#include <linux/iio/buffer.h>
		17	#include <linux/iio/buffer_impl.h>
17	#include <linux/iio/buffer-dma.h>	18	#include <linux/iio/buffer-dma.h>
18	#include <linux/iio/buffer-dmaengine.h>	19	#include <linux/iio/buffer-dmaengine.h>
19		20

drivers/iio/imu/inv_mpu6050/inv_mpu_core.c+36−3

@@ -41,6 +41,7 @@ static const int accel_scale[] = {598, 1196, 2392, 4785}; · 40 unmodified lines
41	static const struct inv_mpu6050_reg_map reg_set_6500 = {	41	static const struct inv_mpu6050_reg_map reg_set_6500 = {
42	.sample_rate_div = INV_MPU6050_REG_SAMPLE_RATE_DIV,	42	.sample_rate_div = INV_MPU6050_REG_SAMPLE_RATE_DIV,
43	.lpf = INV_MPU6050_REG_CONFIG,	43	.lpf = INV_MPU6050_REG_CONFIG,
		44	.accel_lpf = INV_MPU6500_REG_ACCEL_CONFIG_2,
44	.user_ctrl = INV_MPU6050_REG_USER_CTRL,	45	.user_ctrl = INV_MPU6050_REG_USER_CTRL,
45	.fifo_en = INV_MPU6050_REG_FIFO_EN,	46	.fifo_en = INV_MPU6050_REG_FIFO_EN,
46	.gyro_config = INV_MPU6050_REG_GYRO_CONFIG,	47	.gyro_config = INV_MPU6050_REG_GYRO_CONFIG,
@@ -210,6 +211,37 @@ int inv_mpu6050_set_power_itg(struct inv_mpu6050_state *st, bool power_on) · 163 unmodified lines
210	}	211	}
211	EXPORT_SYMBOL_GPL(inv_mpu6050_set_power_itg);	212	EXPORT_SYMBOL_GPL(inv_mpu6050_set_power_itg);
212		213
		214	/**
		215	* inv_mpu6050_set_lpf_regs() - set low pass filter registers, chip dependent
		216	*
		217	* MPU60xx/MPU9150 use only 1 register for accelerometer + gyroscope
		218	* MPU6500 and above have a dedicated register for accelerometer
		219	*/
		220	static int inv_mpu6050_set_lpf_regs(struct inv_mpu6050_state *st,
		221	enum inv_mpu6050_filter_e val)
		222	{
		223	int result;
		224
		225	result = regmap_write(st->map, st->reg->lpf, val);
		226	if (result)
		227	return result;
		228
		229	switch (st->chip_type) {
		230	case INV_MPU6050:
		231	case INV_MPU6000:
		232	case INV_MPU9150:
		233	/* old chips, nothing to do */
		234	result = 0;
		235	break;
		236	default:
		237	/* set accel lpf */
		238	result = regmap_write(st->map, st->reg->accel_lpf, val);
		239	break;
		240	}
		241
		242	return result;
		243	}
		244
213	/**	245	/**
214	* inv_mpu6050_init_config() - Initialize hardware, disable FIFO.	246	* inv_mpu6050_init_config() - Initialize hardware, disable FIFO.
215	*	247	*
@@ -233,8 +265,7 @@ static int inv_mpu6050_init_config(struct iio_dev *indio_dev) · 17 unmodified lines
233	if (result)	265	if (result)
234	return result;	266	return result;
235		267
236	d = INV_MPU6050_FILTER_20HZ;	268	result = inv_mpu6050_set_lpf_regs(st, INV_MPU6050_FILTER_20HZ);
237	result = regmap_write(st->map, st->reg->lpf, d);
238	if (result)	269	if (result)
239	return result;	270	return result;
240		271
@@ -537,6 +568,8 @@ error_write_raw: · 296 unmodified lines
537	* would be alising. This function basically search for the	568	* would be alising. This function basically search for the
538	* correct low pass parameters based on the fifo rate, e.g,	569	* correct low pass parameters based on the fifo rate, e.g,
539	* sampling frequency.	570	* sampling frequency.
		571	*
		572	* lpf is set automatically when setting sampling rate to avoid any aliases.
540	*/	573	*/
541	static int inv_mpu6050_set_lpf(struct inv_mpu6050_state *st, int rate)	574	static int inv_mpu6050_set_lpf(struct inv_mpu6050_state *st, int rate)
542	{	575	{
@@ -552,7 +585,7 @@ static int inv_mpu6050_set_lpf(struct inv_mpu6050_state *st, int rate) · 9 unmodified lines
552	while ((h < hz[i]) && (i < ARRAY_SIZE(d) - 1))	585	while ((h < hz[i]) && (i < ARRAY_SIZE(d) - 1))
553	i++;	586	i++;
554	data = d[i];	587	data = d[i];
555	result = regmap_write(st->map, st->reg->lpf, data);	588	result = inv_mpu6050_set_lpf_regs(st, data);
556	if (result)	589	if (result)
557	return result;	590	return result;
558	st->chip_config.lpf = data;	591	st->chip_config.lpf = data;

drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h+3−0

  *  struct inv_mpu6050_reg_map - Notable registers.
  *  @sample_rate_div:	Divider applied to gyro output rate.
  *  @lpf:		Configures internal low pass filter.
+ *  @accel_lpf:		Configures accelerometer low pass filter.
  *  @user_ctrl:		Enables/resets the FIFO.
  *  @fifo_en:		Determines which data will appear in FIFO.
  *  @gyro_config:	gyro config register.
 struct inv_mpu6050_reg_map {
 	u8 sample_rate_div;
 	u8 lpf;
+	u8 accel_lpf;
 	u8 user_ctrl;
 	u8 fifo_en;
 	u8 gyro_config;
 #define INV_MPU6050_FIFO_THRESHOLD           500
 /* mpu6500 registers */
+#define INV_MPU6500_REG_ACCEL_CONFIG_2      0x1D
 #define INV_MPU6500_REG_ACCEL_OFFSET        0x77
 /* delay time in milliseconds */

drivers/iio/industrialio-trigger.c+2−1

@@ -451,7 +451,8 @@ static ssize_t iio_trigger_write_current(struct device *dev, · 450 unmodified lines
451	return len;	451	return len;
452		452
453	out_trigger_put:	453	out_trigger_put:
454	iio_trigger_put(trig);	454	if (trig)
		455	iio_trigger_put(trig);
455	return ret;	456	return ret;
456	}	457	}
457		458

drivers/iio/light/ltr501.c+2−2

 static const struct reg_field reg_field_it =
 				REG_FIELD(LTR501_ALS_MEAS_RATE, 3, 4);
 static const struct reg_field reg_field_als_intr =
-				REG_FIELD(LTR501_INTR, 0, 0);
-static const struct reg_field reg_field_ps_intr =
 				REG_FIELD(LTR501_INTR, 1, 1);
+static const struct reg_field reg_field_ps_intr =
+				REG_FIELD(LTR501_INTR, 0, 0);
 static const struct reg_field reg_field_als_rate =
 				REG_FIELD(LTR501_ALS_MEAS_RATE, 0, 2);
 static const struct reg_field reg_field_ps_rate =

drivers/iio/proximity/as3935.c+6−8

 #define AS3935_AFE_PWR_BIT	BIT(0)
 #define AS3935_INT		0x03
-#define AS3935_INT_MASK		0x07
+#define AS3935_INT_MASK		0x0f
 #define AS3935_EVENT_INT	BIT(3)
-#define AS3935_NOISE_INT	BIT(1)
+#define AS3935_NOISE_INT	BIT(0)
 #define AS3935_DATA		0x07
 #define AS3935_DATA_MASK	0x3F
 	st->buffer[0] = val & AS3935_DATA_MASK;
 	iio_push_to_buffers_with_timestamp(indio_dev, &st->buffer,
-					   pf->timestamp);
+					   iio_get_time_ns(indio_dev));
 err_read:
 	iio_trigger_notify_done(indio_dev->trig);
 	switch (val) {
 	case AS3935_EVENT_INT:
-		iio_trigger_poll(st->trig);
+		iio_trigger_poll_chained(st->trig);
 		break;
 	case AS3935_NOISE_INT:
 		dev_warn(&st->spi->dev, "noise level is too high\n");
 static void calibrate_as3935(struct as3935_state *st)
 {
-	mutex_lock(&st->lock);
 	/* mask disturber interrupt bit */
 	as3935_write(st, AS3935_INT, BIT(5));
 	mdelay(2);
 	as3935_write(st, AS3935_TUNE_CAP, (st->tune_cap / TUNE_CAP_DIV));
-	mutex_unlock(&st->lock);
 }
 #ifdef CONFIG_PM_SLEEP
 	val &= ~AS3935_AFE_PWR_BIT;
 	ret = as3935_write(st, AS3935_AFE_GAIN, val);
+	calibrate_as3935(st);
 err_resume:
 	mutex_unlock(&st->lock);

drivers/infiniband/core/addr.c+1−9

 		return ret;
 	rt = (struct rt6_info *)dst;
-	if (ipv6_addr_any(&fl6.saddr)) {
+	if (ipv6_addr_any(&src_in->sin6_addr)) {
-		ret = ipv6_dev_get_saddr(addr->net, ip6_dst_idev(dst)->dev,
-					 &fl6.daddr, 0, &fl6.saddr);
-		if (ret)
-			goto put;
 		src_in->sin6_family = AF_INET6;
 		src_in->sin6_addr = fl6.saddr;
 	}
 	*pdst = dst;
 	return 0;
-put:
-	dst_release(dst);
-	return ret;
 }
 #else
 static int addr6_resolve(struct sockaddr_in6 *src_in,

drivers/infiniband/core/cm.c+2−2

@@ -1429,7 +1429,7 @@ static void cm_format_paths_from_req(struct cm_req_msg *req_msg, · 1428 unmodified lines
1429	primary_path->packet_life_time =	1429	primary_path->packet_life_time =
1430	cm_req_get_primary_local_ack_timeout(req_msg);	1430	cm_req_get_primary_local_ack_timeout(req_msg);
1431	primary_path->packet_life_time -= (primary_path->packet_life_time > 0);	1431	primary_path->packet_life_time -= (primary_path->packet_life_time > 0);
1432	sa_path_set_service_id(primary_path, req_msg->service_id);	1432	primary_path->service_id = req_msg->service_id;
1433		1433
1434	if (req_msg->alt_local_lid) {	1434	if (req_msg->alt_local_lid) {
1435	alt_path->dgid = req_msg->alt_local_gid;	1435	alt_path->dgid = req_msg->alt_local_gid;
@@ -1452,7 +1452,7 @@ static void cm_format_paths_from_req(struct cm_req_msg *req_msg, · 16 unmodified lines
1452	alt_path->packet_life_time =	1452	alt_path->packet_life_time =
1453	cm_req_get_alt_local_ack_timeout(req_msg);	1453	cm_req_get_alt_local_ack_timeout(req_msg);
1454	alt_path->packet_life_time -= (alt_path->packet_life_time > 0);	1454	alt_path->packet_life_time -= (alt_path->packet_life_time > 0);
1455	sa_path_set_service_id(alt_path, req_msg->service_id);	1455	alt_path->service_id = req_msg->service_id;
1456	}	1456	}
1457	}	1457	}
1458		1458

drivers/infiniband/core/cma.c+6−7

 			ib->sib_pkey = path->pkey;
 			ib->sib_flowinfo = path->flow_label;
 			memcpy(&ib->sib_addr, &path->sgid, 16);
-			ib->sib_sid = sa_path_get_service_id(path);
+			ib->sib_sid = path->service_id;
 			ib->sib_scope_id = 0;
 		} else {
 			ib->sib_pkey = listen_ib->sib_pkey;
 		memcpy(&req->local_gid, &req_param->primary_path->sgid,
 		       sizeof(req->local_gid));
 		req->has_gid	= true;
-		req->service_id	=
+		req->service_id = req_param->primary_path->service_id;
-			sa_path_get_service_id(req_param->primary_path);
 		req->pkey	= be16_to_cpu(req_param->primary_path->pkey);
 		if (req->pkey != req_param->bth_pkey)
 			pr_warn_ratelimited("RDMA CMA: got different BTH P_Key (0x%x) and primary path P_Key (0x%x)\n"
 	struct rdma_route *rt;
 	const sa_family_t ss_family = listen_id->route.addr.src_addr.ss_family;
 	struct sa_path_rec *path = ib_event->param.req_rcvd.primary_path;
-	const __be64 service_id = sa_path_get_service_id(path);
+	const __be64 service_id =
+		ib_event->param.req_rcvd.primary_path->service_id;
 	int ret;
 	id = rdma_create_id(listen_id->route.addr.dev_addr.net,
 	path_rec.pkey = cpu_to_be16(ib_addr_get_pkey(dev_addr));
 	path_rec.numb_path = 1;
 	path_rec.reversible = 1;
-	sa_path_set_service_id(&path_rec,
+	path_rec.service_id = rdma_get_service_id(&id_priv->id,
-			       rdma_get_service_id(&id_priv->id,
+						  cma_dst_addr(id_priv));
-						   cma_dst_addr(id_priv)));
 	comp_mask = IB_SA_PATH_REC_DGID | IB_SA_PATH_REC_SGID |
 		    IB_SA_PATH_REC_PKEY | IB_SA_PATH_REC_NUMB_PATH |

drivers/infiniband/core/core_priv.h+10−0

@@ -169,6 +169,16 @@ void ib_mad_cleanup(void); · 168 unmodified lines
169	int ib_sa_init(void);	169	int ib_sa_init(void);
170	void ib_sa_cleanup(void);	170	void ib_sa_cleanup(void);
171		171
		172	int ibnl_init(void);
		173	void ibnl_cleanup(void);
		174
		175	/**
		176	* Check if there are any listeners to the netlink group
		177	* @group: the netlink group ID
		178	* Returns 0 on success or a negative for no listeners.
		179	*/
		180	int ibnl_chk_listeners(unsigned int group);
		181
172	int ib_nl_handle_resolve_resp(struct sk_buff *skb,	182	int ib_nl_handle_resolve_resp(struct sk_buff *skb,
173	struct netlink_callback *cb);	183	struct netlink_callback *cb);
174	int ib_nl_handle_set_timeout(struct sk_buff *skb,	184	int ib_nl_handle_set_timeout(struct sk_buff *skb,

drivers/infiniband/core/netlink.c+1−1

 #include <net/net_namespace.h>
 #include <net/sock.h>
 #include <rdma/rdma_netlink.h>
+#include "core_priv.h"
 struct ibnl_client {
 	struct list_head		list;
 		return -1;
 	return 0;
 }
-EXPORT_SYMBOL(ibnl_chk_listeners);
 int ibnl_add_client(int index, int nops,
 		    const struct ibnl_client_cbs cb_table[])

drivers/infiniband/core/sa_query.c+3−3

@@ -194,7 +194,7 @@ static u32 tid; · 193 unmodified lines
194	.field_name = "sa_path_rec:" #field	194	.field_name = "sa_path_rec:" #field
195		195
196	static const struct ib_field path_rec_table[] = {	196	static const struct ib_field path_rec_table[] = {
197	{ PATH_REC_FIELD(ib.service_id),	197	{ PATH_REC_FIELD(service_id),
198	.offset_words = 0,	198	.offset_words = 0,
199	.offset_bits = 0,	199	.offset_bits = 0,
200	.size_bits = 64 },	200	.size_bits = 64 },
@@ -296,7 +296,7 @@ static const struct ib_field path_rec_table[] = { · 95 unmodified lines
296	.field_name = "sa_path_rec:" #field	296	.field_name = "sa_path_rec:" #field
297		297
298	static const struct ib_field opa_path_rec_table[] = {	298	static const struct ib_field opa_path_rec_table[] = {
299	{ OPA_PATH_REC_FIELD(opa.service_id),	299	{ OPA_PATH_REC_FIELD(service_id),
300	.offset_words = 0,	300	.offset_words = 0,
301	.offset_bits = 0,	301	.offset_bits = 0,
302	.size_bits = 64 },	302	.size_bits = 64 },
@@ -774,7 +774,7 @@ static void ib_nl_set_path_rec_attrs(struct sk_buff *skb, · 471 unmodified lines
774		774
775	/* Now build the attributes */	775	/* Now build the attributes */
776	if (comp_mask & IB_SA_PATH_REC_SERVICE_ID) {	776	if (comp_mask & IB_SA_PATH_REC_SERVICE_ID) {
777	val64 = be64_to_cpu(sa_path_get_service_id(sa_rec));	777	val64 = be64_to_cpu(sa_rec->service_id);
778	nla_put(skb, RDMA_NLA_F_MANDATORY \| LS_NLA_TYPE_SERVICE_ID,	778	nla_put(skb, RDMA_NLA_F_MANDATORY \| LS_NLA_TYPE_SERVICE_ID,
779	sizeof(val64), &val64);	779	sizeof(val64), &val64);
780	}	780	}

drivers/infiniband/core/umem.c+1−1

@@ -58,7 +58,7 @@ static void __ib_umem_release(struct ib_device dev, struct ib_umem umem, int d · 57 unmodified lines
58	for_each_sg(umem->sg_head.sgl, sg, umem->npages, i) {	58	for_each_sg(umem->sg_head.sgl, sg, umem->npages, i) {
59		59
60	page = sg_page(sg);	60	page = sg_page(sg);
61	if (umem->writable && dirty)	61	if (!PageDirty(page) && umem->writable && dirty)
62	set_page_dirty_lock(page);	62	set_page_dirty_lock(page);
63	put_page(page);	63	put_page(page);
64	}	64	}

drivers/infiniband/core/umem_odp.c+5−1

 		struct vm_area_struct *vma;
 		struct hstate *h;
+		down_read(&mm->mmap_sem);
 		vma = find_vma(mm, ib_umem_start(umem));
-		if (!vma || !is_vm_hugetlb_page(vma))
+		if (!vma || !is_vm_hugetlb_page(vma)) {
+			up_read(&mm->mmap_sem);
 			return -EINVAL;
+		}
 		h = hstate_vma(vma);
 		umem->page_shift = huge_page_shift(h);
+		up_read(&mm->mmap_sem);
 		umem->hugetlb = 1;
 	} else {
 		umem->hugetlb = 0;

drivers/infiniband/core/uverbs_marshall.c+4−4

@@ -96,11 +96,11 @@ void ib_copy_qp_attr_to_user(struct ib_uverbs_qp_attr *dst, · 95 unmodified lines
96	}	96	}
97	EXPORT_SYMBOL(ib_copy_qp_attr_to_user);	97	EXPORT_SYMBOL(ib_copy_qp_attr_to_user);
98		98
99	void __ib_copy_path_rec_to_user(struct ib_user_path_rec *dst,	99	static void __ib_copy_path_rec_to_user(struct ib_user_path_rec *dst,
100	struct sa_path_rec *src)	100	struct sa_path_rec *src)
101	{	101	{
102	memcpy(dst->dgid, src->dgid.raw, sizeof src->dgid);	102	memcpy(dst->dgid, src->dgid.raw, sizeof(src->dgid));
103	memcpy(dst->sgid, src->sgid.raw, sizeof src->sgid);	103	memcpy(dst->sgid, src->sgid.raw, sizeof(src->sgid));
104		104
105	dst->dlid = htons(ntohl(sa_path_get_dlid(src)));	105	dst->dlid = htons(ntohl(sa_path_get_dlid(src)));
106	dst->slid = htons(ntohl(sa_path_get_slid(src)));	106	dst->slid = htons(ntohl(sa_path_get_slid(src)));

drivers/infiniband/hw/bnxt_re/bnxt_re.h+4−0

@@ -56,6 +56,10 @@ · 55 unmodified lines
56	#define BNXT_RE_MAX_SRQC_COUNT (64 * 1024)	56	#define BNXT_RE_MAX_SRQC_COUNT (64 * 1024)
57	#define BNXT_RE_MAX_CQ_COUNT (64 * 1024)	57	#define BNXT_RE_MAX_CQ_COUNT (64 * 1024)
58		58
		59	#define BNXT_RE_UD_QP_HW_STALL 0x400000
		60
		61	#define BNXT_RE_RQ_WQE_THRESHOLD 32
		62
59	struct bnxt_re_work {	63	struct bnxt_re_work {
60	struct work_struct work;	64	struct work_struct work;
61	unsigned long event;	65	unsigned long event;

drivers/infiniband/hw/bnxt_re/ib_verbs.c+347−124

@@ -61,6 +61,48 @@ · 60 unmodified lines
61	#include "ib_verbs.h"	61	#include "ib_verbs.h"
62	#include <rdma/bnxt_re-abi.h>	62	#include <rdma/bnxt_re-abi.h>
63		63
		64	static int __from_ib_access_flags(int iflags)
		65	{
		66	int qflags = 0;
		67
		68	if (iflags & IB_ACCESS_LOCAL_WRITE)
		69	qflags \|= BNXT_QPLIB_ACCESS_LOCAL_WRITE;
		70	if (iflags & IB_ACCESS_REMOTE_READ)
		71	qflags \|= BNXT_QPLIB_ACCESS_REMOTE_READ;
		72	if (iflags & IB_ACCESS_REMOTE_WRITE)
		73	qflags \|= BNXT_QPLIB_ACCESS_REMOTE_WRITE;
		74	if (iflags & IB_ACCESS_REMOTE_ATOMIC)
		75	qflags \|= BNXT_QPLIB_ACCESS_REMOTE_ATOMIC;
		76	if (iflags & IB_ACCESS_MW_BIND)
		77	qflags \|= BNXT_QPLIB_ACCESS_MW_BIND;
		78	if (iflags & IB_ZERO_BASED)
		79	qflags \|= BNXT_QPLIB_ACCESS_ZERO_BASED;
		80	if (iflags & IB_ACCESS_ON_DEMAND)
		81	qflags \|= BNXT_QPLIB_ACCESS_ON_DEMAND;
		82	return qflags;
		83	};
		84
		85	static enum ib_access_flags __to_ib_access_flags(int qflags)
		86	{
		87	enum ib_access_flags iflags = 0;
		88
		89	if (qflags & BNXT_QPLIB_ACCESS_LOCAL_WRITE)
		90	iflags \|= IB_ACCESS_LOCAL_WRITE;
		91	if (qflags & BNXT_QPLIB_ACCESS_REMOTE_WRITE)
		92	iflags \|= IB_ACCESS_REMOTE_WRITE;
		93	if (qflags & BNXT_QPLIB_ACCESS_REMOTE_READ)
		94	iflags \|= IB_ACCESS_REMOTE_READ;
		95	if (qflags & BNXT_QPLIB_ACCESS_REMOTE_ATOMIC)
		96	iflags \|= IB_ACCESS_REMOTE_ATOMIC;
		97	if (qflags & BNXT_QPLIB_ACCESS_MW_BIND)
		98	iflags \|= IB_ACCESS_MW_BIND;
		99	if (qflags & BNXT_QPLIB_ACCESS_ZERO_BASED)
		100	iflags \|= IB_ZERO_BASED;
		101	if (qflags & BNXT_QPLIB_ACCESS_ON_DEMAND)
		102	iflags \|= IB_ACCESS_ON_DEMAND;
		103	return iflags;
		104	};
		105
64	static int bnxt_re_build_sgl(struct ib_sge *ib_sg_list,	106	static int bnxt_re_build_sgl(struct ib_sge *ib_sg_list,
65	struct bnxt_qplib_sge *sg_list, int num)	107	struct bnxt_qplib_sge *sg_list, int num)
66	{	108	{
@@ -149,8 +191,8 @@ int bnxt_re_query_device(struct ib_device *ibdev, · 82 unmodified lines
149	ib_attr->max_total_mcast_qp_attach = 0;	191	ib_attr->max_total_mcast_qp_attach = 0;
150	ib_attr->max_ah = dev_attr->max_ah;	192	ib_attr->max_ah = dev_attr->max_ah;
151		193
152	ib_attr->max_fmr = dev_attr->max_fmr;	194	ib_attr->max_fmr = 0;
153	ib_attr->max_map_per_fmr = 1; /* ? */	195	ib_attr->max_map_per_fmr = 0;
154		196
155	ib_attr->max_srq = dev_attr->max_srq;	197	ib_attr->max_srq = dev_attr->max_srq;
156	ib_attr->max_srq_wr = dev_attr->max_srq_wqes;	198	ib_attr->max_srq_wr = dev_attr->max_srq_wqes;
@@ -410,6 +452,158 @@ enum rdma_link_layer bnxt_re_get_link_layer(struct ib_device *ibdev, · 253 unmodified lines
410	return IB_LINK_LAYER_ETHERNET;	452	return IB_LINK_LAYER_ETHERNET;
411	}	453	}
412		454
		455	#define BNXT_RE_FENCE_PBL_SIZE DIV_ROUND_UP(BNXT_RE_FENCE_BYTES, PAGE_SIZE)
		456
		457	static void bnxt_re_create_fence_wqe(struct bnxt_re_pd *pd)
		458	{
		459	struct bnxt_re_fence_data *fence = &pd->fence;
		460	struct ib_mr *ib_mr = &fence->mr->ib_mr;
		461	struct bnxt_qplib_swqe *wqe = &fence->bind_wqe;
		462
		463	memset(wqe, 0, sizeof(*wqe));
		464	wqe->type = BNXT_QPLIB_SWQE_TYPE_BIND_MW;
		465	wqe->wr_id = BNXT_QPLIB_FENCE_WRID;
		466	wqe->flags \|= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
		467	wqe->flags \|= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
		468	wqe->bind.zero_based = false;
		469	wqe->bind.parent_l_key = ib_mr->lkey;
		470	wqe->bind.va = (u64)(unsigned long)fence->va;
		471	wqe->bind.length = fence->size;
		472	wqe->bind.access_cntl = __from_ib_access_flags(IB_ACCESS_REMOTE_READ);
		473	wqe->bind.mw_type = SQ_BIND_MW_TYPE_TYPE1;
		474
		475	/* Save the initial rkey in fence structure for now;
		476	* wqe->bind.r_key will be set at (re)bind time.
		477	*/
		478	fence->bind_rkey = ib_inc_rkey(fence->mw->rkey);
		479	}
		480
		481	static int bnxt_re_bind_fence_mw(struct bnxt_qplib_qp *qplib_qp)
		482	{
		483	struct bnxt_re_qp *qp = container_of(qplib_qp, struct bnxt_re_qp,
		484	qplib_qp);
		485	struct ib_pd *ib_pd = qp->ib_qp.pd;
		486	struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
		487	struct bnxt_re_fence_data *fence = &pd->fence;
		488	struct bnxt_qplib_swqe *fence_wqe = &fence->bind_wqe;
		489	struct bnxt_qplib_swqe wqe;
		490	int rc;
		491
		492	memcpy(&wqe, fence_wqe, sizeof(wqe));
		493	wqe.bind.r_key = fence->bind_rkey;
		494	fence->bind_rkey = ib_inc_rkey(fence->bind_rkey);
		495
		496	dev_dbg(rdev_to_dev(qp->rdev),
		497	"Posting bind fence-WQE: rkey: %#x QP: %d PD: %p\n",
		498	wqe.bind.r_key, qp->qplib_qp.id, pd);
		499	rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe);
		500	if (rc) {
		501	dev_err(rdev_to_dev(qp->rdev), "Failed to bind fence-WQE\n");
		502	return rc;
		503	}
		504	bnxt_qplib_post_send_db(&qp->qplib_qp);
		505
		506	return rc;
		507	}
		508
		509	static void bnxt_re_destroy_fence_mr(struct bnxt_re_pd *pd)
		510	{
		511	struct bnxt_re_fence_data *fence = &pd->fence;
		512	struct bnxt_re_dev *rdev = pd->rdev;
		513	struct device *dev = &rdev->en_dev->pdev->dev;
		514	struct bnxt_re_mr *mr = fence->mr;
		515
		516	if (fence->mw) {
		517	bnxt_re_dealloc_mw(fence->mw);
		518	fence->mw = NULL;
		519	}
		520	if (mr) {
		521	if (mr->ib_mr.rkey)
		522	bnxt_qplib_dereg_mrw(&rdev->qplib_res, &mr->qplib_mr,
		523	true);
		524	if (mr->ib_mr.lkey)
		525	bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
		526	kfree(mr);
		527	fence->mr = NULL;
		528	}
		529	if (fence->dma_addr) {
		530	dma_unmap_single(dev, fence->dma_addr, BNXT_RE_FENCE_BYTES,
		531	DMA_BIDIRECTIONAL);
		532	fence->dma_addr = 0;
		533	}
		534	}
		535
		536	static int bnxt_re_create_fence_mr(struct bnxt_re_pd *pd)
		537	{
		538	int mr_access_flags = IB_ACCESS_LOCAL_WRITE \| IB_ACCESS_MW_BIND;
		539	struct bnxt_re_fence_data *fence = &pd->fence;
		540	struct bnxt_re_dev *rdev = pd->rdev;
		541	struct device *dev = &rdev->en_dev->pdev->dev;
		542	struct bnxt_re_mr *mr = NULL;
		543	dma_addr_t dma_addr = 0;
		544	struct ib_mw *mw;
		545	u64 pbl_tbl;
		546	int rc;
		547
		548	dma_addr = dma_map_single(dev, fence->va, BNXT_RE_FENCE_BYTES,
		549	DMA_BIDIRECTIONAL);
		550	rc = dma_mapping_error(dev, dma_addr);
		551	if (rc) {
		552	dev_err(rdev_to_dev(rdev), "Failed to dma-map fence-MR-mem\n");
		553	rc = -EIO;
		554	fence->dma_addr = 0;
		555	goto fail;
		556	}
		557	fence->dma_addr = dma_addr;
		558
		559	/* Allocate a MR */
		560	mr = kzalloc(sizeof(*mr), GFP_KERNEL);
		561	if (!mr) {
		562	rc = -ENOMEM;
		563	goto fail;
		564	}
		565	fence->mr = mr;
		566	mr->rdev = rdev;
		567	mr->qplib_mr.pd = &pd->qplib_pd;
		568	mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
		569	mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags);
		570	rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
		571	if (rc) {
		572	dev_err(rdev_to_dev(rdev), "Failed to alloc fence-HW-MR\n");
		573	goto fail;
		574	}
		575
		576	/* Register MR */
		577	mr->ib_mr.lkey = mr->qplib_mr.lkey;
		578	mr->qplib_mr.va = (u64)(unsigned long)fence->va;
		579	mr->qplib_mr.total_size = BNXT_RE_FENCE_BYTES;
		580	pbl_tbl = dma_addr;
		581	rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, &pbl_tbl,
		582	BNXT_RE_FENCE_PBL_SIZE, false);
		583	if (rc) {
		584	dev_err(rdev_to_dev(rdev), "Failed to register fence-MR\n");
		585	goto fail;
		586	}
		587	mr->ib_mr.rkey = mr->qplib_mr.rkey;
		588
		589	/* Create a fence MW only for kernel consumers */
		590	mw = bnxt_re_alloc_mw(&pd->ib_pd, IB_MW_TYPE_1, NULL);
		591	if (!mw) {
		592	dev_err(rdev_to_dev(rdev),
		593	"Failed to create fence-MW for PD: %p\n", pd);
		594	rc = -EINVAL;
		595	goto fail;
		596	}
		597	fence->mw = mw;
		598
		599	bnxt_re_create_fence_wqe(pd);
		600	return 0;
		601
		602	fail:
		603	bnxt_re_destroy_fence_mr(pd);
		604	return rc;
		605	}
		606
413	/* Protection Domains */	607	/* Protection Domains */
414	int bnxt_re_dealloc_pd(struct ib_pd *ib_pd)	608	int bnxt_re_dealloc_pd(struct ib_pd *ib_pd)
415	{	609	{
@@ -417,6 +611,7 @@ int bnxt_re_dealloc_pd(struct ib_pd *ib_pd) · 1 unmodified line
417	struct bnxt_re_dev *rdev = pd->rdev;	611	struct bnxt_re_dev *rdev = pd->rdev;
418	int rc;	612	int rc;
419		613
		614	bnxt_re_destroy_fence_mr(pd);
420	if (ib_pd->uobject && pd->dpi.dbr) {	615	if (ib_pd->uobject && pd->dpi.dbr) {
421	struct ib_ucontext *ib_uctx = ib_pd->uobject->context;	616	struct ib_ucontext *ib_uctx = ib_pd->uobject->context;
422	struct bnxt_re_ucontext *ucntx;	617	struct bnxt_re_ucontext *ucntx;
@@ -498,6 +693,10 @@ struct ib_pd bnxt_re_alloc_pd(struct ib_device ibdev, · 75 unmodified lines
498	}	693	}
499	}	694	}
500		695
		696	if (!udata)
		697	if (bnxt_re_create_fence_mr(pd))
		698	dev_warn(rdev_to_dev(rdev),
		699	"Failed to create Fence-MR\n");
501	return &pd->ib_pd;	700	return &pd->ib_pd;
502	dbfail:	701	dbfail:
503	(void)bnxt_qplib_dealloc_pd(&rdev->qplib_res, &rdev->qplib_res.pd_tbl,	702	(void)bnxt_qplib_dealloc_pd(&rdev->qplib_res, &rdev->qplib_res.pd_tbl,
@@ -849,12 +1048,16 @@ static struct bnxt_re_qp *bnxt_re_create_shadow_qp · 345 unmodified lines
849	/* Shadow QP SQ depth should be same as QP1 RQ depth */	1048	/* Shadow QP SQ depth should be same as QP1 RQ depth */
850	qp->qplib_qp.sq.max_wqe = qp1_qp->rq.max_wqe;	1049	qp->qplib_qp.sq.max_wqe = qp1_qp->rq.max_wqe;
851	qp->qplib_qp.sq.max_sge = 2;	1050	qp->qplib_qp.sq.max_sge = 2;
		1051	/* Q full delta can be 1 since it is internal QP */
		1052	qp->qplib_qp.sq.q_full_delta = 1;
852		1053
853	qp->qplib_qp.scq = qp1_qp->scq;	1054	qp->qplib_qp.scq = qp1_qp->scq;
854	qp->qplib_qp.rcq = qp1_qp->rcq;	1055	qp->qplib_qp.rcq = qp1_qp->rcq;
855		1056
856	qp->qplib_qp.rq.max_wqe = qp1_qp->rq.max_wqe;	1057	qp->qplib_qp.rq.max_wqe = qp1_qp->rq.max_wqe;
857	qp->qplib_qp.rq.max_sge = qp1_qp->rq.max_sge;	1058	qp->qplib_qp.rq.max_sge = qp1_qp->rq.max_sge;
		1059	/* Q full delta can be 1 since it is internal QP */
		1060	qp->qplib_qp.rq.q_full_delta = 1;
858		1061
859	qp->qplib_qp.mtu = qp1_qp->mtu;	1062	qp->qplib_qp.mtu = qp1_qp->mtu;
860		1063
@@ -917,10 +1120,6 @@ struct ib_qp bnxt_re_create_qp(struct ib_pd ib_pd, · 56 unmodified lines
917	qp->qplib_qp.sig_type = ((qp_init_attr->sq_sig_type ==	1120	qp->qplib_qp.sig_type = ((qp_init_attr->sq_sig_type ==
918	IB_SIGNAL_ALL_WR) ? true : false);	1121	IB_SIGNAL_ALL_WR) ? true : false);
919		1122
920	entries = roundup_pow_of_two(qp_init_attr->cap.max_send_wr + 1);
921	qp->qplib_qp.sq.max_wqe = min_t(u32, entries,
922	dev_attr->max_qp_wqes + 1);
923
924	qp->qplib_qp.sq.max_sge = qp_init_attr->cap.max_send_sge;	1123	qp->qplib_qp.sq.max_sge = qp_init_attr->cap.max_send_sge;
925	if (qp->qplib_qp.sq.max_sge > dev_attr->max_qp_sges)	1124	if (qp->qplib_qp.sq.max_sge > dev_attr->max_qp_sges)
926	qp->qplib_qp.sq.max_sge = dev_attr->max_qp_sges;	1125	qp->qplib_qp.sq.max_sge = dev_attr->max_qp_sges;
@@ -959,6 +1158,9 @@ struct ib_qp bnxt_re_create_qp(struct ib_pd ib_pd, · 32 unmodified lines
959	qp->qplib_qp.rq.max_wqe = min_t(u32, entries,	1158	qp->qplib_qp.rq.max_wqe = min_t(u32, entries,
960	dev_attr->max_qp_wqes + 1);	1159	dev_attr->max_qp_wqes + 1);
961		1160
		1161	qp->qplib_qp.rq.q_full_delta = qp->qplib_qp.rq.max_wqe -
		1162	qp_init_attr->cap.max_recv_wr;
		1163
962	qp->qplib_qp.rq.max_sge = qp_init_attr->cap.max_recv_sge;	1164	qp->qplib_qp.rq.max_sge = qp_init_attr->cap.max_recv_sge;
963	if (qp->qplib_qp.rq.max_sge > dev_attr->max_qp_sges)	1165	if (qp->qplib_qp.rq.max_sge > dev_attr->max_qp_sges)
964	qp->qplib_qp.rq.max_sge = dev_attr->max_qp_sges;	1166	qp->qplib_qp.rq.max_sge = dev_attr->max_qp_sges;
@@ -967,6 +1169,12 @@ struct ib_qp bnxt_re_create_qp(struct ib_pd ib_pd, · 2 unmodified lines
967	qp->qplib_qp.mtu = ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu));	1169	qp->qplib_qp.mtu = ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu));
968		1170
969	if (qp_init_attr->qp_type == IB_QPT_GSI) {	1171	if (qp_init_attr->qp_type == IB_QPT_GSI) {
		1172	/* Allocate 1 more than what's provided */
		1173	entries = roundup_pow_of_two(qp_init_attr->cap.max_send_wr + 1);
		1174	qp->qplib_qp.sq.max_wqe = min_t(u32, entries,
		1175	dev_attr->max_qp_wqes + 1);
		1176	qp->qplib_qp.sq.q_full_delta = qp->qplib_qp.sq.max_wqe -
		1177	qp_init_attr->cap.max_send_wr;
970	qp->qplib_qp.rq.max_sge = dev_attr->max_qp_sges;	1178	qp->qplib_qp.rq.max_sge = dev_attr->max_qp_sges;
971	if (qp->qplib_qp.rq.max_sge > dev_attr->max_qp_sges)	1179	if (qp->qplib_qp.rq.max_sge > dev_attr->max_qp_sges)
972	qp->qplib_qp.rq.max_sge = dev_attr->max_qp_sges;	1180	qp->qplib_qp.rq.max_sge = dev_attr->max_qp_sges;
@@ -1006,6 +1214,22 @@ struct ib_qp bnxt_re_create_qp(struct ib_pd ib_pd, · 33 unmodified lines
1006	}	1214	}
1007		1215
1008	} else {	1216	} else {
		1217	/* Allocate 128 + 1 more than what's provided */
		1218	entries = roundup_pow_of_two(qp_init_attr->cap.max_send_wr +
		1219	BNXT_QPLIB_RESERVED_QP_WRS + 1);
		1220	qp->qplib_qp.sq.max_wqe = min_t(u32, entries,
		1221	dev_attr->max_qp_wqes +
		1222	BNXT_QPLIB_RESERVED_QP_WRS + 1);
		1223	qp->qplib_qp.sq.q_full_delta = BNXT_QPLIB_RESERVED_QP_WRS + 1;
		1224
		1225	/*
		1226	* Reserving one slot for Phantom WQE. Application can
		1227	* post one extra entry in this case. But allowing this to avoid
		1228	* unexpected Queue full condition
		1229	*/
		1230
		1231	qp->qplib_qp.sq.q_full_delta -= 1;
		1232
1009	qp->qplib_qp.max_rd_atomic = dev_attr->max_qp_rd_atom;	1233	qp->qplib_qp.max_rd_atomic = dev_attr->max_qp_rd_atom;
1010	qp->qplib_qp.max_dest_rd_atomic = dev_attr->max_qp_init_rd_atom;	1234	qp->qplib_qp.max_dest_rd_atomic = dev_attr->max_qp_init_rd_atom;
1011	if (udata) {	1235	if (udata) {
@@ -1025,6 +1249,7 @@ struct ib_qp bnxt_re_create_qp(struct ib_pd ib_pd, · 13 unmodified lines
1025		1249
1026	qp->ib_qp.qp_num = qp->qplib_qp.id;	1250	qp->ib_qp.qp_num = qp->qplib_qp.id;
1027	spin_lock_init(&qp->sq_lock);	1251	spin_lock_init(&qp->sq_lock);
		1252	spin_lock_init(&qp->rq_lock);
1028		1253
1029	if (udata) {	1254	if (udata) {
1030	struct bnxt_re_qp_resp resp;	1255	struct bnxt_re_qp_resp resp;
@@ -1129,48 +1354,6 @@ static enum ib_mtu __to_ib_mtu(u32 mtu) · 98 unmodified lines
1129	}	1354	}
1130	}	1355	}
1131		1356
1132	static int __from_ib_access_flags(int iflags)
1133	{
1134	int qflags = 0;
1135
1136	if (iflags & IB_ACCESS_LOCAL_WRITE)
1137	qflags \|= BNXT_QPLIB_ACCESS_LOCAL_WRITE;
1138	if (iflags & IB_ACCESS_REMOTE_READ)
1139	qflags \|= BNXT_QPLIB_ACCESS_REMOTE_READ;
1140	if (iflags & IB_ACCESS_REMOTE_WRITE)
1141	qflags \|= BNXT_QPLIB_ACCESS_REMOTE_WRITE;
1142	if (iflags & IB_ACCESS_REMOTE_ATOMIC)
1143	qflags \|= BNXT_QPLIB_ACCESS_REMOTE_ATOMIC;
1144	if (iflags & IB_ACCESS_MW_BIND)
1145	qflags \|= BNXT_QPLIB_ACCESS_MW_BIND;
1146	if (iflags & IB_ZERO_BASED)
1147	qflags \|= BNXT_QPLIB_ACCESS_ZERO_BASED;
1148	if (iflags & IB_ACCESS_ON_DEMAND)
1149	qflags \|= BNXT_QPLIB_ACCESS_ON_DEMAND;
1150	return qflags;
1151	};
1152
1153	static enum ib_access_flags __to_ib_access_flags(int qflags)
1154	{
1155	enum ib_access_flags iflags = 0;
1156
1157	if (qflags & BNXT_QPLIB_ACCESS_LOCAL_WRITE)
1158	iflags \|= IB_ACCESS_LOCAL_WRITE;
1159	if (qflags & BNXT_QPLIB_ACCESS_REMOTE_WRITE)
1160	iflags \|= IB_ACCESS_REMOTE_WRITE;
1161	if (qflags & BNXT_QPLIB_ACCESS_REMOTE_READ)
1162	iflags \|= IB_ACCESS_REMOTE_READ;
1163	if (qflags & BNXT_QPLIB_ACCESS_REMOTE_ATOMIC)
1164	iflags \|= IB_ACCESS_REMOTE_ATOMIC;
1165	if (qflags & BNXT_QPLIB_ACCESS_MW_BIND)
1166	iflags \|= IB_ACCESS_MW_BIND;
1167	if (qflags & BNXT_QPLIB_ACCESS_ZERO_BASED)
1168	iflags \|= IB_ZERO_BASED;
1169	if (qflags & BNXT_QPLIB_ACCESS_ON_DEMAND)
1170	iflags \|= IB_ACCESS_ON_DEMAND;
1171	return iflags;
1172	};
1173
1174	static int bnxt_re_modify_shadow_qp(struct bnxt_re_dev *rdev,	1357	static int bnxt_re_modify_shadow_qp(struct bnxt_re_dev *rdev,
1175	struct bnxt_re_qp *qp1_qp,	1358	struct bnxt_re_qp *qp1_qp,
1176	int qp_attr_mask)	1359	int qp_attr_mask)
@@ -1378,11 +1561,21 @@ int bnxt_re_modify_qp(struct ib_qp ib_qp, struct ib_qp_attr qp_attr, · 201 unmodified lines
1378	entries = roundup_pow_of_two(qp_attr->cap.max_send_wr);	1561	entries = roundup_pow_of_two(qp_attr->cap.max_send_wr);
1379	qp->qplib_qp.sq.max_wqe = min_t(u32, entries,	1562	qp->qplib_qp.sq.max_wqe = min_t(u32, entries,
1380	dev_attr->max_qp_wqes + 1);	1563	dev_attr->max_qp_wqes + 1);
		1564	qp->qplib_qp.sq.q_full_delta = qp->qplib_qp.sq.max_wqe -
		1565	qp_attr->cap.max_send_wr;
		1566	/*
		1567	* Reserving one slot for Phantom WQE. Some application can
		1568	* post one extra entry in this case. Allowing this to avoid
		1569	* unexpected Queue full condition
		1570	*/
		1571	qp->qplib_qp.sq.q_full_delta -= 1;
1381	qp->qplib_qp.sq.max_sge = qp_attr->cap.max_send_sge;	1572	qp->qplib_qp.sq.max_sge = qp_attr->cap.max_send_sge;
1382	if (qp->qplib_qp.rq.max_wqe) {	1573	if (qp->qplib_qp.rq.max_wqe) {
1383	entries = roundup_pow_of_two(qp_attr->cap.max_recv_wr);	1574	entries = roundup_pow_of_two(qp_attr->cap.max_recv_wr);
1384	qp->qplib_qp.rq.max_wqe =	1575	qp->qplib_qp.rq.max_wqe =
1385	min_t(u32, entries, dev_attr->max_qp_wqes + 1);	1576	min_t(u32, entries, dev_attr->max_qp_wqes + 1);
		1577	qp->qplib_qp.rq.q_full_delta = qp->qplib_qp.rq.max_wqe -
		1578	qp_attr->cap.max_recv_wr;
1386	qp->qplib_qp.rq.max_sge = qp_attr->cap.max_recv_sge;	1579	qp->qplib_qp.rq.max_sge = qp_attr->cap.max_recv_sge;
1387	} else {	1580	} else {
1388	/* SRQ was used prior, just ignore the RQ caps */	1581	/* SRQ was used prior, just ignore the RQ caps */
@@ -1883,6 +2076,22 @@ static int bnxt_re_copy_wr_payload(struct bnxt_re_dev *rdev, · 494 unmodified lines
1883	return payload_sz;	2076	return payload_sz;
1884	}	2077	}
1885		2078
		2079	static void bnxt_ud_qp_hw_stall_workaround(struct bnxt_re_qp *qp)
		2080	{
		2081	if ((qp->ib_qp.qp_type == IB_QPT_UD \|\|
		2082	qp->ib_qp.qp_type == IB_QPT_GSI \|\|
		2083	qp->ib_qp.qp_type == IB_QPT_RAW_ETHERTYPE) &&
		2084	qp->qplib_qp.wqe_cnt == BNXT_RE_UD_QP_HW_STALL) {
		2085	int qp_attr_mask;
		2086	struct ib_qp_attr qp_attr;
		2087
		2088	qp_attr_mask = IB_QP_STATE;
		2089	qp_attr.qp_state = IB_QPS_RTS;
		2090	bnxt_re_modify_qp(&qp->ib_qp, &qp_attr, qp_attr_mask, NULL);
		2091	qp->qplib_qp.wqe_cnt = 0;
		2092	}
		2093	}
		2094
1886	static int bnxt_re_post_send_shadow_qp(struct bnxt_re_dev *rdev,	2095	static int bnxt_re_post_send_shadow_qp(struct bnxt_re_dev *rdev,
1887	struct bnxt_re_qp *qp,	2096	struct bnxt_re_qp *qp,
1888	struct ib_send_wr *wr)	2097	struct ib_send_wr *wr)
@@ -1928,6 +2137,7 @@ bad: · 39 unmodified lines
1928	wr = wr->next;	2137	wr = wr->next;
1929	}	2138	}
1930	bnxt_qplib_post_send_db(&qp->qplib_qp);	2139	bnxt_qplib_post_send_db(&qp->qplib_qp);
		2140	bnxt_ud_qp_hw_stall_workaround(qp);
1931	spin_unlock_irqrestore(&qp->sq_lock, flags);	2141	spin_unlock_irqrestore(&qp->sq_lock, flags);
1932	return rc;	2142	return rc;
1933	}	2143	}
@@ -2024,6 +2234,7 @@ bad: · 90 unmodified lines
2024	wr = wr->next;	2234	wr = wr->next;
2025	}	2235	}
2026	bnxt_qplib_post_send_db(&qp->qplib_qp);	2236	bnxt_qplib_post_send_db(&qp->qplib_qp);
		2237	bnxt_ud_qp_hw_stall_workaround(qp);
2027	spin_unlock_irqrestore(&qp->sq_lock, flags);	2238	spin_unlock_irqrestore(&qp->sq_lock, flags);
2028		2239
2029	return rc;	2240	return rc;
@@ -2071,7 +2282,10 @@ int bnxt_re_post_recv(struct ib_qp ib_qp, struct ib_recv_wr wr, · 41 unmodified lines
2071	struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);	2282	struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
2072	struct bnxt_qplib_swqe wqe;	2283	struct bnxt_qplib_swqe wqe;
2073	int rc = 0, payload_sz = 0;	2284	int rc = 0, payload_sz = 0;
		2285	unsigned long flags;
		2286	u32 count = 0;
2074		2287
		2288	spin_lock_irqsave(&qp->rq_lock, flags);
2075	while (wr) {	2289	while (wr) {
2076	/* House keeping */	2290	/* House keeping */
2077	memset(&wqe, 0, sizeof(wqe));	2291	memset(&wqe, 0, sizeof(wqe));
@@ -2100,9 +2314,21 @@ int bnxt_re_post_recv(struct ib_qp ib_qp, struct ib_recv_wr wr, · 22 unmodified lines
2100	*bad_wr = wr;	2314	*bad_wr = wr;
2101	break;	2315	break;
2102	}	2316	}
		2317
		2318	/* Ring DB if the RQEs posted reaches a threshold value */
		2319	if (++count >= BNXT_RE_RQ_WQE_THRESHOLD) {
		2320	bnxt_qplib_post_recv_db(&qp->qplib_qp);
		2321	count = 0;
		2322	}
		2323
2103	wr = wr->next;	2324	wr = wr->next;
2104	}	2325	}
2105	bnxt_qplib_post_recv_db(&qp->qplib_qp);	2326
		2327	if (count)
		2328	bnxt_qplib_post_recv_db(&qp->qplib_qp);
		2329
		2330	spin_unlock_irqrestore(&qp->rq_lock, flags);
		2331
2106	return rc;	2332	return rc;
2107	}	2333	}
2108		2334
@@ -2643,12 +2869,36 @@ static void bnxt_re_process_res_ud_wc(struct ib_wc *wc, · 534 unmodified lines
2643	wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;	2869	wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
2644	}	2870	}
2645		2871
		2872	static int send_phantom_wqe(struct bnxt_re_qp *qp)
		2873	{
		2874	struct bnxt_qplib_qp *lib_qp = &qp->qplib_qp;
		2875	unsigned long flags;
		2876	int rc = 0;
		2877
		2878	spin_lock_irqsave(&qp->sq_lock, flags);
		2879
		2880	rc = bnxt_re_bind_fence_mw(lib_qp);
		2881	if (!rc) {
		2882	lib_qp->sq.phantom_wqe_cnt++;
		2883	dev_dbg(&lib_qp->sq.hwq.pdev->dev,
		2884	"qp %#x sq->prod %#x sw_prod %#x phantom_wqe_cnt %d\n",
		2885	lib_qp->id, lib_qp->sq.hwq.prod,
		2886	HWQ_CMP(lib_qp->sq.hwq.prod, &lib_qp->sq.hwq),
		2887	lib_qp->sq.phantom_wqe_cnt);
		2888	}
		2889
		2890	spin_unlock_irqrestore(&qp->sq_lock, flags);
		2891	return rc;
		2892	}
		2893
2646	int bnxt_re_poll_cq(struct ib_cq ib_cq, int num_entries, struct ib_wc wc)	2894	int bnxt_re_poll_cq(struct ib_cq ib_cq, int num_entries, struct ib_wc wc)
2647	{	2895	{
2648	struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);	2896	struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
2649	struct bnxt_re_qp *qp;	2897	struct bnxt_re_qp *qp;
2650	struct bnxt_qplib_cqe *cqe;	2898	struct bnxt_qplib_cqe *cqe;
2651	int i, ncqe, budget;	2899	int i, ncqe, budget;
		2900	struct bnxt_qplib_q *sq;
		2901	struct bnxt_qplib_qp *lib_qp;
2652	u32 tbl_idx;	2902	u32 tbl_idx;
2653	struct bnxt_re_sqp_entries *sqp_entry = NULL;	2903	struct bnxt_re_sqp_entries *sqp_entry = NULL;
2654	unsigned long flags;	2904	unsigned long flags;
@@ -2661,7 +2911,21 @@ int bnxt_re_poll_cq(struct ib_cq ib_cq, int num_entries, struct ib_wc wc) · 6 unmodified lines
2661	}	2911	}
2662	cqe = &cq->cql[0];	2912	cqe = &cq->cql[0];
2663	while (budget) {	2913	while (budget) {
2664	ncqe = bnxt_qplib_poll_cq(&cq->qplib_cq, cqe, budget);	2914	lib_qp = NULL;
		2915	ncqe = bnxt_qplib_poll_cq(&cq->qplib_cq, cqe, budget, &lib_qp);
		2916	if (lib_qp) {
		2917	sq = &lib_qp->sq;
		2918	if (sq->send_phantom) {
		2919	qp = container_of(lib_qp,
		2920	struct bnxt_re_qp, qplib_qp);
		2921	if (send_phantom_wqe(qp) == -ENOMEM)
		2922	dev_err(rdev_to_dev(cq->rdev),
		2923	"Phantom failed! Scheduled to send again\n");
		2924	else
		2925	sq->send_phantom = false;
		2926	}
		2927	}
		2928
2665	if (!ncqe)	2929	if (!ncqe)
2666	break;	2930	break;
2667		2931
@@ -2822,6 +3086,12 @@ int bnxt_re_dereg_mr(struct ib_mr *ib_mr) · 154 unmodified lines
2822	struct bnxt_re_dev *rdev = mr->rdev;	3086	struct bnxt_re_dev *rdev = mr->rdev;
2823	int rc;	3087	int rc;
2824		3088
		3089	rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
		3090	if (rc) {
		3091	dev_err(rdev_to_dev(rdev), "Dereg MR failed: %#x\n", rc);
		3092	return rc;
		3093	}
		3094
2825	if (mr->npages && mr->pages) {	3095	if (mr->npages && mr->pages) {
2826	rc = bnxt_qplib_free_fast_reg_page_list(&rdev->qplib_res,	3096	rc = bnxt_qplib_free_fast_reg_page_list(&rdev->qplib_res,
2827	&mr->qplib_frpl);	3097	&mr->qplib_frpl);
@@ -2829,8 +3099,6 @@ int bnxt_re_dereg_mr(struct ib_mr *ib_mr) · 1 unmodified line
2829	mr->npages = 0;	3099	mr->npages = 0;
2830	mr->pages = NULL;	3100	mr->pages = NULL;
2831	}	3101	}
2832	rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
2833
2834	if (!IS_ERR_OR_NULL(mr->ib_umem))	3102	if (!IS_ERR_OR_NULL(mr->ib_umem))
2835	ib_umem_release(mr->ib_umem);	3103	ib_umem_release(mr->ib_umem);
2836		3104
@@ -2914,97 +3182,52 @@ fail: · 77 unmodified lines
2914	return ERR_PTR(rc);	3182	return ERR_PTR(rc);
2915	}	3183	}
2916		3184
2917	/* Fast Memory Regions */	3185	struct ib_mw bnxt_re_alloc_mw(struct ib_pd ib_pd, enum ib_mw_type type,
2918	struct ib_fmr bnxt_re_alloc_fmr(struct ib_pd ib_pd, int mr_access_flags,	3186	struct ib_udata *udata)
2919	struct ib_fmr_attr *fmr_attr)
2920	{	3187	{
2921	struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);	3188	struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
2922	struct bnxt_re_dev *rdev = pd->rdev;	3189	struct bnxt_re_dev *rdev = pd->rdev;
2923	struct bnxt_re_fmr *fmr;	3190	struct bnxt_re_mw *mw;
2924	int rc;	3191	int rc;
2925		3192
2926	if (fmr_attr->max_pages > MAX_PBL_LVL_2_PGS \|\|	3193	mw = kzalloc(sizeof(*mw), GFP_KERNEL);
2927	fmr_attr->max_maps > rdev->dev_attr.max_map_per_fmr) {	3194	if (!mw)
2928	dev_err(rdev_to_dev(rdev), "Allocate FMR exceeded Max limit");
2929	return ERR_PTR(-ENOMEM);	3195	return ERR_PTR(-ENOMEM);
2930	}	3196	mw->rdev = rdev;
2931	fmr = kzalloc(sizeof(*fmr), GFP_KERNEL);	3197	mw->qplib_mw.pd = &pd->qplib_pd;
2932	if (!fmr)
2933	return ERR_PTR(-ENOMEM);
2934
2935	fmr->rdev = rdev;
2936	fmr->qplib_fmr.pd = &pd->qplib_pd;
2937	fmr->qplib_fmr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
2938		3198
2939	rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &fmr->qplib_fmr);	3199	mw->qplib_mw.type = (type == IB_MW_TYPE_1 ?
2940	if (rc)	3200	CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1 :
		3201	CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B);
		3202	rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mw->qplib_mw);
		3203	if (rc) {
		3204	dev_err(rdev_to_dev(rdev), "Allocate MW failed!");
2941	goto fail;	3205	goto fail;
		3206	}
		3207	mw->ib_mw.rkey = mw->qplib_mw.rkey;
2942		3208
2943	fmr->qplib_fmr.flags = __from_ib_access_flags(mr_access_flags);	3209	atomic_inc(&rdev->mw_count);
2944	fmr->ib_fmr.lkey = fmr->qplib_fmr.lkey;	3210	return &mw->ib_mw;
2945	fmr->ib_fmr.rkey = fmr->ib_fmr.lkey;
2946		3211
2947	atomic_inc(&rdev->mr_count);
2948	return &fmr->ib_fmr;
2949	fail:	3212	fail:
2950	kfree(fmr);	3213	kfree(mw);
2951	return ERR_PTR(rc);	3214	return ERR_PTR(rc);
2952	}	3215	}
2953		3216
2954	int bnxt_re_map_phys_fmr(struct ib_fmr ib_fmr, u64 page_list, int list_len,	3217	int bnxt_re_dealloc_mw(struct ib_mw *ib_mw)
2955	u64 iova)
2956	{	3218	{
2957	struct bnxt_re_fmr *fmr = container_of(ib_fmr, struct bnxt_re_fmr,	3219	struct bnxt_re_mw *mw = container_of(ib_mw, struct bnxt_re_mw, ib_mw);
2958	ib_fmr);	3220	struct bnxt_re_dev *rdev = mw->rdev;
2959	struct bnxt_re_dev *rdev = fmr->rdev;
2960	int rc;	3221	int rc;
2961		3222
2962	fmr->qplib_fmr.va = iova;	3223	rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mw->qplib_mw);
2963	fmr->qplib_fmr.total_size = list_len * PAGE_SIZE;	3224	if (rc) {
2964		3225	dev_err(rdev_to_dev(rdev), "Free MW failed: %#x\n", rc);
2965	rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &fmr->qplib_fmr, page_list,	3226	return rc;
2966	list_len, true);
2967	if (rc)
2968	dev_err(rdev_to_dev(rdev), "Failed to map FMR for lkey = 0x%x!",
2969	fmr->ib_fmr.lkey);
2970	return rc;
2971	}
2972
2973	int bnxt_re_unmap_fmr(struct list_head *fmr_list)
2974	{
2975	struct bnxt_re_dev *rdev;
2976	struct bnxt_re_fmr *fmr;
2977	struct ib_fmr *ib_fmr;
2978	int rc = 0;
2979
2980	/* Validate each FMRs inside the fmr_list */
2981	list_for_each_entry(ib_fmr, fmr_list, list) {
2982	fmr = container_of(ib_fmr, struct bnxt_re_fmr, ib_fmr);
2983	rdev = fmr->rdev;
2984
2985	if (rdev) {
2986	rc = bnxt_qplib_dereg_mrw(&rdev->qplib_res,
2987	&fmr->qplib_fmr, true);
2988	if (rc)
2989	break;
2990	}
2991	}	3227	}
2992	return rc;
2993	}
2994
2995	int bnxt_re_dealloc_fmr(struct ib_fmr *ib_fmr)
2996	{
2997	struct bnxt_re_fmr *fmr = container_of(ib_fmr, struct bnxt_re_fmr,
2998	ib_fmr);
2999	struct bnxt_re_dev *rdev = fmr->rdev;
3000	int rc;
3001		3228
3002	rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &fmr->qplib_fmr);	3229	kfree(mw);
3003	if (rc)	3230	atomic_dec(&rdev->mw_count);
3004	dev_err(rdev_to_dev(rdev), "Failed to free FMR");
3005
3006	kfree(fmr);
3007	atomic_dec(&rdev->mr_count);
3008	return rc;	3231	return rc;
3009	}	3232	}
3010		3233

drivers/infiniband/hw/bnxt_re/ib_verbs.h+16−6

 	u32			refcnt;
 };
+#define BNXT_RE_FENCE_BYTES	64
+struct bnxt_re_fence_data {
+	u32 size;
+	u8 va[BNXT_RE_FENCE_BYTES];
+	dma_addr_t dma_addr;
+	struct bnxt_re_mr *mr;
+	struct ib_mw *mw;
+	struct bnxt_qplib_swqe bind_wqe;
+	u32 bind_rkey;
+};
 struct bnxt_re_pd {
 	struct bnxt_re_dev	*rdev;
 	struct ib_pd		ib_pd;
 	struct bnxt_qplib_pd	qplib_pd;
 	struct bnxt_qplib_dpi	dpi;
+	struct bnxt_re_fence_data fence;
 };
 struct bnxt_re_ah {
 	struct bnxt_re_dev	*rdev;
 	struct ib_qp		ib_qp;
 	spinlock_t		sq_lock;	/* protect sq */
+	spinlock_t		rq_lock;	/* protect rq */
 	struct bnxt_qplib_qp	qplib_qp;
 	struct ib_umem		*sumem;
 	struct ib_umem		*rumem;
 struct ib_mr *bnxt_re_alloc_mr(struct ib_pd *ib_pd, enum ib_mr_type mr_type,
 			       u32 max_num_sg);
 int bnxt_re_dereg_mr(struct ib_mr *mr);
-struct ib_fmr *bnxt_re_alloc_fmr(struct ib_pd *pd, int mr_access_flags,
+struct ib_mw *bnxt_re_alloc_mw(struct ib_pd *ib_pd, enum ib_mw_type type,
-				 struct ib_fmr_attr *fmr_attr);
+			       struct ib_udata *udata);
-int bnxt_re_map_phys_fmr(struct ib_fmr *fmr, u64 *page_list, int list_len,
+int bnxt_re_dealloc_mw(struct ib_mw *mw);
-			 u64 iova);
-int bnxt_re_unmap_fmr(struct list_head *fmr_list);
-int bnxt_re_dealloc_fmr(struct ib_fmr *fmr);
 struct ib_mr *bnxt_re_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
 				  u64 virt_addr, int mr_access_flags,
 				  struct ib_udata *udata);

drivers/infiniband/hw/bnxt_re/main.c+0−4

 	ibdev->dereg_mr			= bnxt_re_dereg_mr;
 	ibdev->alloc_mr			= bnxt_re_alloc_mr;
 	ibdev->map_mr_sg		= bnxt_re_map_mr_sg;
-	ibdev->alloc_fmr		= bnxt_re_alloc_fmr;
-	ibdev->map_phys_fmr		= bnxt_re_map_phys_fmr;
-	ibdev->unmap_fmr		= bnxt_re_unmap_fmr;
-	ibdev->dealloc_fmr		= bnxt_re_dealloc_fmr;
 	ibdev->reg_user_mr		= bnxt_re_reg_user_mr;
 	ibdev->alloc_ucontext		= bnxt_re_alloc_ucontext;

drivers/infiniband/hw/bnxt_re/qplib_fp.c+199−185

@@ -284,7 +284,7 @@ int bnxt_qplib_create_qp1(struct bnxt_qplib_res res, struct bnxt_qplib_qp qp) · 283 unmodified lines
284	{	284	{
285	struct bnxt_qplib_rcfw *rcfw = res->rcfw;	285	struct bnxt_qplib_rcfw *rcfw = res->rcfw;
286	struct cmdq_create_qp1 req;	286	struct cmdq_create_qp1 req;
287	struct creq_create_qp1_resp *resp;	287	struct creq_create_qp1_resp resp;
288	struct bnxt_qplib_pbl *pbl;	288	struct bnxt_qplib_pbl *pbl;
289	struct bnxt_qplib_q *sq = &qp->sq;	289	struct bnxt_qplib_q *sq = &qp->sq;
290	struct bnxt_qplib_q *rq = &qp->rq;	290	struct bnxt_qplib_q *rq = &qp->rq;
@@ -394,31 +394,12 @@ int bnxt_qplib_create_qp1(struct bnxt_qplib_res res, struct bnxt_qplib_qp qp) · 103 unmodified lines
394		394
395	req.pd_id = cpu_to_le32(qp->pd->id);	395	req.pd_id = cpu_to_le32(qp->pd->id);
396		396
397	resp = (struct creq_create_qp1_resp *)	397	rc = bnxt_qplib_rcfw_send_message(rcfw, (void *)&req,
398	bnxt_qplib_rcfw_send_message(rcfw, (void *)&req,	398	(void *)&resp, NULL, 0);
399	NULL, 0);	399	if (rc)
400	if (!resp) {
401	dev_err(&res->pdev->dev, "QPLIB: FP: CREATE_QP1 send failed");
402	rc = -EINVAL;
403	goto fail;
404	}
405	if (!bnxt_qplib_rcfw_wait_for_resp(rcfw, le16_to_cpu(req.cookie))) {
406	/* Cmd timed out */
407	dev_err(&rcfw->pdev->dev, "QPLIB: FP: CREATE_QP1 timed out");
408	rc = -ETIMEDOUT;
409	goto fail;
410	}
411	if (resp->status \|\|
412	le16_to_cpu(resp->cookie) != le16_to_cpu(req.cookie)) {
413	dev_err(&rcfw->pdev->dev, "QPLIB: FP: CREATE_QP1 failed ");
414	dev_err(&rcfw->pdev->dev,
415	"QPLIB: with status 0x%x cmdq 0x%x resp 0x%x",
416	resp->status, le16_to_cpu(req.cookie),
417	le16_to_cpu(resp->cookie));
418	rc = -EINVAL;
419	goto fail;	400	goto fail;
420	}	401
421	qp->id = le32_to_cpu(resp->xid);	402	qp->id = le32_to_cpu(resp.xid);
422	qp->cur_qp_state = CMDQ_MODIFY_QP_NEW_STATE_RESET;	403	qp->cur_qp_state = CMDQ_MODIFY_QP_NEW_STATE_RESET;
423	sq->flush_in_progress = false;	404	sq->flush_in_progress = false;
424	rq->flush_in_progress = false;	405	rq->flush_in_progress = false;
@@ -442,7 +423,7 @@ int bnxt_qplib_create_qp(struct bnxt_qplib_res res, struct bnxt_qplib_qp qp) · 17 unmodified lines
442	struct bnxt_qplib_rcfw *rcfw = res->rcfw;	423	struct bnxt_qplib_rcfw *rcfw = res->rcfw;
443	struct sq_send hw_sq_send_hdr, *hw_sq_send_ptr;	424	struct sq_send hw_sq_send_hdr, *hw_sq_send_ptr;
444	struct cmdq_create_qp req;	425	struct cmdq_create_qp req;
445	struct creq_create_qp_resp *resp;	426	struct creq_create_qp_resp resp;
446	struct bnxt_qplib_pbl *pbl;	427	struct bnxt_qplib_pbl *pbl;
447	struct sq_psn_search **psn_search_ptr;	428	struct sq_psn_search **psn_search_ptr;
448	unsigned long int psn_search, poff = 0;	429	unsigned long int psn_search, poff = 0;
@@ -627,31 +608,12 @@ int bnxt_qplib_create_qp(struct bnxt_qplib_res res, struct bnxt_qplib_qp qp) · 178 unmodified lines
627	}	608	}
628	req.pd_id = cpu_to_le32(qp->pd->id);	609	req.pd_id = cpu_to_le32(qp->pd->id);
629		610
630	resp = (struct creq_create_qp_resp *)	611	rc = bnxt_qplib_rcfw_send_message(rcfw, (void *)&req,
631	bnxt_qplib_rcfw_send_message(rcfw, (void *)&req,	612	(void *)&resp, NULL, 0);
632	NULL, 0);	613	if (rc)
633	if (!resp) {
634	dev_err(&rcfw->pdev->dev, "QPLIB: FP: CREATE_QP send failed");
635	rc = -EINVAL;
636	goto fail;
637	}
638	if (!bnxt_qplib_rcfw_wait_for_resp(rcfw, le16_to_cpu(req.cookie))) {
639	/* Cmd timed out */
640	dev_err(&rcfw->pdev->dev, "QPLIB: FP: CREATE_QP timed out");
641	rc = -ETIMEDOUT;
642	goto fail;
643	}
644	if (resp->status \|\|
645	le16_to_cpu(resp->cookie) != le16_to_cpu(req.cookie)) {
646	dev_err(&rcfw->pdev->dev, "QPLIB: FP: CREATE_QP failed ");
647	dev_err(&rcfw->pdev->dev,
648	"QPLIB: with status 0x%x cmdq 0x%x resp 0x%x",
649	resp->status, le16_to_cpu(req.cookie),
650	le16_to_cpu(resp->cookie));
651	rc = -EINVAL;
652	goto fail;	614	goto fail;
653	}	615
654	qp->id = le32_to_cpu(resp->xid);	616	qp->id = le32_to_cpu(resp.xid);
655	qp->cur_qp_state = CMDQ_MODIFY_QP_NEW_STATE_RESET;	617	qp->cur_qp_state = CMDQ_MODIFY_QP_NEW_STATE_RESET;
656	sq->flush_in_progress = false;	618	sq->flush_in_progress = false;
657	rq->flush_in_progress = false;	619	rq->flush_in_progress = false;
@@ -769,10 +731,11 @@ int bnxt_qplib_modify_qp(struct bnxt_qplib_res res, struct bnxt_qplib_qp qp) · 111 unmodified lines
769	{	731	{
770	struct bnxt_qplib_rcfw *rcfw = res->rcfw;	732	struct bnxt_qplib_rcfw *rcfw = res->rcfw;
771	struct cmdq_modify_qp req;	733	struct cmdq_modify_qp req;
772	struct creq_modify_qp_resp *resp;	734	struct creq_modify_qp_resp resp;
773	u16 cmd_flags = 0, pkey;	735	u16 cmd_flags = 0, pkey;
774	u32 temp32[4];	736	u32 temp32[4];
775	u32 bmask;	737	u32 bmask;
		738	int rc;
776		739
777	RCFW_CMD_PREP(req, MODIFY_QP, cmd_flags);	740	RCFW_CMD_PREP(req, MODIFY_QP, cmd_flags);
778		741
@@ -862,27 +825,10 @@ int bnxt_qplib_modify_qp(struct bnxt_qplib_res res, struct bnxt_qplib_qp qp) · 83 unmodified lines
862		825
863	req.vlan_pcp_vlan_dei_vlan_id = cpu_to_le16(qp->vlan_id);	826	req.vlan_pcp_vlan_dei_vlan_id = cpu_to_le16(qp->vlan_id);
864		827
865	resp = (struct creq_modify_qp_resp *)	828	rc = bnxt_qplib_rcfw_send_message(rcfw, (void *)&req,
866	bnxt_qplib_rcfw_send_message(rcfw, (void *)&req,	829	(void *)&resp, NULL, 0);
867	NULL, 0);	830	if (rc)
868	if (!resp) {	831	return rc;
869	dev_err(&rcfw->pdev->dev, "QPLIB: FP: MODIFY_QP send failed");
870	return -EINVAL;
871	}
872	if (!bnxt_qplib_rcfw_wait_for_resp(rcfw, le16_to_cpu(req.cookie))) {
873	/* Cmd timed out */
874	dev_err(&rcfw->pdev->dev, "QPLIB: FP: MODIFY_QP timed out");
875	return -ETIMEDOUT;
876	}
877	if (resp->status \|\|
878	le16_to_cpu(resp->cookie) != le16_to_cpu(req.cookie)) {
879	dev_err(&rcfw->pdev->dev, "QPLIB: FP: MODIFY_QP failed ");
880	dev_err(&rcfw->pdev->dev,
881	"QPLIB: with status 0x%x cmdq 0x%x resp 0x%x",
882	resp->status, le16_to_cpu(req.cookie),
883	le16_to_cpu(resp->cookie));
884	return -EINVAL;
885	}
886	qp->cur_qp_state = qp->state;	832	qp->cur_qp_state = qp->state;
887	return 0;	833	return 0;
888	}	834	}
@@ -891,37 +837,26 @@ int bnxt_qplib_query_qp(struct bnxt_qplib_res res, struct bnxt_qplib_qp qp) · 2 unmodified lines
891	{	837	{
892	struct bnxt_qplib_rcfw *rcfw = res->rcfw;	838	struct bnxt_qplib_rcfw *rcfw = res->rcfw;
893	struct cmdq_query_qp req;	839	struct cmdq_query_qp req;
894	struct creq_query_qp_resp *resp;	840	struct creq_query_qp_resp resp;
		841	struct bnxt_qplib_rcfw_sbuf *sbuf;
895	struct creq_query_qp_resp_sb *sb;	842	struct creq_query_qp_resp_sb *sb;
896	u16 cmd_flags = 0;	843	u16 cmd_flags = 0;
897	u32 temp32[4];	844	u32 temp32[4];
898	int i;	845	int i, rc = 0;
899		846
900	RCFW_CMD_PREP(req, QUERY_QP, cmd_flags);	847	RCFW_CMD_PREP(req, QUERY_QP, cmd_flags);
901		848
		849	sbuf = bnxt_qplib_rcfw_alloc_sbuf(rcfw, sizeof(*sb));
		850	if (!sbuf)
		851	return -ENOMEM;
		852	sb = sbuf->sb;
		853
902	req.qp_cid = cpu_to_le32(qp->id);	854	req.qp_cid = cpu_to_le32(qp->id);
903	req.resp_size = sizeof(*sb) / BNXT_QPLIB_CMDQE_UNITS;	855	req.resp_size = sizeof(*sb) / BNXT_QPLIB_CMDQE_UNITS;
904	resp = (struct creq_query_qp_resp *)	856	rc = bnxt_qplib_rcfw_send_message(rcfw, (void )&req, (void )&resp,
905	bnxt_qplib_rcfw_send_message(rcfw, (void *)&req,	857	(void *)sbuf, 0);
906	(void **)&sb, 0);	858	if (rc)
907	if (!resp) {	859	goto bail;
908	dev_err(&rcfw->pdev->dev, "QPLIB: FP: QUERY_QP send failed");
909	return -EINVAL;
910	}
911	if (!bnxt_qplib_rcfw_wait_for_resp(rcfw, le16_to_cpu(req.cookie))) {
912	/* Cmd timed out */
913	dev_err(&rcfw->pdev->dev, "QPLIB: FP: QUERY_QP timed out");
914	return -ETIMEDOUT;
915	}
916	if (resp->status \|\|
917	le16_to_cpu(resp->cookie) != le16_to_cpu(req.cookie)) {
918	dev_err(&rcfw->pdev->dev, "QPLIB: FP: QUERY_QP failed ");
919	dev_err(&rcfw->pdev->dev,
920	"QPLIB: with status 0x%x cmdq 0x%x resp 0x%x",
921	resp->status, le16_to_cpu(req.cookie),
922	le16_to_cpu(resp->cookie));
923	return -EINVAL;
924	}
925	/* Extract the context from the side buffer */	860	/* Extract the context from the side buffer */
926	qp->state = sb->en_sqd_async_notify_state &	861	qp->state = sb->en_sqd_async_notify_state &
927	CREQ_QUERY_QP_RESP_SB_STATE_MASK;	862	CREQ_QUERY_QP_RESP_SB_STATE_MASK;
@@ -976,7 +911,9 @@ int bnxt_qplib_query_qp(struct bnxt_qplib_res res, struct bnxt_qplib_qp qp) · 48 unmodified lines
976	qp->dest_qpn = le32_to_cpu(sb->dest_qp_id);	911	qp->dest_qpn = le32_to_cpu(sb->dest_qp_id);
977	memcpy(qp->smac, sb->src_mac, 6);	912	memcpy(qp->smac, sb->src_mac, 6);
978	qp->vlan_id = le16_to_cpu(sb->vlan_pcp_vlan_dei_vlan_id);	913	qp->vlan_id = le16_to_cpu(sb->vlan_pcp_vlan_dei_vlan_id);
979	return 0;	914	bail:
		915	bnxt_qplib_rcfw_free_sbuf(rcfw, sbuf);
		916	return rc;
980	}	917	}
981		918
982	static void __clean_cq(struct bnxt_qplib_cq *cq, u64 qp)	919	static void __clean_cq(struct bnxt_qplib_cq *cq, u64 qp)
@@ -1021,34 +958,18 @@ int bnxt_qplib_destroy_qp(struct bnxt_qplib_res *res, · 38 unmodified lines
1021	{	958	{
1022	struct bnxt_qplib_rcfw *rcfw = res->rcfw;	959	struct bnxt_qplib_rcfw *rcfw = res->rcfw;
1023	struct cmdq_destroy_qp req;	960	struct cmdq_destroy_qp req;
1024	struct creq_destroy_qp_resp *resp;	961	struct creq_destroy_qp_resp resp;
1025	unsigned long flags;	962	unsigned long flags;
1026	u16 cmd_flags = 0;	963	u16 cmd_flags = 0;
		964	int rc;
1027		965
1028	RCFW_CMD_PREP(req, DESTROY_QP, cmd_flags);	966	RCFW_CMD_PREP(req, DESTROY_QP, cmd_flags);
1029		967
1030	req.qp_cid = cpu_to_le32(qp->id);	968	req.qp_cid = cpu_to_le32(qp->id);
1031	resp = (struct creq_destroy_qp_resp *)	969	rc = bnxt_qplib_rcfw_send_message(rcfw, (void *)&req,
1032	bnxt_qplib_rcfw_send_message(rcfw, (void *)&req,	970	(void *)&resp, NULL, 0);
1033	NULL, 0);	971	if (rc)
1034	if (!resp) {	972	return rc;
1035	dev_err(&rcfw->pdev->dev, "QPLIB: FP: DESTROY_QP send failed");
1036	return -EINVAL;
1037	}
1038	if (!bnxt_qplib_rcfw_wait_for_resp(rcfw, le16_to_cpu(req.cookie))) {
1039	/* Cmd timed out */
1040	dev_err(&rcfw->pdev->dev, "QPLIB: FP: DESTROY_QP timed out");
1041	return -ETIMEDOUT;
1042	}
1043	if (resp->status \|\|
1044	le16_to_cpu(resp->cookie) != le16_to_cpu(req.cookie)) {
1045	dev_err(&rcfw->pdev->dev, "QPLIB: FP: DESTROY_QP failed ");
1046	dev_err(&rcfw->pdev->dev,
1047	"QPLIB: with status 0x%x cmdq 0x%x resp 0x%x",
1048	resp->status, le16_to_cpu(req.cookie),
1049	le16_to_cpu(resp->cookie));
1050	return -EINVAL;
1051	}
1052		973
1053	/* Must walk the associated CQs to nullified the QP ptr */	974	/* Must walk the associated CQs to nullified the QP ptr */
1054	spin_lock_irqsave(&qp->scq->hwq.lock, flags);	975	spin_lock_irqsave(&qp->scq->hwq.lock, flags);
@@ -1162,8 +1083,12 @@ int bnxt_qplib_post_send(struct bnxt_qplib_qp *qp, · 107 unmodified lines
1162	rc = -EINVAL;	1083	rc = -EINVAL;
1163	goto done;	1084	goto done;
1164	}	1085	}
1165	if (HWQ_CMP((sq->hwq.prod + 1), &sq->hwq) ==	1086
1166	HWQ_CMP(sq->hwq.cons, &sq->hwq)) {	1087	if (bnxt_qplib_queue_full(sq)) {
		1088	dev_err(&sq->hwq.pdev->dev,
		1089	"QPLIB: prod = %#x cons = %#x qdepth = %#x delta = %#x",
		1090	sq->hwq.prod, sq->hwq.cons, sq->hwq.max_elements,
		1091	sq->q_full_delta);
1167	rc = -ENOMEM;	1092	rc = -ENOMEM;
1168	goto done;	1093	goto done;
1169	}	1094	}
@@ -1373,6 +1298,9 @@ int bnxt_qplib_post_send(struct bnxt_qplib_qp *qp, · 203 unmodified lines
1373	}	1298	}
1374		1299
1375	sq->hwq.prod++;	1300	sq->hwq.prod++;
		1301
		1302	qp->wqe_cnt++;
		1303
1376	done:	1304	done:
1377	return rc;	1305	return rc;
1378	}	1306	}
@@ -1411,8 +1339,7 @@ int bnxt_qplib_post_recv(struct bnxt_qplib_qp *qp, · 32 unmodified lines
1411	rc = -EINVAL;	1339	rc = -EINVAL;
1412	goto done;	1340	goto done;
1413	}	1341	}
1414	if (HWQ_CMP((rq->hwq.prod + 1), &rq->hwq) ==	1342	if (bnxt_qplib_queue_full(rq)) {
1415	HWQ_CMP(rq->hwq.cons, &rq->hwq)) {
1416	dev_err(&rq->hwq.pdev->dev,	1343	dev_err(&rq->hwq.pdev->dev,
1417	"QPLIB: FP: QP (0x%x) RQ is full!", qp->id);	1344	"QPLIB: FP: QP (0x%x) RQ is full!", qp->id);
1418	rc = -EINVAL;	1345	rc = -EINVAL;
@@ -1483,7 +1410,7 @@ int bnxt_qplib_create_cq(struct bnxt_qplib_res res, struct bnxt_qplib_cq cq) · 64 unmodified lines
1483	{	1410	{
1484	struct bnxt_qplib_rcfw *rcfw = res->rcfw;	1411	struct bnxt_qplib_rcfw *rcfw = res->rcfw;
1485	struct cmdq_create_cq req;	1412	struct cmdq_create_cq req;
1486	struct creq_create_cq_resp *resp;	1413	struct creq_create_cq_resp resp;
1487	struct bnxt_qplib_pbl *pbl;	1414	struct bnxt_qplib_pbl *pbl;
1488	u16 cmd_flags = 0;	1415	u16 cmd_flags = 0;
1489	int rc;	1416	int rc;
@@ -1525,30 +1452,12 @@ int bnxt_qplib_create_cq(struct bnxt_qplib_res res, struct bnxt_qplib_cq cq) · 35 unmodified lines
1525	(cq->cnq_hw_ring_id & CMDQ_CREATE_CQ_CNQ_ID_MASK) <<	1452	(cq->cnq_hw_ring_id & CMDQ_CREATE_CQ_CNQ_ID_MASK) <<
1526	CMDQ_CREATE_CQ_CNQ_ID_SFT);	1453	CMDQ_CREATE_CQ_CNQ_ID_SFT);
1527		1454
1528	resp = (struct creq_create_cq_resp *)	1455	rc = bnxt_qplib_rcfw_send_message(rcfw, (void *)&req,
1529	bnxt_qplib_rcfw_send_message(rcfw, (void *)&req,	1456	(void *)&resp, NULL, 0);
1530	NULL, 0);	1457	if (rc)
1531	if (!resp) {
1532	dev_err(&rcfw->pdev->dev, "QPLIB: FP: CREATE_CQ send failed");
1533	return -EINVAL;
1534	}
1535	if (!bnxt_qplib_rcfw_wait_for_resp(rcfw, le16_to_cpu(req.cookie))) {
1536	/* Cmd timed out */
1537	dev_err(&rcfw->pdev->dev, "QPLIB: FP: CREATE_CQ timed out");
1538	rc = -ETIMEDOUT;
1539	goto fail;
1540	}
1541	if (resp->status \|\|
1542	le16_to_cpu(resp->cookie) != le16_to_cpu(req.cookie)) {
1543	dev_err(&rcfw->pdev->dev, "QPLIB: FP: CREATE_CQ failed ");
1544	dev_err(&rcfw->pdev->dev,
1545	"QPLIB: with status 0x%x cmdq 0x%x resp 0x%x",
1546	resp->status, le16_to_cpu(req.cookie),
1547	le16_to_cpu(resp->cookie));
1548	rc = -EINVAL;
1549	goto fail;	1458	goto fail;
1550	}	1459
1551	cq->id = le32_to_cpu(resp->xid);	1460	cq->id = le32_to_cpu(resp.xid);
1552	cq->dbr_base = res->dpi_tbl.dbr_bar_reg_iomem;	1461	cq->dbr_base = res->dpi_tbl.dbr_bar_reg_iomem;
1553	cq->period = BNXT_QPLIB_QUEUE_START_PERIOD;	1462	cq->period = BNXT_QPLIB_QUEUE_START_PERIOD;
1554	init_waitqueue_head(&cq->waitq);	1463	init_waitqueue_head(&cq->waitq);
@@ -1566,33 +1475,17 @@ int bnxt_qplib_destroy_cq(struct bnxt_qplib_res res, struct bnxt_qplib_cq cq) · 11 unmodified lines
1566	{	1475	{
1567	struct bnxt_qplib_rcfw *rcfw = res->rcfw;	1476	struct bnxt_qplib_rcfw *rcfw = res->rcfw;
1568	struct cmdq_destroy_cq req;	1477	struct cmdq_destroy_cq req;
1569	struct creq_destroy_cq_resp *resp;	1478	struct creq_destroy_cq_resp resp;
1570	u16 cmd_flags = 0;	1479	u16 cmd_flags = 0;
		1480	int rc;
1571		1481
1572	RCFW_CMD_PREP(req, DESTROY_CQ, cmd_flags);	1482	RCFW_CMD_PREP(req, DESTROY_CQ, cmd_flags);
1573		1483
1574	req.cq_cid = cpu_to_le32(cq->id);	1484	req.cq_cid = cpu_to_le32(cq->id);
1575	resp = (struct creq_destroy_cq_resp *)	1485	rc = bnxt_qplib_rcfw_send_message(rcfw, (void *)&req,
1576	bnxt_qplib_rcfw_send_message(rcfw, (void *)&req,	1486	(void *)&resp, NULL, 0);
1577	NULL, 0);	1487	if (rc)
1578	if (!resp) {	1488	return rc;
1579	dev_err(&rcfw->pdev->dev, "QPLIB: FP: DESTROY_CQ send failed");
1580	return -EINVAL;
1581	}
1582	if (!bnxt_qplib_rcfw_wait_for_resp(rcfw, le16_to_cpu(req.cookie))) {
1583	/* Cmd timed out */
1584	dev_err(&rcfw->pdev->dev, "QPLIB: FP: DESTROY_CQ timed out");
1585	return -ETIMEDOUT;
1586	}
1587	if (resp->status \|\|
1588	le16_to_cpu(resp->cookie) != le16_to_cpu(req.cookie)) {
1589	dev_err(&rcfw->pdev->dev, "QPLIB: FP: DESTROY_CQ failed ");
1590	dev_err(&rcfw->pdev->dev,
1591	"QPLIB: with status 0x%x cmdq 0x%x resp 0x%x",
1592	resp->status, le16_to_cpu(req.cookie),
1593	le16_to_cpu(resp->cookie));
1594	return -EINVAL;
1595	}
1596	bnxt_qplib_free_hwq(res->pdev, &cq->hwq);	1489	bnxt_qplib_free_hwq(res->pdev, &cq->hwq);
1597	return 0;	1490	return 0;
1598	}	1491	}
@@ -1664,14 +1557,113 @@ static int __flush_rq(struct bnxt_qplib_q rq, struct bnxt_qplib_qp qp, · 65 unmodified lines
1664	return rc;	1557	return rc;
1665	}	1558	}
1666		1559
		1560	/* Note: SQE is valid from sw_sq_cons up to cqe_sq_cons (exclusive)
		1561	* CQE is track from sw_cq_cons to max_element but valid only if VALID=1
		1562	*/
		1563	static int do_wa9060(struct bnxt_qplib_qp qp, struct bnxt_qplib_cq cq,
		1564	u32 cq_cons, u32 sw_sq_cons, u32 cqe_sq_cons)
		1565	{
		1566	struct bnxt_qplib_q *sq = &qp->sq;
		1567	struct bnxt_qplib_swq *swq;
		1568	u32 peek_sw_cq_cons, peek_raw_cq_cons, peek_sq_cons_idx;
		1569	struct cq_base peek_hwcqe, *peek_hw_cqe_ptr;
		1570	struct cq_req *peek_req_hwcqe;
		1571	struct bnxt_qplib_qp *peek_qp;
		1572	struct bnxt_qplib_q *peek_sq;
		1573	int i, rc = 0;
		1574
		1575	/* Normal mode */
		1576	/* Check for the psn_search marking before completing */
		1577	swq = &sq->swq[sw_sq_cons];
		1578	if (swq->psn_search &&
		1579	le32_to_cpu(swq->psn_search->flags_next_psn) & 0x80000000) {
		1580	/* Unmark */
		1581	swq->psn_search->flags_next_psn = cpu_to_le32
		1582	(le32_to_cpu(swq->psn_search->flags_next_psn)
		1583	& ~0x80000000);
		1584	dev_dbg(&cq->hwq.pdev->dev,
		1585	"FP: Process Req cq_cons=0x%x qp=0x%x sq cons sw=0x%x cqe=0x%x marked!\n",
		1586	cq_cons, qp->id, sw_sq_cons, cqe_sq_cons);
		1587	sq->condition = true;
		1588	sq->send_phantom = true;
		1589
		1590	/* TODO: Only ARM if the previous SQE is ARMALL */
		1591	bnxt_qplib_arm_cq(cq, DBR_DBR_TYPE_CQ_ARMALL);
		1592
		1593	rc = -EAGAIN;
		1594	goto out;
		1595	}
		1596	if (sq->condition) {
		1597	/* Peek at the completions */
		1598	peek_raw_cq_cons = cq->hwq.cons;
		1599	peek_sw_cq_cons = cq_cons;
		1600	i = cq->hwq.max_elements;
		1601	while (i--) {
		1602	peek_sw_cq_cons = HWQ_CMP((peek_sw_cq_cons), &cq->hwq);
		1603	peek_hw_cqe_ptr = (struct cq_base **)cq->hwq.pbl_ptr;
		1604	peek_hwcqe = &peek_hw_cqe_ptr[CQE_PG(peek_sw_cq_cons)]
		1605	[CQE_IDX(peek_sw_cq_cons)];
		1606	/* If the next hwcqe is VALID */
		1607	if (CQE_CMP_VALID(peek_hwcqe, peek_raw_cq_cons,
		1608	cq->hwq.max_elements)) {
		1609	/* If the next hwcqe is a REQ */
		1610	if ((peek_hwcqe->cqe_type_toggle &
		1611	CQ_BASE_CQE_TYPE_MASK) ==
		1612	CQ_BASE_CQE_TYPE_REQ) {
		1613	peek_req_hwcqe = (struct cq_req *)
		1614	peek_hwcqe;
		1615	peek_qp = (struct bnxt_qplib_qp *)
		1616	((unsigned long)
		1617	le64_to_cpu
		1618	(peek_req_hwcqe->qp_handle));
		1619	peek_sq = &peek_qp->sq;
		1620	peek_sq_cons_idx = HWQ_CMP(le16_to_cpu(
		1621	peek_req_hwcqe->sq_cons_idx) - 1
		1622	, &sq->hwq);
		1623	/* If the hwcqe's sq's wr_id matches */
		1624	if (peek_sq == sq &&
		1625	sq->swq[peek_sq_cons_idx].wr_id ==
		1626	BNXT_QPLIB_FENCE_WRID) {
		1627	/*
		1628	* Unbreak only if the phantom
		1629	* comes back
		1630	*/
		1631	dev_dbg(&cq->hwq.pdev->dev,
		1632	"FP:Got Phantom CQE");
		1633	sq->condition = false;
		1634	sq->single = true;
		1635	rc = 0;
		1636	goto out;
		1637	}
		1638	}
		1639	/* Valid but not the phantom, so keep looping */
		1640	} else {
		1641	/* Not valid yet, just exit and wait */
		1642	rc = -EINVAL;
		1643	goto out;
		1644	}
		1645	peek_sw_cq_cons++;
		1646	peek_raw_cq_cons++;
		1647	}
		1648	dev_err(&cq->hwq.pdev->dev,
		1649	"Should not have come here! cq_cons=0x%x qp=0x%x sq cons sw=0x%x hw=0x%x",
		1650	cq_cons, qp->id, sw_sq_cons, cqe_sq_cons);
		1651	rc = -EINVAL;
		1652	}
		1653	out:
		1654	return rc;
		1655	}
		1656
1667	static int bnxt_qplib_cq_process_req(struct bnxt_qplib_cq *cq,	1657	static int bnxt_qplib_cq_process_req(struct bnxt_qplib_cq *cq,
1668	struct cq_req *hwcqe,	1658	struct cq_req *hwcqe,
1669	struct bnxt_qplib_cqe *pcqe, int budget)	1659	struct bnxt_qplib_cqe *pcqe, int budget,
		1660	u32 cq_cons, struct bnxt_qplib_qp **lib_qp)
1670	{	1661	{
1671	struct bnxt_qplib_qp *qp;	1662	struct bnxt_qplib_qp *qp;
1672	struct bnxt_qplib_q *sq;	1663	struct bnxt_qplib_q *sq;
1673	struct bnxt_qplib_cqe *cqe;	1664	struct bnxt_qplib_cqe *cqe;
1674	u32 sw_cons, cqe_cons;	1665	u32 sw_sq_cons, cqe_sq_cons;
		1666	struct bnxt_qplib_swq *swq;
1675	int rc = 0;	1667	int rc = 0;
1676		1668
1677	qp = (struct bnxt_qplib_qp *)((unsigned long)	1669	qp = (struct bnxt_qplib_qp *)((unsigned long)
@@ -1683,13 +1675,13 @@ static int bnxt_qplib_cq_process_req(struct bnxt_qplib_cq *cq, · 5 unmodified lines
1683	}	1675	}
1684	sq = &qp->sq;	1676	sq = &qp->sq;
1685		1677
1686	cqe_cons = HWQ_CMP(le16_to_cpu(hwcqe->sq_cons_idx), &sq->hwq);	1678	cqe_sq_cons = HWQ_CMP(le16_to_cpu(hwcqe->sq_cons_idx), &sq->hwq);
1687	if (cqe_cons > sq->hwq.max_elements) {	1679	if (cqe_sq_cons > sq->hwq.max_elements) {
1688	dev_err(&cq->hwq.pdev->dev,	1680	dev_err(&cq->hwq.pdev->dev,
1689	"QPLIB: FP: CQ Process req reported ");	1681	"QPLIB: FP: CQ Process req reported ");
1690	dev_err(&cq->hwq.pdev->dev,	1682	dev_err(&cq->hwq.pdev->dev,
1691	"QPLIB: sq_cons_idx 0x%x which exceeded max 0x%x",	1683	"QPLIB: sq_cons_idx 0x%x which exceeded max 0x%x",
1692	cqe_cons, sq->hwq.max_elements);	1684	cqe_sq_cons, sq->hwq.max_elements);
1693	return -EINVAL;	1685	return -EINVAL;
1694	}	1686	}
1695	/* If we were in the middle of flushing the SQ, continue */	1687	/* If we were in the middle of flushing the SQ, continue */
@@ -1698,53 +1690,74 @@ static int bnxt_qplib_cq_process_req(struct bnxt_qplib_cq *cq, · 2 unmodified lines
1698		1690
1699	/* Require to walk the sq's swq to fabricate CQEs for all previously	1691	/* Require to walk the sq's swq to fabricate CQEs for all previously
1700	* signaled SWQEs due to CQE aggregation from the current sq cons	1692	* signaled SWQEs due to CQE aggregation from the current sq cons
1701	* to the cqe_cons	1693	* to the cqe_sq_cons
1702	*/	1694	*/
1703	cqe = *pcqe;	1695	cqe = *pcqe;
1704	while (*budget) {	1696	while (*budget) {
1705	sw_cons = HWQ_CMP(sq->hwq.cons, &sq->hwq);	1697	sw_sq_cons = HWQ_CMP(sq->hwq.cons, &sq->hwq);
1706	if (sw_cons == cqe_cons)	1698	if (sw_sq_cons == cqe_sq_cons)
		1699	/* Done */
1707	break;	1700	break;
		1701
		1702	swq = &sq->swq[sw_sq_cons];
1708	memset(cqe, 0, sizeof(*cqe));	1703	memset(cqe, 0, sizeof(*cqe));
1709	cqe->opcode = CQ_BASE_CQE_TYPE_REQ;	1704	cqe->opcode = CQ_BASE_CQE_TYPE_REQ;
1710	cqe->qp_handle = (u64)(unsigned long)qp;	1705	cqe->qp_handle = (u64)(unsigned long)qp;
1711	cqe->src_qp = qp->id;	1706	cqe->src_qp = qp->id;
1712	cqe->wr_id = sq->swq[sw_cons].wr_id;	1707	cqe->wr_id = swq->wr_id;
1713	cqe->type = sq->swq[sw_cons].type;	1708	if (cqe->wr_id == BNXT_QPLIB_FENCE_WRID)
		1709	goto skip;
		1710	cqe->type = swq->type;
1714		1711
1715	/* For the last CQE, check for status. For errors, regardless	1712	/* For the last CQE, check for status. For errors, regardless
1716	* of the request being signaled or not, it must complete with	1713	* of the request being signaled or not, it must complete with
1717	* the hwcqe error status	1714	* the hwcqe error status
1718	*/	1715	*/
1719	if (HWQ_CMP((sw_cons + 1), &sq->hwq) == cqe_cons &&	1716	if (HWQ_CMP((sw_sq_cons + 1), &sq->hwq) == cqe_sq_cons &&
1720	hwcqe->status != CQ_REQ_STATUS_OK) {	1717	hwcqe->status != CQ_REQ_STATUS_OK) {
1721	cqe->status = hwcqe->status;	1718	cqe->status = hwcqe->status;
1722	dev_err(&cq->hwq.pdev->dev,	1719	dev_err(&cq->hwq.pdev->dev,
1723	"QPLIB: FP: CQ Processed Req ");	1720	"QPLIB: FP: CQ Processed Req ");
1724	dev_err(&cq->hwq.pdev->dev,	1721	dev_err(&cq->hwq.pdev->dev,
1725	"QPLIB: wr_id[%d] = 0x%llx with status 0x%x",	1722	"QPLIB: wr_id[%d] = 0x%llx with status 0x%x",
1726	sw_cons, cqe->wr_id, cqe->status);	1723	sw_sq_cons, cqe->wr_id, cqe->status);
1727	cqe++;	1724	cqe++;
1728	(*budget)--;	1725	(*budget)--;
1729	sq->flush_in_progress = true;	1726	sq->flush_in_progress = true;
1730	/* Must block new posting of SQ and RQ */	1727	/* Must block new posting of SQ and RQ */
1731	qp->state = CMDQ_MODIFY_QP_NEW_STATE_ERR;	1728	qp->state = CMDQ_MODIFY_QP_NEW_STATE_ERR;
		1729	sq->condition = false;
		1730	sq->single = false;
1732	} else {	1731	} else {
1733	if (sq->swq[sw_cons].flags &	1732	if (swq->flags & SQ_SEND_FLAGS_SIGNAL_COMP) {
1734	SQ_SEND_FLAGS_SIGNAL_COMP) {	1733	/* Before we complete, do WA 9060 */
		1734	if (do_wa9060(qp, cq, cq_cons, sw_sq_cons,
		1735	cqe_sq_cons)) {
		1736	*lib_qp = qp;
		1737	goto out;
		1738	}
1735	cqe->status = CQ_REQ_STATUS_OK;	1739	cqe->status = CQ_REQ_STATUS_OK;
1736	cqe++;	1740	cqe++;
1737	(*budget)--;	1741	(*budget)--;
1738	}	1742	}
1739	}	1743	}
		1744	skip:
1740	sq->hwq.cons++;	1745	sq->hwq.cons++;
		1746	if (sq->single)
		1747	break;
1741	}	1748	}
		1749	out:
1742	*pcqe = cqe;	1750	*pcqe = cqe;
1743	if (!*budget && HWQ_CMP(sq->hwq.cons, &sq->hwq) != cqe_cons) {	1751	if (HWQ_CMP(sq->hwq.cons, &sq->hwq) != cqe_sq_cons) {
1744	/* Out of budget */	1752	/* Out of budget */
1745	rc = -EAGAIN;	1753	rc = -EAGAIN;
1746	goto done;	1754	goto done;
1747	}	1755	}
		1756	/*
		1757	* Back to normal completion mode only after it has completed all of
		1758	* the WC for this CQE
		1759	*/
		1760	sq->single = false;
1748	if (!sq->flush_in_progress)	1761	if (!sq->flush_in_progress)
1749	goto done;	1762	goto done;
1750	flush:	1763	flush:
@@ -2074,7 +2087,7 @@ static int bnxt_qplib_cq_process_cutoff(struct bnxt_qplib_cq *cq, · 323 unmodified lines
2074	}	2087	}
2075		2088
2076	int bnxt_qplib_poll_cq(struct bnxt_qplib_cq cq, struct bnxt_qplib_cqe cqe,	2089	int bnxt_qplib_poll_cq(struct bnxt_qplib_cq cq, struct bnxt_qplib_cqe cqe,
2077	int num_cqes)	2090	int num_cqes, struct bnxt_qplib_qp **lib_qp)
2078	{	2091	{
2079	struct cq_base hw_cqe, *hw_cqe_ptr;	2092	struct cq_base hw_cqe, *hw_cqe_ptr;
2080	unsigned long flags;	2093	unsigned long flags;
@@ -2099,7 +2112,8 @@ int bnxt_qplib_poll_cq(struct bnxt_qplib_cq cq, struct bnxt_qplib_cqe cqe, · 18 unmodified lines
2099	case CQ_BASE_CQE_TYPE_REQ:	2112	case CQ_BASE_CQE_TYPE_REQ:
2100	rc = bnxt_qplib_cq_process_req(cq,	2113	rc = bnxt_qplib_cq_process_req(cq,
2101	(struct cq_req *)hw_cqe,	2114	(struct cq_req *)hw_cqe,
2102	&cqe, &budget);	2115	&cqe, &budget,
		2116	sw_cons, lib_qp);
2103	break;	2117	break;
2104	case CQ_BASE_CQE_TYPE_RES_RC:	2118	case CQ_BASE_CQE_TYPE_RES_RC:
2105	rc = bnxt_qplib_cq_process_res_rc(cq,	2119	rc = bnxt_qplib_cq_process_res_rc(cq,

drivers/infiniband/hw/bnxt_re/qplib_fp.h+17−1

 struct bnxt_qplib_swqe {
 	/* General */
+#define	BNXT_QPLIB_FENCE_WRID	0x46454E43	/* "FENC" */
 	u64				wr_id;
 	u8				reqs_type;
 	u8				type;
 	struct scatterlist		*sglist;
 	u32				nmap;
 	u32				max_wqe;
+	u16				q_full_delta;
 	u16				max_sge;
 	u32				psn;
 	bool				flush_in_progress;
+	bool				condition;
+	bool				single;
+	bool				send_phantom;
+	u32				phantom_wqe_cnt;
+	u32				phantom_cqe_cnt;
+	u32				next_cq_cons;
 };
 struct bnxt_qplib_qp {
 	u8				timeout;
 	u8				retry_cnt;
 	u8				rnr_retry;
+	u64				wqe_cnt;
 	u32				min_rnr_timer;
 	u32				max_rd_atomic;
 	u32				max_dest_rd_atomic;
 	(!!((hdr)->cqe_type_toggle & CQ_BASE_TOGGLE) ==		\
 	   !((raw_cons) & (cp_bit)))
+static inline bool bnxt_qplib_queue_full(struct bnxt_qplib_q *qplib_q)
+{
+	return HWQ_CMP((qplib_q->hwq.prod + qplib_q->q_full_delta),
+		       &qplib_q->hwq) == HWQ_CMP(qplib_q->hwq.cons,
+						 &qplib_q->hwq);
+}
 struct bnxt_qplib_cqe {
 	u8				status;
 	u8				type;
 int bnxt_qplib_create_cq(struct bnxt_qplib_res *res, struct bnxt_qplib_cq *cq);
 int bnxt_qplib_destroy_cq(struct bnxt_qplib_res *res, struct bnxt_qplib_cq *cq);
 int bnxt_qplib_poll_cq(struct bnxt_qplib_cq *cq, struct bnxt_qplib_cqe *cqe,
-		       int num);
+		       int num, struct bnxt_qplib_qp **qp);
 void bnxt_qplib_req_notify_cq(struct bnxt_qplib_cq *cq, u32 arm_type);
 void bnxt_qplib_free_nq(struct bnxt_qplib_nq *nq);
 int bnxt_qplib_alloc_nq(struct pci_dev *pdev, struct bnxt_qplib_nq *nq);

drivers/infiniband/hw/bnxt_re/qplib_rcfw.c+164−150

@@ -39,72 +39,55 @@ · 38 unmodified lines
39	#include <linux/spinlock.h>	39	#include <linux/spinlock.h>
40	#include <linux/pci.h>	40	#include <linux/pci.h>
41	#include <linux/prefetch.h>	41	#include <linux/prefetch.h>
		42	#include <linux/delay.h>
		43
42	#include "roce_hsi.h"	44	#include "roce_hsi.h"
43	#include "qplib_res.h"	45	#include "qplib_res.h"
44	#include "qplib_rcfw.h"	46	#include "qplib_rcfw.h"
45	static void bnxt_qplib_service_creq(unsigned long data);	47	static void bnxt_qplib_service_creq(unsigned long data);
46		48
47	/* Hardware communication channel */	49	/* Hardware communication channel */
48	int bnxt_qplib_rcfw_wait_for_resp(struct bnxt_qplib_rcfw *rcfw, u16 cookie)	50	static int __wait_for_resp(struct bnxt_qplib_rcfw *rcfw, u16 cookie)
49	{	51	{
50	u16 cbit;	52	u16 cbit;
51	int rc;	53	int rc;
52		54
53	cookie &= RCFW_MAX_COOKIE_VALUE;
54	cbit = cookie % RCFW_MAX_OUTSTANDING_CMD;	55	cbit = cookie % RCFW_MAX_OUTSTANDING_CMD;
55	if (!test_bit(cbit, rcfw->cmdq_bitmap))
56	dev_warn(&rcfw->pdev->dev,
57	"QPLIB: CMD bit %d for cookie 0x%x is not set?",
58	cbit, cookie);
59
60	rc = wait_event_timeout(rcfw->waitq,	56	rc = wait_event_timeout(rcfw->waitq,
61	!test_bit(cbit, rcfw->cmdq_bitmap),	57	!test_bit(cbit, rcfw->cmdq_bitmap),
62	msecs_to_jiffies(RCFW_CMD_WAIT_TIME_MS));	58	msecs_to_jiffies(RCFW_CMD_WAIT_TIME_MS));
63	if (!rc) {	59	return rc ? 0 : -ETIMEDOUT;
64	dev_warn(&rcfw->pdev->dev,
65	"QPLIB: Bono Error: timeout %d msec, msg {0x%x}\n",
66	RCFW_CMD_WAIT_TIME_MS, cookie);
67	}
68
69	return rc;
70	};	60	};
71		61
72	int bnxt_qplib_rcfw_block_for_resp(struct bnxt_qplib_rcfw *rcfw, u16 cookie)	62	static int __block_for_resp(struct bnxt_qplib_rcfw *rcfw, u16 cookie)
73	{	63	{
74	u32 count = -1;	64	u32 count = RCFW_BLOCKED_CMD_WAIT_COUNT;
75	u16 cbit;	65	u16 cbit;
76		66
77	cookie &= RCFW_MAX_COOKIE_VALUE;
78	cbit = cookie % RCFW_MAX_OUTSTANDING_CMD;	67	cbit = cookie % RCFW_MAX_OUTSTANDING_CMD;
79	if (!test_bit(cbit, rcfw->cmdq_bitmap))	68	if (!test_bit(cbit, rcfw->cmdq_bitmap))
80	goto done;	69	goto done;
81	do {	70	do {
		71	mdelay(1); /* 1m sec */
82	bnxt_qplib_service_creq((unsigned long)rcfw);	72	bnxt_qplib_service_creq((unsigned long)rcfw);
83	} while (test_bit(cbit, rcfw->cmdq_bitmap) && --count);	73	} while (test_bit(cbit, rcfw->cmdq_bitmap) && --count);
84	done:	74	done:
85	return count;	75	return count ? 0 : -ETIMEDOUT;
86	};	76	};
87		77
88	void bnxt_qplib_rcfw_send_message(struct bnxt_qplib_rcfw rcfw,	78	static int __send_message(struct bnxt_qplib_rcfw rcfw, struct cmdq_base req,
89	struct cmdq_base req, void *crsbe,	79	struct creq_base resp, void sb, u8 is_block)
90	u8 is_block)
91	{	80	{
92	struct bnxt_qplib_crsq *crsq = &rcfw->crsq;
93	struct bnxt_qplib_cmdqe cmdqe, *cmdq_ptr;	81	struct bnxt_qplib_cmdqe cmdqe, *cmdq_ptr;
94	struct bnxt_qplib_hwq *cmdq = &rcfw->cmdq;	82	struct bnxt_qplib_hwq *cmdq = &rcfw->cmdq;
95	struct bnxt_qplib_hwq *crsb = &rcfw->crsb;	83	struct bnxt_qplib_crsq *crsqe;
96	struct bnxt_qplib_crsqe *crsqe = NULL;
97	struct bnxt_qplib_crsbe **crsb_ptr;
98	u32 sw_prod, cmdq_prod;	84	u32 sw_prod, cmdq_prod;
99	u8 retry_cnt = 0xFF;
100	dma_addr_t dma_addr;
101	unsigned long flags;	85	unsigned long flags;
102	u32 size, opcode;	86	u32 size, opcode;
103	u16 cookie, cbit;	87	u16 cookie, cbit;
104	int pg, idx;	88	int pg, idx;
105	u8 *preq;	89	u8 *preq;
106		90
107	retry:
108	opcode = req->opcode;	91	opcode = req->opcode;
109	if (!test_bit(FIRMWARE_INITIALIZED_FLAG, &rcfw->flags) &&	92	if (!test_bit(FIRMWARE_INITIALIZED_FLAG, &rcfw->flags) &&
110	(opcode != CMDQ_BASE_OPCODE_QUERY_FUNC &&	93	(opcode != CMDQ_BASE_OPCODE_QUERY_FUNC &&
@@ -112,63 +95,50 @@ retry: · 1 unmodified line
112	dev_err(&rcfw->pdev->dev,	95	dev_err(&rcfw->pdev->dev,
113	"QPLIB: RCFW not initialized, reject opcode 0x%x",	96	"QPLIB: RCFW not initialized, reject opcode 0x%x",
114	opcode);	97	opcode);
115	return NULL;	98	return -EINVAL;
116	}	99	}
117		100
118	if (test_bit(FIRMWARE_INITIALIZED_FLAG, &rcfw->flags) &&	101	if (test_bit(FIRMWARE_INITIALIZED_FLAG, &rcfw->flags) &&
119	opcode == CMDQ_BASE_OPCODE_INITIALIZE_FW) {	102	opcode == CMDQ_BASE_OPCODE_INITIALIZE_FW) {
120	dev_err(&rcfw->pdev->dev, "QPLIB: RCFW already initialized!");	103	dev_err(&rcfw->pdev->dev, "QPLIB: RCFW already initialized!");
121	return NULL;	104	return -EINVAL;
122	}	105	}
123		106
124	/* Cmdq are in 16-byte units, each request can consume 1 or more	107	/* Cmdq are in 16-byte units, each request can consume 1 or more
125	* cmdqe	108	* cmdqe
126	*/	109	*/
127	spin_lock_irqsave(&cmdq->lock, flags);	110	spin_lock_irqsave(&cmdq->lock, flags);
128	if (req->cmd_size > cmdq->max_elements -	111	if (req->cmd_size >= HWQ_FREE_SLOTS(cmdq)) {
129	((HWQ_CMP(cmdq->prod, cmdq) - HWQ_CMP(cmdq->cons, cmdq)) &
130	(cmdq->max_elements - 1))) {
131	dev_err(&rcfw->pdev->dev, "QPLIB: RCFW: CMDQ is full!");	112	dev_err(&rcfw->pdev->dev, "QPLIB: RCFW: CMDQ is full!");
132	spin_unlock_irqrestore(&cmdq->lock, flags);	113	spin_unlock_irqrestore(&cmdq->lock, flags);
133		114	return -EAGAIN;
134	if (!retry_cnt--)
135	return NULL;
136	goto retry;
137	}	115	}
138		116
139	retry_cnt = 0xFF;
140		117
141	cookie = atomic_inc_return(&rcfw->seq_num) & RCFW_MAX_COOKIE_VALUE;	118	cookie = rcfw->seq_num & RCFW_MAX_COOKIE_VALUE;
142	cbit = cookie % RCFW_MAX_OUTSTANDING_CMD;	119	cbit = cookie % RCFW_MAX_OUTSTANDING_CMD;
143	if (is_block)	120	if (is_block)
144	cookie \|= RCFW_CMD_IS_BLOCKING;	121	cookie \|= RCFW_CMD_IS_BLOCKING;
		122
		123	set_bit(cbit, rcfw->cmdq_bitmap);
145	req->cookie = cpu_to_le16(cookie);	124	req->cookie = cpu_to_le16(cookie);
146	if (test_and_set_bit(cbit, rcfw->cmdq_bitmap)) {	125	crsqe = &rcfw->crsqe_tbl[cbit];
147	dev_err(&rcfw->pdev->dev,	126	if (crsqe->resp) {
148	"QPLIB: RCFW MAX outstanding cmd reached!");
149	atomic_dec(&rcfw->seq_num);
150	spin_unlock_irqrestore(&cmdq->lock, flags);	127	spin_unlock_irqrestore(&cmdq->lock, flags);
151		128	return -EBUSY;
152	if (!retry_cnt--)
153	return NULL;
154	goto retry;
155	}	129	}
156	/* Reserve a resp buffer slot if requested */	130	memset(resp, 0, sizeof(*resp));
157	if (req->resp_size && crsbe) {	131	crsqe->resp = (struct creq_qp_event *)resp;
158	spin_lock(&crsb->lock);	132	crsqe->resp->cookie = req->cookie;
159	sw_prod = HWQ_CMP(crsb->prod, crsb);	133	crsqe->req_size = req->cmd_size;
160	crsb_ptr = (struct bnxt_qplib_crsbe **)crsb->pbl_ptr;	134	if (req->resp_size && sb) {
161	crsbe = (void )&crsb_ptr[get_crsb_pg(sw_prod)]	135	struct bnxt_qplib_rcfw_sbuf *sbuf = sb;
162	[get_crsb_idx(sw_prod)];	136
163	bnxt_qplib_crsb_dma_next(crsb->pbl_dma_ptr, sw_prod, &dma_addr);	137	req->resp_addr = cpu_to_le64(sbuf->dma_addr);
164	req->resp_addr = cpu_to_le64(dma_addr);	138	req->resp_size = (sbuf->size + BNXT_QPLIB_CMDQE_UNITS - 1) /
165	crsb->prod++;	139	BNXT_QPLIB_CMDQE_UNITS;
166	spin_unlock(&crsb->lock);
167
168	req->resp_size = (sizeof(struct bnxt_qplib_crsbe) +
169	BNXT_QPLIB_CMDQE_UNITS - 1) /
170	BNXT_QPLIB_CMDQE_UNITS;
171	}	140	}
		141
172	cmdq_ptr = (struct bnxt_qplib_cmdqe **)cmdq->pbl_ptr;	142	cmdq_ptr = (struct bnxt_qplib_cmdqe **)cmdq->pbl_ptr;
173	preq = (u8 *)req;	143	preq = (u8 *)req;
174	size = req->cmd_size * BNXT_QPLIB_CMDQE_UNITS;	144	size = req->cmd_size * BNXT_QPLIB_CMDQE_UNITS;
@@ -190,23 +160,24 @@ retry: · 15 unmodified lines
190	preq += min_t(u32, size, sizeof(*cmdqe));	160	preq += min_t(u32, size, sizeof(*cmdqe));
191	size -= min_t(u32, size, sizeof(*cmdqe));	161	size -= min_t(u32, size, sizeof(*cmdqe));
192	cmdq->prod++;	162	cmdq->prod++;
		163	rcfw->seq_num++;
193	} while (size > 0);	164	} while (size > 0);
194		165
		166	rcfw->seq_num++;
		167
195	cmdq_prod = cmdq->prod;	168	cmdq_prod = cmdq->prod;
196	if (rcfw->flags & FIRMWARE_FIRST_FLAG) {	169	if (rcfw->flags & FIRMWARE_FIRST_FLAG) {
197	/* The very first doorbell write is required to set this flag	170	/* The very first doorbell write
198	* which prompts the FW to reset its internal pointers	171	* is required to set this flag
		172	* which prompts the FW to reset
		173	* its internal pointers
199	*/	174	*/
200	cmdq_prod \|= FIRMWARE_FIRST_FLAG;	175	cmdq_prod \|= FIRMWARE_FIRST_FLAG;
201	rcfw->flags &= ~FIRMWARE_FIRST_FLAG;	176	rcfw->flags &= ~FIRMWARE_FIRST_FLAG;
202	}	177	}
203	sw_prod = HWQ_CMP(crsq->prod, crsq);
204	crsqe = &crsq->crsq[sw_prod];
205	memset(crsqe, 0, sizeof(*crsqe));
206	crsq->prod++;
207	crsqe->req_size = req->cmd_size;
208		178
209	/* ring CMDQ DB */	179	/* ring CMDQ DB */
		180	wmb();
210	writel(cmdq_prod, rcfw->cmdq_bar_reg_iomem +	181	writel(cmdq_prod, rcfw->cmdq_bar_reg_iomem +
211	rcfw->cmdq_bar_reg_prod_off);	182	rcfw->cmdq_bar_reg_prod_off);
212	writel(RCFW_CMDQ_TRIG_VAL, rcfw->cmdq_bar_reg_iomem +	183	writel(RCFW_CMDQ_TRIG_VAL, rcfw->cmdq_bar_reg_iomem +
@@ -214,9 +185,56 @@ retry: · 1 unmodified line
214	done:	185	done:
215	spin_unlock_irqrestore(&cmdq->lock, flags);	186	spin_unlock_irqrestore(&cmdq->lock, flags);
216	/* Return the CREQ response pointer */	187	/* Return the CREQ response pointer */
217	return crsqe ? &crsqe->qp_event : NULL;	188	return 0;
218	}	189	}
219		190
		191	int bnxt_qplib_rcfw_send_message(struct bnxt_qplib_rcfw *rcfw,
		192	struct cmdq_base *req,
		193	struct creq_base *resp,
		194	void *sb, u8 is_block)
		195	{
		196	struct creq_qp_event evnt = (struct creq_qp_event )resp;
		197	u16 cookie;
		198	u8 opcode, retry_cnt = 0xFF;
		199	int rc = 0;
		200
		201	do {
		202	opcode = req->opcode;
		203	rc = __send_message(rcfw, req, resp, sb, is_block);
		204	cookie = le16_to_cpu(req->cookie) & RCFW_MAX_COOKIE_VALUE;
		205	if (!rc)
		206	break;
		207
		208	if (!retry_cnt \|\| (rc != -EAGAIN && rc != -EBUSY)) {
		209	/* send failed */
		210	dev_err(&rcfw->pdev->dev, "QPLIB: cmdq[%#x]=%#x send failed",
		211	cookie, opcode);
		212	return rc;
		213	}
		214	is_block ? mdelay(1) : usleep_range(500, 1000);
		215
		216	} while (retry_cnt--);
		217
		218	if (is_block)
		219	rc = __block_for_resp(rcfw, cookie);
		220	else
		221	rc = __wait_for_resp(rcfw, cookie);
		222	if (rc) {
		223	/* timed out */
		224	dev_err(&rcfw->pdev->dev, "QPLIB: cmdq[%#x]=%#x timedout (%d)msec",
		225	cookie, opcode, RCFW_CMD_WAIT_TIME_MS);
		226	return rc;
		227	}
		228
		229	if (evnt->status) {
		230	/* failed with status */
		231	dev_err(&rcfw->pdev->dev, "QPLIB: cmdq[%#x]=%#x status %#x",
		232	cookie, opcode, evnt->status);
		233	rc = -EFAULT;
		234	}
		235
		236	return rc;
		237	}
220	/* Completions */	238	/* Completions */
221	static int bnxt_qplib_process_func_event(struct bnxt_qplib_rcfw *rcfw,	239	static int bnxt_qplib_process_func_event(struct bnxt_qplib_rcfw *rcfw,
222	struct creq_func_event *func_event)	240	struct creq_func_event *func_event)
@@ -260,12 +278,12 @@ static int bnxt_qplib_process_func_event(struct bnxt_qplib_rcfw *rcfw, · 37 unmodified lines
260	static int bnxt_qplib_process_qp_event(struct bnxt_qplib_rcfw *rcfw,	278	static int bnxt_qplib_process_qp_event(struct bnxt_qplib_rcfw *rcfw,
261	struct creq_qp_event *qp_event)	279	struct creq_qp_event *qp_event)
262	{	280	{
263	struct bnxt_qplib_crsq *crsq = &rcfw->crsq;
264	struct bnxt_qplib_hwq *cmdq = &rcfw->cmdq;	281	struct bnxt_qplib_hwq *cmdq = &rcfw->cmdq;
265	struct bnxt_qplib_crsqe *crsqe;	282	struct bnxt_qplib_crsq *crsqe;
266	u16 cbit, cookie, blocked = 0;
267	unsigned long flags;	283	unsigned long flags;
268	u32 sw_cons;	284	u16 cbit, blocked = 0;
		285	u16 cookie;
		286	__le16 mcookie;
269		287
270	switch (qp_event->event) {	288	switch (qp_event->event) {
271	case CREQ_QP_EVENT_EVENT_QP_ERROR_NOTIFICATION:	289	case CREQ_QP_EVENT_EVENT_QP_ERROR_NOTIFICATION:
@@ -275,24 +293,31 @@ static int bnxt_qplib_process_qp_event(struct bnxt_qplib_rcfw *rcfw, · 3 unmodified lines
275	default:	293	default:
276	/* Command Response */	294	/* Command Response */
277	spin_lock_irqsave(&cmdq->lock, flags);	295	spin_lock_irqsave(&cmdq->lock, flags);
278	sw_cons = HWQ_CMP(crsq->cons, crsq);	296	cookie = le16_to_cpu(qp_event->cookie);
279	crsqe = &crsq->crsq[sw_cons];	297	mcookie = qp_event->cookie;
280	crsq->cons++;
281	memcpy(&crsqe->qp_event, qp_event, sizeof(crsqe->qp_event));
282
283	cookie = le16_to_cpu(crsqe->qp_event.cookie);
284	blocked = cookie & RCFW_CMD_IS_BLOCKING;	298	blocked = cookie & RCFW_CMD_IS_BLOCKING;
285	cookie &= RCFW_MAX_COOKIE_VALUE;	299	cookie &= RCFW_MAX_COOKIE_VALUE;
286	cbit = cookie % RCFW_MAX_OUTSTANDING_CMD;	300	cbit = cookie % RCFW_MAX_OUTSTANDING_CMD;
		301	crsqe = &rcfw->crsqe_tbl[cbit];
		302	if (crsqe->resp &&
		303	crsqe->resp->cookie == mcookie) {
		304	memcpy(crsqe->resp, qp_event, sizeof(*qp_event));
		305	crsqe->resp = NULL;
		306	} else {
		307	dev_err(&rcfw->pdev->dev,
		308	"QPLIB: CMD %s resp->cookie = %#x, evnt->cookie = %#x",
		309	crsqe->resp ? "mismatch" : "collision",
		310	crsqe->resp ? crsqe->resp->cookie : 0, mcookie);
		311	}
287	if (!test_and_clear_bit(cbit, rcfw->cmdq_bitmap))	312	if (!test_and_clear_bit(cbit, rcfw->cmdq_bitmap))
288	dev_warn(&rcfw->pdev->dev,	313	dev_warn(&rcfw->pdev->dev,
289	"QPLIB: CMD bit %d was not requested", cbit);	314	"QPLIB: CMD bit %d was not requested", cbit);
290
291	cmdq->cons += crsqe->req_size;	315	cmdq->cons += crsqe->req_size;
292	spin_unlock_irqrestore(&cmdq->lock, flags);	316	crsqe->req_size = 0;
		317
293	if (!blocked)	318	if (!blocked)
294	wake_up(&rcfw->waitq);	319	wake_up(&rcfw->waitq);
295	break;	320	spin_unlock_irqrestore(&cmdq->lock, flags);
296	}	321	}
297	return 0;	322	return 0;
298	}	323	}
@@ -305,12 +330,12 @@ static void bnxt_qplib_service_creq(unsigned long data) · 6 unmodified lines
305	struct creq_base creqe, *creq_ptr;	330	struct creq_base creqe, *creq_ptr;
306	u32 sw_cons, raw_cons;	331	u32 sw_cons, raw_cons;
307	unsigned long flags;	332	unsigned long flags;
308	u32 type;	333	u32 type, budget = CREQ_ENTRY_POLL_BUDGET;
309		334
310	/* Service the CREQ until empty */	335	/* Service the CREQ until budget is over */
311	spin_lock_irqsave(&creq->lock, flags);	336	spin_lock_irqsave(&creq->lock, flags);
312	raw_cons = creq->cons;	337	raw_cons = creq->cons;
313	while (1) {	338	while (budget > 0) {
314	sw_cons = HWQ_CMP(raw_cons, creq);	339	sw_cons = HWQ_CMP(raw_cons, creq);
315	creq_ptr = (struct creq_base **)creq->pbl_ptr;	340	creq_ptr = (struct creq_base **)creq->pbl_ptr;
316	creqe = &creq_ptr[get_creq_pg(sw_cons)][get_creq_idx(sw_cons)];	341	creqe = &creq_ptr[get_creq_pg(sw_cons)][get_creq_idx(sw_cons)];
@@ -320,15 +345,9 @@ static void bnxt_qplib_service_creq(unsigned long data) · 3 unmodified lines
320	type = creqe->type & CREQ_BASE_TYPE_MASK;	345	type = creqe->type & CREQ_BASE_TYPE_MASK;
321	switch (type) {	346	switch (type) {
322	case CREQ_BASE_TYPE_QP_EVENT:	347	case CREQ_BASE_TYPE_QP_EVENT:
323	if (!bnxt_qplib_process_qp_event	348	bnxt_qplib_process_qp_event
324	(rcfw, (struct creq_qp_event *)creqe))	349	(rcfw, (struct creq_qp_event *)creqe);
325	rcfw->creq_qp_event_processed++;	350	rcfw->creq_qp_event_processed++;
326	else {
327	dev_warn(&rcfw->pdev->dev, "QPLIB: crsqe with");
328	dev_warn(&rcfw->pdev->dev,
329	"QPLIB: type = 0x%x not handled",
330	type);
331	}
332	break;	351	break;
333	case CREQ_BASE_TYPE_FUNC_EVENT:	352	case CREQ_BASE_TYPE_FUNC_EVENT:
334	if (!bnxt_qplib_process_func_event	353	if (!bnxt_qplib_process_func_event
@@ -346,7 +365,9 @@ static void bnxt_qplib_service_creq(unsigned long data) · 11 unmodified lines
346	break;	365	break;
347	}	366	}
348	raw_cons++;	367	raw_cons++;
		368	budget--;
349	}	369	}
		370
350	if (creq->cons != raw_cons) {	371	if (creq->cons != raw_cons) {
351	creq->cons = raw_cons;	372	creq->cons = raw_cons;
352	CREQ_DB_REARM(rcfw->creq_bar_reg_iomem, raw_cons,	373	CREQ_DB_REARM(rcfw->creq_bar_reg_iomem, raw_cons,
@@ -375,23 +396,16 @@ static irqreturn_t bnxt_qplib_creq_irq(int irq, void *dev_instance) · 22 unmodified lines
375	/* RCFW */	396	/* RCFW */
376	int bnxt_qplib_deinit_rcfw(struct bnxt_qplib_rcfw *rcfw)	397	int bnxt_qplib_deinit_rcfw(struct bnxt_qplib_rcfw *rcfw)
377	{	398	{
378	struct creq_deinitialize_fw_resp *resp;
379	struct cmdq_deinitialize_fw req;	399	struct cmdq_deinitialize_fw req;
		400	struct creq_deinitialize_fw_resp resp;
380	u16 cmd_flags = 0;	401	u16 cmd_flags = 0;
		402	int rc;
381		403
382	RCFW_CMD_PREP(req, DEINITIALIZE_FW, cmd_flags);	404	RCFW_CMD_PREP(req, DEINITIALIZE_FW, cmd_flags);
383	resp = (struct creq_deinitialize_fw_resp *)	405	rc = bnxt_qplib_rcfw_send_message(rcfw, (void )&req, (void )&resp,
384	bnxt_qplib_rcfw_send_message(rcfw, (void *)&req,	406	NULL, 0);
385	NULL, 0);	407	if (rc)
386	if (!resp)	408	return rc;
387	return -EINVAL;
388
389	if (!bnxt_qplib_rcfw_wait_for_resp(rcfw, le16_to_cpu(req.cookie)))
390	return -ETIMEDOUT;
391
392	if (resp->status \|\|
393	le16_to_cpu(resp->cookie) != le16_to_cpu(req.cookie))
394	return -EFAULT;
395		409
396	clear_bit(FIRMWARE_INITIALIZED_FLAG, &rcfw->flags);	410	clear_bit(FIRMWARE_INITIALIZED_FLAG, &rcfw->flags);
397	return 0;	411	return 0;
@@ -417,9 +431,10 @@ static int __get_pbl_pg_idx(struct bnxt_qplib_pbl *pbl) · 19 unmodified lines
417	int bnxt_qplib_init_rcfw(struct bnxt_qplib_rcfw *rcfw,	431	int bnxt_qplib_init_rcfw(struct bnxt_qplib_rcfw *rcfw,
418	struct bnxt_qplib_ctx *ctx, int is_virtfn)	432	struct bnxt_qplib_ctx *ctx, int is_virtfn)
419	{	433	{
420	struct creq_initialize_fw_resp *resp;
421	struct cmdq_initialize_fw req;	434	struct cmdq_initialize_fw req;
		435	struct creq_initialize_fw_resp resp;
422	u16 cmd_flags = 0, level;	436	u16 cmd_flags = 0, level;
		437	int rc;
423		438
424	RCFW_CMD_PREP(req, INITIALIZE_FW, cmd_flags);	439	RCFW_CMD_PREP(req, INITIALIZE_FW, cmd_flags);
425		440
@@ -482,37 +497,19 @@ int bnxt_qplib_init_rcfw(struct bnxt_qplib_rcfw *rcfw, · 56 unmodified lines
482		497
483	skip_ctx_setup:	498	skip_ctx_setup:
484	req.stat_ctx_id = cpu_to_le32(ctx->stats.fw_id);	499	req.stat_ctx_id = cpu_to_le32(ctx->stats.fw_id);
485	resp = (struct creq_initialize_fw_resp *)	500	rc = bnxt_qplib_rcfw_send_message(rcfw, (void )&req, (void )&resp,
486	bnxt_qplib_rcfw_send_message(rcfw, (void *)&req,	501	NULL, 0);
487	NULL, 0);	502	if (rc)
488	if (!resp) {	503	return rc;
489	dev_err(&rcfw->pdev->dev,
490	"QPLIB: RCFW: INITIALIZE_FW send failed");
491	return -EINVAL;
492	}
493	if (!bnxt_qplib_rcfw_wait_for_resp(rcfw, le16_to_cpu(req.cookie))) {
494	/* Cmd timed out */
495	dev_err(&rcfw->pdev->dev,
496	"QPLIB: RCFW: INITIALIZE_FW timed out");
497	return -ETIMEDOUT;
498	}
499	if (resp->status \|\|
500	le16_to_cpu(resp->cookie) != le16_to_cpu(req.cookie)) {
501	dev_err(&rcfw->pdev->dev,
502	"QPLIB: RCFW: INITIALIZE_FW failed");
503	return -EINVAL;
504	}
505	set_bit(FIRMWARE_INITIALIZED_FLAG, &rcfw->flags);	504	set_bit(FIRMWARE_INITIALIZED_FLAG, &rcfw->flags);
506	return 0;	505	return 0;
507	}	506	}
508		507
509	void bnxt_qplib_free_rcfw_channel(struct bnxt_qplib_rcfw *rcfw)	508	void bnxt_qplib_free_rcfw_channel(struct bnxt_qplib_rcfw *rcfw)
510	{	509	{
511	bnxt_qplib_free_hwq(rcfw->pdev, &rcfw->crsb);	510	kfree(rcfw->crsqe_tbl);
512	kfree(rcfw->crsq.crsq);
513	bnxt_qplib_free_hwq(rcfw->pdev, &rcfw->cmdq);	511	bnxt_qplib_free_hwq(rcfw->pdev, &rcfw->cmdq);
514	bnxt_qplib_free_hwq(rcfw->pdev, &rcfw->creq);	512	bnxt_qplib_free_hwq(rcfw->pdev, &rcfw->creq);
515
516	rcfw->pdev = NULL;	513	rcfw->pdev = NULL;
517	}	514	}
518		515
@@ -539,21 +536,11 @@ int bnxt_qplib_alloc_rcfw_channel(struct pci_dev *pdev, · 20 unmodified lines
539	goto fail;	536	goto fail;
540	}	537	}
541		538
542	rcfw->crsq.max_elements = rcfw->cmdq.max_elements;	539	rcfw->crsqe_tbl = kcalloc(rcfw->cmdq.max_elements,
543	rcfw->crsq.crsq = kcalloc(rcfw->crsq.max_elements,	540	sizeof(*rcfw->crsqe_tbl), GFP_KERNEL);
544	sizeof(*rcfw->crsq.crsq), GFP_KERNEL);	541	if (!rcfw->crsqe_tbl)
545	if (!rcfw->crsq.crsq)
546	goto fail;	542	goto fail;
547		543
548	rcfw->crsb.max_elements = BNXT_QPLIB_CRSBE_MAX_CNT;
549	if (bnxt_qplib_alloc_init_hwq(rcfw->pdev, &rcfw->crsb, NULL, 0,
550	&rcfw->crsb.max_elements,
551	BNXT_QPLIB_CRSBE_UNITS, 0, PAGE_SIZE,
552	HWQ_TYPE_CTX)) {
553	dev_err(&rcfw->pdev->dev,
554	"QPLIB: HW channel CRSB allocation failed");
555	goto fail;
556	}
557	return 0;	544	return 0;
558		545
559	fail:	546	fail:
@@ -606,7 +593,7 @@ int bnxt_qplib_enable_rcfw_channel(struct pci_dev *pdev, · 46 unmodified lines
606	int rc;	593	int rc;
607		594
608	/* General */	595	/* General */
609	atomic_set(&rcfw->seq_num, 0);	596	rcfw->seq_num = 0;
610	rcfw->flags = FIRMWARE_FIRST_FLAG;	597	rcfw->flags = FIRMWARE_FIRST_FLAG;
611	bmap_size = BITS_TO_LONGS(RCFW_MAX_OUTSTANDING_CMD *	598	bmap_size = BITS_TO_LONGS(RCFW_MAX_OUTSTANDING_CMD *
612	sizeof(unsigned long));	599	sizeof(unsigned long));
@@ -636,10 +623,6 @@ int bnxt_qplib_enable_rcfw_channel(struct pci_dev *pdev, · 23 unmodified lines
636		623
637	rcfw->cmdq_bar_reg_trig_off = RCFW_COMM_TRIG_OFFSET;	624	rcfw->cmdq_bar_reg_trig_off = RCFW_COMM_TRIG_OFFSET;
638		625
639	/* CRSQ */
640	rcfw->crsq.prod = 0;
641	rcfw->crsq.cons = 0;
642
643	/* CREQ */	626	/* CREQ */
644	rcfw->creq_bar_reg = RCFW_COMM_CONS_PCI_BAR_REGION;	627	rcfw->creq_bar_reg = RCFW_COMM_CONS_PCI_BAR_REGION;
645	res_base = pci_resource_start(pdev, rcfw->creq_bar_reg);	628	res_base = pci_resource_start(pdev, rcfw->creq_bar_reg);
@@ -692,3 +675,34 @@ int bnxt_qplib_enable_rcfw_channel(struct pci_dev *pdev, · 46 unmodified lines
692	__iowrite32_copy(rcfw->cmdq_bar_reg_iomem, &init, sizeof(init) / 4);	675	__iowrite32_copy(rcfw->cmdq_bar_reg_iomem, &init, sizeof(init) / 4);
693	return 0;	676	return 0;
694	}	677	}
		678
		679	struct bnxt_qplib_rcfw_sbuf *bnxt_qplib_rcfw_alloc_sbuf(
		680	struct bnxt_qplib_rcfw *rcfw,
		681	u32 size)
		682	{
		683	struct bnxt_qplib_rcfw_sbuf *sbuf;
		684
		685	sbuf = kzalloc(sizeof(*sbuf), GFP_ATOMIC);
		686	if (!sbuf)
		687	return NULL;
		688
		689	sbuf->size = size;
		690	sbuf->sb = dma_zalloc_coherent(&rcfw->pdev->dev, sbuf->size,
		691	&sbuf->dma_addr, GFP_ATOMIC);
		692	if (!sbuf->sb)
		693	goto bail;
		694
		695	return sbuf;
		696	bail:
		697	kfree(sbuf);
		698	return NULL;
		699	}
		700
		701	void bnxt_qplib_rcfw_free_sbuf(struct bnxt_qplib_rcfw *rcfw,
		702	struct bnxt_qplib_rcfw_sbuf *sbuf)
		703	{
		704	if (sbuf->sb)
		705	dma_free_coherent(&rcfw->pdev->dev, sbuf->size,
		706	sbuf->sb, sbuf->dma_addr);
		707	kfree(sbuf);
		708	}

drivers/infiniband/hw/bnxt_re/qplib_rcfw.h+20−41

@@ -73,6 +73,7 @@ · 72 unmodified lines
73	#define RCFW_MAX_OUTSTANDING_CMD BNXT_QPLIB_CMDQE_MAX_CNT	73	#define RCFW_MAX_OUTSTANDING_CMD BNXT_QPLIB_CMDQE_MAX_CNT
74	#define RCFW_MAX_COOKIE_VALUE 0x7FFF	74	#define RCFW_MAX_COOKIE_VALUE 0x7FFF
75	#define RCFW_CMD_IS_BLOCKING 0x8000	75	#define RCFW_CMD_IS_BLOCKING 0x8000
		76	#define RCFW_BLOCKED_CMD_WAIT_COUNT 0x4E20
76		77
77	/* Cmdq contains a fix number of a 16-Byte slots */	78	/* Cmdq contains a fix number of a 16-Byte slots */
78	struct bnxt_qplib_cmdqe {	79	struct bnxt_qplib_cmdqe {
@@ -94,32 +95,6 @@ struct bnxt_qplib_crsbe { · 15 unmodified lines
94	u8 data[1024];	95	u8 data[1024];
95	};	96	};
96		97
97	/* CRSQ SB */
98	#define BNXT_QPLIB_CRSBE_MAX_CNT 4
99	#define BNXT_QPLIB_CRSBE_UNITS sizeof(struct bnxt_qplib_crsbe)
100	#define BNXT_QPLIB_CRSBE_CNT_PER_PG (PAGE_SIZE / BNXT_QPLIB_CRSBE_UNITS)
101
102	#define MAX_CRSB_IDX (BNXT_QPLIB_CRSBE_MAX_CNT - 1)
103	#define MAX_CRSB_IDX_PER_PG (BNXT_QPLIB_CRSBE_CNT_PER_PG - 1)
104
105	static inline u32 get_crsb_pg(u32 val)
106	{
107	return (val & ~MAX_CRSB_IDX_PER_PG) / BNXT_QPLIB_CRSBE_CNT_PER_PG;
108	}
109
110	static inline u32 get_crsb_idx(u32 val)
111	{
112	return val & MAX_CRSB_IDX_PER_PG;
113	}
114
115	static inline void bnxt_qplib_crsb_dma_next(dma_addr_t *pg_map_arr,
116	u32 prod, dma_addr_t *dma_addr)
117	{
118	*dma_addr = pg_map_arr[(prod) / BNXT_QPLIB_CRSBE_CNT_PER_PG];
119	dma_addr += ((prod) % BNXT_QPLIB_CRSBE_CNT_PER_PG)
120	BNXT_QPLIB_CRSBE_UNITS;
121	}
122
123	/* CREQ */	98	/* CREQ */
124	/* Allocate 1 per QP for async error notification for now */	99	/* Allocate 1 per QP for async error notification for now */
125	#define BNXT_QPLIB_CREQE_MAX_CNT (64 * 1024)	100	#define BNXT_QPLIB_CREQE_MAX_CNT (64 * 1024)
@@ -158,17 +133,19 @@ static inline u32 get_creq_idx(u32 val) · 32 unmodified lines
158	#define CREQ_DB(db, raw_cons, cp_bit) \	133	#define CREQ_DB(db, raw_cons, cp_bit) \
159	writel(CREQ_DB_CP_FLAGS \| ((raw_cons) & ((cp_bit) - 1)), db)	134	writel(CREQ_DB_CP_FLAGS \| ((raw_cons) & ((cp_bit) - 1)), db)
160		135
		136	#define CREQ_ENTRY_POLL_BUDGET 0x100
		137
161	/* HWQ */	138	/* HWQ */
162	struct bnxt_qplib_crsqe {	139
163	struct creq_qp_event qp_event;	140	struct bnxt_qplib_crsq {
		141	struct creq_qp_event *resp;
164	u32 req_size;	142	u32 req_size;
165	};	143	};
166		144
167	struct bnxt_qplib_crsq {	145	struct bnxt_qplib_rcfw_sbuf {
168	struct bnxt_qplib_crsqe *crsq;	146	void *sb;
169	u32 prod;	147	dma_addr_t dma_addr;
170	u32 cons;	148	u32 size;
171	u32 max_elements;
172	};	149	};
173		150
174	/* RCFW Communication Channels */	151	/* RCFW Communication Channels */
@@ -185,7 +162,7 @@ struct bnxt_qplib_rcfw { · 10 unmodified lines
185	wait_queue_head_t waitq;	162	wait_queue_head_t waitq;
186	int (aeq_handler)(struct bnxt_qplib_rcfw ,	163	int (aeq_handler)(struct bnxt_qplib_rcfw ,
187	struct creq_func_event *);	164	struct creq_func_event *);
188	atomic_t seq_num;	165	u32 seq_num;
189		166
190	/* Bar region info */	167	/* Bar region info */
191	void __iomem *cmdq_bar_reg_iomem;	168	void __iomem *cmdq_bar_reg_iomem;
@@ -203,8 +180,7 @@ struct bnxt_qplib_rcfw { · 11 unmodified lines
203		180
204	/* Actual Cmd and Resp Queues */	181	/* Actual Cmd and Resp Queues */
205	struct bnxt_qplib_hwq cmdq;	182	struct bnxt_qplib_hwq cmdq;
206	struct bnxt_qplib_crsq crsq;	183	struct bnxt_qplib_crsq *crsqe_tbl;
207	struct bnxt_qplib_hwq crsb;
208	};	184	};
209		185
210	void bnxt_qplib_free_rcfw_channel(struct bnxt_qplib_rcfw *rcfw);	186	void bnxt_qplib_free_rcfw_channel(struct bnxt_qplib_rcfw *rcfw);
@@ -219,11 +195,14 @@ int bnxt_qplib_enable_rcfw_channel(struct pci_dev *pdev, · 8 unmodified lines
219	(struct bnxt_qplib_rcfw *,	195	(struct bnxt_qplib_rcfw *,
220	struct creq_func_event *));	196	struct creq_func_event *));
221		197
222	int bnxt_qplib_rcfw_block_for_resp(struct bnxt_qplib_rcfw *rcfw, u16 cookie);	198	struct bnxt_qplib_rcfw_sbuf *bnxt_qplib_rcfw_alloc_sbuf(
223	int bnxt_qplib_rcfw_wait_for_resp(struct bnxt_qplib_rcfw *rcfw, u16 cookie);	199	struct bnxt_qplib_rcfw *rcfw,
224	void bnxt_qplib_rcfw_send_message(struct bnxt_qplib_rcfw rcfw,	200	u32 size);
225	struct cmdq_base req, void *crsbe,	201	void bnxt_qplib_rcfw_free_sbuf(struct bnxt_qplib_rcfw *rcfw,
226	u8 is_block);	202	struct bnxt_qplib_rcfw_sbuf *sbuf);
		203	int bnxt_qplib_rcfw_send_message(struct bnxt_qplib_rcfw *rcfw,
		204	struct cmdq_base req, struct creq_base resp,
		205	void *sbuf, u8 is_block);
227		206
228	int bnxt_qplib_deinit_rcfw(struct bnxt_qplib_rcfw *rcfw);	207	int bnxt_qplib_deinit_rcfw(struct bnxt_qplib_rcfw *rcfw);
229	int bnxt_qplib_init_rcfw(struct bnxt_qplib_rcfw *rcfw,	208	int bnxt_qplib_init_rcfw(struct bnxt_qplib_rcfw *rcfw,

drivers/infiniband/hw/bnxt_re/qplib_res.h+4−0

 #define HWQ_CMP(idx, hwq)	((idx) & ((hwq)->max_elements - 1))
+#define HWQ_FREE_SLOTS(hwq)	(hwq->max_elements - \
+				((HWQ_CMP(hwq->prod, hwq)\
+				- HWQ_CMP(hwq->cons, hwq))\
+				& (hwq->max_elements - 1)))
 enum bnxt_qplib_hwq_type {
 	HWQ_TYPE_CTX,
 	HWQ_TYPE_QUEUE,

drivers/infiniband/hw/bnxt_re/qplib_sp.c+83−250

@@ -55,37 +55,30 @@ int bnxt_qplib_get_dev_attr(struct bnxt_qplib_rcfw *rcfw, · 54 unmodified lines
55	struct bnxt_qplib_dev_attr *attr)	55	struct bnxt_qplib_dev_attr *attr)
56	{	56	{
57	struct cmdq_query_func req;	57	struct cmdq_query_func req;
58	struct creq_query_func_resp *resp;	58	struct creq_query_func_resp resp;
		59	struct bnxt_qplib_rcfw_sbuf *sbuf;
59	struct creq_query_func_resp_sb *sb;	60	struct creq_query_func_resp_sb *sb;
60	u16 cmd_flags = 0;	61	u16 cmd_flags = 0;
61	u32 temp;	62	u32 temp;
62	u8 *tqm_alloc;	63	u8 *tqm_alloc;
63	int i;	64	int i, rc = 0;
64		65
65	RCFW_CMD_PREP(req, QUERY_FUNC, cmd_flags);	66	RCFW_CMD_PREP(req, QUERY_FUNC, cmd_flags);
66		67
67	req.resp_size = sizeof(*sb) / BNXT_QPLIB_CMDQE_UNITS;	68	sbuf = bnxt_qplib_rcfw_alloc_sbuf(rcfw, sizeof(*sb));
68	resp = (struct creq_query_func_resp *)	69	if (!sbuf) {
69	bnxt_qplib_rcfw_send_message(rcfw, (void )&req, (void *)&sb,
70	0);
71	if (!resp) {
72	dev_err(&rcfw->pdev->dev, "QPLIB: SP: QUERY_FUNC send failed");
73	return -EINVAL;
74	}
75	if (!bnxt_qplib_rcfw_wait_for_resp(rcfw, le16_to_cpu(req.cookie))) {
76	/* Cmd timed out */
77	dev_err(&rcfw->pdev->dev, "QPLIB: SP: QUERY_FUNC timed out");
78	return -ETIMEDOUT;
79	}
80	if (resp->status \|\|
81	le16_to_cpu(resp->cookie) != le16_to_cpu(req.cookie)) {
82	dev_err(&rcfw->pdev->dev, "QPLIB: SP: QUERY_FUNC failed ");
83	dev_err(&rcfw->pdev->dev,	70	dev_err(&rcfw->pdev->dev,
84	"QPLIB: with status 0x%x cmdq 0x%x resp 0x%x",	71	"QPLIB: SP: QUERY_FUNC alloc side buffer failed");
85	resp->status, le16_to_cpu(req.cookie),	72	return -ENOMEM;
86	le16_to_cpu(resp->cookie));
87	return -EINVAL;
88	}	73	}
		74
		75	sb = sbuf->sb;
		76	req.resp_size = sizeof(*sb) / BNXT_QPLIB_CMDQE_UNITS;
		77	rc = bnxt_qplib_rcfw_send_message(rcfw, (void )&req, (void )&resp,
		78	(void *)sbuf, 0);
		79	if (rc)
		80	goto bail;
		81
89	/* Extract the context from the side buffer */	82	/* Extract the context from the side buffer */
90	attr->max_qp = le32_to_cpu(sb->max_qp);	83	attr->max_qp = le32_to_cpu(sb->max_qp);
91	attr->max_qp_rd_atom =	84	attr->max_qp_rd_atom =
@@ -95,6 +88,11 @@ int bnxt_qplib_get_dev_attr(struct bnxt_qplib_rcfw *rcfw, · 3 unmodified lines
95	sb->max_qp_init_rd_atom > BNXT_QPLIB_MAX_OUT_RD_ATOM ?	88	sb->max_qp_init_rd_atom > BNXT_QPLIB_MAX_OUT_RD_ATOM ?
96	BNXT_QPLIB_MAX_OUT_RD_ATOM : sb->max_qp_init_rd_atom;	89	BNXT_QPLIB_MAX_OUT_RD_ATOM : sb->max_qp_init_rd_atom;
97	attr->max_qp_wqes = le16_to_cpu(sb->max_qp_wr);	90	attr->max_qp_wqes = le16_to_cpu(sb->max_qp_wr);
		91	/*
		92	* 128 WQEs needs to be reserved for the HW (8916). Prevent
		93	* reporting the max number
		94	*/
		95	attr->max_qp_wqes -= BNXT_QPLIB_RESERVED_QP_WRS;
98	attr->max_qp_sges = sb->max_sge;	96	attr->max_qp_sges = sb->max_sge;
99	attr->max_cq = le32_to_cpu(sb->max_cq);	97	attr->max_cq = le32_to_cpu(sb->max_cq);
100	attr->max_cq_wqes = le32_to_cpu(sb->max_cqe);	98	attr->max_cq_wqes = le32_to_cpu(sb->max_cqe);
@@ -130,7 +128,10 @@ int bnxt_qplib_get_dev_attr(struct bnxt_qplib_rcfw *rcfw, · 29 unmodified lines
130	attr->tqm_alloc_reqs[i * 4 + 2] = *(++tqm_alloc);	128	attr->tqm_alloc_reqs[i * 4 + 2] = *(++tqm_alloc);
131	attr->tqm_alloc_reqs[i * 4 + 3] = *(++tqm_alloc);	129	attr->tqm_alloc_reqs[i * 4 + 3] = *(++tqm_alloc);
132	}	130	}
133	return 0;	131
		132	bail:
		133	bnxt_qplib_rcfw_free_sbuf(rcfw, sbuf);
		134	return rc;
134	}	135	}
135		136
136	/* SGID */	137	/* SGID */
@@ -178,8 +179,9 @@ int bnxt_qplib_del_sgid(struct bnxt_qplib_sgid_tbl *sgid_tbl, · 41 unmodified lines
178	/* Remove GID from the SGID table */	179	/* Remove GID from the SGID table */
179	if (update) {	180	if (update) {
180	struct cmdq_delete_gid req;	181	struct cmdq_delete_gid req;
181	struct creq_delete_gid_resp *resp;	182	struct creq_delete_gid_resp resp;
182	u16 cmd_flags = 0;	183	u16 cmd_flags = 0;
		184	int rc;
183		185
184	RCFW_CMD_PREP(req, DELETE_GID, cmd_flags);	186	RCFW_CMD_PREP(req, DELETE_GID, cmd_flags);
185	if (sgid_tbl->hw_id[index] == 0xFFFF) {	187	if (sgid_tbl->hw_id[index] == 0xFFFF) {
@@ -188,31 +190,10 @@ int bnxt_qplib_del_sgid(struct bnxt_qplib_sgid_tbl *sgid_tbl, · 2 unmodified lines
188	return -EINVAL;	190	return -EINVAL;
189	}	191	}
190	req.gid_index = cpu_to_le16(sgid_tbl->hw_id[index]);	192	req.gid_index = cpu_to_le16(sgid_tbl->hw_id[index]);
191	resp = (struct creq_delete_gid_resp *)	193	rc = bnxt_qplib_rcfw_send_message(rcfw, (void *)&req,
192	bnxt_qplib_rcfw_send_message(rcfw, (void *)&req, NULL,	194	(void *)&resp, NULL, 0);
193	0);	195	if (rc)
194	if (!resp) {	196	return rc;
195	dev_err(&res->pdev->dev,
196	"QPLIB: SP: DELETE_GID send failed");
197	return -EINVAL;
198	}
199	if (!bnxt_qplib_rcfw_wait_for_resp(rcfw,
200	le16_to_cpu(req.cookie))) {
201	/* Cmd timed out */
202	dev_err(&res->pdev->dev,
203	"QPLIB: SP: DELETE_GID timed out");
204	return -ETIMEDOUT;
205	}
206	if (resp->status \|\|
207	le16_to_cpu(resp->cookie) != le16_to_cpu(req.cookie)) {
208	dev_err(&res->pdev->dev,
209	"QPLIB: SP: DELETE_GID failed ");
210	dev_err(&res->pdev->dev,
211	"QPLIB: with status 0x%x cmdq 0x%x resp 0x%x",
212	resp->status, le16_to_cpu(req.cookie),
213	le16_to_cpu(resp->cookie));
214	return -EINVAL;
215	}
216	}	197	}
217	memcpy(&sgid_tbl->tbl[index], &bnxt_qplib_gid_zero,	198	memcpy(&sgid_tbl->tbl[index], &bnxt_qplib_gid_zero,
218	sizeof(bnxt_qplib_gid_zero));	199	sizeof(bnxt_qplib_gid_zero));
@@ -234,7 +215,7 @@ int bnxt_qplib_add_sgid(struct bnxt_qplib_sgid_tbl *sgid_tbl, · 15 unmodified lines
234	struct bnxt_qplib_res,	215	struct bnxt_qplib_res,
235	sgid_tbl);	216	sgid_tbl);
236	struct bnxt_qplib_rcfw *rcfw = res->rcfw;	217	struct bnxt_qplib_rcfw *rcfw = res->rcfw;
237	int i, free_idx, rc = 0;	218	int i, free_idx;
238		219
239	if (!sgid_tbl) {	220	if (!sgid_tbl) {
240	dev_err(&res->pdev->dev, "QPLIB: SGID table not allocated");	221	dev_err(&res->pdev->dev, "QPLIB: SGID table not allocated");
@@ -266,10 +247,11 @@ int bnxt_qplib_add_sgid(struct bnxt_qplib_sgid_tbl *sgid_tbl, · 25 unmodified lines
266	}	247	}
267	if (update) {	248	if (update) {
268	struct cmdq_add_gid req;	249	struct cmdq_add_gid req;
269	struct creq_add_gid_resp *resp;	250	struct creq_add_gid_resp resp;
270	u16 cmd_flags = 0;	251	u16 cmd_flags = 0;
271	u32 temp32[4];	252	u32 temp32[4];
272	u16 temp16[3];	253	u16 temp16[3];
		254	int rc;
273		255
274	RCFW_CMD_PREP(req, ADD_GID, cmd_flags);	256	RCFW_CMD_PREP(req, ADD_GID, cmd_flags);
275		257
@@ -290,31 +272,11 @@ int bnxt_qplib_add_sgid(struct bnxt_qplib_sgid_tbl *sgid_tbl, · 14 unmodified lines
290	req.src_mac[1] = cpu_to_be16(temp16[1]);	272	req.src_mac[1] = cpu_to_be16(temp16[1]);
291	req.src_mac[2] = cpu_to_be16(temp16[2]);	273	req.src_mac[2] = cpu_to_be16(temp16[2]);
292		274
293	resp = (struct creq_add_gid_resp *)	275	rc = bnxt_qplib_rcfw_send_message(rcfw, (void *)&req,
294	bnxt_qplib_rcfw_send_message(rcfw, (void *)&req,	276	(void *)&resp, NULL, 0);
295	NULL, 0);	277	if (rc)
296	if (!resp) {	278	return rc;
297	dev_err(&res->pdev->dev,	279	sgid_tbl->hw_id[free_idx] = le32_to_cpu(resp.xid);
298	"QPLIB: SP: ADD_GID send failed");
299	return -EINVAL;
300	}
301	if (!bnxt_qplib_rcfw_wait_for_resp(rcfw,
302	le16_to_cpu(req.cookie))) {
303	/* Cmd timed out */
304	dev_err(&res->pdev->dev,
305	"QPIB: SP: ADD_GID timed out");
306	return -ETIMEDOUT;
307	}
308	if (resp->status \|\|
309	le16_to_cpu(resp->cookie) != le16_to_cpu(req.cookie)) {
310	dev_err(&res->pdev->dev, "QPLIB: SP: ADD_GID failed ");
311	dev_err(&res->pdev->dev,
312	"QPLIB: with status 0x%x cmdq 0x%x resp 0x%x",
313	resp->status, le16_to_cpu(req.cookie),
314	le16_to_cpu(resp->cookie));
315	return -EINVAL;
316	}
317	sgid_tbl->hw_id[free_idx] = le32_to_cpu(resp->xid);
318	}	280	}
319	/* Add GID to the sgid_tbl */	281	/* Add GID to the sgid_tbl */
320	memcpy(&sgid_tbl->tbl[free_idx], gid, sizeof(*gid));	282	memcpy(&sgid_tbl->tbl[free_idx], gid, sizeof(*gid));
@@ -325,7 +287,7 @@ int bnxt_qplib_add_sgid(struct bnxt_qplib_sgid_tbl *sgid_tbl, · 4 unmodified lines
325		287
326	*index = free_idx;	288	*index = free_idx;
327	/* unlock */	289	/* unlock */
328	return rc;	290	return 0;
329	}	291	}
330		292
331	/* pkeys */	293	/* pkeys */
@@ -422,10 +384,11 @@ int bnxt_qplib_create_ah(struct bnxt_qplib_res res, struct bnxt_qplib_ah ah) · 90 unmodified lines
422	{	384	{
423	struct bnxt_qplib_rcfw *rcfw = res->rcfw;	385	struct bnxt_qplib_rcfw *rcfw = res->rcfw;
424	struct cmdq_create_ah req;	386	struct cmdq_create_ah req;
425	struct creq_create_ah_resp *resp;	387	struct creq_create_ah_resp resp;
426	u16 cmd_flags = 0;	388	u16 cmd_flags = 0;
427	u32 temp32[4];	389	u32 temp32[4];
428	u16 temp16[3];	390	u16 temp16[3];
		391	int rc;
429		392
430	RCFW_CMD_PREP(req, CREATE_AH, cmd_flags);	393	RCFW_CMD_PREP(req, CREATE_AH, cmd_flags);
431		394
@@ -450,28 +413,12 @@ int bnxt_qplib_create_ah(struct bnxt_qplib_res res, struct bnxt_qplib_ah ah) · 18 unmodified lines
450	req.dest_mac[1] = cpu_to_le16(temp16[1]);	413	req.dest_mac[1] = cpu_to_le16(temp16[1]);
451	req.dest_mac[2] = cpu_to_le16(temp16[2]);	414	req.dest_mac[2] = cpu_to_le16(temp16[2]);
452		415
453	resp = (struct creq_create_ah_resp *)	416	rc = bnxt_qplib_rcfw_send_message(rcfw, (void )&req, (void )&resp,
454	bnxt_qplib_rcfw_send_message(rcfw, (void *)&req,	417	NULL, 1);
455	NULL, 1);	418	if (rc)
456	if (!resp) {	419	return rc;
457	dev_err(&rcfw->pdev->dev, "QPLIB: SP: CREATE_AH send failed");	420
458	return -EINVAL;	421	ah->id = le32_to_cpu(resp.xid);
459	}
460	if (!bnxt_qplib_rcfw_block_for_resp(rcfw, le16_to_cpu(req.cookie))) {
461	/* Cmd timed out */
462	dev_err(&rcfw->pdev->dev, "QPLIB: SP: CREATE_AH timed out");
463	return -ETIMEDOUT;
464	}
465	if (resp->status \|\|
466	le16_to_cpu(resp->cookie) != le16_to_cpu(req.cookie)) {
467	dev_err(&rcfw->pdev->dev, "QPLIB: SP: CREATE_AH failed ");
468	dev_err(&rcfw->pdev->dev,
469	"QPLIB: with status 0x%x cmdq 0x%x resp 0x%x",
470	resp->status, le16_to_cpu(req.cookie),
471	le16_to_cpu(resp->cookie));
472	return -EINVAL;
473	}
474	ah->id = le32_to_cpu(resp->xid);
475	return 0;	422	return 0;
476	}	423	}
477		424
@@ -479,35 +426,19 @@ int bnxt_qplib_destroy_ah(struct bnxt_qplib_res res, struct bnxt_qplib_ah ah) · 1 unmodified line
479	{	426	{
480	struct bnxt_qplib_rcfw *rcfw = res->rcfw;	427	struct bnxt_qplib_rcfw *rcfw = res->rcfw;
481	struct cmdq_destroy_ah req;	428	struct cmdq_destroy_ah req;
482	struct creq_destroy_ah_resp *resp;	429	struct creq_destroy_ah_resp resp;
483	u16 cmd_flags = 0;	430	u16 cmd_flags = 0;
		431	int rc;
484		432
485	/* Clean up the AH table in the device */	433	/* Clean up the AH table in the device */
486	RCFW_CMD_PREP(req, DESTROY_AH, cmd_flags);	434	RCFW_CMD_PREP(req, DESTROY_AH, cmd_flags);
487		435
488	req.ah_cid = cpu_to_le32(ah->id);	436	req.ah_cid = cpu_to_le32(ah->id);
489		437
490	resp = (struct creq_destroy_ah_resp *)	438	rc = bnxt_qplib_rcfw_send_message(rcfw, (void )&req, (void )&resp,
491	bnxt_qplib_rcfw_send_message(rcfw, (void *)&req,	439	NULL, 1);
492	NULL, 1);	440	if (rc)
493	if (!resp) {	441	return rc;
494	dev_err(&rcfw->pdev->dev, "QPLIB: SP: DESTROY_AH send failed");
495	return -EINVAL;
496	}
497	if (!bnxt_qplib_rcfw_block_for_resp(rcfw, le16_to_cpu(req.cookie))) {
498	/* Cmd timed out */
499	dev_err(&rcfw->pdev->dev, "QPLIB: SP: DESTROY_AH timed out");
500	return -ETIMEDOUT;
501	}
502	if (resp->status \|\|
503	le16_to_cpu(resp->cookie) != le16_to_cpu(req.cookie)) {
504	dev_err(&rcfw->pdev->dev, "QPLIB: SP: DESTROY_AH failed ");
505	dev_err(&rcfw->pdev->dev,
506	"QPLIB: with status 0x%x cmdq 0x%x resp 0x%x",
507	resp->status, le16_to_cpu(req.cookie),
508	le16_to_cpu(resp->cookie));
509	return -EINVAL;
510	}
511	return 0;	442	return 0;
512	}	443	}
513		444
@@ -516,8 +447,9 @@ int bnxt_qplib_free_mrw(struct bnxt_qplib_res res, struct bnxt_qplib_mrw mrw) · 2 unmodified lines
516	{	447	{
517	struct bnxt_qplib_rcfw *rcfw = res->rcfw;	448	struct bnxt_qplib_rcfw *rcfw = res->rcfw;
518	struct cmdq_deallocate_key req;	449	struct cmdq_deallocate_key req;
519	struct creq_deallocate_key_resp *resp;	450	struct creq_deallocate_key_resp resp;
520	u16 cmd_flags = 0;	451	u16 cmd_flags = 0;
		452	int rc;
521		453
522	if (mrw->lkey == 0xFFFFFFFF) {	454	if (mrw->lkey == 0xFFFFFFFF) {
523	dev_info(&res->pdev->dev,	455	dev_info(&res->pdev->dev,
@@ -536,27 +468,11 @@ int bnxt_qplib_free_mrw(struct bnxt_qplib_res res, struct bnxt_qplib_mrw mrw) · 12 unmodified lines
536	else	468	else
537	req.key = cpu_to_le32(mrw->lkey);	469	req.key = cpu_to_le32(mrw->lkey);
538		470
539	resp = (struct creq_deallocate_key_resp *)	471	rc = bnxt_qplib_rcfw_send_message(rcfw, (void )&req, (void )&resp,
540	bnxt_qplib_rcfw_send_message(rcfw, (void *)&req,	472	NULL, 0);
541	NULL, 0);	473	if (rc)
542	if (!resp) {	474	return rc;
543	dev_err(&res->pdev->dev, "QPLIB: SP: FREE_MR send failed");	475
544	return -EINVAL;
545	}
546	if (!bnxt_qplib_rcfw_wait_for_resp(rcfw, le16_to_cpu(req.cookie))) {
547	/* Cmd timed out */
548	dev_err(&res->pdev->dev, "QPLIB: SP: FREE_MR timed out");
549	return -ETIMEDOUT;
550	}
551	if (resp->status \|\|
552	le16_to_cpu(resp->cookie) != le16_to_cpu(req.cookie)) {
553	dev_err(&res->pdev->dev, "QPLIB: SP: FREE_MR failed ");
554	dev_err(&res->pdev->dev,
555	"QPLIB: with status 0x%x cmdq 0x%x resp 0x%x",
556	resp->status, le16_to_cpu(req.cookie),
557	le16_to_cpu(resp->cookie));
558	return -EINVAL;
559	}
560	/* Free the qplib's MRW memory */	476	/* Free the qplib's MRW memory */
561	if (mrw->hwq.max_elements)	477	if (mrw->hwq.max_elements)
562	bnxt_qplib_free_hwq(res->pdev, &mrw->hwq);	478	bnxt_qplib_free_hwq(res->pdev, &mrw->hwq);
@@ -568,9 +484,10 @@ int bnxt_qplib_alloc_mrw(struct bnxt_qplib_res res, struct bnxt_qplib_mrw mrw) · 5 unmodified lines
568	{	484	{
569	struct bnxt_qplib_rcfw *rcfw = res->rcfw;	485	struct bnxt_qplib_rcfw *rcfw = res->rcfw;
570	struct cmdq_allocate_mrw req;	486	struct cmdq_allocate_mrw req;
571	struct creq_allocate_mrw_resp *resp;	487	struct creq_allocate_mrw_resp resp;
572	u16 cmd_flags = 0;	488	u16 cmd_flags = 0;
573	unsigned long tmp;	489	unsigned long tmp;
		490	int rc;
574		491
575	RCFW_CMD_PREP(req, ALLOCATE_MRW, cmd_flags);	492	RCFW_CMD_PREP(req, ALLOCATE_MRW, cmd_flags);
576		493
@@ -584,33 +501,17 @@ int bnxt_qplib_alloc_mrw(struct bnxt_qplib_res res, struct bnxt_qplib_mrw mrw) · 7 unmodified lines
584	tmp = (unsigned long)mrw;	501	tmp = (unsigned long)mrw;
585	req.mrw_handle = cpu_to_le64(tmp);	502	req.mrw_handle = cpu_to_le64(tmp);
586		503
587	resp = (struct creq_allocate_mrw_resp *)	504	rc = bnxt_qplib_rcfw_send_message(rcfw, (void *)&req,
588	bnxt_qplib_rcfw_send_message(rcfw, (void *)&req,	505	(void *)&resp, NULL, 0);
589	NULL, 0);	506	if (rc)
590	if (!resp) {	507	return rc;
591	dev_err(&rcfw->pdev->dev, "QPLIB: SP: ALLOC_MRW send failed");	508
592	return -EINVAL;
593	}
594	if (!bnxt_qplib_rcfw_wait_for_resp(rcfw, le16_to_cpu(req.cookie))) {
595	/* Cmd timed out */
596	dev_err(&rcfw->pdev->dev, "QPLIB: SP: ALLOC_MRW timed out");
597	return -ETIMEDOUT;
598	}
599	if (resp->status \|\|
600	le16_to_cpu(resp->cookie) != le16_to_cpu(req.cookie)) {
601	dev_err(&rcfw->pdev->dev, "QPLIB: SP: ALLOC_MRW failed ");
602	dev_err(&rcfw->pdev->dev,
603	"QPLIB: with status 0x%x cmdq 0x%x resp 0x%x",
604	resp->status, le16_to_cpu(req.cookie),
605	le16_to_cpu(resp->cookie));
606	return -EINVAL;
607	}
608	if ((mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1) \|\|	509	if ((mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1) \|\|
609	(mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A) \|\|	510	(mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A) \|\|
610	(mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B))	511	(mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B))
611	mrw->rkey = le32_to_cpu(resp->xid);	512	mrw->rkey = le32_to_cpu(resp.xid);
612	else	513	else
613	mrw->lkey = le32_to_cpu(resp->xid);	514	mrw->lkey = le32_to_cpu(resp.xid);
614	return 0;	515	return 0;
615	}	516	}
616		517
@@ -619,40 +520,17 @@ int bnxt_qplib_dereg_mrw(struct bnxt_qplib_res res, struct bnxt_qplib_mrw mrw, · 2 unmodified lines
619	{	520	{
620	struct bnxt_qplib_rcfw *rcfw = res->rcfw;	521	struct bnxt_qplib_rcfw *rcfw = res->rcfw;
621	struct cmdq_deregister_mr req;	522	struct cmdq_deregister_mr req;
622	struct creq_deregister_mr_resp *resp;	523	struct creq_deregister_mr_resp resp;
623	u16 cmd_flags = 0;	524	u16 cmd_flags = 0;
624	int rc;	525	int rc;
625		526
626	RCFW_CMD_PREP(req, DEREGISTER_MR, cmd_flags);	527	RCFW_CMD_PREP(req, DEREGISTER_MR, cmd_flags);
627		528
628	req.lkey = cpu_to_le32(mrw->lkey);	529	req.lkey = cpu_to_le32(mrw->lkey);
629	resp = (struct creq_deregister_mr_resp *)	530	rc = bnxt_qplib_rcfw_send_message(rcfw, (void *)&req,
630	bnxt_qplib_rcfw_send_message(rcfw, (void *)&req,	531	(void *)&resp, NULL, block);
631	NULL, block);	532	if (rc)
632	if (!resp) {	533	return rc;
633	dev_err(&rcfw->pdev->dev, "QPLIB: SP: DEREG_MR send failed");
634	return -EINVAL;
635	}
636	if (block)
637	rc = bnxt_qplib_rcfw_block_for_resp(rcfw,
638	le16_to_cpu(req.cookie));
639	else
640	rc = bnxt_qplib_rcfw_wait_for_resp(rcfw,
641	le16_to_cpu(req.cookie));
642	if (!rc) {
643	/* Cmd timed out */
644	dev_err(&res->pdev->dev, "QPLIB: SP: DEREG_MR timed out");
645	return -ETIMEDOUT;
646	}
647	if (resp->status \|\|
648	le16_to_cpu(resp->cookie) != le16_to_cpu(req.cookie)) {
649	dev_err(&rcfw->pdev->dev, "QPLIB: SP: DEREG_MR failed ");
650	dev_err(&rcfw->pdev->dev,
651	"QPLIB: with status 0x%x cmdq 0x%x resp 0x%x",
652	resp->status, le16_to_cpu(req.cookie),
653	le16_to_cpu(resp->cookie));
654	return -EINVAL;
655	}
656		534
657	/* Free the qplib's MR memory */	535	/* Free the qplib's MR memory */
658	if (mrw->hwq.max_elements) {	536	if (mrw->hwq.max_elements) {
@@ -669,7 +547,7 @@ int bnxt_qplib_reg_mr(struct bnxt_qplib_res res, struct bnxt_qplib_mrw mr, · 10 unmodified lines
669	{	547	{
670	struct bnxt_qplib_rcfw *rcfw = res->rcfw;	548	struct bnxt_qplib_rcfw *rcfw = res->rcfw;
671	struct cmdq_register_mr req;	549	struct cmdq_register_mr req;
672	struct creq_register_mr_resp *resp;	550	struct creq_register_mr_resp resp;
673	u16 cmd_flags = 0, level;	551	u16 cmd_flags = 0, level;
674	int pg_ptrs, pages, i, rc;	552	int pg_ptrs, pages, i, rc;
675	dma_addr_t **pbl_ptr;	553	dma_addr_t **pbl_ptr;
@@ -730,36 +608,11 @@ int bnxt_qplib_reg_mr(struct bnxt_qplib_res res, struct bnxt_qplib_mrw mr, · 54 unmodified lines
730	req.key = cpu_to_le32(mr->lkey);	608	req.key = cpu_to_le32(mr->lkey);
731	req.mr_size = cpu_to_le64(mr->total_size);	609	req.mr_size = cpu_to_le64(mr->total_size);
732		610
733	resp = (struct creq_register_mr_resp *)	611	rc = bnxt_qplib_rcfw_send_message(rcfw, (void *)&req,
734	bnxt_qplib_rcfw_send_message(rcfw, (void *)&req,	612	(void *)&resp, NULL, block);
735	NULL, block);	613	if (rc)
736	if (!resp) {
737	dev_err(&res->pdev->dev, "SP: REG_MR send failed");
738	rc = -EINVAL;
739	goto fail;
740	}
741	if (block)
742	rc = bnxt_qplib_rcfw_block_for_resp(rcfw,
743	le16_to_cpu(req.cookie));
744	else
745	rc = bnxt_qplib_rcfw_wait_for_resp(rcfw,
746	le16_to_cpu(req.cookie));
747	if (!rc) {
748	/* Cmd timed out */
749	dev_err(&res->pdev->dev, "SP: REG_MR timed out");
750	rc = -ETIMEDOUT;
751	goto fail;
752	}
753	if (resp->status \|\|
754	le16_to_cpu(resp->cookie) != le16_to_cpu(req.cookie)) {
755	dev_err(&res->pdev->dev, "QPLIB: SP: REG_MR failed ");
756	dev_err(&res->pdev->dev,
757	"QPLIB: SP: with status 0x%x cmdq 0x%x resp 0x%x",
758	resp->status, le16_to_cpu(req.cookie),
759	le16_to_cpu(resp->cookie));
760	rc = -EINVAL;
761	goto fail;	614	goto fail;
762	}	615
763	return 0;	616	return 0;
764		617
765	fail:	618	fail:
@@ -804,35 +657,15 @@ int bnxt_qplib_map_tc2cos(struct bnxt_qplib_res res, u16 cids) · 38 unmodified lines
804	{	657	{
805	struct bnxt_qplib_rcfw *rcfw = res->rcfw;	658	struct bnxt_qplib_rcfw *rcfw = res->rcfw;
806	struct cmdq_map_tc_to_cos req;	659	struct cmdq_map_tc_to_cos req;
807	struct creq_map_tc_to_cos_resp *resp;	660	struct creq_map_tc_to_cos_resp resp;
808	u16 cmd_flags = 0;	661	u16 cmd_flags = 0;
809	int tleft;	662	int rc = 0;
810		663
811	RCFW_CMD_PREP(req, MAP_TC_TO_COS, cmd_flags);	664	RCFW_CMD_PREP(req, MAP_TC_TO_COS, cmd_flags);
812	req.cos0 = cpu_to_le16(cids[0]);	665	req.cos0 = cpu_to_le16(cids[0]);
813	req.cos1 = cpu_to_le16(cids[1]);	666	req.cos1 = cpu_to_le16(cids[1]);
814		667
815	resp = bnxt_qplib_rcfw_send_message(rcfw, (void *)&req, NULL, 0);	668	rc = bnxt_qplib_rcfw_send_message(rcfw, (void *)&req,
816	if (!resp) {	669	(void *)&resp, NULL, 0);
817	dev_err(&res->pdev->dev, "QPLIB: SP: MAP_TC2COS send failed");
818	return -EINVAL;
819	}
820
821	tleft = bnxt_qplib_rcfw_block_for_resp(rcfw, le16_to_cpu(req.cookie));
822	if (!tleft) {
823	dev_err(&res->pdev->dev, "QPLIB: SP: MAP_TC2COS timed out");
824	return -ETIMEDOUT;
825	}
826
827	if (resp->status \|\|
828	le16_to_cpu(resp->cookie) != le16_to_cpu(req.cookie)) {
829	dev_err(&res->pdev->dev, "QPLIB: SP: MAP_TC2COS failed ");
830	dev_err(&res->pdev->dev,
831	"QPLIB: with status 0x%x cmdq 0x%x resp 0x%x",
832	resp->status, le16_to_cpu(req.cookie),
833	le16_to_cpu(resp->cookie));
834	return -EINVAL;
835	}
836
837	return 0;	670	return 0;
838	}	671	}

drivers/infiniband/hw/bnxt_re/qplib_sp.h+2−0

@@ -40,6 +40,8 @@ · 39 unmodified lines
40	#ifndef __BNXT_QPLIB_SP_H__	40	#ifndef __BNXT_QPLIB_SP_H__
41	#define __BNXT_QPLIB_SP_H__	41	#define __BNXT_QPLIB_SP_H__
42		42
		43	#define BNXT_QPLIB_RESERVED_QP_WRS 128
		44
43	struct bnxt_qplib_dev_attr {	45	struct bnxt_qplib_dev_attr {
44	char fw_ver[32];	46	char fw_ver[32];
45	u16 max_sgid;	47	u16 max_sgid;

drivers/infiniband/hw/cxgb4/cm.c+7−2

 	ep = *((struct c4iw_ep **)(skb->cb + 2 * sizeof(void *)));
 	release_ep_resources(ep);
+	kfree_skb(skb);
 	return 0;
 }
 	ep = *((struct c4iw_ep **)(skb->cb + 2 * sizeof(void *)));
 	c4iw_put_ep(&ep->parent_ep->com);
 	release_ep_resources(ep);
+	kfree_skb(skb);
 	return 0;
 }
 	pr_debug("%s rdev %p\n", __func__, rdev);
 	req->cmd = CPL_ABORT_NO_RST;
+	skb_get(skb);
 	ret = c4iw_ofld_send(rdev, skb);
 	if (ret) {
 		__state_set(&ep->com, DEAD);
 		queue_arp_failure_cpl(ep, skb, FAKE_CPL_PUT_EP_SAFE);
-	}
+	} else
+		kfree_skb(skb);
 }
 static int send_flowc(struct c4iw_ep *ep)
 		goto reject;
 	}
-	hdrs = sizeof(struct iphdr) + sizeof(struct tcphdr) +
+	hdrs = ((iptype == 4) ? sizeof(struct iphdr) : sizeof(struct ipv6hdr)) +
+	       sizeof(struct tcphdr) +
 	       ((enable_tcp_timestamps && req->tcpopt.tstamp) ? 12 : 0);
 	if (peer_mss && child_ep->mtu > (peer_mss + hdrs))
 		child_ep->mtu = peer_mss + hdrs;

drivers/infiniband/hw/cxgb4/device.c+8−4

 		kfree(entry);
 	}
-	list_for_each_safe(pos, nxt, &uctx->qpids) {
+	list_for_each_safe(pos, nxt, &uctx->cqids) {
 		entry = list_entry(pos, struct c4iw_qid_list, entry);
 		list_del_init(&entry->entry);
 		kfree(entry);
 	rdev->free_workq = create_singlethread_workqueue("iw_cxgb4_free");
 	if (!rdev->free_workq) {
 		err = -ENOMEM;
-		goto err_free_status_page;
+		goto err_free_status_page_and_wr_log;
 	}
 	rdev->status_page->db_off = 0;
 	return 0;
-err_free_status_page:
+err_free_status_page_and_wr_log:
+	if (c4iw_wr_log && rdev->wr_log)
+		kfree(rdev->wr_log);
 	free_page((unsigned long)rdev->status_page);
 destroy_ocqp_pool:
 	c4iw_ocqp_pool_destroy(rdev);
 {
 	destroy_workqueue(rdev->free_workq);
 	kfree(rdev->wr_log);
+	c4iw_release_dev_ucontext(rdev, &rdev->uctx);
 	free_page((unsigned long)rdev->status_page);
 	c4iw_pblpool_destroy(rdev);
 	c4iw_rqtpool_destroy(rdev);
+	c4iw_ocqp_pool_destroy(rdev);
 	c4iw_destroy_resource(&rdev->resource);
 }
 		 devp->rdev.lldi.sge_egrstatuspagesize);
 	devp->rdev.hw_queue.t4_eq_status_entries =
-		devp->rdev.lldi.sge_ingpadboundary > 64 ? 2 : 1;
+		devp->rdev.lldi.sge_egrstatuspagesize / 64;
 	devp->rdev.hw_queue.t4_max_eq_size = 65520;
 	devp->rdev.hw_queue.t4_max_iq_size = 65520;
 	devp->rdev.hw_queue.t4_max_rq_size = 8192 -

drivers/infiniband/hw/hfi1/chip.c+50−17

@@ -6312,25 +6312,38 @@ static void handle_8051_request(struct hfi1_pportdata *ppd) · 6311 unmodified lines
6312	}	6312	}
6313	}	6313	}
6314		6314
6315	static void write_global_credit(struct hfi1_devdata *dd,	6315	/*
6316	u8 vau, u16 total, u16 shared)	6316	* Set up allocation unit vaulue.
		6317	*/
		6318	void set_up_vau(struct hfi1_devdata *dd, u8 vau)
6317	{	6319	{
6318	write_csr(dd, SEND_CM_GLOBAL_CREDIT,	6320	u64 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);
6319	((u64)total <<	6321
6320	SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT) \|	6322	/* do not modify other values in the register */
6321	((u64)shared <<	6323	reg &= ~SEND_CM_GLOBAL_CREDIT_AU_SMASK;
6322	SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SHIFT) \|	6324	reg \|= (u64)vau << SEND_CM_GLOBAL_CREDIT_AU_SHIFT;
6323	((u64)vau << SEND_CM_GLOBAL_CREDIT_AU_SHIFT));	6325	write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg);
6324	}	6326	}
6325		6327
6326	/*	6328	/*
6327	* Set up initial VL15 credits of the remote. Assumes the rest of	6329	* Set up initial VL15 credits of the remote. Assumes the rest of
6328	* the CM credit registers are zero from a previous global or credit reset .	6330	* the CM credit registers are zero from a previous global or credit reset.
		6331	* Shared limit for VL15 will always be 0.
6329	*/	6332	*/
6330	void set_up_vl15(struct hfi1_devdata *dd, u8 vau, u16 vl15buf)	6333	void set_up_vl15(struct hfi1_devdata *dd, u16 vl15buf)
6331	{	6334	{
6332	/* leave shared count at zero for both global and VL15 */	6335	u64 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);
6333	write_global_credit(dd, vau, vl15buf, 0);	6336
		6337	/* set initial values for total and shared credit limit */
		6338	reg &= ~(SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SMASK \|
		6339	SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SMASK);
		6340
		6341	/*
		6342	* Set total limit to be equal to VL15 credits.
		6343	* Leave shared limit at 0.
		6344	*/
		6345	reg \|= (u64)vl15buf << SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT;
		6346	write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg);
6334		6347
6335	write_csr(dd, SEND_CM_CREDIT_VL15, (u64)vl15buf	6348	write_csr(dd, SEND_CM_CREDIT_VL15, (u64)vl15buf
6336	<< SEND_CM_CREDIT_VL15_DEDICATED_LIMIT_VL_SHIFT);	6349	<< SEND_CM_CREDIT_VL15_DEDICATED_LIMIT_VL_SHIFT);
@@ -6348,9 +6361,11 @@ void reset_link_credits(struct hfi1_devdata *dd) · 11 unmodified lines
6348	for (i = 0; i < TXE_NUM_DATA_VL; i++)	6361	for (i = 0; i < TXE_NUM_DATA_VL; i++)
6349	write_csr(dd, SEND_CM_CREDIT_VL + (8 * i), 0);	6362	write_csr(dd, SEND_CM_CREDIT_VL + (8 * i), 0);
6350	write_csr(dd, SEND_CM_CREDIT_VL15, 0);	6363	write_csr(dd, SEND_CM_CREDIT_VL15, 0);
6351	write_global_credit(dd, 0, 0, 0);	6364	write_csr(dd, SEND_CM_GLOBAL_CREDIT, 0);
6352	/* reset the CM block */	6365	/* reset the CM block */
6353	pio_send_control(dd, PSC_CM_RESET);	6366	pio_send_control(dd, PSC_CM_RESET);
		6367	/* reset cached value */
		6368	dd->vl15buf_cached = 0;
6354	}	6369	}
6355		6370
6356	/* convert a vCU to a CU */	6371	/* convert a vCU to a CU */
@@ -6839,24 +6854,35 @@ void handle_link_up(struct work_struct *work) · 482 unmodified lines
6839	{	6854	{
6840	struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,	6855	struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
6841	link_up_work);	6856	link_up_work);
		6857	struct hfi1_devdata *dd = ppd->dd;
		6858
6842	set_link_state(ppd, HLS_UP_INIT);	6859	set_link_state(ppd, HLS_UP_INIT);
6843		6860
6844	/* cache the read of DC_LCB_STS_ROUND_TRIP_LTP_CNT */	6861	/* cache the read of DC_LCB_STS_ROUND_TRIP_LTP_CNT */
6845	read_ltp_rtt(ppd->dd);	6862	read_ltp_rtt(dd);
6846	/*	6863	/*
6847	* OPA specifies that certain counters are cleared on a transition	6864	* OPA specifies that certain counters are cleared on a transition
6848	* to link up, so do that.	6865	* to link up, so do that.
6849	*/	6866	*/
6850	clear_linkup_counters(ppd->dd);	6867	clear_linkup_counters(dd);
6851	/*	6868	/*
6852	* And (re)set link up default values.	6869	* And (re)set link up default values.
6853	*/	6870	*/
6854	set_linkup_defaults(ppd);	6871	set_linkup_defaults(ppd);
6855		6872
		6873	/*
		6874	* Set VL15 credits. Use cached value from verify cap interrupt.
		6875	* In case of quick linkup or simulator, vl15 value will be set by
		6876	* handle_linkup_change. VerifyCap interrupt handler will not be
		6877	* called in those scenarios.
		6878	*/
		6879	if (!(quick_linkup \|\| dd->icode == ICODE_FUNCTIONAL_SIMULATOR))
		6880	set_up_vl15(dd, dd->vl15buf_cached);
		6881
6856	/* enforce link speed enabled */	6882	/* enforce link speed enabled */
6857	if ((ppd->link_speed_active & ppd->link_speed_enabled) == 0) {	6883	if ((ppd->link_speed_active & ppd->link_speed_enabled) == 0) {
6858	/* oops - current speed is not enabled, bounce */	6884	/* oops - current speed is not enabled, bounce */
6859	dd_dev_err(ppd->dd,	6885	dd_dev_err(dd,
6860	"Link speed active 0x%x is outside enabled 0x%x, downing link\n",	6886	"Link speed active 0x%x is outside enabled 0x%x, downing link\n",
6861	ppd->link_speed_active, ppd->link_speed_enabled);	6887	ppd->link_speed_active, ppd->link_speed_enabled);
6862	set_link_down_reason(ppd, OPA_LINKDOWN_REASON_SPEED_POLICY, 0,	6888	set_link_down_reason(ppd, OPA_LINKDOWN_REASON_SPEED_POLICY, 0,
@@ -7357,7 +7383,14 @@ void handle_verify_cap(struct work_struct *work) · 494 unmodified lines
7357	*/	7383	*/
7358	if (vau == 0)	7384	if (vau == 0)
7359	vau = 1;	7385	vau = 1;
7360	set_up_vl15(dd, vau, vl15buf);	7386	set_up_vau(dd, vau);
		7387
		7388	/*
		7389	* Set VL15 credits to 0 in global credit register. Cache remote VL15
		7390	* credits value and wait for link-up interrupt ot set it.
		7391	*/
		7392	set_up_vl15(dd, 0);
		7393	dd->vl15buf_cached = vl15buf;
7361		7394
7362	/* set up the LCB CRC mode */	7395	/* set up the LCB CRC mode */
7363	crc_mask = ppd->port_crc_mode_enabled & partner_supported_crc;	7396	crc_mask = ppd->port_crc_mode_enabled & partner_supported_crc;

drivers/infiniband/hw/hfi1/chip_registers.h+2−0

 #define SEND_CM_CTRL_FORCE_CREDIT_MODE_SMASK 0x8ull
 #define SEND_CM_CTRL_RESETCSR 0x0000000000000020ull
 #define SEND_CM_GLOBAL_CREDIT (TXE + 0x000000000508)
+#define SEND_CM_GLOBAL_CREDIT_AU_MASK 0x7ull
 #define SEND_CM_GLOBAL_CREDIT_AU_SHIFT 16
+#define SEND_CM_GLOBAL_CREDIT_AU_SMASK 0x70000ull
 #define SEND_CM_GLOBAL_CREDIT_RESETCSR 0x0000094000030000ull
 #define SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_MASK 0xFFFFull
 #define SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SHIFT 0

drivers/infiniband/hw/hfi1/hfi.h+10−1

 	/* initial vl15 credits to use */
 	u16 vl15_init;
+	/*
+	 * Cached value for vl15buf, read during verify cap interrupt. VL15
+	 * credits are to be kept at 0 and set when handling the link-up
+	 * interrupt. This removes the possibility of receiving VL15 MAD
+	 * packets before this HFI is ready.
+	 */
+	u16 vl15buf_cached;
 	/* Misc small ints */
 	u8 n_krcv_queues;
 	u8 qos_shift;
 int fm_get_table(struct hfi1_pportdata *ppd, int which, void *t);
 int fm_set_table(struct hfi1_pportdata *ppd, int which, void *t);
-void set_up_vl15(struct hfi1_devdata *dd, u8 vau, u16 vl15buf);
+void set_up_vau(struct hfi1_devdata *dd, u8 vau);
+void set_up_vl15(struct hfi1_devdata *dd, u16 vl15buf);
 void reset_link_credits(struct hfi1_devdata *dd);
 void assign_remote_cm_au_table(struct hfi1_devdata *dd, u8 vcu);

drivers/infiniband/hw/hfi1/intr.c+2−1

@@ -130,7 +130,8 @@ void handle_linkup_change(struct hfi1_devdata *dd, u32 linkup) · 129 unmodified lines
130	* the remote values. Both sides must be using the values.	130	* the remote values. Both sides must be using the values.
131	*/	131	*/
132	if (quick_linkup \|\| dd->icode == ICODE_FUNCTIONAL_SIMULATOR) {	132	if (quick_linkup \|\| dd->icode == ICODE_FUNCTIONAL_SIMULATOR) {
133	set_up_vl15(dd, dd->vau, dd->vl15_init);	133	set_up_vau(dd, dd->vau);
		134	set_up_vl15(dd, dd->vl15_init);
134	assign_remote_cm_au_table(dd, dd->vcu);	135	assign_remote_cm_au_table(dd, dd->vcu);
135	}	136	}
136		137

drivers/infiniband/hw/hfi1/pcie.c+2−2

@@ -207,8 +207,8 @@ int hfi1_pcie_ddinit(struct hfi1_devdata dd, struct pci_dev pdev) · 206 unmodified lines
207	/*	207	/*
208	* Save BARs and command to rewrite after device reset.	208	* Save BARs and command to rewrite after device reset.
209	*/	209	*/
210	dd->pcibar0 = addr;	210	pci_read_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0, &dd->pcibar0);
211	dd->pcibar1 = addr >> 32;	211	pci_read_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1, &dd->pcibar1);
212	pci_read_config_dword(dd->pcidev, PCI_ROM_ADDRESS, &dd->pci_rom);	212	pci_read_config_dword(dd->pcidev, PCI_ROM_ADDRESS, &dd->pci_rom);
213	pci_read_config_word(dd->pcidev, PCI_COMMAND, &dd->pci_command);	213	pci_read_config_word(dd->pcidev, PCI_COMMAND, &dd->pci_command);
214	pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL, &dd->pcie_devctl);	214	pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL, &dd->pcie_devctl);

drivers/infiniband/hw/hfi1/rc.c+4−1

 		ret = hfi1_rvt_get_rwqe(qp, 1);
 		if (ret < 0)
 			goto nack_op_err;
-		if (!ret)
+		if (!ret) {
+			/* peer will send again */
+			rvt_put_ss(&qp->r_sge);
 			goto rnr_nak;
+		}
 		wc.ex.imm_data = ohdr->u.rc.imm_data;
 		wc.wc_flags = IB_WC_WITH_IMM;
 		goto send_last;

drivers/infiniband/hw/hfi1/sysfs.c+2−1

@@ -196,7 +196,8 @@ static const struct sysfs_ops port_cc_sysfs_ops = { · 195 unmodified lines
196	};	196	};
197		197
198	static struct attribute *port_cc_default_attributes[] = {	198	static struct attribute *port_cc_default_attributes[] = {
199	&cc_prescan_attr.attr	199	&cc_prescan_attr.attr,
		200	NULL
200	};	201	};
201		202
202	static struct kobj_type port_cc_ktype = {	203	static struct kobj_type port_cc_ktype = {

drivers/infiniband/hw/i40iw/i40iw_cm.c+1−2

 	}
 	ctrl_ird |= IETF_PEER_TO_PEER;
-	ctrl_ird |= IETF_FLPDU_ZERO_LEN;
 	switch (mpa_key) {
 	case MPA_KEY_REQUEST:
 		} else {
 			type = I40IW_CM_EVENT_CONNECTED;
 			cm_node->state = I40IW_CM_STATE_OFFLOADED;
-			i40iw_send_ack(cm_node);
 		}
+		i40iw_send_ack(cm_node);
 		break;
 	default:
 		pr_err("%s wrong cm_node state =%d\n", __func__, cm_node->state);

drivers/infiniband/hw/i40iw/i40iw_ctrl.c+1−11

 	struct i40iw_sc_dev *dev = vsi->dev;
 	struct i40iw_sc_qp *qp = NULL;
 	bool qs_handle_change = false;
-	bool mss_change = false;
 	unsigned long flags;
 	u16 qs_handle;
 	int i;
-	if (vsi->mss != l2params->mss) {
+	vsi->mss = l2params->mss;
-		mss_change = true;
-		vsi->mss = l2params->mss;
-	}
 	i40iw_fill_qos_list(l2params->qs_handle_list);
 	for (i = 0; i < I40IW_MAX_USER_PRIORITY; i++) {
 		qs_handle = l2params->qs_handle_list[i];
 		if (vsi->qos[i].qs_handle != qs_handle)
 			qs_handle_change = true;
-		else if (!mss_change)
-			continue;       /* no MSS nor qs handle change */
 		spin_lock_irqsave(&vsi->qos[i].lock, flags);
 		qp = i40iw_get_qp(&vsi->qos[i].qplist, qp);
 		while (qp) {
-			if (mss_change)
-				i40iw_qp_mss_modify(dev, qp);
 			if (qs_handle_change) {
 				qp->qs_handle = qs_handle;
 				/* issue cqp suspend command */
 	set_64bit_val(wqe,
 		      8,
-		      LS_64(info->new_mss, I40IW_CQPSQ_QP_NEWMSS) |
 		      LS_64(term_len, I40IW_CQPSQ_QP_TERMLEN));
 	set_64bit_val(wqe, 16, qp->hw_host_ctx_pa);
 		 LS_64(info->cq_num_valid, I40IW_CQPSQ_QP_CQNUMVALID) |
 		 LS_64(info->force_loopback, I40IW_CQPSQ_QP_FORCELOOPBACK) |
 		 LS_64(qp->qp_type, I40IW_CQPSQ_QP_QPTYPE) |
-		 LS_64(info->mss_change, I40IW_CQPSQ_QP_MSSCHANGE) |
 		 LS_64(info->static_rsrc, I40IW_CQPSQ_QP_STATRSRC) |
 		 LS_64(info->remove_hash_idx, I40IW_CQPSQ_QP_REMOVEHASHENTRY) |
 		 LS_64(term_actions, I40IW_CQPSQ_QP_TERMACT) |

drivers/infiniband/hw/i40iw/i40iw_main.c+13−7

@@ -1319,13 +1319,13 @@ static enum i40iw_status_code i40iw_initialize_dev(struct i40iw_device *iwdev, · 1318 unmodified lines
1319	status = i40iw_obj_aligned_mem(iwdev, &mem, I40IW_QUERY_FPM_BUF_SIZE,	1319	status = i40iw_obj_aligned_mem(iwdev, &mem, I40IW_QUERY_FPM_BUF_SIZE,
1320	I40IW_FPM_QUERY_BUF_ALIGNMENT_MASK);	1320	I40IW_FPM_QUERY_BUF_ALIGNMENT_MASK);
1321	if (status)	1321	if (status)
1322	goto exit;	1322	goto error;
1323	info.fpm_query_buf_pa = mem.pa;	1323	info.fpm_query_buf_pa = mem.pa;
1324	info.fpm_query_buf = mem.va;	1324	info.fpm_query_buf = mem.va;
1325	status = i40iw_obj_aligned_mem(iwdev, &mem, I40IW_COMMIT_FPM_BUF_SIZE,	1325	status = i40iw_obj_aligned_mem(iwdev, &mem, I40IW_COMMIT_FPM_BUF_SIZE,
1326	I40IW_FPM_COMMIT_BUF_ALIGNMENT_MASK);	1326	I40IW_FPM_COMMIT_BUF_ALIGNMENT_MASK);
1327	if (status)	1327	if (status)
1328	goto exit;	1328	goto error;
1329	info.fpm_commit_buf_pa = mem.pa;	1329	info.fpm_commit_buf_pa = mem.pa;
1330	info.fpm_commit_buf = mem.va;	1330	info.fpm_commit_buf = mem.va;
1331	info.hmc_fn_id = ldev->fid;	1331	info.hmc_fn_id = ldev->fid;
@@ -1347,11 +1347,9 @@ static enum i40iw_status_code i40iw_initialize_dev(struct i40iw_device *iwdev, · 15 unmodified lines
1347	info.exception_lan_queue = 1;	1347	info.exception_lan_queue = 1;
1348	info.vchnl_send = i40iw_virtchnl_send;	1348	info.vchnl_send = i40iw_virtchnl_send;
1349	status = i40iw_device_init(&iwdev->sc_dev, &info);	1349	status = i40iw_device_init(&iwdev->sc_dev, &info);
1350	exit:	1350
1351	if (status) {	1351	if (status)
1352	kfree(iwdev->hmc_info_mem);	1352	goto error;
1353	iwdev->hmc_info_mem = NULL;
1354	}
1355	memset(&vsi_info, 0, sizeof(vsi_info));	1353	memset(&vsi_info, 0, sizeof(vsi_info));
1356	vsi_info.dev = &iwdev->sc_dev;	1354	vsi_info.dev = &iwdev->sc_dev;
1357	vsi_info.back_vsi = (void *)iwdev;	1355	vsi_info.back_vsi = (void *)iwdev;
@@ -1362,11 +1360,19 @@ exit: · 4 unmodified lines
1362	memset(&stats_info, 0, sizeof(stats_info));	1360	memset(&stats_info, 0, sizeof(stats_info));
1363	stats_info.fcn_id = ldev->fid;	1361	stats_info.fcn_id = ldev->fid;
1364	stats_info.pestat = kzalloc(sizeof(*stats_info.pestat), GFP_KERNEL);	1362	stats_info.pestat = kzalloc(sizeof(*stats_info.pestat), GFP_KERNEL);
		1363	if (!stats_info.pestat) {
		1364	status = I40IW_ERR_NO_MEMORY;
		1365	goto error;
		1366	}
1365	stats_info.stats_initialize = true;	1367	stats_info.stats_initialize = true;
1366	if (stats_info.pestat)	1368	if (stats_info.pestat)
1367	i40iw_vsi_stats_init(&iwdev->vsi, &stats_info);	1369	i40iw_vsi_stats_init(&iwdev->vsi, &stats_info);
1368	}	1370	}
1369	return status;	1371	return status;
		1372	error:
		1373	kfree(iwdev->hmc_info_mem);
		1374	iwdev->hmc_info_mem = NULL;
		1375	return status;
1370	}	1376	}
1371		1377
1372	/**	1378	/**

drivers/infiniband/hw/i40iw/i40iw_osdep.h+0−1

@@ -199,7 +199,6 @@ void i40iw_cqp_spawn_worker(struct i40iw_sc_dev *dev, · 198 unmodified lines
199	struct i40iw_virtchnl_work_info *work_info, u32 iw_vf_idx);	199	struct i40iw_virtchnl_work_info *work_info, u32 iw_vf_idx);
200	void i40iw_remove_head(struct list_head list);	200	void i40iw_remove_head(struct list_head list);
201	void i40iw_qp_suspend_resume(struct i40iw_sc_dev dev, struct i40iw_sc_qp qp, bool suspend);	201	void i40iw_qp_suspend_resume(struct i40iw_sc_dev dev, struct i40iw_sc_qp qp, bool suspend);
202	void i40iw_qp_mss_modify(struct i40iw_sc_dev dev, struct i40iw_sc_qp qp);
203		202
204	void i40iw_term_modify_qp(struct i40iw_sc_qp *qp, u8 next_state, u8 term, u8 term_len);	203	void i40iw_term_modify_qp(struct i40iw_sc_qp *qp, u8 next_state, u8 term, u8 term_len);
205	void i40iw_terminate_done(struct i40iw_sc_qp *qp, int timeout_occurred);	204	void i40iw_terminate_done(struct i40iw_sc_qp *qp, int timeout_occurred);

drivers/infiniband/hw/i40iw/i40iw_type.h+0−2

 struct i40iw_modify_qp_info {
 	u64 rx_win0;
 	u64 rx_win1;
-	u16 new_mss;
 	u8 next_iwarp_state;
 	u8 termlen;
 	bool ord_valid;
 	bool dont_send_term;
 	bool dont_send_fin;
 	bool cached_var_valid;
-	bool mss_change;
 	bool force_loopback;
 };

drivers/infiniband/hw/i40iw/i40iw_utils.c+0−17

@@ -756,23 +756,6 @@ void i40iw_qp_suspend_resume(struct i40iw_sc_dev dev, struct i40iw_sc_qp qp, b · 755 unmodified lines
756	i40iw_pr_err("CQP-OP QP Suspend/Resume fail");	756	i40iw_pr_err("CQP-OP QP Suspend/Resume fail");
757	}	757	}
758		758
759	/**
760	* i40iw_qp_mss_modify - modify mss for qp
761	* @dev: hardware control device structure
762	* @qp: hardware control qp
763	*/
764	void i40iw_qp_mss_modify(struct i40iw_sc_dev dev, struct i40iw_sc_qp qp)
765	{
766	struct i40iw_device iwdev = (struct i40iw_device )dev->back_dev;
767	struct i40iw_qp iwqp = (struct i40iw_qp )qp->back_qp;
768	struct i40iw_modify_qp_info info;
769
770	memset(&info, 0, sizeof(info));
771	info.mss_change = true;
772	info.new_mss = qp->vsi->mss;
773	i40iw_hw_modify_qp(iwdev, iwqp, &info, false);
774	}
775
776	/**	759	/**
777	* i40iw_term_modify_qp - modify qp for term message	760	* i40iw_term_modify_qp - modify qp for term message
778	* @qp: hardware control qp	761	* @qp: hardware control qp

drivers/infiniband/hw/i40iw/i40iw_virtchnl.c+1−4

 	if (!dev->vchnl_up)
 		return I40IW_ERR_NOT_READY;
 	if (vchnl_msg->iw_op_code == I40IW_VCHNL_OP_GET_VER) {
-		if (vchnl_msg->iw_op_ver != I40IW_VCHNL_OP_GET_VER_V0)
+		vchnl_pf_send_get_ver_resp(dev, vf_id, vchnl_msg);
-			vchnl_pf_send_get_ver_resp(dev, vf_id, vchnl_msg);
-		else
-			vchnl_pf_send_get_ver_resp(dev, vf_id, vchnl_msg);
 		return I40IW_SUCCESS;
 	}
 	for (iw_vf_idx = 0; iw_vf_idx < I40IW_MAX_PE_ENABLED_VF_COUNT; iw_vf_idx++) {

drivers/infiniband/hw/mlx4/mad.c+1−0

@@ -1578,6 +1578,7 @@ static void mlx4_ib_multiplex_mad(struct mlx4_ib_demux_pv_ctx *ctx, struct ib_wc · 1577 unmodified lines
1578	if (port < 0)	1578	if (port < 0)
1579	return;	1579	return;
1580	ah.av.ib.port_pd = cpu_to_be32(port << 24 \| (be32_to_cpu(ah.av.ib.port_pd) & 0xffffff));	1580	ah.av.ib.port_pd = cpu_to_be32(port << 24 \| (be32_to_cpu(ah.av.ib.port_pd) & 0xffffff));
		1581	ah.ibah.type = rdma_ah_find_type(&dev->ib_dev, port);
1581		1582
1582	mlx4_ib_query_ah(&ah.ibah, &ah_attr);	1583	mlx4_ib_query_ah(&ah.ibah, &ah_attr);
1583	if (rdma_ah_get_ah_flags(&ah_attr) & IB_AH_GRH)	1584	if (rdma_ah_get_ah_flags(&ah_attr) & IB_AH_GRH)

drivers/infiniband/hw/mlx5/main.c+18−2

 	return ret;
 }
+static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
+{
+	switch (umr_fence_cap) {
+	case MLX5_CAP_UMR_FENCE_NONE:
+		return MLX5_FENCE_MODE_NONE;
+	case MLX5_CAP_UMR_FENCE_SMALL:
+		return MLX5_FENCE_MODE_INITIATOR_SMALL;
+	default:
+		return MLX5_FENCE_MODE_STRONG_ORDERING;
+	}
+}
 static int create_dev_resources(struct mlx5_ib_resources *devr)
 {
 	struct ib_srq_init_attr attr;
 	dev->ib_dev.check_mr_status	= mlx5_ib_check_mr_status;
 	dev->ib_dev.get_port_immutable  = mlx5_port_immutable;
 	dev->ib_dev.get_dev_fw_str      = get_dev_fw_str;
-	dev->ib_dev.alloc_rdma_netdev	= mlx5_ib_alloc_rdma_netdev;
+	if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads)) {
-	dev->ib_dev.free_rdma_netdev	= mlx5_ib_free_rdma_netdev;
+		dev->ib_dev.alloc_rdma_netdev	= mlx5_ib_alloc_rdma_netdev;
+		dev->ib_dev.free_rdma_netdev	= mlx5_ib_free_rdma_netdev;
+	}
 	if (mlx5_core_is_pf(mdev)) {
 		dev->ib_dev.get_vf_config	= mlx5_ib_get_vf_config;
 		dev->ib_dev.set_vf_link_state	= mlx5_ib_set_vf_link_state;
 	mlx5_ib_internal_fill_odp_caps(dev);
+	dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
 	if (MLX5_CAP_GEN(mdev, imaicl)) {
 		dev->ib_dev.alloc_mw		= mlx5_ib_alloc_mw;
 		dev->ib_dev.dealloc_mw		= mlx5_ib_dealloc_mw;

drivers/infiniband/hw/mlx5/mlx5_ib.h+2−1

 	struct mlx5_ib_wq	rq;
 	u8			sq_signal_bits;
-	u8			fm_cache;
+	u8			next_fence;
 	struct mlx5_ib_wq	sq;
 	/* serialize qp state modifications
 	struct mlx5_ib_port	*port;
 	struct mlx5_sq_bfreg     bfreg;
 	struct mlx5_sq_bfreg     fp_bfreg;
+	u8				umr_fence;
 };
 static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq)

drivers/infiniband/hw/mlx5/qp.c+23−36

 	}
 }
-static u8 get_fence(u8 fence, struct ib_send_wr *wr)
-{
-	if (unlikely(wr->opcode == IB_WR_LOCAL_INV &&
-		     wr->send_flags & IB_SEND_FENCE))
-		return MLX5_FENCE_MODE_STRONG_ORDERING;
-	if (unlikely(fence)) {
-		if (wr->send_flags & IB_SEND_FENCE)
-			return MLX5_FENCE_MODE_SMALL_AND_FENCE;
-		else
-			return fence;
-	} else if (unlikely(wr->send_flags & IB_SEND_FENCE)) {
-		return MLX5_FENCE_MODE_FENCE;
-	}
-	return 0;
-}
 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
 		     struct mlx5_wqe_ctrl_seg **ctrl,
 		     struct ib_send_wr *wr, unsigned *idx,
 static void finish_wqe(struct mlx5_ib_qp *qp,
 		       struct mlx5_wqe_ctrl_seg *ctrl,
 		       u8 size, unsigned idx, u64 wr_id,
-		       int nreq, u8 fence, u8 next_fence,
+		       int nreq, u8 fence, u32 mlx5_opcode)
-		       u32 mlx5_opcode)
 {
 	u8 opmod = 0;
 					     mlx5_opcode | ((u32)opmod << 24));
 	ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
 	ctrl->fm_ce_se |= fence;
-	qp->fm_cache = next_fence;
 	if (unlikely(qp->wq_sig))
 		ctrl->signature = wq_sig(ctrl);
 			goto out;
 		}
-		fence = qp->fm_cache;
 		num_sge = wr->num_sge;
 		if (unlikely(num_sge > qp->sq.max_gs)) {
 			mlx5_ib_warn(dev, "\n");
 			goto out;
 		}
+		if (wr->opcode == IB_WR_LOCAL_INV ||
+		    wr->opcode == IB_WR_REG_MR) {
+			fence = dev->umr_fence;
+			next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
+		} else if (wr->send_flags & IB_SEND_FENCE) {
+			if (qp->next_fence)
+				fence = MLX5_FENCE_MODE_SMALL_AND_FENCE;
+			else
+				fence = MLX5_FENCE_MODE_FENCE;
+		} else {
+			fence = qp->next_fence;
+		}
 		switch (ibqp->qp_type) {
 		case IB_QPT_XRC_INI:
 			xrc = seg;
 				goto out;
 			case IB_WR_LOCAL_INV:
-				next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
 				qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
 				ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
 				set_linv_wr(qp, &seg, &size);
 				break;
 			case IB_WR_REG_MR:
-				next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
 				qp->sq.wr_data[idx] = IB_WR_REG_MR;
 				ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
 				err = set_reg_wr(qp, reg_wr(wr), &seg, &size);
 					goto out;
 				}
-				finish_wqe(qp, ctrl, size, idx, wr->wr_id,
+				finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
-					   nreq, get_fence(fence, wr),
+					   fence, MLX5_OPCODE_UMR);
-					   next_fence, MLX5_OPCODE_UMR);
 				/*
 				 * SET_PSV WQEs are not signaled and solicited
 				 * on error
 					goto out;
 				}
-				finish_wqe(qp, ctrl, size, idx, wr->wr_id,
+				finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
-					   nreq, get_fence(fence, wr),
+					   fence, MLX5_OPCODE_SET_PSV);
-					   next_fence, MLX5_OPCODE_SET_PSV);
 				err = begin_wqe(qp, &seg, &ctrl, wr,
 						&idx, &size, nreq);
 				if (err) {
 					goto out;
 				}
-				next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
 				err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
 						 mr->sig->psv_wire.psv_idx, &seg,
 						 &size);
 					goto out;
 				}
-				finish_wqe(qp, ctrl, size, idx, wr->wr_id,
+				finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
-					   nreq, get_fence(fence, wr),
+					   fence, MLX5_OPCODE_SET_PSV);
-					   next_fence, MLX5_OPCODE_SET_PSV);
+				qp->next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
 				num_sge = 0;
 				goto skip_psv;
 			}
 		}
-		finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
+		qp->next_fence = next_fence;
-			   get_fence(fence, wr), next_fence,
+		finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, fence,
 			   mlx5_ib_opcode[wr->opcode]);
 skip_psv:
 		if (0)

drivers/infiniband/hw/nes/nes_cm.c+1−2

@@ -610,7 +610,6 @@ static void build_mpa_v2(struct nes_cm_node *cm_node, · 609 unmodified lines
610	ctrl_ord = cm_node->ord_size & IETF_NO_IRD_ORD;	610	ctrl_ord = cm_node->ord_size & IETF_NO_IRD_ORD;
611	}	611	}
612	ctrl_ird \|= IETF_PEER_TO_PEER;	612	ctrl_ird \|= IETF_PEER_TO_PEER;
613	ctrl_ird \|= IETF_FLPDU_ZERO_LEN;
614		613
615	switch (mpa_key) {	614	switch (mpa_key) {
616	case MPA_KEY_REQUEST:	615	case MPA_KEY_REQUEST:
@@ -1826,7 +1825,7 @@ static void handle_rcv_mpa(struct nes_cm_node cm_node, struct sk_buff skb) · 1209 unmodified lines
1826	type = NES_CM_EVENT_CONNECTED;	1825	type = NES_CM_EVENT_CONNECTED;
1827	cm_node->state = NES_CM_STATE_TSA;	1826	cm_node->state = NES_CM_STATE_TSA;
1828	}	1827	}
1829		1828	send_ack(cm_node, NULL);
1830	break;	1829	break;
1831	default:	1830	default:
1832	WARN_ON(1);	1831	WARN_ON(1);

drivers/infiniband/hw/qedr/qedr.h+4−1

@@ -58,7 +58,10 @@ · 57 unmodified lines
58	#define QEDR_MSG_QP " QP"	58	#define QEDR_MSG_QP " QP"
59	#define QEDR_MSG_GSI " GSI"	59	#define QEDR_MSG_GSI " GSI"
60		60
61	#define QEDR_CQ_MAGIC_NUMBER (0x11223344)	61	#define QEDR_CQ_MAGIC_NUMBER (0x11223344)
		62
		63	#define FW_PAGE_SIZE (RDMA_RING_PAGE_SIZE)
		64	#define FW_PAGE_SHIFT (12)
62		65
63	struct qedr_dev;	66	struct qedr_dev;
64		67

drivers/infiniband/hw/qedr/qedr_cm.c+6−4

 		return rc;
 	}
-	vlan_id = rdma_vlan_dev_vlan_id(sgid_attr.ndev);
+	if (sgid_attr.ndev) {
-	if (vlan_id < VLAN_CFI_MASK)
+		vlan_id = rdma_vlan_dev_vlan_id(sgid_attr.ndev);
-		has_vlan = true;
+		if (vlan_id < VLAN_CFI_MASK)
-	if (sgid_attr.ndev)
+			has_vlan = true;
 		dev_put(sgid_attr.ndev);
+	}
 	if (!memcmp(&sgid, &zgid, sizeof(sgid))) {
 		DP_ERR(dev, "gsi post send: GID not found GID index %d\n",

drivers/infiniband/hw/qedr/verbs.c+41−27

@@ -653,14 +653,15 @@ static int qedr_prepare_pbl_tbl(struct qedr_dev *dev, · 652 unmodified lines
653		653
654	static void qedr_populate_pbls(struct qedr_dev dev, struct ib_umem umem,	654	static void qedr_populate_pbls(struct qedr_dev dev, struct ib_umem umem,
655	struct qedr_pbl *pbl,	655	struct qedr_pbl *pbl,
656	struct qedr_pbl_info *pbl_info)	656	struct qedr_pbl_info *pbl_info, u32 pg_shift)
657	{	657	{
658	int shift, pg_cnt, pages, pbe_cnt, total_num_pbes = 0;	658	int shift, pg_cnt, pages, pbe_cnt, total_num_pbes = 0;
		659	u32 fw_pg_cnt, fw_pg_per_umem_pg;
659	struct qedr_pbl *pbl_tbl;	660	struct qedr_pbl *pbl_tbl;
660	struct scatterlist *sg;	661	struct scatterlist *sg;
661	struct regpair *pbe;	662	struct regpair *pbe;
		663	u64 pg_addr;
662	int entry;	664	int entry;
663	u32 addr;
664		665
665	if (!pbl_info->num_pbes)	666	if (!pbl_info->num_pbes)
666	return;	667	return;
@@ -683,29 +684,35 @@ static void qedr_populate_pbls(struct qedr_dev dev, struct ib_umem umem, · 16 unmodified lines
683		684
684	shift = umem->page_shift;	685	shift = umem->page_shift;
685		686
		687	fw_pg_per_umem_pg = BIT(umem->page_shift - pg_shift);
		688
686	for_each_sg(umem->sg_head.sgl, sg, umem->nmap, entry) {	689	for_each_sg(umem->sg_head.sgl, sg, umem->nmap, entry) {
687	pages = sg_dma_len(sg) >> shift;	690	pages = sg_dma_len(sg) >> shift;
		691	pg_addr = sg_dma_address(sg);
688	for (pg_cnt = 0; pg_cnt < pages; pg_cnt++) {	692	for (pg_cnt = 0; pg_cnt < pages; pg_cnt++) {
689	/* store the page address in pbe */	693	for (fw_pg_cnt = 0; fw_pg_cnt < fw_pg_per_umem_pg;) {
690	pbe->lo = cpu_to_le32(sg_dma_address(sg) +	694	pbe->lo = cpu_to_le32(pg_addr);
691	(pg_cnt << shift));	695	pbe->hi = cpu_to_le32(upper_32_bits(pg_addr));
692	addr = upper_32_bits(sg_dma_address(sg) +	696
693	(pg_cnt << shift));	697	pg_addr += BIT(pg_shift);
694	pbe->hi = cpu_to_le32(addr);	698	pbe_cnt++;
695	pbe_cnt++;	699	total_num_pbes++;
696	total_num_pbes++;	700	pbe++;
697	pbe++;	701
698		702	if (total_num_pbes == pbl_info->num_pbes)
699	if (total_num_pbes == pbl_info->num_pbes)	703	return;
700	return;	704
701		705	/* If the given pbl is full storing the pbes,
702	/* If the given pbl is full storing the pbes,	706	* move to next pbl.
703	* move to next pbl.	707	*/
704	*/	708	if (pbe_cnt ==
705	if (pbe_cnt == (pbl_info->pbl_size / sizeof(u64))) {	709	(pbl_info->pbl_size / sizeof(u64))) {
706	pbl_tbl++;	710	pbl_tbl++;
707	pbe = (struct regpair *)pbl_tbl->va;	711	pbe = (struct regpair *)pbl_tbl->va;
708	pbe_cnt = 0;	712	pbe_cnt = 0;
		713	}
		714
		715	fw_pg_cnt++;
709	}	716	}
710	}	717	}
711	}	718	}
@@ -754,7 +761,7 @@ static inline int qedr_init_user_queue(struct ib_ucontext *ib_ctx, · 42 unmodified lines
754	u64 buf_addr, size_t buf_len,	761	u64 buf_addr, size_t buf_len,
755	int access, int dmasync)	762	int access, int dmasync)
756	{	763	{
757	int page_cnt;	764	u32 fw_pages;
758	int rc;	765	int rc;
759		766
760	q->buf_addr = buf_addr;	767	q->buf_addr = buf_addr;
@@ -766,8 +773,10 @@ static inline int qedr_init_user_queue(struct ib_ucontext *ib_ctx, · 5 unmodified lines
766	return PTR_ERR(q->umem);	773	return PTR_ERR(q->umem);
767	}	774	}
768		775
769	page_cnt = ib_umem_page_count(q->umem);	776	fw_pages = ib_umem_page_count(q->umem) <<
770	rc = qedr_prepare_pbl_tbl(dev, &q->pbl_info, page_cnt, 0);	777	(q->umem->page_shift - FW_PAGE_SHIFT);
		778
		779	rc = qedr_prepare_pbl_tbl(dev, &q->pbl_info, fw_pages, 0);
771	if (rc)	780	if (rc)
772	goto err0;	781	goto err0;
773		782
@@ -777,7 +786,8 @@ static inline int qedr_init_user_queue(struct ib_ucontext *ib_ctx, · 3 unmodified lines
777	goto err0;	786	goto err0;
778	}	787	}
779		788
780	qedr_populate_pbls(dev, q->umem, q->pbl_tbl, &q->pbl_info);	789	qedr_populate_pbls(dev, q->umem, q->pbl_tbl, &q->pbl_info,
		790	FW_PAGE_SHIFT);
781		791
782	return 0;	792	return 0;
783		793
@@ -2226,7 +2236,7 @@ struct ib_mr qedr_reg_user_mr(struct ib_pd ibpd, u64 start, u64 len, · 1442 unmodified lines
2226	goto err1;	2236	goto err1;
2227		2237
2228	qedr_populate_pbls(dev, mr->umem, mr->info.pbl_table,	2238	qedr_populate_pbls(dev, mr->umem, mr->info.pbl_table,
2229	&mr->info.pbl_info);	2239	&mr->info.pbl_info, mr->umem->page_shift);
2230		2240
2231	rc = dev->ops->rdma_alloc_tid(dev->rdma_ctx, &mr->hw_mr.itid);	2241	rc = dev->ops->rdma_alloc_tid(dev->rdma_ctx, &mr->hw_mr.itid);
2232	if (rc) {	2242	if (rc) {
@@ -3209,6 +3219,10 @@ static int process_req(struct qedr_dev dev, struct qedr_qp qp, · 976 unmodified lines
3209	case IB_WC_REG_MR:	3219	case IB_WC_REG_MR:
3210	qp->wqe_wr_id[qp->sq.cons].mr->info.completed++;	3220	qp->wqe_wr_id[qp->sq.cons].mr->info.completed++;
3211	break;	3221	break;
		3222	case IB_WC_RDMA_READ:
		3223	case IB_WC_SEND:
		3224	wc->byte_len = qp->wqe_wr_id[qp->sq.cons].bytes_len;
		3225	break;
3212	default:	3226	default:
3213	break;	3227	break;
3214	}	3228	}

drivers/infiniband/hw/qib/qib_rc.c+3−1

 		ret = qib_get_rwqe(qp, 1);
 		if (ret < 0)
 			goto nack_op_err;
-		if (!ret)
+		if (!ret) {
+			rvt_put_ss(&qp->r_sge);
 			goto rnr_nak;
+		}
 		wc.ex.imm_data = ohdr->u.rc.imm_data;
 		hdrsize += 4;
 		wc.wc_flags = IB_WC_WITH_IMM;

drivers/infiniband/sw/rxe/rxe.h+4−1

 static inline u32 rxe_crc32(struct rxe_dev *rxe,
 			    u32 crc, void *next, size_t len)
 {
+	u32 retval;
 	int err;
 	SHASH_DESC_ON_STACK(shash, rxe->tfm);
 		return crc32_le(crc, next, len);
 	}
-	return *(u32 *)shash_desc_ctx(shash);
+	retval = *(u32 *)shash_desc_ctx(shash);
+	barrier_data(shash_desc_ctx(shash));
+	return retval;
 }
 int rxe_set_mtu(struct rxe_dev *rxe, unsigned int dev_mtu);

drivers/infiniband/sw/rxe/rxe_verbs.c+2−7

 		sge = ibwr->sg_list;
 		for (i = 0; i < num_sge; i++, sge++) {
-			if (qp->is_user && copy_from_user(p, (__user void *)
+			memcpy(p, (void *)(uintptr_t)sge->addr,
-					    (uintptr_t)sge->addr, sge->length))
+					sge->length);
-				return -EFAULT;
-			else if (!qp->is_user)
-				memcpy(p, (void *)(uintptr_t)sge->addr,
-				       sge->length);
 			p += sge->length;
 		}

drivers/infiniband/ulp/ipoib/ipoib_ethtool.c+1−1

@@ -178,7 +178,7 @@ static inline int ib_speed_enum_to_int(int speed) · 177 unmodified lines
178	static int ipoib_get_link_ksettings(struct net_device *netdev,	178	static int ipoib_get_link_ksettings(struct net_device *netdev,
179	struct ethtool_link_ksettings *cmd)	179	struct ethtool_link_ksettings *cmd)
180	{	180	{
181	struct ipoib_dev_priv *priv = netdev_priv(netdev);	181	struct ipoib_dev_priv *priv = ipoib_priv(netdev);
182	struct ib_port_attr attr;	182	struct ib_port_attr attr;
183	int ret, speed, width;	183	int ret, speed, width;
184		184

drivers/infiniband/ulp/ipoib/ipoib_ib.c+0−1

@@ -863,7 +863,6 @@ dev_stop: · 862 unmodified lines
863	set_bit(IPOIB_STOP_REAPER, &priv->flags);	863	set_bit(IPOIB_STOP_REAPER, &priv->flags);
864	cancel_delayed_work(&priv->ah_reap_task);	864	cancel_delayed_work(&priv->ah_reap_task);
865	set_bit(IPOIB_FLAG_INITIALIZED, &priv->flags);	865	set_bit(IPOIB_FLAG_INITIALIZED, &priv->flags);
866	napi_enable(&priv->napi);
867	ipoib_ib_dev_stop(dev);	866	ipoib_ib_dev_stop(dev);
868	return -1;	867	return -1;
869	}	868	}

drivers/infiniband/ulp/ipoib/ipoib_main.c+14−3

 	wait_for_completion(&priv->ntbl.deleted);
 }
-void ipoib_dev_uninit_default(struct net_device *dev)
+static void ipoib_dev_uninit_default(struct net_device *dev)
 {
 	struct ipoib_dev_priv *priv = ipoib_priv(dev);
 	ipoib_transport_dev_cleanup(dev);
+	netif_napi_del(&priv->napi);
 	ipoib_cm_dev_cleanup(dev);
 	kfree(priv->rx_ring);
 	kfree(priv->rx_ring);
 out:
+	netif_napi_del(&priv->napi);
 	return -ENOMEM;
 }
 device_init_failed:
 	free_netdev(priv->dev);
+	kfree(priv);
 alloc_mem_failed:
 	return ERR_PTR(result);
 static void ipoib_remove_one(struct ib_device *device, void *client_data)
 {
-	struct ipoib_dev_priv *priv, *tmp;
+	struct ipoib_dev_priv *priv, *tmp, *cpriv, *tcpriv;
 	struct list_head *dev_list = client_data;
 	if (!dev_list)
 		flush_workqueue(priv->wq);
 		unregister_netdev(priv->dev);
-		free_netdev(priv->dev);
+		if (device->free_rdma_netdev)
+			device->free_rdma_netdev(priv->dev);
+		else
+			free_netdev(priv->dev);
+		list_for_each_entry_safe(cpriv, tcpriv, &priv->child_intfs, list)
+			kfree(cpriv);
 		kfree(priv);
 	}

drivers/infiniband/ulp/ipoib/ipoib_vlan.c+7−4

 	snprintf(intf_name, sizeof intf_name, "%s.%04x",
 		 ppriv->dev->name, pkey);
+	if (!rtnl_trylock())
+		return restart_syscall();
 	priv = ipoib_intf_alloc(ppriv->ca, ppriv->port, intf_name);
 	if (!priv)
 		return -ENOMEM;
-	if (!rtnl_trylock())
-		return restart_syscall();
 	down_write(&ppriv->vlan_rwsem);
 	/*
 	rtnl_unlock();
-	if (result)
+	if (result) {
 		free_netdev(priv->dev);
+		kfree(priv);
+	}
 	return result;
 }
 	if (dev) {
 		free_netdev(dev);
+		kfree(priv);
 		return 0;
 	}

drivers/infiniband/ulp/srp/ib_srp.c+2−2

@@ -320,7 +320,7 @@ static int srp_new_cm_id(struct srp_rdma_ch *ch) · 319 unmodified lines
320	ch->path.sgid = target->sgid;	320	ch->path.sgid = target->sgid;
321	ch->path.dgid = target->orig_dgid;	321	ch->path.dgid = target->orig_dgid;
322	ch->path.pkey = target->pkey;	322	ch->path.pkey = target->pkey;
323	sa_path_set_service_id(&ch->path, target->service_id);	323	ch->path.service_id = target->service_id;
324		324
325	return 0;	325	return 0;
326	}	326	}
@@ -575,7 +575,7 @@ static int srp_create_ch_ib(struct srp_rdma_ch *ch) · 248 unmodified lines
575	return 0;	575	return 0;
576		576
577	err_qp:	577	err_qp:
578	srp_destroy_qp(ch, qp);	578	ib_destroy_qp(qp);
579		579
580	err_send_cq:	580	err_send_cq:
581	ib_free_cq(send_cq);	581	ib_free_cq(send_cq);

drivers/input/keyboard/tm2-touchkey.c+1−1

@@ -213,7 +213,7 @@ static int tm2_touchkey_probe(struct i2c_client *client, · 212 unmodified lines
213	/* led device */	213	/* led device */
214	touchkey->led_dev.name = TM2_TOUCHKEY_DEV_NAME;	214	touchkey->led_dev.name = TM2_TOUCHKEY_DEV_NAME;
215	touchkey->led_dev.brightness = LED_FULL;	215	touchkey->led_dev.brightness = LED_FULL;
216	touchkey->led_dev.max_brightness = LED_FULL;	216	touchkey->led_dev.max_brightness = LED_ON;
217	touchkey->led_dev.brightness_set = tm2_touchkey_led_brightness_set;	217	touchkey->led_dev.brightness_set = tm2_touchkey_led_brightness_set;
218		218
219	error = devm_led_classdev_register(&client->dev, &touchkey->led_dev);	219	error = devm_led_classdev_register(&client->dev, &touchkey->led_dev);

drivers/input/misc/axp20x-pek.c+37−7

@@ -256,6 +256,42 @@ static int axp20x_pek_probe_input_device(struct axp20x_pek *axp20x_pek, · 255 unmodified lines
256	return 0;	256	return 0;
257	}	257	}
258		258
		259	#ifdef CONFIG_ACPI
		260	static bool axp20x_pek_should_register_input(struct axp20x_pek *axp20x_pek,
		261	struct platform_device *pdev)
		262	{
		263	unsigned long long hrv = 0;
		264	acpi_status status;
		265
		266	if (IS_ENABLED(CONFIG_INPUT_SOC_BUTTON_ARRAY) &&
		267	axp20x_pek->axp20x->variant == AXP288_ID) {
		268	status = acpi_evaluate_integer(ACPI_HANDLE(pdev->dev.parent),
		269	"_HRV", NULL, &hrv);
		270	if (ACPI_FAILURE(status))
		271	dev_err(&pdev->dev, "Failed to get PMIC hardware revision\n");
		272
		273	/*
		274	* On Cherry Trail platforms (hrv == 3), do not register the
		275	* input device if there is an "INTCFD9" or "ACPI0011" gpio
		276	* button ACPI device, as that handles the power button too,
		277	* and otherwise we end up reporting all presses twice.
		278	*/
		279	if (hrv == 3 && (acpi_dev_present("INTCFD9", NULL, -1) \|\|
		280	acpi_dev_present("ACPI0011", NULL, -1)))
		281	return false;
		282
		283	}
		284
		285	return true;
		286	}
		287	#else
		288	static bool axp20x_pek_should_register_input(struct axp20x_pek *axp20x_pek,
		289	struct platform_device *pdev)
		290	{
		291	return true;
		292	}
		293	#endif
		294
259	static int axp20x_pek_probe(struct platform_device *pdev)	295	static int axp20x_pek_probe(struct platform_device *pdev)
260	{	296	{
261	struct axp20x_pek *axp20x_pek;	297	struct axp20x_pek *axp20x_pek;
@@ -268,13 +304,7 @@ static int axp20x_pek_probe(struct platform_device *pdev) · 6 unmodified lines
268		304
269	axp20x_pek->axp20x = dev_get_drvdata(pdev->dev.parent);	305	axp20x_pek->axp20x = dev_get_drvdata(pdev->dev.parent);
270		306
271	/*	307	if (axp20x_pek_should_register_input(axp20x_pek, pdev)) {
272	* Do not register the input device if there is an "INTCFD9"
273	* gpio button ACPI device, that handles the power button too,
274	* and otherwise we end up reporting all presses twice.
275	*/
276	if (!acpi_dev_found("INTCFD9") \|\|
277	!IS_ENABLED(CONFIG_INPUT_SOC_BUTTON_ARRAY)) {
278	error = axp20x_pek_probe_input_device(axp20x_pek, pdev);	308	error = axp20x_pek_probe_input_device(axp20x_pek, pdev);
279	if (error)	309	if (error)
280	return error;	310	return error;

drivers/input/mouse/elantech.c+16−0

  * Asus UX32VD             0x361f02        00, 15, 0e      clickpad
  * Avatar AVIU-145A2       0x361f00        ?               clickpad
  * Fujitsu LIFEBOOK E544   0x470f00        d0, 12, 09      2 hw buttons
+ * Fujitsu LIFEBOOK E546   0x470f00        50, 12, 09      2 hw buttons
  * Fujitsu LIFEBOOK E547   0x470f00        50, 12, 09      2 hw buttons
  * Fujitsu LIFEBOOK E554   0x570f01        40, 14, 0c      2 hw buttons
+ * Fujitsu LIFEBOOK E557   0x570f01        40, 14, 0c      2 hw buttons
  * Fujitsu T725            0x470f01        05, 12, 09      2 hw buttons
  * Fujitsu H730            0x570f00        c0, 14, 0c      3 hw buttons (**)
  * Gigabyte U2442          0x450f01        58, 17, 0c      2 hw buttons
 			DMI_MATCH(DMI_PRODUCT_NAME, "LIFEBOOK E544"),
 		},
 	},
+	{
+		/* Fujitsu LIFEBOOK E546  does not work with crc_enabled == 0 */
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"),
+			DMI_MATCH(DMI_PRODUCT_NAME, "LIFEBOOK E546"),
+		},
+	},
 	{
 		/* Fujitsu LIFEBOOK E547 does not work with crc_enabled == 0 */
 		.matches = {
 			DMI_MATCH(DMI_PRODUCT_NAME, "LIFEBOOK E556"),
 		},
 	},
+	{
+		/* Fujitsu LIFEBOOK E557 does not work with crc_enabled == 0 */
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"),
+			DMI_MATCH(DMI_PRODUCT_NAME, "LIFEBOOK E557"),
+		},
+	},
 	{
 		/* Fujitsu LIFEBOOK U745 does not work with crc_enabled == 0 */
 		.matches = {

drivers/input/mouse/synaptics.c+28−9

 	NULL
 };
+static const char * const forcepad_pnp_ids[] = {
+	"SYN300D",
+	"SYN3014",
+	NULL
+};
 /*
  * Send a command to the synpatics touchpad by special commands
  */
 {
 	int error;
+	memset(info, 0, sizeof(*info));
 	error = synaptics_identify(psmouse, info);
 	if (error)
 		return error;
 	{ }
 };
-/* This list has been kindly provided by Synaptics. */
-static const char * const forcepad_pnp_ids[] = {
-	"SYN300D",
-	"SYN3014",
-	NULL
-};
 /*****************************************************************************
  *	Synaptics communications functions
  ****************************************************************************/
 	SYNAPTICS_INTERTOUCH_ON,
 };
-static int synaptics_intertouch = SYNAPTICS_INTERTOUCH_NOT_SET;
+static int synaptics_intertouch = IS_ENABLED(CONFIG_RMI4_SMB) ?
+		SYNAPTICS_INTERTOUCH_NOT_SET : SYNAPTICS_INTERTOUCH_OFF;
 module_param_named(synaptics_intertouch, synaptics_intertouch, int, 0644);
 MODULE_PARM_DESC(synaptics_intertouch, "Use a secondary bus for the Synaptics device.");
 	if (synaptics_intertouch == SYNAPTICS_INTERTOUCH_NOT_SET) {
 		if (!psmouse_matches_pnp_id(psmouse, topbuttonpad_pnp_ids) &&
-		    !psmouse_matches_pnp_id(psmouse, smbus_pnp_ids))
+		    !psmouse_matches_pnp_id(psmouse, smbus_pnp_ids)) {
+			if (!psmouse_matches_pnp_id(psmouse, forcepad_pnp_ids))
+				psmouse_info(psmouse,
+					     "Your touchpad (%s) says it can support a different bus. "
+					     "If i2c-hid and hid-rmi are not used, you might want to try setting psmouse.synaptics_intertouch to 1 and report this to linux-input@vger.kernel.org.\n",
+					     psmouse->ps2dev.serio->firmware_id);
 			return -ENXIO;
+		}
 	}
 	psmouse_info(psmouse, "Trying to set up SMBus access\n");
 	}
 	if (SYN_CAP_INTERTOUCH(info.ext_cap_0c)) {
+		if ((!IS_ENABLED(CONFIG_RMI4_SMB) ||
+		     !IS_ENABLED(CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS)) &&
+		    /* Forcepads need F21, which is not ready */
+		    !psmouse_matches_pnp_id(psmouse, forcepad_pnp_ids)) {
+			psmouse_warn(psmouse,
+				     "The touchpad can support a better bus than the too old PS/2 protocol. "
+				     "Make sure MOUSE_PS2_SYNAPTICS_SMBUS and RMI4_SMB are enabled to get a better touchpad experience.\n");
+		}
 		error = synaptics_setup_intertouch(psmouse, &info, true);
 		if (!error)
 			return PSMOUSE_SYNAPTICS_SMBUS;

drivers/input/rmi4/rmi_f03.c+1−1

@@ -146,7 +146,7 @@ static int rmi_f03_register_pt(struct f03_data *f03) · 145 unmodified lines
146	if (!serio)	146	if (!serio)
147	return -ENOMEM;	147	return -ENOMEM;
148		148
149	serio->id.type = SERIO_8042;	149	serio->id.type = SERIO_PS_PSTHRU;
150	serio->write = rmi_f03_pt_write;	150	serio->write = rmi_f03_pt_write;
151	serio->port_data = f03;	151	serio->port_data = f03;
152		152

drivers/input/touchscreen/silead.c+3−0

 {
 	struct i2c_client *client = to_i2c_client(dev);
+	disable_irq(client->irq);
 	silead_ts_set_power(client, SILEAD_POWER_OFF);
 	return 0;
 }
 		return -ENODEV;
 	}
+	enable_irq(client->irq);
 	return 0;
 }

drivers/iommu/of_iommu.c+7−0

 	ops = iommu_ops_from_fwnode(fwnode);
 	if ((ops && !ops->of_xlate) ||
+	    !of_device_is_available(iommu_spec->np) ||
 	    (!ops && !of_iommu_driver_present(iommu_spec->np)))
 		return NULL;
 			ops = ERR_PTR(err);
 	}
+	/* Ignore all other errors apart from EPROBE_DEFER */
+	if (IS_ERR(ops) && (PTR_ERR(ops) != -EPROBE_DEFER)) {
+		dev_dbg(dev, "Adding to IOMMU failed: %ld\n", PTR_ERR(ops));
+		ops = NULL;
+	}
 	return ops;
 }

drivers/irqchip/irq-xtensa-mx.c+1−1

@@ -142,7 +142,7 @@ static struct irq_chip xtensa_mx_irq_chip = { · 141 unmodified lines
142	int __init xtensa_mx_init_legacy(struct device_node *interrupt_parent)	142	int __init xtensa_mx_init_legacy(struct device_node *interrupt_parent)
143	{	143	{
144	struct irq_domain *root_domain =	144	struct irq_domain *root_domain =
145	irq_domain_add_legacy(NULL, NR_IRQS, 0, 0,	145	irq_domain_add_legacy(NULL, NR_IRQS - 1, 1, 0,
146	&xtensa_mx_irq_domain_ops,	146	&xtensa_mx_irq_domain_ops,
147	&xtensa_mx_irq_chip);	147	&xtensa_mx_irq_chip);
148	irq_set_default_host(root_domain);	148	irq_set_default_host(root_domain);

drivers/irqchip/irq-xtensa-pic.c+1−1

@@ -89,7 +89,7 @@ static struct irq_chip xtensa_irq_chip = { · 88 unmodified lines
89	int __init xtensa_pic_init_legacy(struct device_node *interrupt_parent)	89	int __init xtensa_pic_init_legacy(struct device_node *interrupt_parent)
90	{	90	{
91	struct irq_domain *root_domain =	91	struct irq_domain *root_domain =
92	irq_domain_add_legacy(NULL, NR_IRQS, 0, 0,	92	irq_domain_add_legacy(NULL, NR_IRQS - 1, 1, 0,
93	&xtensa_irq_domain_ops, &xtensa_irq_chip);	93	&xtensa_irq_domain_ops, &xtensa_irq_chip);
94	irq_set_default_host(root_domain);	94	irq_set_default_host(root_domain);
95	return 0;	95	return 0;

drivers/isdn/i4l/isdn_ppp.c+1−1

@@ -2364,7 +2364,7 @@ static struct ippp_ccp_reset_state *isdn_ppp_ccp_reset_alloc_state(struct ippp_s · 2363 unmodified lines
2364	id);	2364	id);
2365	return NULL;	2365	return NULL;
2366	} else {	2366	} else {
2367	rs = kzalloc(sizeof(struct ippp_ccp_reset_state), GFP_KERNEL);	2367	rs = kzalloc(sizeof(struct ippp_ccp_reset_state), GFP_ATOMIC);
2368	if (!rs)	2368	if (!rs)
2369	return NULL;	2369	return NULL;
2370	rs->state = CCPResetIdle;	2370	rs->state = CCPResetIdle;

drivers/isdn/mISDN/stack.c+1−1

@@ -75,7 +75,7 @@ send_socklist(struct mISDN_sock_list sl, struct sk_buff skb) · 74 unmodified lines
75	if (sk->sk_state != MISDN_BOUND)	75	if (sk->sk_state != MISDN_BOUND)
76	continue;	76	continue;
77	if (!cskb)	77	if (!cskb)
78	cskb = skb_copy(skb, GFP_KERNEL);	78	cskb = skb_copy(skb, GFP_ATOMIC);
79	if (!cskb) {	79	if (!cskb) {
80	printk(KERN_WARNING "%s no skb\n", __func__);	80	printk(KERN_WARNING "%s no skb\n", __func__);
81	break;	81	break;

drivers/leds/leds-bcm6328.c+2−2

@@ -242,7 +242,7 @@ static int bcm6328_hwled(struct device dev, struct device_node nc, u32 reg, · 241 unmodified lines
242		242
243	spin_lock_irqsave(lock, flags);	243	spin_lock_irqsave(lock, flags);
244	val = bcm6328_led_read(addr);	244	val = bcm6328_led_read(addr);
245	val \|= (BIT(reg) << (((sel % 4) * 4) + 16));	245	val \|= (BIT(reg % 4) << (((sel % 4) * 4) + 16));
246	bcm6328_led_write(addr, val);	246	bcm6328_led_write(addr, val);
247	spin_unlock_irqrestore(lock, flags);	247	spin_unlock_irqrestore(lock, flags);
248	}	248	}
@@ -269,7 +269,7 @@ static int bcm6328_hwled(struct device dev, struct device_node nc, u32 reg, · 20 unmodified lines
269		269
270	spin_lock_irqsave(lock, flags);	270	spin_lock_irqsave(lock, flags);
271	val = bcm6328_led_read(addr);	271	val = bcm6328_led_read(addr);
272	val \|= (BIT(reg) << ((sel % 4) * 4));	272	val \|= (BIT(reg % 4) << ((sel % 4) * 4));
273	bcm6328_led_write(addr, val);	273	bcm6328_led_write(addr, val);
274	spin_unlock_irqrestore(lock, flags);	274	spin_unlock_irqrestore(lock, flags);
275	}	275	}

drivers/leds/trigger/ledtrig-heartbeat.c+0−31

@@ -20,7 +20,6 @@ · 19 unmodified lines
20	#include <linux/sched/loadavg.h>	20	#include <linux/sched/loadavg.h>
21	#include <linux/leds.h>	21	#include <linux/leds.h>
22	#include <linux/reboot.h>	22	#include <linux/reboot.h>
23	#include <linux/suspend.h>
24	#include "../leds.h"	23	#include "../leds.h"
25		24
26	static int panic_heartbeats;	25	static int panic_heartbeats;
@@ -163,30 +162,6 @@ static struct led_trigger heartbeat_led_trigger = { · 136 unmodified lines
163	.deactivate = heartbeat_trig_deactivate,	162	.deactivate = heartbeat_trig_deactivate,
164	};	163	};
165		164
166	static int heartbeat_pm_notifier(struct notifier_block *nb,
167	unsigned long pm_event, void *unused)
168	{
169	int rc;
170
171	switch (pm_event) {
172	case PM_SUSPEND_PREPARE:
173	case PM_HIBERNATION_PREPARE:
174	case PM_RESTORE_PREPARE:
175	led_trigger_unregister(&heartbeat_led_trigger);
176	break;
177	case PM_POST_SUSPEND:
178	case PM_POST_HIBERNATION:
179	case PM_POST_RESTORE:
180	rc = led_trigger_register(&heartbeat_led_trigger);
181	if (rc)
182	pr_err("could not re-register heartbeat trigger\n");
183	break;
184	default:
185	break;
186	}
187	return NOTIFY_DONE;
188	}
189
190	static int heartbeat_reboot_notifier(struct notifier_block *nb,	165	static int heartbeat_reboot_notifier(struct notifier_block *nb,
191	unsigned long code, void *unused)	166	unsigned long code, void *unused)
192	{	167	{
@@ -201,10 +176,6 @@ static int heartbeat_panic_notifier(struct notifier_block *nb, · 8 unmodified lines
201	return NOTIFY_DONE;	176	return NOTIFY_DONE;
202	}	177	}
203		178
204	static struct notifier_block heartbeat_pm_nb = {
205	.notifier_call = heartbeat_pm_notifier,
206	};
207
208	static struct notifier_block heartbeat_reboot_nb = {	179	static struct notifier_block heartbeat_reboot_nb = {
209	.notifier_call = heartbeat_reboot_notifier,	180	.notifier_call = heartbeat_reboot_notifier,
210	};	181	};
@@ -221,14 +192,12 @@ static int __init heartbeat_trig_init(void) · 10 unmodified lines
221	atomic_notifier_chain_register(&panic_notifier_list,	192	atomic_notifier_chain_register(&panic_notifier_list,
222	&heartbeat_panic_nb);	193	&heartbeat_panic_nb);
223	register_reboot_notifier(&heartbeat_reboot_nb);	194	register_reboot_notifier(&heartbeat_reboot_nb);
224	register_pm_notifier(&heartbeat_pm_nb);
225	}	195	}
226	return rc;	196	return rc;
227	}	197	}
228		198
229	static void __exit heartbeat_trig_exit(void)	199	static void __exit heartbeat_trig_exit(void)
230	{	200	{
231	unregister_pm_notifier(&heartbeat_pm_nb);
232	unregister_reboot_notifier(&heartbeat_reboot_nb);	201	unregister_reboot_notifier(&heartbeat_reboot_nb);
233	atomic_notifier_chain_unregister(&panic_notifier_list,	202	atomic_notifier_chain_unregister(&panic_notifier_list,
234	&heartbeat_panic_nb);	203	&heartbeat_panic_nb);

drivers/md/bitmap.c+4−4

@@ -485,10 +485,10 @@ void bitmap_print_sb(struct bitmap *bitmap) · 484 unmodified lines
485	pr_debug(" magic: %08x\n", le32_to_cpu(sb->magic));	485	pr_debug(" magic: %08x\n", le32_to_cpu(sb->magic));
486	pr_debug(" version: %d\n", le32_to_cpu(sb->version));	486	pr_debug(" version: %d\n", le32_to_cpu(sb->version));
487	pr_debug(" uuid: %08x.%08x.%08x.%08x\n",	487	pr_debug(" uuid: %08x.%08x.%08x.%08x\n",
488	(__u32 )(sb->uuid+0),	488	le32_to_cpu((__u32 )(sb->uuid+0)),
489	(__u32 )(sb->uuid+4),	489	le32_to_cpu((__u32 )(sb->uuid+4)),
490	(__u32 )(sb->uuid+8),	490	le32_to_cpu((__u32 )(sb->uuid+8)),
491	(__u32 )(sb->uuid+12));	491	le32_to_cpu((__u32 )(sb->uuid+12)));
492	pr_debug(" events: %llu\n",	492	pr_debug(" events: %llu\n",
493	(unsigned long long) le64_to_cpu(sb->events));	493	(unsigned long long) le64_to_cpu(sb->events));
494	pr_debug("events cleared: %llu\n",	494	pr_debug("events cleared: %llu\n",

drivers/md/dm-bufio.c+1−1

@@ -1334,7 +1334,7 @@ int dm_bufio_issue_flush(struct dm_bufio_client *c) · 1333 unmodified lines
1334	{	1334	{
1335	struct dm_io_request io_req = {	1335	struct dm_io_request io_req = {
1336	.bi_op = REQ_OP_WRITE,	1336	.bi_op = REQ_OP_WRITE,
1337	.bi_op_flags = REQ_PREFLUSH,	1337	.bi_op_flags = REQ_PREFLUSH \| REQ_SYNC,
1338	.mem.type = DM_IO_KMEM,	1338	.mem.type = DM_IO_KMEM,
1339	.mem.ptr.addr = NULL,	1339	.mem.ptr.addr = NULL,
1340	.client = c->dm_io,	1340	.client = c->dm_io,

drivers/md/dm-integrity.c+8−22

 			for (i = 0; i < commit_sections; i++)
 				rw_section_mac(ic, commit_start + i, true);
 		}
-		rw_journal(ic, REQ_OP_WRITE, REQ_FUA, commit_start, commit_sections, &io_comp);
+		rw_journal(ic, REQ_OP_WRITE, REQ_FUA | REQ_SYNC, commit_start,
+			   commit_sections, &io_comp);
 	} else {
 		unsigned to_end;
 		io_comp.in_flight = (atomic_t)ATOMIC_INIT(2);
 	blk_queue_max_integrity_segments(disk->queue, UINT_MAX);
 }
-/* FIXME: use new kvmalloc */
-static void *dm_integrity_kvmalloc(size_t size, gfp_t gfp)
-{
-	void *ptr = NULL;
-	if (size <= PAGE_SIZE)
-		ptr = kmalloc(size, GFP_KERNEL | gfp);
-	if (!ptr && size <= KMALLOC_MAX_SIZE)
-		ptr = kmalloc(size, GFP_KERNEL | __GFP_NOWARN | __GFP_NORETRY | gfp);
-	if (!ptr)
-		ptr = __vmalloc(size, GFP_KERNEL | gfp, PAGE_KERNEL);
-	return ptr;
-}
 static void dm_integrity_free_page_list(struct dm_integrity_c *ic, struct page_list *pl)
 {
 	unsigned i;
 	struct page_list *pl;
 	unsigned i;
-	pl = dm_integrity_kvmalloc(page_list_desc_size, __GFP_ZERO);
+	pl = kvmalloc(page_list_desc_size, GFP_KERNEL | __GFP_ZERO);
 	if (!pl)
 		return NULL;
 	struct scatterlist **sl;
 	unsigned i;
-	sl = dm_integrity_kvmalloc(ic->journal_sections * sizeof(struct scatterlist *), __GFP_ZERO);
+	sl = kvmalloc(ic->journal_sections * sizeof(struct scatterlist *), GFP_KERNEL | __GFP_ZERO);
 	if (!sl)
 		return NULL;
 		n_pages = (end_index - start_index + 1);
-		s = dm_integrity_kvmalloc(n_pages * sizeof(struct scatterlist), 0);
+		s = kvmalloc(n_pages * sizeof(struct scatterlist), GFP_KERNEL);
 		if (!s) {
 			dm_integrity_free_journal_scatterlist(ic, sl);
 			return NULL;
 				goto bad;
 			}
-			sg = dm_integrity_kvmalloc((ic->journal_pages + 1) * sizeof(struct scatterlist), 0);
+			sg = kvmalloc((ic->journal_pages + 1) * sizeof(struct scatterlist), GFP_KERNEL);
 			if (!sg) {
 				*error = "Unable to allocate sg list";
 				r = -ENOMEM;
 				r = -ENOMEM;
 				goto bad;
 			}
-			ic->sk_requests = dm_integrity_kvmalloc(ic->journal_sections * sizeof(struct skcipher_request *), __GFP_ZERO);
+			ic->sk_requests = kvmalloc(ic->journal_sections * sizeof(struct skcipher_request *), GFP_KERNEL | __GFP_ZERO);
 			if (!ic->sk_requests) {
 				*error = "Unable to allocate sk requests";
 				r = -ENOMEM;
 		r = -ENOMEM;
 		goto bad;
 	}
-	ic->journal_tree = dm_integrity_kvmalloc(journal_tree_size, 0);
+	ic->journal_tree = kvmalloc(journal_tree_size, GFP_KERNEL);
 	if (!ic->journal_tree) {
 		*error = "Could not allocate memory for journal tree";
 		r = -ENOMEM;

drivers/md/dm-ioctl.c+3−2

 	}
 	/*
-	 * Try to avoid low memory issues when a device is suspended.
+	 * Use __GFP_HIGH to avoid low memory issues when a device is
+	 * suspended and the ioctl is needed to resume it.
 	 * Use kmalloc() rather than vmalloc() when we can.
 	 */
 	dmi = NULL;
 	noio_flag = memalloc_noio_save();
-	dmi = kvmalloc(param_kernel->data_size, GFP_KERNEL);
+	dmi = kvmalloc(param_kernel->data_size, GFP_KERNEL | __GFP_HIGH);
 	memalloc_noio_restore(noio_flag);
 	if (!dmi) {

drivers/md/dm-raid1.c+1−1

@@ -260,7 +260,7 @@ static int mirror_flush(struct dm_target *ti) · 259 unmodified lines
260	struct mirror *m;	260	struct mirror *m;
261	struct dm_io_request io_req = {	261	struct dm_io_request io_req = {
262	.bi_op = REQ_OP_WRITE,	262	.bi_op = REQ_OP_WRITE,
263	.bi_op_flags = REQ_PREFLUSH,	263	.bi_op_flags = REQ_PREFLUSH \| REQ_SYNC,
264	.mem.type = DM_IO_KMEM,	264	.mem.type = DM_IO_KMEM,
265	.mem.ptr.addr = NULL,	265	.mem.ptr.addr = NULL,
266	.client = ms->io_client,	266	.client = ms->io_client,

drivers/md/dm-snap-persistent.c+2−1

@@ -741,7 +741,8 @@ static void persistent_commit_exception(struct dm_exception_store *store, · 740 unmodified lines
741	/*	741	/*
742	* Commit exceptions to disk.	742	* Commit exceptions to disk.
743	*/	743	*/
744	if (ps->valid && area_io(ps, REQ_OP_WRITE, REQ_PREFLUSH \| REQ_FUA))	744	if (ps->valid && area_io(ps, REQ_OP_WRITE,
		745	REQ_PREFLUSH \| REQ_FUA \| REQ_SYNC))
745	ps->valid = 0;	746	ps->valid = 0;
746		747
747	/*	748	/*

drivers/md/dm-verity-target.c+2−2

@@ -166,7 +166,7 @@ static int verity_hash_init(struct dm_verity v, struct ahash_request req, · 165 unmodified lines
166	return r;	166	return r;
167	}	167	}
168		168
169	if (likely(v->version >= 1))	169	if (likely(v->salt_size && (v->version >= 1)))
170	r = verity_hash_update(v, req, v->salt, v->salt_size, res);	170	r = verity_hash_update(v, req, v->salt, v->salt_size, res);
171		171
172	return r;	172	return r;
@@ -177,7 +177,7 @@ static int verity_hash_final(struct dm_verity v, struct ahash_request req, · 4 unmodified lines
177	{	177	{
178	int r;	178	int r;
179		179
180	if (unlikely(!v->version)) {	180	if (unlikely(v->salt_size && (!v->version))) {
181	r = verity_hash_update(v, req, v->salt, v->salt_size, res);	181	r = verity_hash_update(v, req, v->salt, v->salt_size, res);
182		182
183	if (r < 0) {	183	if (r < 0) {

drivers/md/dm.c+1−1

@@ -1657,7 +1657,7 @@ static struct mapped_device *alloc_dev(int minor) · 1656 unmodified lines
1657		1657
1658	bio_init(&md->flush_bio, NULL, 0);	1658	bio_init(&md->flush_bio, NULL, 0);
1659	md->flush_bio.bi_bdev = md->bdev;	1659	md->flush_bio.bi_bdev = md->bdev;
1660	md->flush_bio.bi_opf = REQ_OP_WRITE \| REQ_PREFLUSH;	1660	md->flush_bio.bi_opf = REQ_OP_WRITE \| REQ_PREFLUSH \| REQ_SYNC;
1661		1661
1662	dm_stats_init(&md->stats);	1662	dm_stats_init(&md->stats);
1663		1663

drivers/md/md-cluster.c+3−1

 	cmsg.raid_slot = cpu_to_le32(rdev->desc_nr);
 	lock_comm(cinfo, 1);
 	ret = __sendmsg(cinfo, &cmsg);
-	if (ret)
+	if (ret) {
+		unlock_comm(cinfo);
 		return ret;
+	}
 	cinfo->no_new_dev_lockres->flags |= DLM_LKF_NOQUEUE;
 	ret = dlm_lock_sync(cinfo->no_new_dev_lockres, DLM_LOCK_EX);
 	cinfo->no_new_dev_lockres->flags &= ~DLM_LKF_NOQUEUE;

drivers/md/md.c+13−5

 	    test_bit(FailFast, &rdev->flags) &&
 	    !test_bit(LastDev, &rdev->flags))
 		ff = MD_FAILFAST;
-	bio->bi_opf = REQ_OP_WRITE | REQ_PREFLUSH | REQ_FUA | ff;
+	bio->bi_opf = REQ_OP_WRITE | REQ_SYNC | REQ_PREFLUSH | REQ_FUA | ff;
 	atomic_inc(&mddev->pending_writes);
 	submit_bio(bio);
 static void no_op(struct percpu_ref *r) {}
+int mddev_init_writes_pending(struct mddev *mddev)
+{
+	if (mddev->writes_pending.percpu_count_ptr)
+		return 0;
+	if (percpu_ref_init(&mddev->writes_pending, no_op, 0, GFP_KERNEL) < 0)
+		return -ENOMEM;
+	/* We want to start with the refcount at zero */
+	percpu_ref_put(&mddev->writes_pending);
+	return 0;
+}
+EXPORT_SYMBOL_GPL(mddev_init_writes_pending);
 static int md_alloc(dev_t dev, char *name)
 {
 	/*
 	blk_queue_make_request(mddev->queue, md_make_request);
 	blk_set_stacking_limits(&mddev->queue->limits);
-	if (percpu_ref_init(&mddev->writes_pending, no_op, 0, GFP_KERNEL) < 0)
-		goto abort;
-	/* We want to start with the refcount at zero */
-	percpu_ref_put(&mddev->writes_pending);
 	disk = alloc_disk(1 << shift);
 	if (!disk) {
 		blk_cleanup_queue(mddev->queue);

drivers/md/md.h+1−0

@@ -648,6 +648,7 @@ extern void md_unregister_thread(struct md_thread **threadp); · 647 unmodified lines
648	extern void md_wakeup_thread(struct md_thread *thread);	648	extern void md_wakeup_thread(struct md_thread *thread);
649	extern void md_check_recovery(struct mddev *mddev);	649	extern void md_check_recovery(struct mddev *mddev);
650	extern void md_reap_sync_thread(struct mddev *mddev);	650	extern void md_reap_sync_thread(struct mddev *mddev);
		651	extern int mddev_init_writes_pending(struct mddev *mddev);
651	extern void md_write_start(struct mddev mddev, struct bio bi);	652	extern void md_write_start(struct mddev mddev, struct bio bi);
652	extern void md_write_inc(struct mddev mddev, struct bio bi);	653	extern void md_write_inc(struct mddev mddev, struct bio bi);
653	extern void md_write_end(struct mddev *mddev);	654	extern void md_write_end(struct mddev *mddev);

drivers/md/raid1.c+2−0

 			mdname(mddev));
 		return -EIO;
 	}
+	if (mddev_init_writes_pending(mddev) < 0)
+		return -ENOMEM;
 	/*
 	 * copy the already verified devices into our private RAID1
 	 * bookkeeping area. [whatever we allocate in run(),

drivers/md/raid10.c+3−0

@@ -3611,6 +3611,9 @@ static int raid10_run(struct mddev *mddev) · 3610 unmodified lines
3611	int first = 1;	3611	int first = 1;
3612	bool discard_supported = false;	3612	bool discard_supported = false;
3613		3613
		3614	if (mddev_init_writes_pending(mddev) < 0)
		3615	return -ENOMEM;
		3616
3614	if (mddev->private == NULL) {	3617	if (mddev->private == NULL) {
3615	conf = setup_conf(mddev);	3618	conf = setup_conf(mddev);
3616	if (IS_ERR(conf))	3619	if (IS_ERR(conf))

drivers/md/raid5-cache.c+2−2

@@ -1782,7 +1782,7 @@ static int r5l_log_write_empty_meta_block(struct r5l_log *log, sector_t pos, · 1781 unmodified lines
1782	mb->checksum = cpu_to_le32(crc32c_le(log->uuid_checksum,	1782	mb->checksum = cpu_to_le32(crc32c_le(log->uuid_checksum,
1783	mb, PAGE_SIZE));	1783	mb, PAGE_SIZE));
1784	if (!sync_page_io(log->rdev, pos, PAGE_SIZE, page, REQ_OP_WRITE,	1784	if (!sync_page_io(log->rdev, pos, PAGE_SIZE, page, REQ_OP_WRITE,
1785	REQ_FUA, false)) {	1785	REQ_SYNC \| REQ_FUA, false)) {
1786	__free_page(page);	1786	__free_page(page);
1787	return -EIO;	1787	return -EIO;
1788	}	1788	}
@@ -2388,7 +2388,7 @@ r5c_recovery_rewrite_data_only_stripes(struct r5l_log *log, · 599 unmodified lines
2388	mb->checksum = cpu_to_le32(crc32c_le(log->uuid_checksum,	2388	mb->checksum = cpu_to_le32(crc32c_le(log->uuid_checksum,
2389	mb, PAGE_SIZE));	2389	mb, PAGE_SIZE));
2390	sync_page_io(log->rdev, ctx->pos, PAGE_SIZE, page,	2390	sync_page_io(log->rdev, ctx->pos, PAGE_SIZE, page,
2391	REQ_OP_WRITE, REQ_FUA, false);	2391	REQ_OP_WRITE, REQ_SYNC \| REQ_FUA, false);
2392	sh->log_start = ctx->pos;	2392	sh->log_start = ctx->pos;
2393	list_add_tail(&sh->r5c, &log->stripe_in_journal_list);	2393	list_add_tail(&sh->r5c, &log->stripe_in_journal_list);
2394	atomic_inc(&log->stripe_in_journal_count);	2394	atomic_inc(&log->stripe_in_journal_count);

drivers/md/raid5-ppl.c+2−2

@@ -907,8 +907,8 @@ static int ppl_write_empty_header(struct ppl_log *log) · 906 unmodified lines
907	pplhdr->checksum = cpu_to_le32(~crc32c_le(~0, pplhdr, PAGE_SIZE));	907	pplhdr->checksum = cpu_to_le32(~crc32c_le(~0, pplhdr, PAGE_SIZE));
908		908
909	if (!sync_page_io(rdev, rdev->ppl.sector - rdev->data_offset,	909	if (!sync_page_io(rdev, rdev->ppl.sector - rdev->data_offset,
910	PPL_HEADER_SIZE, page, REQ_OP_WRITE \| REQ_FUA, 0,	910	PPL_HEADER_SIZE, page, REQ_OP_WRITE \| REQ_SYNC \|
911	false)) {	911	REQ_FUA, 0, false)) {
912	md_error(rdev->mddev, rdev);	912	md_error(rdev->mddev, rdev);
913	ret = -EIO;	913	ret = -EIO;
914	}	914	}

drivers/md/raid5.c+17−4

 			set_bit(STRIPE_INSYNC, &sh->state);
 		else {
 			atomic64_add(STRIPE_SECTORS, &conf->mddev->resync_mismatches);
-			if (test_bit(MD_RECOVERY_CHECK, &conf->mddev->recovery))
+			if (test_bit(MD_RECOVERY_CHECK, &conf->mddev->recovery)) {
 				/* don't try to repair!! */
 				set_bit(STRIPE_INSYNC, &sh->state);
-			else {
+				pr_warn_ratelimited("%s: mismatch sector in range "
+						    "%llu-%llu\n", mdname(conf->mddev),
+						    (unsigned long long) sh->sector,
+						    (unsigned long long) sh->sector +
+						    STRIPE_SECTORS);
+			} else {
 				sh->check_state = check_state_compute_run;
 				set_bit(STRIPE_COMPUTE_RUN, &sh->state);
 				set_bit(STRIPE_OP_COMPUTE_BLK, &s->ops_request);
 			}
 		} else {
 			atomic64_add(STRIPE_SECTORS, &conf->mddev->resync_mismatches);
-			if (test_bit(MD_RECOVERY_CHECK, &conf->mddev->recovery))
+			if (test_bit(MD_RECOVERY_CHECK, &conf->mddev->recovery)) {
 				/* don't try to repair!! */
 				set_bit(STRIPE_INSYNC, &sh->state);
-			else {
+				pr_warn_ratelimited("%s: mismatch sector in range "
+						    "%llu-%llu\n", mdname(conf->mddev),
+						    (unsigned long long) sh->sector,
+						    (unsigned long long) sh->sector +
+						    STRIPE_SECTORS);
+			} else {
 				int *target = &sh->ops.target;
 				sh->ops.target = -1;
 	long long min_offset_diff = 0;
 	int first = 1;
+	if (mddev_init_writes_pending(mddev) < 0)
+		return -ENOMEM;
 	if (mddev->recovery_cp != MaxSector)
 		pr_notice("md/raid:%s: not clean -- starting background reconstruction\n",
 			  mdname(mddev));

drivers/media/cec/cec-api.c+1−7

 			bool block, struct cec_msg __user *parg)
 {
 	struct cec_msg msg = {};
-	long err = 0;
+	long err;
 	if (copy_from_user(&msg, parg, sizeof(msg)))
 		return -EFAULT;
-	mutex_lock(&adap->lock);
-	if (!adap->is_configured && fh->mode_follower < CEC_MODE_MONITOR)
-		err = -ENONET;
-	mutex_unlock(&adap->lock);
-	if (err)
-		return err;
 	err = cec_receive_msg(fh, &msg, block);
 	if (err)

drivers/media/platform/mtk-vcodec/vdec/vdec_h264_if.c+4−4

@@ -493,10 +493,10 @@ static int vdec_h264_get_param(unsigned long h_vdec, · 492 unmodified lines
493	}	493	}
494		494
495	static struct vdec_common_if vdec_h264_if = {	495	static struct vdec_common_if vdec_h264_if = {
496	vdec_h264_init,	496	.init = vdec_h264_init,
497	vdec_h264_decode,	497	.decode = vdec_h264_decode,
498	vdec_h264_get_param,	498	.get_param = vdec_h264_get_param,
499	vdec_h264_deinit,	499	.deinit = vdec_h264_deinit,
500	};	500	};
501		501
502	struct vdec_common_if *get_h264_dec_comm_if(void);	502	struct vdec_common_if *get_h264_dec_comm_if(void);

drivers/media/platform/mtk-vcodec/vdec/vdec_vp8_if.c+4−4

@@ -620,10 +620,10 @@ static void vdec_vp8_deinit(unsigned long h_vdec) · 619 unmodified lines
620	}	620	}
621		621
622	static struct vdec_common_if vdec_vp8_if = {	622	static struct vdec_common_if vdec_vp8_if = {
623	vdec_vp8_init,	623	.init = vdec_vp8_init,
624	vdec_vp8_decode,	624	.decode = vdec_vp8_decode,
625	vdec_vp8_get_param,	625	.get_param = vdec_vp8_get_param,
626	vdec_vp8_deinit,	626	.deinit = vdec_vp8_deinit,
627	};	627	};
628		628
629	struct vdec_common_if *get_vp8_dec_comm_if(void);	629	struct vdec_common_if *get_vp8_dec_comm_if(void);

drivers/media/platform/mtk-vcodec/vdec/vdec_vp9_if.c+4−4

@@ -979,10 +979,10 @@ static int vdec_vp9_get_param(unsigned long h_vdec, · 978 unmodified lines
979	}	979	}
980		980
981	static struct vdec_common_if vdec_vp9_if = {	981	static struct vdec_common_if vdec_vp9_if = {
982	vdec_vp9_init,	982	.init = vdec_vp9_init,
983	vdec_vp9_decode,	983	.decode = vdec_vp9_decode,
984	vdec_vp9_get_param,	984	.get_param = vdec_vp9_get_param,
985	vdec_vp9_deinit,	985	.deinit = vdec_vp9_deinit,
986	};	986	};
987		987
988	struct vdec_common_if *get_vp9_dec_comm_if(void);	988	struct vdec_common_if *get_vp9_dec_comm_if(void);

drivers/memory/atmel-ebi.c+1−1

@@ -581,7 +581,7 @@ static int atmel_ebi_probe(struct platform_device *pdev) · 580 unmodified lines
581	return of_platform_populate(np, NULL, NULL, dev);	581	return of_platform_populate(np, NULL, NULL, dev);
582	}	582	}
583		583
584	static int atmel_ebi_resume(struct device *dev)	584	static __maybe_unused int atmel_ebi_resume(struct device *dev)
585	{	585	{
586	struct atmel_ebi *ebi = dev_get_drvdata(dev);	586	struct atmel_ebi *ebi = dev_get_drvdata(dev);
587	struct atmel_ebi_dev *ebid;	587	struct atmel_ebi_dev *ebid;

drivers/misc/cxl/file.c+2−5

 	/* Do this outside the status_mutex to avoid a circular dependency with
 	 * the locking in cxl_mmap_fault() */
-	if (copy_from_user(&work, uwork,
+	if (copy_from_user(&work, uwork, sizeof(work)))
-			   sizeof(struct cxl_ioctl_start_work))) {
+		return -EFAULT;
-		rc = -EFAULT;
-		goto out;
-	}
 	mutex_lock(&ctx->status_mutex);
 	if (ctx->status != OPENED) {

drivers/misc/cxl/native.c+11−3

 void cxl_native_release_psl_err_irq(struct cxl *adapter)
 {
-	if (adapter->native->err_virq != irq_find_mapping(NULL, adapter->native->err_hwirq))
+	if (adapter->native->err_virq == 0 ||
+	    adapter->native->err_virq !=
+	    irq_find_mapping(NULL, adapter->native->err_hwirq))
 		return;
 	cxl_p1_write(adapter, CXL_PSL_ErrIVTE, 0x0000000000000000);
 	cxl_unmap_irq(adapter->native->err_virq, adapter);
 	cxl_ops->release_one_irq(adapter, adapter->native->err_hwirq);
 	kfree(adapter->irq_name);
+	adapter->native->err_virq = 0;
 }
 int cxl_native_register_serr_irq(struct cxl_afu *afu)
 void cxl_native_release_serr_irq(struct cxl_afu *afu)
 {
-	if (afu->serr_virq != irq_find_mapping(NULL, afu->serr_hwirq))
+	if (afu->serr_virq == 0 ||
+	    afu->serr_virq != irq_find_mapping(NULL, afu->serr_hwirq))
 		return;
 	cxl_p1n_write(afu, CXL_PSL_SERR_An, 0x0000000000000000);
 	cxl_unmap_irq(afu->serr_virq, afu);
 	cxl_ops->release_one_irq(afu->adapter, afu->serr_hwirq);
 	kfree(afu->err_irq_name);
+	afu->serr_virq = 0;
 }
 int cxl_native_register_psl_irq(struct cxl_afu *afu)
 void cxl_native_release_psl_irq(struct cxl_afu *afu)
 {
-	if (afu->native->psl_virq != irq_find_mapping(NULL, afu->native->psl_hwirq))
+	if (afu->native->psl_virq == 0 ||
+	    afu->native->psl_virq !=
+	    irq_find_mapping(NULL, afu->native->psl_hwirq))
 		return;
 	cxl_unmap_irq(afu->native->psl_virq, afu);
 	cxl_ops->release_one_irq(afu->adapter, afu->native->psl_hwirq);
 	kfree(afu->psl_irq_name);
+	afu->native->psl_virq = 0;
 }
 static void recover_psl_err(struct cxl_afu *afu, u64 errstat)

drivers/misc/mei/bus.c+3−1

 {
 	struct mei_cl_device *cldev = to_mei_cl_device(dev);
 	const uuid_le *uuid = mei_me_cl_uuid(cldev->me_cl);
+	u8 version = mei_me_cl_ver(cldev->me_cl);
-	return scnprintf(buf, PAGE_SIZE, "mei:%s:%pUl:", cldev->name, uuid);
+	return scnprintf(buf, PAGE_SIZE, "mei:%s:%pUl:%02X:",
+			 cldev->name, uuid, version);
 }
 static DEVICE_ATTR_RO(modalias);

drivers/misc/sgi-xp/xp.h+11−1

 xpc_send(short partid, int ch_number, u32 flags, void *payload,
 	 u16 payload_size)
 {
+	if (!xpc_interface.send)
+		return xpNotLoaded;
 	return xpc_interface.send(partid, ch_number, flags, payload,
 				  payload_size);
 }
 xpc_send_notify(short partid, int ch_number, u32 flags, void *payload,
 		u16 payload_size, xpc_notify_func func, void *key)
 {
+	if (!xpc_interface.send_notify)
+		return xpNotLoaded;
 	return xpc_interface.send_notify(partid, ch_number, flags, payload,
 					 payload_size, func, key);
 }
 static inline void
 xpc_received(short partid, int ch_number, void *payload)
 {
-	return xpc_interface.received(partid, ch_number, payload);
+	if (xpc_interface.received)
+		xpc_interface.received(partid, ch_number, payload);
 }
 static inline enum xp_retval
 xpc_partid_to_nasids(short partid, void *nasids)
 {
+	if (!xpc_interface.partid_to_nasids)
+		return xpNotLoaded;
 	return xpc_interface.partid_to_nasids(partid, nasids);
 }

drivers/misc/sgi-xp/xp_main.c+7−29

 EXPORT_SYMBOL_GPL(xpc_registrations);
 /*
- * Initialize the XPC interface to indicate that XPC isn't loaded.
+ * Initialize the XPC interface to NULL to indicate that XPC isn't loaded.
  */
-static enum xp_retval
+struct xpc_interface xpc_interface = { };
-xpc_notloaded(void)
-{
-	return xpNotLoaded;
-}
-struct xpc_interface xpc_interface = {
-	(void (*)(int))xpc_notloaded,
-	(void (*)(int))xpc_notloaded,
-	(enum xp_retval(*)(short, int, u32, void *, u16))xpc_notloaded,
-	(enum xp_retval(*)(short, int, u32, void *, u16, xpc_notify_func,
-			   void *))xpc_notloaded,
-	(void (*)(short, int, void *))xpc_notloaded,
-	(enum xp_retval(*)(short, void *))xpc_notloaded
-};
 EXPORT_SYMBOL_GPL(xpc_interface);
 /*
 void
 xpc_clear_interface(void)
 {
-	xpc_interface.connect = (void (*)(int))xpc_notloaded;
+	memset(&xpc_interface, 0, sizeof(xpc_interface));
-	xpc_interface.disconnect = (void (*)(int))xpc_notloaded;
-	xpc_interface.send = (enum xp_retval(*)(short, int, u32, void *, u16))
-	    xpc_notloaded;
-	xpc_interface.send_notify = (enum xp_retval(*)(short, int, u32, void *,
-						       u16, xpc_notify_func,
-						       void *))xpc_notloaded;
-	xpc_interface.received = (void (*)(short, int, void *))
-	    xpc_notloaded;
-	xpc_interface.partid_to_nasids = (enum xp_retval(*)(short, void *))
-	    xpc_notloaded;
 }
 EXPORT_SYMBOL_GPL(xpc_clear_interface);
 	mutex_unlock(&registration->mutex);
-	xpc_interface.connect(ch_number);
+	if (xpc_interface.connect)
+		xpc_interface.connect(ch_number);
 	return xpSuccess;
 }
 	registration->assigned_limit = 0;
 	registration->idle_limit = 0;
-	xpc_interface.disconnect(ch_number);
+	if (xpc_interface.disconnect)
+		xpc_interface.disconnect(ch_number);
 	mutex_unlock(&registration->mutex);

drivers/mmc/host/meson-gx-mmc.c+9−0

@@ -210,6 +210,15 @@ static void meson_mmc_get_transfer_mode(struct mmc_host *mmc, · 209 unmodified lines
210	int i;	210	int i;
211	bool use_desc_chain_mode = true;	211	bool use_desc_chain_mode = true;
212		212
		213	/*
		214	* Broken SDIO with AP6255-based WiFi on Khadas VIM Pro has been
		215	* reported. For some strange reason this occurs in descriptor
		216	* chain mode only. So let's fall back to bounce buffer mode
		217	* for command SD_IO_RW_EXTENDED.
		218	*/
		219	if (mrq->cmd->opcode == SD_IO_RW_EXTENDED)
		220	return;
		221
213	for_each_sg(data->sg, sg, data->sg_len, i)	222	for_each_sg(data->sg, sg, data->sg_len, i)
214	/* check for 8 byte alignment */	223	/* check for 8 byte alignment */
215	if (sg->offset & 7) {	224	if (sg->offset & 7) {

drivers/mtd/nand/nand_base.c+35−11

 	return 0;
 }
-const struct mtd_ooblayout_ops nand_ooblayout_lp_hamming_ops = {
+static const struct mtd_ooblayout_ops nand_ooblayout_lp_hamming_ops = {
 	.ecc = nand_ooblayout_ecc_lp_hamming,
 	.free = nand_ooblayout_free_lp_hamming,
 };
 	/* Initialize the ->data_interface field. */
 	ret = nand_init_data_interface(chip);
 	if (ret)
-		return ret;
+		goto err_nand_init;
 	/*
 	 * Setup the data interface correctly on the chip and controller side.
 	 */
 	ret = nand_setup_data_interface(chip);
 	if (ret)
-		return ret;
+		goto err_nand_init;
 	nand_maf_id = chip->id.data[0];
 	nand_dev_id = chip->id.data[1];
 	mtd->size = i * chip->chipsize;
 	return 0;
+err_nand_init:
+	/* Free manufacturer priv data. */
+	nand_manufacturer_cleanup(chip);
+	return ret;
 }
 EXPORT_SYMBOL(nand_scan_ident);
 	/* New bad blocks should be marked in OOB, flash-based BBT, or both */
 	if (WARN_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
-		   !(chip->bbt_options & NAND_BBT_USE_FLASH)))
+		   !(chip->bbt_options & NAND_BBT_USE_FLASH))) {
-		return -EINVAL;
+		ret = -EINVAL;
+		goto err_ident;
+	}
 	if (invalid_ecc_page_accessors(chip)) {
 		pr_err("Invalid ECC page accessors setup\n");
-		return -EINVAL;
+		ret = -EINVAL;
+		goto err_ident;
 	}
 	if (!(chip->options & NAND_OWN_BUFFERS)) {
 		nbuf = kzalloc(sizeof(*nbuf), GFP_KERNEL);
-		if (!nbuf)
+		if (!nbuf) {
-			return -ENOMEM;
+			ret = -ENOMEM;
+			goto err_ident;
+		}
 		nbuf->ecccalc = kmalloc(mtd->oobsize, GFP_KERNEL);
 		if (!nbuf->ecccalc) {
 		chip->buffers = nbuf;
 	} else {
-		if (!chip->buffers)
+		if (!chip->buffers) {
-			return -ENOMEM;
+			ret = -ENOMEM;
+			goto err_ident;
+		}
 	}
 	/* Set the internal oob buffer location, just after the page data */
 		return 0;
 	/* Build bad block table */
-	return chip->scan_bbt(mtd);
+	ret = chip->scan_bbt(mtd);
+	if (ret)
+		goto err_free;
+	return 0;
 err_free:
 	if (nbuf) {
 		kfree(nbuf->databuf);
 		kfree(nbuf->ecccalc);
 		kfree(nbuf);
 	}
+err_ident:
+	/* Clean up nand_scan_ident(). */
+	/* Free manufacturer priv data. */
+	nand_manufacturer_cleanup(chip);
 	return ret;
 }
 EXPORT_SYMBOL(nand_scan_tail);

drivers/mtd/nand/nand_ids.c+0−1

@@ -6,7 +6,6 @@ · 5 unmodified lines
6	* published by the Free Software Foundation.	6	* published by the Free Software Foundation.
7	*	7	*
8	*/	8	*/
9	#include <linux/module.h>
10	#include <linux/mtd/nand.h>	9	#include <linux/mtd/nand.h>
11	#include <linux/sizes.h>	10	#include <linux/sizes.h>
12		11

drivers/mtd/nand/nand_samsung.c+3−0

 			case 7:
 				chip->ecc_strength_ds = 60;
 				break;
+			default:
+				WARN(1, "Could not decode ECC info");
+				chip->ecc_step_ds = 0;
 			}
 		}
 	} else {

drivers/mtd/nand/tango_nand.c+16−7

  * byte 1 for other packets in the page (PKT_N, for N > 0)
  * ERR_COUNT_PKT_N is the max error count over all but the first packet.
  */
-#define DECODE_OK_PKT_0(v)	((v) & BIT(7))
-#define DECODE_OK_PKT_N(v)	((v) & BIT(15))
 #define ERR_COUNT_PKT_0(v)	(((v) >> 0) & 0x3f)
 #define ERR_COUNT_PKT_N(v)	(((v) >> 8) & 0x3f)
+#define DECODE_FAIL_PKT_0(v)	(((v) & BIT(7)) == 0)
+#define DECODE_FAIL_PKT_N(v)	(((v) & BIT(15)) == 0)
 /* Offsets relative to pbus_base */
 #define PBUS_CS_CTRL	0x83c
 						  chip->ecc.strength);
 		if (res < 0)
 			mtd->ecc_stats.failed++;
+		else
+			mtd->ecc_stats.corrected += res;
 		bitflips = max(res, bitflips);
 		buf += pkt_size;
 	return bitflips;
 }
-static int decode_error_report(struct tango_nfc *nfc)
+static int decode_error_report(struct nand_chip *chip)
 {
 	u32 status, res;
+	struct mtd_info *mtd = nand_to_mtd(chip);
+	struct tango_nfc *nfc = to_tango_nfc(chip->controller);
 	status = readl_relaxed(nfc->reg_base + NFC_XFER_STATUS);
 	if (status & PAGE_IS_EMPTY)
 	res = readl_relaxed(nfc->mem_base + ERROR_REPORT);
-	if (DECODE_OK_PKT_0(res) && DECODE_OK_PKT_N(res))
+	if (DECODE_FAIL_PKT_0(res) || DECODE_FAIL_PKT_N(res))
-		return max(ERR_COUNT_PKT_0(res), ERR_COUNT_PKT_N(res));
+		return -EBADMSG;
+	/* ERR_COUNT_PKT_N is max, not sum, but that's all we have */
+	mtd->ecc_stats.corrected +=
+		ERR_COUNT_PKT_0(res) + ERR_COUNT_PKT_N(res);
-	return -EBADMSG;
+	return max(ERR_COUNT_PKT_0(res), ERR_COUNT_PKT_N(res));
 }
 static void tango_dma_callback(void *arg)
 	if (err)
 		return err;
-	res = decode_error_report(nfc);
+	res = decode_error_report(chip);
 	if (res < 0) {
 		chip->ecc.read_oob_raw(mtd, chip, page);
 		res = check_erased_page(chip, buf);
 	{ .compatible = "sigma,smp8758-nand" },
 	{ /* sentinel */ }
 };
+MODULE_DEVICE_TABLE(of, tango_nand_ids);
 static struct platform_driver tango_nand_driver = {
 	.probe	= tango_nand_probe,

drivers/net/bonding/bond_3ad.c+27−0

 	AD_LINK_SPEED_100MBPS,
 	AD_LINK_SPEED_1000MBPS,
 	AD_LINK_SPEED_2500MBPS,
+	AD_LINK_SPEED_5000MBPS,
 	AD_LINK_SPEED_10000MBPS,
+	AD_LINK_SPEED_14000MBPS,
 	AD_LINK_SPEED_20000MBPS,
 	AD_LINK_SPEED_25000MBPS,
 	AD_LINK_SPEED_40000MBPS,
+	AD_LINK_SPEED_50000MBPS,
 	AD_LINK_SPEED_56000MBPS,
 	AD_LINK_SPEED_100000MBPS,
 };
  *     %AD_LINK_SPEED_100MBPS,
  *     %AD_LINK_SPEED_1000MBPS,
  *     %AD_LINK_SPEED_2500MBPS,
+ *     %AD_LINK_SPEED_5000MBPS,
  *     %AD_LINK_SPEED_10000MBPS
+ *     %AD_LINK_SPEED_14000MBPS,
  *     %AD_LINK_SPEED_20000MBPS
  *     %AD_LINK_SPEED_25000MBPS
  *     %AD_LINK_SPEED_40000MBPS
+ *     %AD_LINK_SPEED_50000MBPS
  *     %AD_LINK_SPEED_56000MBPS
  *     %AD_LINK_SPEED_100000MBPS
  */
 			speed = AD_LINK_SPEED_2500MBPS;
 			break;
+		case SPEED_5000:
+			speed = AD_LINK_SPEED_5000MBPS;
+			break;
 		case SPEED_10000:
 			speed = AD_LINK_SPEED_10000MBPS;
 			break;
+		case SPEED_14000:
+			speed = AD_LINK_SPEED_14000MBPS;
+			break;
 		case SPEED_20000:
 			speed = AD_LINK_SPEED_20000MBPS;
 			break;
 			speed = AD_LINK_SPEED_40000MBPS;
 			break;
+		case SPEED_50000:
+			speed = AD_LINK_SPEED_50000MBPS;
+			break;
 		case SPEED_56000:
 			speed = AD_LINK_SPEED_56000MBPS;
 			break;
 		case AD_LINK_SPEED_2500MBPS:
 			bandwidth = nports * 2500;
 			break;
+		case AD_LINK_SPEED_5000MBPS:
+			bandwidth = nports * 5000;
+			break;
 		case AD_LINK_SPEED_10000MBPS:
 			bandwidth = nports * 10000;
 			break;
+		case AD_LINK_SPEED_14000MBPS:
+			bandwidth = nports * 14000;
+			break;
 		case AD_LINK_SPEED_20000MBPS:
 			bandwidth = nports * 20000;
 			break;
 		case AD_LINK_SPEED_40000MBPS:
 			bandwidth = nports * 40000;
 			break;
+		case AD_LINK_SPEED_50000MBPS:
+			bandwidth = nports * 50000;
+			break;
 		case AD_LINK_SPEED_56000MBPS:
 			bandwidth = nports * 56000;
 			break;

drivers/net/bonding/bond_main.c+3−3

 	struct bonding *bond = netdev_priv(bond_dev);
 	if (bond->wq)
 		destroy_workqueue(bond->wq);
-	free_netdev(bond_dev);
 }
 void bond_setup(struct net_device *bond_dev)
 	bond_dev->netdev_ops = &bond_netdev_ops;
 	bond_dev->ethtool_ops = &bond_ethtool_ops;
-	bond_dev->destructor = bond_destructor;
+	bond_dev->needs_free_netdev = true;
+	bond_dev->priv_destructor = bond_destructor;
 	SET_NETDEV_DEVTYPE(bond_dev, &bond_type);
 	rtnl_unlock();
 	if (res < 0)
-		bond_destructor(bond_dev);
+		free_netdev(bond_dev);
 	return res;
 }

drivers/net/caif/caif_hsi.c+1−1

@@ -1121,7 +1121,7 @@ static void cfhsi_setup(struct net_device *dev) · 1120 unmodified lines
1121	dev->flags = IFF_POINTOPOINT \| IFF_NOARP;	1121	dev->flags = IFF_POINTOPOINT \| IFF_NOARP;
1122	dev->mtu = CFHSI_MAX_CAIF_FRAME_SZ;	1122	dev->mtu = CFHSI_MAX_CAIF_FRAME_SZ;
1123	dev->priv_flags \|= IFF_NO_QUEUE;	1123	dev->priv_flags \|= IFF_NO_QUEUE;
1124	dev->destructor = free_netdev;	1124	dev->needs_free_netdev = true;
1125	dev->netdev_ops = &cfhsi_netdevops;	1125	dev->netdev_ops = &cfhsi_netdevops;
1126	for (i = 0; i < CFHSI_PRIO_LAST; ++i)	1126	for (i = 0; i < CFHSI_PRIO_LAST; ++i)
1127	skb_queue_head_init(&cfhsi->qhead[i]);	1127	skb_queue_head_init(&cfhsi->qhead[i]);

drivers/net/caif/caif_serial.c+1−1

@@ -428,7 +428,7 @@ static void caifdev_setup(struct net_device *dev) · 427 unmodified lines
428	dev->flags = IFF_POINTOPOINT \| IFF_NOARP;	428	dev->flags = IFF_POINTOPOINT \| IFF_NOARP;
429	dev->mtu = CAIF_MAX_MTU;	429	dev->mtu = CAIF_MAX_MTU;
430	dev->priv_flags \|= IFF_NO_QUEUE;	430	dev->priv_flags \|= IFF_NO_QUEUE;
431	dev->destructor = free_netdev;	431	dev->needs_free_netdev = true;
432	skb_queue_head_init(&serdev->head);	432	skb_queue_head_init(&serdev->head);
433	serdev->common.link_select = CAIF_LINK_LOW_LATENCY;	433	serdev->common.link_select = CAIF_LINK_LOW_LATENCY;
434	serdev->common.use_frag = true;	434	serdev->common.use_frag = true;

drivers/net/caif/caif_spi.c+1−1

@@ -712,7 +712,7 @@ static void cfspi_setup(struct net_device *dev) · 711 unmodified lines
712	dev->flags = IFF_NOARP \| IFF_POINTOPOINT;	712	dev->flags = IFF_NOARP \| IFF_POINTOPOINT;
713	dev->priv_flags \|= IFF_NO_QUEUE;	713	dev->priv_flags \|= IFF_NO_QUEUE;
714	dev->mtu = SPI_MAX_PAYLOAD_SIZE;	714	dev->mtu = SPI_MAX_PAYLOAD_SIZE;
715	dev->destructor = free_netdev;	715	dev->needs_free_netdev = true;
716	skb_queue_head_init(&cfspi->qhead);	716	skb_queue_head_init(&cfspi->qhead);
717	skb_queue_head_init(&cfspi->chead);	717	skb_queue_head_init(&cfspi->chead);
718	cfspi->cfdev.link_select = CAIF_LINK_HIGH_BANDW;	718	cfspi->cfdev.link_select = CAIF_LINK_HIGH_BANDW;

drivers/net/caif/caif_virtio.c+1−1

@@ -617,7 +617,7 @@ static void cfv_netdev_setup(struct net_device *netdev) · 616 unmodified lines
617	netdev->tx_queue_len = 100;	617	netdev->tx_queue_len = 100;
618	netdev->flags = IFF_POINTOPOINT \| IFF_NOARP;	618	netdev->flags = IFF_POINTOPOINT \| IFF_NOARP;
619	netdev->mtu = CFV_DEF_MTU_SIZE;	619	netdev->mtu = CFV_DEF_MTU_SIZE;
620	netdev->destructor = free_netdev;	620	netdev->needs_free_netdev = true;
621	}	621	}
622		622
623	/* Create debugfs counters for the device */	623	/* Create debugfs counters for the device */

drivers/net/can/dev.c+3−0

@@ -391,6 +391,9 @@ void can_change_state(struct net_device dev, struct can_frame cf, · 390 unmodified lines
391	can_update_state_error_stats(dev, new_state);	391	can_update_state_error_stats(dev, new_state);
392	priv->state = new_state;	392	priv->state = new_state;
393		393
		394	if (!cf)
		395	return;
		396
394	if (unlikely(new_state == CAN_STATE_BUS_OFF)) {	397	if (unlikely(new_state == CAN_STATE_BUS_OFF)) {
395	cf->can_id \|= CAN_ERR_BUSOFF;	398	cf->can_id \|= CAN_ERR_BUSOFF;
396	return;	399	return;

drivers/net/can/peak_canfd/peak_canfd.c+1−1

@@ -489,7 +489,7 @@ int peak_canfd_handle_msgs_list(struct peak_canfd_priv *priv, · 488 unmodified lines
489	struct pucan_rx_msg *msg_list, int msg_count)	489	struct pucan_rx_msg *msg_list, int msg_count)
490	{	490	{
491	void *msg_ptr = msg_list;	491	void *msg_ptr = msg_list;
492	int i, msg_size;	492	int i, msg_size = 0;
493		493
494	for (i = 0; i < msg_count; i++) {	494	for (i = 0; i < msg_count; i++) {
495	msg_size = peak_canfd_handle_msg(priv, msg_ptr);	495	msg_size = peak_canfd_handle_msg(priv, msg_ptr);

drivers/net/can/slcan.c+3−4

@@ -417,7 +417,7 @@ static int slc_open(struct net_device *dev) · 416 unmodified lines
417	static void slc_free_netdev(struct net_device *dev)	417	static void slc_free_netdev(struct net_device *dev)
418	{	418	{
419	int i = dev->base_addr;	419	int i = dev->base_addr;
420	free_netdev(dev);	420
421	slcan_devs[i] = NULL;	421	slcan_devs[i] = NULL;
422	}	422	}
423		423
@@ -436,7 +436,8 @@ static const struct net_device_ops slc_netdev_ops = { · 12 unmodified lines
436	static void slc_setup(struct net_device *dev)	436	static void slc_setup(struct net_device *dev)
437	{	437	{
438	dev->netdev_ops = &slc_netdev_ops;	438	dev->netdev_ops = &slc_netdev_ops;
439	dev->destructor = slc_free_netdev;	439	dev->needs_free_netdev = true;
		440	dev->priv_destructor = slc_free_netdev;
440		441
441	dev->hard_header_len = 0;	442	dev->hard_header_len = 0;
442	dev->addr_len = 0;	443	dev->addr_len = 0;
@@ -761,8 +762,6 @@ static void __exit slcan_exit(void) · 318 unmodified lines
761	if (sl->tty) {	762	if (sl->tty) {
762	printk(KERN_ERR "%s: tty discipline still running\n",	763	printk(KERN_ERR "%s: tty discipline still running\n",
763	dev->name);	764	dev->name);
764	/* Intentionally leak the control block. */
765	dev->destructor = NULL;
766	}	765	}
767		766
768	unregister_netdev(dev);	767	unregister_netdev(dev);

drivers/net/can/usb/gs_usb.c+2−0

@@ -265,6 +265,8 @@ static int gs_cmd_reset(struct gs_usb gsusb, struct gs_can gsdev) · 264 unmodified lines
265	sizeof(*dm),	265	sizeof(*dm),
266	1000);	266	1000);
267		267
		268	kfree(dm);
		269
268	return rc;	270	return rc;
269	}	271	}
270		272

drivers/net/can/usb/peak_usb/pcan_usb_core.c+1−3

 	const struct peak_usb_adapter *peak_usb_adapter = NULL;
 	int i, err = -ENOMEM;
-	usb_dev = interface_to_usbdev(intf);
 	/* get corresponding PCAN-USB adapter */
 	for (i = 0; i < ARRAY_SIZE(peak_usb_adapters_list); i++)
 		if (peak_usb_adapters_list[i]->device_id == usb_id_product) {
 	if (!peak_usb_adapter) {
 		/* should never come except device_id bad usage in this file */
 		pr_err("%s: didn't find device id. 0x%x in devices list\n",
-			PCAN_USB_DRIVER_NAME, usb_dev->descriptor.idProduct);
+			PCAN_USB_DRIVER_NAME, usb_id_product);
 		return -ENODEV;
 	}

drivers/net/can/vcan.c+2−2

@@ -152,7 +152,7 @@ static const struct net_device_ops vcan_netdev_ops = { · 151 unmodified lines
152	static void vcan_setup(struct net_device *dev)	152	static void vcan_setup(struct net_device *dev)
153	{	153	{
154	dev->type = ARPHRD_CAN;	154	dev->type = ARPHRD_CAN;
155	dev->mtu = CAN_MTU;	155	dev->mtu = CANFD_MTU;
156	dev->hard_header_len = 0;	156	dev->hard_header_len = 0;
157	dev->addr_len = 0;	157	dev->addr_len = 0;
158	dev->tx_queue_len = 0;	158	dev->tx_queue_len = 0;
@@ -163,7 +163,7 @@ static void vcan_setup(struct net_device *dev) · 4 unmodified lines
163	dev->flags \|= IFF_ECHO;	163	dev->flags \|= IFF_ECHO;
164		164
165	dev->netdev_ops = &vcan_netdev_ops;	165	dev->netdev_ops = &vcan_netdev_ops;
166	dev->destructor = free_netdev;	166	dev->needs_free_netdev = true;
167	}	167	}
168		168
169	static struct rtnl_link_ops vcan_link_ops __read_mostly = {	169	static struct rtnl_link_ops vcan_link_ops __read_mostly = {

drivers/net/can/vxcan.c+2−2

@@ -150,13 +150,13 @@ static const struct net_device_ops vxcan_netdev_ops = { · 149 unmodified lines
150	static void vxcan_setup(struct net_device *dev)	150	static void vxcan_setup(struct net_device *dev)
151	{	151	{
152	dev->type = ARPHRD_CAN;	152	dev->type = ARPHRD_CAN;
153	dev->mtu = CAN_MTU;	153	dev->mtu = CANFD_MTU;
154	dev->hard_header_len = 0;	154	dev->hard_header_len = 0;
155	dev->addr_len = 0;	155	dev->addr_len = 0;
156	dev->tx_queue_len = 0;	156	dev->tx_queue_len = 0;
157	dev->flags = (IFF_NOARP\|IFF_ECHO);	157	dev->flags = (IFF_NOARP\|IFF_ECHO);
158	dev->netdev_ops = &vxcan_netdev_ops;	158	dev->netdev_ops = &vxcan_netdev_ops;
159	dev->destructor = free_netdev;	159	dev->needs_free_netdev = true;
160	}	160	}
161		161
162	/* forward declaration for rtnl_create_link() */	162	/* forward declaration for rtnl_create_link() */

drivers/net/dsa/mv88e6xxx/global2.h+3−3

@@ -114,13 +114,13 @@ static inline int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip, · 113 unmodified lines
114	return -EOPNOTSUPP;	114	return -EOPNOTSUPP;
115	}	115	}
116		116
117	int mv88e6xxx_g2_pvt_write(struct mv88e6xxx_chip *chip, int src_dev,	117	static inline int mv88e6xxx_g2_pvt_write(struct mv88e6xxx_chip *chip,
118	int src_port, u16 data)	118	int src_dev, int src_port, u16 data)
119	{	119	{
120	return -EOPNOTSUPP;	120	return -EOPNOTSUPP;
121	}	121	}
122		122
123	int mv88e6xxx_g2_misc_4_bit_port(struct mv88e6xxx_chip *chip)	123	static inline int mv88e6xxx_g2_misc_4_bit_port(struct mv88e6xxx_chip *chip)
124	{	124	{
125	return -EOPNOTSUPP;	125	return -EOPNOTSUPP;
126	}	126	}

drivers/net/dummy.c+2−2

 	struct dummy_priv *priv = netdev_priv(dev);
 	kfree(priv->vfinfo);
-	free_netdev(dev);
 }
 static void dummy_setup(struct net_device *dev)
 	/* Initialize the device structure. */
 	dev->netdev_ops = &dummy_netdev_ops;
 	dev->ethtool_ops = &dummy_ethtool_ops;
-	dev->destructor = dummy_free_netdev;
+	dev->needs_free_netdev = true;
+	dev->priv_destructor = dummy_free_netdev;
 	/* Fill in device structure with ethernet-generic values. */
 	dev->flags |= IFF_NOARP;

drivers/net/ethernet/amazon/ena/ena_com.c+21−14

 #define ENA_MMIO_READ_TIMEOUT 0xFFFFFFFF
+#define ENA_REGS_ADMIN_INTR_MASK 1
 /*****************************************************************************/
 /*****************************************************************************/
 /*****************************************************************************/
 	tail_masked = admin_queue->sq.tail & queue_size_mask;
 	/* In case of queue FULL */
-	cnt = admin_queue->sq.tail - admin_queue->sq.head;
+	cnt = atomic_read(&admin_queue->outstanding_cmds);
 	if (cnt >= admin_queue->q_depth) {
-		pr_debug("admin queue is FULL (tail %d head %d depth: %d)\n",
+		pr_debug("admin queue is full.\n");
-			 admin_queue->sq.tail, admin_queue->sq.head,
-			 admin_queue->q_depth);
 		admin_queue->stats.out_of_space++;
 		return ERR_PTR(-ENOSPC);
 	}
 static int ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx *comp_ctx,
 						     struct ena_com_admin_queue *admin_queue)
 {
-	unsigned long flags;
+	unsigned long flags, timeout;
-	u32 start_time;
 	int ret;
-	start_time = ((u32)jiffies_to_usecs(jiffies));
+	timeout = jiffies + ADMIN_CMD_TIMEOUT_US;
+	while (1) {
+		spin_lock_irqsave(&admin_queue->q_lock, flags);
+		ena_com_handle_admin_completion(admin_queue);
+		spin_unlock_irqrestore(&admin_queue->q_lock, flags);
+		if (comp_ctx->status != ENA_CMD_SUBMITTED)
+			break;
-	while (comp_ctx->status == ENA_CMD_SUBMITTED) {
+		if (time_is_before_jiffies(timeout)) {
-		if ((((u32)jiffies_to_usecs(jiffies)) - start_time) >
-		    ADMIN_CMD_TIMEOUT_US) {
 			pr_err("Wait for completion (polling) timeout\n");
 			/* ENA didn't have any completion */
 			spin_lock_irqsave(&admin_queue->q_lock, flags);
 			goto err;
 		}
-		spin_lock_irqsave(&admin_queue->q_lock, flags);
-		ena_com_handle_admin_completion(admin_queue);
-		spin_unlock_irqrestore(&admin_queue->q_lock, flags);
 		msleep(100);
 	}
 void ena_com_set_admin_polling_mode(struct ena_com_dev *ena_dev, bool polling)
 {
+	u32 mask_value = 0;
+	if (polling)
+		mask_value = ENA_REGS_ADMIN_INTR_MASK;
+	writel(mask_value, ena_dev->reg_bar + ENA_REGS_INTR_MASK_OFF);
 	ena_dev->admin_queue.polling = polling;
 }

drivers/net/ethernet/amazon/ena/ena_ethtool.c+1−1

 	ENA_STAT_TX_ENTRY(tx_poll),
 	ENA_STAT_TX_ENTRY(doorbells),
 	ENA_STAT_TX_ENTRY(prepare_ctx_err),
-	ENA_STAT_TX_ENTRY(missing_tx_comp),
 	ENA_STAT_TX_ENTRY(bad_req_id),
 };
 	ENA_STAT_RX_ENTRY(dma_mapping_err),
 	ENA_STAT_RX_ENTRY(bad_desc_num),
 	ENA_STAT_RX_ENTRY(rx_copybreak_pkt),
+	ENA_STAT_RX_ENTRY(empty_rx_ring),
 };
 static const struct ena_stats ena_stats_ena_com_strings[] = {

drivers/net/ethernet/amazon/ena/ena_netdev.c+132−47

 		rxr->sgl_size = adapter->max_rx_sgl_size;
 		rxr->smoothed_interval =
 			ena_com_get_nonadaptive_moderation_interval_rx(ena_dev);
+		rxr->empty_rx_queue = 0;
 	}
 }
 	rx_ring->per_napi_bytes = 0;
 }
+static inline void ena_unmask_interrupt(struct ena_ring *tx_ring,
+					struct ena_ring *rx_ring)
+{
+	struct ena_eth_io_intr_reg intr_reg;
+	/* Update intr register: rx intr delay,
+	 * tx intr delay and interrupt unmask
+	 */
+	ena_com_update_intr_reg(&intr_reg,
+				rx_ring->smoothed_interval,
+				tx_ring->smoothed_interval,
+				true);
+	/* It is a shared MSI-X.
+	 * Tx and Rx CQ have pointer to it.
+	 * So we use one of them to reach the intr reg
+	 */
+	ena_com_unmask_intr(rx_ring->ena_com_io_cq, &intr_reg);
+}
 static inline void ena_update_ring_numa_node(struct ena_ring *tx_ring,
 					     struct ena_ring *rx_ring)
 {
 {
 	struct ena_napi *ena_napi = container_of(napi, struct ena_napi, napi);
 	struct ena_ring *tx_ring, *rx_ring;
-	struct ena_eth_io_intr_reg intr_reg;
 	u32 tx_work_done;
 	u32 rx_work_done;
 			if (ena_com_get_adaptive_moderation_enabled(rx_ring->ena_dev))
 				ena_adjust_intr_moderation(rx_ring, tx_ring);
-			/* Update intr register: rx intr delay,
+			ena_unmask_interrupt(tx_ring, rx_ring);
-			 * tx intr delay and interrupt unmask
-			 */
-			ena_com_update_intr_reg(&intr_reg,
-						rx_ring->smoothed_interval,
-						tx_ring->smoothed_interval,
-						true);
-			/* It is a shared MSI-X.
-			 * Tx and Rx CQ have pointer to it.
-			 * So we use one of them to reach the intr reg
-			 */
-			ena_com_unmask_intr(rx_ring->ena_com_io_cq, &intr_reg);
 		}
 		ena_update_ring_numa_node(tx_ring, rx_ring);
 		ret = rx_work_done;
 	ena_napi_enable_all(adapter);
+	/* Enable completion queues interrupt */
+	for (i = 0; i < adapter->num_queues; i++)
+		ena_unmask_interrupt(&adapter->tx_ring[i],
+				     &adapter->rx_ring[i]);
 	/* schedule napi in case we had pending packets
 	 * from the last time we disable napi
 	 */
 			  "Failed to get TX queue handlers. TX queue num %d rc: %d\n",
 			  qid, rc);
 		ena_com_destroy_io_queue(ena_dev, ena_qid);
+		return rc;
 	}
 	ena_com_update_numa_node(tx_ring->ena_com_io_cq, ctx.numa_node);
 			  "Failed to get RX queue handlers. RX queue num %d rc: %d\n",
 			  qid, rc);
 		ena_com_destroy_io_queue(ena_dev, ena_qid);
+		return rc;
 	}
 	ena_com_update_numa_node(rx_ring->ena_com_io_cq, ctx.numa_node);
 	tx_info->tx_descs = nb_hw_desc;
 	tx_info->last_jiffies = jiffies;
+	tx_info->print_once = 0;
 	tx_ring->next_to_use = ENA_TX_RING_IDX_NEXT(next_to_use,
 		tx_ring->ring_size);
 		"Reset attempt failed. Can not reset the device\n");
 }
-static void check_for_missing_tx_completions(struct ena_adapter *adapter)
+static int check_missing_comp_in_queue(struct ena_adapter *adapter,
+				       struct ena_ring *tx_ring)
 {
 	struct ena_tx_buffer *tx_buf;
 	unsigned long last_jiffies;
+	u32 missed_tx = 0;
+	int i;
+	for (i = 0; i < tx_ring->ring_size; i++) {
+		tx_buf = &tx_ring->tx_buffer_info[i];
+		last_jiffies = tx_buf->last_jiffies;
+		if (unlikely(last_jiffies &&
+			     time_is_before_jiffies(last_jiffies + TX_TIMEOUT))) {
+			if (!tx_buf->print_once)
+				netif_notice(adapter, tx_err, adapter->netdev,
+					     "Found a Tx that wasn't completed on time, qid %d, index %d.\n",
+					     tx_ring->qid, i);
+			tx_buf->print_once = 1;
+			missed_tx++;
+			if (unlikely(missed_tx > MAX_NUM_OF_TIMEOUTED_PACKETS)) {
+				netif_err(adapter, tx_err, adapter->netdev,
+					  "The number of lost tx completions is above the threshold (%d > %d). Reset the device\n",
+					  missed_tx, MAX_NUM_OF_TIMEOUTED_PACKETS);
+				set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
+				return -EIO;
+			}
+		}
+	}
+	return 0;
+}
+static void check_for_missing_tx_completions(struct ena_adapter *adapter)
+{
 	struct ena_ring *tx_ring;
-	int i, j, budget;
+	int i, budget, rc;
-	u32 missed_tx;
 	/* Make sure the driver doesn't turn the device in other process */
 	smp_rmb();
 	for (i = adapter->last_monitored_tx_qid; i < adapter->num_queues; i++) {
 		tx_ring = &adapter->tx_ring[i];
-		for (j = 0; j < tx_ring->ring_size; j++) {
+		rc = check_missing_comp_in_queue(adapter, tx_ring);
-			tx_buf = &tx_ring->tx_buffer_info[j];
+		if (unlikely(rc))
-			last_jiffies = tx_buf->last_jiffies;
+			return;
-			if (unlikely(last_jiffies && time_is_before_jiffies(last_jiffies + TX_TIMEOUT))) {
-				netif_notice(adapter, tx_err, adapter->netdev,
-					     "Found a Tx that wasn't completed on time, qid %d, index %d.\n",
-					     tx_ring->qid, j);
-				u64_stats_update_begin(&tx_ring->syncp);
-				missed_tx = tx_ring->tx_stats.missing_tx_comp++;
-				u64_stats_update_end(&tx_ring->syncp);
-				/* Clear last jiffies so the lost buffer won't
-				 * be counted twice.
-				 */
-				tx_buf->last_jiffies = 0;
-				if (unlikely(missed_tx > MAX_NUM_OF_TIMEOUTED_PACKETS)) {
-					netif_err(adapter, tx_err, adapter->netdev,
-						  "The number of lost tx completion is above the threshold (%d > %d). Reset the device\n",
-						  missed_tx, MAX_NUM_OF_TIMEOUTED_PACKETS);
-					set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
-				}
-			}
-		}
 		budget--;
 		if (!budget)
 	adapter->last_monitored_tx_qid = i % adapter->num_queues;
 }
+/* trigger napi schedule after 2 consecutive detections */
+#define EMPTY_RX_REFILL 2
+/* For the rare case where the device runs out of Rx descriptors and the
+ * napi handler failed to refill new Rx descriptors (due to a lack of memory
+ * for example).
+ * This case will lead to a deadlock:
+ * The device won't send interrupts since all the new Rx packets will be dropped
+ * The napi handler won't allocate new Rx descriptors so the device will be
+ * able to send new packets.
+ *
+ * This scenario can happen when the kernel's vm.min_free_kbytes is too small.
+ * It is recommended to have at least 512MB, with a minimum of 128MB for
+ * constrained environment).
+ *
+ * When such a situation is detected - Reschedule napi
+ */
+static void check_for_empty_rx_ring(struct ena_adapter *adapter)
+{
+	struct ena_ring *rx_ring;
+	int i, refill_required;
+	if (!test_bit(ENA_FLAG_DEV_UP, &adapter->flags))
+		return;
+	if (test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))
+		return;
+	for (i = 0; i < adapter->num_queues; i++) {
+		rx_ring = &adapter->rx_ring[i];
+		refill_required =
+			ena_com_sq_empty_space(rx_ring->ena_com_io_sq);
+		if (unlikely(refill_required == (rx_ring->ring_size - 1))) {
+			rx_ring->empty_rx_queue++;
+			if (rx_ring->empty_rx_queue >= EMPTY_RX_REFILL) {
+				u64_stats_update_begin(&rx_ring->syncp);
+				rx_ring->rx_stats.empty_rx_ring++;
+				u64_stats_update_end(&rx_ring->syncp);
+				netif_err(adapter, drv, adapter->netdev,
+					  "trigger refill for ring %d\n", i);
+				napi_schedule(rx_ring->napi);
+				rx_ring->empty_rx_queue = 0;
+			}
+		} else {
+			rx_ring->empty_rx_queue = 0;
+		}
+	}
+}
 /* Check for keep alive expiration */
 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
 {
 	check_for_missing_tx_completions(adapter);
+	check_for_empty_rx_ring(adapter);
 	if (debug_area)
 		ena_dump_stats_to_buf(adapter, debug_area);
 {
 	int release_bars;
+	if (ena_dev->mem_bar)
+		devm_iounmap(&pdev->dev, ena_dev->mem_bar);
+	devm_iounmap(&pdev->dev, ena_dev->reg_bar);
 	release_bars = pci_select_bars(pdev, IORESOURCE_MEM) & ENA_BAR_MASK;
 	pci_release_selected_regions(pdev, release_bars);
 }
 		goto err_free_ena_dev;
 	}
-	ena_dev->reg_bar = ioremap(pci_resource_start(pdev, ENA_REG_BAR),
+	ena_dev->reg_bar = devm_ioremap(&pdev->dev,
-				   pci_resource_len(pdev, ENA_REG_BAR));
+					pci_resource_start(pdev, ENA_REG_BAR),
+					pci_resource_len(pdev, ENA_REG_BAR));
 	if (!ena_dev->reg_bar) {
 		dev_err(&pdev->dev, "failed to remap regs bar\n");
 		rc = -EFAULT;
 	ena_set_push_mode(pdev, ena_dev, &get_feat_ctx);
 	if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
-		ena_dev->mem_bar = ioremap_wc(pci_resource_start(pdev, ENA_MEM_BAR),
+		ena_dev->mem_bar = devm_ioremap_wc(&pdev->dev,
-					      pci_resource_len(pdev, ENA_MEM_BAR));
+						   pci_resource_start(pdev, ENA_MEM_BAR),
+						   pci_resource_len(pdev, ENA_MEM_BAR));
 		if (!ena_dev->mem_bar) {
 			rc = -EFAULT;
 			goto err_device_destroy;

drivers/net/ethernet/amazon/ena/ena_netdev.h+15−3

@@ -45,7 +45,7 @@ · 44 unmodified lines
45		45
46	#define DRV_MODULE_VER_MAJOR 1	46	#define DRV_MODULE_VER_MAJOR 1
47	#define DRV_MODULE_VER_MINOR 1	47	#define DRV_MODULE_VER_MINOR 1
48	#define DRV_MODULE_VER_SUBMINOR 2	48	#define DRV_MODULE_VER_SUBMINOR 7
49		49
50	#define DRV_MODULE_NAME "ena"	50	#define DRV_MODULE_NAME "ena"
51	#ifndef DRV_MODULE_VERSION	51	#ifndef DRV_MODULE_VERSION
@@ -146,7 +146,18 @@ struct ena_tx_buffer { · 94 unmodified lines
146	u32 tx_descs;	146	u32 tx_descs;
147	/* num of buffers used by this skb */	147	/* num of buffers used by this skb */
148	u32 num_of_bufs;	148	u32 num_of_bufs;
149	/* Save the last jiffies to detect missing tx packets */	149
		150	/* Used for detect missing tx packets to limit the number of prints */
		151	u32 print_once;
		152	/* Save the last jiffies to detect missing tx packets
		153	*
		154	* sets to non zero value on ena_start_xmit and set to zero on
		155	* napi and timer_Service_routine.
		156	*
		157	* while this value is not protected by lock,
		158	* a given packet is not expected to be handled by ena_start_xmit
		159	* and by napi/timer_service at the same time.
		160	*/
150	unsigned long last_jiffies;	161	unsigned long last_jiffies;
151	struct ena_com_buf bufs[ENA_PKT_MAX_BUFS];	162	struct ena_com_buf bufs[ENA_PKT_MAX_BUFS];
152	} ____cacheline_aligned;	163	} ____cacheline_aligned;
@@ -170,7 +181,6 @@ struct ena_stats_tx { · 17 unmodified lines
170	u64 napi_comp;	181	u64 napi_comp;
171	u64 tx_poll;	182	u64 tx_poll;
172	u64 doorbells;	183	u64 doorbells;
173	u64 missing_tx_comp;
174	u64 bad_req_id;	184	u64 bad_req_id;
175	};	185	};
176		186
@@ -184,6 +194,7 @@ struct ena_stats_rx { · 7 unmodified lines
184	u64 dma_mapping_err;	194	u64 dma_mapping_err;
185	u64 bad_desc_num;	195	u64 bad_desc_num;
186	u64 rx_copybreak_pkt;	196	u64 rx_copybreak_pkt;
		197	u64 empty_rx_ring;
187	};	198	};
188		199
189	struct ena_ring {	200	struct ena_ring {
@@ -231,6 +242,7 @@ struct ena_ring { · 41 unmodified lines
231	struct ena_stats_tx tx_stats;	242	struct ena_stats_tx tx_stats;
232	struct ena_stats_rx rx_stats;	243	struct ena_stats_rx rx_stats;
233	};	244	};
		245	int empty_rx_queue;
234	} ____cacheline_aligned;	246	} ____cacheline_aligned;
235		247
236	struct ena_stats_dev {	248	struct ena_stats_dev {

drivers/net/ethernet/amd/xgbe/xgbe-desc.c+2−3

 			      struct xgbe_ring *ring,
 			      struct xgbe_ring_data *rdata)
 {
-	int order, ret;
+	int ret;
 	if (!ring->rx_hdr_pa.pages) {
 		ret = xgbe_alloc_pages(pdata, &ring->rx_hdr_pa, GFP_ATOMIC, 0);
 	}
 	if (!ring->rx_buf_pa.pages) {
-		order = max_t(int, PAGE_ALLOC_COSTLY_ORDER - 1, 0);
 		ret = xgbe_alloc_pages(pdata, &ring->rx_buf_pa, GFP_ATOMIC,
-				       order);
+				       PAGE_ALLOC_COSTLY_ORDER);
 		if (ret)
 			return ret;
 	}

drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h+0−3

@@ -193,9 +193,6 @@ int hw_atl_utils_hw_get_regs(struct aq_hw_s *self, · 192 unmodified lines
193	struct aq_hw_caps_s *aq_hw_caps,	193	struct aq_hw_caps_s *aq_hw_caps,
194	u32 *regs_buff);	194	u32 *regs_buff);
195		195
196	int hw_atl_utils_hw_get_settings(struct aq_hw_s *self,
197	struct ethtool_cmd *cmd);
198
199	int hw_atl_utils_hw_set_power(struct aq_hw_s *self,	196	int hw_atl_utils_hw_set_power(struct aq_hw_s *self,
200	unsigned int power_state);	197	unsigned int power_state);
201		198

drivers/net/ethernet/broadcom/bcmsysport.c+5−2

 	priv->num_rx_desc_words = params->num_rx_desc_words;
 	priv->irq0 = platform_get_irq(pdev, 0);
-	if (!priv->is_lite)
+	if (!priv->is_lite) {
 		priv->irq1 = platform_get_irq(pdev, 1);
-	priv->wol_irq = platform_get_irq(pdev, 2);
+		priv->wol_irq = platform_get_irq(pdev, 2);
+	} else {
+		priv->wol_irq = platform_get_irq(pdev, 1);
+	}
 	if (priv->irq0 <= 0 || (priv->irq1 <= 0 && !priv->is_lite)) {
 		dev_err(&pdev->dev, "invalid interrupts\n");
 		ret = -EINVAL;

drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c+16−5

 	}
 	/* select a non-FCoE queue */
-	return fallback(dev, skb) % BNX2X_NUM_ETH_QUEUES(bp);
+	return fallback(dev, skb) % (BNX2X_NUM_ETH_QUEUES(bp) * bp->max_cos);
 }
 void bnx2x_set_num_queues(struct bnx2x *bp)
 		/* when transmitting in a vf, start bd must hold the ethertype
 		 * for fw to enforce it
 		 */
+		u16 vlan_tci = 0;
 #ifndef BNX2X_STOP_ON_ERROR
-		if (IS_VF(bp))
+		if (IS_VF(bp)) {
 #endif
-			tx_start_bd->vlan_or_ethertype =
+			/* Still need to consider inband vlan for enforced */
-				cpu_to_le16(ntohs(eth->h_proto));
+			if (__vlan_get_tag(skb, &vlan_tci)) {
+				tx_start_bd->vlan_or_ethertype =
+					cpu_to_le16(ntohs(eth->h_proto));
+			} else {
+				tx_start_bd->bd_flags.as_bitfield |=
+					(X_ETH_INBAND_VLAN <<
+					 ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT);
+				tx_start_bd->vlan_or_ethertype =
+					cpu_to_le16(vlan_tci);
+			}
 #ifndef BNX2X_STOP_ON_ERROR
-		else
+		} else {
 			/* used by FW for packet accounting */
 			tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
+		}
 #endif
 	}

drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c+13−2

 	/* release VF resources */
 	bnx2x_vf_free_resc(bp, vf);
+	vf->malicious = false;
 	/* re-open the mailbox */
 	bnx2x_vf_enable_mbx(bp, vf->abs_vfid);
 	return;
 		   vf->abs_vfid, qidx);
 		bnx2x_vf_handle_rss_update_eqe(bp, vf);
 	case EVENT_RING_OPCODE_VF_FLR:
-	case EVENT_RING_OPCODE_MALICIOUS_VF:
 		/* Do nothing for now */
 		return 0;
+	case EVENT_RING_OPCODE_MALICIOUS_VF:
+		vf->malicious = true;
+		return 0;
 	}
 	return 0;
 			continue;
 		}
+		if (vf->malicious) {
+			DP_AND((BNX2X_MSG_IOV | BNX2X_MSG_STATS),
+			       "vf %d malicious so no stats for it\n",
+			       vf->abs_vfid);
+			continue;
+		}
 		DP_AND((BNX2X_MSG_IOV | BNX2X_MSG_STATS),
 		       "add addresses for vf %d\n", vf->abs_vfid);
 		for_each_vfq(vf, j) {
 {
 	BNX2X_PCI_FREE(bp->vf2pf_mbox, bp->vf2pf_mbox_mapping,
 		       sizeof(struct bnx2x_vf_mbx_msg));
-	BNX2X_PCI_FREE(bp->vf2pf_mbox, bp->pf2vf_bulletin_mapping,
+	BNX2X_PCI_FREE(bp->pf2vf_bulletin, bp->pf2vf_bulletin_mapping,
 		       sizeof(union pf_vf_bulletin));
 }

drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.h+1−0

@@ -141,6 +141,7 @@ struct bnx2x_virtf { · 140 unmodified lines
141	#define VF_RESET 3 /* VF FLR'd, pending cleanup */	141	#define VF_RESET 3 /* VF FLR'd, pending cleanup */
142		142
143	bool flr_clnup_stage; /* true during flr cleanup */	143	bool flr_clnup_stage; /* true during flr cleanup */
		144	bool malicious; /* true if FW indicated so, until FLR */
144		145
145	/* dma */	146	/* dma */
146	dma_addr_t fw_stat_map;	147	dma_addr_t fw_stat_map;

drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c+18−9

@@ -2196,10 +2196,14 @@ static int cxgb_up(struct adapter *adap) · 2195 unmodified lines
2196	if (err)	2196	if (err)
2197	goto irq_err;	2197	goto irq_err;
2198	}	2198	}
		2199
		2200	mutex_lock(&uld_mutex);
2199	enable_rx(adap);	2201	enable_rx(adap);
2200	t4_sge_start(adap);	2202	t4_sge_start(adap);
2201	t4_intr_enable(adap);	2203	t4_intr_enable(adap);
2202	adap->flags \|= FULL_INIT_DONE;	2204	adap->flags \|= FULL_INIT_DONE;
		2205	mutex_unlock(&uld_mutex);
		2206
2203	notify_ulds(adap, CXGB4_STATE_UP);	2207	notify_ulds(adap, CXGB4_STATE_UP);
2204	#if IS_ENABLED(CONFIG_IPV6)	2208	#if IS_ENABLED(CONFIG_IPV6)
2205	update_clip(adap);	2209	update_clip(adap);
@@ -2771,6 +2775,9 @@ void t4_fatal_err(struct adapter *adap) · 565 unmodified lines
2771	{	2775	{
2772	int port;	2776	int port;
2773		2777
		2778	if (pci_channel_offline(adap->pdev))
		2779	return;
		2780
2774	/* Disable the SGE since ULDs are going to free resources that	2781	/* Disable the SGE since ULDs are going to free resources that
2775	* could be exposed to the adapter. RDMA MWs for example...	2782	* could be exposed to the adapter. RDMA MWs for example...
2776	*/	2783	*/
@@ -3882,9 +3889,10 @@ static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev, · 1105 unmodified lines
3882	spin_lock(&adap->stats_lock);	3889	spin_lock(&adap->stats_lock);
3883	for_each_port(adap, i) {	3890	for_each_port(adap, i) {
3884	struct net_device *dev = adap->port[i];	3891	struct net_device *dev = adap->port[i];
3885		3892	if (dev) {
3886	netif_device_detach(dev);	3893	netif_device_detach(dev);
3887	netif_carrier_off(dev);	3894	netif_carrier_off(dev);
		3895	}
3888	}	3896	}
3889	spin_unlock(&adap->stats_lock);	3897	spin_unlock(&adap->stats_lock);
3890	disable_interrupts(adap);	3898	disable_interrupts(adap);
@@ -3963,12 +3971,13 @@ static void eeh_resume(struct pci_dev *pdev) · 72 unmodified lines
3963	rtnl_lock();	3971	rtnl_lock();
3964	for_each_port(adap, i) {	3972	for_each_port(adap, i) {
3965	struct net_device *dev = adap->port[i];	3973	struct net_device *dev = adap->port[i];
3966		3974	if (dev) {
3967	if (netif_running(dev)) {	3975	if (netif_running(dev)) {
3968	link_start(dev);	3976	link_start(dev);
3969	cxgb_set_rxmode(dev);	3977	cxgb_set_rxmode(dev);
		3978	}
		3979	netif_device_attach(dev);
3970	}	3980	}
3971	netif_device_attach(dev);
3972	}	3981	}
3973	rtnl_unlock();	3982	rtnl_unlock();
3974	}	3983	}
@@ -4516,7 +4525,7 @@ static void dummy_setup(struct net_device *dev) · 541 unmodified lines
4516	/* Initialize the device structure. */	4525	/* Initialize the device structure. */
4517	dev->netdev_ops = &cxgb4_mgmt_netdev_ops;	4526	dev->netdev_ops = &cxgb4_mgmt_netdev_ops;
4518	dev->ethtool_ops = &cxgb4_mgmt_ethtool_ops;	4527	dev->ethtool_ops = &cxgb4_mgmt_ethtool_ops;
4519	dev->destructor = free_netdev;	4528	dev->needs_free_netdev = true;
4520	}	4529	}
4521		4530
4522	static int config_mgmt_dev(struct pci_dev *pdev)	4531	static int config_mgmt_dev(struct pci_dev *pdev)

drivers/net/ethernet/chelsio/cxgb4/t4_hw.c+7−2

@@ -4557,8 +4557,13 @@ void t4_intr_enable(struct adapter *adapter) · 4556 unmodified lines
4557	*/	4557	*/
4558	void t4_intr_disable(struct adapter *adapter)	4558	void t4_intr_disable(struct adapter *adapter)
4559	{	4559	{
4560	u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A);	4560	u32 whoami, pf;
4561	u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?	4561
		4562	if (pci_channel_offline(adapter->pdev))
		4563	return;
		4564
		4565	whoami = t4_read_reg(adapter, PL_WHOAMI_A);
		4566	pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
4562	SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);	4567	SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4563		4568
4564	t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), 0);	4569	t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), 0);

drivers/net/ethernet/chelsio/cxgb4/t4fw_version.h+3−3

drivers/net/ethernet/ethoc.c+2−1

 	if (ret)
 		return ret;
+	napi_enable(&priv->napi);
 	ethoc_init_ring(priv, dev->mem_start);
 	ethoc_reset(priv);
 	priv->old_duplex = -1;
 	phy_start(dev->phydev);
-	napi_enable(&priv->napi);
 	if (netif_msg_ifup(priv)) {
 		dev_info(&dev->dev, "I/O: %08lx Memory: %08lx-%08lx\n",

drivers/net/ethernet/freescale/fsl_pq_mdio.c+8−1

 {
 	const struct of_device_id *id =
 		of_match_device(fsl_pq_mdio_match, &pdev->dev);
-	const struct fsl_pq_mdio_data *data = id->data;
+	const struct fsl_pq_mdio_data *data;
 	struct device_node *np = pdev->dev.of_node;
 	struct resource res;
 	struct device_node *tbi;
 	struct mii_bus *new_bus;
 	int err;
+	if (!id) {
+		dev_err(&pdev->dev, "Failed to match device\n");
+		return -ENODEV;
+	}
+	data = id->data;
 	dev_dbg(&pdev->dev, "found %s compatible node\n", id->compatible);
 	new_bus = mdiobus_alloc_size(sizeof(*priv));

drivers/net/ethernet/ibm/emac/core.c+40−27

 {
 	struct emac_regs __iomem *p = dev->emacp;
 	int n = 20;
+	bool __maybe_unused try_internal_clock = false;
 	DBG(dev, "reset" NL);
 	}
 #ifdef CONFIG_PPC_DCR_NATIVE
+do_retry:
 	/*
 	 * PPC460EX/GT Embedded Processor Advanced User's Manual
 	 * section 28.10.1 Mode Register 0 (EMACx_MR0) states:
 	 * of the EMAC. If none is present, select the internal clock
 	 * (SDR0_ETH_CFG[EMACx_PHY_CLK] = 1).
 	 * After a soft reset, select the external clock.
+	 *
+	 * The AR8035-A PHY Meraki MR24 does not provide a TX Clk if the
+	 * ethernet cable is not attached. This causes the reset to timeout
+	 * and the PHY detection code in emac_init_phy() is unable to
+	 * communicate and detect the AR8035-A PHY. As a result, the emac
+	 * driver bails out early and the user has no ethernet.
+	 * In order to stay compatible with existing configurations, the
+	 * driver will temporarily switch to the internal clock, after
+	 * the first reset fails.
 	 */
 	if (emac_has_feature(dev, EMAC_FTR_460EX_PHY_CLK_FIX)) {
-		if (dev->phy_address == 0xffffffff &&
+		if (try_internal_clock || (dev->phy_address == 0xffffffff &&
-		    dev->phy_map == 0xffffffff) {
+					   dev->phy_map == 0xffffffff)) {
 			/* No PHY: select internal loop clock before reset */
 			dcri_clrset(SDR0, SDR0_ETH_CFG,
 				    0, SDR0_ETH_CFG_ECS << dev->cell_index);
 #ifdef CONFIG_PPC_DCR_NATIVE
 	if (emac_has_feature(dev, EMAC_FTR_460EX_PHY_CLK_FIX)) {
-		if (dev->phy_address == 0xffffffff &&
+		if (!n && !try_internal_clock) {
-		    dev->phy_map == 0xffffffff) {
+			/* first attempt has timed out. */
+			n = 20;
+			try_internal_clock = true;
+			goto do_retry;
+		}
+		if (try_internal_clock || (dev->phy_address == 0xffffffff &&
+					   dev->phy_map == 0xffffffff)) {
 			/* No PHY: restore external clock source after reset */
 			dcri_clrset(SDR0, SDR0_ETH_CFG,
 				    SDR0_ETH_CFG_ECS << dev->cell_index, 0);
 	return emac_reset(dev);
 }
+static int emac_mdio_phy_start_aneg(struct mii_phy *phy,
+				    struct phy_device *phy_dev)
+{
+	phy_dev->autoneg = phy->autoneg;
+	phy_dev->speed = phy->speed;
+	phy_dev->duplex = phy->duplex;
+	phy_dev->advertising = phy->advertising;
+	return phy_start_aneg(phy_dev);
+}
 static int emac_mdio_setup_aneg(struct mii_phy *phy, u32 advertise)
 {
 	struct net_device *ndev = phy->dev;
 	struct emac_instance *dev = netdev_priv(ndev);
-	dev->phy.autoneg = AUTONEG_ENABLE;
-	dev->phy.speed = SPEED_1000;
-	dev->phy.duplex = DUPLEX_FULL;
-	dev->phy.advertising = advertise;
 	phy->autoneg = AUTONEG_ENABLE;
-	phy->speed = dev->phy.speed;
-	phy->duplex = dev->phy.duplex;
 	phy->advertising = advertise;
-	return phy_start_aneg(dev->phy_dev);
+	return emac_mdio_phy_start_aneg(phy, dev->phy_dev);
 }
 static int emac_mdio_setup_forced(struct mii_phy *phy, int speed, int fd)
 	struct net_device *ndev = phy->dev;
 	struct emac_instance *dev = netdev_priv(ndev);
-	dev->phy.autoneg =  AUTONEG_DISABLE;
-	dev->phy.speed = speed;
-	dev->phy.duplex = fd;
 	phy->autoneg = AUTONEG_DISABLE;
 	phy->speed = speed;
 	phy->duplex = fd;
-	return phy_start_aneg(dev->phy_dev);
+	return emac_mdio_phy_start_aneg(phy, dev->phy_dev);
 }
 static int emac_mdio_poll_link(struct mii_phy *phy)
 {
 	struct net_device *ndev = phy->dev;
 	struct emac_instance *dev = netdev_priv(ndev);
+	struct phy_device *phy_dev = dev->phy_dev;
 	int res;
-	res = phy_read_status(dev->phy_dev);
+	res = phy_read_status(phy_dev);
 	if (res)
 		return res;
-	dev->phy.speed = phy->speed;
+	phy->speed = phy_dev->speed;
-	dev->phy.duplex = phy->duplex;
+	phy->duplex = phy_dev->duplex;
-	dev->phy.pause = phy->pause;
+	phy->pause = phy_dev->pause;
-	dev->phy.asym_pause = phy->asym_pause;
+	phy->asym_pause = phy_dev->asym_pause;
 	return 0;
 }
 	struct emac_instance *dev = netdev_priv(ndev);
 	phy_start(dev->phy_dev);
-	dev->phy.autoneg = phy->autoneg;
-	dev->phy.speed = phy->speed;
-	dev->phy.duplex = phy->duplex;
-	dev->phy.advertising = phy->advertising;
-	dev->phy.pause = phy->pause;
-	dev->phy.asym_pause = phy->asym_pause;
 	return phy_init_hw(dev->phy_dev);
 }

drivers/net/ethernet/ibm/ibmvnic.c+7−1

 static const char ibmvnic_driver_name[] = "ibmvnic";
 static const char ibmvnic_driver_string[] = "IBM System i/p Virtual NIC Driver";
-MODULE_AUTHOR("Santiago Leon <santi_leon@yahoo.com>");
+MODULE_AUTHOR("Santiago Leon");
 MODULE_DESCRIPTION("IBM System i/p Virtual NIC Driver");
 MODULE_LICENSE("GPL");
 MODULE_VERSION(IBMVNIC_DRIVER_VERSION);
 }
 #endif
+static int ibmvnic_change_mtu(struct net_device *netdev, int new_mtu)
+{
+	return -EOPNOTSUPP;
+}
 static const struct net_device_ops ibmvnic_netdev_ops = {
 	.ndo_open		= ibmvnic_open,
 	.ndo_stop		= ibmvnic_close,
 #ifdef CONFIG_NET_POLL_CONTROLLER
 	.ndo_poll_controller	= ibmvnic_netpoll_controller,
 #endif
+	.ndo_change_mtu		= ibmvnic_change_mtu,
 };
 /* ethtool functions */

drivers/net/ethernet/intel/i40e/i40e.h+1−0

@@ -399,6 +399,7 @@ struct i40e_pf { · 398 unmodified lines
399	#define I40E_FLAG_RX_CSUM_ENABLED BIT_ULL(1)	399	#define I40E_FLAG_RX_CSUM_ENABLED BIT_ULL(1)
400	#define I40E_FLAG_MSI_ENABLED BIT_ULL(2)	400	#define I40E_FLAG_MSI_ENABLED BIT_ULL(2)
401	#define I40E_FLAG_MSIX_ENABLED BIT_ULL(3)	401	#define I40E_FLAG_MSIX_ENABLED BIT_ULL(3)
		402	#define I40E_FLAG_HW_ATR_EVICT_ENABLED BIT_ULL(4)
402	#define I40E_FLAG_RSS_ENABLED BIT_ULL(6)	403	#define I40E_FLAG_RSS_ENABLED BIT_ULL(6)
403	#define I40E_FLAG_VMDQ_ENABLED BIT_ULL(7)	404	#define I40E_FLAG_VMDQ_ENABLED BIT_ULL(7)
404	#define I40E_FLAG_IWARP_ENABLED BIT_ULL(10)	405	#define I40E_FLAG_IWARP_ENABLED BIT_ULL(10)

drivers/net/ethernet/intel/i40e/i40e_ethtool.c+2−2

@@ -224,7 +224,7 @@ static const struct i40e_priv_flags i40e_gstrings_priv_flags[] = { · 223 unmodified lines
224	I40E_PRIV_FLAG("LinkPolling", I40E_FLAG_LINK_POLLING_ENABLED, 0),	224	I40E_PRIV_FLAG("LinkPolling", I40E_FLAG_LINK_POLLING_ENABLED, 0),
225	I40E_PRIV_FLAG("flow-director-atr", I40E_FLAG_FD_ATR_ENABLED, 0),	225	I40E_PRIV_FLAG("flow-director-atr", I40E_FLAG_FD_ATR_ENABLED, 0),
226	I40E_PRIV_FLAG("veb-stats", I40E_FLAG_VEB_STATS_ENABLED, 0),	226	I40E_PRIV_FLAG("veb-stats", I40E_FLAG_VEB_STATS_ENABLED, 0),
227	I40E_PRIV_FLAG("hw-atr-eviction", I40E_FLAG_HW_ATR_EVICT_CAPABLE, 0),	227	I40E_PRIV_FLAG("hw-atr-eviction", I40E_FLAG_HW_ATR_EVICT_ENABLED, 0),
228	I40E_PRIV_FLAG("legacy-rx", I40E_FLAG_LEGACY_RX, 0),	228	I40E_PRIV_FLAG("legacy-rx", I40E_FLAG_LEGACY_RX, 0),
229	};	229	};
230		230
@@ -4092,7 +4092,7 @@ flags_complete: · 3861 unmodified lines
4092		4092
4093	/* Only allow ATR evict on hardware that is capable of handling it */	4093	/* Only allow ATR evict on hardware that is capable of handling it */
4094	if (pf->flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE)	4094	if (pf->flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE)
4095	pf->flags &= ~I40E_FLAG_HW_ATR_EVICT_CAPABLE;	4095	pf->flags &= ~I40E_FLAG_HW_ATR_EVICT_ENABLED;
4096		4096
4097	if (changed_flags & I40E_FLAG_TRUE_PROMISC_SUPPORT) {	4097	if (changed_flags & I40E_FLAG_TRUE_PROMISC_SUPPORT) {
4098	u16 sw_flags = 0, valid_flags = 0;	4098	u16 sw_flags = 0, valid_flags = 0;

drivers/net/ethernet/intel/i40e/i40e_main.c+22−21

  **/
 void i40e_service_event_schedule(struct i40e_pf *pf)
 {
-	if (!test_bit(__I40E_VSI_DOWN, pf->state) &&
+	if (!test_bit(__I40E_DOWN, pf->state) &&
 	    !test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state))
 		queue_work(i40e_wq, &pf->service_task);
 }
 		 * this is not a performance path and napi_schedule()
 		 * can deal with rescheduling.
 		 */
-		if (!test_bit(__I40E_VSI_DOWN, pf->state))
+		if (!test_bit(__I40E_DOWN, pf->state))
 			napi_schedule_irqoff(&q_vector->napi);
 	}
 enable_intr:
 	/* re-enable interrupt causes */
 	wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
-	if (!test_bit(__I40E_VSI_DOWN, pf->state)) {
+	if (!test_bit(__I40E_DOWN, pf->state)) {
 		i40e_service_event_schedule(pf);
 		i40e_irq_dynamic_enable_icr0(pf, false);
 	}
 {
 	/* if interface is down do nothing */
-	if (test_bit(__I40E_VSI_DOWN, pf->state))
+	if (test_bit(__I40E_DOWN, pf->state))
 		return;
 	if (test_bit(__I40E_FD_FLUSH_REQUESTED, pf->state))
 	int i;
 	/* if interface is down do nothing */
-	if (test_bit(__I40E_VSI_DOWN, pf->state) ||
+	if (test_bit(__I40E_DOWN, pf->state) ||
 	    test_bit(__I40E_CONFIG_BUSY, pf->state))
 		return;
 		reset_flags |= BIT(__I40E_GLOBAL_RESET_REQUESTED);
 		clear_bit(__I40E_GLOBAL_RESET_REQUESTED, pf->state);
 	}
-	if (test_bit(__I40E_VSI_DOWN_REQUESTED, pf->state)) {
+	if (test_bit(__I40E_DOWN_REQUESTED, pf->state)) {
-		reset_flags |= BIT(__I40E_VSI_DOWN_REQUESTED);
+		reset_flags |= BIT(__I40E_DOWN_REQUESTED);
-		clear_bit(__I40E_VSI_DOWN_REQUESTED, pf->state);
+		clear_bit(__I40E_DOWN_REQUESTED, pf->state);
 	}
 	/* If there's a recovery already waiting, it takes
 	/* If we're already down or resetting, just bail */
 	if (reset_flags &&
-	    !test_bit(__I40E_VSI_DOWN, pf->state) &&
+	    !test_bit(__I40E_DOWN, pf->state) &&
 	    !test_bit(__I40E_CONFIG_BUSY, pf->state)) {
 		rtnl_lock();
 		i40e_do_reset(pf, reset_flags, true);
 	u32 val;
 	int v;
-	if (test_bit(__I40E_VSI_DOWN, pf->state))
+	if (test_bit(__I40E_DOWN, pf->state))
 		goto clear_recovery;
 	dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n");
 		    (pf->hw.aq.api_min_ver > 4))) {
 		/* Supported in FW API version higher than 1.4 */
 		pf->flags |= I40E_FLAG_GENEVE_OFFLOAD_CAPABLE;
-		pf->flags = I40E_FLAG_HW_ATR_EVICT_CAPABLE;
-	} else {
-		pf->flags = I40E_FLAG_HW_ATR_EVICT_CAPABLE;
 	}
+	/* Enable HW ATR eviction if possible */
+	if (pf->flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE)
+		pf->flags |= I40E_FLAG_HW_ATR_EVICT_ENABLED;
 	pf->eeprom_version = 0xDEAD;
 	pf->lan_veb = I40E_NO_VEB;
 	pf->lan_vsi = I40E_NO_VSI;
 		return -ENODEV;
 	}
 	if (vsi == pf->vsi[pf->lan_vsi] &&
-	    !test_bit(__I40E_VSI_DOWN, pf->state)) {
+	    !test_bit(__I40E_DOWN, pf->state)) {
 		dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
 		return -ENODEV;
 	}
 	}
 	pf->next_vsi = 0;
 	pf->pdev = pdev;
-	set_bit(__I40E_VSI_DOWN, pf->state);
+	set_bit(__I40E_DOWN, pf->state);
 	hw = &pf->hw;
 	hw->back = pf;
 	 * before setting up the misc vector or we get a race and the vector
 	 * ends up disabled forever.
 	 */
-	clear_bit(__I40E_VSI_DOWN, pf->state);
+	clear_bit(__I40E_DOWN, pf->state);
 	/* In case of MSIX we are going to setup the misc vector right here
 	 * to handle admin queue events etc. In case of legacy and MSI
 	/* Unwind what we've done if something failed in the setup */
 err_vsis:
-	set_bit(__I40E_VSI_DOWN, pf->state);
+	set_bit(__I40E_DOWN, pf->state);
 	i40e_clear_interrupt_scheme(pf);
 	kfree(pf->vsi);
 err_switch_setup:
 	/* no more scheduling of any task */
 	set_bit(__I40E_SUSPENDED, pf->state);
-	set_bit(__I40E_VSI_DOWN, pf->state);
+	set_bit(__I40E_DOWN, pf->state);
 	if (pf->service_timer.data)
 		del_timer_sync(&pf->service_timer);
 	if (pf->service_task.func)
 	struct i40e_hw *hw = &pf->hw;
 	set_bit(__I40E_SUSPENDED, pf->state);
-	set_bit(__I40E_VSI_DOWN, pf->state);
+	set_bit(__I40E_DOWN, pf->state);
 	rtnl_lock();
 	i40e_prep_for_reset(pf, true);
 	rtnl_unlock();
 	int retval = 0;
 	set_bit(__I40E_SUSPENDED, pf->state);
-	set_bit(__I40E_VSI_DOWN, pf->state);
+	set_bit(__I40E_DOWN, pf->state);
 	if (pf->wol_en && (pf->flags & I40E_FLAG_WOL_MC_MAGIC_PKT_WAKE))
 		i40e_enable_mc_magic_wake(pf);
 	/* handling the reset will rebuild the device state */
 	if (test_and_clear_bit(__I40E_SUSPENDED, pf->state)) {
-		clear_bit(__I40E_VSI_DOWN, pf->state);
+		clear_bit(__I40E_DOWN, pf->state);
 		rtnl_lock();
 		i40e_reset_and_rebuild(pf, false, true);
 		rtnl_unlock();

drivers/net/ethernet/intel/i40e/i40e_txrx.c+4−3

 #if (PAGE_SIZE < 8192)
 	unsigned int truesize = i40e_rx_pg_size(rx_ring) / 2;
 #else
-	unsigned int truesize = SKB_DATA_ALIGN(size);
+	unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
+				SKB_DATA_ALIGN(I40E_SKB_PAD + size);
 #endif
 	struct sk_buff *skb;
 	/* Due to lack of space, no more new filters can be programmed */
 	if (th->syn && (pf->flags & I40E_FLAG_FD_ATR_AUTO_DISABLED))
 		return;
-	if (pf->flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE) {
+	if (pf->flags & I40E_FLAG_HW_ATR_EVICT_ENABLED) {
 		/* HW ATR eviction will take care of removing filters on FIN
 		 * and RST packets.
 		 */
 			I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
 			I40E_TXD_FLTR_QW1_CNTINDEX_MASK;
-	if (pf->flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE)
+	if (pf->flags & I40E_FLAG_HW_ATR_EVICT_ENABLED)
 		dtype_cmd |= I40E_TXD_FLTR_QW1_ATR_MASK;
 	fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype);

drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c+2−0

 					   VLAN_VID_MASK));
 	}
+	spin_unlock_bh(&vsi->mac_filter_hash_lock);
 	if (vlan_id || qos)
 		ret = i40e_vsi_add_pvid(vsi, vlanprio);
 	else
 		i40e_vsi_remove_pvid(vsi);
+	spin_lock_bh(&vsi->mac_filter_hash_lock);
 	if (vlan_id) {
 		dev_info(&pf->pdev->dev, "Setting VLAN %d, QOS 0x%x on VF %d\n",

drivers/net/ethernet/intel/i40evf/i40e_txrx.c+2−1

@@ -1190,7 +1190,8 @@ static struct sk_buff i40e_build_skb(struct i40e_ring rx_ring, · 1189 unmodified lines
1190	#if (PAGE_SIZE < 8192)	1190	#if (PAGE_SIZE < 8192)
1191	unsigned int truesize = i40e_rx_pg_size(rx_ring) / 2;	1191	unsigned int truesize = i40e_rx_pg_size(rx_ring) / 2;
1192	#else	1192	#else
1193	unsigned int truesize = SKB_DATA_ALIGN(size);	1193	unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
		1194	SKB_DATA_ALIGN(I40E_SKB_PAD + size);
1194	#endif	1195	#endif
1195	struct sk_buff *skb;	1196	struct sk_buff *skb;
1196		1197

drivers/net/ethernet/marvell/mvpp2.c+33−43

 				    dma_addr_t *dma_addr,
 				    phys_addr_t *phys_addr)
 {
-	int cpu = smp_processor_id();
+	int cpu = get_cpu();
 	*dma_addr = mvpp2_percpu_read(priv, cpu,
 				      MVPP2_BM_PHY_ALLOC_REG(bm_pool->id));
 		if (sizeof(phys_addr_t) == 8)
 			*phys_addr |= (u64)phys_addr_highbits << 32;
 	}
+	put_cpu();
 }
 /* Free all buffers from the pool */
 	return bm;
 }
-/* Get pool number from a BM cookie */
-static inline int mvpp2_bm_cookie_pool_get(unsigned long cookie)
-{
-	return (cookie >> MVPP2_BM_COOKIE_POOL_OFFS) & 0xFF;
-}
 /* Release buffer to BM */
 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
 				     dma_addr_t buf_dma_addr,
 				     phys_addr_t buf_phys_addr)
 {
-	int cpu = smp_processor_id();
+	int cpu = get_cpu();
 	if (port->priv->hw_version == MVPP22) {
 		u32 val = 0;
 			   MVPP2_BM_VIRT_RLS_REG, buf_phys_addr);
 	mvpp2_percpu_write(port->priv, cpu,
 			   MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr);
+	put_cpu();
 }
 /* Refill BM pool */
-static void mvpp2_pool_refill(struct mvpp2_port *port, u32 bm,
+static void mvpp2_pool_refill(struct mvpp2_port *port, int pool,
 			      dma_addr_t dma_addr,
 			      phys_addr_t phys_addr)
 {
-	int pool = mvpp2_bm_cookie_pool_get(bm);
 	mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
 }
 {
 	u32 val;
-	return;
 	/* Only GOP port 0 has an XLG MAC */
 	if (port->gop_id == 0) {
 		val = readl(port->base + MVPP22_XLG_CTRL3_REG);
 	mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
 }
-/* Obtain BM cookie information from descriptor */
-static u32 mvpp2_bm_cookie_build(struct mvpp2_port *port,
-				 struct mvpp2_rx_desc *rx_desc)
-{
-	int cpu = smp_processor_id();
-	int pool;
-	pool = (mvpp2_rxdesc_status_get(port, rx_desc) &
-		MVPP2_RXD_BM_POOL_ID_MASK) >>
-		MVPP2_RXD_BM_POOL_ID_OFFS;
-	return ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS) |
-	       ((cpu & 0xFF) << MVPP2_BM_COOKIE_CPU_OFFS);
-}
 /* Tx descriptors helper methods */
 /* Get pointer to next Tx descriptor to be processed (send) by HW */
 static void mvpp2_rx_pkts_coal_set(struct mvpp2_port *port,
 				   struct mvpp2_rx_queue *rxq)
 {
-	int cpu = smp_processor_id();
+	int cpu = get_cpu();
 	if (rxq->pkts_coal > MVPP2_OCCUPIED_THRESH_MASK)
 		rxq->pkts_coal = MVPP2_OCCUPIED_THRESH_MASK;
 	mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_NUM_REG, rxq->id);
 	mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_THRESH_REG,
 			   rxq->pkts_coal);
+	put_cpu();
 }
 static u32 mvpp2_usec_to_cycles(u32 usec, unsigned long clk_hz)
 	mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
 	/* Set Rx descriptors queue starting address - indirect access */
-	cpu = smp_processor_id();
+	cpu = get_cpu();
 	mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_NUM_REG, rxq->id);
 	if (port->priv->hw_version == MVPP21)
 		rxq_dma = rxq->descs_dma;
 	mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma);
 	mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_DESC_SIZE_REG, rxq->size);
 	mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_INDEX_REG, 0);
+	put_cpu();
 	/* Set Offset */
 	mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD);
 	for (i = 0; i < rx_received; i++) {
 		struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
-		u32 bm = mvpp2_bm_cookie_build(port, rx_desc);
+		u32 status = mvpp2_rxdesc_status_get(port, rx_desc);
+		int pool;
+		pool = (status & MVPP2_RXD_BM_POOL_ID_MASK) >>
+			MVPP2_RXD_BM_POOL_ID_OFFS;
-		mvpp2_pool_refill(port, bm,
+		mvpp2_pool_refill(port, pool,
 				  mvpp2_rxdesc_dma_addr_get(port, rx_desc),
 				  mvpp2_rxdesc_cookie_get(port, rx_desc));
 	}
 	 * free descriptor number
 	 */
 	mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
-	cpu = smp_processor_id();
+	cpu = get_cpu();
 	mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_NUM_REG, rxq->id);
 	mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_DESC_ADDR_REG, 0);
 	mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_DESC_SIZE_REG, 0);
+	put_cpu();
 }
 /* Create and initialize a Tx queue */
 	txq->last_desc = txq->size - 1;
 	/* Set Tx descriptors queue starting address - indirect access */
-	cpu = smp_processor_id();
+	cpu = get_cpu();
 	mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_NUM_REG, txq->id);
 	mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_DESC_ADDR_REG,
 			   txq->descs_dma);
 	mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_PREF_BUF_REG,
 			   MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 |
 			   MVPP2_PREF_BUF_THRESH(desc_per_txq / 2));
+	put_cpu();
 	/* WRR / EJP configuration - indirect access */
 	tx_port_num = mvpp2_egress_port(port);
 	mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0);
 	/* Set Tx descriptors queue starting address and size */
-	cpu = smp_processor_id();
+	cpu = get_cpu();
 	mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_NUM_REG, txq->id);
 	mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_DESC_ADDR_REG, 0);
 	mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_DESC_SIZE_REG, 0);
+	put_cpu();
 }
 /* Cleanup Tx ports */
 	int delay, pending, cpu;
 	u32 val;
-	cpu = smp_processor_id();
+	cpu = get_cpu();
 	mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_NUM_REG, txq->id);
 	val = mvpp2_percpu_read(port->priv, cpu, MVPP2_TXQ_PREF_BUF_REG);
 	val |= MVPP2_TXQ_DRAIN_EN_MASK;
 	val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
 	mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_PREF_BUF_REG, val);
+	put_cpu();
 	for_each_present_cpu(cpu) {
 		txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
 /* Reuse skb if possible, or allocate a new skb and add it to BM pool */
 static int mvpp2_rx_refill(struct mvpp2_port *port,
-			   struct mvpp2_bm_pool *bm_pool, u32 bm)
+			   struct mvpp2_bm_pool *bm_pool, int pool)
 {
 	dma_addr_t dma_addr;
 	phys_addr_t phys_addr;
 	if (!buf)
 		return -ENOMEM;
-	mvpp2_pool_refill(port, bm, dma_addr, phys_addr);
+	mvpp2_pool_refill(port, pool, dma_addr, phys_addr);
 	return 0;
 }
 		unsigned int frag_size;
 		dma_addr_t dma_addr;
 		phys_addr_t phys_addr;
-		u32 bm, rx_status;
+		u32 rx_status;
 		int pool, rx_bytes, err;
 		void *data;
 		phys_addr = mvpp2_rxdesc_cookie_get(port, rx_desc);
 		data = (void *)phys_to_virt(phys_addr);
-		bm = mvpp2_bm_cookie_build(port, rx_desc);
+		pool = (rx_status & MVPP2_RXD_BM_POOL_ID_MASK) >>
-		pool = mvpp2_bm_cookie_pool_get(bm);
+			MVPP2_RXD_BM_POOL_ID_OFFS;
 		bm_pool = &port->priv->bm_pools[pool];
 		/* In case of an error, release the requested buffer pointer
 			dev->stats.rx_errors++;
 			mvpp2_rx_error(port, rx_desc);
 			/* Return the buffer to the pool */
-			mvpp2_pool_refill(port, bm, dma_addr, phys_addr);
+			mvpp2_pool_refill(port, pool, dma_addr, phys_addr);
 			continue;
 		}
 			goto err_drop_frame;
 		}
-		err = mvpp2_rx_refill(port, bm_pool, bm);
+		err = mvpp2_rx_refill(port, bm_pool, pool);
 		if (err) {
 			netdev_err(port->dev, "failed to refill BM pools\n");
 			goto err_drop_frame;

drivers/net/ethernet/mellanox/mlx4/en_ethtool.c+0−5

 		qpn = priv->drop_qp.qpn;
 	else if (cmd->fs.ring_cookie & EN_ETHTOOL_QP_ATTACH) {
 		qpn = cmd->fs.ring_cookie & (EN_ETHTOOL_QP_ATTACH - 1);
-		if (qpn < priv->rss_map.base_qpn ||
-		    qpn >= priv->rss_map.base_qpn + priv->rx_ring_num) {
-			en_warn(priv, "rxnfc: QP (0x%x) doesn't exist\n", qpn);
-			return -EINVAL;
-		}
 	} else {
 		if (cmd->fs.ring_cookie >= priv->rx_ring_num) {
 			en_warn(priv, "rxnfc: RX ring (%llu) doesn't exist\n",

drivers/net/ethernet/mellanox/mlx4/mcg.c+11−4

@@ -35,6 +35,7 @@ · 34 unmodified lines
35	#include <linux/etherdevice.h>	35	#include <linux/etherdevice.h>
36		36
37	#include <linux/mlx4/cmd.h>	37	#include <linux/mlx4/cmd.h>
		38	#include <linux/mlx4/qp.h>
38	#include <linux/export.h>	39	#include <linux/export.h>
39		40
40	#include "mlx4.h"	41	#include "mlx4.h"
@@ -985,16 +986,21 @@ int mlx4_flow_attach(struct mlx4_dev *dev, · 944 unmodified lines
985	if (IS_ERR(mailbox))	986	if (IS_ERR(mailbox))
986	return PTR_ERR(mailbox);	987	return PTR_ERR(mailbox);
987		988
		989	if (!mlx4_qp_lookup(dev, rule->qpn)) {
		990	mlx4_err_rule(dev, "QP doesn't exist\n", rule);
		991	ret = -EINVAL;
		992	goto out;
		993	}
		994
988	trans_rule_ctrl_to_hw(rule, mailbox->buf);	995	trans_rule_ctrl_to_hw(rule, mailbox->buf);
989		996
990	size += sizeof(struct mlx4_net_trans_rule_hw_ctrl);	997	size += sizeof(struct mlx4_net_trans_rule_hw_ctrl);
991		998
992	list_for_each_entry(cur, &rule->list, list) {	999	list_for_each_entry(cur, &rule->list, list) {
993	ret = parse_trans_rule(dev, cur, mailbox->buf + size);	1000	ret = parse_trans_rule(dev, cur, mailbox->buf + size);
994	if (ret < 0) {	1001	if (ret < 0)
995	mlx4_free_cmd_mailbox(dev, mailbox);	1002	goto out;
996	return ret;	1003
997	}
998	size += ret;	1004	size += ret;
999	}	1005	}
1000		1006
@@ -1021,6 +1027,7 @@ int mlx4_flow_attach(struct mlx4_dev *dev, · 20 unmodified lines
1021	}	1027	}
1022	}	1028	}
1023		1029
		1030	out:
1024	mlx4_free_cmd_mailbox(dev, mailbox);	1031	mlx4_free_cmd_mailbox(dev, mailbox);
1025		1032
1026	return ret;	1033	return ret;

drivers/net/ethernet/mellanox/mlx4/qp.c+19−0

@@ -384,6 +384,19 @@ static void mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn) · 383 unmodified lines
384	__mlx4_qp_free_icm(dev, qpn);	384	__mlx4_qp_free_icm(dev, qpn);
385	}	385	}
386		386
		387	struct mlx4_qp mlx4_qp_lookup(struct mlx4_dev dev, u32 qpn)
		388	{
		389	struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table;
		390	struct mlx4_qp *qp;
		391
		392	spin_lock(&qp_table->lock);
		393
		394	qp = __mlx4_qp_lookup(dev, qpn);
		395
		396	spin_unlock(&qp_table->lock);
		397	return qp;
		398	}
		399
387	int mlx4_qp_alloc(struct mlx4_dev dev, int qpn, struct mlx4_qp qp, gfp_t gfp)	400	int mlx4_qp_alloc(struct mlx4_dev dev, int qpn, struct mlx4_qp qp, gfp_t gfp)
388	{	401	{
389	struct mlx4_priv *priv = mlx4_priv(dev);	402	struct mlx4_priv *priv = mlx4_priv(dev);
@@ -471,6 +484,12 @@ int mlx4_update_qp(struct mlx4_dev *dev, u32 qpn, · 81 unmodified lines
471	}	484	}
472		485
473	if (attr & MLX4_UPDATE_QP_QOS_VPORT) {	486	if (attr & MLX4_UPDATE_QP_QOS_VPORT) {
		487	if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_QOS_VPP)) {
		488	mlx4_warn(dev, "Granular QoS per VF is not enabled\n");
		489	err = -EOPNOTSUPP;
		490	goto out;
		491	}
		492
474	qp_mask \|= 1ULL << MLX4_UPD_QP_MASK_QOS_VPP;	493	qp_mask \|= 1ULL << MLX4_UPD_QP_MASK_QOS_VPP;
475	cmd->qp_context.qos_vport = params->qos_vport;	494	cmd->qp_context.qos_vport = params->qos_vport;
476	}	495	}

drivers/net/ethernet/mellanox/mlx4/resource_tracker.c+11−5

@@ -5255,6 +5255,13 @@ void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave) · 5254 unmodified lines
5255	mutex_unlock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);	5255	mutex_unlock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
5256	}	5256	}
5257		5257
		5258	static void update_qos_vpp(struct mlx4_update_qp_context *ctx,
		5259	struct mlx4_vf_immed_vlan_work *work)
		5260	{
		5261	ctx->qp_mask \|= cpu_to_be64(1ULL << MLX4_UPD_QP_MASK_QOS_VPP);
		5262	ctx->qp_context.qos_vport = work->qos_vport;
		5263	}
		5264
5258	void mlx4_vf_immed_vlan_work_handler(struct work_struct *_work)	5265	void mlx4_vf_immed_vlan_work_handler(struct work_struct *_work)
5259	{	5266	{
5260	struct mlx4_vf_immed_vlan_work *work =	5267	struct mlx4_vf_immed_vlan_work *work =
@@ -5369,11 +5376,10 @@ void mlx4_vf_immed_vlan_work_handler(struct work_struct *_work) · 108 unmodified lines
5369	qp->sched_queue & 0xC7;	5376	qp->sched_queue & 0xC7;
5370	upd_context->qp_context.pri_path.sched_queue \|=	5377	upd_context->qp_context.pri_path.sched_queue \|=
5371	((work->qos & 0x7) << 3);	5378	((work->qos & 0x7) << 3);
5372	upd_context->qp_mask \|=	5379
5373	cpu_to_be64(1ULL <<	5380	if (dev->caps.flags2 &
5374	MLX4_UPD_QP_MASK_QOS_VPP);	5381	MLX4_DEV_CAP_FLAG2_QOS_VPP)
5375	upd_context->qp_context.qos_vport =	5382	update_qos_vpp(upd_context, work);
5376	work->qos_vport;
5377	}	5383	}
5378		5384
5379	err = mlx4_cmd(dev, mailbox->dma,	5385	err = mlx4_cmd(dev, mailbox->dma,

drivers/net/ethernet/mellanox/mlx5/core/en.h+5−3

 struct mlx5e_rx_am_stats {
 	int ppms; /* packets per msec */
+	int bpms; /* bytes per msec */
 	int epms; /* events per msec */
 };
 struct mlx5e_rx_am_sample {
-	ktime_t		time;
+	ktime_t	time;
-	unsigned int	pkt_ctr;
+	u32	pkt_ctr;
-	u16		event_ctr;
+	u32	byte_ctr;
+	u16	event_ctr;
 };
 struct mlx5e_rx_am { /* Adaptive Moderation */

drivers/net/ethernet/mellanox/mlx5/core/en_rx_am.c+26−19

@@ -183,28 +183,27 @@ static void mlx5e_am_exit_parking(struct mlx5e_rx_am *am) · 182 unmodified lines
183	mlx5e_am_step(am);	183	mlx5e_am_step(am);
184	}	184	}
185		185
		186	#define IS_SIGNIFICANT_DIFF(val, ref) \
		187	(((100 * abs((val) - (ref))) / (ref)) > 10) /* more than 10% difference */
		188
186	static int mlx5e_am_stats_compare(struct mlx5e_rx_am_stats *curr,	189	static int mlx5e_am_stats_compare(struct mlx5e_rx_am_stats *curr,
187	struct mlx5e_rx_am_stats *prev)	190	struct mlx5e_rx_am_stats *prev)
188	{	191	{
189	int diff;	192	if (!prev->bpms)
190		193	return curr->bpms ? MLX5E_AM_STATS_BETTER :
191	if (!prev->ppms)
192	return curr->ppms ? MLX5E_AM_STATS_BETTER :
193	MLX5E_AM_STATS_SAME;	194	MLX5E_AM_STATS_SAME;
194		195
195	diff = curr->ppms - prev->ppms;	196	if (IS_SIGNIFICANT_DIFF(curr->bpms, prev->bpms))
196	if (((100 * abs(diff)) / prev->ppms) > 10) /* more than 10% diff */	197	return (curr->bpms > prev->bpms) ? MLX5E_AM_STATS_BETTER :
197	return (diff > 0) ? MLX5E_AM_STATS_BETTER :	198	MLX5E_AM_STATS_WORSE;
198	MLX5E_AM_STATS_WORSE;
199		199
200	if (!prev->epms)	200	if (IS_SIGNIFICANT_DIFF(curr->ppms, prev->ppms))
201	return curr->epms ? MLX5E_AM_STATS_WORSE :	201	return (curr->ppms > prev->ppms) ? MLX5E_AM_STATS_BETTER :
202	MLX5E_AM_STATS_SAME;	202	MLX5E_AM_STATS_WORSE;
203		203
204	diff = curr->epms - prev->epms;	204	if (IS_SIGNIFICANT_DIFF(curr->epms, prev->epms))
205	if (((100 * abs(diff)) / prev->epms) > 10) /* more than 10% diff */	205	return (curr->epms < prev->epms) ? MLX5E_AM_STATS_BETTER :
206	return (diff < 0) ? MLX5E_AM_STATS_BETTER :	206	MLX5E_AM_STATS_WORSE;
207	MLX5E_AM_STATS_WORSE;
208		207
209	return MLX5E_AM_STATS_SAME;	208	return MLX5E_AM_STATS_SAME;
210	}	209	}
@@ -266,10 +265,13 @@ static void mlx5e_am_sample(struct mlx5e_rq *rq, · 55 unmodified lines
266	{	265	{
267	s->time = ktime_get();	266	s->time = ktime_get();
268	s->pkt_ctr = rq->stats.packets;	267	s->pkt_ctr = rq->stats.packets;
		268	s->byte_ctr = rq->stats.bytes;
269	s->event_ctr = rq->cq.event_ctr;	269	s->event_ctr = rq->cq.event_ctr;
270	}	270	}
271		271
272	#define MLX5E_AM_NEVENTS 64	272	#define MLX5E_AM_NEVENTS 64
		273	#define BITS_PER_TYPE(type) (sizeof(type) * BITS_PER_BYTE)
		274	#define BIT_GAP(bits, end, start) ((((end) - (start)) + BIT_ULL(bits)) & (BIT_ULL(bits) - 1))
273		275
274	static void mlx5e_am_calc_stats(struct mlx5e_rx_am_sample *start,	276	static void mlx5e_am_calc_stats(struct mlx5e_rx_am_sample *start,
275	struct mlx5e_rx_am_sample *end,	277	struct mlx5e_rx_am_sample *end,
@@ -277,13 +279,17 @@ static void mlx5e_am_calc_stats(struct mlx5e_rx_am_sample *start, · 1 unmodified line
277	{	279	{
278	/* u32 holds up to 71 minutes, should be enough */	280	/* u32 holds up to 71 minutes, should be enough */
279	u32 delta_us = ktime_us_delta(end->time, start->time);	281	u32 delta_us = ktime_us_delta(end->time, start->time);
280	unsigned int npkts = end->pkt_ctr - start->pkt_ctr;	282	u32 npkts = BIT_GAP(BITS_PER_TYPE(u32), end->pkt_ctr, start->pkt_ctr);
		283	u32 nbytes = BIT_GAP(BITS_PER_TYPE(u32), end->byte_ctr,
		284	start->byte_ctr);
281		285
282	if (!delta_us)	286	if (!delta_us)
283	return;	287	return;
284		288
285	curr_stats->ppms = (npkts * USEC_PER_MSEC) / delta_us;	289	curr_stats->ppms = DIV_ROUND_UP(npkts * USEC_PER_MSEC, delta_us);
286	curr_stats->epms = (MLX5E_AM_NEVENTS * USEC_PER_MSEC) / delta_us;	290	curr_stats->bpms = DIV_ROUND_UP(nbytes * USEC_PER_MSEC, delta_us);
		291	curr_stats->epms = DIV_ROUND_UP(MLX5E_AM_NEVENTS * USEC_PER_MSEC,
		292	delta_us);
287	}	293	}
288		294
289	void mlx5e_rx_am_work(struct work_struct *work)	295	void mlx5e_rx_am_work(struct work_struct *work)
@@ -308,7 +314,8 @@ void mlx5e_rx_am(struct mlx5e_rq *rq) · 18 unmodified lines
308		314
309	switch (am->state) {	315	switch (am->state) {
310	case MLX5E_AM_MEASURE_IN_PROGRESS:	316	case MLX5E_AM_MEASURE_IN_PROGRESS:
311	nevents = rq->cq.event_ctr - am->start_sample.event_ctr;	317	nevents = BIT_GAP(BITS_PER_TYPE(u16), rq->cq.event_ctr,
		318	am->start_sample.event_ctr);
312	if (nevents < MLX5E_AM_NEVENTS)	319	if (nevents < MLX5E_AM_NEVENTS)
313	break;	320	break;
314	mlx5e_am_sample(rq, &end_sample);	321	mlx5e_am_sample(rq, &end_sample);

drivers/net/ethernet/mellanox/mlx5/core/en_stats.h+2−9

 };
 static const struct counter_desc mlx5e_pme_status_desc[] = {
-	{ "module_plug", 0 },
 	{ "module_unplug", 8 },
 };
 static const struct counter_desc mlx5e_pme_error_desc[] = {
-	{ "module_pwr_budget_exd", 0 },  /* power budget exceed */
+	{ "module_bus_stuck", 16 },       /* bus stuck (I2C or data shorted) */
-	{ "module_long_range", 8 },      /* long range for non MLNX cable */
+	{ "module_high_temp", 48 },       /* high temperature */
-	{ "module_bus_stuck", 16 },      /* bus stuck (I2C or data shorted) */
-	{ "module_no_eeprom", 24 },      /* no eeprom/retry time out */
-	{ "module_enforce_part", 32 },   /* enforce part number list */
-	{ "module_unknown_id", 40 },     /* unknown identifier */
-	{ "module_high_temp", 48 },      /* high temperature */
 	{ "module_bad_shorted", 56 },    /* bad or shorted cable/module */
-	{ "module_unknown_status", 64 },
 };
 #endif /* __MLX5_EN_STATS_H__ */

drivers/net/ethernet/mellanox/mlx5/core/fs_core.c+1−1

@@ -862,7 +862,7 @@ struct mlx5_flow_table *mlx5_create_vport_flow_table(struct mlx5_flow_namespace · 861 unmodified lines
862	ft_attr.level = level;	862	ft_attr.level = level;
863	ft_attr.prio = prio;	863	ft_attr.prio = prio;
864		864
865	return __mlx5_create_flow_table(ns, &ft_attr, FS_FT_OP_MOD_NORMAL, 0);	865	return __mlx5_create_flow_table(ns, &ft_attr, FS_FT_OP_MOD_NORMAL, vport);
866	}	866	}
867		867
868	struct mlx5_flow_table*	868	struct mlx5_flow_table*

drivers/net/ethernet/mellanox/mlx5/core/health.c+5−6

 	struct mlx5_core_health *health = &dev->priv.health;
 	u32 count;
-	if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
+	if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR)
-		mod_timer(&health->timer, get_next_poll_jiffies());
+		goto out;
-		return;
-	}
 	count = ioread32be(health->health_counter);
 	if (count == health->prev)
 	if (health->miss_counter == MAX_MISSES) {
 		dev_err(&dev->pdev->dev, "device's health compromised - reached miss count\n");
 		print_health_info(dev);
-	} else {
-		mod_timer(&health->timer, get_next_poll_jiffies());
 	}
 	if (in_fatal(dev) && !health->sick) {
 				"new health works are not permitted at this stage\n");
 		spin_unlock(&health->wq_lock);
 	}
+out:
+	mod_timer(&health->timer, get_next_poll_jiffies());
 }
 void mlx5_start_health_poll(struct mlx5_core_dev *dev)

drivers/net/ethernet/mellanox/mlx5/core/main.c+6−5

 	/* disable cmdif checksum */
 	MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
-	/* If the HCA supports 4K UARs use it */
+	/* Enable 4K UAR only when HCA supports it and page size is bigger
-	if (MLX5_CAP_GEN_MAX(dev, uar_4k))
+	 * than 4K.
+	 */
+	if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096)
 		MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1);
 	MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
 	cpumask_set_cpu(cpumask_local_spread(i, priv->numa_node),
 			priv->irq_info[i].mask);
-#ifdef CONFIG_SMP
+	if (IS_ENABLED(CONFIG_SMP) &&
-	if (irq_set_affinity_hint(irq, priv->irq_info[i].mask))
+	    irq_set_affinity_hint(irq, priv->irq_info[i].mask))
 		mlx5_core_warn(mdev, "irq_set_affinity_hint failed, irq 0x%.4x", irq);
-#endif
 	return 0;
 }

drivers/net/ethernet/qlogic/qed/qed_debug.c+1−1

@@ -2956,7 +2956,7 @@ static u32 qed_grc_dump_ctx_data(struct qed_hwfn *p_hwfn, · 2955 unmodified lines
2956	qed_wr(p_hwfn,	2956	qed_wr(p_hwfn,
2957	p_ptt,	2957	p_ptt,
2958	s_storm_defs[storm_id].cm_ctx_wr_addr,	2958	s_storm_defs[storm_id].cm_ctx_wr_addr,
2959	BIT(9) \| lid);	2959	(i << 9) \| lid);
2960	*(dump_buf + offset) = qed_rd(p_hwfn,	2960	*(dump_buf + offset) = qed_rd(p_hwfn,
2961	p_ptt,	2961	p_ptt,
2962	rd_reg_addr);	2962	rd_reg_addr);

drivers/net/ethernet/qlogic/qed/qed_main.c+2−1

 		qed_get_protocol_stats_iscsi(cdev, &stats->iscsi_stats);
 		break;
 	default:
-		DP_ERR(cdev, "Invalid protocol type = %d\n", type);
+		DP_VERBOSE(cdev, QED_MSG_SP,
+			   "Invalid protocol type = %d\n", type);
 		return;
 	}
 }

drivers/net/ethernet/qlogic/qlcnic/qlcnic.h+24−2

 	u32 (*get_cap_size)(void *, int);
 	void (*set_sys_info)(void *, int, u32);
 	void (*store_cap_mask)(void *, u32);
+	bool (*encap_rx_offload) (struct qlcnic_adapter *adapter);
+	bool (*encap_tx_offload) (struct qlcnic_adapter *adapter);
 };
 extern struct qlcnic_nic_template qlcnic_vf_ops;
-static inline bool qlcnic_encap_tx_offload(struct qlcnic_adapter *adapter)
+static inline bool qlcnic_83xx_encap_tx_offload(struct qlcnic_adapter *adapter)
 {
 	return adapter->ahw->extra_capability[0] &
 	       QLCNIC_83XX_FW_CAPAB_ENCAP_TX_OFFLOAD;
 }
-static inline bool qlcnic_encap_rx_offload(struct qlcnic_adapter *adapter)
+static inline bool qlcnic_83xx_encap_rx_offload(struct qlcnic_adapter *adapter)
 {
 	return adapter->ahw->extra_capability[0] &
 	       QLCNIC_83XX_FW_CAPAB_ENCAP_RX_OFFLOAD;
 }
+static inline bool qlcnic_82xx_encap_tx_offload(struct qlcnic_adapter *adapter)
+{
+	return false;
+}
+static inline bool qlcnic_82xx_encap_rx_offload(struct qlcnic_adapter *adapter)
+{
+        return false;
+}
+static inline bool qlcnic_encap_rx_offload(struct qlcnic_adapter *adapter)
+{
+        return adapter->ahw->hw_ops->encap_rx_offload(adapter);
+}
+static inline bool qlcnic_encap_tx_offload(struct qlcnic_adapter *adapter)
+{
+        return adapter->ahw->hw_ops->encap_tx_offload(adapter);
+}
 static inline int qlcnic_start_firmware(struct qlcnic_adapter *adapter)
 {
 	return adapter->nic_ops->start_firmware(adapter);

drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c+2−0

@@ -242,6 +242,8 @@ static struct qlcnic_hardware_ops qlcnic_83xx_hw_ops = { · 241 unmodified lines
242	.get_cap_size = qlcnic_83xx_get_cap_size,	242	.get_cap_size = qlcnic_83xx_get_cap_size,
243	.set_sys_info = qlcnic_83xx_set_sys_info,	243	.set_sys_info = qlcnic_83xx_set_sys_info,
244	.store_cap_mask = qlcnic_83xx_store_cap_mask,	244	.store_cap_mask = qlcnic_83xx_store_cap_mask,
		245	.encap_rx_offload = qlcnic_83xx_encap_rx_offload,
		246	.encap_tx_offload = qlcnic_83xx_encap_tx_offload,
245	};	247	};
246		248
247	static struct qlcnic_nic_template qlcnic_83xx_ops = {	249	static struct qlcnic_nic_template qlcnic_83xx_ops = {

drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c+1−1

@@ -341,7 +341,7 @@ qlcnic_pcie_sem_lock(struct qlcnic_adapter *adapter, int sem, u32 id_reg) · 340 unmodified lines
341	}	341	}
342	return -EIO;	342	return -EIO;
343	}	343	}
344	usleep_range(1000, 1500);	344	udelay(1200);
345	}	345	}
346		346
347	if (id_reg)	347	if (id_reg)

drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c+2−0

@@ -632,6 +632,8 @@ static struct qlcnic_hardware_ops qlcnic_hw_ops = { · 631 unmodified lines
632	.get_cap_size = qlcnic_82xx_get_cap_size,	632	.get_cap_size = qlcnic_82xx_get_cap_size,
633	.set_sys_info = qlcnic_82xx_set_sys_info,	633	.set_sys_info = qlcnic_82xx_set_sys_info,
634	.store_cap_mask = qlcnic_82xx_store_cap_mask,	634	.store_cap_mask = qlcnic_82xx_store_cap_mask,
		635	.encap_rx_offload = qlcnic_82xx_encap_rx_offload,
		636	.encap_tx_offload = qlcnic_82xx_encap_tx_offload,
635	};	637	};
636		638
637	static int qlcnic_check_multi_tx_capability(struct qlcnic_adapter *adapter)	639	static int qlcnic_check_multi_tx_capability(struct qlcnic_adapter *adapter)

drivers/net/ethernet/qlogic/qlcnic/qlcnic_sriov_common.c+2−0

@@ -77,6 +77,8 @@ static struct qlcnic_hardware_ops qlcnic_sriov_vf_hw_ops = { · 76 unmodified lines
77	.free_mac_list = qlcnic_sriov_vf_free_mac_list,	77	.free_mac_list = qlcnic_sriov_vf_free_mac_list,
78	.enable_sds_intr = qlcnic_83xx_enable_sds_intr,	78	.enable_sds_intr = qlcnic_83xx_enable_sds_intr,
79	.disable_sds_intr = qlcnic_83xx_disable_sds_intr,	79	.disable_sds_intr = qlcnic_83xx_disable_sds_intr,
		80	.encap_rx_offload = qlcnic_83xx_encap_rx_offload,
		81	.encap_tx_offload = qlcnic_83xx_encap_tx_offload,
80	};	82	};
81		83
82	static struct qlcnic_nic_template qlcnic_sriov_vf_ops = {	84	static struct qlcnic_nic_template qlcnic_sriov_vf_ops = {

drivers/net/ethernet/qualcomm/emac/emac-mac.c+1−1

@@ -931,7 +931,7 @@ int emac_mac_up(struct emac_adapter *adpt) · 930 unmodified lines
931	emac_mac_config(adpt);	931	emac_mac_config(adpt);
932	emac_mac_rx_descs_refill(adpt, &adpt->rx_q);	932	emac_mac_rx_descs_refill(adpt, &adpt->rx_q);
933		933
934	adpt->phydev->irq = PHY_IGNORE_INTERRUPT;	934	adpt->phydev->irq = PHY_POLL;
935	ret = phy_connect_direct(netdev, adpt->phydev, emac_adjust_link,	935	ret = phy_connect_direct(netdev, adpt->phydev, emac_adjust_link,
936	PHY_INTERFACE_MODE_SGMII);	936	PHY_INTERFACE_MODE_SGMII);
937	if (ret) {	937	if (ret) {

drivers/net/ethernet/qualcomm/emac/emac-phy.c+4−71

@@ -13,15 +13,11 @@ · 12 unmodified lines
13	/* Qualcomm Technologies, Inc. EMAC PHY Controller driver.	13	/* Qualcomm Technologies, Inc. EMAC PHY Controller driver.
14	*/	14	*/
15		15
16	#include <linux/module.h>
17	#include <linux/of.h>
18	#include <linux/of_net.h>
19	#include <linux/of_mdio.h>	16	#include <linux/of_mdio.h>
20	#include <linux/phy.h>	17	#include <linux/phy.h>
21	#include <linux/iopoll.h>	18	#include <linux/iopoll.h>
22	#include <linux/acpi.h>	19	#include <linux/acpi.h>
23	#include "emac.h"	20	#include "emac.h"
24	#include "emac-mac.h"
25		21
26	/* EMAC base register offsets */	22	/* EMAC base register offsets */
27	#define EMAC_MDIO_CTRL 0x001414	23	#define EMAC_MDIO_CTRL 0x001414
@@ -52,62 +48,10 @@ · 24 unmodified lines
52		48
53	#define MDIO_WAIT_TIMES 1000	49	#define MDIO_WAIT_TIMES 1000
54		50
55	#define EMAC_LINK_SPEED_DEFAULT (\
56	EMAC_LINK_SPEED_10_HALF \|\
57	EMAC_LINK_SPEED_10_FULL \|\
58	EMAC_LINK_SPEED_100_HALF \|\
59	EMAC_LINK_SPEED_100_FULL \|\
60	EMAC_LINK_SPEED_1GB_FULL)
61
62	/**
63	* emac_phy_mdio_autopoll_disable() - disable mdio autopoll
64	* @adpt: the emac adapter
65	*
66	* The autopoll feature takes over the MDIO bus. In order for
67	* the PHY driver to be able to talk to the PHY over the MDIO
68	* bus, we need to temporarily disable the autopoll feature.
69	*/
70	static int emac_phy_mdio_autopoll_disable(struct emac_adapter *adpt)
71	{
72	u32 val;
73
74	/* disable autopoll */
75	emac_reg_update32(adpt->base + EMAC_MDIO_CTRL, MDIO_AP_EN, 0);
76
77	/* wait for any mdio polling to complete */
78	if (!readl_poll_timeout(adpt->base + EMAC_MDIO_CTRL, val,
79	!(val & MDIO_BUSY), 100, MDIO_WAIT_TIMES * 100))
80	return 0;
81
82	/* failed to disable; ensure it is enabled before returning */
83	emac_reg_update32(adpt->base + EMAC_MDIO_CTRL, 0, MDIO_AP_EN);
84
85	return -EBUSY;
86	}
87
88	/**
89	* emac_phy_mdio_autopoll_disable() - disable mdio autopoll
90	* @adpt: the emac adapter
91	*
92	* The EMAC has the ability to poll the external PHY on the MDIO
93	* bus for link state changes. This eliminates the need for the
94	* driver to poll the phy. If if the link state does change,
95	* the EMAC issues an interrupt on behalf of the PHY.
96	*/
97	static void emac_phy_mdio_autopoll_enable(struct emac_adapter *adpt)
98	{
99	emac_reg_update32(adpt->base + EMAC_MDIO_CTRL, 0, MDIO_AP_EN);
100	}
101
102	static int emac_mdio_read(struct mii_bus *bus, int addr, int regnum)	51	static int emac_mdio_read(struct mii_bus *bus, int addr, int regnum)
103	{	52	{
104	struct emac_adapter *adpt = bus->priv;	53	struct emac_adapter *adpt = bus->priv;
105	u32 reg;	54	u32 reg;
106	int ret;
107
108	ret = emac_phy_mdio_autopoll_disable(adpt);
109	if (ret)
110	return ret;
111		55
112	emac_reg_update32(adpt->base + EMAC_PHY_STS, PHY_ADDR_BMSK,	56	emac_reg_update32(adpt->base + EMAC_PHY_STS, PHY_ADDR_BMSK,
113	(addr << PHY_ADDR_SHFT));	57	(addr << PHY_ADDR_SHFT));
@@ -122,24 +66,15 @@ static int emac_mdio_read(struct mii_bus *bus, int addr, int regnum) · 8 unmodified lines
122	if (readl_poll_timeout(adpt->base + EMAC_MDIO_CTRL, reg,	66	if (readl_poll_timeout(adpt->base + EMAC_MDIO_CTRL, reg,
123	!(reg & (MDIO_START \| MDIO_BUSY)),	67	!(reg & (MDIO_START \| MDIO_BUSY)),
124	100, MDIO_WAIT_TIMES * 100))	68	100, MDIO_WAIT_TIMES * 100))
125	ret = -EIO;	69	return -EIO;
126	else
127	ret = (reg >> MDIO_DATA_SHFT) & MDIO_DATA_BMSK;
128		70
129	emac_phy_mdio_autopoll_enable(adpt);	71	return (reg >> MDIO_DATA_SHFT) & MDIO_DATA_BMSK;
130
131	return ret;
132	}	72	}
133		73
134	static int emac_mdio_write(struct mii_bus *bus, int addr, int regnum, u16 val)	74	static int emac_mdio_write(struct mii_bus *bus, int addr, int regnum, u16 val)
135	{	75	{
136	struct emac_adapter *adpt = bus->priv;	76	struct emac_adapter *adpt = bus->priv;
137	u32 reg;	77	u32 reg;
138	int ret;
139
140	ret = emac_phy_mdio_autopoll_disable(adpt);
141	if (ret)
142	return ret;
143		78
144	emac_reg_update32(adpt->base + EMAC_PHY_STS, PHY_ADDR_BMSK,	79	emac_reg_update32(adpt->base + EMAC_PHY_STS, PHY_ADDR_BMSK,
145	(addr << PHY_ADDR_SHFT));	80	(addr << PHY_ADDR_SHFT));
@@ -155,11 +90,9 @@ static int emac_mdio_write(struct mii_bus *bus, int addr, int regnum, u16 val) · 9 unmodified lines
155	if (readl_poll_timeout(adpt->base + EMAC_MDIO_CTRL, reg,	90	if (readl_poll_timeout(adpt->base + EMAC_MDIO_CTRL, reg,
156	!(reg & (MDIO_START \| MDIO_BUSY)), 100,	91	!(reg & (MDIO_START \| MDIO_BUSY)), 100,
157	MDIO_WAIT_TIMES * 100))	92	MDIO_WAIT_TIMES * 100))
158	ret = -EIO;	93	return -EIO;
159		94
160	emac_phy_mdio_autopoll_enable(adpt);	95	return 0;
161
162	return ret;
163	}	96	}
164		97
165	/* Configure the MDIO bus and connect the external PHY */	98	/* Configure the MDIO bus and connect the external PHY */

drivers/net/ethernet/qualcomm/emac/emac.c+1−21

@@ -50,19 +50,7 @@ · 49 unmodified lines
50	#define DMAR_DLY_CNT_DEF 15	50	#define DMAR_DLY_CNT_DEF 15
51	#define DMAW_DLY_CNT_DEF 4	51	#define DMAW_DLY_CNT_DEF 4
52		52
53	#define IMR_NORMAL_MASK (\	53	#define IMR_NORMAL_MASK (ISR_ERROR \| ISR_OVER \| ISR_TX_PKT)
54	ISR_ERROR \|\
55	ISR_GPHY_LINK \|\
56	ISR_TX_PKT \|\
57	GPHY_WAKEUP_INT)
58
59	#define IMR_EXTENDED_MASK (\
60	SW_MAN_INT \|\
61	ISR_OVER \|\
62	ISR_ERROR \|\
63	ISR_GPHY_LINK \|\
64	ISR_TX_PKT \|\
65	GPHY_WAKEUP_INT)
66		54
67	#define ISR_TX_PKT (\	55	#define ISR_TX_PKT (\
68	TX_PKT_INT \|\	56	TX_PKT_INT \|\
@@ -70,10 +58,6 @@ · 1 unmodified line
70	TX_PKT_INT2 \|\	58	TX_PKT_INT2 \|\
71	TX_PKT_INT3)	59	TX_PKT_INT3)
72		60
73	#define ISR_GPHY_LINK (\
74	GPHY_LINK_UP_INT \|\
75	GPHY_LINK_DOWN_INT)
76
77	#define ISR_OVER (\	61	#define ISR_OVER (\
78	RFD0_UR_INT \|\	62	RFD0_UR_INT \|\
79	RFD1_UR_INT \|\	63	RFD1_UR_INT \|\
@@ -187,10 +171,6 @@ irqreturn_t emac_isr(int _irq, void *data) · 107 unmodified lines
187	if (status & ISR_OVER)	171	if (status & ISR_OVER)
188	net_warn_ratelimited("warning: TX/RX overflow\n");	172	net_warn_ratelimited("warning: TX/RX overflow\n");
189		173
190	/* link event */
191	if (status & ISR_GPHY_LINK)
192	phy_mac_interrupt(adpt->phydev, !!(status & GPHY_LINK_UP_INT));
193
194	exit:	174	exit:
195	/* enable the interrupt */	175	/* enable the interrupt */
196	writel(irq->mask, adpt->base + EMAC_INT_MASK);	176	writel(irq->mask, adpt->base + EMAC_INT_MASK);

drivers/net/ethernet/renesas/ravb_main.c+12−12

 	int ring_size;
 	int i;
-	/* Free RX skb ringbuffer */
-	if (priv->rx_skb[q]) {
-		for (i = 0; i < priv->num_rx_ring[q]; i++)
-			dev_kfree_skb(priv->rx_skb[q][i]);
-	}
-	kfree(priv->rx_skb[q]);
-	priv->rx_skb[q] = NULL;
-	/* Free aligned TX buffers */
-	kfree(priv->tx_align[q]);
-	priv->tx_align[q] = NULL;
 	if (priv->rx_ring[q]) {
 		for (i = 0; i < priv->num_rx_ring[q]; i++) {
 			struct ravb_ex_rx_desc *desc = &priv->rx_ring[q][i];
 		priv->tx_ring[q] = NULL;
 	}
+	/* Free RX skb ringbuffer */
+	if (priv->rx_skb[q]) {
+		for (i = 0; i < priv->num_rx_ring[q]; i++)
+			dev_kfree_skb(priv->rx_skb[q][i]);
+	}
+	kfree(priv->rx_skb[q]);
+	priv->rx_skb[q] = NULL;
+	/* Free aligned TX buffers */
+	kfree(priv->tx_align[q]);
+	priv->tx_align[q] = NULL;
 	/* Free TX skb ringbuffer.
 	 * SKBs are freed by ravb_tx_free() call above.
 	 */

drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c+5−1

 #define TSE_PCS_CONTROL_AN_EN_MASK			BIT(12)
 #define TSE_PCS_CONTROL_REG				0x00
 #define TSE_PCS_CONTROL_RESTART_AN_MASK			BIT(9)
+#define TSE_PCS_CTRL_AUTONEG_SGMII			0x1140
 #define TSE_PCS_IF_MODE_REG				0x28
 #define TSE_PCS_LINK_TIMER_0_REG			0x24
 #define TSE_PCS_LINK_TIMER_1_REG			0x26
 #define TSE_PCS_SW_RESET_TIMEOUT			100
 #define TSE_PCS_USE_SGMII_AN_MASK			BIT(1)
 #define TSE_PCS_USE_SGMII_ENA				BIT(0)
+#define TSE_PCS_IF_USE_SGMII				0x03
 #define SGMII_ADAPTER_CTRL_REG				0x00
 #define SGMII_ADAPTER_DISABLE				0x0001
 {
 	int ret = 0;
-	writew(TSE_PCS_USE_SGMII_ENA, base + TSE_PCS_IF_MODE_REG);
+	writew(TSE_PCS_IF_USE_SGMII, base + TSE_PCS_IF_MODE_REG);
+	writew(TSE_PCS_CTRL_AUTONEG_SGMII, base + TSE_PCS_CONTROL_REG);
 	writew(TSE_PCS_SGMII_LINK_TIMER_0, base + TSE_PCS_LINK_TIMER_0_REG);
 	writew(TSE_PCS_SGMII_LINK_TIMER_1, base + TSE_PCS_LINK_TIMER_1_REG);

drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c+7−4

 {
 	/* Context type from W/B descriptor must be zero */
 	if (le32_to_cpu(p->des3) & TDES3_CONTEXT_TYPE)
-		return -EINVAL;
+		return 0;
 	/* Tx Timestamp Status is 1 so des0 and des1'll have valid values */
 	if (le32_to_cpu(p->des3) & TDES3_TIMESTAMP_STATUS)
-		return 0;
+		return 1;
-	return 1;
+	return 0;
 }
 static inline u64 dwmac4_get_timestamp(void *desc, u32 ats)
 		}
 	}
 exit:
-	return ret;
+	if (likely(ret == 0))
+		return 1;
+	return 0;
 }
 static void dwmac4_rd_init_rx_desc(struct dma_desc *p, int disable_rx_ic,

drivers/net/ethernet/stmicro/stmmac/stmmac_main.c+21−11

 		return;
 	/* check tx tstamp status */
-	if (!priv->hw->desc->get_tx_timestamp_status(p)) {
+	if (priv->hw->desc->get_tx_timestamp_status(p)) {
 		/* get the valid tstamp */
 		ns = priv->hw->desc->get_timestamp(p, priv->adv_ts);
 		memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 		shhwtstamp.hwtstamp = ns_to_ktime(ns);
-		netdev_info(priv->dev, "get valid TX hw timestamp %llu\n", ns);
+		netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns);
 		/* pass tstamp to stack */
 		skb_tstamp_tx(skb, &shhwtstamp);
 	}
 		return;
 	/* Check if timestamp is available */
-	if (!priv->hw->desc->get_rx_timestamp_status(p, priv->adv_ts)) {
+	if (priv->hw->desc->get_rx_timestamp_status(p, priv->adv_ts)) {
 		/* For GMAC4, the valid timestamp is from CTX next desc. */
 		if (priv->plat->has_gmac4)
 			ns = priv->hw->desc->get_timestamp(np, priv->adv_ts);
 		else
 			ns = priv->hw->desc->get_timestamp(p, priv->adv_ts);
-		netdev_info(priv->dev, "get valid RX hw timestamp %llu\n", ns);
+		netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns);
 		shhwtstamp = skb_hwtstamps(skb);
 		memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 		shhwtstamp->hwtstamp = ns_to_ktime(ns);
 	} else  {
-		netdev_err(priv->dev, "cannot get RX hw timestamp\n");
+		netdev_dbg(priv->dev, "cannot get RX hw timestamp\n");
 	}
 }
 			/* PTP v1, UDP, any kind of event packet */
 			config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 			/* take time stamp for all event messages */
-			snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
+			if (priv->plat->has_gmac4)
+				snap_type_sel = PTP_GMAC4_TCR_SNAPTYPSEL_1;
+			else
+				snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 			ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 			ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 			config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
 			ptp_v2 = PTP_TCR_TSVER2ENA;
 			/* take time stamp for all event messages */
-			snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
+			if (priv->plat->has_gmac4)
+				snap_type_sel = PTP_GMAC4_TCR_SNAPTYPSEL_1;
+			else
+				snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 			ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 			ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 			config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
 			ptp_v2 = PTP_TCR_TSVER2ENA;
 			/* take time stamp for all event messages */
-			snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
+			if (priv->plat->has_gmac4)
+				snap_type_sel = PTP_GMAC4_TCR_SNAPTYPSEL_1;
+			else
+				snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 			ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 			ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 	u32 rx_count = priv->plat->rx_queues_to_use;
 	unsigned int bfsize = 0;
 	int ret = -ENOMEM;
-	u32 queue;
+	int queue;
 	int i;
 	if (priv->hw->mode->set_16kib_bfsize)
 		priv->hw->desc->prepare_tso_tx_desc(desc, 0, buff_size,
 			0, 1,
-			(last_segment) && (buff_size < TSO_MAX_BUFF_SIZE),
+			(last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE),
 			0, 0);
 		tmp_len -= TSO_MAX_BUFF_SIZE;
 	int i, csum_insertion = 0, is_jumbo = 0;
 	u32 queue = skb_get_queue_mapping(skb);
 	int nfrags = skb_shinfo(skb)->nr_frags;
-	unsigned int entry, first_entry;
+	int entry;
+	unsigned int first_entry;
 	struct dma_desc *desc, *first;
 	struct stmmac_tx_queue *tx_q;
 	unsigned int enh_desc;

drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.h+2−1

@@ -59,7 +59,8 @@ · 58 unmodified lines
59	/* Enable Snapshot for Messages Relevant to Master */	59	/* Enable Snapshot for Messages Relevant to Master */
60	#define PTP_TCR_TSMSTRENA BIT(15)	60	#define PTP_TCR_TSMSTRENA BIT(15)
61	/* Select PTP packets for Taking Snapshots */	61	/* Select PTP packets for Taking Snapshots */
62	#define PTP_TCR_SNAPTYPSEL_1 GENMASK(17, 16)	62	#define PTP_TCR_SNAPTYPSEL_1 BIT(16)
		63	#define PTP_GMAC4_TCR_SNAPTYPSEL_1 GENMASK(17, 16)
63	/* Enable MAC address for PTP Frame Filtering */	64	/* Enable MAC address for PTP Frame Filtering */
64	#define PTP_TCR_TSENMACADDR BIT(18)	65	#define PTP_TCR_TSENMACADDR BIT(18)
65		66

drivers/net/geneve.c+2−2

@@ -1007,7 +1007,7 @@ static void geneve_setup(struct net_device *dev) · 1006 unmodified lines
1007		1007
1008	dev->netdev_ops = &geneve_netdev_ops;	1008	dev->netdev_ops = &geneve_netdev_ops;
1009	dev->ethtool_ops = &geneve_ethtool_ops;	1009	dev->ethtool_ops = &geneve_ethtool_ops;
1010	dev->destructor = free_netdev;	1010	dev->needs_free_netdev = true;
1011		1011
1012	SET_NETDEV_DEVTYPE(dev, &geneve_type);	1012	SET_NETDEV_DEVTYPE(dev, &geneve_type);
1013		1013
@@ -1133,7 +1133,7 @@ static int geneve_configure(struct net net, struct net_device dev, · 119 unmodified lines
1133		1133
1134	/* make enough headroom for basic scenario */	1134	/* make enough headroom for basic scenario */
1135	encap_len = GENEVE_BASE_HLEN + ETH_HLEN;	1135	encap_len = GENEVE_BASE_HLEN + ETH_HLEN;
1136	if (ip_tunnel_info_af(info) == AF_INET) {	1136	if (!metadata && ip_tunnel_info_af(info) == AF_INET) {
1137	encap_len += sizeof(struct iphdr);	1137	encap_len += sizeof(struct iphdr);
1138	dev->max_mtu -= sizeof(struct iphdr);	1138	dev->max_mtu -= sizeof(struct iphdr);
1139	} else {	1139	} else {

drivers/net/gtp.c+1−1

@@ -611,7 +611,7 @@ static const struct net_device_ops gtp_netdev_ops = { · 610 unmodified lines
611	static void gtp_link_setup(struct net_device *dev)	611	static void gtp_link_setup(struct net_device *dev)
612	{	612	{
613	dev->netdev_ops = &gtp_netdev_ops;	613	dev->netdev_ops = &gtp_netdev_ops;
614	dev->destructor = free_netdev;	614	dev->needs_free_netdev = true;
615		615
616	dev->hard_header_len = 0;	616	dev->hard_header_len = 0;
617	dev->addr_len = 0;	617	dev->addr_len = 0;

drivers/net/hamradio/6pack.c+1−1

@@ -311,7 +311,7 @@ static void sp_setup(struct net_device *dev) · 310 unmodified lines
311	{	311	{
312	/* Finish setting up the DEVICE info. */	312	/* Finish setting up the DEVICE info. */
313	dev->netdev_ops = &sp_netdev_ops;	313	dev->netdev_ops = &sp_netdev_ops;
314	dev->destructor = free_netdev;	314	dev->needs_free_netdev = true;
315	dev->mtu = SIXP_MTU;	315	dev->mtu = SIXP_MTU;
316	dev->hard_header_len = AX25_MAX_HEADER_LEN;	316	dev->hard_header_len = AX25_MAX_HEADER_LEN;
317	dev->header_ops = &ax25_header_ops;	317	dev->header_ops = &ax25_header_ops;

drivers/net/hamradio/bpqether.c+1−1

@@ -476,7 +476,7 @@ static const struct net_device_ops bpq_netdev_ops = { · 475 unmodified lines
476	static void bpq_setup(struct net_device *dev)	476	static void bpq_setup(struct net_device *dev)
477	{	477	{
478	dev->netdev_ops = &bpq_netdev_ops;	478	dev->netdev_ops = &bpq_netdev_ops;
479	dev->destructor = free_netdev;	479	dev->needs_free_netdev = true;
480		480
481	memcpy(dev->broadcast, &ax25_bcast, AX25_ADDR_LEN);	481	memcpy(dev->broadcast, &ax25_bcast, AX25_ADDR_LEN);
482	memcpy(dev->dev_addr, &ax25_defaddr, AX25_ADDR_LEN);	482	memcpy(dev->dev_addr, &ax25_defaddr, AX25_ADDR_LEN);

drivers/net/hamradio/hdlcdrv.c+2−0

 	case HDLCDRVCTL_CALIBRATE:
 		if(!capable(CAP_SYS_RAWIO))
 			return -EPERM;
+		if (s->par.bitrate <= 0)
+			return -EINVAL;
 		if (bi.data.calibrate > INT_MAX / s->par.bitrate)
 			return -EINVAL;
 		s->hdlctx.calibrate = bi.data.calibrate * s->par.bitrate / 16;

drivers/net/hyperv/hyperv_net.h+3−2

 	spinlock_t request_lock;
 	struct list_head req_list;
+	struct work_struct mcast_work;
 	u8 hw_mac_adr[ETH_ALEN];
 	u8 rss_key[NETVSC_HASH_KEYLEN];
 	u16 ind_table[ITAB_NUM];
 int rndis_filter_close(struct netvsc_device *nvdev);
 int rndis_filter_device_add(struct hv_device *dev,
 			    struct netvsc_device_info *info);
+void rndis_filter_update(struct netvsc_device *nvdev);
 void rndis_filter_device_remove(struct hv_device *dev,
 				struct netvsc_device *nvdev);
 int rndis_filter_set_rss_param(struct rndis_device *rdev,
 			 struct vmbus_channel *channel,
 			 void *data, u32 buflen);
-int rndis_filter_set_packet_filter(struct rndis_device *dev, u32 new_filter);
 int rndis_filter_set_device_mac(struct net_device *ndev, char *mac);
 void netvsc_switch_datapath(struct net_device *nv_dev, bool vf);
 	/* list protection */
 	spinlock_t lock;
-	struct work_struct work;
 	u32 msg_enable; /* debug level */
 	u32 tx_checksum_mask;

drivers/net/hyperv/netvsc_drv.c+18−36

 module_param(debug, int, S_IRUGO);
 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
-static void do_set_multicast(struct work_struct *w)
-{
-	struct net_device_context *ndevctx =
-		container_of(w, struct net_device_context, work);
-	struct hv_device *device_obj = ndevctx->device_ctx;
-	struct net_device *ndev = hv_get_drvdata(device_obj);
-	struct netvsc_device *nvdev = rcu_dereference(ndevctx->nvdev);
-	struct rndis_device *rdev;
-	if (!nvdev)
-		return;
-	rdev = nvdev->extension;
-	if (rdev == NULL)
-		return;
-	if (ndev->flags & IFF_PROMISC)
-		rndis_filter_set_packet_filter(rdev,
-			NDIS_PACKET_TYPE_PROMISCUOUS);
-	else
-		rndis_filter_set_packet_filter(rdev,
-			NDIS_PACKET_TYPE_BROADCAST |
-			NDIS_PACKET_TYPE_ALL_MULTICAST |
-			NDIS_PACKET_TYPE_DIRECTED);
-}
 static void netvsc_set_multicast_list(struct net_device *net)
 {
 	struct net_device_context *net_device_ctx = netdev_priv(net);
+	struct netvsc_device *nvdev = rtnl_dereference(net_device_ctx->nvdev);
-	schedule_work(&net_device_ctx->work);
+	rndis_filter_update(nvdev);
 }
 static int netvsc_open(struct net_device *net)
 	netif_tx_disable(net);
-	/* Make sure netvsc_set_multicast_list doesn't re-enable filter! */
-	cancel_work_sync(&net_device_ctx->work);
 	ret = rndis_filter_close(nvdev);
 	if (ret != 0) {
 		netdev_err(net, "unable to close device (ret %d).\n", ret);
 static int netvsc_get_sset_count(struct net_device *dev, int string_set)
 {
 	struct net_device_context *ndc = netdev_priv(dev);
-	struct netvsc_device *nvdev = rcu_dereference(ndc->nvdev);
+	struct netvsc_device *nvdev = rtnl_dereference(ndc->nvdev);
 	if (!nvdev)
 		return -ENODEV;
 }
 #ifdef CONFIG_NET_POLL_CONTROLLER
-static void netvsc_poll_controller(struct net_device *net)
+static void netvsc_poll_controller(struct net_device *dev)
 {
-	/* As netvsc_start_xmit() works synchronous we don't have to
+	struct net_device_context *ndc = netdev_priv(dev);
-	 * trigger anything here.
+	struct netvsc_device *ndev;
-	 */
+	int i;
+	rcu_read_lock();
+	ndev = rcu_dereference(ndc->nvdev);
+	if (ndev) {
+		for (i = 0; i < ndev->num_chn; i++) {
+			struct netvsc_channel *nvchan = &ndev->chan_table[i];
+			napi_schedule(&nvchan->napi);
+		}
+	}
+	rcu_read_unlock();
 }
 #endif
 	hv_set_drvdata(dev, net);
 	INIT_DELAYED_WORK(&net_device_ctx->dwork, netvsc_link_change);
-	INIT_WORK(&net_device_ctx->work, do_set_multicast);
 	spin_lock_init(&net_device_ctx->lock);
 	INIT_LIST_HEAD(&net_device_ctx->reconfig_events);
 	netif_device_detach(net);
 	cancel_delayed_work_sync(&ndev_ctx->dwork);
-	cancel_work_sync(&ndev_ctx->work);
 	/*
 	 * Call to the vsc driver to let it know that the device is being

drivers/net/hyperv/rndis_filter.c+29−1

 #include "hyperv_net.h"
+static void rndis_set_multicast(struct work_struct *w);
 #define RNDIS_EXT_LEN PAGE_SIZE
 struct rndis_request {
 	spin_lock_init(&device->request_lock);
 	INIT_LIST_HEAD(&device->req_list);
+	INIT_WORK(&device->mcast_work, rndis_set_multicast);
 	device->state = RNDIS_DEV_UNINITIALIZED;
 	return ret;
 }
-int rndis_filter_set_packet_filter(struct rndis_device *dev, u32 new_filter)
+static int rndis_filter_set_packet_filter(struct rndis_device *dev,
+					  u32 new_filter)
 {
 	struct rndis_request *request;
 	struct rndis_set_request *set;
 	return ret;
 }
+static void rndis_set_multicast(struct work_struct *w)
+{
+	struct rndis_device *rdev
+		= container_of(w, struct rndis_device, mcast_work);
+	if (rdev->ndev->flags & IFF_PROMISC)
+		rndis_filter_set_packet_filter(rdev,
+					       NDIS_PACKET_TYPE_PROMISCUOUS);
+	else
+		rndis_filter_set_packet_filter(rdev,
+					       NDIS_PACKET_TYPE_BROADCAST |
+					       NDIS_PACKET_TYPE_ALL_MULTICAST |
+					       NDIS_PACKET_TYPE_DIRECTED);
+}
+void rndis_filter_update(struct netvsc_device *nvdev)
+{
+	struct rndis_device *rdev = nvdev->extension;
+	schedule_work(&rdev->mcast_work);
+}
 static int rndis_filter_init_device(struct rndis_device *dev)
 {
 	struct rndis_request *request;
 	if (dev->state != RNDIS_DEV_DATAINITIALIZED)
 		return 0;
+	/* Make sure rndis_set_multicast doesn't re-enable filter! */
+	cancel_work_sync(&dev->mcast_work);
 	ret = rndis_filter_set_packet_filter(dev, 0);
 	if (ret == -ENODEV)
 		ret = 0;

drivers/net/ifb.c+2−2

 		__skb_queue_purge(&txp->tq);
 	}
 	kfree(dp->tx_private);
-	free_netdev(dev);
 }
 static void ifb_setup(struct net_device *dev)
 	dev->priv_flags &= ~IFF_TX_SKB_SHARING;
 	netif_keep_dst(dev);
 	eth_hw_addr_random(dev);
-	dev->destructor = ifb_dev_free;
+	dev->needs_free_netdev = true;
+	dev->priv_destructor = ifb_dev_free;
 }
 static netdev_tx_t ifb_xmit(struct sk_buff *skb, struct net_device *dev)

drivers/net/ipvlan/ipvlan_main.c+1−1

@@ -632,7 +632,7 @@ void ipvlan_link_setup(struct net_device *dev) · 631 unmodified lines
632	dev->priv_flags &= ~(IFF_XMIT_DST_RELEASE \| IFF_TX_SKB_SHARING);	632	dev->priv_flags &= ~(IFF_XMIT_DST_RELEASE \| IFF_TX_SKB_SHARING);
633	dev->priv_flags \|= IFF_UNICAST_FLT \| IFF_NO_QUEUE;	633	dev->priv_flags \|= IFF_UNICAST_FLT \| IFF_NO_QUEUE;
634	dev->netdev_ops = &ipvlan_netdev_ops;	634	dev->netdev_ops = &ipvlan_netdev_ops;
635	dev->destructor = free_netdev;	635	dev->needs_free_netdev = true;
636	dev->header_ops = &ipvlan_header_ops;	636	dev->header_ops = &ipvlan_header_ops;
637	dev->ethtool_ops = &ipvlan_ethtool_ops;	637	dev->ethtool_ops = &ipvlan_ethtool_ops;
638	}	638	}

drivers/net/loopback.c+2−2

 {
 	dev_net(dev)->loopback_dev = NULL;
 	free_percpu(dev->lstats);
-	free_netdev(dev);
 }
 static const struct net_device_ops loopback_ops = {
 	dev->ethtool_ops	= &loopback_ethtool_ops;
 	dev->header_ops		= &eth_header_ops;
 	dev->netdev_ops		= &loopback_ops;
-	dev->destructor		= loopback_dev_free;
+	dev->needs_free_netdev	= true;
+	dev->priv_destructor	= loopback_dev_free;
 }
 /* Setup and register the loopback device. */

drivers/net/macsec.c+2−2

 	free_percpu(macsec->secy.tx_sc.stats);
 	dev_put(real_dev);
-	free_netdev(dev);
 }
 static void macsec_setup(struct net_device *dev)
 	dev->max_mtu = ETH_MAX_MTU;
 	dev->priv_flags |= IFF_NO_QUEUE;
 	dev->netdev_ops = &macsec_netdev_ops;
-	dev->destructor = macsec_free_netdev;
+	dev->needs_free_netdev = true;
+	dev->priv_destructor = macsec_free_netdev;
 	SET_NETDEV_DEVTYPE(dev, &macsec_type);
 	eth_zero_addr(dev->broadcast);

drivers/net/macvlan.c+1−1

@@ -1092,7 +1092,7 @@ void macvlan_common_setup(struct net_device *dev) · 1091 unmodified lines
1092	netif_keep_dst(dev);	1092	netif_keep_dst(dev);
1093	dev->priv_flags \|= IFF_UNICAST_FLT;	1093	dev->priv_flags \|= IFF_UNICAST_FLT;
1094	dev->netdev_ops = &macvlan_netdev_ops;	1094	dev->netdev_ops = &macvlan_netdev_ops;
1095	dev->destructor = free_netdev;	1095	dev->needs_free_netdev = true;
1096	dev->header_ops = &macvlan_hard_header_ops;	1096	dev->header_ops = &macvlan_hard_header_ops;
1097	dev->ethtool_ops = &macvlan_ethtool_ops;	1097	dev->ethtool_ops = &macvlan_ethtool_ops;
1098	}	1098	}

drivers/net/netconsole.c+1−1

@@ -358,7 +358,7 @@ static ssize_t enabled_store(struct config_item *item, · 357 unmodified lines
358	if (err)	358	if (err)
359	goto out_unlock;	359	goto out_unlock;
360		360
361	pr_info("netconsole: network logging started\n");	361	pr_info("network logging started\n");
362	} else { /* false */	362	} else { /* false */
363	/* We need to disable the netconsole before cleaning it up	363	/* We need to disable the netconsole before cleaning it up
364	* otherwise we might end up in write_msg() with	364	* otherwise we might end up in write_msg() with

drivers/net/nlmon.c+1−1

@@ -113,7 +113,7 @@ static void nlmon_setup(struct net_device *dev) · 112 unmodified lines
113		113
114	dev->netdev_ops = &nlmon_ops;	114	dev->netdev_ops = &nlmon_ops;
115	dev->ethtool_ops = &nlmon_ethtool_ops;	115	dev->ethtool_ops = &nlmon_ethtool_ops;
116	dev->destructor = free_netdev;	116	dev->needs_free_netdev = true;
117		117
118	dev->features = NETIF_F_SG \| NETIF_F_FRAGLIST \|	118	dev->features = NETIF_F_SG \| NETIF_F_FRAGLIST \|
119	NETIF_F_HIGHDMA \| NETIF_F_LLTX;	119	NETIF_F_HIGHDMA \| NETIF_F_LLTX;

drivers/net/phy/Kconfig+1−0

@@ -127,6 +127,7 @@ config MDIO_THUNDER · 126 unmodified lines
127	tristate "ThunderX SOCs MDIO buses"	127	tristate "ThunderX SOCs MDIO buses"
128	depends on 64BIT	128	depends on 64BIT
129	depends on PCI	129	depends on PCI
		130	depends on !(MDIO_DEVICE=y && PHYLIB=m)
130	select MDIO_CAVIUM	131	select MDIO_CAVIUM
131	help	132	help
132	This driver supports the MDIO interfaces found on Cavium	133	This driver supports the MDIO interfaces found on Cavium

drivers/net/phy/marvell.c+0−2

@@ -1127,8 +1127,6 @@ static int marvell_read_status_page(struct phy_device *phydev, int page) · 1126 unmodified lines
1127	if (adv < 0)	1127	if (adv < 0)
1128	return adv;	1128	return adv;
1129		1129
1130	lpa &= adv;
1131
1132	if (status & MII_M1011_PHY_STATUS_FULLDUPLEX)	1130	if (status & MII_M1011_PHY_STATUS_FULLDUPLEX)
1133	phydev->duplex = DUPLEX_FULL;	1131	phydev->duplex = DUPLEX_FULL;
1134	else	1132	else

drivers/net/phy/mdio_bus.c+13−0

@@ -658,6 +658,18 @@ static int mdio_bus_match(struct device dev, struct device_driver drv) · 657 unmodified lines
658	return 0;	658	return 0;
659	}	659	}
660		660
		661	static int mdio_uevent(struct device dev, struct kobj_uevent_env env)
		662	{
		663	int rc;
		664
		665	/* Some devices have extra OF data and an OF-style MODALIAS */
		666	rc = of_device_uevent_modalias(dev, env);
		667	if (rc != -ENODEV)
		668	return rc;
		669
		670	return 0;
		671	}
		672
661	#ifdef CONFIG_PM	673	#ifdef CONFIG_PM
662	static int mdio_bus_suspend(struct device *dev)	674	static int mdio_bus_suspend(struct device *dev)
663	{	675	{
@@ -708,6 +720,7 @@ static const struct dev_pm_ops mdio_bus_pm_ops = { · 44 unmodified lines
708	struct bus_type mdio_bus_type = {	720	struct bus_type mdio_bus_type = {
709	.name = "mdio_bus",	721	.name = "mdio_bus",
710	.match = mdio_bus_match,	722	.match = mdio_bus_match,
		723	.uevent = mdio_uevent,
711	.pm = MDIO_BUS_PM_OPS,	724	.pm = MDIO_BUS_PM_OPS,
712	};	725	};
713	EXPORT_SYMBOL(mdio_bus_type);	726	EXPORT_SYMBOL(mdio_bus_type);

drivers/net/phy/micrel.c+28−14

 	return ret;
 }
-static int kszphy_config_init(struct phy_device *phydev)
+/* Some config bits need to be set again on resume, handle them here. */
+static int kszphy_config_reset(struct phy_device *phydev)
 {
 	struct kszphy_priv *priv = phydev->priv;
-	const struct kszphy_type *type;
 	int ret;
-	if (!priv)
-		return 0;
-	type = priv->type;
-	if (type->has_broadcast_disable)
-		kszphy_broadcast_disable(phydev);
-	if (type->has_nand_tree_disable)
-		kszphy_nand_tree_disable(phydev);
 	if (priv->rmii_ref_clk_sel) {
 		ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val);
 		if (ret) {
 	}
 	if (priv->led_mode >= 0)
-		kszphy_setup_led(phydev, type->led_mode_reg, priv->led_mode);
+		kszphy_setup_led(phydev, priv->type->led_mode_reg, priv->led_mode);
 	return 0;
 }
+static int kszphy_config_init(struct phy_device *phydev)
+{
+	struct kszphy_priv *priv = phydev->priv;
+	const struct kszphy_type *type;
+	if (!priv)
+		return 0;
+	type = priv->type;
+	if (type->has_broadcast_disable)
+		kszphy_broadcast_disable(phydev);
+	if (type->has_nand_tree_disable)
+		kszphy_nand_tree_disable(phydev);
+	return kszphy_config_reset(phydev);
+}
 static int ksz8041_config_init(struct phy_device *phydev)
 {
 	struct device_node *of_node = phydev->mdio.dev.of_node;
 static int kszphy_resume(struct phy_device *phydev)
 {
+	int ret;
 	genphy_resume(phydev);
+	ret = kszphy_config_reset(phydev);
+	if (ret)
+		return ret;
 	/* Enable PHY Interrupts */
 	if (phy_interrupt_is_valid(phydev)) {
 		phydev->interrupts = PHY_INTERRUPT_ENABLED;

drivers/net/phy/phy.c+3−1

 		return "5Gbps";
 	case SPEED_10000:
 		return "10Gbps";
+	case SPEED_14000:
+		return "14Gbps";
 	case SPEED_20000:
 		return "20Gbps";
 	case SPEED_25000:
  * phy_lookup_setting - lookup a PHY setting
  * @speed: speed to match
  * @duplex: duplex to match
- * @feature: allowed link modes
+ * @features: allowed link modes
  * @exact: an exact match is required
  *
  * Search the settings array for a setting that matches the speed and

drivers/net/slip/slip.c+3−4

@@ -629,7 +629,7 @@ static void sl_uninit(struct net_device *dev) · 628 unmodified lines
629	static void sl_free_netdev(struct net_device *dev)	629	static void sl_free_netdev(struct net_device *dev)
630	{	630	{
631	int i = dev->base_addr;	631	int i = dev->base_addr;
632	free_netdev(dev);	632
633	slip_devs[i] = NULL;	633	slip_devs[i] = NULL;
634	}	634	}
635		635
@@ -651,7 +651,8 @@ static const struct net_device_ops sl_netdev_ops = { · 15 unmodified lines
651	static void sl_setup(struct net_device *dev)	651	static void sl_setup(struct net_device *dev)
652	{	652	{
653	dev->netdev_ops = &sl_netdev_ops;	653	dev->netdev_ops = &sl_netdev_ops;
654	dev->destructor = sl_free_netdev;	654	dev->needs_free_netdev = true;
		655	dev->priv_destructor = sl_free_netdev;
655		656
656	dev->hard_header_len = 0;	657	dev->hard_header_len = 0;
657	dev->addr_len = 0;	658	dev->addr_len = 0;
@@ -1369,8 +1370,6 @@ static void __exit slip_exit(void) · 711 unmodified lines
1369	if (sl->tty) {	1370	if (sl->tty) {
1370	printk(KERN_ERR "%s: tty discipline still running\n",	1371	printk(KERN_ERR "%s: tty discipline still running\n",
1371	dev->name);	1372	dev->name);
1372	/* Intentionally leak the control block. */
1373	dev->destructor = NULL;
1374	}	1373	}
1375		1374
1376	unregister_netdev(dev);	1375	unregister_netdev(dev);

drivers/net/team/team.c+2−2

 	struct team *team = netdev_priv(dev);
 	free_percpu(team->pcpu_stats);
-	free_netdev(dev);
 }
 static int team_open(struct net_device *dev)
 	dev->netdev_ops = &team_netdev_ops;
 	dev->ethtool_ops = &team_ethtool_ops;
-	dev->destructor	= team_destructor;
+	dev->needs_free_netdev = true;
+	dev->priv_destructor = team_destructor;
 	dev->priv_flags &= ~(IFF_XMIT_DST_RELEASE | IFF_TX_SKB_SHARING);
 	dev->priv_flags |= IFF_NO_QUEUE;
 	dev->priv_flags |= IFF_TEAM;

drivers/net/tun.c+2−2

 	free_percpu(tun->pcpu_stats);
 	tun_flow_uninit(tun);
 	security_tun_dev_free_security(tun->security);
-	free_netdev(dev);
 }
 static void tun_setup(struct net_device *dev)
 	tun->group = INVALID_GID;
 	dev->ethtool_ops = &tun_ethtool_ops;
-	dev->destructor = tun_free_netdev;
+	dev->needs_free_netdev = true;
+	dev->priv_destructor = tun_free_netdev;
 	/* We prefer our own queue length */
 	dev->tx_queue_len = TUN_READQ_SIZE;
 }

drivers/net/usb/cdc-phonet.c+1−1

@@ -298,7 +298,7 @@ static void usbpn_setup(struct net_device *dev) · 297 unmodified lines
298	dev->addr_len = 1;	298	dev->addr_len = 1;
299	dev->tx_queue_len = 3;	299	dev->tx_queue_len = 3;
300		300
301	dev->destructor = free_netdev;	301	dev->needs_free_netdev = true;
302	}	302	}
303		303
304	/*	304	/*

drivers/net/usb/qmi_wwan.c+5−1

 	dev->addr_len        = 0;
 	dev->flags           = IFF_POINTOPOINT | IFF_NOARP | IFF_MULTICAST;
 	dev->netdev_ops      = &qmimux_netdev_ops;
-	dev->destructor      = free_netdev;
+	dev->needs_free_netdev = true;
 }
 static struct net_device *qmimux_find_dev(struct usbnet *dev, u8 mux_id)
 	{QMI_FIXED_INTF(0x1199, 0x9056, 8)},	/* Sierra Wireless Modem */
 	{QMI_FIXED_INTF(0x1199, 0x9057, 8)},
 	{QMI_FIXED_INTF(0x1199, 0x9061, 8)},	/* Sierra Wireless Modem */
+	{QMI_FIXED_INTF(0x1199, 0x9063, 8)},	/* Sierra Wireless EM7305 */
+	{QMI_FIXED_INTF(0x1199, 0x9063, 10)},	/* Sierra Wireless EM7305 */
 	{QMI_FIXED_INTF(0x1199, 0x9071, 8)},	/* Sierra Wireless MC74xx */
 	{QMI_FIXED_INTF(0x1199, 0x9071, 10)},	/* Sierra Wireless MC74xx */
 	{QMI_FIXED_INTF(0x1199, 0x9079, 8)},	/* Sierra Wireless EM74xx */
 	{QMI_FIXED_INTF(0x1bc7, 0x1100, 3)},	/* Telit ME910 */
 	{QMI_FIXED_INTF(0x1bc7, 0x1200, 5)},	/* Telit LE920 */
 	{QMI_QUIRK_SET_DTR(0x1bc7, 0x1201, 2)},	/* Telit LE920, LE920A4 */
+	{QMI_FIXED_INTF(0x1c9e, 0x9801, 3)},	/* Telewell TW-3G HSPA+ */
+	{QMI_FIXED_INTF(0x1c9e, 0x9803, 4)},	/* Telewell TW-3G HSPA+ */
 	{QMI_FIXED_INTF(0x1c9e, 0x9b01, 3)},	/* XS Stick W100-2 from 4G Systems */
 	{QMI_FIXED_INTF(0x0b3c, 0xc000, 4)},	/* Olivetti Olicard 100 */
 	{QMI_FIXED_INTF(0x0b3c, 0xc001, 4)},	/* Olivetti Olicard 120 */

drivers/net/usb/r8152.c+2−0

@@ -4368,6 +4368,8 @@ static u8 rtl_get_version(struct usb_interface *intf) · 4367 unmodified lines
4368	break;	4368	break;
4369	}	4369	}
4370		4370
		4371	dev_dbg(&intf->dev, "Detected version 0x%04x\n", version);
		4372
4371	return version;	4373	return version;
4372	}	4374	}
4373		4375

drivers/net/veth.c+2−2

 static void veth_dev_free(struct net_device *dev)
 {
 	free_percpu(dev->vstats);
-	free_netdev(dev);
 }
 #ifdef CONFIG_NET_POLL_CONTROLLER
 			       NETIF_F_HW_VLAN_STAG_TX |
 			       NETIF_F_HW_VLAN_CTAG_RX |
 			       NETIF_F_HW_VLAN_STAG_RX);
-	dev->destructor = veth_dev_free;
+	dev->needs_free_netdev = true;
+	dev->priv_destructor = veth_dev_free;
 	dev->max_mtu = ETH_MAX_MTU;
 	dev->hw_features = VETH_FEATURES;

drivers/net/virtio_net.c+3−2

 	unsigned int len;
 	len = hdr_len + clamp_t(unsigned int, ewma_pkt_len_read(avg_pkt_len),
-				rq->min_buf_len - hdr_len, PAGE_SIZE - hdr_len);
+				rq->min_buf_len, PAGE_SIZE - hdr_len);
 	return ALIGN(len, L1_CACHE_BYTES);
 }
 	unsigned int buf_len = hdr_len + ETH_HLEN + VLAN_HLEN + packet_len;
 	unsigned int min_buf_len = DIV_ROUND_UP(buf_len, rq_size);
-	return max(min_buf_len, hdr_len);
+	return max(max(min_buf_len, hdr_len) - hdr_len,
+		   (unsigned int)GOOD_PACKET_LEN);
 }
 static int virtnet_find_vqs(struct virtnet_info *vi)

drivers/net/vrf.c+33−5

@@ -36,12 +36,14 @@ · 35 unmodified lines
36	#include <net/addrconf.h>	36	#include <net/addrconf.h>
37	#include <net/l3mdev.h>	37	#include <net/l3mdev.h>
38	#include <net/fib_rules.h>	38	#include <net/fib_rules.h>
		39	#include <net/netns/generic.h>
39		40
40	#define DRV_NAME "vrf"	41	#define DRV_NAME "vrf"
41	#define DRV_VERSION "1.0"	42	#define DRV_VERSION "1.0"
42		43
43	#define FIB_RULE_PREF 1000 /* default preference for FIB rules */	44	#define FIB_RULE_PREF 1000 /* default preference for FIB rules */
44	static bool add_fib_rules = true;	45
		46	static unsigned int vrf_net_id;
45		47
46	struct net_vrf {	48	struct net_vrf {
47	struct rtable __rcu *rth;	49	struct rtable __rcu *rth;
@@ -1348,7 +1350,7 @@ static void vrf_setup(struct net_device *dev) · 1300 unmodified lines
1348	dev->netdev_ops = &vrf_netdev_ops;	1350	dev->netdev_ops = &vrf_netdev_ops;
1349	dev->l3mdev_ops = &vrf_l3mdev_ops;	1351	dev->l3mdev_ops = &vrf_l3mdev_ops;
1350	dev->ethtool_ops = &vrf_ethtool_ops;	1352	dev->ethtool_ops = &vrf_ethtool_ops;
1351	dev->destructor = free_netdev;	1353	dev->needs_free_netdev = true;
1352		1354
1353	/* Fill in device structure with ethernet-generic values. */	1355	/* Fill in device structure with ethernet-generic values. */
1354	eth_hw_addr_random(dev);	1356	eth_hw_addr_random(dev);
@@ -1394,6 +1396,8 @@ static int vrf_newlink(struct net src_net, struct net_device dev, · 39 unmodified lines
1394	struct nlattr tb[], struct nlattr data[])	1396	struct nlattr tb[], struct nlattr data[])
1395	{	1397	{
1396	struct net_vrf *vrf = netdev_priv(dev);	1398	struct net_vrf *vrf = netdev_priv(dev);
		1399	bool *add_fib_rules;
		1400	struct net *net;
1397	int err;	1401	int err;
1398		1402
1399	if (!data \|\| !data[IFLA_VRF_TABLE])	1403	if (!data \|\| !data[IFLA_VRF_TABLE])
@@ -1409,13 +1413,15 @@ static int vrf_newlink(struct net src_net, struct net_device dev, · 9 unmodified lines
1409	if (err)	1413	if (err)
1410	goto out;	1414	goto out;
1411		1415
1412	if (add_fib_rules) {	1416	net = dev_net(dev);
		1417	add_fib_rules = net_generic(net, vrf_net_id);
		1418	if (*add_fib_rules) {
1413	err = vrf_add_fib_rules(dev);	1419	err = vrf_add_fib_rules(dev);
1414	if (err) {	1420	if (err) {
1415	unregister_netdevice(dev);	1421	unregister_netdevice(dev);
1416	goto out;	1422	goto out;
1417	}	1423	}
1418	add_fib_rules = false;	1424	*add_fib_rules = false;
1419	}	1425	}
1420		1426
1421	out:	1427	out:
@@ -1498,16 +1504,38 @@ static struct notifier_block vrf_notifier_block __read_mostly = { · 76 unmodified lines
1498	.notifier_call = vrf_device_event,	1504	.notifier_call = vrf_device_event,
1499	};	1505	};
1500		1506
		1507	/* Initialize per network namespace state */
		1508	static int __net_init vrf_netns_init(struct net *net)
		1509	{
		1510	bool *add_fib_rules = net_generic(net, vrf_net_id);
		1511
		1512	*add_fib_rules = true;
		1513
		1514	return 0;
		1515	}
		1516
		1517	static struct pernet_operations vrf_net_ops __net_initdata = {
		1518	.init = vrf_netns_init,
		1519	.id = &vrf_net_id,
		1520	.size = sizeof(bool),
		1521	};
		1522
1501	static int __init vrf_init_module(void)	1523	static int __init vrf_init_module(void)
1502	{	1524	{
1503	int rc;	1525	int rc;
1504		1526
1505	register_netdevice_notifier(&vrf_notifier_block);	1527	register_netdevice_notifier(&vrf_notifier_block);
1506		1528
1507	rc = rtnl_link_register(&vrf_link_ops);	1529	rc = register_pernet_subsys(&vrf_net_ops);
1508	if (rc < 0)	1530	if (rc < 0)
1509	goto error;	1531	goto error;
1510		1532
		1533	rc = rtnl_link_register(&vrf_link_ops);
		1534	if (rc < 0) {
		1535	unregister_pernet_subsys(&vrf_net_ops);
		1536	goto error;
		1537	}
		1538
1511	return 0;	1539	return 0;
1512		1540
1513	error:	1541	error:

drivers/net/vsockmon.c+1−1

@@ -135,7 +135,7 @@ static void vsockmon_setup(struct net_device *dev) · 134 unmodified lines
135		135
136	dev->netdev_ops = &vsockmon_ops;	136	dev->netdev_ops = &vsockmon_ops;
137	dev->ethtool_ops = &vsockmon_ethtool_ops;	137	dev->ethtool_ops = &vsockmon_ethtool_ops;
138	dev->destructor = free_netdev;	138	dev->needs_free_netdev = true;
139		139
140	dev->features = NETIF_F_SG \| NETIF_F_FRAGLIST \|	140	dev->features = NETIF_F_SG \| NETIF_F_FRAGLIST \|
141	NETIF_F_HIGHDMA \| NETIF_F_LLTX;	141	NETIF_F_HIGHDMA \| NETIF_F_LLTX;

drivers/net/vxlan.c+31−10

 static int vxlan_sock_add(struct vxlan_dev *vxlan);
+static void vxlan_vs_del_dev(struct vxlan_dev *vxlan);
 /* per-network namespace private data for this module */
 struct vxlan_net {
 	struct list_head  vxlan_list;
 	call_rcu(&f->rcu, vxlan_fdb_free);
 }
+static void vxlan_dst_free(struct rcu_head *head)
+{
+	struct vxlan_rdst *rd = container_of(head, struct vxlan_rdst, rcu);
+	dst_cache_destroy(&rd->dst_cache);
+	kfree(rd);
+}
+static void vxlan_fdb_dst_destroy(struct vxlan_dev *vxlan, struct vxlan_fdb *f,
+				  struct vxlan_rdst *rd)
+{
+	list_del_rcu(&rd->list);
+	vxlan_fdb_notify(vxlan, f, rd, RTM_DELNEIGH);
+	call_rcu(&rd->rcu, vxlan_dst_free);
+}
 static int vxlan_fdb_parse(struct nlattr *tb[], struct vxlan_dev *vxlan,
 			   union vxlan_addr *ip, __be16 *port, __be32 *src_vni,
 			   __be32 *vni, u32 *ifindex)
 	 * otherwise destroy the fdb entry
 	 */
 	if (rd && !list_is_singular(&f->remotes)) {
-		list_del_rcu(&rd->list);
+		vxlan_fdb_dst_destroy(vxlan, f, rd);
-		vxlan_fdb_notify(vxlan, f, rd, RTM_DELNEIGH);
-		kfree_rcu(rd, rcu);
 		goto out;
 	}
 	rcu_assign_pointer(vxlan->vn4_sock, NULL);
 	synchronize_net();
+	vxlan_vs_del_dev(vxlan);
 	if (__vxlan_sock_release_prep(sock4)) {
 		udp_tunnel_sock_release(sock4->sock);
 		kfree(sock4);
 	mod_timer(&vxlan->age_timer, next_timer);
 }
+static void vxlan_vs_del_dev(struct vxlan_dev *vxlan)
+{
+	struct vxlan_net *vn = net_generic(vxlan->net, vxlan_net_id);
+	spin_lock(&vn->sock_lock);
+	hlist_del_init_rcu(&vxlan->hlist);
+	spin_unlock(&vn->sock_lock);
+}
 static void vxlan_vs_add_dev(struct vxlan_sock *vs, struct vxlan_dev *vxlan)
 {
 	struct vxlan_net *vn = net_generic(vxlan->net, vxlan_net_id);
 	eth_hw_addr_random(dev);
 	ether_setup(dev);
-	dev->destructor = free_netdev;
+	dev->needs_free_netdev = true;
 	SET_NETDEV_DEVTYPE(dev, &vxlan_type);
 	dev->features	|= NETIF_F_LLTX;
 static void vxlan_dellink(struct net_device *dev, struct list_head *head)
 {
 	struct vxlan_dev *vxlan = netdev_priv(dev);
-	struct vxlan_net *vn = net_generic(vxlan->net, vxlan_net_id);
 	vxlan_flush(vxlan, true);
-	spin_lock(&vn->sock_lock);
-	if (!hlist_unhashed(&vxlan->hlist))
-		hlist_del_rcu(&vxlan->hlist);
-	spin_unlock(&vn->sock_lock);
 	gro_cells_destroy(&vxlan->gro_cells);
 	list_del(&vxlan->next);
 	unregister_netdevice_queue(dev, head);

drivers/net/wan/dlci.c+1−1

@@ -475,7 +475,7 @@ static void dlci_setup(struct net_device *dev) · 474 unmodified lines
475	dev->flags = 0;	475	dev->flags = 0;
476	dev->header_ops = &dlci_header_ops;	476	dev->header_ops = &dlci_header_ops;
477	dev->netdev_ops = &dlci_netdev_ops;	477	dev->netdev_ops = &dlci_netdev_ops;
478	dev->destructor = free_netdev;	478	dev->needs_free_netdev = true;
479		479
480	dlp->receive = dlci_receive;	480	dlp->receive = dlci_receive;
481		481

drivers/net/wan/hdlc_fr.c+1−1

@@ -1106,7 +1106,7 @@ static int fr_add_pvc(struct net_device *frad, unsigned int dlci, int type) · 1105 unmodified lines
1106	return -EIO;	1106	return -EIO;
1107	}	1107	}
1108		1108
1109	dev->destructor = free_netdev;	1109	dev->needs_free_netdev = true;
1110	*get_dev_p(pvc, type) = dev;	1110	*get_dev_p(pvc, type) = dev;
1111	if (!used) {	1111	if (!used) {
1112	state(hdlc)->dce_changed = 1;	1112	state(hdlc)->dce_changed = 1;

drivers/net/wan/lapbether.c+1−1

@@ -306,7 +306,7 @@ static const struct net_device_ops lapbeth_netdev_ops = { · 305 unmodified lines
306	static void lapbeth_setup(struct net_device *dev)	306	static void lapbeth_setup(struct net_device *dev)
307	{	307	{
308	dev->netdev_ops = &lapbeth_netdev_ops;	308	dev->netdev_ops = &lapbeth_netdev_ops;
309	dev->destructor = free_netdev;	309	dev->needs_free_netdev = true;
310	dev->type = ARPHRD_X25;	310	dev->type = ARPHRD_X25;
311	dev->hard_header_len = 3;	311	dev->hard_header_len = 3;
312	dev->mtu = 1000;	312	dev->mtu = 1000;

drivers/net/wireless/ath/ath6kl/main.c+1−1

@@ -1287,7 +1287,7 @@ void init_netdev(struct net_device *dev) · 1286 unmodified lines
1287	struct ath6kl *ar = ath6kl_priv(dev);	1287	struct ath6kl *ar = ath6kl_priv(dev);
1288		1288
1289	dev->netdev_ops = &ath6kl_netdev_ops;	1289	dev->netdev_ops = &ath6kl_netdev_ops;
1290	dev->destructor = free_netdev;	1290	dev->needs_free_netdev = true;
1291	dev->watchdog_timeo = ATH6KL_TX_TIMEOUT;	1291	dev->watchdog_timeo = ATH6KL_TX_TIMEOUT;
1292		1292
1293	dev->needed_headroom = ETH_HLEN;	1293	dev->needed_headroom = ETH_HLEN;

drivers/net/wireless/ath/wcn36xx/main.c+2−0

@@ -1271,6 +1271,8 @@ static int wcn36xx_remove(struct platform_device *pdev) · 1270 unmodified lines
1271	qcom_smem_state_put(wcn->tx_enable_state);	1271	qcom_smem_state_put(wcn->tx_enable_state);
1272	qcom_smem_state_put(wcn->tx_rings_empty_state);	1272	qcom_smem_state_put(wcn->tx_rings_empty_state);
1273		1273
		1274	rpmsg_destroy_ept(wcn->smd_channel);
		1275
1274	iounmap(wcn->dxe_base);	1276	iounmap(wcn->dxe_base);
1275	iounmap(wcn->ccu_base);	1277	iounmap(wcn->ccu_base);
1276		1278

drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c+0−1

@@ -5225,7 +5225,6 @@ void brcmf_cfg80211_free_netdev(struct net_device *ndev) · 5224 unmodified lines
5225		5225
5226	if (vif)	5226	if (vif)
5227	brcmf_free_vif(vif);	5227	brcmf_free_vif(vif);
5228	free_netdev(ndev);
5229	}	5228	}
5230		5229
5231	static bool brcmf_is_linkup(const struct brcmf_event_msg *e)	5230	static bool brcmf_is_linkup(const struct brcmf_event_msg *e)

drivers/net/wireless/broadcom/brcm80211/brcmfmac/core.c+2−1

@@ -624,7 +624,8 @@ struct brcmf_if brcmf_add_if(struct brcmf_pub drvr, s32 bsscfgidx, s32 ifidx, · 623 unmodified lines
624	if (!ndev)	624	if (!ndev)
625	return ERR_PTR(-ENOMEM);	625	return ERR_PTR(-ENOMEM);
626		626
627	ndev->destructor = brcmf_cfg80211_free_netdev;	627	ndev->needs_free_netdev = true;
		628	ndev->priv_destructor = brcmf_cfg80211_free_netdev;
628	ifp = netdev_priv(ndev);	629	ifp = netdev_priv(ndev);
629	ifp->ndev = ndev;	630	ifp->ndev = ndev;
630	/* store mapping ifidx to bsscfgidx */	631	/* store mapping ifidx to bsscfgidx */

drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c+1−1

@@ -3422,7 +3422,7 @@ static int brcmf_sdio_bus_preinit(struct device *dev) · 3421 unmodified lines
3422	/* otherwise, set txglomalign */	3422	/* otherwise, set txglomalign */
3423	value = sdiodev->settings->bus.sdio.sd_sgentry_align;	3423	value = sdiodev->settings->bus.sdio.sd_sgentry_align;
3424	/* SDIO ADMA requires at least 32 bit alignment */	3424	/* SDIO ADMA requires at least 32 bit alignment */
3425	value = max_t(u32, value, 4);	3425	value = max_t(u32, value, ALIGNMENT);
3426	err = brcmf_iovar_data_set(dev, "bus:txglomalign", &value,	3426	err = brcmf_iovar_data_set(dev, "bus:txglomalign", &value,
3427	sizeof(u32));	3427	sizeof(u32));
3428	}	3428	}

drivers/net/wireless/intel/iwlwifi/iwl-7000.c+2−2

@@ -79,8 +79,8 @@ · 78 unmodified lines
79	/* Lowest firmware API version supported */	79	/* Lowest firmware API version supported */
80	#define IWL7260_UCODE_API_MIN 17	80	#define IWL7260_UCODE_API_MIN 17
81	#define IWL7265_UCODE_API_MIN 17	81	#define IWL7265_UCODE_API_MIN 17
82	#define IWL7265D_UCODE_API_MIN 17	82	#define IWL7265D_UCODE_API_MIN 22
83	#define IWL3168_UCODE_API_MIN 20	83	#define IWL3168_UCODE_API_MIN 22
84		84
85	/* NVM versions */	85	/* NVM versions */
86	#define IWL7260_NVM_VERSION 0x0a1d	86	#define IWL7260_NVM_VERSION 0x0a1d

drivers/net/wireless/intel/iwlwifi/iwl-8000.c+2−2

@@ -74,8 +74,8 @@ · 73 unmodified lines
74	#define IWL8265_UCODE_API_MAX 30	74	#define IWL8265_UCODE_API_MAX 30
75		75
76	/* Lowest firmware API version supported */	76	/* Lowest firmware API version supported */
77	#define IWL8000_UCODE_API_MIN 17	77	#define IWL8000_UCODE_API_MIN 22
78	#define IWL8265_UCODE_API_MIN 20	78	#define IWL8265_UCODE_API_MIN 22
79		79
80	/* NVM versions */	80	/* NVM versions */
81	#define IWL8000_NVM_VERSION 0x0a1d	81	#define IWL8000_NVM_VERSION 0x0a1d

drivers/net/wireless/intel/iwlwifi/iwl-prph.h+1−0

@@ -370,6 +370,7 @@ · 369 unmodified lines
370	#define MON_DMARB_RD_DATA_ADDR (0xa03c5c)	370	#define MON_DMARB_RD_DATA_ADDR (0xa03c5c)
371		371
372	#define DBGC_IN_SAMPLE (0xa03c00)	372	#define DBGC_IN_SAMPLE (0xa03c00)
		373	#define DBGC_OUT_CTRL (0xa03c0c)
373		374
374	/* enable the ID buf for read */	375	/* enable the ID buf for read */
375	#define WFPM_PS_CTL_CLR 0xA0300C	376	#define WFPM_PS_CTL_CLR 0xA0300C

drivers/net/wireless/intel/iwlwifi/mvm/fw-api-rs.h+5−0

 /* Bit 1-3: LQ command color. Used to match responses to LQ commands */
 #define LQ_FLAG_COLOR_POS               1
 #define LQ_FLAG_COLOR_MSK               (7 << LQ_FLAG_COLOR_POS)
+#define LQ_FLAG_COLOR_GET(_f)		(((_f) & LQ_FLAG_COLOR_MSK) >>\
+					 LQ_FLAG_COLOR_POS)
+#define LQ_FLAGS_COLOR_INC(_c)		((((_c) + 1) << LQ_FLAG_COLOR_POS) &\
+					 LQ_FLAG_COLOR_MSK)
+#define LQ_FLAG_COLOR_SET(_f, _c)	((_c) | ((_f) & ~LQ_FLAG_COLOR_MSK))
 /* Bit 4-5: Tx RTS BW Signalling
  * (0) No RTS BW signalling

drivers/net/wireless/intel/iwlwifi/mvm/fw-api-tx.h+3−0

  * bit-7 invalid rate indication
  */
 #define TX_RES_INIT_RATE_INDEX_MSK 0x0f
+#define TX_RES_RATE_TABLE_COLOR_POS 4
 #define TX_RES_RATE_TABLE_COLOR_MSK 0x70
 #define TX_RES_INV_RATE_INDEX_MSK 0x80
+#define TX_RES_RATE_TABLE_COL_GET(_f) (((_f) & TX_RES_RATE_TABLE_COLOR_MSK) >>\
+				       TX_RES_RATE_TABLE_COLOR_POS)
 #define IWL_MVM_TX_RES_GET_TID(_ra_tid) ((_ra_tid) & 0x0f)
 #define IWL_MVM_TX_RES_GET_RA(_ra_tid) ((_ra_tid) >> 4)

drivers/net/wireless/intel/iwlwifi/mvm/fw-dbg.c+1−11

 	return 0;
 }
-static inline void iwl_mvm_restart_early_start(struct iwl_mvm *mvm)
-{
-	if (mvm->cfg->device_family == IWL_DEVICE_FAMILY_7000)
-		iwl_clear_bits_prph(mvm->trans, MON_BUFF_SAMPLE_CTL, 0x100);
-	else
-		iwl_write_prph(mvm->trans, DBGC_IN_SAMPLE, 1);
-}
 int iwl_mvm_start_fw_dbg_conf(struct iwl_mvm *mvm, u8 conf_id)
 {
 	u8 *ptr;
 	/* EARLY START - firmware's configuration is hard coded */
 	if ((!mvm->fw->dbg_conf_tlv[conf_id] ||
 	     !mvm->fw->dbg_conf_tlv[conf_id]->num_of_hcmds) &&
-	    conf_id == FW_DBG_START_FROM_ALIVE) {
+	    conf_id == FW_DBG_START_FROM_ALIVE)
-		iwl_mvm_restart_early_start(mvm);
 		return 0;
-	}
 	if (!mvm->fw->dbg_conf_tlv[conf_id])
 		return -EINVAL;

drivers/net/wireless/intel/iwlwifi/mvm/mac-ctxt.c+1−1

@@ -1040,7 +1040,7 @@ static int iwl_mvm_mac_ctxt_send_beacon(struct iwl_mvm *mvm, · 1039 unmodified lines
1040	struct iwl_mac_beacon_cmd_v6 beacon_cmd_v6;	1040	struct iwl_mac_beacon_cmd_v6 beacon_cmd_v6;
1041	struct iwl_mac_beacon_cmd_v7 beacon_cmd;	1041	struct iwl_mac_beacon_cmd_v7 beacon_cmd;
1042	} u = {};	1042	} u = {};
1043	struct iwl_mac_beacon_cmd beacon_cmd;	1043	struct iwl_mac_beacon_cmd beacon_cmd = {};
1044	struct ieee80211_tx_info *info;	1044	struct ieee80211_tx_info *info;
1045	u32 beacon_skb_len;	1045	u32 beacon_skb_len;
1046	u32 rate, tx_flags;	1046	u32 rate, tx_flags;

drivers/net/wireless/intel/iwlwifi/mvm/mvm.h+5−1

  */
 static inline u32 iwl_mvm_flushable_queues(struct iwl_mvm *mvm)
 {
+	u32 cmd_queue = iwl_mvm_is_dqa_supported(mvm) ? IWL_MVM_DQA_CMD_QUEUE :
+		IWL_MVM_CMD_QUEUE;
 	return ((BIT(mvm->cfg->base_params->num_of_queues) - 1) &
-		~BIT(IWL_MVM_CMD_QUEUE));
+		~BIT(cmd_queue));
 }
 static inline
 	if (!iwl_mvm_has_new_tx_api(mvm))
 		iwl_free_fw_paging(mvm);
 	mvm->ucode_loaded = false;
+	mvm->fw_dbg_conf = FW_DBG_INVALID;
 	iwl_trans_stop_device(mvm->trans);
 }

drivers/net/wireless/intel/iwlwifi/mvm/ops.c+24−8

 	mutex_lock(&mvm->mutex);
-	/* stop recording */
 	if (mvm->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
+		/* stop recording */
 		iwl_set_bits_prph(mvm->trans, MON_BUFF_SAMPLE_CTL, 0x100);
+		iwl_mvm_fw_error_dump(mvm);
+		/* start recording again if the firmware is not crashed */
+		if (!test_bit(STATUS_FW_ERROR, &mvm->trans->status) &&
+		    mvm->fw->dbg_dest_tlv)
+			iwl_clear_bits_prph(mvm->trans,
+					    MON_BUFF_SAMPLE_CTL, 0x100);
 	} else {
+		u32 in_sample = iwl_read_prph(mvm->trans, DBGC_IN_SAMPLE);
+		u32 out_ctrl = iwl_read_prph(mvm->trans, DBGC_OUT_CTRL);
+		/* stop recording */
 		iwl_write_prph(mvm->trans, DBGC_IN_SAMPLE, 0);
-		/* wait before we collect the data till the DBGC stop */
 		udelay(100);
-	}
+		iwl_write_prph(mvm->trans, DBGC_OUT_CTRL, 0);
+		/* wait before we collect the data till the DBGC stop */
+		udelay(500);
-	iwl_mvm_fw_error_dump(mvm);
+		iwl_mvm_fw_error_dump(mvm);
-	/* start recording again if the firmware is not crashed */
+		/* start recording again if the firmware is not crashed */
-	WARN_ON_ONCE((!test_bit(STATUS_FW_ERROR, &mvm->trans->status)) &&
+		if (!test_bit(STATUS_FW_ERROR, &mvm->trans->status) &&
-		     mvm->fw->dbg_dest_tlv &&
+		    mvm->fw->dbg_dest_tlv) {
-		     iwl_mvm_start_fw_dbg_conf(mvm, mvm->fw_dbg_conf));
+			iwl_write_prph(mvm->trans, DBGC_IN_SAMPLE, in_sample);
+			iwl_write_prph(mvm->trans, DBGC_OUT_CTRL, out_ctrl);
+		}
+	}
 	mutex_unlock(&mvm->mutex);

drivers/net/wireless/intel/iwlwifi/mvm/rs.c+11−35

  *
  * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
- * Copyright(c) 2016 Intel Deutschland GmbH
+ * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms of version 2 of the GNU General Public License as
 		rs_get_lower_rate_in_column(lq_sta, rate);
 }
-/* Check if both rates are identical
- * allow_ant_mismatch enables matching a SISO rate on ANT_A or ANT_B
- * with a rate indicating STBC/BFER and ANT_AB.
- */
-static inline bool rs_rate_equal(struct rs_rate *a,
-				 struct rs_rate *b,
-				 bool allow_ant_mismatch)
-{
-	bool ant_match = (a->ant == b->ant) && (a->stbc == b->stbc) &&
-		(a->bfer == b->bfer);
-	if (allow_ant_mismatch) {
-		if (a->stbc || a->bfer) {
-			WARN_ONCE(a->ant != ANT_AB, "stbc %d bfer %d ant %d",
-				  a->stbc, a->bfer, a->ant);
-			ant_match |= (b->ant == ANT_A || b->ant == ANT_B);
-		} else if (b->stbc || b->bfer) {
-			WARN_ONCE(b->ant != ANT_AB, "stbc %d bfer %d ant %d",
-				  b->stbc, b->bfer, b->ant);
-			ant_match |= (a->ant == ANT_A || a->ant == ANT_B);
-		}
-	}
-	return (a->type == b->type) && (a->bw == b->bw) && (a->sgi == b->sgi) &&
-		(a->ldpc == b->ldpc) && (a->index == b->index) && ant_match;
-}
 /* Check if both rates share the same column */
 static inline bool rs_rate_column_match(struct rs_rate *a,
 					struct rs_rate *b)
 	u32 lq_hwrate;
 	struct rs_rate lq_rate, tx_resp_rate;
 	struct iwl_scale_tbl_info *curr_tbl, *other_tbl, *tmp_tbl;
-	u8 reduced_txp = (uintptr_t)info->status.status_driver_data[0];
+	u32 tlc_info = (uintptr_t)info->status.status_driver_data[0];
+	u8 reduced_txp = tlc_info & RS_DRV_DATA_TXP_MSK;
+	u8 lq_color = RS_DRV_DATA_LQ_COLOR_GET(tlc_info);
 	u32 tx_resp_hwrate = (uintptr_t)info->status.status_driver_data[1];
 	struct iwl_mvm_sta *mvmsta = iwl_mvm_sta_from_mac80211(sta);
 	struct iwl_lq_sta *lq_sta = &mvmsta->lq_sta;
-	bool allow_ant_mismatch = fw_has_api(&mvm->fw->ucode_capa,
-					     IWL_UCODE_TLV_API_LQ_SS_PARAMS);
 	/* Treat uninitialized rate scaling data same as non-existing. */
 	if (!lq_sta) {
 	rs_rate_from_ucode_rate(lq_hwrate, info->band, &lq_rate);
 	/* Here we actually compare this rate to the latest LQ command */
-	if (!rs_rate_equal(&tx_resp_rate, &lq_rate, allow_ant_mismatch)) {
+	if (lq_color != LQ_FLAG_COLOR_GET(table->flags)) {
 		IWL_DEBUG_RATE(mvm,
-			       "initial tx resp rate 0x%x does not match 0x%x\n",
+			       "tx resp color 0x%x does not match 0x%x\n",
-			       tx_resp_hwrate, lq_hwrate);
+			       lq_color, LQ_FLAG_COLOR_GET(table->flags));
 		/*
 		 * Since rates mis-match, the last LQ command may have failed.
 	u8 valid_tx_ant = 0;
 	struct iwl_lq_cmd *lq_cmd = &lq_sta->lq;
 	bool toggle_ant = false;
+	u32 color;
 	memcpy(&rate, initial_rate, sizeof(rate));
 				 num_rates, num_retries, valid_tx_ant,
 				 toggle_ant);
+	/* update the color of the LQ command (as a counter at bits 1-3) */
+	color = LQ_FLAGS_COLOR_INC(LQ_FLAG_COLOR_GET(lq_cmd->flags));
+	lq_cmd->flags = LQ_FLAG_COLOR_SET(lq_cmd->flags, color);
 }
 struct rs_bfer_active_iter_data {

drivers/net/wireless/intel/iwlwifi/mvm/rs.h+15−0

@@ -2,6 +2,7 @@ · 1 unmodified line
2	*	2	*
3	* Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.	3	* Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
4	* Copyright(c) 2015 Intel Mobile Communications GmbH	4	* Copyright(c) 2015 Intel Mobile Communications GmbH
		5	* Copyright(c) 2017 Intel Deutschland GmbH
5	*	6	*
6	* This program is free software; you can redistribute it and/or modify it	7	* This program is free software; you can redistribute it and/or modify it
7	* under the terms of version 2 of the GNU General Public License as	8	* under the terms of version 2 of the GNU General Public License as
@@ -357,6 +358,20 @@ struct iwl_lq_sta { · 349 unmodified lines
357	} pers;	358	} pers;
358	};	359	};
359		360
		361	/* ieee80211_tx_info's status_driver_data[0] is packed with lq color and txp
		362	* Note, it's iwlmvm <-> mac80211 interface.
		363	* bits 0-7: reduced tx power
		364	* bits 8-10: LQ command's color
		365	*/
		366	#define RS_DRV_DATA_TXP_MSK 0xff
		367	#define RS_DRV_DATA_LQ_COLOR_POS 8
		368	#define RS_DRV_DATA_LQ_COLOR_MSK (7 << RS_DRV_DATA_LQ_COLOR_POS)
		369	#define RS_DRV_DATA_LQ_COLOR_GET(_f) (((_f) & RS_DRV_DATA_LQ_COLOR_MSK) >>\
		370	RS_DRV_DATA_LQ_COLOR_POS)
		371	#define RS_DRV_DATA_PACK(_c, _p) ((void *)(uintptr_t)\
		372	(((uintptr_t)_p) \|\
		373	((_c) << RS_DRV_DATA_LQ_COLOR_POS)))
		374
360	/* Initialize station's rate scaling information after adding station */	375	/* Initialize station's rate scaling information after adding station */
361	void iwl_mvm_rs_rate_init(struct iwl_mvm mvm, struct ieee80211_sta sta,	376	void iwl_mvm_rs_rate_init(struct iwl_mvm mvm, struct ieee80211_sta sta,
362	enum nl80211_band band, bool init);	377	enum nl80211_band band, bool init);

drivers/net/wireless/intel/iwlwifi/mvm/sta.c+17−9

 	if (!iwl_mvm_is_dqa_supported(mvm))
 		return 0;
-	if (WARN_ON(vif->type != NL80211_IFTYPE_AP))
+	if (WARN_ON(vif->type != NL80211_IFTYPE_AP &&
+		    vif->type != NL80211_IFTYPE_ADHOC))
 		return -ENOTSUPP;
 	/*
 		mvmvif->cab_queue = queue;
 	} else if (!fw_has_api(&mvm->fw->ucode_capa,
 			       IWL_UCODE_TLV_API_STA_TYPE)) {
+		/*
+		 * In IBSS, ieee80211_check_queues() sets the cab_queue to be
+		 * invalid, so make sure we use the queue we want.
+		 * Note that this is done here as we want to avoid making DQA
+		 * changes in mac80211 layer.
+		 */
+		if (vif->type == NL80211_IFTYPE_ADHOC) {
+			vif->cab_queue = IWL_MVM_DQA_GCAST_QUEUE;
+			mvmvif->cab_queue = vif->cab_queue;
+		}
 		iwl_mvm_enable_txq(mvm, vif->cab_queue, vif->cab_queue, 0,
 				   &cfg, timeout);
 	}
 	/* Get the station from the mvm local station table */
 	mvm_sta = iwl_mvm_get_key_sta(mvm, vif, sta);
-	if (!mvm_sta) {
+	if (mvm_sta)
-		IWL_ERR(mvm, "Failed to find station\n");
+		sta_id = mvm_sta->sta_id;
-		return -EINVAL;
-	}
-	sta_id = mvm_sta->sta_id;
 	IWL_DEBUG_WEP(mvm, "mvm remove dynamic key: idx=%d sta=%d\n",
 		      keyconf->keyidx, sta_id);
-	if (keyconf->cipher == WLAN_CIPHER_SUITE_AES_CMAC ||
+	if (mvm_sta && (keyconf->cipher == WLAN_CIPHER_SUITE_AES_CMAC ||
-	    keyconf->cipher == WLAN_CIPHER_SUITE_BIP_GMAC_128 ||
+			keyconf->cipher == WLAN_CIPHER_SUITE_BIP_GMAC_128 ||
-	    keyconf->cipher == WLAN_CIPHER_SUITE_BIP_GMAC_256)
+			keyconf->cipher == WLAN_CIPHER_SUITE_BIP_GMAC_256))
 		return iwl_mvm_send_sta_igtk(mvm, keyconf, sta_id, true);
 	if (!__test_and_clear_bit(keyconf->hw_key_idx, mvm->fw_key_table)) {

drivers/net/wireless/intel/iwlwifi/mvm/sta.h+2−0

  *	This is basically (last acked packet++).
  * @rate_n_flags: Rate at which Tx was attempted. Holds the data between the
  *	Tx response (TX_CMD), and the block ack notification (COMPRESSED_BA).
+ * @lq_color: the color of the LQ command as it appears in tx response.
  * @amsdu_in_ampdu_allowed: true if A-MSDU in A-MPDU is allowed.
  * @state: state of the BA agreement establishment / tear down.
  * @txq_id: Tx queue used by the BA session / DQA
 	u16 next_reclaimed;
 	/* The rest is Tx AGG related */
 	u32 rate_n_flags;
+	u8 lq_color;
 	bool amsdu_in_ampdu_allowed;
 	enum iwl_mvm_agg_state state;
 	u16 txq_id;

drivers/net/wireless/intel/iwlwifi/mvm/tt.c+5−3

 	struct iwl_mvm *mvm = (struct iwl_mvm *)(cdev->devdata);
 	int ret;
-	if (!mvm->ucode_loaded || !(mvm->cur_ucode == IWL_UCODE_REGULAR))
-		return -EIO;
 	mutex_lock(&mvm->mutex);
+	if (!mvm->ucode_loaded || !(mvm->cur_ucode == IWL_UCODE_REGULAR)) {
+		ret = -EIO;
+		goto unlock;
+	}
 	if (new_state >= ARRAY_SIZE(iwl_mvm_cdev_budgets)) {
 		ret = -EINVAL;
 		goto unlock;

drivers/net/wireless/intel/iwlwifi/mvm/tx.c+11−1

 	struct iwl_mvm_sta *mvmsta;
 	struct sk_buff_head skbs;
 	u8 skb_freed = 0;
+	u8 lq_color;
 	u16 next_reclaimed, seq_ctl;
 	bool is_ndp = false;
 		info->status.tx_time =
 			le16_to_cpu(tx_resp->wireless_media_time);
 		BUILD_BUG_ON(ARRAY_SIZE(info->status.status_driver_data) < 1);
+		lq_color = TX_RES_RATE_TABLE_COL_GET(tx_resp->tlc_info);
 		info->status.status_driver_data[0] =
-				(void *)(uintptr_t)tx_resp->reduced_tpc;
+			RS_DRV_DATA_PACK(lq_color, tx_resp->reduced_tpc);
 		ieee80211_tx_status(mvm->hw, skb);
 	}
 			le32_to_cpu(tx_resp->initial_rate);
 		mvmsta->tid_data[tid].tx_time =
 			le16_to_cpu(tx_resp->wireless_media_time);
+		mvmsta->tid_data[tid].lq_color =
+			(tx_resp->tlc_info & TX_RES_RATE_TABLE_COLOR_MSK) >>
+			TX_RES_RATE_TABLE_COLOR_POS;
 	}
 	rcu_read_unlock();
 	iwl_mvm_check_ratid_empty(mvm, sta, tid);
 	freed = 0;
+	/* pack lq color from tid_data along the reduced txp */
+	ba_info->status.status_driver_data[0] =
+		RS_DRV_DATA_PACK(tid_data->lq_color,
+				 ba_info->status.status_driver_data[0]);
 	ba_info->status.status_driver_data[1] = (void *)(uintptr_t)rate;
 	skb_queue_walk(&reclaimed_skbs, skb) {

drivers/net/wireless/intel/iwlwifi/pcie/trans.c+4−2

 #ifdef CONFIG_PM_SLEEP
 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
 {
-	if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3)
+	if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 &&
+	    (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3))
 		return iwl_pci_fw_enter_d0i3(trans);
 	return 0;
 static void iwl_trans_pcie_resume(struct iwl_trans *trans)
 {
-	if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3)
+	if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 &&
+	    (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3))
 		iwl_pci_fw_exit_d0i3(trans);
 }
 #endif /* CONFIG_PM_SLEEP */

drivers/net/wireless/intel/iwlwifi/pcie/tx-gen2.c+6−3

 	if (WARN_ON(iwl_rx_packet_payload_len(hcmd.resp_pkt) != sizeof(*rsp))) {
 		ret = -EINVAL;
-		goto error;
+		goto error_free_resp;
 	}
 	rsp = (void *)hcmd.resp_pkt->data;
 	if (qid > ARRAY_SIZE(trans_pcie->txq)) {
 		WARN_ONCE(1, "queue index %d unsupported", qid);
 		ret = -EIO;
-		goto error;
+		goto error_free_resp;
 	}
 	if (test_and_set_bit(qid, trans_pcie->queue_used)) {
 		WARN_ONCE(1, "queue %d already used", qid);
 		ret = -EIO;
-		goto error;
+		goto error_free_resp;
 	}
 	txq->id = qid;
 			   (txq->write_ptr) | (qid << 16));
 	IWL_DEBUG_TX_QUEUES(trans, "Activate queue %d\n", qid);
+	iwl_free_resp(&hcmd);
 	return qid;
+error_free_resp:
+	iwl_free_resp(&hcmd);
 error:
 	iwl_pcie_gen2_txq_free_memory(trans, txq);
 	return ret;

drivers/net/wireless/intersil/hostap/hostap_main.c+1−1

@@ -73,7 +73,7 @@ struct net_device * hostap_add_interface(struct local_info *local, · 72 unmodified lines
73	dev->mem_end = mdev->mem_end;	73	dev->mem_end = mdev->mem_end;
74		74
75	hostap_setup_dev(dev, local, type);	75	hostap_setup_dev(dev, local, type);
76	dev->destructor = free_netdev;	76	dev->needs_free_netdev = true;
77		77
78	sprintf(dev->name, "%s%s", prefix, name);	78	sprintf(dev->name, "%s%s", prefix, name);
79	if (!rtnl_locked)	79	if (!rtnl_locked)

drivers/net/wireless/mac80211_hwsim.c+1−1

@@ -2861,7 +2861,7 @@ static const struct net_device_ops hwsim_netdev_ops = { · 2860 unmodified lines
2861	static void hwsim_mon_setup(struct net_device *dev)	2861	static void hwsim_mon_setup(struct net_device *dev)
2862	{	2862	{
2863	dev->netdev_ops = &hwsim_netdev_ops;	2863	dev->netdev_ops = &hwsim_netdev_ops;
2864	dev->destructor = free_netdev;	2864	dev->needs_free_netdev = true;
2865	ether_setup(dev);	2865	ether_setup(dev);
2866	dev->priv_flags \|= IFF_NO_QUEUE;	2866	dev->priv_flags \|= IFF_NO_QUEUE;
2867	dev->type = ARPHRD_IEEE80211_RADIOTAP;	2867	dev->type = ARPHRD_IEEE80211_RADIOTAP;

drivers/net/wireless/marvell/mwifiex/main.c+1−1

@@ -1280,7 +1280,7 @@ void mwifiex_init_priv_params(struct mwifiex_private *priv, · 1279 unmodified lines
1280	struct net_device *dev)	1280	struct net_device *dev)
1281	{	1281	{
1282	dev->netdev_ops = &mwifiex_netdev_ops;	1282	dev->netdev_ops = &mwifiex_netdev_ops;
1283	dev->destructor = free_netdev;	1283	dev->needs_free_netdev = true;
1284	/* Initialize private structure */	1284	/* Initialize private structure */
1285	priv->current_key_index = 0;	1285	priv->current_key_index = 0;
1286	priv->media_connected = false;	1286	priv->media_connected = false;

drivers/nvme/host/core.c+14−7

 static int nvme_char_major;
 module_param(nvme_char_major, int, 0);
-static unsigned long default_ps_max_latency_us = 25000;
+static unsigned long default_ps_max_latency_us = 100000;
 module_param(default_ps_max_latency_us, ulong, 0644);
 MODULE_PARM_DESC(default_ps_max_latency_us,
 		 "max power saving latency for new devices; use PM QOS to change per device");
 	 * transitioning between power states.  Therefore, when running
 	 * in any given state, we will enter the next lower-power
 	 * non-operational state after waiting 50 * (enlat + exlat)
-	 * microseconds, as long as that state's total latency is under
+	 * microseconds, as long as that state's exit latency is under
 	 * the requested maximum latency.
 	 *
 	 * We will not autonomously enter any non-operational state for
 		 * lowest-power state, not the number of states.
 		 */
 		for (state = (int)ctrl->npss; state >= 0; state--) {
-			u64 total_latency_us, transition_ms;
+			u64 total_latency_us, exit_latency_us, transition_ms;
 			if (target)
 				table->entries[state] = target;
 			      NVME_PS_FLAGS_NON_OP_STATE))
 				continue;
-			total_latency_us =
+			exit_latency_us =
-				(u64)le32_to_cpu(ctrl->psd[state].entry_lat) +
+				(u64)le32_to_cpu(ctrl->psd[state].exit_lat);
-				+ le32_to_cpu(ctrl->psd[state].exit_lat);
+			if (exit_latency_us > ctrl->ps_max_latency_us)
-			if (total_latency_us > ctrl->ps_max_latency_us)
 				continue;
+			total_latency_us =
+				exit_latency_us +
+				le32_to_cpu(ctrl->psd[state].entry_lat);
 			/*
 			 * This state is good.  Use it as the APST idle
 			 * target for higher power states.
 	struct nvme_ns *ns;
 	mutex_lock(&ctrl->namespaces_mutex);
+	/* Forcibly start all queues to avoid having stuck requests */
+	blk_mq_start_hw_queues(ctrl->admin_q);
 	list_for_each_entry(ns, &ctrl->namespaces, list) {
 		/*
 		 * Revalidating a dead namespace sets capacity to 0. This will

drivers/nvme/host/fc.c+18−2

 /* *********************** NVME Ctrl Routines **************************** */
 static void __nvme_fc_final_op_cleanup(struct request *rq);
+static void nvme_fc_error_recovery(struct nvme_fc_ctrl *ctrl, char *errmsg);
 static int
 nvme_fc_reinit_request(void *data, struct request *rq)
 	struct nvme_command *sqe = &op->cmd_iu.sqe;
 	__le16 status = cpu_to_le16(NVME_SC_SUCCESS << 1);
 	union nvme_result result;
-	bool complete_rq;
+	bool complete_rq, terminate_assoc = true;
 	/*
 	 * WARNING:
 	 * fabricate a CQE, the following fields will not be set as they
 	 * are not referenced:
 	 *      cqe.sqid,  cqe.sqhd,  cqe.command_id
+	 *
+	 * Failure or error of an individual i/o, in a transport
+	 * detected fashion unrelated to the nvme completion status,
+	 * potentially cause the initiator and target sides to get out
+	 * of sync on SQ head/tail (aka outstanding io count allowed).
+	 * Per FC-NVME spec, failure of an individual command requires
+	 * the connection to be terminated, which in turn requires the
+	 * association to be terminated.
 	 */
 	fc_dma_sync_single_for_cpu(ctrl->lport->dev, op->fcp_req.rspdma,
 		goto done;
 	}
+	terminate_assoc = false;
 done:
 	if (op->flags & FCOP_FLAGS_AEN) {
 		nvme_complete_async_event(&queue->ctrl->ctrl, status, &result);
 		atomic_set(&op->state, FCPOP_STATE_IDLE);
 		op->flags = FCOP_FLAGS_AEN;	/* clear other flags */
 		nvme_fc_ctrl_put(ctrl);
-		return;
+		goto check_error;
 	}
 	complete_rq = __nvme_fc_fcpop_chk_teardowns(ctrl, op);
 		nvme_end_request(rq, status, result);
 	} else
 		__nvme_fc_final_op_cleanup(rq);
+check_error:
+	if (terminate_assoc)
+		nvme_fc_error_recovery(ctrl, "transport detected io error");
 }
 static int
 		ctrl->ctrl.opts = NULL;
 		/* initiate nvme ctrl ref counting teardown */
 		nvme_uninit_ctrl(&ctrl->ctrl);
+		nvme_put_ctrl(&ctrl->ctrl);
 		/* as we're past the point where we transition to the ref
 		 * counting teardown path, if we return a bad pointer here,

drivers/nvme/host/pci.c+6−7

 	bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
 	/* If there is a reset ongoing, we shouldn't reset again. */
-	if (work_busy(&dev->reset_work))
+	if (dev->ctrl.state == NVME_CTRL_RESETTING)
 		return false;
 	/* We shouldn't reset unless the controller is on fatal error state
 	bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
 	int result = -ENODEV;
-	if (WARN_ON(dev->ctrl.state == NVME_CTRL_RESETTING))
+	if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING))
 		goto out;
 	/*
 	if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
 		nvme_dev_disable(dev, false);
-	if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING))
-		goto out;
 	result = nvme_pci_enable(dev);
 	if (result)
 		goto out;
 {
 	if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q))
 		return -ENODEV;
-	if (work_busy(&dev->reset_work))
+	if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING))
-		return -ENODEV;
+		return -EBUSY;
 	if (!queue_work(nvme_workq, &dev->reset_work))
 		return -EBUSY;
 	return 0;
 	if (result)
 		goto release_pools;
+	nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING);
 	dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
 	queue_work(nvme_workq, &dev->reset_work);
 	nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
+	cancel_work_sync(&dev->reset_work);
 	pci_set_drvdata(pdev, NULL);
 	if (!pci_device_is_present(pdev)) {

drivers/nvme/host/rdma.c+29−15

 	if (ret)
 		goto requeue;
-	blk_mq_start_stopped_hw_queues(ctrl->ctrl.admin_q, true);
 	ret = nvmf_connect_admin_queue(&ctrl->ctrl);
 	if (ret)
-		goto stop_admin_q;
+		goto requeue;
 	set_bit(NVME_RDMA_Q_LIVE, &ctrl->queues[0].flags);
 	ret = nvme_enable_ctrl(&ctrl->ctrl, ctrl->cap);
 	if (ret)
-		goto stop_admin_q;
+		goto requeue;
 	nvme_start_keep_alive(&ctrl->ctrl);
 	if (ctrl->queue_count > 1) {
 		ret = nvme_rdma_init_io_queues(ctrl);
 		if (ret)
-			goto stop_admin_q;
+			goto requeue;
 		ret = nvme_rdma_connect_io_queues(ctrl);
 		if (ret)
-			goto stop_admin_q;
+			goto requeue;
 	}
 	changed = nvme_change_ctrl_state(&ctrl->ctrl, NVME_CTRL_LIVE);
 	ctrl->ctrl.opts->nr_reconnects = 0;
 	if (ctrl->queue_count > 1) {
-		nvme_start_queues(&ctrl->ctrl);
 		nvme_queue_scan(&ctrl->ctrl);
 		nvme_queue_async_events(&ctrl->ctrl);
 	}
 	return;
-stop_admin_q:
-	blk_mq_stop_hw_queues(ctrl->ctrl.admin_q);
 requeue:
 	dev_info(ctrl->ctrl.device, "Failed reconnect attempt %d\n",
 			ctrl->ctrl.opts->nr_reconnects);
 	blk_mq_tagset_busy_iter(&ctrl->admin_tag_set,
 				nvme_cancel_request, &ctrl->ctrl);
+	/*
+	 * queues are not a live anymore, so restart the queues to fail fast
+	 * new IO
+	 */
+	blk_mq_start_stopped_hw_queues(ctrl->ctrl.admin_q, true);
+	nvme_start_queues(&ctrl->ctrl);
 	nvme_rdma_reconnect_or_remove(ctrl);
 }
 /*
  * We cannot accept any other command until the Connect command has completed.
  */
-static inline bool nvme_rdma_queue_is_ready(struct nvme_rdma_queue *queue,
+static inline int nvme_rdma_queue_is_ready(struct nvme_rdma_queue *queue,
 		struct request *rq)
 {
 	if (unlikely(!test_bit(NVME_RDMA_Q_LIVE, &queue->flags))) {
 		if (!blk_rq_is_passthrough(rq) ||
 		    cmd->common.opcode != nvme_fabrics_command ||
-		    cmd->fabrics.fctype != nvme_fabrics_type_connect)
+		    cmd->fabrics.fctype != nvme_fabrics_type_connect) {
-			return false;
+			/*
+			 * reconnecting state means transport disruption, which
+			 * can take a long time and even might fail permanently,
+			 * so we can't let incoming I/O be requeued forever.
+			 * fail it fast to allow upper layers a chance to
+			 * failover.
+			 */
+			if (queue->ctrl->ctrl.state == NVME_CTRL_RECONNECTING)
+				return -EIO;
+			else
+				return -EAGAIN;
+		}
 	}
-	return true;
+	return 0;
 }
 static int nvme_rdma_queue_rq(struct blk_mq_hw_ctx *hctx,
 	WARN_ON_ONCE(rq->tag < 0);
-	if (!nvme_rdma_queue_is_ready(queue, rq))
+	ret = nvme_rdma_queue_is_ready(queue, rq);
-		return BLK_MQ_RQ_QUEUE_BUSY;
+	if (unlikely(ret))
+		goto err;
 	dev = queue->device->dev;
 	ib_dma_sync_single_for_cpu(dev, sqe->dma,

drivers/of/device.c+2−2

@@ -144,8 +144,8 @@ int of_dma_configure(struct device dev, struct device_node np) · 143 unmodified lines
144	coherent ? " " : " not ");	144	coherent ? " " : " not ");
145		145
146	iommu = of_iommu_configure(dev, np);	146	iommu = of_iommu_configure(dev, np);
147	if (IS_ERR(iommu))	147	if (IS_ERR(iommu) && PTR_ERR(iommu) == -EPROBE_DEFER)
148	return PTR_ERR(iommu);	148	return -EPROBE_DEFER;
149		149
150	dev_dbg(dev, "device is%sbehind an iommu\n",	150	dev_dbg(dev, "device is%sbehind an iommu\n",
151	iommu ? " " : " not ");	151	iommu ? " " : " not ");

drivers/pci/access.c+6−6

@@ -896,7 +896,7 @@ int pci_read_config_byte(const struct pci_dev dev, int where, u8 val) · 895 unmodified lines
896	{	896	{
897	if (pci_dev_is_disconnected(dev)) {	897	if (pci_dev_is_disconnected(dev)) {
898	*val = ~0;	898	*val = ~0;
899	return -ENODEV;	899	return PCIBIOS_DEVICE_NOT_FOUND;
900	}	900	}
901	return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);	901	return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
902	}	902	}
@@ -906,7 +906,7 @@ int pci_read_config_word(const struct pci_dev dev, int where, u16 val) · 3 unmodified lines
906	{	906	{
907	if (pci_dev_is_disconnected(dev)) {	907	if (pci_dev_is_disconnected(dev)) {
908	*val = ~0;	908	*val = ~0;
909	return -ENODEV;	909	return PCIBIOS_DEVICE_NOT_FOUND;
910	}	910	}
911	return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);	911	return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
912	}	912	}
@@ -917,7 +917,7 @@ int pci_read_config_dword(const struct pci_dev *dev, int where, · 4 unmodified lines
917	{	917	{
918	if (pci_dev_is_disconnected(dev)) {	918	if (pci_dev_is_disconnected(dev)) {
919	*val = ~0;	919	*val = ~0;
920	return -ENODEV;	920	return PCIBIOS_DEVICE_NOT_FOUND;
921	}	921	}
922	return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);	922	return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
923	}	923	}
@@ -926,7 +926,7 @@ EXPORT_SYMBOL(pci_read_config_dword); · 2 unmodified lines
926	int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)	926	int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
927	{	927	{
928	if (pci_dev_is_disconnected(dev))	928	if (pci_dev_is_disconnected(dev))
929	return -ENODEV;	929	return PCIBIOS_DEVICE_NOT_FOUND;
930	return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);	930	return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
931	}	931	}
932	EXPORT_SYMBOL(pci_write_config_byte);	932	EXPORT_SYMBOL(pci_write_config_byte);
@@ -934,7 +934,7 @@ EXPORT_SYMBOL(pci_write_config_byte); · 1 unmodified line
934	int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)	934	int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
935	{	935	{
936	if (pci_dev_is_disconnected(dev))	936	if (pci_dev_is_disconnected(dev))
937	return -ENODEV;	937	return PCIBIOS_DEVICE_NOT_FOUND;
938	return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);	938	return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
939	}	939	}
940	EXPORT_SYMBOL(pci_write_config_word);	940	EXPORT_SYMBOL(pci_write_config_word);
@@ -943,7 +943,7 @@ int pci_write_config_dword(const struct pci_dev *dev, int where, · 2 unmodified lines
943	u32 val)	943	u32 val)
944	{	944	{
945	if (pci_dev_is_disconnected(dev))	945	if (pci_dev_is_disconnected(dev))
946	return -ENODEV;	946	return PCIBIOS_DEVICE_NOT_FOUND;
947	return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);	947	return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
948	}	948	}
949	EXPORT_SYMBOL(pci_write_config_dword);	949	EXPORT_SYMBOL(pci_write_config_dword);

drivers/pci/endpoint/functions/Kconfig+1−0

@@ -5,6 +5,7 @@ · 4 unmodified lines
5	config PCI_EPF_TEST	5	config PCI_EPF_TEST
6	tristate "PCI Endpoint Test driver"	6	tristate "PCI Endpoint Test driver"
7	depends on PCI_ENDPOINT	7	depends on PCI_ENDPOINT
		8	select CRC32
8	help	9	help
9	Enable this configuration option to enable the test driver	10	Enable this configuration option to enable the test driver
10	for PCI Endpoint.	11	for PCI Endpoint.

drivers/perf/arm_pmu_acpi.c+11−0

@@ -29,6 +29,17 @@ static int arm_pmu_acpi_register_irq(int cpu) · 28 unmodified lines
29	return -EINVAL;	29	return -EINVAL;
30		30
31	gsi = gicc->performance_interrupt;	31	gsi = gicc->performance_interrupt;
		32
		33	/*
		34	* Per the ACPI spec, the MADT cannot describe a PMU that doesn't
		35	* have an interrupt. QEMU advertises this by using a GSI of zero,
		36	* which is not known to be valid on any hardware despite being
		37	* valid per the spec. Take the pragmatic approach and reject a
		38	* GSI of zero for now.
		39	*/
		40	if (!gsi)
		41	return 0;
		42
32	if (gicc->flags & ACPI_MADT_PERFORMANCE_IRQ_MODE)	43	if (gicc->flags & ACPI_MADT_PERFORMANCE_IRQ_MODE)
33	trigger = ACPI_EDGE_SENSITIVE;	44	trigger = ACPI_EDGE_SENSITIVE;
34	else	45	else

drivers/phy/phy-qcom-qmp.c+7−7

@@ -844,7 +844,7 @@ static int qcom_qmp_phy_vreg_init(struct device *dev) · 843 unmodified lines
844	int num = qmp->cfg->num_vregs;	844	int num = qmp->cfg->num_vregs;
845	int i;	845	int i;
846		846
847	qmp->vregs = devm_kcalloc(dev, num, sizeof(qmp->vregs), GFP_KERNEL);	847	qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
848	if (!qmp->vregs)	848	if (!qmp->vregs)
849	return -ENOMEM;	849	return -ENOMEM;
850		850
@@ -983,16 +983,16 @@ int qcom_qmp_phy_create(struct device dev, struct device_node np, int id) · 132 unmodified lines
983	* Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.	983	* Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
984	*/	984	*/
985	qphy->tx = of_iomap(np, 0);	985	qphy->tx = of_iomap(np, 0);
986	if (IS_ERR(qphy->tx))	986	if (!qphy->tx)
987	return PTR_ERR(qphy->tx);	987	return -ENOMEM;
988		988
989	qphy->rx = of_iomap(np, 1);	989	qphy->rx = of_iomap(np, 1);
990	if (IS_ERR(qphy->rx))	990	if (!qphy->rx)
991	return PTR_ERR(qphy->rx);	991	return -ENOMEM;
992		992
993	qphy->pcs = of_iomap(np, 2);	993	qphy->pcs = of_iomap(np, 2);
994	if (IS_ERR(qphy->pcs))	994	if (!qphy->pcs)
995	return PTR_ERR(qphy->pcs);	995	return -ENOMEM;
996		996
997	/*	997	/*
998	* Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3	998	* Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3

drivers/pinctrl/core.c+3−17

  * pinctrl_generic_free_groups() - removes all pin groups
  * @pctldev: pin controller device
  *
- * Note that the caller must take care of locking.
+ * Note that the caller must take care of locking. The pinctrl groups
+ * are allocated with devm_kzalloc() so no need to free them here.
  */
 static void pinctrl_generic_free_groups(struct pinctrl_dev *pctldev)
 {
 	struct radix_tree_iter iter;
-	struct group_desc *group;
-	unsigned long *indices;
 	void **slot;
-	int i = 0;
-	indices = devm_kzalloc(pctldev->dev, sizeof(*indices) *
-			       pctldev->num_groups, GFP_KERNEL);
-	if (!indices)
-		return;
 	radix_tree_for_each_slot(slot, &pctldev->pin_group_tree, &iter, 0)
-		indices[i++] = iter.index;
+		radix_tree_delete(&pctldev->pin_group_tree, iter.index);
-	for (i = 0; i < pctldev->num_groups; i++) {
-		group = radix_tree_lookup(&pctldev->pin_group_tree,
-					  indices[i]);
-		radix_tree_delete(&pctldev->pin_group_tree, indices[i]);
-		devm_kfree(pctldev->dev, group);
-	}
 	pctldev->num_groups = 0;
 }

drivers/pinctrl/freescale/pinctrl-mxs.c+12−4

 	return 0;
 }
+static void mxs_pinctrl_rmwl(u32 value, u32 mask, u8 shift, void __iomem *reg)
+{
+	u32 tmp;
+	tmp = readl(reg);
+	tmp &= ~(mask << shift);
+	tmp |= value << shift;
+	writel(tmp, reg);
+}
 static int mxs_pinctrl_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
 			       unsigned group)
 {
 		reg += bank * 0x20 + pin / 16 * 0x10;
 		shift = pin % 16 * 2;
-		writel(0x3 << shift, reg + CLR);
+		mxs_pinctrl_rmwl(g->muxsel[i], 0x3, shift, reg);
-		writel(g->muxsel[i] << shift, reg + SET);
 	}
 	return 0;
 			/* mA */
 			if (config & MA_PRESENT) {
 				shift = pin % 8 * 4;
-				writel(0x3 << shift, reg + CLR);
+				mxs_pinctrl_rmwl(ma, 0x3, shift, reg);
-				writel(ma << shift, reg + SET);
 			}
 			/* vol */

drivers/pinctrl/intel/pinctrl-cherryview.c+19−5

@@ -1539,15 +1539,29 @@ static void chv_gpio_irq_handler(struct irq_desc *desc) · 1538 unmodified lines
1539	* is not listed below.	1539	* is not listed below.
1540	*/	1540	*/
1541	static const struct dmi_system_id chv_no_valid_mask[] = {	1541	static const struct dmi_system_id chv_no_valid_mask[] = {
		1542	/* See https://bugzilla.kernel.org/show_bug.cgi?id=194945 */
1542	{	1543	{
1543	/* See https://bugzilla.kernel.org/show_bug.cgi?id=194945 */	1544	.ident = "Intel_Strago based Chromebooks (All models)",
1544	.ident = "Acer Chromebook (CYAN)",
1545	.matches = {	1545	.matches = {
1546	DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),	1546	DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
1547	DMI_MATCH(DMI_PRODUCT_NAME, "Edgar"),	1547	DMI_MATCH(DMI_PRODUCT_FAMILY, "Intel_Strago"),
1548	DMI_MATCH(DMI_BIOS_DATE, "05/21/2016"),
1549	},	1548	},
1550	}	1549	},
		1550	{
		1551	.ident = "Acer Chromebook R11 (Cyan)",
		1552	.matches = {
		1553	DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
		1554	DMI_MATCH(DMI_PRODUCT_NAME, "Cyan"),
		1555	},
		1556	},
		1557	{
		1558	.ident = "Samsung Chromebook 3 (Celes)",
		1559	.matches = {
		1560	DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
		1561	DMI_MATCH(DMI_PRODUCT_NAME, "Celes"),
		1562	},
		1563	},
		1564	{}
1551	};	1565	};
1552		1566
1553	static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)	1567	static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)

drivers/pinctrl/pinconf-generic.c+0−3

 	PCONFDUMP(PIN_CONFIG_BIAS_PULL_PIN_DEFAULT,
 				"input bias pull to pin specific state", NULL, false),
 	PCONFDUMP(PIN_CONFIG_BIAS_PULL_UP, "input bias pull up", NULL, false),
-	PCONFDUMP(PIN_CONFIG_BIDIRECTIONAL, "bi-directional pin operations", NULL, false),
 	PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_DRAIN, "output drive open drain", NULL, false),
 	PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_SOURCE, "output drive open source", NULL, false),
 	PCONFDUMP(PIN_CONFIG_DRIVE_PUSH_PULL, "output drive push pull", NULL, false),
 	{ "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
 	{ "bias-pull-pin-default", PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, 1 },
 	{ "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
-	{ "bi-directional", PIN_CONFIG_BIDIRECTIONAL, 1 },
 	{ "drive-open-drain", PIN_CONFIG_DRIVE_OPEN_DRAIN, 0 },
 	{ "drive-open-source", PIN_CONFIG_DRIVE_OPEN_SOURCE, 0 },
 	{ "drive-push-pull", PIN_CONFIG_DRIVE_PUSH_PULL, 0 },
 	{ "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 },
 	{ "low-power-disable", PIN_CONFIG_LOW_POWER_MODE, 0 },
 	{ "low-power-enable", PIN_CONFIG_LOW_POWER_MODE, 1 },
-	{ "output-enable", PIN_CONFIG_OUTPUT, 1, },
 	{ "output-high", PIN_CONFIG_OUTPUT, 1, },
 	{ "output-low", PIN_CONFIG_OUTPUT, 0, },
 	{ "power-source", PIN_CONFIG_POWER_SOURCE, 0 },

drivers/pinctrl/pinmux.c+4−17

  * pinmux_generic_free_functions() - removes all functions
  * @pctldev: pin controller device
  *
- * Note that the caller must take care of locking.
+ * Note that the caller must take care of locking. The pinctrl
+ * functions are allocated with devm_kzalloc() so no need to free
+ * them here.
  */
 void pinmux_generic_free_functions(struct pinctrl_dev *pctldev)
 {
 	struct radix_tree_iter iter;
-	struct function_desc *function;
-	unsigned long *indices;
 	void **slot;
-	int i = 0;
-	indices = devm_kzalloc(pctldev->dev, sizeof(*indices) *
-			       pctldev->num_functions, GFP_KERNEL);
-	if (!indices)
-		return;
 	radix_tree_for_each_slot(slot, &pctldev->pin_function_tree, &iter, 0)
-		indices[i++] = iter.index;
+		radix_tree_delete(&pctldev->pin_function_tree, iter.index);
-	for (i = 0; i < pctldev->num_functions; i++) {
-		function = radix_tree_lookup(&pctldev->pin_function_tree,
-					     indices[i]);
-		radix_tree_delete(&pctldev->pin_function_tree, indices[i]);
-		devm_kfree(pctldev->dev, function);
-	}
 	pctldev->num_functions = 0;
 }

drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c+1−1

@@ -394,7 +394,7 @@ static const struct sunxi_desc_pin sun8i_a83t_pins[] = { · 393 unmodified lines
394	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 18),	394	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 18),
395	SUNXI_FUNCTION(0x0, "gpio_in"),	395	SUNXI_FUNCTION(0x0, "gpio_in"),
396	SUNXI_FUNCTION(0x1, "gpio_out"),	396	SUNXI_FUNCTION(0x1, "gpio_out"),
397	SUNXI_FUNCTION(0x3, "owa")), /* DOUT */	397	SUNXI_FUNCTION(0x3, "spdif")), /* DOUT */
398	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 19),	398	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 19),
399	SUNXI_FUNCTION(0x0, "gpio_in"),	399	SUNXI_FUNCTION(0x0, "gpio_in"),
400	SUNXI_FUNCTION(0x1, "gpio_out")),	400	SUNXI_FUNCTION(0x1, "gpio_out")),

drivers/platform/goldfish/goldfish_pipe.c+1−1

@@ -704,7 +704,7 @@ static int get_free_pipe_id_locked(struct goldfish_pipe_dev *dev) · 703 unmodified lines
704	/* Reallocate the array */	704	/* Reallocate the array */
705	u32 new_capacity = 2 * dev->pipes_capacity;	705	u32 new_capacity = 2 * dev->pipes_capacity;
706	struct goldfish_pipe **pipes =	706	struct goldfish_pipe **pipes =
707	kcalloc(new_capacity, sizeof(*pipes), GFP_KERNEL);	707	kcalloc(new_capacity, sizeof(*pipes), GFP_ATOMIC);
708	if (!pipes)	708	if (!pipes)
709	return -ENOMEM;	709	return -ENOMEM;
710	memcpy(pipes, dev->pipes, sizeof(pipes) dev->pipes_capacity);	710	memcpy(pipes, dev->pipes, sizeof(pipes) dev->pipes_capacity);

drivers/platform/x86/intel_telemetry_debugfs.c+7−9

 	} \
 }
-#ifdef CONFIG_PM_SLEEP
 static u8 suspend_prep_ok;
 static u32 suspend_shlw_ctr_temp, suspend_deep_ctr_temp;
 static u64 suspend_shlw_res_temp, suspend_deep_res_temp;
-#endif
 struct telemetry_susp_stats {
 	u32 shlw_swake_ctr;
 	.release	= single_release,
 };
-#ifdef CONFIG_PM_SLEEP
 static int pm_suspend_prep_cb(void)
 {
 	struct telemetry_evtlog evtlog[TELEM_MAX_OS_ALLOCATED_EVENTS];
 static struct notifier_block pm_notifier = {
 	.notifier_call = pm_notification,
 };
-#endif /* CONFIG_PM_SLEEP */
 static int __init telemetry_debugfs_init(void)
 {
 	if (err < 0)
 		return -EINVAL;
-#ifdef CONFIG_PM_SLEEP
 	register_pm_notifier(&pm_notifier);
-#endif /* CONFIG_PM_SLEEP */
 	debugfs_conf->telemetry_dbg_dir = debugfs_create_dir("telemetry", NULL);
-	if (!debugfs_conf->telemetry_dbg_dir)
+	if (!debugfs_conf->telemetry_dbg_dir) {
-		return -ENOMEM;
+		err = -ENOMEM;
+		goto out_pm;
+	}
 	f = debugfs_create_file("pss_info", S_IFREG | S_IRUGO,
 				debugfs_conf->telemetry_dbg_dir, NULL,
 out:
 	debugfs_remove_recursive(debugfs_conf->telemetry_dbg_dir);
 	debugfs_conf->telemetry_dbg_dir = NULL;
+out_pm:
+	unregister_pm_notifier(&pm_notifier);
 	return err;
 }
 {
 	debugfs_remove_recursive(debugfs_conf->telemetry_dbg_dir);
 	debugfs_conf->telemetry_dbg_dir = NULL;
+	unregister_pm_notifier(&pm_notifier);
 }
 late_initcall(telemetry_debugfs_init);

drivers/reset/hisilicon/hi6220_reset.c+2−0

@@ -155,3 +155,5 @@ static int __init hi6220_reset_init(void) · 154 unmodified lines
155	}	155	}
156		156
157	postcore_initcall(hi6220_reset_init);	157	postcore_initcall(hi6220_reset_init);
		158
		159	MODULE_LICENSE("GPL v2");

drivers/s390/cio/vfio_ccw_ops.c+6−6

@@ -70,14 +70,14 @@ static ssize_t name_show(struct kobject kobj, struct device dev, char *buf) · 69 unmodified lines
70	{	70	{
71	return sprintf(buf, "I/O subchannel (Non-QDIO)\n");	71	return sprintf(buf, "I/O subchannel (Non-QDIO)\n");
72	}	72	}
73	MDEV_TYPE_ATTR_RO(name);	73	static MDEV_TYPE_ATTR_RO(name);
74		74
75	static ssize_t device_api_show(struct kobject kobj, struct device dev,	75	static ssize_t device_api_show(struct kobject kobj, struct device dev,
76	char *buf)	76	char *buf)
77	{	77	{
78	return sprintf(buf, "%s\n", VFIO_DEVICE_API_CCW_STRING);	78	return sprintf(buf, "%s\n", VFIO_DEVICE_API_CCW_STRING);
79	}	79	}
80	MDEV_TYPE_ATTR_RO(device_api);	80	static MDEV_TYPE_ATTR_RO(device_api);
81		81
82	static ssize_t available_instances_show(struct kobject *kobj,	82	static ssize_t available_instances_show(struct kobject *kobj,
83	struct device dev, char buf)	83	struct device dev, char buf)
@@ -86,7 +86,7 @@ static ssize_t available_instances_show(struct kobject *kobj, · 2 unmodified lines
86		86
87	return sprintf(buf, "%d\n", atomic_read(&private->avail));	87	return sprintf(buf, "%d\n", atomic_read(&private->avail));
88	}	88	}
89	MDEV_TYPE_ATTR_RO(available_instances);	89	static MDEV_TYPE_ATTR_RO(available_instances);
90		90
91	static struct attribute *mdev_types_attrs[] = {	91	static struct attribute *mdev_types_attrs[] = {
92	&mdev_type_attr_name.attr,	92	&mdev_type_attr_name.attr,
@@ -100,7 +100,7 @@ static struct attribute_group mdev_type_group = { · 7 unmodified lines
100	.attrs = mdev_types_attrs,	100	.attrs = mdev_types_attrs,
101	};	101	};
102		102
103	struct attribute_group *mdev_type_groups[] = {	103	static struct attribute_group *mdev_type_groups[] = {
104	&mdev_type_group,	104	&mdev_type_group,
105	NULL,	105	NULL,
106	};	106	};
@@ -152,7 +152,7 @@ static int vfio_ccw_mdev_open(struct mdev_device *mdev) · 45 unmodified lines
152	&events, &private->nb);	152	&events, &private->nb);
153	}	153	}
154		154
155	void vfio_ccw_mdev_release(struct mdev_device *mdev)	155	static void vfio_ccw_mdev_release(struct mdev_device *mdev)
156	{	156	{
157	struct vfio_ccw_private *private =	157	struct vfio_ccw_private *private =
158	dev_get_drvdata(mdev_parent_dev(mdev));	158	dev_get_drvdata(mdev_parent_dev(mdev));
@@ -233,7 +233,7 @@ static int vfio_ccw_mdev_get_region_info(struct vfio_region_info *info, · 74 unmodified lines
233	}	233	}
234	}	234	}
235		235
236	int vfio_ccw_mdev_get_irq_info(struct vfio_irq_info *info)	236	static int vfio_ccw_mdev_get_irq_info(struct vfio_irq_info *info)
237	{	237	{
238	if (info->index != VFIO_CCW_IO_IRQ_INDEX)	238	if (info->index != VFIO_CCW_IO_IRQ_INDEX)
239	return -EINVAL;	239	return -EINVAL;

drivers/s390/crypto/ap_bus.c+24−14

@@ -668,10 +668,28 @@ static int ap_device_probe(struct device *dev) · 667 unmodified lines
668	struct ap_driver *ap_drv = to_ap_drv(dev->driver);	668	struct ap_driver *ap_drv = to_ap_drv(dev->driver);
669	int rc;	669	int rc;
670		670
		671	/* Add queue/card to list of active queues/cards */
		672	spin_lock_bh(&ap_list_lock);
		673	if (is_card_dev(dev))
		674	list_add(&to_ap_card(dev)->list, &ap_card_list);
		675	else
		676	list_add(&to_ap_queue(dev)->list,
		677	&to_ap_queue(dev)->card->queues);
		678	spin_unlock_bh(&ap_list_lock);
		679
671	ap_dev->drv = ap_drv;	680	ap_dev->drv = ap_drv;
672	rc = ap_drv->probe ? ap_drv->probe(ap_dev) : -ENODEV;	681	rc = ap_drv->probe ? ap_drv->probe(ap_dev) : -ENODEV;
673	if (rc)	682
		683	if (rc) {
		684	spin_lock_bh(&ap_list_lock);
		685	if (is_card_dev(dev))
		686	list_del_init(&to_ap_card(dev)->list);
		687	else
		688	list_del_init(&to_ap_queue(dev)->list);
		689	spin_unlock_bh(&ap_list_lock);
674	ap_dev->drv = NULL;	690	ap_dev->drv = NULL;
		691	}
		692
675	return rc;	693	return rc;
676	}	694	}
677		695
@@ -680,14 +698,17 @@ static int ap_device_remove(struct device *dev) · 2 unmodified lines
680	struct ap_device *ap_dev = to_ap_dev(dev);	698	struct ap_device *ap_dev = to_ap_dev(dev);
681	struct ap_driver *ap_drv = ap_dev->drv;	699	struct ap_driver *ap_drv = ap_dev->drv;
682		700
		701	if (ap_drv->remove)
		702	ap_drv->remove(ap_dev);
		703
		704	/* Remove queue/card from list of active queues/cards */
683	spin_lock_bh(&ap_list_lock);	705	spin_lock_bh(&ap_list_lock);
684	if (is_card_dev(dev))	706	if (is_card_dev(dev))
685	list_del_init(&to_ap_card(dev)->list);	707	list_del_init(&to_ap_card(dev)->list);
686	else	708	else
687	list_del_init(&to_ap_queue(dev)->list);	709	list_del_init(&to_ap_queue(dev)->list);
688	spin_unlock_bh(&ap_list_lock);	710	spin_unlock_bh(&ap_list_lock);
689	if (ap_drv->remove)	711
690	ap_drv->remove(ap_dev);
691	return 0;	712	return 0;
692	}	713	}
693		714
@@ -1056,10 +1077,6 @@ static void ap_scan_bus(struct work_struct *unused) · 362 unmodified lines
1056	}	1077	}
1057	/* get it and thus adjust reference counter */	1078	/* get it and thus adjust reference counter */
1058	get_device(&ac->ap_dev.device);	1079	get_device(&ac->ap_dev.device);
1059	/* Add card device to card list */
1060	spin_lock_bh(&ap_list_lock);
1061	list_add(&ac->list, &ap_card_list);
1062	spin_unlock_bh(&ap_list_lock);
1063	}	1080	}
1064	/* now create the new queue device */	1081	/* now create the new queue device */
1065	aq = ap_queue_create(qid, type);	1082	aq = ap_queue_create(qid, type);
@@ -1070,10 +1087,6 @@ static void ap_scan_bus(struct work_struct *unused) · 4 unmodified lines
1070	aq->ap_dev.device.parent = &ac->ap_dev.device;	1087	aq->ap_dev.device.parent = &ac->ap_dev.device;
1071	dev_set_name(&aq->ap_dev.device,	1088	dev_set_name(&aq->ap_dev.device,
1072	"%02x.%04x", id, dom);	1089	"%02x.%04x", id, dom);
1073	/* Add queue device to card queue list */
1074	spin_lock_bh(&ap_list_lock);
1075	list_add(&aq->list, &ac->queues);
1076	spin_unlock_bh(&ap_list_lock);
1077	/* Start with a device reset */	1090	/* Start with a device reset */
1078	spin_lock_bh(&aq->lock);	1091	spin_lock_bh(&aq->lock);
1079	ap_wait(ap_sm_event(aq, AP_EVENT_POLL));	1092	ap_wait(ap_sm_event(aq, AP_EVENT_POLL));
@@ -1081,9 +1094,6 @@ static void ap_scan_bus(struct work_struct *unused) · 1 unmodified line
1081	/* Register device */	1094	/* Register device */
1082	rc = device_register(&aq->ap_dev.device);	1095	rc = device_register(&aq->ap_dev.device);
1083	if (rc) {	1096	if (rc) {
1084	spin_lock_bh(&ap_list_lock);
1085	list_del_init(&aq->list);
1086	spin_unlock_bh(&ap_list_lock);
1087	put_device(&aq->ap_dev.device);	1097	put_device(&aq->ap_dev.device);
1088	continue;	1098	continue;
1089	}	1099	}

drivers/s390/crypto/ap_card.c+8−1

 static void ap_card_device_release(struct device *dev)
 {
-	kfree(to_ap_card(dev));
+	struct ap_card *ac = to_ap_card(dev);
+	if (!list_empty(&ac->list)) {
+		spin_lock_bh(&ap_list_lock);
+		list_del_init(&ac->list);
+		spin_unlock_bh(&ap_list_lock);
+	}
+	kfree(ac);
 }
 struct ap_card *ap_card_create(int id, int queue_depth, int device_type,

drivers/s390/crypto/ap_queue.c+8−1

 static void ap_queue_device_release(struct device *dev)
 {
-	kfree(to_ap_queue(dev));
+	struct ap_queue *aq = to_ap_queue(dev);
+	if (!list_empty(&aq->list)) {
+		spin_lock_bh(&ap_list_lock);
+		list_del_init(&aq->list);
+		spin_unlock_bh(&ap_list_lock);
+	}
+	kfree(aq);
 }
 struct ap_queue *ap_queue_create(ap_qid_t qid, int device_type)

drivers/s390/net/netiucv.c+2−2

@@ -1954,7 +1954,6 @@ static void netiucv_free_netdevice(struct net_device *dev) · 1953 unmodified lines
1954	privptr->conn = NULL; privptr->fsm = NULL;	1954	privptr->conn = NULL; privptr->fsm = NULL;
1955	/* privptr gets freed by free_netdev() */	1955	/* privptr gets freed by free_netdev() */
1956	}	1956	}
1957	free_netdev(dev);

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@@ -247,7 +247,6 @@ bias-bus-hold - latch weakly · 246 unmodified lines
247	bias-pull-up - pull up the pin	247	bias-pull-up - pull up the pin
248	bias-pull-down - pull down the pin	248	bias-pull-down - pull down the pin
249	bias-pull-pin-default - use pin-default pull state	249	bias-pull-pin-default - use pin-default pull state
250	bi-directional - pin supports simultaneous input/output operations
251	drive-push-pull - drive actively high and low	250	drive-push-pull - drive actively high and low
252	drive-open-drain - drive with open drain	251	drive-open-drain - drive with open drain
253	drive-open-source - drive with open source	252	drive-open-source - drive with open source
@@ -260,7 +259,6 @@ input-debounce - debounce mode with debound time X · 6 unmodified lines
260	power-source - select between different power supplies	259	power-source - select between different power supplies
261	low-power-enable - enable low power mode	260	low-power-enable - enable low power mode
262	low-power-disable - disable low power mode	261	low-power-disable - disable low power mode
263	output-enable - enable output on pin regardless of output value
264	output-low - set the pin to output mode with low level	262	output-low - set the pin to output mode with low level
265	output-high - set the pin to output mode with high level	263	output-high - set the pin to output mode with high level
266	slew-rate - set the slew rate	264	slew-rate - set the slew rate

@@ -402,7 +402,7 @@ static struct power_pmu power9_isa207_pmu = { · 401 unmodified lines
402	.name = "POWER9",	402	.name = "POWER9",
403	.n_counter = MAX_PMU_COUNTERS,	403	.n_counter = MAX_PMU_COUNTERS,
404	.add_fields = ISA207_ADD_FIELDS,	404	.add_fields = ISA207_ADD_FIELDS,
405	.test_adder = ISA207_TEST_ADDER,	405	.test_adder = P9_DD1_TEST_ADDER,
406	.compute_mmcr = isa207_compute_mmcr,	406	.compute_mmcr = isa207_compute_mmcr,
407	.config_bhrb = power9_config_bhrb,	407	.config_bhrb = power9_config_bhrb,
408	.bhrb_filter_map = power9_bhrb_filter_map,	408	.bhrb_filter_map = power9_bhrb_filter_map,
@@ -421,7 +421,7 @@ static struct power_pmu power9_pmu = { · 12 unmodified lines
421	.name = "POWER9",	421	.name = "POWER9",
422	.n_counter = MAX_PMU_COUNTERS,	422	.n_counter = MAX_PMU_COUNTERS,
423	.add_fields = ISA207_ADD_FIELDS,	423	.add_fields = ISA207_ADD_FIELDS,
424	.test_adder = P9_DD1_TEST_ADDER,	424	.test_adder = ISA207_TEST_ADDER,
425	.compute_mmcr = isa207_compute_mmcr,	425	.compute_mmcr = isa207_compute_mmcr,
426	.config_bhrb = power9_config_bhrb,	426	.config_bhrb = power9_config_bhrb,
427	.bhrb_filter_map = power9_bhrb_filter_map,	427	.bhrb_filter_map = power9_bhrb_filter_map,

@@ -37,7 +37,7 @@ · 36 unmodified lines
37		37
38	#define T4FW_VERSION_MAJOR 0x01	38	#define T4FW_VERSION_MAJOR 0x01
39	#define T4FW_VERSION_MINOR 0x10	39	#define T4FW_VERSION_MINOR 0x10
40	#define T4FW_VERSION_MICRO 0x2B	40	#define T4FW_VERSION_MICRO 0x2D
41	#define T4FW_VERSION_BUILD 0x00	41	#define T4FW_VERSION_BUILD 0x00
42		42
43	#define T4FW_MIN_VERSION_MAJOR 0x01	43	#define T4FW_MIN_VERSION_MAJOR 0x01
@@ -46,7 +46,7 @@ · 2 unmodified lines
46		46
47	#define T5FW_VERSION_MAJOR 0x01	47	#define T5FW_VERSION_MAJOR 0x01
48	#define T5FW_VERSION_MINOR 0x10	48	#define T5FW_VERSION_MINOR 0x10
49	#define T5FW_VERSION_MICRO 0x2B	49	#define T5FW_VERSION_MICRO 0x2D
50	#define T5FW_VERSION_BUILD 0x00	50	#define T5FW_VERSION_BUILD 0x00
51		51
52	#define T5FW_MIN_VERSION_MAJOR 0x00	52	#define T5FW_MIN_VERSION_MAJOR 0x00
@@ -55,7 +55,7 @@ · 2 unmodified lines
55		55
56	#define T6FW_VERSION_MAJOR 0x01	56	#define T6FW_VERSION_MAJOR 0x01
57	#define T6FW_VERSION_MINOR 0x10	57	#define T6FW_VERSION_MINOR 0x10
58	#define T6FW_VERSION_MICRO 0x2B	58	#define T6FW_VERSION_MICRO 0x2D
59	#define T6FW_VERSION_BUILD 0x00	59	#define T6FW_VERSION_BUILD 0x00
60		60
61	#define T6FW_MIN_VERSION_MAJOR 0x00	61	#define T6FW_MIN_VERSION_MAJOR 0x00