Pull EDAC updates from Borislav Petkov: "The new thing this time around is that we have three maintainers now and a new, old repo. New because it is new for the EDAC tree which is hosted there from now on and old because it is Tony's and mine's old RAS repo which we still use occasionally when the stuff isn't in tip. Summary: - EDAC tree has three maintainers and one new designated reviewer now, so that the work can scale better. - New driver for Mellanox' BlueField SoC DDR controller (Shravan Kumar Ramani) - AMD Rome support in amd64_edac (Yazen Ghannam and Isaac Vaughn) - Misc fixes, cleanups and code improvements" * tag 'edac_for_5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras: EDAC/amd64: Add PCI device IDs for family 17h, model 70h MAINTAINERS: Add Robert as a EDAC reviewer EDAC/mc_sysfs: Make debug messages consistent EDAC/mc_sysfs: Remove pointless gotos EDAC: Prefer 'unsigned int' to bare use of 'unsigned' EDAC/amd64: Support asymmetric dual-rank DIMMs EDAC/amd64: Cache secondary Chip Select registers EDAC/amd64: Decode syndrome before translating address EDAC/amd64: Find Chip Select memory size using Address Mask EDAC/amd64: Initialize DIMM info for systems with more than two channels EDAC/amd64: Recognize DRAM device type ECC capability EDAC/amd64: Support more than two controllers for chip selects handling EDAC/mc: Cleanup _edac_mc_free() code EDAC, pnd2: Fix ioremap() size in dnv_rd_reg() EDAC, mellanox: Add ECC support for BlueField DDR4 EDAC/altera: Use the proper type for the IRQ status bits EDAC/mc: Fix grain_bits calculation edac: altera: Move Stratix10 SDRAM ECC to peripheral MAINTAINERS: update EDAC entry to reflect current tree and maintainers
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| @@ -440,7 +440,7 @@ struct dimm_info { · 439 unmodified lines | ||
| 440 | 440 | char label[EDAC_MC_LABEL_LEN + 1]; /* DIMM label on motherboard */ |
| 441 | 441 | |
| 442 | 442 | /* Memory location data */ |
| 443 | − unsigned location[EDAC_MAX_LAYERS]; | |
| 443 | + unsigned int location[EDAC_MAX_LAYERS]; | |
| 444 | 444 | |
| 445 | 445 | struct mem_ctl_info *mci; /* the parent */ |
| 446 | 446 | |
| @@ -451,7 +451,7 @@ struct dimm_info { · 4 unmodified lines | ||
| 451 | 451 | |
| 452 | 452 | u32 nr_pages; /* number of pages on this dimm */ |
| 453 | 453 | |
| 454 | − unsigned csrow, cschannel; /* Points to the old API data */ | |
| 454 | + unsigned int csrow, cschannel; /* Points to the old API data */ | |
| 455 | 455 | |
| 456 | 456 | u16 smbios_handle; /* Handle for SMBIOS type 17 */ |
| 457 | 457 | }; |
| @@ -597,7 +597,7 @@ struct mem_ctl_info { · 139 unmodified lines | ||
| 597 | 597 | unsigned long page); |
| 598 | 598 | int mc_idx; |
| 599 | 599 | struct csrow_info **csrows; |
| 600 | − unsigned nr_csrows, num_cschannel; | |
| 600 | + unsigned int nr_csrows, num_cschannel; | |
| 601 | 601 | |
| 602 | 602 | /* |
| 603 | 603 | * Memory Controller hierarchy |
| @@ -608,14 +608,14 @@ struct mem_ctl_info { · 4 unmodified lines | ||
| 608 | 608 | * of the recent drivers enumerate memories per DIMM, instead. |
| 609 | 609 | * When the memory controller is per rank, csbased is true. |
| 610 | 610 | */ |
| 611 | − unsigned n_layers; | |
| 611 | + unsigned int n_layers; | |
| 612 | 612 | struct edac_mc_layer *layers; |
| 613 | 613 | bool csbased; |
| 614 | 614 | |
| 615 | 615 | /* |
| 616 | 616 | * DIMM info. Will eventually remove the entire csrows_info some day |
| 617 | 617 | */ |
| 618 | − unsigned tot_dimms; | |
| 618 | + unsigned int tot_dimms; | |
| 619 | 619 | struct dimm_info **dimms; |
| 620 | 620 | |
| 621 | 621 | /* |