Pull drm merge from Dave Airlie: "Highlights: - TI LCD controller KMS driver - TI OMAP KMS driver merged from staging - drop gma500 stub driver - the fbcon locking fixes - the vgacon dirty like zebra fix. - open firmware videomode and hdmi common code helpers - major locking rework for kms object handling - pageflip/cursor won't block on polling anymore! - fbcon helper and prime helper cleanups - i915: all over the map, haswell power well enhancements, valleyview macro horrors cleaned up, killing lots of legacy GTT code, - radeon: CS ioctl unification, deprecated UMS support, gpu reset rework, VM fixes - nouveau: reworked thermal code, external dp/tmds encoder support (anx9805), fences sleep instead of polling, - exynos: all over the driver fixes." Lovely conflict in radeon/evergreen_cs.c between commit de0babd60d8d ("drm/radeon: enforce use of radeon_get_ib_value when reading user cmd") and the new changes that modified that evergreen_dma_cs_parse() function. * 'drm-next' of git://people.freedesktop.org/~airlied/linux: (508 commits) drm/tilcdc: only build on arm drm/i915: Revert hdmi HDP pin checks drm/tegra: Add list of framebuffers to debugfs drm/tegra: Fix color expansion drm/tegra: Split DC_CMD_STATE_CONTROL register write drm/tegra: Implement page-flipping support drm/tegra: Implement VBLANK support drm/tegra: Implement .mode_set_base() drm/tegra: Add plane support drm/tegra: Remove bogus tegra_framebuffer structure drm: Add consistency check for page-flipping drm/radeon: Use generic HDMI infoframe helpers drm/tegra: Use generic HDMI infoframe helpers drm: Add EDID helper documentation drm: Add HDMI infoframe helpers video: Add generic HDMI infoframe helpers drm: Add some missing forward declarations drm: Move mode tables to drm_edid.c drm: Remove duplicate drm_mode_cea_vic() gma500: Fix n, m1 and m2 clock limits for sdvo and lvds ...
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| @@ -308,6 +308,8 @@ typedef struct drm_i915_irq_wait { · 307 unmodified lines | ||
| 308 | 308 | #define I915_PARAM_RSVD_FOR_FUTURE_USE 22 |
| 309 | 309 | #define I915_PARAM_HAS_SECURE_BATCHES 23 |
| 310 | 310 | #define I915_PARAM_HAS_PINNED_BATCHES 24 |
| 311 | +#define I915_PARAM_HAS_EXEC_NO_RELOC 25 | |
| 312 | +#define I915_PARAM_HAS_EXEC_HANDLE_LUT 26 | |
| 311 | 313 | |
| 312 | 314 | typedef struct drm_i915_getparam { |
| 313 | 315 | int param; |
| @@ -628,7 +630,11 @@ struct drm_i915_gem_exec_object2 { · 314 unmodified lines | ||
| 628 | 630 | __u64 offset; |
| 629 | 631 | |
| 630 | 632 | #define EXEC_OBJECT_NEEDS_FENCE (1<<0) |
| 633 | +#define EXEC_OBJECT_NEEDS_GTT (1<<1) | |
| 634 | +#define EXEC_OBJECT_WRITE (1<<2) | |
| 635 | +#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_WRITE<<1) | |
| 631 | 636 | __u64 flags; |
| 637 | + | |
| 632 | 638 | __u64 rsvd1; |
| 633 | 639 | __u64 rsvd2; |
| 634 | 640 | }; |
| @@ -687,6 +693,20 @@ struct drm_i915_gem_execbuffer2 { · 52 unmodified lines | ||
| 687 | 693 | */ |
| 688 | 694 | #define I915_EXEC_IS_PINNED (1<<10) |
| 689 | 695 | |
| 696 | +/** Provide a hint to the kernel that the command stream and auxilliary | |
| 697 | + * state buffers already holds the correct presumed addresses and so the | |
| 698 | + * relocation process may be skipped if no buffers need to be moved in | |
| 699 | + * preparation for the execbuffer. | |
| 700 | + */ | |
| 701 | +#define I915_EXEC_NO_RELOC (1<<11) | |
| 702 | + | |
| 703 | +/** Use the reloc.handle as an index into the exec object array rather | |
| 704 | + * than as the per-file handle. | |
| 705 | + */ | |
| 706 | +#define I915_EXEC_HANDLE_LUT (1<<12) | |
| 707 | + | |
| 708 | +#define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_HANDLE_LUT<<1) | |
| 709 | + | |
| 690 | 710 | #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) |
| 691 | 711 | #define i915_execbuffer2_set_context_id(eb2, context) \ |
| 692 | 712 | (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK |
| @@ -0,0 +1,123 @@ | ||
| 1 | +/* | |
| 2 | + * include/uapi/drm/omap_drm.h | |
| 3 | + * | |
| 4 | + * Copyright (C) 2011 Texas Instruments | |
| 5 | + * Author: Rob Clark <rob@ti.com> | |
| 6 | + * | |
| 7 | + * This program is free software; you can redistribute it and/or modify it | |
| 8 | + * under the terms of the GNU General Public License version 2 as published by | |
| 9 | + * the Free Software Foundation. | |
| 10 | + * | |
| 11 | + * This program is distributed in the hope that it will be useful, but WITHOUT | |
| 12 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 13 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
| 14 | + * more details. | |
| 15 | + * | |
| 16 | + * You should have received a copy of the GNU General Public License along with | |
| 17 | + * this program. If not, see <http://www.gnu.org/licenses/>. | |
| 18 | + */ | |
| 19 | + | |
| 20 | +#ifndef __OMAP_DRM_H__ | |
| 21 | +#define __OMAP_DRM_H__ | |
| 22 | + | |
| 23 | +#include <drm/drm.h> | |
| 24 | + | |
| 25 | +/* Please note that modifications to all structs defined here are | |
| 26 | + * subject to backwards-compatibility constraints. | |
| 27 | + */ | |
| 28 | + | |
| 29 | +#define OMAP_PARAM_CHIPSET_ID 1 /* ie. 0x3430, 0x4430, etc */ | |
| 30 | + | |
| 31 | +struct drm_omap_param { | |
| 32 | + uint64_t param; /* in */ | |
| 33 | + uint64_t value; /* in (set_param), out (get_param) */ | |
| 34 | +}; | |
| 35 | + | |
| 36 | +#define OMAP_BO_SCANOUT 0x00000001 /* scanout capable (phys contiguous) */ | |
| 37 | +#define OMAP_BO_CACHE_MASK 0x00000006 /* cache type mask, see cache modes */ | |
| 38 | +#define OMAP_BO_TILED_MASK 0x00000f00 /* tiled mapping mask, see tiled modes */ | |
| 39 | + | |
| 40 | +/* cache modes */ | |
| 41 | +#define OMAP_BO_CACHED 0x00000000 /* default */ | |
| 42 | +#define OMAP_BO_WC 0x00000002 /* write-combine */ | |
| 43 | +#define OMAP_BO_UNCACHED 0x00000004 /* strongly-ordered (uncached) */ | |
| 44 | + | |
| 45 | +/* tiled modes */ | |
| 46 | +#define OMAP_BO_TILED_8 0x00000100 | |
| 47 | +#define OMAP_BO_TILED_16 0x00000200 | |
| 48 | +#define OMAP_BO_TILED_32 0x00000300 | |
| 49 | +#define OMAP_BO_TILED (OMAP_BO_TILED_8 | OMAP_BO_TILED_16 | OMAP_BO_TILED_32) | |
| 50 | + | |
| 51 | +union omap_gem_size { | |
| 52 | + uint32_t bytes; /* (for non-tiled formats) */ | |
| 53 | + struct { | |
| 54 | + uint16_t width; | |
| 55 | + uint16_t height; | |
| 56 | + } tiled; /* (for tiled formats) */ | |
| 57 | +}; | |
| 58 | + | |
| 59 | +struct drm_omap_gem_new { | |
| 60 | + union omap_gem_size size; /* in */ | |
| 61 | + uint32_t flags; /* in */ | |
| 62 | + uint32_t handle; /* out */ | |
| 63 | + uint32_t __pad; | |
| 64 | +}; | |
| 65 | + | |
| 66 | +/* mask of operations: */ | |
| 67 | +enum omap_gem_op { | |
| 68 | + OMAP_GEM_READ = 0x01, | |
| 69 | + OMAP_GEM_WRITE = 0x02, | |
| 70 | +}; | |
| 71 | + | |
| 72 | +struct drm_omap_gem_cpu_prep { | |
| 73 | + uint32_t handle; /* buffer handle (in) */ | |
| 74 | + uint32_t op; /* mask of omap_gem_op (in) */ | |
| 75 | +}; | |
| 76 | + | |
| 77 | +struct drm_omap_gem_cpu_fini { | |
| 78 | + uint32_t handle; /* buffer handle (in) */ | |
| 79 | + uint32_t op; /* mask of omap_gem_op (in) */ | |
| 80 | + /* TODO maybe here we pass down info about what regions are touched | |
| 81 | + * by sw so we can be clever about cache ops? For now a placeholder, | |
| 82 | + * set to zero and we just do full buffer flush.. | |
| 83 | + */ | |
| 84 | + uint32_t nregions; | |
| 85 | + uint32_t __pad; | |
| 86 | +}; | |
| 87 | + | |
| 88 | +struct drm_omap_gem_info { | |
| 89 | + uint32_t handle; /* buffer handle (in) */ | |
| 90 | + uint32_t pad; | |
| 91 | + uint64_t offset; /* mmap offset (out) */ | |
| 92 | + /* note: in case of tiled buffers, the user virtual size can be | |
| 93 | + * different from the physical size (ie. how many pages are needed | |
| 94 | + * to back the object) which is returned in DRM_IOCTL_GEM_OPEN.. | |
| 95 | + * This size here is the one that should be used if you want to | |
| 96 | + * mmap() the buffer: | |
| 97 | + */ | |
| 98 | + uint32_t size; /* virtual size for mmap'ing (out) */ | |
| 99 | + uint32_t __pad; | |
| 100 | +}; | |
| 101 | + | |
| 102 | +#define DRM_OMAP_GET_PARAM 0x00 | |
| 103 | +#define DRM_OMAP_SET_PARAM 0x01 | |
| 104 | +/* placeholder for plugin-api | |
| 105 | +#define DRM_OMAP_GET_BASE 0x02 | |
| 106 | +*/ | |
| 107 | +#define DRM_OMAP_GEM_NEW 0x03 | |
| 108 | +#define DRM_OMAP_GEM_CPU_PREP 0x04 | |
| 109 | +#define DRM_OMAP_GEM_CPU_FINI 0x05 | |
| 110 | +#define DRM_OMAP_GEM_INFO 0x06 | |
| 111 | +#define DRM_OMAP_NUM_IOCTLS 0x07 | |
| 112 | + | |
| 113 | +#define DRM_IOCTL_OMAP_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_OMAP_GET_PARAM, struct drm_omap_param) | |
| 114 | +#define DRM_IOCTL_OMAP_SET_PARAM DRM_IOW (DRM_COMMAND_BASE + DRM_OMAP_SET_PARAM, struct drm_omap_param) | |
| 115 | +/* placeholder for plugin-api | |
| 116 | +#define DRM_IOCTL_OMAP_GET_BASE DRM_IOWR(DRM_COMMAND_BASE + DRM_OMAP_GET_BASE, struct drm_omap_get_base) | |
| 117 | +*/ | |
| 118 | +#define DRM_IOCTL_OMAP_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_OMAP_GEM_NEW, struct drm_omap_gem_new) | |
| 119 | +#define DRM_IOCTL_OMAP_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_OMAP_GEM_CPU_PREP, struct drm_omap_gem_cpu_prep) | |
| 120 | +#define DRM_IOCTL_OMAP_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_OMAP_GEM_CPU_FINI, struct drm_omap_gem_cpu_fini) | |
| 121 | +#define DRM_IOCTL_OMAP_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_OMAP_GEM_INFO, struct drm_omap_gem_info) | |
| 122 | + | |
| 123 | +#endif /* __OMAP_DRM_H__ */ | |