- writeback - D_VREG? vector register type/index field? - ACASE/ABCASE - register in ACASE must be dead after use, or better, take two registers MOVWZ -> MOVWU? basic §3.2 CBZ Rt, label (imm19) CBNZ B. label (imm19) SVC $imm16 HVC SMC BRK HLT DCPS1 DCPS2 DCPS3 MSR $imm, CRn HINT CLREX DSB DMB ISB SYS CRm, CRn, Rt MSR CRm, CRn, Rt SYSL CRm, CRn, Rt MRS CRm, CRn, Rt TBZ $b5:b40, Rt, label (imm14) # bit number TBNZ B label (imm26) BL BR Rn BLR RET ERET Rn=1F DRPS §3.3 [SIMD later] LDR label:19, Rt LDR [SIMD&FP] LDRSW PRFM [load/store exclusive, later] [load/store no-allocate pair, later] # post-index write-back load/store [simm9 range -256 to 255, then scaled] STR[BWHX] #, [Rn], Rt LDR[S][BWHX] # pre-index write-back STR[BWHX] [Rn, ]!, Rt LDR[S][BWHX] # unsigned offset STR[BWHX] (Rn), Rt # scaled by operand size field LDR[S][BWHX] STR[BWHX] Rm [