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Added basic writing support. Removed the string representations of instructions and changed instruction reading to ensure that an instance of a specific class is created for each instruction. Fixed the definition of the frame instruction.

David Boddie committed 9 years ago

Commit 9bbb0591 parent b2622162 files · +245 −57Browse files

Showing the changes to opcodes.py (1 of 2 files). Show all

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opcodes.py+58−44
@@ -21,34 +21,6 @@ along with this program. If not, see <http://www.gnu.org/licenses/>. · 20 unmodified lines
21 21
22from utils import read_B, read_OP, write_B, write_OP22from utils import read_B, read_OP, write_B, write_OP
23 23
24# Define string representations of the opcodes.
25
26instruction_names = [
27 "nop", "alt", "nbalt", "goto", "call", "frame", "spawn", "runt",
28 "load", "mcall", "mspawn", "mframe", "ret", "jmp", "case", "exit",
29 "new", "newa", "newcb", "newcw", "newcf", "newcp", "newcm", "newcmp",
30 "send", "recv", "consb", "consw", "consp", "consf", "consm", "consmp",
31 "headb", "headw", "headp", "headf", "headm", "headmp", "tail", "lea",
32 "indx", "movp", "movm", "movmp", "movb", "movw", "movf", "cvtbw",
33 "cvtwb", "cvtfw", "cvtwf", "cvtca", "cvtac", "cvtwc", "cvtcw", "cvtfc",
34 "cvtcf", "addb", "addw", "addf", "subb", "subw", "subf", "mulb",
35 "mulw", "mulf", "divb", "divw", "divf", "modw", "modb", "andb",
36 "andw", "orb", "orw", "xorb", "xorw", "shlb", "shlw", "shrb",
37 "shrw", "insc", "indc", "addc", "lenc", "lena", "lenl", "beqb",
38 "bneb", "bltb", "bleb", "bgtb", "bgeb", "beqw", "bnew", "bltw",
39 "blew", "bgtw", "bgew", "beqf", "bnef", "bltf", "blef", "bgtf",
40 "bgef", "beqc", "bnec", "bltc", "blec", "bgtc", "bgec", "slicea",
41 "slicela", "slicec", "indw", "indf", "indb", "negf", "movl", "addl",
42 "subl", "divl", "modl", "mull", "andl", "orl", "xorl", "shll",
43 "shrl", "bnel", "bltl", "blel", "bgtl", "bgel", "beql", "cvtlf",
44 "cvtfl", "cvtlw", "cvtwl", "cvtlc", "cvtcl", "headl", "consl", "newcl",
45 "casec", "indl", "movpc", "tcmp", "mnewz", "cvtrf", "cvtfr", "cvtws",
46 "cvtsw", "lsrw", "lsrl", "eclr", "newz", "newaz", "raise", "casel",
47 "mulx", "divx", "cvtxx", "mulx0", "divx0", "cvtxx0", "mulx1", "divx1",
48 "cvtxx1", "cvtfx", "cvtxf", "expw", "expl", "expf", "self"
49 ]
50
51
52class Instruction:24class Instruction:
53 25
54 def __init__(self):26 def __init__(self):
@@ -60,19 +32,34 @@ class Instruction: · 5 unmodified lines
60 32
61 def read(self, f):33 def read(self, f):
62 34
63 self.opcode = read_B(f)35 opcode = read_B(f)
64 self.address_mode = read_B(f)36 class_ = instructions[opcode]
37
38 address_mode = read_B(f)
65 39
66 middle = self.address_mode & 0xc040 middle = address_mode & 0xc0
67 self.middle = self.read_middle_operand(middle, f)41 middle = self.read_middle_operand(middle, f)
68 42
69 source = (self.address_mode & 0x38) >> 343 source = (address_mode & 0x38) >> 3
70 self.source = self.read_operand(source, f)44 source = self.read_operand(source, f)
71 45
72 destination = self.address_mode & 0x0746 destination = address_mode & 0x07
73 self.destination = self.read_operand(destination, f)47 destination = self.read_operand(destination, f)
74 48
75 return self49 if issubclass(class_, Src):
50 return class_(source)
51 elif issubclass(class_, Src_Src):
52 return class_(source, middle)
53 elif issubclass(class_, Src_Dst):
54 return class_(source, destination)
55 elif issubclass(class_, Src_Src_Dst):
56 return class_(source, middle, destination)
57 elif issubclass(class_, Src_Src_Src):
58 return class_(source, middle, destination)
59 elif issubclass(class_, Dst):
60 return class_(destination)
61 else:
62 return class_()
76 63
77 def set_address_mode(self):64 def set_address_mode(self):
78 65
@@ -130,7 +117,7 @@ class Instruction: · 51 unmodified lines
130 def __repr__(self):117 def __repr__(self):
131 118
132 try:119 try:
133 name = instruction_names[self.opcode]120 name = self.__class__.__name__
134 except IndexError:121 except IndexError:
135 name = hex(self.opcode)122 name = hex(self.opcode)
136 123
@@ -203,11 +190,11 @@ class DoubleShortOffset(Operand): · 66 unmodified lines
203 write_OP(f, self.value[0] & 0xffff)190 write_OP(f, self.value[0] & 0xffff)
204 write_OP(f, self.value[1] & 0xffff)191 write_OP(f, self.value[1] & 0xffff)
205 192
206class DoubleShortOffsetMP(Operand):193class DoubleShortOffsetMP(DoubleShortOffset):
207 str_pattern = "%i(%i(mp))"194 str_pattern = "%i(%i(mp))"
208 address_mode = 0x04195 address_mode = 0x04
209 196
210class DoubleShortOffsetFP(Operand):197class DoubleShortOffsetFP(DoubleShortOffset):
211 str_pattern = "%i(%i(fp))"198 str_pattern = "%i(%i(fp))"
212 address_mode = 0x05199 address_mode = 0x05
213 200
@@ -250,7 +237,7 @@ class Src_Src_Dst(Instruction): · 36 unmodified lines
250 self.destination = dst237 self.destination = dst
251 self.set_address_mode()238 self.set_address_mode()
252 239
253class Src_Src_src(Instruction):240class Src_Src_Src(Instruction):
254 241
255 def __init__(self, src1, src2, src3):242 def __init__(self, src1, src2, src3):
256 243
@@ -380,7 +367,7 @@ class exit(Instruction): opcode = 0x0f · 123 unmodified lines
380class expf(Src_Src_Dst): opcode = 0xad # word word -> float (xec.c)367class expf(Src_Src_Dst): opcode = 0xad # word word -> float (xec.c)
381class expl(Src_Src_Dst): opcode = 0xac # word long -> long (xec.c)368class expl(Src_Src_Dst): opcode = 0xac # word long -> long (xec.c)
382class expw(Src_Src_Dst): opcode = 0xab # word word -> word (xec.c)369class expw(Src_Src_Dst): opcode = 0xab # word word -> word (xec.c)
383class frame(Src_Src): opcode = 0x05370class frame(Src_Dst): opcode = 0x05 # not src1, src2 as in documentation
384class goto(Src_Dst): opcode = 0x03371class goto(Src_Dst): opcode = 0x03
385class headb(headx): opcode = 0x20372class headb(headx): opcode = 0x20
386class headf(headx): opcode = 0x23373class headf(headx): opcode = 0x23
@@ -404,7 +391,7 @@ class lenl(Src_Dst): opcode = 0x56 · 17 unmodified lines
404class load(Src_Src_Dst): opcode = 0x08391class load(Src_Src_Dst): opcode = 0x08
405class lsrl(lsrx): opcode = 0x9a392class lsrl(lsrx): opcode = 0x9a
406class lsrw(lsrx): opcode = 0x99393class lsrw(lsrx): opcode = 0x99
407class mcall(Src_Src_src): opcode = 0x09394class mcall(Src_Src_Src): opcode = 0x09
408class mframe(Src_Src_Dst): opcode = 0x0b395class mframe(Src_Src_Dst): opcode = 0x0b
409class mnewz(Src_Src_Dst): opcode = 0x94396class mnewz(Src_Src_Dst): opcode = 0x94
410class modb(modx): opcode = 0x46397class modb(modx): opcode = 0x46
@@ -418,7 +405,7 @@ class movmp(Src_Src_Dst): opcode = 0x2b · 7 unmodified lines
418class movpc(Src_Dst): opcode = 0x92405class movpc(Src_Dst): opcode = 0x92
419class movp(Src_Dst): opcode = 0x29406class movp(Src_Dst): opcode = 0x29
420class movw(movx): opcode = 0x2d407class movw(movx): opcode = 0x2d
421class mspawn(Src_Src_src): opcode = 0x0a408class mspawn(Src_Src_Src): opcode = 0x0a
422class mulb(mulx_): opcode = 0x3f409class mulb(mulx_): opcode = 0x3f
423class mulf(mulx_): opcode = 0x41410class mulf(mulx_): opcode = 0x41
424class mull(mulx_): opcode = 0x7b411class mull(mulx_): opcode = 0x7b
@@ -468,3 +455,30 @@ class tcmp(Src_Dst): opcode = 0x93 · 43 unmodified lines
468class xorb(xorx): opcode = 0x4b455class xorb(xorx): opcode = 0x4b
469class xorl(xorx): opcode = 0x7e456class xorl(xorx): opcode = 0x7e
470class xorw(xorx): opcode = 0x4c457class xorw(xorx): opcode = 0x4c
458
459# Define a list to map opcodes to instruction classes.
460
461instructions = [
462 nop, alt, nbalt, goto, call, frame, spawn, runt,
463 load, mcall, mspawn, mframe, ret, jmp, case, exit,
464 new, newa, newcb, newcw, newcf, newcp, newcm, newcmp,
465 send, recv, consb, consw, consp, consf, consm, consmp,
466 headb, headw, headp, headf, headm, headmp, tail, lea,
467 indx, movp, movm, movmp, movb, movw, movf, cvtbw,
468 cvtwb, cvtfw, cvtwf, cvtca, cvtac, cvtwc, cvtcw, cvtfc,
469 cvtcf, addb, addw, addf, subb, subw, subf, mulb,
470 mulw, mulf, divb, divw, divf, modw, modb, andb,
471 andw, orb, orw, xorb, xorw, shlb, shlw, shrb,
472 shrw, insc, indc, addc, lenc, lena, lenl, beqb,
473 bneb, bltb, bleb, bgtb, bgeb, beqw, bnew, bltw,
474 blew, bgtw, bgew, beqf, bnef, bltf, blef, bgtf,
475 bgef, beqc, bnec, bltc, blec, bgtc, bgec, slicea,
476 slicela, slicec, indw, indf, indb, negf, movl, addl,
477 subl, divl, modl, mull, andl, orl, xorl, shll,
478 shrl, bnel, bltl, blel, bgtl, bgel, beql, cvtlf,
479 cvtfl, cvtlw, cvtwl, cvtlc, cvtcl, headl, consl, newcl,
480 casec, indl, movpc, tcmp, mnewz, cvtrf, cvtfr, cvtws,
481 cvtsw, lsrw, lsrl, eclr, newz, newaz, raise_, casel,
482 mulx, divx, cvtxx, mulx0, divx0, cvtxx0, mulx1, divx1,
483 cvtxx1, cvtfx, cvtxf, expw, expl, expf, self
484 ]