T-Head C908 (cycles): vc1dsp.vc1_inv_trans_8x8_c: 871.7 vc1dsp.vc1_inv_trans_8x8_rvv_i32: 286.7
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| @@ -26,6 +26,7 @@ · 25 unmodified lines | ||
| 26 | 26 | #include "libavcodec/vc1.h" |
| 27 | 27 | |
| 28 | 28 | void ff_vc1_inv_trans_8x8_dc_rvv(uint8_t *dest, ptrdiff_t stride, int16_t *block); |
| 29 | +void ff_vc1_inv_trans_8x8_rvv(int16_t block[64]); | |
| 29 | 30 | void ff_vc1_inv_trans_4x8_dc_rvv(uint8_t *dest, ptrdiff_t stride, int16_t *block); |
| 30 | 31 | void ff_vc1_inv_trans_8x4_dc_rvv(uint8_t *dest, ptrdiff_t stride, int16_t *block); |
| 31 | 32 | void ff_vc1_inv_trans_4x4_dc_rvv(uint8_t *dest, ptrdiff_t stride, int16_t *block); |
| @@ -53,6 +54,7 @@ av_cold void ff_vc1dsp_init_riscv(VC1DSPContext *dsp) · 21 unmodified lines | ||
| 53 | 54 | # if HAVE_RVV |
| 54 | 55 | if (flags & AV_CPU_FLAG_RVV_I32) { |
| 55 | 56 | if (ff_rv_vlen_least(128)) { |
| 57 | + dsp->vc1_inv_trans_8x8 = ff_vc1_inv_trans_8x8_rvv; | |
| 56 | 58 | dsp->vc1_inv_trans_4x8_dc = ff_vc1_inv_trans_4x8_dc_rvv; |
| 57 | 59 | dsp->vc1_inv_trans_4x4_dc = ff_vc1_inv_trans_4x4_dc_rvv; |
| 58 | 60 | dsp->avg_vc1_mspel_pixels_tab[0][0] = ff_avg_pixels16x16_rvv; |
| @@ -113,6 +113,116 @@ func ff_vc1_inv_trans_4x4_dc_rvv, zve32x · 112 unmodified lines | ||
| 113 | 113 | ret |
| 114 | 114 | endfunc |
| 115 | 115 | |
| 116 | + .variant_cc ff_vc1_inv_trans_8_rvv | |
| 117 | +func ff_vc1_inv_trans_8_rvv, zve32x | |
| 118 | + li t4, 12 | |
| 119 | + vsll.vi v18, v6, 4 | |
| 120 | + li t2, 6 | |
| 121 | + vmul.vx v8, v0, t4 | |
| 122 | + li t5, 15 | |
| 123 | + vmul.vx v10, v4, t4 | |
| 124 | + li t3, 9 | |
| 125 | + # t[2..5] = [6 9 12 15] | |
| 126 | + vsll.vi v12, v2, 4 | |
| 127 | + vmul.vx v14, v6, t2 | |
| 128 | + vmul.vx v16, v2, t2 | |
| 129 | + vadd.vv v26, v12, v14 # t3 | |
| 130 | + vadd.vv v24, v8, v10 # t1 | |
| 131 | + vsub.vv v25, v8, v10 # t2 | |
| 132 | + vsub.vv v27, v16, v18 # t4 | |
| 133 | + vadd.vv v28, v24, v26 # t5 | |
| 134 | + vsub.vv v31, v24, v26 # t8 | |
| 135 | + vadd.vv v29, v25, v27 # t6 | |
| 136 | + vsub.vv v30, v25, v27 # t7 | |
| 137 | + vsll.vi v20, v1, 4 | |
| 138 | + vmul.vx v21, v3, t5 | |
| 139 | + vmul.vx v22, v5, t3 | |
| 140 | + vsll.vi v23, v7, 2 | |
| 141 | + vadd.vv v20, v20, v21 | |
| 142 | + vadd.vv v22, v22, v23 | |
| 143 | + vsll.vi v21, v3, 2 | |
| 144 | + vadd.vv v16, v20, v22 # t1 | |
| 145 | + vmul.vx v20, v1, t5 | |
| 146 | + vsll.vi v22, v5, 4 | |
| 147 | + vmul.vx v23, v7, t3 | |
| 148 | + vsub.vv v20, v20, v21 | |
| 149 | + vadd.vv v22, v22, v23 | |
| 150 | + vsll.vi v21, v3, 4 | |
| 151 | + vsub.vv v17, v20, v22 # t2 | |
| 152 | + vmul.vx v20, v1, t3 | |
| 153 | + vsll.vi v22, v5, 2 | |
| 154 | + vmul.vx v23, v7, t5 | |
| 155 | + vsub.vv v20, v20, v21 | |
| 156 | + vadd.vv v22, v22, v23 | |
| 157 | + vmul.vx v21, v3, t3 | |
| 158 | + vadd.vv v18, v20, v22 # t3 | |
| 159 | + vsll.vi v20, v1, 2 | |
| 160 | + vmul.vx v22, v5, t5 | |
| 161 | + vsll.vi v23, v7, 4 | |
| 162 | + vsub.vv v20, v20, v21 | |
| 163 | + vsub.vv v22, v22, v23 | |
| 164 | + vadd.vv v0, v28, v16 | |
| 165 | + vadd.vv v19, v20, v22 # t4 | |
| 166 | + vadd.vv v1, v29, v17 | |
| 167 | + vadd.vv v2, v30, v18 | |
| 168 | + vadd.vv v3, v31, v19 | |
| 169 | + vsub.vv v4, v31, v19 | |
| 170 | + vsub.vv v5, v30, v18 | |
| 171 | + vsub.vv v6, v29, v17 | |
| 172 | + vsub.vv v7, v28, v16 | |
| 173 | + jr t0 | |
| 174 | +endfunc | |
| 175 | + | |
| 176 | +func ff_vc1_inv_trans_8x8_rvv, zve32x | |
| 177 | + csrwi vxrm, 0 | |
| 178 | + vsetivli zero, 8, e16, m1, ta, ma | |
| 179 | + addi a1, a0, 1 * 8 * 2 | |
| 180 | + vle16.v v0, (a0) | |
| 181 | + addi a2, a0, 2 * 8 * 2 | |
| 182 | + vle16.v v1, (a1) | |
| 183 | + addi a3, a0, 3 * 8 * 2 | |
| 184 | + vle16.v v2, (a2) | |
| 185 | + addi a4, a0, 4 * 8 * 2 | |
| 186 | + vle16.v v3, (a3) | |
| 187 | + addi a5, a0, 5 * 8 * 2 | |
| 188 | + vle16.v v4, (a4) | |
| 189 | + addi a6, a0, 6 * 8 * 2 | |
| 190 | + vle16.v v5, (a5) | |
| 191 | + addi a7, a0, 7 * 8 * 2 | |
| 192 | + vle16.v v6, (a6) | |
| 193 | + vle16.v v7, (a7) | |
| 194 | + jal t0, ff_vc1_inv_trans_8_rvv | |
| 195 | + .irp n,0,1,2,3,4,5,6,7 | |
| 196 | + vssra.vi v\n, v\n, 3 | |
| 197 | + .endr | |
| 198 | + vsseg8e16.v v0, (a0) | |
| 199 | + .irp n,0,1,2,3,4,5,6,7 | |
| 200 | + vle16.v v\n, (a\n) | |
| 201 | + .endr | |
| 202 | + jal t0, ff_vc1_inv_trans_8_rvv | |
| 203 | + vadd.vi v4, v4, 1 | |
| 204 | + vadd.vi v5, v5, 1 | |
| 205 | + vssra.vi v4, v4, 7 | |
| 206 | + vssra.vi v5, v5, 7 | |
| 207 | + vse16.v v4, (a4) | |
| 208 | + vadd.vi v6, v6, 1 | |
| 209 | + vse16.v v5, (a5) | |
| 210 | + vadd.vi v7, v7, 1 | |
| 211 | + vssra.vi v6, v6, 7 | |
| 212 | + vssra.vi v7, v7, 7 | |
| 213 | + vse16.v v6, (a6) | |
| 214 | + vssra.vi v0, v0, 7 | |
| 215 | + vse16.v v7, (a7) | |
| 216 | + vssra.vi v1, v1, 7 | |
| 217 | + vse16.v v0, (a0) | |
| 218 | + vssra.vi v2, v2, 7 | |
| 219 | + vse16.v v1, (a1) | |
| 220 | + vssra.vi v3, v3, 7 | |
| 221 | + vse16.v v2, (a2) | |
| 222 | + vse16.v v3, (a3) | |
| 223 | + ret | |
| 224 | +endfunc | |
| 225 | + | |
| 116 | 226 | .macro mspel_op op pos n1 n2 |
| 117 | 227 | add t1, \pos, a2 |
| 118 | 228 | v\op\()e8.v v\n1, (\pos) |