Unified · Split
| @@ -902,13 +902,13 @@ void ff_hevc_dsp_init_x86(HEVCDSPContext *c, const int bit_depth) · 901 unmodified lines | ||
| 902 | 902 | c->put_hevc_qpel_uni[8][0][0] = hevc_put_uni_pel_pixels48_8_avx2; |
| 903 | 903 | c->put_hevc_qpel_uni[9][0][0] = hevc_put_uni_pel_pixels64_8_avx2; |
| 904 | 904 | |
| 905 | − c->put_hevc_qpel_bi[7][0][0] = ff_hevc_put_bi_pel_pixels32_8_avx2; | |
| 906 | − c->put_hevc_qpel_bi[8][0][0] = ff_hevc_put_bi_pel_pixels48_8_avx2; | |
| 907 | − c->put_hevc_qpel_bi[9][0][0] = ff_hevc_put_bi_pel_pixels64_8_avx2; | |
| 905 | + c->put_hevc_qpel_bi[7][0][0] = ff_hevc_put_bi_pel_pixels32_8_avx2; | |
| 906 | + c->put_hevc_qpel_bi[8][0][0] = ff_hevc_put_bi_pel_pixels48_8_avx2; | |
| 907 | + c->put_hevc_qpel_bi[9][0][0] = ff_hevc_put_bi_pel_pixels64_8_avx2; | |
| 908 | 908 | |
| 909 | − c->put_hevc_epel_bi[7][0][0] = ff_hevc_put_bi_pel_pixels32_8_avx2; | |
| 910 | − c->put_hevc_epel_bi[8][0][0] = ff_hevc_put_bi_pel_pixels48_8_avx2; | |
| 911 | − c->put_hevc_epel_bi[9][0][0] = ff_hevc_put_bi_pel_pixels64_8_avx2; | |
| 909 | + c->put_hevc_epel_bi[7][0][0] = ff_hevc_put_bi_pel_pixels32_8_avx2; | |
| 910 | + c->put_hevc_epel_bi[8][0][0] = ff_hevc_put_bi_pel_pixels48_8_avx2; | |
| 911 | + c->put_hevc_epel_bi[9][0][0] = ff_hevc_put_bi_pel_pixels64_8_avx2; | |
| 912 | 912 | |
| 913 | 913 | c->put_hevc_epel[7][0][1] = hevc_put_epel_h32_8_avx2; |
| 914 | 914 | c->put_hevc_epel[8][0][1] = hevc_put_epel_h48_8_avx2; |
| @@ -918,9 +918,9 @@ void ff_hevc_dsp_init_x86(HEVCDSPContext *c, const int bit_depth) · 3 unmodified lines | ||
| 918 | 918 | c->put_hevc_epel_uni[8][0][1] = hevc_put_uni_epel_h48_8_avx2; |
| 919 | 919 | c->put_hevc_epel_uni[9][0][1] = hevc_put_uni_epel_h64_8_avx2; |
| 920 | 920 | |
| 921 | − c->put_hevc_epel_bi[7][0][1] = ff_hevc_put_bi_epel_h32_8_avx2; | |
| 922 | − c->put_hevc_epel_bi[8][0][1] = ff_hevc_put_bi_epel_h48_8_avx2; | |
| 923 | − c->put_hevc_epel_bi[9][0][1] = ff_hevc_put_bi_epel_h64_8_avx2; | |
| 921 | + c->put_hevc_epel_bi[7][0][1] = ff_hevc_put_bi_epel_h32_8_avx2; | |
| 922 | + c->put_hevc_epel_bi[8][0][1] = ff_hevc_put_bi_epel_h48_8_avx2; | |
| 923 | + c->put_hevc_epel_bi[9][0][1] = ff_hevc_put_bi_epel_h64_8_avx2; | |
| 924 | 924 | |
| 925 | 925 | c->put_hevc_epel[7][1][0] = hevc_put_epel_v32_8_avx2; |
| 926 | 926 | c->put_hevc_epel[8][1][0] = hevc_put_epel_v48_8_avx2; |
| @@ -930,9 +930,9 @@ void ff_hevc_dsp_init_x86(HEVCDSPContext *c, const int bit_depth) · 3 unmodified lines | ||
| 930 | 930 | c->put_hevc_epel_uni[8][1][0] = hevc_put_uni_epel_v48_8_avx2; |
| 931 | 931 | c->put_hevc_epel_uni[9][1][0] = hevc_put_uni_epel_v64_8_avx2; |
| 932 | 932 | |
| 933 | − c->put_hevc_epel_bi[7][1][0] = ff_hevc_put_bi_epel_v32_8_avx2; | |
| 934 | − c->put_hevc_epel_bi[8][1][0] = ff_hevc_put_bi_epel_v48_8_avx2; | |
| 935 | − c->put_hevc_epel_bi[9][1][0] = ff_hevc_put_bi_epel_v64_8_avx2; | |
| 933 | + c->put_hevc_epel_bi[7][1][0] = ff_hevc_put_bi_epel_v32_8_avx2; | |
| 934 | + c->put_hevc_epel_bi[8][1][0] = ff_hevc_put_bi_epel_v48_8_avx2; | |
| 935 | + c->put_hevc_epel_bi[9][1][0] = ff_hevc_put_bi_epel_v64_8_avx2; | |
| 936 | 936 | |
| 937 | 937 | c->put_hevc_epel[7][1][1] = hevc_put_epel_hv32_8_avx2; |
| 938 | 938 | c->put_hevc_epel[8][1][1] = hevc_put_epel_hv48_8_avx2; |
| @@ -942,9 +942,9 @@ void ff_hevc_dsp_init_x86(HEVCDSPContext *c, const int bit_depth) · 3 unmodified lines | ||
| 942 | 942 | c->put_hevc_epel_uni[8][1][1] = hevc_put_uni_epel_hv48_8_avx2; |
| 943 | 943 | c->put_hevc_epel_uni[9][1][1] = hevc_put_uni_epel_hv64_8_avx2; |
| 944 | 944 | |
| 945 | − c->put_hevc_epel_bi[7][1][1] = ff_hevc_put_bi_epel_hv32_8_avx2; | |
| 946 | − c->put_hevc_epel_bi[8][1][1] = ff_hevc_put_bi_epel_hv48_8_avx2; | |
| 947 | − c->put_hevc_epel_bi[9][1][1] = ff_hevc_put_bi_epel_hv64_8_avx2; | |
| 945 | + c->put_hevc_epel_bi[7][1][1] = ff_hevc_put_bi_epel_hv32_8_avx2; | |
| 946 | + c->put_hevc_epel_bi[8][1][1] = ff_hevc_put_bi_epel_hv48_8_avx2; | |
| 947 | + c->put_hevc_epel_bi[9][1][1] = ff_hevc_put_bi_epel_hv64_8_avx2; | |
| 948 | 948 | |
| 949 | 949 | c->put_hevc_qpel[7][0][1] = hevc_put_qpel_h32_8_avx2; |
| 950 | 950 | c->put_hevc_qpel[8][0][1] = hevc_put_qpel_h48_8_avx2; |
| @@ -962,13 +962,13 @@ void ff_hevc_dsp_init_x86(HEVCDSPContext *c, const int bit_depth) · 11 unmodified lines | ||
| 962 | 962 | c->put_hevc_qpel_uni[8][1][0] = hevc_put_uni_qpel_v48_8_avx2; |
| 963 | 963 | c->put_hevc_qpel_uni[9][1][0] = hevc_put_uni_qpel_v64_8_avx2; |
| 964 | 964 | |
| 965 | − c->put_hevc_qpel_bi[7][0][1] = ff_hevc_put_bi_qpel_h32_8_avx2; | |
| 966 | − c->put_hevc_qpel_bi[8][0][1] = ff_hevc_put_bi_qpel_h48_8_avx2; | |
| 967 | − c->put_hevc_qpel_bi[9][0][1] = ff_hevc_put_bi_qpel_h64_8_avx2; | |
| 965 | + c->put_hevc_qpel_bi[7][0][1] = ff_hevc_put_bi_qpel_h32_8_avx2; | |
| 966 | + c->put_hevc_qpel_bi[8][0][1] = ff_hevc_put_bi_qpel_h48_8_avx2; | |
| 967 | + c->put_hevc_qpel_bi[9][0][1] = ff_hevc_put_bi_qpel_h64_8_avx2; | |
| 968 | 968 | |
| 969 | − c->put_hevc_qpel_bi[7][1][0] = ff_hevc_put_bi_qpel_v32_8_avx2; | |
| 970 | − c->put_hevc_qpel_bi[8][1][0] = ff_hevc_put_bi_qpel_v48_8_avx2; | |
| 971 | − c->put_hevc_qpel_bi[9][1][0] = ff_hevc_put_bi_qpel_v64_8_avx2; | |
| 969 | + c->put_hevc_qpel_bi[7][1][0] = ff_hevc_put_bi_qpel_v32_8_avx2; | |
| 970 | + c->put_hevc_qpel_bi[8][1][0] = ff_hevc_put_bi_qpel_v48_8_avx2; | |
| 971 | + c->put_hevc_qpel_bi[9][1][0] = ff_hevc_put_bi_qpel_v64_8_avx2; | |
| 972 | 972 | #endif /* ARCH_X86_64 */ |
| 973 | 973 | |
| 974 | 974 | SAO_BAND_INIT(8, avx2); |
| @@ -1083,16 +1083,16 @@ void ff_hevc_dsp_init_x86(HEVCDSPContext *c, const int bit_depth) · 108 unmodified lines | ||
| 1083 | 1083 | c->put_hevc_qpel_uni[8][0][0] = hevc_put_uni_pel_pixels96_8_avx2; |
| 1084 | 1084 | c->put_hevc_qpel_uni[9][0][0] = hevc_put_uni_pel_pixels128_8_avx2; |
| 1085 | 1085 | |
| 1086 | − c->put_hevc_epel_bi[5][0][0] = ff_hevc_put_bi_pel_pixels16_10_avx2; | |
| 1087 | − c->put_hevc_epel_bi[6][0][0] = ff_hevc_put_bi_pel_pixels24_10_avx2; | |
| 1088 | − c->put_hevc_epel_bi[7][0][0] = ff_hevc_put_bi_pel_pixels32_10_avx2; | |
| 1089 | − c->put_hevc_epel_bi[8][0][0] = ff_hevc_put_bi_pel_pixels48_10_avx2; | |
| 1090 | − c->put_hevc_epel_bi[9][0][0] = ff_hevc_put_bi_pel_pixels64_10_avx2; | |
| 1091 | − c->put_hevc_qpel_bi[5][0][0] = ff_hevc_put_bi_pel_pixels16_10_avx2; | |
| 1092 | − c->put_hevc_qpel_bi[6][0][0] = ff_hevc_put_bi_pel_pixels24_10_avx2; | |
| 1093 | − c->put_hevc_qpel_bi[7][0][0] = ff_hevc_put_bi_pel_pixels32_10_avx2; | |
| 1094 | − c->put_hevc_qpel_bi[8][0][0] = ff_hevc_put_bi_pel_pixels48_10_avx2; | |
| 1095 | − c->put_hevc_qpel_bi[9][0][0] = ff_hevc_put_bi_pel_pixels64_10_avx2; | |
| 1086 | + c->put_hevc_epel_bi[5][0][0] = ff_hevc_put_bi_pel_pixels16_10_avx2; | |
| 1087 | + c->put_hevc_epel_bi[6][0][0] = ff_hevc_put_bi_pel_pixels24_10_avx2; | |
| 1088 | + c->put_hevc_epel_bi[7][0][0] = ff_hevc_put_bi_pel_pixels32_10_avx2; | |
| 1089 | + c->put_hevc_epel_bi[8][0][0] = ff_hevc_put_bi_pel_pixels48_10_avx2; | |
| 1090 | + c->put_hevc_epel_bi[9][0][0] = ff_hevc_put_bi_pel_pixels64_10_avx2; | |
| 1091 | + c->put_hevc_qpel_bi[5][0][0] = ff_hevc_put_bi_pel_pixels16_10_avx2; | |
| 1092 | + c->put_hevc_qpel_bi[6][0][0] = ff_hevc_put_bi_pel_pixels24_10_avx2; | |
| 1093 | + c->put_hevc_qpel_bi[7][0][0] = ff_hevc_put_bi_pel_pixels32_10_avx2; | |
| 1094 | + c->put_hevc_qpel_bi[8][0][0] = ff_hevc_put_bi_pel_pixels48_10_avx2; | |
| 1095 | + c->put_hevc_qpel_bi[9][0][0] = ff_hevc_put_bi_pel_pixels64_10_avx2; | |
| 1096 | 1096 | |
| 1097 | 1097 | c->put_hevc_epel[5][0][1] = hevc_put_epel_h16_10_avx2; |
| 1098 | 1098 | c->put_hevc_epel[6][0][1] = hevc_put_epel_h24_10_avx2; |
| @@ -1106,11 +1106,11 @@ void ff_hevc_dsp_init_x86(HEVCDSPContext *c, const int bit_depth) · 7 unmodified lines | ||
| 1106 | 1106 | c->put_hevc_epel_uni[8][0][1] = hevc_put_uni_epel_h48_10_avx2; |
| 1107 | 1107 | c->put_hevc_epel_uni[9][0][1] = hevc_put_uni_epel_h64_10_avx2; |
| 1108 | 1108 | |
| 1109 | − c->put_hevc_epel_bi[5][0][1] = ff_hevc_put_bi_epel_h16_10_avx2; | |
| 1110 | − c->put_hevc_epel_bi[6][0][1] = ff_hevc_put_bi_epel_h24_10_avx2; | |
| 1111 | − c->put_hevc_epel_bi[7][0][1] = ff_hevc_put_bi_epel_h32_10_avx2; | |
| 1112 | − c->put_hevc_epel_bi[8][0][1] = ff_hevc_put_bi_epel_h48_10_avx2; | |
| 1113 | − c->put_hevc_epel_bi[9][0][1] = ff_hevc_put_bi_epel_h64_10_avx2; | |
| 1109 | + c->put_hevc_epel_bi[5][0][1] = ff_hevc_put_bi_epel_h16_10_avx2; | |
| 1110 | + c->put_hevc_epel_bi[6][0][1] = ff_hevc_put_bi_epel_h24_10_avx2; | |
| 1111 | + c->put_hevc_epel_bi[7][0][1] = ff_hevc_put_bi_epel_h32_10_avx2; | |
| 1112 | + c->put_hevc_epel_bi[8][0][1] = ff_hevc_put_bi_epel_h48_10_avx2; | |
| 1113 | + c->put_hevc_epel_bi[9][0][1] = ff_hevc_put_bi_epel_h64_10_avx2; | |
| 1114 | 1114 | |
| 1115 | 1115 | c->put_hevc_epel[5][1][0] = hevc_put_epel_v16_10_avx2; |
| 1116 | 1116 | c->put_hevc_epel[6][1][0] = hevc_put_epel_v24_10_avx2; |
| @@ -1124,11 +1124,11 @@ void ff_hevc_dsp_init_x86(HEVCDSPContext *c, const int bit_depth) · 7 unmodified lines | ||
| 1124 | 1124 | c->put_hevc_epel_uni[8][1][0] = hevc_put_uni_epel_v48_10_avx2; |
| 1125 | 1125 | c->put_hevc_epel_uni[9][1][0] = hevc_put_uni_epel_v64_10_avx2; |
| 1126 | 1126 | |
| 1127 | − c->put_hevc_epel_bi[5][1][0] = ff_hevc_put_bi_epel_v16_10_avx2; | |
| 1128 | − c->put_hevc_epel_bi[6][1][0] = ff_hevc_put_bi_epel_v24_10_avx2; | |
| 1129 | − c->put_hevc_epel_bi[7][1][0] = ff_hevc_put_bi_epel_v32_10_avx2; | |
| 1130 | − c->put_hevc_epel_bi[8][1][0] = ff_hevc_put_bi_epel_v48_10_avx2; | |
| 1131 | − c->put_hevc_epel_bi[9][1][0] = ff_hevc_put_bi_epel_v64_10_avx2; | |
| 1127 | + c->put_hevc_epel_bi[5][1][0] = ff_hevc_put_bi_epel_v16_10_avx2; | |
| 1128 | + c->put_hevc_epel_bi[6][1][0] = ff_hevc_put_bi_epel_v24_10_avx2; | |
| 1129 | + c->put_hevc_epel_bi[7][1][0] = ff_hevc_put_bi_epel_v32_10_avx2; | |
| 1130 | + c->put_hevc_epel_bi[8][1][0] = ff_hevc_put_bi_epel_v48_10_avx2; | |
| 1131 | + c->put_hevc_epel_bi[9][1][0] = ff_hevc_put_bi_epel_v64_10_avx2; | |
| 1132 | 1132 | |
| 1133 | 1133 | c->put_hevc_epel[5][1][1] = hevc_put_epel_hv16_10_avx2; |
| 1134 | 1134 | c->put_hevc_epel[6][1][1] = hevc_put_epel_hv24_10_avx2; |
| @@ -1142,11 +1142,11 @@ void ff_hevc_dsp_init_x86(HEVCDSPContext *c, const int bit_depth) · 7 unmodified lines | ||
| 1142 | 1142 | c->put_hevc_epel_uni[8][1][1] = hevc_put_uni_epel_hv48_10_avx2; |
| 1143 | 1143 | c->put_hevc_epel_uni[9][1][1] = hevc_put_uni_epel_hv64_10_avx2; |
| 1144 | 1144 | |
| 1145 | − c->put_hevc_epel_bi[5][1][1] = ff_hevc_put_bi_epel_hv16_10_avx2; | |
| 1146 | − c->put_hevc_epel_bi[6][1][1] = ff_hevc_put_bi_epel_hv24_10_avx2; | |
| 1147 | − c->put_hevc_epel_bi[7][1][1] = ff_hevc_put_bi_epel_hv32_10_avx2; | |
| 1148 | − c->put_hevc_epel_bi[8][1][1] = ff_hevc_put_bi_epel_hv48_10_avx2; | |
| 1149 | − c->put_hevc_epel_bi[9][1][1] = ff_hevc_put_bi_epel_hv64_10_avx2; | |
| 1145 | + c->put_hevc_epel_bi[5][1][1] = ff_hevc_put_bi_epel_hv16_10_avx2; | |
| 1146 | + c->put_hevc_epel_bi[6][1][1] = ff_hevc_put_bi_epel_hv24_10_avx2; | |
| 1147 | + c->put_hevc_epel_bi[7][1][1] = ff_hevc_put_bi_epel_hv32_10_avx2; | |
| 1148 | + c->put_hevc_epel_bi[8][1][1] = ff_hevc_put_bi_epel_hv48_10_avx2; | |
| 1149 | + c->put_hevc_epel_bi[9][1][1] = ff_hevc_put_bi_epel_hv64_10_avx2; | |
| 1150 | 1150 | |
| 1151 | 1151 | c->put_hevc_qpel[5][0][1] = hevc_put_qpel_h16_10_avx2; |
| 1152 | 1152 | c->put_hevc_qpel[6][0][1] = hevc_put_qpel_h24_10_avx2; |
| @@ -1160,11 +1160,11 @@ void ff_hevc_dsp_init_x86(HEVCDSPContext *c, const int bit_depth) · 7 unmodified lines | ||
| 1160 | 1160 | c->put_hevc_qpel_uni[8][0][1] = hevc_put_uni_qpel_h48_10_avx2; |
| 1161 | 1161 | c->put_hevc_qpel_uni[9][0][1] = hevc_put_uni_qpel_h64_10_avx2; |
| 1162 | 1162 | |
| 1163 | − c->put_hevc_qpel_bi[5][0][1] = ff_hevc_put_bi_qpel_h16_10_avx2; | |
| 1164 | − c->put_hevc_qpel_bi[6][0][1] = ff_hevc_put_bi_qpel_h24_10_avx2; | |
| 1165 | − c->put_hevc_qpel_bi[7][0][1] = ff_hevc_put_bi_qpel_h32_10_avx2; | |
| 1166 | − c->put_hevc_qpel_bi[8][0][1] = ff_hevc_put_bi_qpel_h48_10_avx2; | |
| 1167 | − c->put_hevc_qpel_bi[9][0][1] = ff_hevc_put_bi_qpel_h64_10_avx2; | |
| 1163 | + c->put_hevc_qpel_bi[5][0][1] = ff_hevc_put_bi_qpel_h16_10_avx2; | |
| 1164 | + c->put_hevc_qpel_bi[6][0][1] = ff_hevc_put_bi_qpel_h24_10_avx2; | |
| 1165 | + c->put_hevc_qpel_bi[7][0][1] = ff_hevc_put_bi_qpel_h32_10_avx2; | |
| 1166 | + c->put_hevc_qpel_bi[8][0][1] = ff_hevc_put_bi_qpel_h48_10_avx2; | |
| 1167 | + c->put_hevc_qpel_bi[9][0][1] = ff_hevc_put_bi_qpel_h64_10_avx2; | |
| 1168 | 1168 | |
| 1169 | 1169 | c->put_hevc_qpel[5][1][0] = hevc_put_qpel_v16_10_avx2; |
| 1170 | 1170 | c->put_hevc_qpel[6][1][0] = hevc_put_qpel_v24_10_avx2; |
| @@ -1178,11 +1178,11 @@ void ff_hevc_dsp_init_x86(HEVCDSPContext *c, const int bit_depth) · 7 unmodified lines | ||
| 1178 | 1178 | c->put_hevc_qpel_uni[8][1][0] = hevc_put_uni_qpel_v48_10_avx2; |
| 1179 | 1179 | c->put_hevc_qpel_uni[9][1][0] = hevc_put_uni_qpel_v64_10_avx2; |
| 1180 | 1180 | |
| 1181 | − c->put_hevc_qpel_bi[5][1][0] = ff_hevc_put_bi_qpel_v16_10_avx2; | |
| 1182 | − c->put_hevc_qpel_bi[6][1][0] = ff_hevc_put_bi_qpel_v24_10_avx2; | |
| 1183 | − c->put_hevc_qpel_bi[7][1][0] = ff_hevc_put_bi_qpel_v32_10_avx2; | |
| 1184 | − c->put_hevc_qpel_bi[8][1][0] = ff_hevc_put_bi_qpel_v48_10_avx2; | |
| 1185 | − c->put_hevc_qpel_bi[9][1][0] = ff_hevc_put_bi_qpel_v64_10_avx2; | |
| 1181 | + c->put_hevc_qpel_bi[5][1][0] = ff_hevc_put_bi_qpel_v16_10_avx2; | |
| 1182 | + c->put_hevc_qpel_bi[6][1][0] = ff_hevc_put_bi_qpel_v24_10_avx2; | |
| 1183 | + c->put_hevc_qpel_bi[7][1][0] = ff_hevc_put_bi_qpel_v32_10_avx2; | |
| 1184 | + c->put_hevc_qpel_bi[8][1][0] = ff_hevc_put_bi_qpel_v48_10_avx2; | |
| 1185 | + c->put_hevc_qpel_bi[9][1][0] = ff_hevc_put_bi_qpel_v64_10_avx2; | |
| 1186 | 1186 | |
| 1187 | 1187 | c->put_hevc_qpel[5][1][1] = hevc_put_qpel_hv16_10_avx2; |
| 1188 | 1188 | c->put_hevc_qpel[6][1][1] = hevc_put_qpel_hv24_10_avx2; |
| @@ -1196,11 +1196,11 @@ void ff_hevc_dsp_init_x86(HEVCDSPContext *c, const int bit_depth) · 7 unmodified lines | ||
| 1196 | 1196 | c->put_hevc_qpel_uni[8][1][1] = hevc_put_uni_qpel_hv48_10_avx2; |
| 1197 | 1197 | c->put_hevc_qpel_uni[9][1][1] = hevc_put_uni_qpel_hv64_10_avx2; |
| 1198 | 1198 | |
| 1199 | − c->put_hevc_qpel_bi[5][1][1] = ff_hevc_put_bi_qpel_hv16_10_avx2; | |
| 1200 | − c->put_hevc_qpel_bi[6][1][1] = ff_hevc_put_bi_qpel_hv24_10_avx2; | |
| 1201 | − c->put_hevc_qpel_bi[7][1][1] = ff_hevc_put_bi_qpel_hv32_10_avx2; | |
| 1202 | − c->put_hevc_qpel_bi[8][1][1] = ff_hevc_put_bi_qpel_hv48_10_avx2; | |
| 1203 | − c->put_hevc_qpel_bi[9][1][1] = ff_hevc_put_bi_qpel_hv64_10_avx2; | |
| 1199 | + c->put_hevc_qpel_bi[5][1][1] = ff_hevc_put_bi_qpel_hv16_10_avx2; | |
| 1200 | + c->put_hevc_qpel_bi[6][1][1] = ff_hevc_put_bi_qpel_hv24_10_avx2; | |
| 1201 | + c->put_hevc_qpel_bi[7][1][1] = ff_hevc_put_bi_qpel_hv32_10_avx2; | |
| 1202 | + c->put_hevc_qpel_bi[8][1][1] = ff_hevc_put_bi_qpel_hv48_10_avx2; | |
| 1203 | + c->put_hevc_qpel_bi[9][1][1] = ff_hevc_put_bi_qpel_hv64_10_avx2; | |
| 1204 | 1204 | #endif /* ARCH_X86_64 */ |
| 1205 | 1205 | |
| 1206 | 1206 | SAO_BAND_INIT(10, avx2); |