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lavu/riscv: remove bespoke SH{1,2,3}ADD assembler

configure checks that the assembler supports the B extension (or rather its constituents) anyway. These macros were dodging sanity checks for unsupported instructions and nothing else.

Rémi Denis-Courmont committed 2 years ago

Commit 529d4231 parent 5f101731 file · +0 −19Browse files

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libavutil/riscv/asm.S+0−19
@@ -83,25 +83,6 @@ · 82 unmodified lines
83 .endm83 .endm
84 .endm84 .endm
85 85
86#if !defined (__riscv_zba)
87 /* SH{1,2,3}ADD definitions for pre-Zba assemblers */
88 .macro shnadd n, rd, rs1, rs2
89 .insn r OP, 2 * \n, 16, \rd, \rs1, \rs2
90 .endm
91
92 .macro sh1add rd, rs1, rs2
93 shnadd 1, \rd, \rs1, \rs2
94 .endm
95
96 .macro sh2add rd, rs1, rs2
97 shnadd 2, \rd, \rs1, \rs2
98 .endm
99
100 .macro sh3add rd, rs1, rs2
101 shnadd 3, \rd, \rs1, \rs2
102 .endm
103#endif
104
105#if defined (__riscv_v_elen)86#if defined (__riscv_v_elen)
106# define RV_V_ELEN __riscv_v_elen87# define RV_V_ELEN __riscv_v_elen
107#else88#else

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