Broken in afa471d0efed1df5dca6eeeb2fcdd211ae4cad4e. It just happened to work before due to x86inc.asm previously performing XMM spills in INIT_MMX mode which was more of a bug than an intentional feature.
Unified · Split
| @@ -716,11 +716,9 @@ RET · 715 unmodified lines | |||
| 716 | %endif | 716 | %endif |
| 717 | %endmacro | 717 | %endmacro |
| 718 | 718 | ||
| 719 | %macro IDCT_DC_DEQUANT 1 | 719 | INIT_XMM sse2 |
| 720 | cglobal h264_luma_dc_dequant_idct, 3, 4, %1 | 720 | cglobal h264_luma_dc_dequant_idct, 3, 4, 7 |
| 721 | ; manually spill XMM registers for Win64 because | 721 | INIT_MMX cpuname |
| 722 | ; the code here is initialized with INIT_MMX | ||
| 723 | WIN64_SPILL_XMM %1 | ||
| 724 | movq m3, [r1+24] | 722 | movq m3, [r1+24] |
| 725 | movq m2, [r1+16] | 723 | movq m2, [r1+16] |
| 726 | movq m1, [r1+ 8] | 724 | movq m1, [r1+ 8] |
| @@ -757,10 +755,6 @@ cglobal h264_luma_dc_dequant_idct, 3, 4, %1 · 30 unmodified lines | |||
| 757 | movd xmm6, t1d | 755 | movd xmm6, t1d |
| 758 | DEQUANT_STORE xmm6 | 756 | DEQUANT_STORE xmm6 |
| 759 | RET | 757 | RET |
| 760 | %endmacro | ||
| 761 | |||
| 762 | INIT_MMX sse2 | ||
| 763 | IDCT_DC_DEQUANT 7 | ||
| 764 | 758 | ||
| 765 | %ifdef __NASM_VER__ | 759 | %ifdef __NASM_VER__ |
| 766 | %if __NASM_MAJOR__ >= 2 && __NASM_MINOR__ >= 4 | 760 | %if __NASM_MAJOR__ >= 2 && __NASM_MINOR__ >= 4 |