This is not great as transposition is poorly supported, but it works: vp8_luma_dc_wht_c: 2.5 vp8_luma_dc_wht_rvv_i32: 1.7
Unified · Split
| @@ -26,6 +26,7 @@ · 25 unmodified lines | |||
| 26 | #include "libavcodec/vp8dsp.h" | 26 | #include "libavcodec/vp8dsp.h" |
| 27 | #include "vp8dsp.h" | 27 | #include "vp8dsp.h" |
| 28 | 28 | ||
| 29 | void ff_vp8_luma_dc_wht_rvv(int16_t block[4][4][16], int16_t dc[16]); | ||
| 29 | void ff_vp8_idct_dc_add_rvv(uint8_t *dst, int16_t block[16], ptrdiff_t stride); | 30 | void ff_vp8_idct_dc_add_rvv(uint8_t *dst, int16_t block[16], ptrdiff_t stride); |
| 30 | void ff_vp8_idct_dc_add4y_rvv(uint8_t *dst, int16_t block[4][16], ptrdiff_t stride); | 31 | void ff_vp8_idct_dc_add4y_rvv(uint8_t *dst, int16_t block[4][16], ptrdiff_t stride); |
| 31 | void ff_vp8_idct_dc_add4uv_rvv(uint8_t *dst, int16_t block[4][16], ptrdiff_t stride); | 32 | void ff_vp8_idct_dc_add4uv_rvv(uint8_t *dst, int16_t block[4][16], ptrdiff_t stride); |
| @@ -124,6 +125,10 @@ av_cold void ff_vp8dsp_init_riscv(VP8DSPContext *c) · 92 unmodified lines | |||
| 124 | int flags = av_get_cpu_flags(); | 125 | int flags = av_get_cpu_flags(); |
| 125 | 126 | ||
| 126 | if (flags & AV_CPU_FLAG_RVV_I32 && ff_rv_vlen_least(128)) { | 127 | if (flags & AV_CPU_FLAG_RVV_I32 && ff_rv_vlen_least(128)) { |
| 128 | #if __riscv_xlen >= 64 | ||
| 129 | if (flags & AV_CPU_FLAG_RVV_I64) | ||
| 130 | c->vp8_luma_dc_wht = ff_vp8_luma_dc_wht_rvv; | ||
| 131 | #endif | ||
| 127 | c->vp8_idct_dc_add = ff_vp8_idct_dc_add_rvv; | 132 | c->vp8_idct_dc_add = ff_vp8_idct_dc_add_rvv; |
| 128 | c->vp8_idct_dc_add4y = ff_vp8_idct_dc_add4y_rvv; | 133 | c->vp8_idct_dc_add4y = ff_vp8_idct_dc_add4y_rvv; |
| 129 | if (flags & AV_CPU_FLAG_RVB_ADDR) { | 134 | if (flags & AV_CPU_FLAG_RVB_ADDR) { |
| @@ -1,5 +1,6 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Copyright (c) 2024 Institue of Software Chinese Academy of Sciences (ISCAS). | 2 | * Copyright (c) 2024 Institue of Software Chinese Academy of Sciences (ISCAS). |
| 3 | * Copyright © 2024 Rémi Denis-Courmont. | ||
| 3 | * | 4 | * |
| 4 | * This file is part of FFmpeg. | 5 | * This file is part of FFmpeg. |
| 5 | * | 6 | * |
| @@ -42,6 +43,61 @@ · 36 unmodified lines | |||
| 42 | .endif | 43 | .endif |
| 43 | .endm | 44 | .endm |
| 44 | 45 | ||
| 46 | #if __riscv_xlen >= 64 | ||
| 47 | func ff_vp8_luma_dc_wht_rvv, zve64x | ||
| 48 | vsetivli zero, 1, e64, m1, ta, ma | ||
| 49 | vlseg4e64.v v4, (a1) | ||
| 50 | vsetivli zero, 4, e16, mf2, ta, ma | ||
| 51 | vwadd.vv v1, v5, v6 | ||
| 52 | addi t1, sp, -48 | ||
| 53 | vwadd.vv v0, v4, v7 | ||
| 54 | addi t2, sp, -32 | ||
| 55 | vwsub.vv v2, v5, v6 | ||
| 56 | addi t3, sp, -16 | ||
| 57 | vwsub.vv v3, v4, v7 | ||
| 58 | addi sp, sp, -64 | ||
| 59 | vsetvli zero, zero, e32, m1, ta, ma | ||
| 60 | vadd.vv v4, v0, v1 | ||
| 61 | vadd.vv v5, v3, v2 | ||
| 62 | vse32.v v4, (sp) | ||
| 63 | vsub.vv v6, v0, v1 | ||
| 64 | vse32.v v5, (t1) | ||
| 65 | vsub.vv v7, v3, v2 | ||
| 66 | vse32.v v6, (t2) | ||
| 67 | vse32.v v7, (t3) | ||
| 68 | vlseg4e32.v v4, (sp) | ||
| 69 | vadd.vv v0, v4, v7 | ||
| 70 | sd zero, (a1) | ||
| 71 | vadd.vv v1, v5, v6 | ||
| 72 | sd zero, 8(a1) | ||
| 73 | vsub.vv v2, v5, v6 | ||
| 74 | sd zero, 16(a1) | ||
| 75 | vsub.vv v3, v4, v7 | ||
| 76 | sd zero, 24(a1) | ||
| 77 | vadd.vi v0, v0, 3 # rounding mode not supported, do it manually | ||
| 78 | li t0, 4 * 16 * 2 | ||
| 79 | vadd.vi v3, v3, 3 | ||
| 80 | addi t1, a0, 16 * 2 | ||
| 81 | vadd.vv v4, v0, v1 | ||
| 82 | addi t2, a0, 16 * 2 * 2 | ||
| 83 | vadd.vv v5, v3, v2 | ||
| 84 | addi t3, a0, 16 * 2 * 3 | ||
| 85 | vsub.vv v6, v0, v1 | ||
| 86 | vsub.vv v7, v3, v2 | ||
| 87 | vsetvli zero, zero, e16, mf2, ta, ma | ||
| 88 | vnsra.wi v0, v4, 3 | ||
| 89 | addi sp, sp, 64 | ||
| 90 | vnsra.wi v1, v5, 3 | ||
| 91 | vsse16.v v0, (a0), t0 | ||
| 92 | vnsra.wi v2, v6, 3 | ||
| 93 | vsse16.v v1, (t1), t0 | ||
| 94 | vnsra.wi v3, v7, 3 | ||
| 95 | vsse16.v v2, (t2), t0 | ||
| 96 | vsse16.v v3, (t3), t0 | ||
| 97 | ret | ||
| 98 | endfunc | ||
| 99 | #endif | ||
| 100 | |||
| 45 | .macro vp8_idct_dc_add | 101 | .macro vp8_idct_dc_add |
| 46 | vlse32.v v0, (a0), a2 | 102 | vlse32.v v0, (a0), a2 |
| 47 | lh a5, 0(a1) | 103 | lh a5, 0(a1) |